1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 10 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 15 16 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target teams distribute private(t_var, vec, s_arr, var) 57 for (int i = 0; i < 2; ++i) { 58 vec[i] = t_var; 59 s_arr[i] = var; 60 } 61 return T(); 62 } 63 64 S<float> test; 65 int t_var = 333; 66 int vec[] = {1, 2}; 67 S<float> s_arr[] = {1, 2}; 68 S<float> var(3); 69 70 int main() { 71 static int sivar; 72 #ifdef LAMBDA 73 [&]() { 74 #pragma omp target teams distribute private(g, g1, sivar) 75 for (int i = 0; i < 2; ++i) { 76 77 // Skip global, bound tid and loop vars 78 g = 1; 79 g1 = 1; 80 sivar = 2; 81 [&]() { 82 g = 2; 83 g1 = 2; 84 sivar = 4; 85 86 }(); 87 } 88 }(); 89 return 0; 90 #else 91 #pragma omp target teams distribute private(t_var, vec, s_arr, var, sivar) 92 for (int i = 0; i < 2; ++i) { 93 vec[i] = t_var; 94 s_arr[i] = var; 95 sivar += i; 96 } 97 return tmain<int>(); 98 #endif 99 } 100 101 102 103 // Skip global, bound tid and loop vars 104 105 // private(s_arr) 106 107 // private(var) 108 109 110 111 112 113 // Skip global, bound tid and loop vars 114 115 // private(s_arr) 116 117 118 // private(var) 119 120 121 #endif 122 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 123 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 124 // CHECK1-NEXT: entry: 125 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 126 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 127 // CHECK1-NEXT: ret void 128 // 129 // 130 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 131 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 132 // CHECK1-NEXT: entry: 133 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 134 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 135 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 136 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 137 // CHECK1-NEXT: ret void 138 // 139 // 140 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 141 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 142 // CHECK1-NEXT: entry: 143 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 144 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 145 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 146 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 147 // CHECK1-NEXT: ret void 148 // 149 // 150 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 151 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 152 // CHECK1-NEXT: entry: 153 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 154 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 155 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 156 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 157 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 158 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 159 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4 160 // CHECK1-NEXT: ret void 161 // 162 // 163 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 164 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 165 // CHECK1-NEXT: entry: 166 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 167 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 168 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 169 // CHECK1-NEXT: ret void 170 // 171 // 172 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 173 // CHECK1-SAME: () #[[ATTR0]] { 174 // CHECK1-NEXT: entry: 175 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 176 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 177 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 178 // CHECK1-NEXT: ret void 179 // 180 // 181 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 182 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 183 // CHECK1-NEXT: entry: 184 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 185 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 186 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 187 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 188 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 189 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 190 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 191 // CHECK1-NEXT: ret void 192 // 193 // 194 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 195 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 196 // CHECK1-NEXT: entry: 197 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 198 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 199 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 200 // CHECK1: arraydestroy.body: 201 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 202 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 203 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 204 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 205 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 206 // CHECK1: arraydestroy.done1: 207 // CHECK1-NEXT: ret void 208 // 209 // 210 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 211 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 212 // CHECK1-NEXT: entry: 213 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 214 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 215 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 216 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 217 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 218 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 219 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 220 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 221 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 222 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 223 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 224 // CHECK1-NEXT: ret void 225 // 226 // 227 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 228 // CHECK1-SAME: () #[[ATTR0]] { 229 // CHECK1-NEXT: entry: 230 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 231 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 232 // CHECK1-NEXT: ret void 233 // 234 // 235 // CHECK1-LABEL: define {{[^@]+}}@main 236 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 237 // CHECK1-NEXT: entry: 238 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 239 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 240 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 241 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 242 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 243 // CHECK1-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 244 // CHECK1-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 245 // CHECK1: omp_offload.failed: 246 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]] 247 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 248 // CHECK1: omp_offload.cont: 249 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 250 // CHECK1-NEXT: ret i32 [[CALL]] 251 // 252 // 253 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 254 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 255 // CHECK1-NEXT: entry: 256 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 257 // CHECK1-NEXT: ret void 258 // 259 // 260 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 261 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 262 // CHECK1-NEXT: entry: 263 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 264 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 265 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 266 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 267 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 268 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 269 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 270 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 271 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 272 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 273 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 274 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 275 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 276 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 277 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 278 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 279 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 280 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 281 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 282 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 283 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 284 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 285 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 286 // CHECK1: arrayctor.loop: 287 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 288 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 289 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 290 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 291 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 292 // CHECK1: arrayctor.cont: 293 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 294 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 295 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 296 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 297 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 298 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 299 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 300 // CHECK1: cond.true: 301 // CHECK1-NEXT: br label [[COND_END:%.*]] 302 // CHECK1: cond.false: 303 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 304 // CHECK1-NEXT: br label [[COND_END]] 305 // CHECK1: cond.end: 306 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 307 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 308 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 309 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 310 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 311 // CHECK1: omp.inner.for.cond: 312 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 313 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 314 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 315 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 316 // CHECK1: omp.inner.for.cond.cleanup: 317 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 318 // CHECK1: omp.inner.for.body: 319 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 320 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 321 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 322 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 323 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 324 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 325 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 326 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 327 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 328 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 329 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 330 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] 331 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* 332 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8* 333 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false) 334 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 335 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4 336 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 337 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR]], align 4 338 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 339 // CHECK1: omp.body.continue: 340 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 341 // CHECK1: omp.inner.for.inc: 342 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 343 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 344 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 345 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 346 // CHECK1: omp.inner.for.end: 347 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 348 // CHECK1: omp.loop.exit: 349 // CHECK1-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 350 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 351 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) 352 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 353 // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 354 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 355 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 356 // CHECK1: arraydestroy.body: 357 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 358 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 359 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 360 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 361 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 362 // CHECK1: arraydestroy.done7: 363 // CHECK1-NEXT: ret void 364 // 365 // 366 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 367 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat { 368 // CHECK1-NEXT: entry: 369 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 370 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 371 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 372 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 373 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 374 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 375 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 376 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 377 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 378 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 379 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 380 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 381 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 382 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 383 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 384 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 385 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 386 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 387 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 388 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 389 // CHECK1-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 390 // CHECK1-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 391 // CHECK1: omp_offload.failed: 392 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 393 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 394 // CHECK1: omp_offload.cont: 395 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 396 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 397 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 398 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 399 // CHECK1: arraydestroy.body: 400 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 401 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 402 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 403 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 404 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 405 // CHECK1: arraydestroy.done2: 406 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 407 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 408 // CHECK1-NEXT: ret i32 [[TMP4]] 409 // 410 // 411 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 412 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 413 // CHECK1-NEXT: entry: 414 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 415 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 416 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 417 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 418 // CHECK1-NEXT: ret void 419 // 420 // 421 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 422 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 423 // CHECK1-NEXT: entry: 424 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 425 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 426 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 427 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 428 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 429 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 430 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 431 // CHECK1-NEXT: ret void 432 // 433 // 434 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 435 // CHECK1-SAME: () #[[ATTR4]] { 436 // CHECK1-NEXT: entry: 437 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) 438 // CHECK1-NEXT: ret void 439 // 440 // 441 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 442 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 443 // CHECK1-NEXT: entry: 444 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 445 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 446 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 447 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 448 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 449 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 450 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 451 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 452 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 453 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 454 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 455 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 456 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 457 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 458 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 459 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 460 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 461 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 462 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 463 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 464 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 465 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 466 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 467 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 468 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 469 // CHECK1: arrayctor.loop: 470 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 471 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 472 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 473 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 474 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 475 // CHECK1: arrayctor.cont: 476 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 477 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 478 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 479 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 480 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 481 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 482 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 483 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 484 // CHECK1: cond.true: 485 // CHECK1-NEXT: br label [[COND_END:%.*]] 486 // CHECK1: cond.false: 487 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 488 // CHECK1-NEXT: br label [[COND_END]] 489 // CHECK1: cond.end: 490 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 491 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 492 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 493 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 494 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 495 // CHECK1: omp.inner.for.cond: 496 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 497 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 498 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 499 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 500 // CHECK1: omp.inner.for.cond.cleanup: 501 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 502 // CHECK1: omp.inner.for.body: 503 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 504 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 505 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 506 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 507 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 508 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 509 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 510 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 511 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 512 // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 513 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 514 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 515 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] 516 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* 517 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 518 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) 519 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 520 // CHECK1: omp.body.continue: 521 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 522 // CHECK1: omp.inner.for.inc: 523 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 524 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 525 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 526 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 527 // CHECK1: omp.inner.for.end: 528 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 529 // CHECK1: omp.loop.exit: 530 // CHECK1-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 531 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 532 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) 533 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 534 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 535 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 536 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 537 // CHECK1: arraydestroy.body: 538 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 539 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 540 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 541 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 542 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 543 // CHECK1: arraydestroy.done8: 544 // CHECK1-NEXT: ret void 545 // 546 // 547 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 548 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 549 // CHECK1-NEXT: entry: 550 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 551 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 552 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 553 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 554 // CHECK1-NEXT: ret void 555 // 556 // 557 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 558 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 559 // CHECK1-NEXT: entry: 560 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 561 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 562 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 563 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 564 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 565 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 566 // CHECK1-NEXT: ret void 567 // 568 // 569 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 570 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 571 // CHECK1-NEXT: entry: 572 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 573 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 574 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 575 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 576 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 577 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 578 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 579 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 580 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 581 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 582 // CHECK1-NEXT: ret void 583 // 584 // 585 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 586 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 587 // CHECK1-NEXT: entry: 588 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 589 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 590 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 591 // CHECK1-NEXT: ret void 592 // 593 // 594 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp 595 // CHECK1-SAME: () #[[ATTR0]] { 596 // CHECK1-NEXT: entry: 597 // CHECK1-NEXT: call void @__cxx_global_var_init() 598 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 599 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 600 // CHECK1-NEXT: ret void 601 // 602 // 603 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 604 // CHECK1-SAME: () #[[ATTR0]] { 605 // CHECK1-NEXT: entry: 606 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 607 // CHECK1-NEXT: ret void 608 // 609 // 610 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 611 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 612 // CHECK3-NEXT: entry: 613 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 614 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 615 // CHECK3-NEXT: ret void 616 // 617 // 618 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 619 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 620 // CHECK3-NEXT: entry: 621 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 622 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 623 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 624 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 625 // CHECK3-NEXT: ret void 626 // 627 // 628 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 629 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 630 // CHECK3-NEXT: entry: 631 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 632 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 633 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 634 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 635 // CHECK3-NEXT: ret void 636 // 637 // 638 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 639 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 640 // CHECK3-NEXT: entry: 641 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 642 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 643 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 644 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 645 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 646 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 647 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4 648 // CHECK3-NEXT: ret void 649 // 650 // 651 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 652 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 653 // CHECK3-NEXT: entry: 654 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 655 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 656 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 657 // CHECK3-NEXT: ret void 658 // 659 // 660 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 661 // CHECK3-SAME: () #[[ATTR0]] { 662 // CHECK3-NEXT: entry: 663 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) 664 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) 665 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 666 // CHECK3-NEXT: ret void 667 // 668 // 669 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 670 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 671 // CHECK3-NEXT: entry: 672 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 673 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 674 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 675 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 676 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 677 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 678 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 679 // CHECK3-NEXT: ret void 680 // 681 // 682 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 683 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 684 // CHECK3-NEXT: entry: 685 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 686 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 687 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 688 // CHECK3: arraydestroy.body: 689 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 690 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 691 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 692 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 693 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 694 // CHECK3: arraydestroy.done1: 695 // CHECK3-NEXT: ret void 696 // 697 // 698 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 699 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 700 // CHECK3-NEXT: entry: 701 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 702 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 703 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 704 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 705 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 706 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 707 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 708 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 709 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 710 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 711 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 712 // CHECK3-NEXT: ret void 713 // 714 // 715 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 716 // CHECK3-SAME: () #[[ATTR0]] { 717 // CHECK3-NEXT: entry: 718 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 719 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 720 // CHECK3-NEXT: ret void 721 // 722 // 723 // CHECK3-LABEL: define {{[^@]+}}@main 724 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 725 // CHECK3-NEXT: entry: 726 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 727 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 728 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 729 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 730 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 731 // CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 732 // CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 733 // CHECK3: omp_offload.failed: 734 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]] 735 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 736 // CHECK3: omp_offload.cont: 737 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 738 // CHECK3-NEXT: ret i32 [[CALL]] 739 // 740 // 741 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 742 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 743 // CHECK3-NEXT: entry: 744 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 745 // CHECK3-NEXT: ret void 746 // 747 // 748 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 749 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 750 // CHECK3-NEXT: entry: 751 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 752 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 753 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 754 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 755 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 756 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 757 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 758 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 759 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 760 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 761 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 762 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 763 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 764 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 765 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 766 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 767 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 768 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 769 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 770 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 771 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 772 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 773 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 774 // CHECK3: arrayctor.loop: 775 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 776 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 777 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 778 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 779 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 780 // CHECK3: arrayctor.cont: 781 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 782 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 783 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 784 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 785 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 786 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 787 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 788 // CHECK3: cond.true: 789 // CHECK3-NEXT: br label [[COND_END:%.*]] 790 // CHECK3: cond.false: 791 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 792 // CHECK3-NEXT: br label [[COND_END]] 793 // CHECK3: cond.end: 794 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 795 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 796 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 797 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 798 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 799 // CHECK3: omp.inner.for.cond: 800 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 801 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 802 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 803 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 804 // CHECK3: omp.inner.for.cond.cleanup: 805 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 806 // CHECK3: omp.inner.for.body: 807 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 808 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 809 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 810 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 811 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 812 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 813 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] 814 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 815 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 816 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP10]] 817 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 818 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8* 819 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false) 820 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 821 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4 822 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 823 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 824 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 825 // CHECK3: omp.body.continue: 826 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 827 // CHECK3: omp.inner.for.inc: 828 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 829 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 830 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 831 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 832 // CHECK3: omp.inner.for.end: 833 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 834 // CHECK3: omp.loop.exit: 835 // CHECK3-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 836 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 837 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) 838 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 839 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 840 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 841 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 842 // CHECK3: arraydestroy.body: 843 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 844 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 845 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 846 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 847 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 848 // CHECK3: arraydestroy.done6: 849 // CHECK3-NEXT: ret void 850 // 851 // 852 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 853 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat { 854 // CHECK3-NEXT: entry: 855 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 856 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 857 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 858 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 859 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 860 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 861 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 862 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 863 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 864 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 865 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 866 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 867 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 868 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) 869 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 870 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 871 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 872 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 873 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 874 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 875 // CHECK3-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 876 // CHECK3-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 877 // CHECK3: omp_offload.failed: 878 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 879 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 880 // CHECK3: omp_offload.cont: 881 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 882 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 883 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 884 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 885 // CHECK3: arraydestroy.body: 886 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 887 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 888 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 889 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 890 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 891 // CHECK3: arraydestroy.done2: 892 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 893 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 894 // CHECK3-NEXT: ret i32 [[TMP4]] 895 // 896 // 897 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 898 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 899 // CHECK3-NEXT: entry: 900 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 901 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 902 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 903 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 904 // CHECK3-NEXT: ret void 905 // 906 // 907 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 908 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 909 // CHECK3-NEXT: entry: 910 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 911 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 912 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 913 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 914 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 915 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 916 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 917 // CHECK3-NEXT: ret void 918 // 919 // 920 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 921 // CHECK3-SAME: () #[[ATTR4]] { 922 // CHECK3-NEXT: entry: 923 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) 924 // CHECK3-NEXT: ret void 925 // 926 // 927 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 928 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 929 // CHECK3-NEXT: entry: 930 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 931 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 932 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 933 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 934 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 935 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 936 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 937 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 938 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 939 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 940 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 941 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 942 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 943 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 944 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 945 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 946 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 947 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 948 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 949 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 950 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 951 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 952 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 953 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 954 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 955 // CHECK3: arrayctor.loop: 956 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 957 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 958 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 959 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 960 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 961 // CHECK3: arrayctor.cont: 962 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 963 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 964 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 965 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 966 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 967 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 968 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 969 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 970 // CHECK3: cond.true: 971 // CHECK3-NEXT: br label [[COND_END:%.*]] 972 // CHECK3: cond.false: 973 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 974 // CHECK3-NEXT: br label [[COND_END]] 975 // CHECK3: cond.end: 976 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 977 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 978 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 979 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 980 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 981 // CHECK3: omp.inner.for.cond: 982 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 983 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 984 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 985 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 986 // CHECK3: omp.inner.for.cond.cleanup: 987 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 988 // CHECK3: omp.inner.for.body: 989 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 990 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 991 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 992 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 993 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 994 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 995 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] 996 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 997 // CHECK3-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 998 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 999 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] 1000 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* 1001 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 1002 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) 1003 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1004 // CHECK3: omp.body.continue: 1005 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1006 // CHECK3: omp.inner.for.inc: 1007 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1008 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 1009 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 1010 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1011 // CHECK3: omp.inner.for.end: 1012 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1013 // CHECK3: omp.loop.exit: 1014 // CHECK3-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1015 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 1016 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) 1017 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1018 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1019 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 1020 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1021 // CHECK3: arraydestroy.body: 1022 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1023 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1024 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1025 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 1026 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1027 // CHECK3: arraydestroy.done7: 1028 // CHECK3-NEXT: ret void 1029 // 1030 // 1031 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1032 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1033 // CHECK3-NEXT: entry: 1034 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1035 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1036 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1037 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1038 // CHECK3-NEXT: ret void 1039 // 1040 // 1041 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1042 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1043 // CHECK3-NEXT: entry: 1044 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1045 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1046 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1047 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1048 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1049 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1050 // CHECK3-NEXT: ret void 1051 // 1052 // 1053 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1054 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1055 // CHECK3-NEXT: entry: 1056 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1057 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1058 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1059 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1060 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1061 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1062 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1063 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1064 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1065 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1066 // CHECK3-NEXT: ret void 1067 // 1068 // 1069 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1070 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1071 // CHECK3-NEXT: entry: 1072 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1073 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1074 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1075 // CHECK3-NEXT: ret void 1076 // 1077 // 1078 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp 1079 // CHECK3-SAME: () #[[ATTR0]] { 1080 // CHECK3-NEXT: entry: 1081 // CHECK3-NEXT: call void @__cxx_global_var_init() 1082 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1083 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1084 // CHECK3-NEXT: ret void 1085 // 1086 // 1087 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1088 // CHECK3-SAME: () #[[ATTR0]] { 1089 // CHECK3-NEXT: entry: 1090 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 1091 // CHECK3-NEXT: ret void 1092 // 1093 // 1094 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 1095 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 1096 // CHECK9-NEXT: entry: 1097 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 1098 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1099 // CHECK9-NEXT: ret void 1100 // 1101 // 1102 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1103 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1104 // CHECK9-NEXT: entry: 1105 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1106 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1107 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1108 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1109 // CHECK9-NEXT: ret void 1110 // 1111 // 1112 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1113 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1114 // CHECK9-NEXT: entry: 1115 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1116 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1117 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1118 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1119 // CHECK9-NEXT: ret void 1120 // 1121 // 1122 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1123 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1124 // CHECK9-NEXT: entry: 1125 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1126 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1127 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1128 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1129 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1130 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1131 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 1132 // CHECK9-NEXT: ret void 1133 // 1134 // 1135 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1136 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1137 // CHECK9-NEXT: entry: 1138 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1139 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1140 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1141 // CHECK9-NEXT: ret void 1142 // 1143 // 1144 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1145 // CHECK9-SAME: () #[[ATTR0]] { 1146 // CHECK9-NEXT: entry: 1147 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 1148 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 1149 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1150 // CHECK9-NEXT: ret void 1151 // 1152 // 1153 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1154 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1155 // CHECK9-NEXT: entry: 1156 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1157 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1158 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1159 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1160 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1161 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1162 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1163 // CHECK9-NEXT: ret void 1164 // 1165 // 1166 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1167 // CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 1168 // CHECK9-NEXT: entry: 1169 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1170 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1171 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1172 // CHECK9: arraydestroy.body: 1173 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1174 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1175 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1176 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1177 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1178 // CHECK9: arraydestroy.done1: 1179 // CHECK9-NEXT: ret void 1180 // 1181 // 1182 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1183 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1184 // CHECK9-NEXT: entry: 1185 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1186 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1187 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1188 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1189 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1190 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1191 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1192 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1193 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1194 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1195 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 1196 // CHECK9-NEXT: ret void 1197 // 1198 // 1199 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1200 // CHECK9-SAME: () #[[ATTR0]] { 1201 // CHECK9-NEXT: entry: 1202 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1203 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1204 // CHECK9-NEXT: ret void 1205 // 1206 // 1207 // CHECK9-LABEL: define {{[^@]+}}@main 1208 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 1209 // CHECK9-NEXT: entry: 1210 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1211 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1212 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 1213 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1214 // CHECK9-NEXT: ret i32 0 1215 // 1216 // 1217 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 1218 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] { 1219 // CHECK9-NEXT: entry: 1220 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 1221 // CHECK9-NEXT: ret void 1222 // 1223 // 1224 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 1225 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { 1226 // CHECK9-NEXT: entry: 1227 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1228 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1229 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1230 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1231 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 1232 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1233 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1234 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1235 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1236 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 1237 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 1238 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 1239 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1240 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1241 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1242 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1243 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1244 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8 1245 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1246 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1247 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1248 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1249 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 1250 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1251 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1252 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1253 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1254 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1255 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1256 // CHECK9: cond.true: 1257 // CHECK9-NEXT: br label [[COND_END:%.*]] 1258 // CHECK9: cond.false: 1259 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1260 // CHECK9-NEXT: br label [[COND_END]] 1261 // CHECK9: cond.end: 1262 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1263 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1264 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1265 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1266 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1267 // CHECK9: omp.inner.for.cond: 1268 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1269 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1270 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1271 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1272 // CHECK9: omp.inner.for.body: 1273 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1274 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1275 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1276 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1277 // CHECK9-NEXT: store i32 1, i32* [[G]], align 4 1278 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8 1279 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 1280 // CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4 1281 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 1282 // CHECK9-NEXT: store i32* [[G]], i32** [[TMP9]], align 8 1283 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 1284 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8 1285 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 1286 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 1287 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 1288 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 1289 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1290 // CHECK9: omp.body.continue: 1291 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1292 // CHECK9: omp.inner.for.inc: 1293 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1294 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 1295 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 1296 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 1297 // CHECK9: omp.inner.for.end: 1298 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1299 // CHECK9: omp.loop.exit: 1300 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 1301 // CHECK9-NEXT: ret void 1302 // 1303 // 1304 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp 1305 // CHECK9-SAME: () #[[ATTR0]] { 1306 // CHECK9-NEXT: entry: 1307 // CHECK9-NEXT: call void @__cxx_global_var_init() 1308 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 1309 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 1310 // CHECK9-NEXT: ret void 1311 // 1312 // 1313 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1314 // CHECK9-SAME: () #[[ATTR0]] { 1315 // CHECK9-NEXT: entry: 1316 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 1317 // CHECK9-NEXT: ret void 1318 // 1319