1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
8
9 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
10 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
12 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
15
16 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
19
20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
23
24 // expected-no-diagnostics
25 #ifndef HEADER
26 #define HEADER
27
28 struct St {
29 int a, b;
StSt30 St() : a(0), b(0) {}
StSt31 St(const St &st) : a(st.a + st.b), b(0) {}
~StSt32 ~St() {}
33 };
34
35 volatile int g = 1212;
36 volatile int &g1 = g;
37
38 template <class T>
39 struct S {
40 T f;
SS41 S(T a) : f(a + g) {}
SS42 S() : f(g) {}
SS43 S(const S &s, St t = St()) : f(s.f + t.a) {}
operator TS44 operator T() { return T(); }
~SS45 ~S() {}
46 };
47
48
49 template <typename T>
tmain()50 T tmain() {
51 S<T> test;
52 T t_var = T();
53 T vec[] = {1, 2};
54 S<T> s_arr[] = {1, 2};
55 S<T> &var = test;
56 #pragma omp target teams distribute private(t_var, vec, s_arr, var)
57 for (int i = 0; i < 2; ++i) {
58 vec[i] = t_var;
59 s_arr[i] = var;
60 }
61 return T();
62 }
63
64 S<float> test;
65 int t_var = 333;
66 int vec[] = {1, 2};
67 S<float> s_arr[] = {1, 2};
68 S<float> var(3);
69
main()70 int main() {
71 static int sivar;
72 #ifdef LAMBDA
73 [&]() {
74 #pragma omp target teams distribute private(g, g1, sivar)
75 for (int i = 0; i < 2; ++i) {
76
77 // Skip global, bound tid and loop vars
78 g = 1;
79 g1 = 1;
80 sivar = 2;
81 [&]() {
82 g = 2;
83 g1 = 2;
84 sivar = 4;
85
86 }();
87 }
88 }();
89 return 0;
90 #else
91 #pragma omp target teams distribute private(t_var, vec, s_arr, var, sivar)
92 for (int i = 0; i < 2; ++i) {
93 vec[i] = t_var;
94 s_arr[i] = var;
95 sivar += i;
96 }
97 return tmain<int>();
98 #endif
99 }
100
101
102
103 // Skip global, bound tid and loop vars
104
105 // private(s_arr)
106
107 // private(var)
108
109
110
111
112
113 // Skip global, bound tid and loop vars
114
115 // private(s_arr)
116
117
118 // private(var)
119
120
121 #endif
122 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
123 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
124 // CHECK1-NEXT: entry:
125 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
126 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
127 // CHECK1-NEXT: ret void
128 //
129 //
130 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
131 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
132 // CHECK1-NEXT: entry:
133 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
134 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
135 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
136 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
137 // CHECK1-NEXT: ret void
138 //
139 //
140 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
141 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
142 // CHECK1-NEXT: entry:
143 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
144 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
145 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
146 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
147 // CHECK1-NEXT: ret void
148 //
149 //
150 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
151 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
152 // CHECK1-NEXT: entry:
153 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
154 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
155 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
156 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
157 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
158 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
159 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4
160 // CHECK1-NEXT: ret void
161 //
162 //
163 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
164 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
165 // CHECK1-NEXT: entry:
166 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
167 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
168 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
169 // CHECK1-NEXT: ret void
170 //
171 //
172 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
173 // CHECK1-SAME: () #[[ATTR0]] {
174 // CHECK1-NEXT: entry:
175 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
176 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
177 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
178 // CHECK1-NEXT: ret void
179 //
180 //
181 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
182 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
183 // CHECK1-NEXT: entry:
184 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
185 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
186 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
187 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
188 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
189 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
190 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
191 // CHECK1-NEXT: ret void
192 //
193 //
194 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
195 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
196 // CHECK1-NEXT: entry:
197 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
198 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
199 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
200 // CHECK1: arraydestroy.body:
201 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
202 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
203 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
204 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
205 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
206 // CHECK1: arraydestroy.done1:
207 // CHECK1-NEXT: ret void
208 //
209 //
210 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
211 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
212 // CHECK1-NEXT: entry:
213 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
214 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
215 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
216 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
217 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
218 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
219 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
220 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
221 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
222 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
223 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
224 // CHECK1-NEXT: ret void
225 //
226 //
227 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
228 // CHECK1-SAME: () #[[ATTR0]] {
229 // CHECK1-NEXT: entry:
230 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
231 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
232 // CHECK1-NEXT: ret void
233 //
234 //
235 // CHECK1-LABEL: define {{[^@]+}}@main
236 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
237 // CHECK1-NEXT: entry:
238 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
239 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
240 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
241 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
242 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
243 // CHECK1-NEXT: store i32 1, i32* [[TMP0]], align 4
244 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
245 // CHECK1-NEXT: store i32 0, i32* [[TMP1]], align 4
246 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
247 // CHECK1-NEXT: store i8** null, i8*** [[TMP2]], align 8
248 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
249 // CHECK1-NEXT: store i8** null, i8*** [[TMP3]], align 8
250 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
251 // CHECK1-NEXT: store i64* null, i64** [[TMP4]], align 8
252 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
253 // CHECK1-NEXT: store i64* null, i64** [[TMP5]], align 8
254 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
255 // CHECK1-NEXT: store i8** null, i8*** [[TMP6]], align 8
256 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
257 // CHECK1-NEXT: store i8** null, i8*** [[TMP7]], align 8
258 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
259 // CHECK1-NEXT: store i64 2, i64* [[TMP8]], align 8
260 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
261 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
262 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
263 // CHECK1: omp_offload.failed:
264 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]]
265 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
266 // CHECK1: omp_offload.cont:
267 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
268 // CHECK1-NEXT: ret i32 [[CALL]]
269 //
270 //
271 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91
272 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
273 // CHECK1-NEXT: entry:
274 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
275 // CHECK1-NEXT: ret void
276 //
277 //
278 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
279 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
280 // CHECK1-NEXT: entry:
281 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
282 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
283 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
284 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
285 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
286 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
287 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
288 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
289 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
290 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
291 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
292 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
293 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
294 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
295 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
296 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
297 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
298 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
299 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
300 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
301 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
302 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
303 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
304 // CHECK1: arrayctor.loop:
305 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
306 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
307 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
308 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
309 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
310 // CHECK1: arrayctor.cont:
311 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]])
312 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
313 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
314 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
315 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
316 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
317 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
318 // CHECK1: cond.true:
319 // CHECK1-NEXT: br label [[COND_END:%.*]]
320 // CHECK1: cond.false:
321 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
322 // CHECK1-NEXT: br label [[COND_END]]
323 // CHECK1: cond.end:
324 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
325 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
326 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
327 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
328 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
329 // CHECK1: omp.inner.for.cond:
330 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
331 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
332 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
333 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
334 // CHECK1: omp.inner.for.cond.cleanup:
335 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
336 // CHECK1: omp.inner.for.body:
337 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
338 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
339 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
340 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
341 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4
342 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
343 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
344 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
345 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4
346 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4
347 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64
348 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]]
349 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8*
350 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8*
351 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false)
352 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
353 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4
354 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
355 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR]], align 4
356 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
357 // CHECK1: omp.body.continue:
358 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
359 // CHECK1: omp.inner.for.inc:
360 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
361 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1
362 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
363 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
364 // CHECK1: omp.inner.for.end:
365 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
366 // CHECK1: omp.loop.exit:
367 // CHECK1-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
368 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
369 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]])
370 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
371 // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
372 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2
373 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
374 // CHECK1: arraydestroy.body:
375 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
376 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
377 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
378 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
379 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
380 // CHECK1: arraydestroy.done7:
381 // CHECK1-NEXT: ret void
382 //
383 //
384 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
385 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat {
386 // CHECK1-NEXT: entry:
387 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
388 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
389 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
390 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
391 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
392 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
393 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
394 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
395 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
396 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4
397 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
398 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
399 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
400 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
401 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
402 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
403 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
404 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
405 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
406 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
407 // CHECK1-NEXT: store i32 1, i32* [[TMP1]], align 4
408 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
409 // CHECK1-NEXT: store i32 0, i32* [[TMP2]], align 4
410 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
411 // CHECK1-NEXT: store i8** null, i8*** [[TMP3]], align 8
412 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
413 // CHECK1-NEXT: store i8** null, i8*** [[TMP4]], align 8
414 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
415 // CHECK1-NEXT: store i64* null, i64** [[TMP5]], align 8
416 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
417 // CHECK1-NEXT: store i64* null, i64** [[TMP6]], align 8
418 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
419 // CHECK1-NEXT: store i8** null, i8*** [[TMP7]], align 8
420 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
421 // CHECK1-NEXT: store i8** null, i8*** [[TMP8]], align 8
422 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
423 // CHECK1-NEXT: store i64 2, i64* [[TMP9]], align 8
424 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
425 // CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
426 // CHECK1-NEXT: br i1 [[TMP11]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
427 // CHECK1: omp_offload.failed:
428 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
429 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
430 // CHECK1: omp_offload.cont:
431 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
432 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
433 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
434 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
435 // CHECK1: arraydestroy.body:
436 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
437 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
438 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
439 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
440 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
441 // CHECK1: arraydestroy.done2:
442 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
443 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4
444 // CHECK1-NEXT: ret i32 [[TMP13]]
445 //
446 //
447 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
448 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
449 // CHECK1-NEXT: entry:
450 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
451 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
452 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
453 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
454 // CHECK1-NEXT: ret void
455 //
456 //
457 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
458 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
459 // CHECK1-NEXT: entry:
460 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
461 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
462 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
463 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
464 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
465 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
466 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
467 // CHECK1-NEXT: ret void
468 //
469 //
470 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
471 // CHECK1-SAME: () #[[ATTR4]] {
472 // CHECK1-NEXT: entry:
473 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*))
474 // CHECK1-NEXT: ret void
475 //
476 //
477 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
478 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
479 // CHECK1-NEXT: entry:
480 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
481 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
482 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
483 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
484 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
485 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
486 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
487 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
488 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
489 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
490 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
491 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
492 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
493 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8
494 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
495 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
496 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
497 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
498 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
499 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
500 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
501 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
502 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
503 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
504 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
505 // CHECK1: arrayctor.loop:
506 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
507 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
508 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
509 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
510 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
511 // CHECK1: arrayctor.cont:
512 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]])
513 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8
514 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
515 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
516 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
517 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
518 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
519 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
520 // CHECK1: cond.true:
521 // CHECK1-NEXT: br label [[COND_END:%.*]]
522 // CHECK1: cond.false:
523 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
524 // CHECK1-NEXT: br label [[COND_END]]
525 // CHECK1: cond.end:
526 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
527 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
528 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
529 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
530 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
531 // CHECK1: omp.inner.for.cond:
532 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
533 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
534 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
535 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
536 // CHECK1: omp.inner.for.cond.cleanup:
537 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
538 // CHECK1: omp.inner.for.body:
539 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
540 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
541 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
542 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
543 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4
544 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
545 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
546 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
547 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4
548 // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8
549 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
550 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
551 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]]
552 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8*
553 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8*
554 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false)
555 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
556 // CHECK1: omp.body.continue:
557 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
558 // CHECK1: omp.inner.for.inc:
559 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
560 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1
561 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
562 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
563 // CHECK1: omp.inner.for.end:
564 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
565 // CHECK1: omp.loop.exit:
566 // CHECK1-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
567 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4
568 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
569 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
570 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
571 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2
572 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
573 // CHECK1: arraydestroy.body:
574 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
575 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
576 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
577 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
578 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
579 // CHECK1: arraydestroy.done8:
580 // CHECK1-NEXT: ret void
581 //
582 //
583 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
584 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
585 // CHECK1-NEXT: entry:
586 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
587 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
588 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
589 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
590 // CHECK1-NEXT: ret void
591 //
592 //
593 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
594 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
595 // CHECK1-NEXT: entry:
596 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
597 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
598 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
599 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
600 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
601 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
602 // CHECK1-NEXT: ret void
603 //
604 //
605 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
606 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
607 // CHECK1-NEXT: entry:
608 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
609 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
610 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
611 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
612 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
613 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
614 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
615 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
616 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
617 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
618 // CHECK1-NEXT: ret void
619 //
620 //
621 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
622 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
623 // CHECK1-NEXT: entry:
624 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
625 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
626 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
627 // CHECK1-NEXT: ret void
628 //
629 //
630 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp
631 // CHECK1-SAME: () #[[ATTR0]] {
632 // CHECK1-NEXT: entry:
633 // CHECK1-NEXT: call void @__cxx_global_var_init()
634 // CHECK1-NEXT: call void @__cxx_global_var_init.1()
635 // CHECK1-NEXT: call void @__cxx_global_var_init.2()
636 // CHECK1-NEXT: ret void
637 //
638 //
639 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
640 // CHECK1-SAME: () #[[ATTR0]] {
641 // CHECK1-NEXT: entry:
642 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
643 // CHECK1-NEXT: ret void
644 //
645 //
646 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
647 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
648 // CHECK3-NEXT: entry:
649 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
650 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
651 // CHECK3-NEXT: ret void
652 //
653 //
654 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
655 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
656 // CHECK3-NEXT: entry:
657 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
658 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
659 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
660 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
661 // CHECK3-NEXT: ret void
662 //
663 //
664 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
665 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
666 // CHECK3-NEXT: entry:
667 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
668 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
669 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
670 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
671 // CHECK3-NEXT: ret void
672 //
673 //
674 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
675 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
676 // CHECK3-NEXT: entry:
677 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
678 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
679 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
680 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
681 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
682 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
683 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4
684 // CHECK3-NEXT: ret void
685 //
686 //
687 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
688 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
689 // CHECK3-NEXT: entry:
690 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
691 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
692 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
693 // CHECK3-NEXT: ret void
694 //
695 //
696 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
697 // CHECK3-SAME: () #[[ATTR0]] {
698 // CHECK3-NEXT: entry:
699 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00)
700 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00)
701 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
702 // CHECK3-NEXT: ret void
703 //
704 //
705 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
706 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
707 // CHECK3-NEXT: entry:
708 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
709 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
710 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
711 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
712 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
713 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
714 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
715 // CHECK3-NEXT: ret void
716 //
717 //
718 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
719 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
720 // CHECK3-NEXT: entry:
721 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
722 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
723 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
724 // CHECK3: arraydestroy.body:
725 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
726 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
727 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
728 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
729 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
730 // CHECK3: arraydestroy.done1:
731 // CHECK3-NEXT: ret void
732 //
733 //
734 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
735 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
736 // CHECK3-NEXT: entry:
737 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
738 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
739 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
740 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
741 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
742 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
743 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
744 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
745 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
746 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
747 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4
748 // CHECK3-NEXT: ret void
749 //
750 //
751 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
752 // CHECK3-SAME: () #[[ATTR0]] {
753 // CHECK3-NEXT: entry:
754 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
755 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
756 // CHECK3-NEXT: ret void
757 //
758 //
759 // CHECK3-LABEL: define {{[^@]+}}@main
760 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
761 // CHECK3-NEXT: entry:
762 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
763 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
764 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
765 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
766 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
767 // CHECK3-NEXT: store i32 1, i32* [[TMP0]], align 4
768 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
769 // CHECK3-NEXT: store i32 0, i32* [[TMP1]], align 4
770 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
771 // CHECK3-NEXT: store i8** null, i8*** [[TMP2]], align 4
772 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
773 // CHECK3-NEXT: store i8** null, i8*** [[TMP3]], align 4
774 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
775 // CHECK3-NEXT: store i64* null, i64** [[TMP4]], align 4
776 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
777 // CHECK3-NEXT: store i64* null, i64** [[TMP5]], align 4
778 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
779 // CHECK3-NEXT: store i8** null, i8*** [[TMP6]], align 4
780 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
781 // CHECK3-NEXT: store i8** null, i8*** [[TMP7]], align 4
782 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
783 // CHECK3-NEXT: store i64 2, i64* [[TMP8]], align 8
784 // CHECK3-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
785 // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
786 // CHECK3-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
787 // CHECK3: omp_offload.failed:
788 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]]
789 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
790 // CHECK3: omp_offload.cont:
791 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
792 // CHECK3-NEXT: ret i32 [[CALL]]
793 //
794 //
795 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91
796 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
797 // CHECK3-NEXT: entry:
798 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
799 // CHECK3-NEXT: ret void
800 //
801 //
802 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
803 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
804 // CHECK3-NEXT: entry:
805 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
806 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
807 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
808 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
809 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
810 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
811 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
812 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
813 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
814 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
815 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
816 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
817 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
818 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
819 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
820 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
821 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
822 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
823 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
824 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
825 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
826 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
827 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
828 // CHECK3: arrayctor.loop:
829 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
830 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
831 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
832 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
833 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
834 // CHECK3: arrayctor.cont:
835 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]])
836 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
837 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
838 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
839 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
840 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
841 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
842 // CHECK3: cond.true:
843 // CHECK3-NEXT: br label [[COND_END:%.*]]
844 // CHECK3: cond.false:
845 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
846 // CHECK3-NEXT: br label [[COND_END]]
847 // CHECK3: cond.end:
848 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
849 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
850 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
851 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
852 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
853 // CHECK3: omp.inner.for.cond:
854 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
855 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
856 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
857 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
858 // CHECK3: omp.inner.for.cond.cleanup:
859 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
860 // CHECK3: omp.inner.for.body:
861 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
862 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
863 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
864 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
865 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4
866 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
867 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]]
868 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4
869 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4
870 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP10]]
871 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
872 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8*
873 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false)
874 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
875 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4
876 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
877 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4
878 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
879 // CHECK3: omp.body.continue:
880 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
881 // CHECK3: omp.inner.for.inc:
882 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
883 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1
884 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
885 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
886 // CHECK3: omp.inner.for.end:
887 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
888 // CHECK3: omp.loop.exit:
889 // CHECK3-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
890 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
891 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]])
892 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
893 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
894 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2
895 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
896 // CHECK3: arraydestroy.body:
897 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
898 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
899 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
900 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
901 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
902 // CHECK3: arraydestroy.done6:
903 // CHECK3-NEXT: ret void
904 //
905 //
906 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
907 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat {
908 // CHECK3-NEXT: entry:
909 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
910 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
911 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
912 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
913 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
914 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
915 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
916 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
917 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
918 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4
919 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
920 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
921 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
922 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
923 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
924 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
925 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
926 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
927 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
928 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
929 // CHECK3-NEXT: store i32 1, i32* [[TMP1]], align 4
930 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
931 // CHECK3-NEXT: store i32 0, i32* [[TMP2]], align 4
932 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
933 // CHECK3-NEXT: store i8** null, i8*** [[TMP3]], align 4
934 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
935 // CHECK3-NEXT: store i8** null, i8*** [[TMP4]], align 4
936 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
937 // CHECK3-NEXT: store i64* null, i64** [[TMP5]], align 4
938 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
939 // CHECK3-NEXT: store i64* null, i64** [[TMP6]], align 4
940 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
941 // CHECK3-NEXT: store i8** null, i8*** [[TMP7]], align 4
942 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
943 // CHECK3-NEXT: store i8** null, i8*** [[TMP8]], align 4
944 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
945 // CHECK3-NEXT: store i64 2, i64* [[TMP9]], align 8
946 // CHECK3-NEXT: [[TMP10:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
947 // CHECK3-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
948 // CHECK3-NEXT: br i1 [[TMP11]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
949 // CHECK3: omp_offload.failed:
950 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
951 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
952 // CHECK3: omp_offload.cont:
953 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
954 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
955 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
956 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
957 // CHECK3: arraydestroy.body:
958 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
959 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
960 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
961 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
962 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
963 // CHECK3: arraydestroy.done2:
964 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
965 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4
966 // CHECK3-NEXT: ret i32 [[TMP13]]
967 //
968 //
969 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
970 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
971 // CHECK3-NEXT: entry:
972 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
973 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
974 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
975 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
976 // CHECK3-NEXT: ret void
977 //
978 //
979 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
980 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
981 // CHECK3-NEXT: entry:
982 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
983 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
984 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
985 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
986 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
987 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
988 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
989 // CHECK3-NEXT: ret void
990 //
991 //
992 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
993 // CHECK3-SAME: () #[[ATTR4]] {
994 // CHECK3-NEXT: entry:
995 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*))
996 // CHECK3-NEXT: ret void
997 //
998 //
999 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
1000 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
1001 // CHECK3-NEXT: entry:
1002 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1003 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1004 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1005 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1006 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1007 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1008 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1009 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1010 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1011 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1012 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1013 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1014 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1015 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4
1016 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1017 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1018 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1019 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1020 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1021 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1022 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1023 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1024 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1025 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1026 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1027 // CHECK3: arrayctor.loop:
1028 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1029 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1030 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
1031 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1032 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1033 // CHECK3: arrayctor.cont:
1034 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]])
1035 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4
1036 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1037 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1038 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1039 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1040 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1041 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1042 // CHECK3: cond.true:
1043 // CHECK3-NEXT: br label [[COND_END:%.*]]
1044 // CHECK3: cond.false:
1045 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1046 // CHECK3-NEXT: br label [[COND_END]]
1047 // CHECK3: cond.end:
1048 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1049 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1050 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1051 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1052 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1053 // CHECK3: omp.inner.for.cond:
1054 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1055 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1056 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1057 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1058 // CHECK3: omp.inner.for.cond.cleanup:
1059 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1060 // CHECK3: omp.inner.for.body:
1061 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1062 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1063 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1064 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1065 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4
1066 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
1067 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]]
1068 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4
1069 // CHECK3-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4
1070 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
1071 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]]
1072 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8*
1073 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8*
1074 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false)
1075 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1076 // CHECK3: omp.body.continue:
1077 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1078 // CHECK3: omp.inner.for.inc:
1079 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1080 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
1081 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
1082 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
1083 // CHECK3: omp.inner.for.end:
1084 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1085 // CHECK3: omp.loop.exit:
1086 // CHECK3-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1087 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4
1088 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
1089 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1090 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1091 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2
1092 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1093 // CHECK3: arraydestroy.body:
1094 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1095 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1096 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1097 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
1098 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
1099 // CHECK3: arraydestroy.done7:
1100 // CHECK3-NEXT: ret void
1101 //
1102 //
1103 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1104 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1105 // CHECK3-NEXT: entry:
1106 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1107 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1108 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1109 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1110 // CHECK3-NEXT: ret void
1111 //
1112 //
1113 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1114 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1115 // CHECK3-NEXT: entry:
1116 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1117 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1118 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1119 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1120 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1121 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1122 // CHECK3-NEXT: ret void
1123 //
1124 //
1125 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1126 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1127 // CHECK3-NEXT: entry:
1128 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1129 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1130 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1131 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1132 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1133 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1134 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1135 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1136 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1137 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1138 // CHECK3-NEXT: ret void
1139 //
1140 //
1141 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1142 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1143 // CHECK3-NEXT: entry:
1144 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1145 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1146 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1147 // CHECK3-NEXT: ret void
1148 //
1149 //
1150 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp
1151 // CHECK3-SAME: () #[[ATTR0]] {
1152 // CHECK3-NEXT: entry:
1153 // CHECK3-NEXT: call void @__cxx_global_var_init()
1154 // CHECK3-NEXT: call void @__cxx_global_var_init.1()
1155 // CHECK3-NEXT: call void @__cxx_global_var_init.2()
1156 // CHECK3-NEXT: ret void
1157 //
1158 //
1159 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1160 // CHECK3-SAME: () #[[ATTR0]] {
1161 // CHECK3-NEXT: entry:
1162 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
1163 // CHECK3-NEXT: ret void
1164 //
1165 //
1166 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init
1167 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
1168 // CHECK9-NEXT: entry:
1169 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
1170 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1171 // CHECK9-NEXT: ret void
1172 //
1173 //
1174 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1175 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1176 // CHECK9-NEXT: entry:
1177 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1178 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1179 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1180 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1181 // CHECK9-NEXT: ret void
1182 //
1183 //
1184 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1185 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1186 // CHECK9-NEXT: entry:
1187 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1188 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1189 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1190 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1191 // CHECK9-NEXT: ret void
1192 //
1193 //
1194 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1195 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1196 // CHECK9-NEXT: entry:
1197 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1198 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1199 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1200 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1201 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1202 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1203 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4
1204 // CHECK9-NEXT: ret void
1205 //
1206 //
1207 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1208 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1209 // CHECK9-NEXT: entry:
1210 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1211 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1212 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1213 // CHECK9-NEXT: ret void
1214 //
1215 //
1216 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1217 // CHECK9-SAME: () #[[ATTR0]] {
1218 // CHECK9-NEXT: entry:
1219 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
1220 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
1221 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
1222 // CHECK9-NEXT: ret void
1223 //
1224 //
1225 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1226 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1227 // CHECK9-NEXT: entry:
1228 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1229 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1230 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1231 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1232 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1233 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1234 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1235 // CHECK9-NEXT: ret void
1236 //
1237 //
1238 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1239 // CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
1240 // CHECK9-NEXT: entry:
1241 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
1242 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1243 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1244 // CHECK9: arraydestroy.body:
1245 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1246 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1247 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1248 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
1249 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1250 // CHECK9: arraydestroy.done1:
1251 // CHECK9-NEXT: ret void
1252 //
1253 //
1254 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1255 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1256 // CHECK9-NEXT: entry:
1257 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1258 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1259 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1260 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1261 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1262 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1263 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1264 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1265 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1266 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1267 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4
1268 // CHECK9-NEXT: ret void
1269 //
1270 //
1271 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1272 // CHECK9-SAME: () #[[ATTR0]] {
1273 // CHECK9-NEXT: entry:
1274 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1275 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1276 // CHECK9-NEXT: ret void
1277 //
1278 //
1279 // CHECK9-LABEL: define {{[^@]+}}@main
1280 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
1281 // CHECK9-NEXT: entry:
1282 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1283 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
1284 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4
1285 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
1286 // CHECK9-NEXT: ret i32 0
1287 //
1288 //
1289 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74
1290 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] {
1291 // CHECK9-NEXT: entry:
1292 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
1293 // CHECK9-NEXT: ret void
1294 //
1295 //
1296 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
1297 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
1298 // CHECK9-NEXT: entry:
1299 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1300 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1301 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1302 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
1303 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8
1304 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1305 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1306 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1307 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1308 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4
1309 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4
1310 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8
1311 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1312 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
1313 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
1314 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1315 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1316 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8
1317 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1318 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1319 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1320 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1321 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8
1322 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1323 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1324 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1325 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1326 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1327 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1328 // CHECK9: cond.true:
1329 // CHECK9-NEXT: br label [[COND_END:%.*]]
1330 // CHECK9: cond.false:
1331 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1332 // CHECK9-NEXT: br label [[COND_END]]
1333 // CHECK9: cond.end:
1334 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1335 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1336 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1337 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1338 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1339 // CHECK9: omp.inner.for.cond:
1340 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1341 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1342 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1343 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1344 // CHECK9: omp.inner.for.body:
1345 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1346 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1347 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1348 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1349 // CHECK9-NEXT: store i32 1, i32* [[G]], align 4
1350 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8
1351 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4
1352 // CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4
1353 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
1354 // CHECK9-NEXT: store i32* [[G]], i32** [[TMP9]], align 8
1355 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
1356 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8
1357 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8
1358 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
1359 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8
1360 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])
1361 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1362 // CHECK9: omp.body.continue:
1363 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1364 // CHECK9: omp.inner.for.inc:
1365 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1366 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
1367 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
1368 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
1369 // CHECK9: omp.inner.for.end:
1370 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1371 // CHECK9: omp.loop.exit:
1372 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
1373 // CHECK9-NEXT: ret void
1374 //
1375 //
1376 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp
1377 // CHECK9-SAME: () #[[ATTR0]] {
1378 // CHECK9-NEXT: entry:
1379 // CHECK9-NEXT: call void @__cxx_global_var_init()
1380 // CHECK9-NEXT: call void @__cxx_global_var_init.1()
1381 // CHECK9-NEXT: call void @__cxx_global_var_init.2()
1382 // CHECK9-NEXT: ret void
1383 //
1384 //
1385 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1386 // CHECK9-SAME: () #[[ATTR0]] {
1387 // CHECK9-NEXT: entry:
1388 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1)
1389 // CHECK9-NEXT: ret void
1390 //
1391