1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target teams distribute private(t_var, vec, s_arr, var) 57 for (int i = 0; i < 2; ++i) { 58 vec[i] = t_var; 59 s_arr[i] = var; 60 } 61 return T(); 62 } 63 64 S<float> test; 65 int t_var = 333; 66 int vec[] = {1, 2}; 67 S<float> s_arr[] = {1, 2}; 68 S<float> var(3); 69 70 int main() { 71 static int sivar; 72 #ifdef LAMBDA 73 [&]() { 74 #pragma omp target teams distribute private(g, g1, sivar) 75 for (int i = 0; i < 2; ++i) { 76 77 // Skip global, bound tid and loop vars 78 g = 1; 79 g1 = 1; 80 sivar = 2; 81 [&]() { 82 g = 2; 83 g1 = 2; 84 sivar = 4; 85 86 }(); 87 } 88 }(); 89 return 0; 90 #else 91 #pragma omp target teams distribute private(t_var, vec, s_arr, var, sivar) 92 for (int i = 0; i < 2; ++i) { 93 vec[i] = t_var; 94 s_arr[i] = var; 95 sivar += i; 96 } 97 return tmain<int>(); 98 #endif 99 } 100 101 102 103 // Skip global, bound tid and loop vars 104 105 // private(s_arr) 106 107 // private(var) 108 109 110 111 112 113 // Skip global, bound tid and loop vars 114 115 // private(s_arr) 116 117 118 // private(var) 119 120 121 #endif 122 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 123 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 124 // CHECK1-NEXT: entry: 125 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 126 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 127 // CHECK1-NEXT: ret void 128 // 129 // 130 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 131 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 132 // CHECK1-NEXT: entry: 133 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 134 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 135 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 136 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 137 // CHECK1-NEXT: ret void 138 // 139 // 140 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 141 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 142 // CHECK1-NEXT: entry: 143 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 144 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 145 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 146 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 147 // CHECK1-NEXT: ret void 148 // 149 // 150 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 151 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 152 // CHECK1-NEXT: entry: 153 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 154 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 155 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 156 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 157 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 158 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 159 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4 160 // CHECK1-NEXT: ret void 161 // 162 // 163 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 164 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 165 // CHECK1-NEXT: entry: 166 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 167 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 168 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 169 // CHECK1-NEXT: ret void 170 // 171 // 172 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 173 // CHECK1-SAME: () #[[ATTR0]] { 174 // CHECK1-NEXT: entry: 175 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 176 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 177 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 178 // CHECK1-NEXT: ret void 179 // 180 // 181 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 182 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 183 // CHECK1-NEXT: entry: 184 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 185 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 186 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 187 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 188 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 189 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 190 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 191 // CHECK1-NEXT: ret void 192 // 193 // 194 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 195 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 196 // CHECK1-NEXT: entry: 197 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 198 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 199 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 200 // CHECK1: arraydestroy.body: 201 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 202 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 203 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 204 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 205 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 206 // CHECK1: arraydestroy.done1: 207 // CHECK1-NEXT: ret void 208 // 209 // 210 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 211 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 212 // CHECK1-NEXT: entry: 213 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 214 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 215 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 216 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 217 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 218 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 219 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 220 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 221 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 222 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 223 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 224 // CHECK1-NEXT: ret void 225 // 226 // 227 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 228 // CHECK1-SAME: () #[[ATTR0]] { 229 // CHECK1-NEXT: entry: 230 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 231 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 232 // CHECK1-NEXT: ret void 233 // 234 // 235 // CHECK1-LABEL: define {{[^@]+}}@main 236 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 237 // CHECK1-NEXT: entry: 238 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 239 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 240 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 241 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 242 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 243 // CHECK1-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 244 // CHECK1-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 245 // CHECK1: omp_offload.failed: 246 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]] 247 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 248 // CHECK1: omp_offload.cont: 249 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 250 // CHECK1-NEXT: ret i32 [[CALL]] 251 // 252 // 253 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 254 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 255 // CHECK1-NEXT: entry: 256 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 257 // CHECK1-NEXT: ret void 258 // 259 // 260 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 261 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 262 // CHECK1-NEXT: entry: 263 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 264 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 265 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 266 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 267 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 268 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 269 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 270 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 271 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 272 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 273 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 274 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 275 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 276 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 277 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 278 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 279 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 280 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 281 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 282 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 283 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 284 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 285 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 286 // CHECK1: arrayctor.loop: 287 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 288 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 289 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 290 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 291 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 292 // CHECK1: arrayctor.cont: 293 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 294 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 295 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 296 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 297 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 298 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 299 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 300 // CHECK1: cond.true: 301 // CHECK1-NEXT: br label [[COND_END:%.*]] 302 // CHECK1: cond.false: 303 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 304 // CHECK1-NEXT: br label [[COND_END]] 305 // CHECK1: cond.end: 306 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 307 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 308 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 309 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 310 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 311 // CHECK1: omp.inner.for.cond: 312 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 313 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 314 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 315 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 316 // CHECK1: omp.inner.for.cond.cleanup: 317 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 318 // CHECK1: omp.inner.for.body: 319 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 320 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 321 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 322 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 323 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 324 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 325 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 326 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 327 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 328 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 329 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 330 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] 331 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* 332 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8* 333 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false) 334 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 335 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4 336 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 337 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR]], align 4 338 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 339 // CHECK1: omp.body.continue: 340 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 341 // CHECK1: omp.inner.for.inc: 342 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 343 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 344 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 345 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 346 // CHECK1: omp.inner.for.end: 347 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 348 // CHECK1: omp.loop.exit: 349 // CHECK1-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 350 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 351 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) 352 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 353 // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 354 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 355 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 356 // CHECK1: arraydestroy.body: 357 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 358 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 359 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 360 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 361 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 362 // CHECK1: arraydestroy.done7: 363 // CHECK1-NEXT: ret void 364 // 365 // 366 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 367 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat { 368 // CHECK1-NEXT: entry: 369 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 370 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 371 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 372 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 373 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 374 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 375 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 376 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 377 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 378 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 379 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 380 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 381 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 382 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 383 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 384 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 385 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 386 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 387 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 388 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 389 // CHECK1-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 390 // CHECK1-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 391 // CHECK1: omp_offload.failed: 392 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 393 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 394 // CHECK1: omp_offload.cont: 395 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 396 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 397 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 398 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 399 // CHECK1: arraydestroy.body: 400 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 401 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 402 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 403 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 404 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 405 // CHECK1: arraydestroy.done2: 406 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 407 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 408 // CHECK1-NEXT: ret i32 [[TMP4]] 409 // 410 // 411 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 412 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 413 // CHECK1-NEXT: entry: 414 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 415 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 416 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 417 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 418 // CHECK1-NEXT: ret void 419 // 420 // 421 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 422 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 423 // CHECK1-NEXT: entry: 424 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 425 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 426 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 427 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 428 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 429 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 430 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 431 // CHECK1-NEXT: ret void 432 // 433 // 434 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 435 // CHECK1-SAME: () #[[ATTR4]] { 436 // CHECK1-NEXT: entry: 437 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) 438 // CHECK1-NEXT: ret void 439 // 440 // 441 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 442 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 443 // CHECK1-NEXT: entry: 444 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 445 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 446 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 447 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 448 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 449 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 450 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 451 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 452 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 453 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 454 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 455 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 456 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 457 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 458 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 459 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 460 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 461 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 462 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 463 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 464 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 465 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 466 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 467 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 468 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 469 // CHECK1: arrayctor.loop: 470 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 471 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 472 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 473 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 474 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 475 // CHECK1: arrayctor.cont: 476 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) 477 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 478 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 479 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 480 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 481 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 482 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 483 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 484 // CHECK1: cond.true: 485 // CHECK1-NEXT: br label [[COND_END:%.*]] 486 // CHECK1: cond.false: 487 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 488 // CHECK1-NEXT: br label [[COND_END]] 489 // CHECK1: cond.end: 490 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 491 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 492 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 493 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 494 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 495 // CHECK1: omp.inner.for.cond: 496 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 497 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 498 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 499 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 500 // CHECK1: omp.inner.for.cond.cleanup: 501 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 502 // CHECK1: omp.inner.for.body: 503 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 504 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 505 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 506 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 507 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 508 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 509 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 510 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 511 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 512 // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 513 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 514 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 515 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] 516 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* 517 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 518 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) 519 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 520 // CHECK1: omp.body.continue: 521 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 522 // CHECK1: omp.inner.for.inc: 523 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 524 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 525 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 526 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 527 // CHECK1: omp.inner.for.end: 528 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 529 // CHECK1: omp.loop.exit: 530 // CHECK1-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 531 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 532 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) 533 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 534 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 535 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 536 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 537 // CHECK1: arraydestroy.body: 538 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 539 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 540 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 541 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 542 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 543 // CHECK1: arraydestroy.done8: 544 // CHECK1-NEXT: ret void 545 // 546 // 547 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 548 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 549 // CHECK1-NEXT: entry: 550 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 551 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 552 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 553 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 554 // CHECK1-NEXT: ret void 555 // 556 // 557 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 558 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 559 // CHECK1-NEXT: entry: 560 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 561 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 562 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 563 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 564 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 565 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 566 // CHECK1-NEXT: ret void 567 // 568 // 569 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 570 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 571 // CHECK1-NEXT: entry: 572 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 573 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 574 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 575 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 576 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 577 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 578 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 579 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 580 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 581 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 582 // CHECK1-NEXT: ret void 583 // 584 // 585 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 586 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 587 // CHECK1-NEXT: entry: 588 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 589 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 590 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 591 // CHECK1-NEXT: ret void 592 // 593 // 594 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp 595 // CHECK1-SAME: () #[[ATTR0]] { 596 // CHECK1-NEXT: entry: 597 // CHECK1-NEXT: call void @__cxx_global_var_init() 598 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 599 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 600 // CHECK1-NEXT: ret void 601 // 602 // 603 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 604 // CHECK1-SAME: () #[[ATTR0]] { 605 // CHECK1-NEXT: entry: 606 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 607 // CHECK1-NEXT: ret void 608 // 609 // 610 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init 611 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 612 // CHECK2-NEXT: entry: 613 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 614 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 615 // CHECK2-NEXT: ret void 616 // 617 // 618 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 619 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 620 // CHECK2-NEXT: entry: 621 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 622 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 623 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 624 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 625 // CHECK2-NEXT: ret void 626 // 627 // 628 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 629 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 630 // CHECK2-NEXT: entry: 631 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 632 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 633 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 634 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 635 // CHECK2-NEXT: ret void 636 // 637 // 638 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 639 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 640 // CHECK2-NEXT: entry: 641 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 642 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 643 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 644 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 645 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 646 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 647 // CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4 648 // CHECK2-NEXT: ret void 649 // 650 // 651 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 652 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 653 // CHECK2-NEXT: entry: 654 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 655 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 656 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 657 // CHECK2-NEXT: ret void 658 // 659 // 660 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 661 // CHECK2-SAME: () #[[ATTR0]] { 662 // CHECK2-NEXT: entry: 663 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 664 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 665 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 666 // CHECK2-NEXT: ret void 667 // 668 // 669 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 670 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 671 // CHECK2-NEXT: entry: 672 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 673 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 674 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 675 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 676 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 677 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 678 // CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 679 // CHECK2-NEXT: ret void 680 // 681 // 682 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 683 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 684 // CHECK2-NEXT: entry: 685 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 686 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 687 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 688 // CHECK2: arraydestroy.body: 689 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 690 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 691 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 692 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 693 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 694 // CHECK2: arraydestroy.done1: 695 // CHECK2-NEXT: ret void 696 // 697 // 698 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 699 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 700 // CHECK2-NEXT: entry: 701 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 702 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 703 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 704 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 705 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 706 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 707 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 708 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 709 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 710 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 711 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4 712 // CHECK2-NEXT: ret void 713 // 714 // 715 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 716 // CHECK2-SAME: () #[[ATTR0]] { 717 // CHECK2-NEXT: entry: 718 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 719 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 720 // CHECK2-NEXT: ret void 721 // 722 // 723 // CHECK2-LABEL: define {{[^@]+}}@main 724 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 725 // CHECK2-NEXT: entry: 726 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 727 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 728 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 729 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 730 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 731 // CHECK2-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 732 // CHECK2-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 733 // CHECK2: omp_offload.failed: 734 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]] 735 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 736 // CHECK2: omp_offload.cont: 737 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 738 // CHECK2-NEXT: ret i32 [[CALL]] 739 // 740 // 741 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 742 // CHECK2-SAME: () #[[ATTR4:[0-9]+]] { 743 // CHECK2-NEXT: entry: 744 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 745 // CHECK2-NEXT: ret void 746 // 747 // 748 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 749 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 750 // CHECK2-NEXT: entry: 751 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 752 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 753 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 754 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 755 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 756 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 757 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 758 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 759 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 760 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 761 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 762 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 763 // CHECK2-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 764 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 765 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 766 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 767 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 768 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 769 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 770 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 771 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 772 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 773 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 774 // CHECK2: arrayctor.loop: 775 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 776 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 777 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 778 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 779 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 780 // CHECK2: arrayctor.cont: 781 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 782 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 783 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 784 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 785 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 786 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 787 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 788 // CHECK2: cond.true: 789 // CHECK2-NEXT: br label [[COND_END:%.*]] 790 // CHECK2: cond.false: 791 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 792 // CHECK2-NEXT: br label [[COND_END]] 793 // CHECK2: cond.end: 794 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 795 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 796 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 797 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 798 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 799 // CHECK2: omp.inner.for.cond: 800 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 801 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 802 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 803 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 804 // CHECK2: omp.inner.for.cond.cleanup: 805 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 806 // CHECK2: omp.inner.for.body: 807 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 808 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 809 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 810 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 811 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 812 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 813 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 814 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 815 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 816 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 817 // CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 818 // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] 819 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* 820 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8* 821 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false) 822 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 823 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4 824 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 825 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[SIVAR]], align 4 826 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 827 // CHECK2: omp.body.continue: 828 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 829 // CHECK2: omp.inner.for.inc: 830 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 831 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 832 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 833 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 834 // CHECK2: omp.inner.for.end: 835 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 836 // CHECK2: omp.loop.exit: 837 // CHECK2-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 838 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 839 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) 840 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 841 // CHECK2-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 842 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 843 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 844 // CHECK2: arraydestroy.body: 845 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 846 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 847 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 848 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 849 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 850 // CHECK2: arraydestroy.done7: 851 // CHECK2-NEXT: ret void 852 // 853 // 854 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 855 // CHECK2-SAME: () #[[ATTR6:[0-9]+]] comdat { 856 // CHECK2-NEXT: entry: 857 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 858 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 859 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 860 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 861 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 862 // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 863 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 864 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 865 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 866 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 867 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 868 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 869 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 870 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 871 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 872 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 873 // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 874 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 875 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 876 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 877 // CHECK2-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 878 // CHECK2-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 879 // CHECK2: omp_offload.failed: 880 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 881 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 882 // CHECK2: omp_offload.cont: 883 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 884 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 885 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 886 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 887 // CHECK2: arraydestroy.body: 888 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 889 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 890 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 891 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 892 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 893 // CHECK2: arraydestroy.done2: 894 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 895 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 896 // CHECK2-NEXT: ret i32 [[TMP4]] 897 // 898 // 899 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 900 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 901 // CHECK2-NEXT: entry: 902 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 903 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 904 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 905 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 906 // CHECK2-NEXT: ret void 907 // 908 // 909 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 910 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 911 // CHECK2-NEXT: entry: 912 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 913 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 914 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 915 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 916 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 917 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 918 // CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 919 // CHECK2-NEXT: ret void 920 // 921 // 922 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 923 // CHECK2-SAME: () #[[ATTR4]] { 924 // CHECK2-NEXT: entry: 925 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) 926 // CHECK2-NEXT: ret void 927 // 928 // 929 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 930 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 931 // CHECK2-NEXT: entry: 932 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 933 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 934 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 935 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 936 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 937 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 938 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 939 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 940 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 941 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 942 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 943 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 944 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 945 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 946 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 947 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 948 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 949 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 950 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 951 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 952 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 953 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 954 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 955 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 956 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 957 // CHECK2: arrayctor.loop: 958 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 959 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 960 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 961 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 962 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 963 // CHECK2: arrayctor.cont: 964 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) 965 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 966 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 967 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 968 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 969 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 970 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 971 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 972 // CHECK2: cond.true: 973 // CHECK2-NEXT: br label [[COND_END:%.*]] 974 // CHECK2: cond.false: 975 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 976 // CHECK2-NEXT: br label [[COND_END]] 977 // CHECK2: cond.end: 978 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 979 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 980 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 981 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 982 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 983 // CHECK2: omp.inner.for.cond: 984 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 985 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 986 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 987 // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 988 // CHECK2: omp.inner.for.cond.cleanup: 989 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 990 // CHECK2: omp.inner.for.body: 991 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 992 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 993 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 994 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 995 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 996 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 997 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 998 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 999 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 1000 // CHECK2-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 1001 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 1002 // CHECK2-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 1003 // CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] 1004 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* 1005 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 1006 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) 1007 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1008 // CHECK2: omp.body.continue: 1009 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1010 // CHECK2: omp.inner.for.inc: 1011 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1012 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 1013 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 1014 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1015 // CHECK2: omp.inner.for.end: 1016 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1017 // CHECK2: omp.loop.exit: 1018 // CHECK2-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1019 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 1020 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) 1021 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1022 // CHECK2-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1023 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 1024 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1025 // CHECK2: arraydestroy.body: 1026 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1027 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1028 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1029 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 1030 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 1031 // CHECK2: arraydestroy.done8: 1032 // CHECK2-NEXT: ret void 1033 // 1034 // 1035 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1036 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1037 // CHECK2-NEXT: entry: 1038 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1039 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1040 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1041 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1042 // CHECK2-NEXT: ret void 1043 // 1044 // 1045 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1046 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1047 // CHECK2-NEXT: entry: 1048 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1049 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1050 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1051 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1052 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1053 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1054 // CHECK2-NEXT: ret void 1055 // 1056 // 1057 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1058 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1059 // CHECK2-NEXT: entry: 1060 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1061 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1062 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1063 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1064 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1065 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1066 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1067 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1068 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1069 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1070 // CHECK2-NEXT: ret void 1071 // 1072 // 1073 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1074 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1075 // CHECK2-NEXT: entry: 1076 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1077 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1078 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1079 // CHECK2-NEXT: ret void 1080 // 1081 // 1082 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp 1083 // CHECK2-SAME: () #[[ATTR0]] { 1084 // CHECK2-NEXT: entry: 1085 // CHECK2-NEXT: call void @__cxx_global_var_init() 1086 // CHECK2-NEXT: call void @__cxx_global_var_init.1() 1087 // CHECK2-NEXT: call void @__cxx_global_var_init.2() 1088 // CHECK2-NEXT: ret void 1089 // 1090 // 1091 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1092 // CHECK2-SAME: () #[[ATTR0]] { 1093 // CHECK2-NEXT: entry: 1094 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 1095 // CHECK2-NEXT: ret void 1096 // 1097 // 1098 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 1099 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 1100 // CHECK3-NEXT: entry: 1101 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 1102 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1103 // CHECK3-NEXT: ret void 1104 // 1105 // 1106 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1107 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1108 // CHECK3-NEXT: entry: 1109 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1110 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1111 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1112 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 1113 // CHECK3-NEXT: ret void 1114 // 1115 // 1116 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1117 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1118 // CHECK3-NEXT: entry: 1119 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1120 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1121 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1122 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1123 // CHECK3-NEXT: ret void 1124 // 1125 // 1126 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1127 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1128 // CHECK3-NEXT: entry: 1129 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1130 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1131 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1132 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1133 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1134 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1135 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4 1136 // CHECK3-NEXT: ret void 1137 // 1138 // 1139 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1140 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1141 // CHECK3-NEXT: entry: 1142 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1143 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1144 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1145 // CHECK3-NEXT: ret void 1146 // 1147 // 1148 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1149 // CHECK3-SAME: () #[[ATTR0]] { 1150 // CHECK3-NEXT: entry: 1151 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 1152 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 1153 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1154 // CHECK3-NEXT: ret void 1155 // 1156 // 1157 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1158 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1159 // CHECK3-NEXT: entry: 1160 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1161 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1162 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1163 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1164 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1165 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1166 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 1167 // CHECK3-NEXT: ret void 1168 // 1169 // 1170 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1171 // CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 1172 // CHECK3-NEXT: entry: 1173 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 1174 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 1175 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1176 // CHECK3: arraydestroy.body: 1177 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1178 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1179 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1180 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1181 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1182 // CHECK3: arraydestroy.done1: 1183 // CHECK3-NEXT: ret void 1184 // 1185 // 1186 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1187 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1188 // CHECK3-NEXT: entry: 1189 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1190 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1191 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1192 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1193 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1194 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1195 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1196 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1197 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1198 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1199 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 1200 // CHECK3-NEXT: ret void 1201 // 1202 // 1203 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1204 // CHECK3-SAME: () #[[ATTR0]] { 1205 // CHECK3-NEXT: entry: 1206 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 1207 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1208 // CHECK3-NEXT: ret void 1209 // 1210 // 1211 // CHECK3-LABEL: define {{[^@]+}}@main 1212 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1213 // CHECK3-NEXT: entry: 1214 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1215 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1216 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 1217 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 1218 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 1219 // CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 1220 // CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1221 // CHECK3: omp_offload.failed: 1222 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]] 1223 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1224 // CHECK3: omp_offload.cont: 1225 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 1226 // CHECK3-NEXT: ret i32 [[CALL]] 1227 // 1228 // 1229 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 1230 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 1231 // CHECK3-NEXT: entry: 1232 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 1233 // CHECK3-NEXT: ret void 1234 // 1235 // 1236 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1237 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1238 // CHECK3-NEXT: entry: 1239 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1240 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1241 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1242 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1243 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1244 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1245 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1246 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1247 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1248 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1249 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1250 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1251 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1252 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1253 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1254 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1255 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1256 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1257 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1258 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1259 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1260 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1261 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1262 // CHECK3: arrayctor.loop: 1263 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1264 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1265 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 1266 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1267 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1268 // CHECK3: arrayctor.cont: 1269 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 1270 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1271 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1272 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1273 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1274 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1275 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1276 // CHECK3: cond.true: 1277 // CHECK3-NEXT: br label [[COND_END:%.*]] 1278 // CHECK3: cond.false: 1279 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1280 // CHECK3-NEXT: br label [[COND_END]] 1281 // CHECK3: cond.end: 1282 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1283 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1284 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1285 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1286 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1287 // CHECK3: omp.inner.for.cond: 1288 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1289 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1290 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1291 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1292 // CHECK3: omp.inner.for.cond.cleanup: 1293 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1294 // CHECK3: omp.inner.for.body: 1295 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1296 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1297 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1298 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1299 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 1300 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 1301 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] 1302 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 1303 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 1304 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP10]] 1305 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 1306 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8* 1307 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false) 1308 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1309 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4 1310 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 1311 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 1312 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1313 // CHECK3: omp.body.continue: 1314 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1315 // CHECK3: omp.inner.for.inc: 1316 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1317 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 1318 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 1319 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1320 // CHECK3: omp.inner.for.end: 1321 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1322 // CHECK3: omp.loop.exit: 1323 // CHECK3-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1324 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 1325 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) 1326 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1327 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1328 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 1329 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1330 // CHECK3: arraydestroy.body: 1331 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1332 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1333 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1334 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 1335 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1336 // CHECK3: arraydestroy.done6: 1337 // CHECK3-NEXT: ret void 1338 // 1339 // 1340 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1341 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat { 1342 // CHECK3-NEXT: entry: 1343 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1344 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1345 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1346 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1347 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1348 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 1349 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1350 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 1351 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 1352 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 1353 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1354 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1355 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1356 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 1357 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 1358 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 1359 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 1360 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 1361 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 1362 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 1363 // CHECK3-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 1364 // CHECK3-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1365 // CHECK3: omp_offload.failed: 1366 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 1367 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1368 // CHECK3: omp_offload.cont: 1369 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 1370 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1371 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1372 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1373 // CHECK3: arraydestroy.body: 1374 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1375 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1376 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1377 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1378 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1379 // CHECK3: arraydestroy.done2: 1380 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1381 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 1382 // CHECK3-NEXT: ret i32 [[TMP4]] 1383 // 1384 // 1385 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1386 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1387 // CHECK3-NEXT: entry: 1388 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1389 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1390 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1391 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 1392 // CHECK3-NEXT: ret void 1393 // 1394 // 1395 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1396 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1397 // CHECK3-NEXT: entry: 1398 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1399 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1400 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1401 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1402 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1403 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1404 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 1405 // CHECK3-NEXT: ret void 1406 // 1407 // 1408 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1409 // CHECK3-SAME: () #[[ATTR4]] { 1410 // CHECK3-NEXT: entry: 1411 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) 1412 // CHECK3-NEXT: ret void 1413 // 1414 // 1415 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 1416 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1417 // CHECK3-NEXT: entry: 1418 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1419 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1420 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1421 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1422 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 1423 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1424 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1425 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1426 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1427 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1428 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1429 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1430 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1431 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 1432 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1433 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1434 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1435 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 1436 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1437 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1438 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1439 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1440 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1441 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1442 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1443 // CHECK3: arrayctor.loop: 1444 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1445 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1446 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 1447 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1448 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1449 // CHECK3: arrayctor.cont: 1450 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) 1451 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 1452 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1453 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1454 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1455 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1456 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1457 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1458 // CHECK3: cond.true: 1459 // CHECK3-NEXT: br label [[COND_END:%.*]] 1460 // CHECK3: cond.false: 1461 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1462 // CHECK3-NEXT: br label [[COND_END]] 1463 // CHECK3: cond.end: 1464 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1465 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1466 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1467 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1468 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1469 // CHECK3: omp.inner.for.cond: 1470 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1471 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1472 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1473 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1474 // CHECK3: omp.inner.for.cond.cleanup: 1475 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1476 // CHECK3: omp.inner.for.body: 1477 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1478 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1479 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1480 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1481 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 1482 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 1483 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] 1484 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 1485 // CHECK3-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 1486 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 1487 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] 1488 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* 1489 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 1490 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) 1491 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1492 // CHECK3: omp.body.continue: 1493 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1494 // CHECK3: omp.inner.for.inc: 1495 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1496 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 1497 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 1498 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1499 // CHECK3: omp.inner.for.end: 1500 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1501 // CHECK3: omp.loop.exit: 1502 // CHECK3-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1503 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 1504 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) 1505 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1506 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1507 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 1508 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1509 // CHECK3: arraydestroy.body: 1510 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1511 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1512 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1513 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 1514 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1515 // CHECK3: arraydestroy.done7: 1516 // CHECK3-NEXT: ret void 1517 // 1518 // 1519 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1520 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1521 // CHECK3-NEXT: entry: 1522 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1523 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1524 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1525 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1526 // CHECK3-NEXT: ret void 1527 // 1528 // 1529 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1530 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1531 // CHECK3-NEXT: entry: 1532 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1533 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1534 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1535 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1536 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1537 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1538 // CHECK3-NEXT: ret void 1539 // 1540 // 1541 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1542 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1543 // CHECK3-NEXT: entry: 1544 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1545 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1546 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1547 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1548 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1549 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1550 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1551 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1552 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1553 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1554 // CHECK3-NEXT: ret void 1555 // 1556 // 1557 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1558 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1559 // CHECK3-NEXT: entry: 1560 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1561 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1562 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1563 // CHECK3-NEXT: ret void 1564 // 1565 // 1566 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp 1567 // CHECK3-SAME: () #[[ATTR0]] { 1568 // CHECK3-NEXT: entry: 1569 // CHECK3-NEXT: call void @__cxx_global_var_init() 1570 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1571 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1572 // CHECK3-NEXT: ret void 1573 // 1574 // 1575 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1576 // CHECK3-SAME: () #[[ATTR0]] { 1577 // CHECK3-NEXT: entry: 1578 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 1579 // CHECK3-NEXT: ret void 1580 // 1581 // 1582 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init 1583 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 1584 // CHECK4-NEXT: entry: 1585 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 1586 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1587 // CHECK4-NEXT: ret void 1588 // 1589 // 1590 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1591 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1592 // CHECK4-NEXT: entry: 1593 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1594 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1595 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1596 // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 1597 // CHECK4-NEXT: ret void 1598 // 1599 // 1600 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1601 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1602 // CHECK4-NEXT: entry: 1603 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1604 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1605 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1606 // CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1607 // CHECK4-NEXT: ret void 1608 // 1609 // 1610 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1611 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1612 // CHECK4-NEXT: entry: 1613 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1614 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1615 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1616 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1617 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1618 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1619 // CHECK4-NEXT: store float [[CONV]], float* [[F]], align 4 1620 // CHECK4-NEXT: ret void 1621 // 1622 // 1623 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1624 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1625 // CHECK4-NEXT: entry: 1626 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1627 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1628 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1629 // CHECK4-NEXT: ret void 1630 // 1631 // 1632 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1633 // CHECK4-SAME: () #[[ATTR0]] { 1634 // CHECK4-NEXT: entry: 1635 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 1636 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 1637 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1638 // CHECK4-NEXT: ret void 1639 // 1640 // 1641 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1642 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1643 // CHECK4-NEXT: entry: 1644 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1645 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1646 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1647 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1648 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1649 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1650 // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 1651 // CHECK4-NEXT: ret void 1652 // 1653 // 1654 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1655 // CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 1656 // CHECK4-NEXT: entry: 1657 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 1658 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 1659 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1660 // CHECK4: arraydestroy.body: 1661 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1662 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1663 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1664 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1665 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1666 // CHECK4: arraydestroy.done1: 1667 // CHECK4-NEXT: ret void 1668 // 1669 // 1670 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1671 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1672 // CHECK4-NEXT: entry: 1673 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1674 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1675 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1676 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1677 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1678 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1679 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1680 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1681 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1682 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1683 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4 1684 // CHECK4-NEXT: ret void 1685 // 1686 // 1687 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1688 // CHECK4-SAME: () #[[ATTR0]] { 1689 // CHECK4-NEXT: entry: 1690 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 1691 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1692 // CHECK4-NEXT: ret void 1693 // 1694 // 1695 // CHECK4-LABEL: define {{[^@]+}}@main 1696 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 1697 // CHECK4-NEXT: entry: 1698 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1699 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 1700 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 1701 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 1702 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 1703 // CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 1704 // CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1705 // CHECK4: omp_offload.failed: 1706 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]] 1707 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 1708 // CHECK4: omp_offload.cont: 1709 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 1710 // CHECK4-NEXT: ret i32 [[CALL]] 1711 // 1712 // 1713 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 1714 // CHECK4-SAME: () #[[ATTR4:[0-9]+]] { 1715 // CHECK4-NEXT: entry: 1716 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 1717 // CHECK4-NEXT: ret void 1718 // 1719 // 1720 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 1721 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1722 // CHECK4-NEXT: entry: 1723 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1724 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1725 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1726 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 1727 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1728 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1729 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1730 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1731 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1732 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1733 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1734 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1735 // CHECK4-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1736 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 1737 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1738 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1739 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1740 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1741 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1742 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1743 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1744 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1745 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1746 // CHECK4: arrayctor.loop: 1747 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1748 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1749 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 1750 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1751 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1752 // CHECK4: arrayctor.cont: 1753 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 1754 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1755 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1756 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1757 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1758 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1759 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1760 // CHECK4: cond.true: 1761 // CHECK4-NEXT: br label [[COND_END:%.*]] 1762 // CHECK4: cond.false: 1763 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1764 // CHECK4-NEXT: br label [[COND_END]] 1765 // CHECK4: cond.end: 1766 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1767 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1768 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1769 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1770 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1771 // CHECK4: omp.inner.for.cond: 1772 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1773 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1774 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1775 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1776 // CHECK4: omp.inner.for.cond.cleanup: 1777 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1778 // CHECK4: omp.inner.for.body: 1779 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1780 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1781 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1782 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1783 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 1784 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 1785 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] 1786 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 1787 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 1788 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP10]] 1789 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 1790 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8* 1791 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false) 1792 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1793 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4 1794 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 1795 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 1796 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1797 // CHECK4: omp.body.continue: 1798 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1799 // CHECK4: omp.inner.for.inc: 1800 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1801 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 1802 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 1803 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 1804 // CHECK4: omp.inner.for.end: 1805 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1806 // CHECK4: omp.loop.exit: 1807 // CHECK4-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1808 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 1809 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) 1810 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1811 // CHECK4-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1812 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 1813 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1814 // CHECK4: arraydestroy.body: 1815 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1816 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1817 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1818 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 1819 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1820 // CHECK4: arraydestroy.done6: 1821 // CHECK4-NEXT: ret void 1822 // 1823 // 1824 // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1825 // CHECK4-SAME: () #[[ATTR6:[0-9]+]] comdat { 1826 // CHECK4-NEXT: entry: 1827 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1828 // CHECK4-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1829 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1830 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1831 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1832 // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 1833 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 1834 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 1835 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 1836 // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 1837 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1838 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1839 // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1840 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 1841 // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 1842 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 1843 // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 1844 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 1845 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 1846 // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 1847 // CHECK4-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 1848 // CHECK4-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1849 // CHECK4: omp_offload.failed: 1850 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 1851 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 1852 // CHECK4: omp_offload.cont: 1853 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 1854 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1855 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1856 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1857 // CHECK4: arraydestroy.body: 1858 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1859 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1860 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1861 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1862 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1863 // CHECK4: arraydestroy.done2: 1864 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1865 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 1866 // CHECK4-NEXT: ret i32 [[TMP4]] 1867 // 1868 // 1869 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1870 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1871 // CHECK4-NEXT: entry: 1872 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1873 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1874 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1875 // CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 1876 // CHECK4-NEXT: ret void 1877 // 1878 // 1879 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1880 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1881 // CHECK4-NEXT: entry: 1882 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1883 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1884 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1885 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1886 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1887 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1888 // CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 1889 // CHECK4-NEXT: ret void 1890 // 1891 // 1892 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1893 // CHECK4-SAME: () #[[ATTR4]] { 1894 // CHECK4-NEXT: entry: 1895 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) 1896 // CHECK4-NEXT: ret void 1897 // 1898 // 1899 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 1900 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1901 // CHECK4-NEXT: entry: 1902 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1903 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1904 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1905 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 1906 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 1907 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1908 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1909 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1910 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1911 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1912 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1913 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1914 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1915 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 1916 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 1917 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1918 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1919 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 1920 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1921 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1922 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1923 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1924 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1925 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1926 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1927 // CHECK4: arrayctor.loop: 1928 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1929 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1930 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 1931 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1932 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1933 // CHECK4: arrayctor.cont: 1934 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) 1935 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 1936 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1937 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1938 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1939 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1940 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1941 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1942 // CHECK4: cond.true: 1943 // CHECK4-NEXT: br label [[COND_END:%.*]] 1944 // CHECK4: cond.false: 1945 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1946 // CHECK4-NEXT: br label [[COND_END]] 1947 // CHECK4: cond.end: 1948 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1949 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1950 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1951 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1952 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1953 // CHECK4: omp.inner.for.cond: 1954 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1955 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1956 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1957 // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1958 // CHECK4: omp.inner.for.cond.cleanup: 1959 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1960 // CHECK4: omp.inner.for.body: 1961 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1962 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1963 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1964 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1965 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 1966 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 1967 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] 1968 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 1969 // CHECK4-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 1970 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 1971 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] 1972 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* 1973 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 1974 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) 1975 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1976 // CHECK4: omp.body.continue: 1977 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1978 // CHECK4: omp.inner.for.inc: 1979 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1980 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 1981 // CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 1982 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 1983 // CHECK4: omp.inner.for.end: 1984 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1985 // CHECK4: omp.loop.exit: 1986 // CHECK4-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1987 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 1988 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) 1989 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1990 // CHECK4-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1991 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 1992 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1993 // CHECK4: arraydestroy.body: 1994 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1995 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1996 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1997 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 1998 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1999 // CHECK4: arraydestroy.done7: 2000 // CHECK4-NEXT: ret void 2001 // 2002 // 2003 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2004 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2005 // CHECK4-NEXT: entry: 2006 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2007 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2008 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2009 // CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2010 // CHECK4-NEXT: ret void 2011 // 2012 // 2013 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2014 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2015 // CHECK4-NEXT: entry: 2016 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2017 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2018 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2019 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2020 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2021 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2022 // CHECK4-NEXT: ret void 2023 // 2024 // 2025 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2026 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2027 // CHECK4-NEXT: entry: 2028 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2029 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2030 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2031 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2032 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2033 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2034 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2035 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2036 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2037 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2038 // CHECK4-NEXT: ret void 2039 // 2040 // 2041 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2042 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2043 // CHECK4-NEXT: entry: 2044 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2045 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2046 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2047 // CHECK4-NEXT: ret void 2048 // 2049 // 2050 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp 2051 // CHECK4-SAME: () #[[ATTR0]] { 2052 // CHECK4-NEXT: entry: 2053 // CHECK4-NEXT: call void @__cxx_global_var_init() 2054 // CHECK4-NEXT: call void @__cxx_global_var_init.1() 2055 // CHECK4-NEXT: call void @__cxx_global_var_init.2() 2056 // CHECK4-NEXT: ret void 2057 // 2058 // 2059 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2060 // CHECK4-SAME: () #[[ATTR0]] { 2061 // CHECK4-NEXT: entry: 2062 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 2063 // CHECK4-NEXT: ret void 2064 // 2065 // 2066 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 2067 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 2068 // CHECK5-NEXT: entry: 2069 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 2070 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2071 // CHECK5-NEXT: ret void 2072 // 2073 // 2074 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2075 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2076 // CHECK5-NEXT: entry: 2077 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2078 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2079 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2080 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 2081 // CHECK5-NEXT: ret void 2082 // 2083 // 2084 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2085 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2086 // CHECK5-NEXT: entry: 2087 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2088 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2089 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2090 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2091 // CHECK5-NEXT: ret void 2092 // 2093 // 2094 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2095 // CHECK5-SAME: () #[[ATTR0]] { 2096 // CHECK5-NEXT: entry: 2097 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 2098 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 2099 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2100 // CHECK5-NEXT: ret void 2101 // 2102 // 2103 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2104 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2105 // CHECK5-NEXT: entry: 2106 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2107 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2108 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2109 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2110 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2111 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2112 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 2113 // CHECK5-NEXT: ret void 2114 // 2115 // 2116 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2117 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 2118 // CHECK5-NEXT: entry: 2119 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2120 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2121 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2122 // CHECK5: arraydestroy.body: 2123 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2124 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2125 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2126 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2127 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2128 // CHECK5: arraydestroy.done1: 2129 // CHECK5-NEXT: ret void 2130 // 2131 // 2132 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2133 // CHECK5-SAME: () #[[ATTR0]] { 2134 // CHECK5-NEXT: entry: 2135 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 2136 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2137 // CHECK5-NEXT: ret void 2138 // 2139 // 2140 // CHECK5-LABEL: define {{[^@]+}}@main 2141 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 2142 // CHECK5-NEXT: entry: 2143 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2144 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2145 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2146 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 2147 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2148 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2149 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2150 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 2151 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2152 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 2153 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2154 // CHECK5: arrayctor.loop: 2155 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2156 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2157 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 2158 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2159 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2160 // CHECK5: arrayctor.cont: 2161 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 2162 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 2163 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 2164 // CHECK5: for.cond: 2165 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 2166 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 2167 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 2168 // CHECK5: for.body: 2169 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 2170 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 2171 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 2172 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 2173 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 2174 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 2175 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 2176 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] 2177 // CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 2178 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* 2179 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) 2180 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 2181 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 2182 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] 2183 // CHECK5-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 2184 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 2185 // CHECK5: for.inc: 2186 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 2187 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 2188 // CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 2189 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 2190 // CHECK5: for.end: 2191 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 2192 // CHECK5-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2193 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 2194 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2195 // CHECK5: arraydestroy.body: 2196 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2197 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2198 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2199 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] 2200 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] 2201 // CHECK5: arraydestroy.done4: 2202 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 2203 // CHECK5-NEXT: ret i32 [[CALL]] 2204 // 2205 // 2206 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2207 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { 2208 // CHECK5-NEXT: entry: 2209 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2210 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2211 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2212 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2213 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2214 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 2215 // CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 2216 // CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 2217 // CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 2218 // CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 2219 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 2220 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2221 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 2222 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 2223 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2224 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 2225 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 2226 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 2227 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 2228 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 2229 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 2230 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2231 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 2232 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2233 // CHECK5: arrayctor.loop: 2234 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2235 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2236 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 2237 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2238 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2239 // CHECK5: arrayctor.cont: 2240 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) 2241 // CHECK5-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 2242 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 2243 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 2244 // CHECK5: for.cond: 2245 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 2246 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 2247 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 2248 // CHECK5: for.body: 2249 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 2250 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 2251 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 2252 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 2253 // CHECK5-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 2254 // CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 2255 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 2256 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 2257 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] 2258 // CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* 2259 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* 2260 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) 2261 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 2262 // CHECK5: for.inc: 2263 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 2264 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 2265 // CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 2266 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 2267 // CHECK5: for.end: 2268 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 2269 // CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2270 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 2271 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2272 // CHECK5: arraydestroy.body: 2273 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2274 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2275 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2276 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 2277 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 2278 // CHECK5: arraydestroy.done8: 2279 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 2280 // CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2281 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 2282 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] 2283 // CHECK5: arraydestroy.body10: 2284 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] 2285 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 2286 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] 2287 // CHECK5-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] 2288 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] 2289 // CHECK5: arraydestroy.done14: 2290 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 2291 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 2292 // CHECK5-NEXT: ret i32 [[TMP11]] 2293 // 2294 // 2295 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2296 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2297 // CHECK5-NEXT: entry: 2298 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2299 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2300 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2301 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2302 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2303 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2304 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 2305 // CHECK5-NEXT: ret void 2306 // 2307 // 2308 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2309 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2310 // CHECK5-NEXT: entry: 2311 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2312 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2313 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2314 // CHECK5-NEXT: ret void 2315 // 2316 // 2317 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2318 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2319 // CHECK5-NEXT: entry: 2320 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2321 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2322 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2323 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2324 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2325 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2326 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2327 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2328 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2329 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2330 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 2331 // CHECK5-NEXT: ret void 2332 // 2333 // 2334 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2335 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2336 // CHECK5-NEXT: entry: 2337 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2338 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2339 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2340 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 2341 // CHECK5-NEXT: ret void 2342 // 2343 // 2344 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2345 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2346 // CHECK5-NEXT: entry: 2347 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2348 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2349 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2350 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2351 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2352 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2353 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 2354 // CHECK5-NEXT: ret void 2355 // 2356 // 2357 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2358 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2359 // CHECK5-NEXT: entry: 2360 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2361 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2362 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2363 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2364 // CHECK5-NEXT: ret void 2365 // 2366 // 2367 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2368 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2369 // CHECK5-NEXT: entry: 2370 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2371 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2372 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2373 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2374 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2375 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2376 // CHECK5-NEXT: ret void 2377 // 2378 // 2379 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2380 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2381 // CHECK5-NEXT: entry: 2382 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2383 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2384 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2385 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2386 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2387 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2388 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2389 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2390 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2391 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2392 // CHECK5-NEXT: ret void 2393 // 2394 // 2395 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2396 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2397 // CHECK5-NEXT: entry: 2398 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2399 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2400 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2401 // CHECK5-NEXT: ret void 2402 // 2403 // 2404 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp 2405 // CHECK5-SAME: () #[[ATTR0]] { 2406 // CHECK5-NEXT: entry: 2407 // CHECK5-NEXT: call void @__cxx_global_var_init() 2408 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 2409 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 2410 // CHECK5-NEXT: ret void 2411 // 2412 // 2413 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init 2414 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { 2415 // CHECK6-NEXT: entry: 2416 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 2417 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2418 // CHECK6-NEXT: ret void 2419 // 2420 // 2421 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2422 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2423 // CHECK6-NEXT: entry: 2424 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2425 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2426 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2427 // CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 2428 // CHECK6-NEXT: ret void 2429 // 2430 // 2431 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2432 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2433 // CHECK6-NEXT: entry: 2434 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2435 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2436 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2437 // CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2438 // CHECK6-NEXT: ret void 2439 // 2440 // 2441 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2442 // CHECK6-SAME: () #[[ATTR0]] { 2443 // CHECK6-NEXT: entry: 2444 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 2445 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 2446 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2447 // CHECK6-NEXT: ret void 2448 // 2449 // 2450 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2451 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2452 // CHECK6-NEXT: entry: 2453 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2454 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2455 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2456 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2457 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2458 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2459 // CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 2460 // CHECK6-NEXT: ret void 2461 // 2462 // 2463 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2464 // CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 2465 // CHECK6-NEXT: entry: 2466 // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2467 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2468 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2469 // CHECK6: arraydestroy.body: 2470 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2471 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2472 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2473 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2474 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2475 // CHECK6: arraydestroy.done1: 2476 // CHECK6-NEXT: ret void 2477 // 2478 // 2479 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2480 // CHECK6-SAME: () #[[ATTR0]] { 2481 // CHECK6-NEXT: entry: 2482 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 2483 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2484 // CHECK6-NEXT: ret void 2485 // 2486 // 2487 // CHECK6-LABEL: define {{[^@]+}}@main 2488 // CHECK6-SAME: () #[[ATTR3:[0-9]+]] { 2489 // CHECK6-NEXT: entry: 2490 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2491 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2492 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2493 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 2494 // CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2495 // CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2496 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 2497 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 2498 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2499 // CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 2500 // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2501 // CHECK6: arrayctor.loop: 2502 // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2503 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2504 // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 2505 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2506 // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2507 // CHECK6: arrayctor.cont: 2508 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 2509 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 2510 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 2511 // CHECK6: for.cond: 2512 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 2513 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 2514 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 2515 // CHECK6: for.body: 2516 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 2517 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 2518 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 2519 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 2520 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 2521 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 2522 // CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 2523 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] 2524 // CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 2525 // CHECK6-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* 2526 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) 2527 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 2528 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 2529 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] 2530 // CHECK6-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 2531 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 2532 // CHECK6: for.inc: 2533 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 2534 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 2535 // CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 2536 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 2537 // CHECK6: for.end: 2538 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 2539 // CHECK6-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2540 // CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 2541 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2542 // CHECK6: arraydestroy.body: 2543 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2544 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2545 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2546 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] 2547 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] 2548 // CHECK6: arraydestroy.done4: 2549 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 2550 // CHECK6-NEXT: ret i32 [[CALL]] 2551 // 2552 // 2553 // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2554 // CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { 2555 // CHECK6-NEXT: entry: 2556 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2557 // CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2558 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2559 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2560 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2561 // CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 2562 // CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 2563 // CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 2564 // CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 2565 // CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 2566 // CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 2567 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 2568 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 2569 // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 2570 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2571 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 2572 // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 2573 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 2574 // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 2575 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 2576 // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 2577 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2578 // CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 2579 // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2580 // CHECK6: arrayctor.loop: 2581 // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2582 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2583 // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 2584 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2585 // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2586 // CHECK6: arrayctor.cont: 2587 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) 2588 // CHECK6-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 2589 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 2590 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 2591 // CHECK6: for.cond: 2592 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 2593 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 2594 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 2595 // CHECK6: for.body: 2596 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 2597 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 2598 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 2599 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 2600 // CHECK6-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 2601 // CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 2602 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 2603 // CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 2604 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] 2605 // CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* 2606 // CHECK6-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* 2607 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) 2608 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 2609 // CHECK6: for.inc: 2610 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 2611 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 2612 // CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 2613 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 2614 // CHECK6: for.end: 2615 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 2616 // CHECK6-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2617 // CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 2618 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2619 // CHECK6: arraydestroy.body: 2620 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2621 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2622 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2623 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 2624 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 2625 // CHECK6: arraydestroy.done8: 2626 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 2627 // CHECK6-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2628 // CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 2629 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] 2630 // CHECK6: arraydestroy.body10: 2631 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] 2632 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 2633 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] 2634 // CHECK6-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] 2635 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] 2636 // CHECK6: arraydestroy.done14: 2637 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 2638 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 2639 // CHECK6-NEXT: ret i32 [[TMP11]] 2640 // 2641 // 2642 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2643 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2644 // CHECK6-NEXT: entry: 2645 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2646 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2647 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2648 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2649 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2650 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2651 // CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 2652 // CHECK6-NEXT: ret void 2653 // 2654 // 2655 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2656 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2657 // CHECK6-NEXT: entry: 2658 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2659 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2660 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2661 // CHECK6-NEXT: ret void 2662 // 2663 // 2664 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2665 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2666 // CHECK6-NEXT: entry: 2667 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2668 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2669 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2670 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2671 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2672 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2673 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2674 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2675 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2676 // CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2677 // CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 2678 // CHECK6-NEXT: ret void 2679 // 2680 // 2681 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2682 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2683 // CHECK6-NEXT: entry: 2684 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2685 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2686 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2687 // CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 2688 // CHECK6-NEXT: ret void 2689 // 2690 // 2691 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2692 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2693 // CHECK6-NEXT: entry: 2694 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2695 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2696 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2697 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2698 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2699 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2700 // CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 2701 // CHECK6-NEXT: ret void 2702 // 2703 // 2704 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2705 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2706 // CHECK6-NEXT: entry: 2707 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2708 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2709 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2710 // CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2711 // CHECK6-NEXT: ret void 2712 // 2713 // 2714 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2715 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2716 // CHECK6-NEXT: entry: 2717 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2718 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2719 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2720 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2721 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2722 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2723 // CHECK6-NEXT: ret void 2724 // 2725 // 2726 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2727 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2728 // CHECK6-NEXT: entry: 2729 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2730 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2731 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2732 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2733 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2734 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2735 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2736 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2737 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2738 // CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2739 // CHECK6-NEXT: ret void 2740 // 2741 // 2742 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2743 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2744 // CHECK6-NEXT: entry: 2745 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2746 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2747 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2748 // CHECK6-NEXT: ret void 2749 // 2750 // 2751 // CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp 2752 // CHECK6-SAME: () #[[ATTR0]] { 2753 // CHECK6-NEXT: entry: 2754 // CHECK6-NEXT: call void @__cxx_global_var_init() 2755 // CHECK6-NEXT: call void @__cxx_global_var_init.1() 2756 // CHECK6-NEXT: call void @__cxx_global_var_init.2() 2757 // CHECK6-NEXT: ret void 2758 // 2759 // 2760 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init 2761 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 2762 // CHECK7-NEXT: entry: 2763 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 2764 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2765 // CHECK7-NEXT: ret void 2766 // 2767 // 2768 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2769 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2770 // CHECK7-NEXT: entry: 2771 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2772 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2773 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2774 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 2775 // CHECK7-NEXT: ret void 2776 // 2777 // 2778 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2779 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2780 // CHECK7-NEXT: entry: 2781 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2782 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2783 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2784 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2785 // CHECK7-NEXT: ret void 2786 // 2787 // 2788 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2789 // CHECK7-SAME: () #[[ATTR0]] { 2790 // CHECK7-NEXT: entry: 2791 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 2792 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 2793 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2794 // CHECK7-NEXT: ret void 2795 // 2796 // 2797 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2798 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2799 // CHECK7-NEXT: entry: 2800 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2801 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2802 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2803 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2804 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2805 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2806 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 2807 // CHECK7-NEXT: ret void 2808 // 2809 // 2810 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2811 // CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 2812 // CHECK7-NEXT: entry: 2813 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 2814 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 2815 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2816 // CHECK7: arraydestroy.body: 2817 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2818 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2819 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2820 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2821 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2822 // CHECK7: arraydestroy.done1: 2823 // CHECK7-NEXT: ret void 2824 // 2825 // 2826 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2827 // CHECK7-SAME: () #[[ATTR0]] { 2828 // CHECK7-NEXT: entry: 2829 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 2830 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2831 // CHECK7-NEXT: ret void 2832 // 2833 // 2834 // CHECK7-LABEL: define {{[^@]+}}@main 2835 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 2836 // CHECK7-NEXT: entry: 2837 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2838 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2839 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2840 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 2841 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2842 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2843 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2844 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 2845 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2846 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 2847 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2848 // CHECK7: arrayctor.loop: 2849 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2850 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2851 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 2852 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2853 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2854 // CHECK7: arrayctor.cont: 2855 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 2856 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 2857 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 2858 // CHECK7: for.cond: 2859 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 2860 // CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 2861 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 2862 // CHECK7: for.body: 2863 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 2864 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 2865 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] 2866 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 2867 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 2868 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] 2869 // CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 2870 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* 2871 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) 2872 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 2873 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 2874 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] 2875 // CHECK7-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 2876 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 2877 // CHECK7: for.inc: 2878 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 2879 // CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 2880 // CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 2881 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 2882 // CHECK7: for.end: 2883 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 2884 // CHECK7-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2885 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 2886 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2887 // CHECK7: arraydestroy.body: 2888 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2889 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2890 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2891 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 2892 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 2893 // CHECK7: arraydestroy.done3: 2894 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 2895 // CHECK7-NEXT: ret i32 [[CALL]] 2896 // 2897 // 2898 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2899 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { 2900 // CHECK7-NEXT: entry: 2901 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2902 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2903 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2904 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2905 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2906 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 2907 // CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 2908 // CHECK7-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 2909 // CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 2910 // CHECK7-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 2911 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 2912 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2913 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 2914 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 2915 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2916 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 2917 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2918 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 2919 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 2920 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 2921 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 2922 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2923 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2924 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2925 // CHECK7: arrayctor.loop: 2926 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2927 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2928 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 2929 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2930 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2931 // CHECK7: arrayctor.cont: 2932 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) 2933 // CHECK7-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 2934 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 2935 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 2936 // CHECK7: for.cond: 2937 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 2938 // CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 2939 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 2940 // CHECK7: for.body: 2941 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 2942 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 2943 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] 2944 // CHECK7-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 2945 // CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2946 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 2947 // CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] 2948 // CHECK7-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* 2949 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* 2950 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) 2951 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 2952 // CHECK7: for.inc: 2953 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 2954 // CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 2955 // CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 2956 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 2957 // CHECK7: for.end: 2958 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 2959 // CHECK7-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2960 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 2961 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2962 // CHECK7: arraydestroy.body: 2963 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2964 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2965 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2966 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 2967 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 2968 // CHECK7: arraydestroy.done7: 2969 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 2970 // CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2971 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 2972 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] 2973 // CHECK7: arraydestroy.body9: 2974 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] 2975 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 2976 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] 2977 // CHECK7-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] 2978 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] 2979 // CHECK7: arraydestroy.done13: 2980 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 2981 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 2982 // CHECK7-NEXT: ret i32 [[TMP11]] 2983 // 2984 // 2985 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2986 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2987 // CHECK7-NEXT: entry: 2988 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2989 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2990 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2991 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2992 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2993 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2994 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 2995 // CHECK7-NEXT: ret void 2996 // 2997 // 2998 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2999 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3000 // CHECK7-NEXT: entry: 3001 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3002 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3003 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3004 // CHECK7-NEXT: ret void 3005 // 3006 // 3007 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3008 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3009 // CHECK7-NEXT: entry: 3010 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3011 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3012 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3013 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3014 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3015 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3016 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3017 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3018 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3019 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3020 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 3021 // CHECK7-NEXT: ret void 3022 // 3023 // 3024 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3025 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3026 // CHECK7-NEXT: entry: 3027 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3028 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3029 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3030 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 3031 // CHECK7-NEXT: ret void 3032 // 3033 // 3034 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3035 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3036 // CHECK7-NEXT: entry: 3037 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3038 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3039 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3040 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3041 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3042 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3043 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 3044 // CHECK7-NEXT: ret void 3045 // 3046 // 3047 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3048 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3049 // CHECK7-NEXT: entry: 3050 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3051 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3052 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3053 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3054 // CHECK7-NEXT: ret void 3055 // 3056 // 3057 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3058 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3059 // CHECK7-NEXT: entry: 3060 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3061 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3062 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3063 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3064 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3065 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3066 // CHECK7-NEXT: ret void 3067 // 3068 // 3069 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3070 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3071 // CHECK7-NEXT: entry: 3072 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3073 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3074 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3075 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3076 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3077 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3078 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3079 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3080 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3081 // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3082 // CHECK7-NEXT: ret void 3083 // 3084 // 3085 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3086 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3087 // CHECK7-NEXT: entry: 3088 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3089 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3090 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3091 // CHECK7-NEXT: ret void 3092 // 3093 // 3094 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp 3095 // CHECK7-SAME: () #[[ATTR0]] { 3096 // CHECK7-NEXT: entry: 3097 // CHECK7-NEXT: call void @__cxx_global_var_init() 3098 // CHECK7-NEXT: call void @__cxx_global_var_init.1() 3099 // CHECK7-NEXT: call void @__cxx_global_var_init.2() 3100 // CHECK7-NEXT: ret void 3101 // 3102 // 3103 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init 3104 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { 3105 // CHECK8-NEXT: entry: 3106 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 3107 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 3108 // CHECK8-NEXT: ret void 3109 // 3110 // 3111 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3112 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3113 // CHECK8-NEXT: entry: 3114 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3115 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3116 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3117 // CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 3118 // CHECK8-NEXT: ret void 3119 // 3120 // 3121 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3122 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3123 // CHECK8-NEXT: entry: 3124 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3125 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3126 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3127 // CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3128 // CHECK8-NEXT: ret void 3129 // 3130 // 3131 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3132 // CHECK8-SAME: () #[[ATTR0]] { 3133 // CHECK8-NEXT: entry: 3134 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 3135 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 3136 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 3137 // CHECK8-NEXT: ret void 3138 // 3139 // 3140 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3141 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3142 // CHECK8-NEXT: entry: 3143 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3144 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3145 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3146 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3147 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3148 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3149 // CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 3150 // CHECK8-NEXT: ret void 3151 // 3152 // 3153 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3154 // CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 3155 // CHECK8-NEXT: entry: 3156 // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 3157 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 3158 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3159 // CHECK8: arraydestroy.body: 3160 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3161 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3162 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3163 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 3164 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3165 // CHECK8: arraydestroy.done1: 3166 // CHECK8-NEXT: ret void 3167 // 3168 // 3169 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3170 // CHECK8-SAME: () #[[ATTR0]] { 3171 // CHECK8-NEXT: entry: 3172 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 3173 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 3174 // CHECK8-NEXT: ret void 3175 // 3176 // 3177 // CHECK8-LABEL: define {{[^@]+}}@main 3178 // CHECK8-SAME: () #[[ATTR3:[0-9]+]] { 3179 // CHECK8-NEXT: entry: 3180 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3181 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3182 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3183 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 3184 // CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 3185 // CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 3186 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 3187 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 3188 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 3189 // CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 3190 // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 3191 // CHECK8: arrayctor.loop: 3192 // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 3193 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 3194 // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 3195 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 3196 // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 3197 // CHECK8: arrayctor.cont: 3198 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 3199 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 3200 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 3201 // CHECK8: for.cond: 3202 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 3203 // CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 3204 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3205 // CHECK8: for.body: 3206 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 3207 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 3208 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] 3209 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 3210 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 3211 // CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] 3212 // CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 3213 // CHECK8-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* 3214 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) 3215 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 3216 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 3217 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] 3218 // CHECK8-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 3219 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 3220 // CHECK8: for.inc: 3221 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 3222 // CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 3223 // CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 3224 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 3225 // CHECK8: for.end: 3226 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 3227 // CHECK8-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 3228 // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 3229 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3230 // CHECK8: arraydestroy.body: 3231 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3232 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3233 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3234 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 3235 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 3236 // CHECK8: arraydestroy.done3: 3237 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 3238 // CHECK8-NEXT: ret i32 [[CALL]] 3239 // 3240 // 3241 // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3242 // CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { 3243 // CHECK8-NEXT: entry: 3244 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3245 // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3246 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3247 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3248 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3249 // CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 3250 // CHECK8-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 3251 // CHECK8-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 3252 // CHECK8-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 3253 // CHECK8-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 3254 // CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 3255 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 3256 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 3257 // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 3258 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3259 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 3260 // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3261 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 3262 // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 3263 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 3264 // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 3265 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3266 // CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 3267 // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 3268 // CHECK8: arrayctor.loop: 3269 // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 3270 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 3271 // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 3272 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 3273 // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 3274 // CHECK8: arrayctor.cont: 3275 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) 3276 // CHECK8-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 3277 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 3278 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 3279 // CHECK8: for.cond: 3280 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 3281 // CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 3282 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3283 // CHECK8: for.body: 3284 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 3285 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 3286 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] 3287 // CHECK8-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 3288 // CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 3289 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 3290 // CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] 3291 // CHECK8-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* 3292 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* 3293 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) 3294 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 3295 // CHECK8: for.inc: 3296 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 3297 // CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 3298 // CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 3299 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 3300 // CHECK8: for.end: 3301 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 3302 // CHECK8-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3303 // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 3304 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3305 // CHECK8: arraydestroy.body: 3306 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3307 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3308 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3309 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 3310 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 3311 // CHECK8: arraydestroy.done7: 3312 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 3313 // CHECK8-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3314 // CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 3315 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] 3316 // CHECK8: arraydestroy.body9: 3317 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] 3318 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 3319 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] 3320 // CHECK8-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] 3321 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] 3322 // CHECK8: arraydestroy.done13: 3323 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 3324 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 3325 // CHECK8-NEXT: ret i32 [[TMP11]] 3326 // 3327 // 3328 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3329 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3330 // CHECK8-NEXT: entry: 3331 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3332 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3333 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3334 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3335 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3336 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3337 // CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 3338 // CHECK8-NEXT: ret void 3339 // 3340 // 3341 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3342 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3343 // CHECK8-NEXT: entry: 3344 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3345 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3346 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3347 // CHECK8-NEXT: ret void 3348 // 3349 // 3350 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3351 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3352 // CHECK8-NEXT: entry: 3353 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3354 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3355 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3356 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3357 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3358 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3359 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3360 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3361 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3362 // CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3363 // CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 3364 // CHECK8-NEXT: ret void 3365 // 3366 // 3367 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3368 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3369 // CHECK8-NEXT: entry: 3370 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3371 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3372 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3373 // CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 3374 // CHECK8-NEXT: ret void 3375 // 3376 // 3377 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3378 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3379 // CHECK8-NEXT: entry: 3380 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3381 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3382 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3383 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3384 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3385 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3386 // CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 3387 // CHECK8-NEXT: ret void 3388 // 3389 // 3390 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3391 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3392 // CHECK8-NEXT: entry: 3393 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3394 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3395 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3396 // CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3397 // CHECK8-NEXT: ret void 3398 // 3399 // 3400 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3401 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3402 // CHECK8-NEXT: entry: 3403 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3404 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3405 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3406 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3407 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3408 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3409 // CHECK8-NEXT: ret void 3410 // 3411 // 3412 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3413 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3414 // CHECK8-NEXT: entry: 3415 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3416 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3417 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3418 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3419 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3420 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3421 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3422 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3423 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3424 // CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3425 // CHECK8-NEXT: ret void 3426 // 3427 // 3428 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3429 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3430 // CHECK8-NEXT: entry: 3431 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3432 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3433 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3434 // CHECK8-NEXT: ret void 3435 // 3436 // 3437 // CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp 3438 // CHECK8-SAME: () #[[ATTR0]] { 3439 // CHECK8-NEXT: entry: 3440 // CHECK8-NEXT: call void @__cxx_global_var_init() 3441 // CHECK8-NEXT: call void @__cxx_global_var_init.1() 3442 // CHECK8-NEXT: call void @__cxx_global_var_init.2() 3443 // CHECK8-NEXT: ret void 3444 // 3445 // 3446 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 3447 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 3448 // CHECK9-NEXT: entry: 3449 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 3450 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 3451 // CHECK9-NEXT: ret void 3452 // 3453 // 3454 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3455 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3456 // CHECK9-NEXT: entry: 3457 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3458 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3459 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3460 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 3461 // CHECK9-NEXT: ret void 3462 // 3463 // 3464 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3465 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3466 // CHECK9-NEXT: entry: 3467 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3468 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3469 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3470 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3471 // CHECK9-NEXT: ret void 3472 // 3473 // 3474 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3475 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3476 // CHECK9-NEXT: entry: 3477 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3478 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3479 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3480 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3481 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3482 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3483 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 3484 // CHECK9-NEXT: ret void 3485 // 3486 // 3487 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3488 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3489 // CHECK9-NEXT: entry: 3490 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3491 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3492 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3493 // CHECK9-NEXT: ret void 3494 // 3495 // 3496 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3497 // CHECK9-SAME: () #[[ATTR0]] { 3498 // CHECK9-NEXT: entry: 3499 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 3500 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 3501 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 3502 // CHECK9-NEXT: ret void 3503 // 3504 // 3505 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3506 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3507 // CHECK9-NEXT: entry: 3508 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3509 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3510 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3511 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3512 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3513 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3514 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 3515 // CHECK9-NEXT: ret void 3516 // 3517 // 3518 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3519 // CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 3520 // CHECK9-NEXT: entry: 3521 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 3522 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 3523 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3524 // CHECK9: arraydestroy.body: 3525 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3526 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3527 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3528 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 3529 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3530 // CHECK9: arraydestroy.done1: 3531 // CHECK9-NEXT: ret void 3532 // 3533 // 3534 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3535 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3536 // CHECK9-NEXT: entry: 3537 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3538 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3539 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3540 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3541 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3542 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3543 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3544 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3545 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3546 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3547 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 3548 // CHECK9-NEXT: ret void 3549 // 3550 // 3551 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3552 // CHECK9-SAME: () #[[ATTR0]] { 3553 // CHECK9-NEXT: entry: 3554 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 3555 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 3556 // CHECK9-NEXT: ret void 3557 // 3558 // 3559 // CHECK9-LABEL: define {{[^@]+}}@main 3560 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 3561 // CHECK9-NEXT: entry: 3562 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3563 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 3564 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 3565 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 3566 // CHECK9-NEXT: ret i32 0 3567 // 3568 // 3569 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 3570 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] { 3571 // CHECK9-NEXT: entry: 3572 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 3573 // CHECK9-NEXT: ret void 3574 // 3575 // 3576 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 3577 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { 3578 // CHECK9-NEXT: entry: 3579 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3580 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3581 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3582 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 3583 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 3584 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3585 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3586 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3587 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3588 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 3589 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 3590 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 3591 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 3592 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 3593 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 3594 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3595 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3596 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8 3597 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3598 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 3599 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3600 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3601 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 3602 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3603 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3604 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3605 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3606 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 3607 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3608 // CHECK9: cond.true: 3609 // CHECK9-NEXT: br label [[COND_END:%.*]] 3610 // CHECK9: cond.false: 3611 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3612 // CHECK9-NEXT: br label [[COND_END]] 3613 // CHECK9: cond.end: 3614 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3615 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3616 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3617 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 3618 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3619 // CHECK9: omp.inner.for.cond: 3620 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3621 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3622 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3623 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3624 // CHECK9: omp.inner.for.body: 3625 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3626 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 3627 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3628 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3629 // CHECK9-NEXT: store i32 1, i32* [[G]], align 4 3630 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8 3631 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 3632 // CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4 3633 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 3634 // CHECK9-NEXT: store i32* [[G]], i32** [[TMP9]], align 8 3635 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 3636 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8 3637 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 3638 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 3639 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 3640 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) 3641 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3642 // CHECK9: omp.body.continue: 3643 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3644 // CHECK9: omp.inner.for.inc: 3645 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3646 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 3647 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 3648 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 3649 // CHECK9: omp.inner.for.end: 3650 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3651 // CHECK9: omp.loop.exit: 3652 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 3653 // CHECK9-NEXT: ret void 3654 // 3655 // 3656 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp 3657 // CHECK9-SAME: () #[[ATTR0]] { 3658 // CHECK9-NEXT: entry: 3659 // CHECK9-NEXT: call void @__cxx_global_var_init() 3660 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 3661 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 3662 // CHECK9-NEXT: ret void 3663 // 3664 // 3665 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3666 // CHECK9-SAME: () #[[ATTR0]] { 3667 // CHECK9-NEXT: entry: 3668 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 3669 // CHECK9-NEXT: ret void 3670 // 3671 // 3672 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init 3673 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 3674 // CHECK10-NEXT: entry: 3675 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 3676 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 3677 // CHECK10-NEXT: ret void 3678 // 3679 // 3680 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3681 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3682 // CHECK10-NEXT: entry: 3683 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3684 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3685 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3686 // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 3687 // CHECK10-NEXT: ret void 3688 // 3689 // 3690 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3691 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3692 // CHECK10-NEXT: entry: 3693 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3694 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3695 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3696 // CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3697 // CHECK10-NEXT: ret void 3698 // 3699 // 3700 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3701 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3702 // CHECK10-NEXT: entry: 3703 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3704 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3705 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3706 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3707 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3708 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3709 // CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 3710 // CHECK10-NEXT: ret void 3711 // 3712 // 3713 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3714 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3715 // CHECK10-NEXT: entry: 3716 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3717 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3718 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3719 // CHECK10-NEXT: ret void 3720 // 3721 // 3722 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3723 // CHECK10-SAME: () #[[ATTR0]] { 3724 // CHECK10-NEXT: entry: 3725 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 3726 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 3727 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 3728 // CHECK10-NEXT: ret void 3729 // 3730 // 3731 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3732 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3733 // CHECK10-NEXT: entry: 3734 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3735 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3736 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3737 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3738 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3739 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3740 // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 3741 // CHECK10-NEXT: ret void 3742 // 3743 // 3744 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3745 // CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 3746 // CHECK10-NEXT: entry: 3747 // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 3748 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 3749 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3750 // CHECK10: arraydestroy.body: 3751 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3752 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3753 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3754 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 3755 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3756 // CHECK10: arraydestroy.done1: 3757 // CHECK10-NEXT: ret void 3758 // 3759 // 3760 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3761 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3762 // CHECK10-NEXT: entry: 3763 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3764 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3765 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3766 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3767 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3768 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3769 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3770 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3771 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3772 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3773 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 3774 // CHECK10-NEXT: ret void 3775 // 3776 // 3777 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3778 // CHECK10-SAME: () #[[ATTR0]] { 3779 // CHECK10-NEXT: entry: 3780 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 3781 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 3782 // CHECK10-NEXT: ret void 3783 // 3784 // 3785 // CHECK10-LABEL: define {{[^@]+}}@main 3786 // CHECK10-SAME: () #[[ATTR3:[0-9]+]] { 3787 // CHECK10-NEXT: entry: 3788 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3789 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 3790 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 3791 // CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 3792 // CHECK10-NEXT: ret i32 0 3793 // 3794 // 3795 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 3796 // CHECK10-SAME: () #[[ATTR5:[0-9]+]] { 3797 // CHECK10-NEXT: entry: 3798 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 3799 // CHECK10-NEXT: ret void 3800 // 3801 // 3802 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 3803 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { 3804 // CHECK10-NEXT: entry: 3805 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3806 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3807 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3808 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 3809 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 3810 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3811 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3812 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3813 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3814 // CHECK10-NEXT: [[G:%.*]] = alloca i32, align 4 3815 // CHECK10-NEXT: [[G1:%.*]] = alloca i32, align 4 3816 // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 3817 // CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 3818 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 3819 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 3820 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3821 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3822 // CHECK10-NEXT: store i32* undef, i32** [[_TMP1]], align 8 3823 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3824 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 3825 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3826 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3827 // CHECK10-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 3828 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3829 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3830 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3831 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3832 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 3833 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3834 // CHECK10: cond.true: 3835 // CHECK10-NEXT: br label [[COND_END:%.*]] 3836 // CHECK10: cond.false: 3837 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3838 // CHECK10-NEXT: br label [[COND_END]] 3839 // CHECK10: cond.end: 3840 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3841 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3842 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3843 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 3844 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3845 // CHECK10: omp.inner.for.cond: 3846 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3847 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3848 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3849 // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3850 // CHECK10: omp.inner.for.body: 3851 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3852 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 3853 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3854 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3855 // CHECK10-NEXT: store i32 1, i32* [[G]], align 4 3856 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8 3857 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 3858 // CHECK10-NEXT: store i32 2, i32* [[SIVAR]], align 4 3859 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 3860 // CHECK10-NEXT: store i32* [[G]], i32** [[TMP9]], align 8 3861 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 3862 // CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8 3863 // CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 3864 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 3865 // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 3866 // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) 3867 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3868 // CHECK10: omp.body.continue: 3869 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3870 // CHECK10: omp.inner.for.inc: 3871 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3872 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 3873 // CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 3874 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 3875 // CHECK10: omp.inner.for.end: 3876 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3877 // CHECK10: omp.loop.exit: 3878 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 3879 // CHECK10-NEXT: ret void 3880 // 3881 // 3882 // CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp 3883 // CHECK10-SAME: () #[[ATTR0]] { 3884 // CHECK10-NEXT: entry: 3885 // CHECK10-NEXT: call void @__cxx_global_var_init() 3886 // CHECK10-NEXT: call void @__cxx_global_var_init.1() 3887 // CHECK10-NEXT: call void @__cxx_global_var_init.2() 3888 // CHECK10-NEXT: ret void 3889 // 3890 // 3891 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3892 // CHECK10-SAME: () #[[ATTR0]] { 3893 // CHECK10-NEXT: entry: 3894 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) 3895 // CHECK10-NEXT: ret void 3896 // 3897 // 3898 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init 3899 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 3900 // CHECK11-NEXT: entry: 3901 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 3902 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 3903 // CHECK11-NEXT: ret void 3904 // 3905 // 3906 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3907 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3908 // CHECK11-NEXT: entry: 3909 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3910 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3911 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3912 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 3913 // CHECK11-NEXT: ret void 3914 // 3915 // 3916 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3917 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3918 // CHECK11-NEXT: entry: 3919 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3920 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3921 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3922 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3923 // CHECK11-NEXT: ret void 3924 // 3925 // 3926 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3927 // CHECK11-SAME: () #[[ATTR0]] { 3928 // CHECK11-NEXT: entry: 3929 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 3930 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 3931 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 3932 // CHECK11-NEXT: ret void 3933 // 3934 // 3935 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3936 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3937 // CHECK11-NEXT: entry: 3938 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3939 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3940 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3941 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3942 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3943 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3944 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 3945 // CHECK11-NEXT: ret void 3946 // 3947 // 3948 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3949 // CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 3950 // CHECK11-NEXT: entry: 3951 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 3952 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 3953 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3954 // CHECK11: arraydestroy.body: 3955 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3956 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3957 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3958 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 3959 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3960 // CHECK11: arraydestroy.done1: 3961 // CHECK11-NEXT: ret void 3962 // 3963 // 3964 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3965 // CHECK11-SAME: () #[[ATTR0]] { 3966 // CHECK11-NEXT: entry: 3967 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 3968 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 3969 // CHECK11-NEXT: ret void 3970 // 3971 // 3972 // CHECK11-LABEL: define {{[^@]+}}@main 3973 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 3974 // CHECK11-NEXT: entry: 3975 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3976 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 3977 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 3978 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 3979 // CHECK11-NEXT: ret i32 0 3980 // 3981 // 3982 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3983 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3984 // CHECK11-NEXT: entry: 3985 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3986 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3987 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3988 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3989 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3990 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3991 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 3992 // CHECK11-NEXT: ret void 3993 // 3994 // 3995 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3996 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3997 // CHECK11-NEXT: entry: 3998 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3999 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4000 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4001 // CHECK11-NEXT: ret void 4002 // 4003 // 4004 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4005 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4006 // CHECK11-NEXT: entry: 4007 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4008 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4009 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4010 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4011 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4012 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4013 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4014 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4015 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4016 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4017 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 4018 // CHECK11-NEXT: ret void 4019 // 4020 // 4021 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp 4022 // CHECK11-SAME: () #[[ATTR0]] { 4023 // CHECK11-NEXT: entry: 4024 // CHECK11-NEXT: call void @__cxx_global_var_init() 4025 // CHECK11-NEXT: call void @__cxx_global_var_init.1() 4026 // CHECK11-NEXT: call void @__cxx_global_var_init.2() 4027 // CHECK11-NEXT: ret void 4028 // 4029 // 4030 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init 4031 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 4032 // CHECK12-NEXT: entry: 4033 // CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 4034 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 4035 // CHECK12-NEXT: ret void 4036 // 4037 // 4038 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4039 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4040 // CHECK12-NEXT: entry: 4041 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4042 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4043 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4044 // CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 4045 // CHECK12-NEXT: ret void 4046 // 4047 // 4048 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4049 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4050 // CHECK12-NEXT: entry: 4051 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4052 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4053 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4054 // CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4055 // CHECK12-NEXT: ret void 4056 // 4057 // 4058 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4059 // CHECK12-SAME: () #[[ATTR0]] { 4060 // CHECK12-NEXT: entry: 4061 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 4062 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 4063 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 4064 // CHECK12-NEXT: ret void 4065 // 4066 // 4067 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4068 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4069 // CHECK12-NEXT: entry: 4070 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4071 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4072 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4073 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4074 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4075 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4076 // CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 4077 // CHECK12-NEXT: ret void 4078 // 4079 // 4080 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 4081 // CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 4082 // CHECK12-NEXT: entry: 4083 // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 4084 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 4085 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4086 // CHECK12: arraydestroy.body: 4087 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4088 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4089 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4090 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 4091 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 4092 // CHECK12: arraydestroy.done1: 4093 // CHECK12-NEXT: ret void 4094 // 4095 // 4096 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 4097 // CHECK12-SAME: () #[[ATTR0]] { 4098 // CHECK12-NEXT: entry: 4099 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 4100 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 4101 // CHECK12-NEXT: ret void 4102 // 4103 // 4104 // CHECK12-LABEL: define {{[^@]+}}@main 4105 // CHECK12-SAME: () #[[ATTR3:[0-9]+]] { 4106 // CHECK12-NEXT: entry: 4107 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4108 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 4109 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 4110 // CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 4111 // CHECK12-NEXT: ret i32 0 4112 // 4113 // 4114 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4115 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4116 // CHECK12-NEXT: entry: 4117 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4118 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4119 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4120 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4121 // CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4122 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4123 // CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 4124 // CHECK12-NEXT: ret void 4125 // 4126 // 4127 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4128 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4129 // CHECK12-NEXT: entry: 4130 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4131 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4132 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4133 // CHECK12-NEXT: ret void 4134 // 4135 // 4136 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4137 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4138 // CHECK12-NEXT: entry: 4139 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4140 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4141 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4142 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4143 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4144 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4145 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4146 // CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4147 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4148 // CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4149 // CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 4150 // CHECK12-NEXT: ret void 4151 // 4152 // 4153 // CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp 4154 // CHECK12-SAME: () #[[ATTR0]] { 4155 // CHECK12-NEXT: entry: 4156 // CHECK12-NEXT: call void @__cxx_global_var_init() 4157 // CHECK12-NEXT: call void @__cxx_global_var_init.1() 4158 // CHECK12-NEXT: call void @__cxx_global_var_init.2() 4159 // CHECK12-NEXT: ret void 4160 // 4161