1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
8
9 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5
12
13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7
14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
15 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7
16 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9
19
20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11
23
24 // expected-no-diagnostics
25 #ifndef HEADER
26 #define HEADER
27
28 template <typename T>
tmain()29 T tmain() {
30 T t_var = T();
31 T vec[] = {1, 2};
32 #pragma omp target teams distribute parallel for simd reduction(+: t_var)
33 for (int i = 0; i < 2; ++i) {
34 t_var += (T) i;
35 }
36 return T();
37 }
38
main()39 int main() {
40 static int sivar;
41 #ifdef LAMBDA
42
43 [&]() {
44 #pragma omp target teams distribute parallel for simd reduction(+: sivar)
45 for (int i = 0; i < 2; ++i) {
46
47 // Skip global and bound tid vars
48
49
50
51 // Skip global and bound tid vars, and prev lb and ub vars
52 // skip loop vars
53
54
55 sivar += i;
56
57 [&]() {
58
59 sivar += 4;
60
61 }();
62 }
63 }();
64 return 0;
65 #else
66 #pragma omp target teams distribute parallel for simd reduction(+: sivar)
67 for (int i = 0; i < 2; ++i) {
68 sivar += i;
69 }
70 return tmain<int>();
71 #endif
72 }
73
74
75
76
77 // Skip global and bound tid vars
78
79
80 // Skip global and bound tid vars, and prev lb and ub
81 // skip loop vars
82
83
84
85
86 // Skip global and bound tid vars
87
88
89 // Skip global and bound tid vars, and prev lb and ub vars
90 // skip loop vars
91
92 #endif
93 // CHECK1-LABEL: define {{[^@]+}}@main
94 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
95 // CHECK1-NEXT: entry:
96 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
97 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
98 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
99 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
100 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
101 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
102 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
103 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to i32**
104 // CHECK1-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP1]], align 8
105 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
106 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32**
107 // CHECK1-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP3]], align 8
108 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
109 // CHECK1-NEXT: store i8* null, i8** [[TMP4]], align 8
110 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
111 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
112 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
113 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
114 // CHECK1-NEXT: store i32 1, i32* [[TMP7]], align 4
115 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
116 // CHECK1-NEXT: store i32 1, i32* [[TMP8]], align 4
117 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
118 // CHECK1-NEXT: store i8** [[TMP5]], i8*** [[TMP9]], align 8
119 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
120 // CHECK1-NEXT: store i8** [[TMP6]], i8*** [[TMP10]], align 8
121 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
122 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP11]], align 8
123 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
124 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP12]], align 8
125 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
126 // CHECK1-NEXT: store i8** null, i8*** [[TMP13]], align 8
127 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
128 // CHECK1-NEXT: store i8** null, i8*** [[TMP14]], align 8
129 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
130 // CHECK1-NEXT: store i64 2, i64* [[TMP15]], align 8
131 // CHECK1-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
132 // CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
133 // CHECK1-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
134 // CHECK1: omp_offload.failed:
135 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66(i32* @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]]
136 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
137 // CHECK1: omp_offload.cont:
138 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
139 // CHECK1-NEXT: ret i32 [[CALL]]
140 //
141 //
142 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66
143 // CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] {
144 // CHECK1-NEXT: entry:
145 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8
146 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8
147 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8
148 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]])
149 // CHECK1-NEXT: ret void
150 //
151 //
152 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
153 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] {
154 // CHECK1-NEXT: entry:
155 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
156 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
157 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8
158 // CHECK1-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4
159 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
160 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
161 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
162 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
163 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
164 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
165 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
166 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8
167 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
168 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
169 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8
170 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8
171 // CHECK1-NEXT: store i32 0, i32* [[SIVAR1]], align 4
172 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
173 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
174 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
175 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
176 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
177 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
178 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
179 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
180 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
181 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
182 // CHECK1: cond.true:
183 // CHECK1-NEXT: br label [[COND_END:%.*]]
184 // CHECK1: cond.false:
185 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
186 // CHECK1-NEXT: br label [[COND_END]]
187 // CHECK1: cond.end:
188 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
189 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
190 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
191 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
192 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
193 // CHECK1: omp.inner.for.cond:
194 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
195 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
196 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
197 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
198 // CHECK1: omp.inner.for.body:
199 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
200 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
201 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
202 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
203 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]), !llvm.access.group !5
204 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
205 // CHECK1: omp.inner.for.inc:
206 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
207 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
208 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
209 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
210 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
211 // CHECK1: omp.inner.for.end:
212 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
213 // CHECK1: omp.loop.exit:
214 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
215 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
216 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
217 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
218 // CHECK1: .omp.final.then:
219 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
220 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
221 // CHECK1: .omp.final.done:
222 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
223 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i32* [[SIVAR1]] to i8*
224 // CHECK1-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8
225 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
226 // CHECK1-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP18]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var)
227 // CHECK1-NEXT: switch i32 [[TMP19]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
228 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
229 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
230 // CHECK1-NEXT: ]
231 // CHECK1: .omp.reduction.case1:
232 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP0]], align 4
233 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR1]], align 4
234 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
235 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[TMP0]], align 4
236 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
237 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
238 // CHECK1: .omp.reduction.case2:
239 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[SIVAR1]], align 4
240 // CHECK1-NEXT: [[TMP23:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP22]] monotonic, align 4
241 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
242 // CHECK1: .omp.reduction.default:
243 // CHECK1-NEXT: ret void
244 //
245 //
246 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
247 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] {
248 // CHECK1-NEXT: entry:
249 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
250 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
251 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
252 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
253 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8
254 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
255 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
256 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
257 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
258 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
259 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
260 // CHECK1-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4
261 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
262 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8
263 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
264 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
265 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
266 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
267 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8
268 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8
269 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
270 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
271 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
272 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
273 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
274 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32
275 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
276 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
277 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
278 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
279 // CHECK1-NEXT: store i32 0, i32* [[SIVAR2]], align 4
280 // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
281 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
282 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
283 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
284 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
285 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
286 // CHECK1: cond.true:
287 // CHECK1-NEXT: br label [[COND_END:%.*]]
288 // CHECK1: cond.false:
289 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
290 // CHECK1-NEXT: br label [[COND_END]]
291 // CHECK1: cond.end:
292 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
293 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
294 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
295 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
296 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
297 // CHECK1: omp.inner.for.cond:
298 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
299 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
300 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
301 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
302 // CHECK1: omp.inner.for.body:
303 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
304 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
305 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
306 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
307 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
308 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4, !llvm.access.group !9
309 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
310 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4, !llvm.access.group !9
311 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
312 // CHECK1: omp.body.continue:
313 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
314 // CHECK1: omp.inner.for.inc:
315 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
316 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1
317 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
318 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
319 // CHECK1: omp.inner.for.end:
320 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
321 // CHECK1: omp.loop.exit:
322 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
323 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
324 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
325 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
326 // CHECK1: .omp.final.then:
327 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
328 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
329 // CHECK1: .omp.final.done:
330 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
331 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i32* [[SIVAR2]] to i8*
332 // CHECK1-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8
333 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
334 // CHECK1-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, i8* [[TMP18]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var)
335 // CHECK1-NEXT: switch i32 [[TMP19]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
336 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
337 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
338 // CHECK1-NEXT: ]
339 // CHECK1: .omp.reduction.case1:
340 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP0]], align 4
341 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR2]], align 4
342 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
343 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[TMP0]], align 4
344 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], [8 x i32]* @.gomp_critical_user_.reduction.var)
345 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
346 // CHECK1: .omp.reduction.case2:
347 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[SIVAR2]], align 4
348 // CHECK1-NEXT: [[TMP23:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP22]] monotonic, align 4
349 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
350 // CHECK1: .omp.reduction.default:
351 // CHECK1-NEXT: ret void
352 //
353 //
354 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
355 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
356 // CHECK1-NEXT: entry:
357 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
358 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8
359 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
360 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8
361 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8
362 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
363 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8
364 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
365 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0
366 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
367 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
368 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0
369 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8
370 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
371 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
372 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
373 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
374 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
375 // CHECK1-NEXT: ret void
376 //
377 //
378 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2
379 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] {
380 // CHECK1-NEXT: entry:
381 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
382 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8
383 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
384 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8
385 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8
386 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
387 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8
388 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
389 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0
390 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
391 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
392 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0
393 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8
394 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
395 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
396 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
397 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
398 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
399 // CHECK1-NEXT: ret void
400 //
401 //
402 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
403 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] comdat {
404 // CHECK1-NEXT: entry:
405 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
406 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
407 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
408 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
409 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
410 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
411 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4
412 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
413 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
414 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
415 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32**
416 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 8
417 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
418 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32**
419 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 8
420 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
421 // CHECK1-NEXT: store i8* null, i8** [[TMP5]], align 8
422 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
423 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
424 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
425 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
426 // CHECK1-NEXT: store i32 1, i32* [[TMP8]], align 4
427 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
428 // CHECK1-NEXT: store i32 1, i32* [[TMP9]], align 4
429 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
430 // CHECK1-NEXT: store i8** [[TMP6]], i8*** [[TMP10]], align 8
431 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
432 // CHECK1-NEXT: store i8** [[TMP7]], i8*** [[TMP11]], align 8
433 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
434 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP12]], align 8
435 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
436 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP13]], align 8
437 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
438 // CHECK1-NEXT: store i8** null, i8*** [[TMP14]], align 8
439 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
440 // CHECK1-NEXT: store i8** null, i8*** [[TMP15]], align 8
441 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
442 // CHECK1-NEXT: store i64 2, i64* [[TMP16]], align 8
443 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB4]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
444 // CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
445 // CHECK1-NEXT: br i1 [[TMP18]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
446 // CHECK1: omp_offload.failed:
447 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32* [[T_VAR]]) #[[ATTR2]]
448 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
449 // CHECK1: omp_offload.cont:
450 // CHECK1-NEXT: ret i32 0
451 //
452 //
453 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32
454 // CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {
455 // CHECK1-NEXT: entry:
456 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
457 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
458 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
459 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[TMP0]])
460 // CHECK1-NEXT: ret void
461 //
462 //
463 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
464 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {
465 // CHECK1-NEXT: entry:
466 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
467 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
468 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
469 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4
470 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
471 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
472 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
473 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
474 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
475 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
476 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
477 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8
478 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
479 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
480 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
481 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
482 // CHECK1-NEXT: store i32 0, i32* [[T_VAR1]], align 4
483 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
484 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
485 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
486 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
487 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
488 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
489 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
490 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
491 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
492 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
493 // CHECK1: cond.true:
494 // CHECK1-NEXT: br label [[COND_END:%.*]]
495 // CHECK1: cond.false:
496 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
497 // CHECK1-NEXT: br label [[COND_END]]
498 // CHECK1: cond.end:
499 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
500 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
501 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
502 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
503 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
504 // CHECK1: omp.inner.for.cond:
505 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
506 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
507 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
508 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
509 // CHECK1: omp.inner.for.body:
510 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
511 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
512 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
513 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
514 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[T_VAR1]]), !llvm.access.group !14
515 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
516 // CHECK1: omp.inner.for.inc:
517 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
518 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14
519 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
520 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
521 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
522 // CHECK1: omp.inner.for.end:
523 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
524 // CHECK1: omp.loop.exit:
525 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
526 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
527 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
528 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
529 // CHECK1: .omp.final.then:
530 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
531 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
532 // CHECK1: .omp.final.done:
533 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
534 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i32* [[T_VAR1]] to i8*
535 // CHECK1-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8
536 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
537 // CHECK1-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP18]], void (i8*, i8*)* @.omp.reduction.reduction_func.6, [8 x i32]* @.gomp_critical_user_.reduction.var)
538 // CHECK1-NEXT: switch i32 [[TMP19]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
539 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
540 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
541 // CHECK1-NEXT: ]
542 // CHECK1: .omp.reduction.case1:
543 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP0]], align 4
544 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[T_VAR1]], align 4
545 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
546 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[TMP0]], align 4
547 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
548 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
549 // CHECK1: .omp.reduction.case2:
550 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR1]], align 4
551 // CHECK1-NEXT: [[TMP23:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP22]] monotonic, align 4
552 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
553 // CHECK1: .omp.reduction.default:
554 // CHECK1-NEXT: ret void
555 //
556 //
557 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
558 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {
559 // CHECK1-NEXT: entry:
560 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
561 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
562 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
563 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
564 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
565 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
566 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
567 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
568 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
569 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
570 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
571 // CHECK1-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
572 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
573 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8
574 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
575 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
576 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
577 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
578 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
579 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
580 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
581 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
582 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
583 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
584 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
585 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32
586 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
587 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
588 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
589 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
590 // CHECK1-NEXT: store i32 0, i32* [[T_VAR2]], align 4
591 // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
592 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
593 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
594 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
595 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
596 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
597 // CHECK1: cond.true:
598 // CHECK1-NEXT: br label [[COND_END:%.*]]
599 // CHECK1: cond.false:
600 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
601 // CHECK1-NEXT: br label [[COND_END]]
602 // CHECK1: cond.end:
603 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
604 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
605 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
606 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
607 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
608 // CHECK1: omp.inner.for.cond:
609 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
610 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17
611 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
612 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
613 // CHECK1: omp.inner.for.body:
614 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
615 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
616 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
617 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
618 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
619 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !17
620 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
621 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[T_VAR2]], align 4, !llvm.access.group !17
622 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
623 // CHECK1: omp.body.continue:
624 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
625 // CHECK1: omp.inner.for.inc:
626 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
627 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1
628 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
629 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
630 // CHECK1: omp.inner.for.end:
631 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
632 // CHECK1: omp.loop.exit:
633 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
634 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
635 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
636 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
637 // CHECK1: .omp.final.then:
638 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
639 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
640 // CHECK1: .omp.final.done:
641 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
642 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i32* [[T_VAR2]] to i8*
643 // CHECK1-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8
644 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
645 // CHECK1-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, i8* [[TMP18]], void (i8*, i8*)* @.omp.reduction.reduction_func.5, [8 x i32]* @.gomp_critical_user_.reduction.var)
646 // CHECK1-NEXT: switch i32 [[TMP19]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
647 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
648 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
649 // CHECK1-NEXT: ]
650 // CHECK1: .omp.reduction.case1:
651 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP0]], align 4
652 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[T_VAR2]], align 4
653 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
654 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[TMP0]], align 4
655 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], [8 x i32]* @.gomp_critical_user_.reduction.var)
656 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
657 // CHECK1: .omp.reduction.case2:
658 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR2]], align 4
659 // CHECK1-NEXT: [[TMP23:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP22]] monotonic, align 4
660 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
661 // CHECK1: .omp.reduction.default:
662 // CHECK1-NEXT: ret void
663 //
664 //
665 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5
666 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] {
667 // CHECK1-NEXT: entry:
668 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
669 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8
670 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
671 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8
672 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8
673 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
674 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8
675 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
676 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0
677 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
678 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
679 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0
680 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8
681 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
682 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
683 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
684 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
685 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
686 // CHECK1-NEXT: ret void
687 //
688 //
689 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6
690 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] {
691 // CHECK1-NEXT: entry:
692 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
693 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8
694 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
695 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8
696 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8
697 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
698 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8
699 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
700 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0
701 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
702 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
703 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0
704 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8
705 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
706 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
707 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
708 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
709 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
710 // CHECK1-NEXT: ret void
711 //
712 //
713 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
714 // CHECK1-SAME: () #[[ATTR7:[0-9]+]] {
715 // CHECK1-NEXT: entry:
716 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
717 // CHECK1-NEXT: ret void
718 //
719 //
720 // CHECK3-LABEL: define {{[^@]+}}@main
721 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
722 // CHECK3-NEXT: entry:
723 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
724 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
725 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
726 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
727 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
728 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
729 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
730 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to i32**
731 // CHECK3-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP1]], align 4
732 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
733 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32**
734 // CHECK3-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP3]], align 4
735 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
736 // CHECK3-NEXT: store i8* null, i8** [[TMP4]], align 4
737 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
738 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
739 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
740 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
741 // CHECK3-NEXT: store i32 1, i32* [[TMP7]], align 4
742 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
743 // CHECK3-NEXT: store i32 1, i32* [[TMP8]], align 4
744 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
745 // CHECK3-NEXT: store i8** [[TMP5]], i8*** [[TMP9]], align 4
746 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
747 // CHECK3-NEXT: store i8** [[TMP6]], i8*** [[TMP10]], align 4
748 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
749 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP11]], align 4
750 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
751 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP12]], align 4
752 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
753 // CHECK3-NEXT: store i8** null, i8*** [[TMP13]], align 4
754 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
755 // CHECK3-NEXT: store i8** null, i8*** [[TMP14]], align 4
756 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
757 // CHECK3-NEXT: store i64 2, i64* [[TMP15]], align 8
758 // CHECK3-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
759 // CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
760 // CHECK3-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
761 // CHECK3: omp_offload.failed:
762 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66(i32* @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]]
763 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
764 // CHECK3: omp_offload.cont:
765 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
766 // CHECK3-NEXT: ret i32 [[CALL]]
767 //
768 //
769 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66
770 // CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] {
771 // CHECK3-NEXT: entry:
772 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4
773 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4
774 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4
775 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]])
776 // CHECK3-NEXT: ret void
777 //
778 //
779 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
780 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] {
781 // CHECK3-NEXT: entry:
782 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
783 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
784 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4
785 // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4
786 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
787 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
788 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
789 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
790 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
791 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
792 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
793 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4
794 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
795 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
796 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4
797 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4
798 // CHECK3-NEXT: store i32 0, i32* [[SIVAR1]], align 4
799 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
800 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
801 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
802 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
803 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
804 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
805 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
806 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
807 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
808 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
809 // CHECK3: cond.true:
810 // CHECK3-NEXT: br label [[COND_END:%.*]]
811 // CHECK3: cond.false:
812 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
813 // CHECK3-NEXT: br label [[COND_END]]
814 // CHECK3: cond.end:
815 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
816 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
817 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
818 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
819 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
820 // CHECK3: omp.inner.for.cond:
821 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
822 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
823 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
824 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
825 // CHECK3: omp.inner.for.body:
826 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
827 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
828 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[SIVAR1]]), !llvm.access.group !6
829 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
830 // CHECK3: omp.inner.for.inc:
831 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
832 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
833 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
834 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
835 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
836 // CHECK3: omp.inner.for.end:
837 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
838 // CHECK3: omp.loop.exit:
839 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
840 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
841 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
842 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
843 // CHECK3: .omp.final.then:
844 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
845 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
846 // CHECK3: .omp.final.done:
847 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0
848 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8*
849 // CHECK3-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 4
850 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
851 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i32 4, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var)
852 // CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
853 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
854 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
855 // CHECK3-NEXT: ]
856 // CHECK3: .omp.reduction.case1:
857 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4
858 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4
859 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
860 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[TMP0]], align 4
861 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
862 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
863 // CHECK3: .omp.reduction.case2:
864 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4
865 // CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4
866 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
867 // CHECK3: .omp.reduction.default:
868 // CHECK3-NEXT: ret void
869 //
870 //
871 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
872 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] {
873 // CHECK3-NEXT: entry:
874 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
875 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
876 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
877 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
878 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4
879 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
880 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
881 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
882 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
883 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
884 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
885 // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4
886 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
887 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4
888 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
889 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
890 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
891 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
892 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4
893 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4
894 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
895 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
896 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
897 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
898 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4
899 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
900 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
901 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
902 // CHECK3-NEXT: store i32 0, i32* [[SIVAR1]], align 4
903 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
904 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
905 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
906 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
907 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
908 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
909 // CHECK3: cond.true:
910 // CHECK3-NEXT: br label [[COND_END:%.*]]
911 // CHECK3: cond.false:
912 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
913 // CHECK3-NEXT: br label [[COND_END]]
914 // CHECK3: cond.end:
915 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
916 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
917 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
918 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
919 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
920 // CHECK3: omp.inner.for.cond:
921 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
922 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
923 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
924 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
925 // CHECK3: omp.inner.for.body:
926 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
927 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
928 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
929 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
930 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
931 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !10
932 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
933 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !10
934 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
935 // CHECK3: omp.body.continue:
936 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
937 // CHECK3: omp.inner.for.inc:
938 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
939 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
940 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
941 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
942 // CHECK3: omp.inner.for.end:
943 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
944 // CHECK3: omp.loop.exit:
945 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
946 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
947 // CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
948 // CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
949 // CHECK3: .omp.final.then:
950 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
951 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
952 // CHECK3: .omp.final.done:
953 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0
954 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i32* [[SIVAR1]] to i8*
955 // CHECK3-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 4
956 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
957 // CHECK3-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, i8* [[TMP18]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var)
958 // CHECK3-NEXT: switch i32 [[TMP19]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
959 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
960 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
961 // CHECK3-NEXT: ]
962 // CHECK3: .omp.reduction.case1:
963 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP0]], align 4
964 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR1]], align 4
965 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
966 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4
967 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], [8 x i32]* @.gomp_critical_user_.reduction.var)
968 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
969 // CHECK3: .omp.reduction.case2:
970 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[SIVAR1]], align 4
971 // CHECK3-NEXT: [[TMP23:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP22]] monotonic, align 4
972 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
973 // CHECK3: .omp.reduction.default:
974 // CHECK3-NEXT: ret void
975 //
976 //
977 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
978 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
979 // CHECK3-NEXT: entry:
980 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
981 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4
982 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
983 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4
984 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4
985 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
986 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4
987 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
988 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0
989 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
990 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
991 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0
992 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4
993 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
994 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
995 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
996 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
997 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
998 // CHECK3-NEXT: ret void
999 //
1000 //
1001 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2
1002 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] {
1003 // CHECK3-NEXT: entry:
1004 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
1005 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4
1006 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
1007 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4
1008 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4
1009 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
1010 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4
1011 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
1012 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0
1013 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
1014 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
1015 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0
1016 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4
1017 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
1018 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
1019 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
1020 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
1021 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
1022 // CHECK3-NEXT: ret void
1023 //
1024 //
1025 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1026 // CHECK3-SAME: () #[[ATTR5:[0-9]+]] comdat {
1027 // CHECK3-NEXT: entry:
1028 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1029 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1030 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
1031 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
1032 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
1033 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1034 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4
1035 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1036 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
1037 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1038 // CHECK3-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32**
1039 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 4
1040 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1041 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32**
1042 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 4
1043 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1044 // CHECK3-NEXT: store i8* null, i8** [[TMP5]], align 4
1045 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1046 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1047 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1048 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1049 // CHECK3-NEXT: store i32 1, i32* [[TMP8]], align 4
1050 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1051 // CHECK3-NEXT: store i32 1, i32* [[TMP9]], align 4
1052 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1053 // CHECK3-NEXT: store i8** [[TMP6]], i8*** [[TMP10]], align 4
1054 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1055 // CHECK3-NEXT: store i8** [[TMP7]], i8*** [[TMP11]], align 4
1056 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1057 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP12]], align 4
1058 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1059 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP13]], align 4
1060 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1061 // CHECK3-NEXT: store i8** null, i8*** [[TMP14]], align 4
1062 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1063 // CHECK3-NEXT: store i8** null, i8*** [[TMP15]], align 4
1064 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1065 // CHECK3-NEXT: store i64 2, i64* [[TMP16]], align 8
1066 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB4]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1067 // CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
1068 // CHECK3-NEXT: br i1 [[TMP18]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1069 // CHECK3: omp_offload.failed:
1070 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32* [[T_VAR]]) #[[ATTR2]]
1071 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1072 // CHECK3: omp_offload.cont:
1073 // CHECK3-NEXT: ret i32 0
1074 //
1075 //
1076 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32
1077 // CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {
1078 // CHECK3-NEXT: entry:
1079 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4
1080 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4
1081 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4
1082 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[TMP0]])
1083 // CHECK3-NEXT: ret void
1084 //
1085 //
1086 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
1087 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {
1088 // CHECK3-NEXT: entry:
1089 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1090 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1091 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4
1092 // CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4
1093 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1094 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1095 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1096 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1097 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1098 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1099 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1100 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4
1101 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1102 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1103 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4
1104 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4
1105 // CHECK3-NEXT: store i32 0, i32* [[T_VAR1]], align 4
1106 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1107 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1108 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1109 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1110 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1111 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
1112 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1113 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1114 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
1115 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1116 // CHECK3: cond.true:
1117 // CHECK3-NEXT: br label [[COND_END:%.*]]
1118 // CHECK3: cond.false:
1119 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1120 // CHECK3-NEXT: br label [[COND_END]]
1121 // CHECK3: cond.end:
1122 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1123 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1124 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1125 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
1126 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1127 // CHECK3: omp.inner.for.cond:
1128 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
1129 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
1130 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
1131 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1132 // CHECK3: omp.inner.for.body:
1133 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
1134 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
1135 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[T_VAR1]]), !llvm.access.group !15
1136 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1137 // CHECK3: omp.inner.for.inc:
1138 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
1139 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
1140 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
1141 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
1142 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
1143 // CHECK3: omp.inner.for.end:
1144 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1145 // CHECK3: omp.loop.exit:
1146 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
1147 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1148 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
1149 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1150 // CHECK3: .omp.final.then:
1151 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
1152 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
1153 // CHECK3: .omp.final.done:
1154 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0
1155 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i32* [[T_VAR1]] to i8*
1156 // CHECK3-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 4
1157 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
1158 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 1, i32 4, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.6, [8 x i32]* @.gomp_critical_user_.reduction.var)
1159 // CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
1160 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
1161 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
1162 // CHECK3-NEXT: ]
1163 // CHECK3: .omp.reduction.case1:
1164 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4
1165 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR1]], align 4
1166 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
1167 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[TMP0]], align 4
1168 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
1169 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
1170 // CHECK3: .omp.reduction.case2:
1171 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[T_VAR1]], align 4
1172 // CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4
1173 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
1174 // CHECK3: .omp.reduction.default:
1175 // CHECK3-NEXT: ret void
1176 //
1177 //
1178 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
1179 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {
1180 // CHECK3-NEXT: entry:
1181 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1182 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1183 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
1184 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
1185 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4
1186 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1187 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1188 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1189 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1190 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1191 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1192 // CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4
1193 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1194 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4
1195 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1196 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1197 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1198 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1199 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4
1200 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4
1201 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1202 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1203 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1204 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1205 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4
1206 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
1207 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1208 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1209 // CHECK3-NEXT: store i32 0, i32* [[T_VAR1]], align 4
1210 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1211 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
1212 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1213 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1214 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
1215 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1216 // CHECK3: cond.true:
1217 // CHECK3-NEXT: br label [[COND_END:%.*]]
1218 // CHECK3: cond.false:
1219 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1220 // CHECK3-NEXT: br label [[COND_END]]
1221 // CHECK3: cond.end:
1222 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
1223 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1224 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1225 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
1226 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1227 // CHECK3: omp.inner.for.cond:
1228 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
1229 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
1230 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
1231 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1232 // CHECK3: omp.inner.for.body:
1233 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
1234 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
1235 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1236 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
1237 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
1238 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !18
1239 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
1240 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !18
1241 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1242 // CHECK3: omp.body.continue:
1243 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1244 // CHECK3: omp.inner.for.inc:
1245 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
1246 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
1247 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
1248 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
1249 // CHECK3: omp.inner.for.end:
1250 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1251 // CHECK3: omp.loop.exit:
1252 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
1253 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1254 // CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
1255 // CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1256 // CHECK3: .omp.final.then:
1257 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
1258 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
1259 // CHECK3: .omp.final.done:
1260 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0
1261 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i32* [[T_VAR1]] to i8*
1262 // CHECK3-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 4
1263 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
1264 // CHECK3-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, i8* [[TMP18]], void (i8*, i8*)* @.omp.reduction.reduction_func.5, [8 x i32]* @.gomp_critical_user_.reduction.var)
1265 // CHECK3-NEXT: switch i32 [[TMP19]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
1266 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
1267 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
1268 // CHECK3-NEXT: ]
1269 // CHECK3: .omp.reduction.case1:
1270 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP0]], align 4
1271 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[T_VAR1]], align 4
1272 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
1273 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4
1274 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], [8 x i32]* @.gomp_critical_user_.reduction.var)
1275 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
1276 // CHECK3: .omp.reduction.case2:
1277 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR1]], align 4
1278 // CHECK3-NEXT: [[TMP23:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP22]] monotonic, align 4
1279 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
1280 // CHECK3: .omp.reduction.default:
1281 // CHECK3-NEXT: ret void
1282 //
1283 //
1284 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5
1285 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] {
1286 // CHECK3-NEXT: entry:
1287 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
1288 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4
1289 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
1290 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4
1291 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4
1292 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
1293 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4
1294 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
1295 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0
1296 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
1297 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
1298 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0
1299 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4
1300 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
1301 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
1302 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
1303 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
1304 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
1305 // CHECK3-NEXT: ret void
1306 //
1307 //
1308 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6
1309 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] {
1310 // CHECK3-NEXT: entry:
1311 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
1312 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4
1313 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
1314 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4
1315 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4
1316 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
1317 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4
1318 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
1319 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0
1320 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
1321 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
1322 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0
1323 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4
1324 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
1325 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
1326 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
1327 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
1328 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
1329 // CHECK3-NEXT: ret void
1330 //
1331 //
1332 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1333 // CHECK3-SAME: () #[[ATTR7:[0-9]+]] {
1334 // CHECK3-NEXT: entry:
1335 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
1336 // CHECK3-NEXT: ret void
1337 //
1338 //
1339 // CHECK5-LABEL: define {{[^@]+}}@main
1340 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
1341 // CHECK5-NEXT: entry:
1342 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1343 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
1344 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
1345 // CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
1346 // CHECK5-NEXT: ret i32 0
1347 //
1348 //
1349 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44
1350 // CHECK5-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] {
1351 // CHECK5-NEXT: entry:
1352 // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8
1353 // CHECK5-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8
1354 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8
1355 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]])
1356 // CHECK5-NEXT: ret void
1357 //
1358 //
1359 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
1360 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] {
1361 // CHECK5-NEXT: entry:
1362 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1363 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1364 // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8
1365 // CHECK5-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4
1366 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1367 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1368 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1369 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1370 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1371 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1372 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1373 // CHECK5-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8
1374 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1375 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1376 // CHECK5-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8
1377 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8
1378 // CHECK5-NEXT: store i32 0, i32* [[SIVAR1]], align 4
1379 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1380 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1381 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1382 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1383 // CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1384 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
1385 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1386 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1387 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
1388 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1389 // CHECK5: cond.true:
1390 // CHECK5-NEXT: br label [[COND_END:%.*]]
1391 // CHECK5: cond.false:
1392 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1393 // CHECK5-NEXT: br label [[COND_END]]
1394 // CHECK5: cond.end:
1395 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1396 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1397 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1398 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
1399 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1400 // CHECK5: omp.inner.for.cond:
1401 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
1402 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
1403 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
1404 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1405 // CHECK5: omp.inner.for.body:
1406 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
1407 // CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
1408 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
1409 // CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
1410 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]), !llvm.access.group !4
1411 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1412 // CHECK5: omp.inner.for.inc:
1413 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
1414 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
1415 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
1416 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
1417 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
1418 // CHECK5: omp.inner.for.end:
1419 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1420 // CHECK5: omp.loop.exit:
1421 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
1422 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1423 // CHECK5-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
1424 // CHECK5-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1425 // CHECK5: .omp.final.then:
1426 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
1427 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
1428 // CHECK5: .omp.final.done:
1429 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
1430 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i32* [[SIVAR1]] to i8*
1431 // CHECK5-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8
1432 // CHECK5-NEXT: [[TMP18:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
1433 // CHECK5-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP18]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var)
1434 // CHECK5-NEXT: switch i32 [[TMP19]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
1435 // CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
1436 // CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
1437 // CHECK5-NEXT: ]
1438 // CHECK5: .omp.reduction.case1:
1439 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP0]], align 4
1440 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR1]], align 4
1441 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
1442 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[TMP0]], align 4
1443 // CHECK5-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
1444 // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
1445 // CHECK5: .omp.reduction.case2:
1446 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[SIVAR1]], align 4
1447 // CHECK5-NEXT: [[TMP23:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP22]] monotonic, align 4
1448 // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
1449 // CHECK5: .omp.reduction.default:
1450 // CHECK5-NEXT: ret void
1451 //
1452 //
1453 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1
1454 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] {
1455 // CHECK5-NEXT: entry:
1456 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1457 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1458 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1459 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1460 // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8
1461 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1462 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1463 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1464 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1465 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1466 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1467 // CHECK5-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4
1468 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1469 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
1470 // CHECK5-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8
1471 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1472 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1473 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1474 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1475 // CHECK5-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8
1476 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8
1477 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1478 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1479 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1480 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
1481 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1482 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32
1483 // CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
1484 // CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
1485 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1486 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1487 // CHECK5-NEXT: store i32 0, i32* [[SIVAR2]], align 4
1488 // CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1489 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
1490 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1491 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1492 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
1493 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1494 // CHECK5: cond.true:
1495 // CHECK5-NEXT: br label [[COND_END:%.*]]
1496 // CHECK5: cond.false:
1497 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1498 // CHECK5-NEXT: br label [[COND_END]]
1499 // CHECK5: cond.end:
1500 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
1501 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1502 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1503 // CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
1504 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1505 // CHECK5: omp.inner.for.cond:
1506 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
1507 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8
1508 // CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
1509 // CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1510 // CHECK5: omp.inner.for.body:
1511 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
1512 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
1513 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1514 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
1515 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
1516 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4, !llvm.access.group !8
1517 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
1518 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4, !llvm.access.group !8
1519 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
1520 // CHECK5-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8, !llvm.access.group !8
1521 // CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !8
1522 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1523 // CHECK5: omp.body.continue:
1524 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1525 // CHECK5: omp.inner.for.inc:
1526 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
1527 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
1528 // CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
1529 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
1530 // CHECK5: omp.inner.for.end:
1531 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1532 // CHECK5: omp.loop.exit:
1533 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
1534 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1535 // CHECK5-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
1536 // CHECK5-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1537 // CHECK5: .omp.final.then:
1538 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
1539 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
1540 // CHECK5: .omp.final.done:
1541 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
1542 // CHECK5-NEXT: [[TMP18:%.*]] = bitcast i32* [[SIVAR2]] to i8*
1543 // CHECK5-NEXT: store i8* [[TMP18]], i8** [[TMP17]], align 8
1544 // CHECK5-NEXT: [[TMP19:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
1545 // CHECK5-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, i8* [[TMP19]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var)
1546 // CHECK5-NEXT: switch i32 [[TMP20]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
1547 // CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
1548 // CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
1549 // CHECK5-NEXT: ]
1550 // CHECK5: .omp.reduction.case1:
1551 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP0]], align 4
1552 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[SIVAR2]], align 4
1553 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
1554 // CHECK5-NEXT: store i32 [[ADD6]], i32* [[TMP0]], align 4
1555 // CHECK5-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], [8 x i32]* @.gomp_critical_user_.reduction.var)
1556 // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
1557 // CHECK5: .omp.reduction.case2:
1558 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR2]], align 4
1559 // CHECK5-NEXT: [[TMP24:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP23]] monotonic, align 4
1560 // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
1561 // CHECK5: .omp.reduction.default:
1562 // CHECK5-NEXT: ret void
1563 //
1564 //
1565 // CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
1566 // CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
1567 // CHECK5-NEXT: entry:
1568 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
1569 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8
1570 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1571 // CHECK5-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8
1572 // CHECK5-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8
1573 // CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
1574 // CHECK5-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8
1575 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
1576 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0
1577 // CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
1578 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
1579 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0
1580 // CHECK5-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8
1581 // CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
1582 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
1583 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
1584 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
1585 // CHECK5-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
1586 // CHECK5-NEXT: ret void
1587 //
1588 //
1589 // CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2
1590 // CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] {
1591 // CHECK5-NEXT: entry:
1592 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
1593 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8
1594 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1595 // CHECK5-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8
1596 // CHECK5-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8
1597 // CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
1598 // CHECK5-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8
1599 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
1600 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0
1601 // CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
1602 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
1603 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0
1604 // CHECK5-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8
1605 // CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
1606 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
1607 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
1608 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
1609 // CHECK5-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
1610 // CHECK5-NEXT: ret void
1611 //
1612 //
1613 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1614 // CHECK5-SAME: () #[[ATTR6:[0-9]+]] {
1615 // CHECK5-NEXT: entry:
1616 // CHECK5-NEXT: call void @__tgt_register_requires(i64 1)
1617 // CHECK5-NEXT: ret void
1618 //
1619 //
1620 // CHECK7-LABEL: define {{[^@]+}}@main
1621 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
1622 // CHECK7-NEXT: entry:
1623 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1624 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
1625 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1626 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1627 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1628 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
1629 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1630 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
1631 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1632 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1633 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1634 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
1635 // CHECK7-NEXT: store i32 0, i32* [[SIVAR]], align 4
1636 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1637 // CHECK7: omp.inner.for.cond:
1638 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1639 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
1640 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1641 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1642 // CHECK7: omp.inner.for.body:
1643 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1644 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1645 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1646 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
1647 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
1648 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2
1649 // CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
1650 // CHECK7-NEXT: store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !2
1651 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1652 // CHECK7: omp.body.continue:
1653 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1654 // CHECK7: omp.inner.for.inc:
1655 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1656 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1
1657 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1658 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
1659 // CHECK7: omp.inner.for.end:
1660 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
1661 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
1662 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4
1663 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]]
1664 // CHECK7-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4
1665 // CHECK7-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
1666 // CHECK7-NEXT: ret i32 [[CALL]]
1667 //
1668 //
1669 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1670 // CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat {
1671 // CHECK7-NEXT: entry:
1672 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1673 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1674 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
1675 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1676 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1677 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1678 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
1679 // CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4
1680 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4
1681 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1682 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
1683 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1684 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1685 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1686 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
1687 // CHECK7-NEXT: store i32 0, i32* [[T_VAR1]], align 4
1688 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1689 // CHECK7: omp.inner.for.cond:
1690 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1691 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
1692 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
1693 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1694 // CHECK7: omp.inner.for.body:
1695 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1696 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
1697 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1698 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
1699 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
1700 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !6
1701 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]]
1702 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !6
1703 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1704 // CHECK7: omp.body.continue:
1705 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1706 // CHECK7: omp.inner.for.inc:
1707 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1708 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1
1709 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1710 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1711 // CHECK7: omp.inner.for.end:
1712 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
1713 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4
1714 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4
1715 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
1716 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[T_VAR]], align 4
1717 // CHECK7-NEXT: ret i32 0
1718 //
1719 //
1720 // CHECK9-LABEL: define {{[^@]+}}@main
1721 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
1722 // CHECK9-NEXT: entry:
1723 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1724 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
1725 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1726 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1727 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1728 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
1729 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1730 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4
1731 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1732 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1733 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1734 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
1735 // CHECK9-NEXT: store i32 0, i32* [[SIVAR]], align 4
1736 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1737 // CHECK9: omp.inner.for.cond:
1738 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1739 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
1740 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1741 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1742 // CHECK9: omp.inner.for.body:
1743 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1744 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1745 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1746 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
1747 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
1748 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3
1749 // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
1750 // CHECK9-NEXT: store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !3
1751 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1752 // CHECK9: omp.body.continue:
1753 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1754 // CHECK9: omp.inner.for.inc:
1755 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1756 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1
1757 // CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1758 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
1759 // CHECK9: omp.inner.for.end:
1760 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4
1761 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
1762 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4
1763 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]]
1764 // CHECK9-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4
1765 // CHECK9-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1766 // CHECK9-NEXT: ret i32 [[CALL]]
1767 //
1768 //
1769 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1770 // CHECK9-SAME: () #[[ATTR1:[0-9]+]] comdat {
1771 // CHECK9-NEXT: entry:
1772 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1773 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1774 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
1775 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1776 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1777 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1778 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
1779 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4
1780 // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4
1781 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1782 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
1783 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1784 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1785 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1786 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
1787 // CHECK9-NEXT: store i32 0, i32* [[T_VAR1]], align 4
1788 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1789 // CHECK9: omp.inner.for.cond:
1790 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
1791 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
1792 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
1793 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1794 // CHECK9: omp.inner.for.body:
1795 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
1796 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
1797 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1798 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
1799 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
1800 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !7
1801 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]]
1802 // CHECK9-NEXT: store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !7
1803 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1804 // CHECK9: omp.body.continue:
1805 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1806 // CHECK9: omp.inner.for.inc:
1807 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
1808 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1
1809 // CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
1810 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
1811 // CHECK9: omp.inner.for.end:
1812 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4
1813 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4
1814 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4
1815 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
1816 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[T_VAR]], align 4
1817 // CHECK9-NEXT: ret i32 0
1818 //
1819 //
1820 // CHECK11-LABEL: define {{[^@]+}}@main
1821 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
1822 // CHECK11-NEXT: entry:
1823 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1824 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
1825 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4
1826 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
1827 // CHECK11-NEXT: ret i32 0
1828 //
1829