1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
8 
9 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5
12 
13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7
14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
15 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7
16 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9
19 
20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11
23 
24 // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region)
25 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
26 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13
27 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
28 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13
29 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
30 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15
31 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
32 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15
33 
34 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
35 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17
36 
37 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
38 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK7
39 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
40 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7
41 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
42 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK9
43 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
44 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9
45 
46 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
47 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK11
48 
49 // expected-no-diagnostics
50 #ifndef HEADER
51 #define HEADER
52 
53 struct St {
54   int a, b;
StSt55   St() : a(0), b(0) {}
StSt56   St(const St &st) : a(st.a + st.b), b(0) {}
~StSt57   ~St() {}
58 };
59 
60 volatile int g = 1212;
61 volatile int &g1 = g;
62 
63 template <class T>
64 struct S {
65   T f;
SS66   S(T a) : f(a + g) {}
SS67   S() : f(g) {}
SS68   S(const S &s, St t = St()) : f(s.f + t.a) {}
operator TS69   operator T() { return T(); }
~SS70   ~S() {}
71 };
72 
73 
74 template <typename T>
tmain()75 T tmain() {
76   S<T> test;
77   T t_var = T();
78   T vec[] = {1, 2};
79   S<T> s_arr[] = {1, 2};
80   S<T> &var = test;
81 #pragma omp target teams distribute parallel for simd firstprivate(t_var, vec, s_arr, var)
82   for (int i = 0; i < 2; ++i) {
83     vec[i] = t_var;
84     s_arr[i] = var;
85   }
86   return T();
87 }
88 
89 S<float> test;
90 int t_var = 333;
91 int vec[] = {1, 2};
92 S<float> s_arr[] = {1, 2};
93 S<float> var(3);
94 
main()95 int main() {
96   static int sivar;
97 #ifdef LAMBDA
98   [&]() {
99 #pragma omp target teams distribute parallel for simd firstprivate(g, g1, sivar)
100   for (int i = 0; i < 2; ++i) {
101 
102     // Skip global and bound tid vars
103     // skip loop vars
104     g = 1;
105     g1 = 1;
106     sivar = 2;
107 
108     // Skip global and bound tid vars, and prev lb and ub vars
109     // skip loop vars
110 
111     // use of private vars
112     [&]() {
113       g = 2;
114       g1 = 2;
115       sivar = 4;
116 
117     }();
118   }
119   }();
120   return 0;
121 #else
122 #pragma omp target teams distribute parallel for simd firstprivate(t_var, vec, s_arr, var, sivar)
123   for (int i = 0; i < 2; ++i) {
124     vec[i] = t_var;
125     s_arr[i] = var;
126     sivar += i;
127   }
128   return tmain<int>();
129 #endif
130 }
131 
132 
133 
134 
135 
136 // Skip global and bound tid vars
137 // Skip temp vars for loop
138 
139 // param copy
140 
141 // T_VAR and SIVAR
142 
143 // preparation vars
144 
145 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
146 
147 // firstprivate(s_arr)
148 
149 // firstprivate(var)
150 
151 
152 // Skip global and bound tid vars, and prev lb ub vars
153 // Skip temp vars for loop
154 
155 // param copy
156 
157 // T_VAR and SIVAR
158 
159 // preparation vars
160 
161 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
162 
163 // firstprivate(s_arr)
164 
165 // firstprivate(var)
166 
167 
168 
169 
170 
171 
172 // Skip global and bound tid vars
173 // Skip temp vars for loop
174 
175 // param copy
176 
177 // T_VAR and preparation variables
178 
179 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
180 
181 // firstprivate(s_arr)
182 
183 // firstprivate(var)
184 
185 
186 // Skip global and bound tid vars
187 // Skip temp vars for loop
188 
189 // param copy
190 
191 // T_VAR and preparation variables
192 
193 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
194 
195 // firstprivate(s_arr)
196 
197 // firstprivate(var)
198 
199 
200 #endif
201 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
202 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
203 // CHECK1-NEXT:  entry:
204 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
205 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
206 // CHECK1-NEXT:    ret void
207 //
208 //
209 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
210 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
211 // CHECK1-NEXT:  entry:
212 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
213 // CHECK1-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
214 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
215 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
216 // CHECK1-NEXT:    ret void
217 //
218 //
219 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
220 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
221 // CHECK1-NEXT:  entry:
222 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
223 // CHECK1-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
224 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
225 // CHECK1-NEXT:    call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
226 // CHECK1-NEXT:    ret void
227 //
228 //
229 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
230 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
231 // CHECK1-NEXT:  entry:
232 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
233 // CHECK1-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
234 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
235 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
236 // CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
237 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
238 // CHECK1-NEXT:    store float [[CONV]], float* [[F]], align 4
239 // CHECK1-NEXT:    ret void
240 //
241 //
242 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
243 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
244 // CHECK1-NEXT:  entry:
245 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
246 // CHECK1-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
247 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
248 // CHECK1-NEXT:    ret void
249 //
250 //
251 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
252 // CHECK1-SAME: () #[[ATTR0]] {
253 // CHECK1-NEXT:  entry:
254 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
255 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
256 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
257 // CHECK1-NEXT:    ret void
258 //
259 //
260 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
261 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
262 // CHECK1-NEXT:  entry:
263 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
264 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
265 // CHECK1-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
266 // CHECK1-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
267 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
268 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
269 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
270 // CHECK1-NEXT:    ret void
271 //
272 //
273 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
274 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
275 // CHECK1-NEXT:  entry:
276 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
277 // CHECK1-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
278 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
279 // CHECK1:       arraydestroy.body:
280 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
281 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
282 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
283 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
284 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
285 // CHECK1:       arraydestroy.done1:
286 // CHECK1-NEXT:    ret void
287 //
288 //
289 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
290 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
291 // CHECK1-NEXT:  entry:
292 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
293 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
294 // CHECK1-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
295 // CHECK1-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
296 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
297 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
298 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
299 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
300 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
301 // CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
302 // CHECK1-NEXT:    store float [[ADD]], float* [[F]], align 4
303 // CHECK1-NEXT:    ret void
304 //
305 //
306 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
307 // CHECK1-SAME: () #[[ATTR0]] {
308 // CHECK1-NEXT:  entry:
309 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
310 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
311 // CHECK1-NEXT:    ret void
312 //
313 //
314 // CHECK1-LABEL: define {{[^@]+}}@main
315 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
316 // CHECK1-NEXT:  entry:
317 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
318 // CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
319 // CHECK1-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8
320 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
321 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
322 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
323 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
324 // CHECK1-NEXT:    store i32 0, i32* [[RETVAL]], align 4
325 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* @t_var, align 4
326 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
327 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
328 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
329 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
330 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
331 // CHECK1-NEXT:    store i32 [[TMP2]], i32* [[CONV1]], align 4
332 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
333 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
334 // CHECK1-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to [2 x i32]**
335 // CHECK1-NEXT:    store [2 x i32]* @vec, [2 x i32]** [[TMP5]], align 8
336 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
337 // CHECK1-NEXT:    [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]**
338 // CHECK1-NEXT:    store [2 x i32]* @vec, [2 x i32]** [[TMP7]], align 8
339 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
340 // CHECK1-NEXT:    store i8* null, i8** [[TMP8]], align 8
341 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
342 // CHECK1-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
343 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
344 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
345 // CHECK1-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
346 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP12]], align 8
347 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
348 // CHECK1-NEXT:    store i8* null, i8** [[TMP13]], align 8
349 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
350 // CHECK1-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]**
351 // CHECK1-NEXT:    store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 8
352 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
353 // CHECK1-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]**
354 // CHECK1-NEXT:    store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 8
355 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
356 // CHECK1-NEXT:    store i8* null, i8** [[TMP18]], align 8
357 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
358 // CHECK1-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S**
359 // CHECK1-NEXT:    store %struct.S* @var, %struct.S** [[TMP20]], align 8
360 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
361 // CHECK1-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S**
362 // CHECK1-NEXT:    store %struct.S* @var, %struct.S** [[TMP22]], align 8
363 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
364 // CHECK1-NEXT:    store i8* null, i8** [[TMP23]], align 8
365 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
366 // CHECK1-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
367 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP25]], align 8
368 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
369 // CHECK1-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
370 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP27]], align 8
371 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
372 // CHECK1-NEXT:    store i8* null, i8** [[TMP28]], align 8
373 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
374 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
375 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
376 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
377 // CHECK1-NEXT:    store i32 1, i32* [[TMP31]], align 4
378 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
379 // CHECK1-NEXT:    store i32 5, i32* [[TMP32]], align 4
380 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
381 // CHECK1-NEXT:    store i8** [[TMP29]], i8*** [[TMP33]], align 8
382 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
383 // CHECK1-NEXT:    store i8** [[TMP30]], i8*** [[TMP34]], align 8
384 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
385 // CHECK1-NEXT:    store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP35]], align 8
386 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
387 // CHECK1-NEXT:    store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP36]], align 8
388 // CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
389 // CHECK1-NEXT:    store i8** null, i8*** [[TMP37]], align 8
390 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
391 // CHECK1-NEXT:    store i8** null, i8*** [[TMP38]], align 8
392 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
393 // CHECK1-NEXT:    store i64 2, i64* [[TMP39]], align 8
394 // CHECK1-NEXT:    [[TMP40:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
395 // CHECK1-NEXT:    [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
396 // CHECK1-NEXT:    br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
397 // CHECK1:       omp_offload.failed:
398 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122([2 x i32]* @vec, i64 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]]
399 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
400 // CHECK1:       omp_offload.cont:
401 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
402 // CHECK1-NEXT:    ret i32 [[CALL]]
403 //
404 //
405 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122
406 // CHECK1-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
407 // CHECK1-NEXT:  entry:
408 // CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
409 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
410 // CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
411 // CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
412 // CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
413 // CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
414 // CHECK1-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8
415 // CHECK1-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
416 // CHECK1-NEXT:    store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
417 // CHECK1-NEXT:    store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
418 // CHECK1-NEXT:    store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
419 // CHECK1-NEXT:    store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
420 // CHECK1-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
421 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
422 // CHECK1-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
423 // CHECK1-NEXT:    [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
424 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
425 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
426 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
427 // CHECK1-NEXT:    store i32 [[TMP3]], i32* [[CONV2]], align 4
428 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
429 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
430 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
431 // CHECK1-NEXT:    store i32 [[TMP5]], i32* [[CONV3]], align 4
432 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
433 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
434 // CHECK1-NEXT:    ret void
435 //
436 //
437 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
438 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {
439 // CHECK1-NEXT:  entry:
440 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
441 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
442 // CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
443 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
444 // CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
445 // CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
446 // CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
447 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
448 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
449 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
450 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
451 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
452 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
453 // CHECK1-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 4
454 // CHECK1-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4
455 // CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
456 // CHECK1-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
457 // CHECK1-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
458 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
459 // CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
460 // CHECK1-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8
461 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
462 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
463 // CHECK1-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
464 // CHECK1-NEXT:    store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
465 // CHECK1-NEXT:    store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
466 // CHECK1-NEXT:    store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
467 // CHECK1-NEXT:    store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
468 // CHECK1-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
469 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
470 // CHECK1-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
471 // CHECK1-NEXT:    [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
472 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
473 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
474 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
475 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
476 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
477 // CHECK1-NEXT:    [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
478 // CHECK1-NEXT:    [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
479 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
480 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
481 // CHECK1-NEXT:    [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
482 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
483 // CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
484 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
485 // CHECK1:       omp.arraycpy.body:
486 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
487 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
488 // CHECK1-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
489 // CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]])
490 // CHECK1-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
491 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
492 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
493 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
494 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
495 // CHECK1:       omp.arraycpy.done4:
496 // CHECK1-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
497 // CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]])
498 // CHECK1-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
499 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
500 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
501 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
502 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
503 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
504 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
505 // CHECK1:       cond.true:
506 // CHECK1-NEXT:    br label [[COND_END:%.*]]
507 // CHECK1:       cond.false:
508 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
509 // CHECK1-NEXT:    br label [[COND_END]]
510 // CHECK1:       cond.end:
511 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
512 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
513 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
514 // CHECK1-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
515 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
516 // CHECK1:       omp.inner.for.cond:
517 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
518 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
519 // CHECK1-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
520 // CHECK1-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
521 // CHECK1:       omp.inner.for.cond.cleanup:
522 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
523 // CHECK1:       omp.inner.for.body:
524 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
525 // CHECK1-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
526 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
527 // CHECK1-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
528 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
529 // CHECK1-NEXT:    [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
530 // CHECK1-NEXT:    store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5
531 // CHECK1-NEXT:    [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5
532 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5
533 // CHECK1-NEXT:    [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
534 // CHECK1-NEXT:    store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5
535 // CHECK1-NEXT:    [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5
536 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5
537 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
538 // CHECK1:       omp.inner.for.inc:
539 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
540 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
541 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
542 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
543 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
544 // CHECK1:       omp.inner.for.end:
545 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
546 // CHECK1:       omp.loop.exit:
547 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
548 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4
549 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]])
550 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
551 // CHECK1-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
552 // CHECK1-NEXT:    br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
553 // CHECK1:       .omp.final.then:
554 // CHECK1-NEXT:    store i32 2, i32* [[I]], align 4
555 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
556 // CHECK1:       .omp.final.done:
557 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
558 // CHECK1-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
559 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2
560 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
561 // CHECK1:       arraydestroy.body:
562 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
563 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
564 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
565 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
566 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
567 // CHECK1:       arraydestroy.done11:
568 // CHECK1-NEXT:    ret void
569 //
570 //
571 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
572 // CHECK1-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
573 // CHECK1-NEXT:  entry:
574 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
575 // CHECK1-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
576 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
577 // CHECK1-NEXT:    call void @_ZN2StC2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]])
578 // CHECK1-NEXT:    ret void
579 //
580 //
581 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
582 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
583 // CHECK1-NEXT:  entry:
584 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
585 // CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca %struct.S*, align 8
586 // CHECK1-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
587 // CHECK1-NEXT:    store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
588 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
589 // CHECK1-NEXT:    [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
590 // CHECK1-NEXT:    call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]])
591 // CHECK1-NEXT:    ret void
592 //
593 //
594 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
595 // CHECK1-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
596 // CHECK1-NEXT:  entry:
597 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
598 // CHECK1-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
599 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
600 // CHECK1-NEXT:    call void @_ZN2StD2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
601 // CHECK1-NEXT:    ret void
602 //
603 //
604 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
605 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {
606 // CHECK1-NEXT:  entry:
607 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
608 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
609 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
610 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
611 // CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
612 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
613 // CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
614 // CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
615 // CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
616 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
617 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
618 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
619 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
620 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
621 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
622 // CHECK1-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 4
623 // CHECK1-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4
624 // CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
625 // CHECK1-NEXT:    [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4
626 // CHECK1-NEXT:    [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
627 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
628 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
629 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
630 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
631 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
632 // CHECK1-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
633 // CHECK1-NEXT:    store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
634 // CHECK1-NEXT:    store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
635 // CHECK1-NEXT:    store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
636 // CHECK1-NEXT:    store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
637 // CHECK1-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
638 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
639 // CHECK1-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
640 // CHECK1-NEXT:    [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
641 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
642 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
643 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
644 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
645 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
646 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
647 // CHECK1-NEXT:    [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
648 // CHECK1-NEXT:    store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
649 // CHECK1-NEXT:    store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
650 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
651 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
652 // CHECK1-NEXT:    [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
653 // CHECK1-NEXT:    [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
654 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false)
655 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
656 // CHECK1-NEXT:    [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
657 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
658 // CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]]
659 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
660 // CHECK1:       omp.arraycpy.body:
661 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
662 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
663 // CHECK1-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
664 // CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]])
665 // CHECK1-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
666 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
667 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
668 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
669 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
670 // CHECK1:       omp.arraycpy.done6:
671 // CHECK1-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]])
672 // CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP8]])
673 // CHECK1-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]]
674 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
675 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
676 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
677 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
678 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1
679 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
680 // CHECK1:       cond.true:
681 // CHECK1-NEXT:    br label [[COND_END:%.*]]
682 // CHECK1:       cond.false:
683 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
684 // CHECK1-NEXT:    br label [[COND_END]]
685 // CHECK1:       cond.end:
686 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
687 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
688 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
689 // CHECK1-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
690 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
691 // CHECK1:       omp.inner.for.cond:
692 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
693 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
694 // CHECK1-NEXT:    [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
695 // CHECK1-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
696 // CHECK1:       omp.inner.for.cond.cleanup:
697 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
698 // CHECK1:       omp.inner.for.body:
699 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
700 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
701 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
702 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
703 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
704 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
705 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
706 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
707 // CHECK1-NEXT:    store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
708 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
709 // CHECK1-NEXT:    [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
710 // CHECK1-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
711 // CHECK1-NEXT:    [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
712 // CHECK1-NEXT:    [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
713 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9
714 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
715 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !9
716 // CHECK1-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
717 // CHECK1-NEXT:    store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !9
718 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
719 // CHECK1:       omp.body.continue:
720 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
721 // CHECK1:       omp.inner.for.inc:
722 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
723 // CHECK1-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
724 // CHECK1-NEXT:    store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
725 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
726 // CHECK1:       omp.inner.for.end:
727 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
728 // CHECK1:       omp.loop.exit:
729 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
730 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
731 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
732 // CHECK1-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
733 // CHECK1-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
734 // CHECK1-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
735 // CHECK1:       .omp.final.then:
736 // CHECK1-NEXT:    store i32 2, i32* [[I]], align 4
737 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
738 // CHECK1:       .omp.final.done:
739 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]]
740 // CHECK1-NEXT:    [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
741 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2
742 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
743 // CHECK1:       arraydestroy.body:
744 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
745 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
746 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
747 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
748 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
749 // CHECK1:       arraydestroy.done15:
750 // CHECK1-NEXT:    ret void
751 //
752 //
753 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
754 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat {
755 // CHECK1-NEXT:  entry:
756 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
757 // CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
758 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
759 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
760 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
761 // CHECK1-NEXT:    [[VAR:%.*]] = alloca %struct.S.0*, align 8
762 // CHECK1-NEXT:    [[TMP:%.*]] = alloca %struct.S.0*, align 8
763 // CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
764 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
765 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
766 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
767 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
768 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
769 // CHECK1-NEXT:    store i32 0, i32* [[T_VAR]], align 4
770 // CHECK1-NEXT:    [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
771 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
772 // CHECK1-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
773 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
774 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
775 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
776 // CHECK1-NEXT:    store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
777 // CHECK1-NEXT:    [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
778 // CHECK1-NEXT:    store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8
779 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
780 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
781 // CHECK1-NEXT:    store i32 [[TMP2]], i32* [[CONV]], align 4
782 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
783 // CHECK1-NEXT:    [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
784 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
785 // CHECK1-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]**
786 // CHECK1-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 8
787 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
788 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]**
789 // CHECK1-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8
790 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
791 // CHECK1-NEXT:    store i8* null, i8** [[TMP9]], align 8
792 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
793 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
794 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
795 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
796 // CHECK1-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
797 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
798 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
799 // CHECK1-NEXT:    store i8* null, i8** [[TMP14]], align 8
800 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
801 // CHECK1-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]**
802 // CHECK1-NEXT:    store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 8
803 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
804 // CHECK1-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
805 // CHECK1-NEXT:    store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8
806 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
807 // CHECK1-NEXT:    store i8* null, i8** [[TMP19]], align 8
808 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
809 // CHECK1-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0**
810 // CHECK1-NEXT:    store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 8
811 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
812 // CHECK1-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
813 // CHECK1-NEXT:    store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 8
814 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
815 // CHECK1-NEXT:    store i8* null, i8** [[TMP24]], align 8
816 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
817 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
818 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
819 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
820 // CHECK1-NEXT:    store i32 1, i32* [[TMP27]], align 4
821 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
822 // CHECK1-NEXT:    store i32 4, i32* [[TMP28]], align 4
823 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
824 // CHECK1-NEXT:    store i8** [[TMP25]], i8*** [[TMP29]], align 8
825 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
826 // CHECK1-NEXT:    store i8** [[TMP26]], i8*** [[TMP30]], align 8
827 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
828 // CHECK1-NEXT:    store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.6, i32 0, i32 0), i64** [[TMP31]], align 8
829 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
830 // CHECK1-NEXT:    store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i64** [[TMP32]], align 8
831 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
832 // CHECK1-NEXT:    store i8** null, i8*** [[TMP33]], align 8
833 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
834 // CHECK1-NEXT:    store i8** null, i8*** [[TMP34]], align 8
835 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
836 // CHECK1-NEXT:    store i64 2, i64* [[TMP35]], align 8
837 // CHECK1-NEXT:    [[TMP36:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
838 // CHECK1-NEXT:    [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0
839 // CHECK1-NEXT:    br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
840 // CHECK1:       omp_offload.failed:
841 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]]
842 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
843 // CHECK1:       omp_offload.cont:
844 // CHECK1-NEXT:    store i32 0, i32* [[RETVAL]], align 4
845 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
846 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
847 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
848 // CHECK1:       arraydestroy.body:
849 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
850 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
851 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
852 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
853 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
854 // CHECK1:       arraydestroy.done2:
855 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
856 // CHECK1-NEXT:    [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4
857 // CHECK1-NEXT:    ret i32 [[TMP39]]
858 //
859 //
860 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
861 // CHECK1-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
862 // CHECK1-NEXT:  entry:
863 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
864 // CHECK1-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
865 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
866 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
867 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
868 // CHECK1-NEXT:    [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
869 // CHECK1-NEXT:    store i32 0, i32* [[B]], align 4
870 // CHECK1-NEXT:    ret void
871 //
872 //
873 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
874 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
875 // CHECK1-NEXT:  entry:
876 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
877 // CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca %struct.S*, align 8
878 // CHECK1-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
879 // CHECK1-NEXT:    store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
880 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
881 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
882 // CHECK1-NEXT:    [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
883 // CHECK1-NEXT:    [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
884 // CHECK1-NEXT:    [[TMP1:%.*]] = load float, float* [[F2]], align 4
885 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
886 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
887 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
888 // CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
889 // CHECK1-NEXT:    store float [[ADD]], float* [[F]], align 4
890 // CHECK1-NEXT:    ret void
891 //
892 //
893 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
894 // CHECK1-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
895 // CHECK1-NEXT:  entry:
896 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
897 // CHECK1-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
898 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
899 // CHECK1-NEXT:    ret void
900 //
901 //
902 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
903 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
904 // CHECK1-NEXT:  entry:
905 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
906 // CHECK1-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
907 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
908 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
909 // CHECK1-NEXT:    ret void
910 //
911 //
912 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
913 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
914 // CHECK1-NEXT:  entry:
915 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
916 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
917 // CHECK1-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
918 // CHECK1-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
919 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
920 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
921 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
922 // CHECK1-NEXT:    ret void
923 //
924 //
925 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81
926 // CHECK1-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
927 // CHECK1-NEXT:  entry:
928 // CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
929 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
930 // CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
931 // CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
932 // CHECK1-NEXT:    [[TMP:%.*]] = alloca %struct.S.0*, align 8
933 // CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
934 // CHECK1-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
935 // CHECK1-NEXT:    store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
936 // CHECK1-NEXT:    store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
937 // CHECK1-NEXT:    store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
938 // CHECK1-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
939 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
940 // CHECK1-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
941 // CHECK1-NEXT:    [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
942 // CHECK1-NEXT:    store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
943 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
944 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
945 // CHECK1-NEXT:    store i32 [[TMP3]], i32* [[CONV1]], align 4
946 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
947 // CHECK1-NEXT:    [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
948 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
949 // CHECK1-NEXT:    ret void
950 //
951 //
952 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
953 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
954 // CHECK1-NEXT:  entry:
955 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
956 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
957 // CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
958 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
959 // CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
960 // CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
961 // CHECK1-NEXT:    [[TMP:%.*]] = alloca %struct.S.0*, align 8
962 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
963 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
964 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
965 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
966 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
967 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
968 // CHECK1-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 4
969 // CHECK1-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
970 // CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
971 // CHECK1-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
972 // CHECK1-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
973 // CHECK1-NEXT:    [[_TMP7:%.*]] = alloca %struct.S.0*, align 8
974 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
975 // CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
976 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
977 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
978 // CHECK1-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
979 // CHECK1-NEXT:    store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
980 // CHECK1-NEXT:    store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
981 // CHECK1-NEXT:    store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
982 // CHECK1-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
983 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
984 // CHECK1-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
985 // CHECK1-NEXT:    [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
986 // CHECK1-NEXT:    store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
987 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
988 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
989 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
990 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
991 // CHECK1-NEXT:    [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
992 // CHECK1-NEXT:    [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
993 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
994 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
995 // CHECK1-NEXT:    [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
996 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
997 // CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
998 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
999 // CHECK1:       omp.arraycpy.body:
1000 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1001 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1002 // CHECK1-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1003 // CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]])
1004 // CHECK1-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1005 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1006 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1007 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
1008 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
1009 // CHECK1:       omp.arraycpy.done4:
1010 // CHECK1-NEXT:    [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1011 // CHECK1-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
1012 // CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]])
1013 // CHECK1-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
1014 // CHECK1-NEXT:    store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8
1015 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1016 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
1017 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1018 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1019 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
1020 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1021 // CHECK1:       cond.true:
1022 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1023 // CHECK1:       cond.false:
1024 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1025 // CHECK1-NEXT:    br label [[COND_END]]
1026 // CHECK1:       cond.end:
1027 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
1028 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1029 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1030 // CHECK1-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
1031 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1032 // CHECK1:       omp.inner.for.cond:
1033 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
1034 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
1035 // CHECK1-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
1036 // CHECK1-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1037 // CHECK1:       omp.inner.for.cond.cleanup:
1038 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1039 // CHECK1:       omp.inner.for.body:
1040 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
1041 // CHECK1-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
1042 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
1043 // CHECK1-NEXT:    [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
1044 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !14
1045 // CHECK1-NEXT:    [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1046 // CHECK1-NEXT:    store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14
1047 // CHECK1-NEXT:    [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14
1048 // CHECK1-NEXT:    [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14
1049 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14
1050 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1051 // CHECK1:       omp.inner.for.inc:
1052 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
1053 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14
1054 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
1055 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
1056 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
1057 // CHECK1:       omp.inner.for.end:
1058 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1059 // CHECK1:       omp.loop.exit:
1060 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1061 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4
1062 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]])
1063 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1064 // CHECK1-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
1065 // CHECK1-NEXT:    br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1066 // CHECK1:       .omp.final.then:
1067 // CHECK1-NEXT:    store i32 2, i32* [[I]], align 4
1068 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1069 // CHECK1:       .omp.final.done:
1070 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1071 // CHECK1-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
1072 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2
1073 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1074 // CHECK1:       arraydestroy.body:
1075 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1076 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1077 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1078 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1079 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1080 // CHECK1:       arraydestroy.done11:
1081 // CHECK1-NEXT:    ret void
1082 //
1083 //
1084 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
1085 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1086 // CHECK1-NEXT:  entry:
1087 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1088 // CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
1089 // CHECK1-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1090 // CHECK1-NEXT:    store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
1091 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1092 // CHECK1-NEXT:    [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
1093 // CHECK1-NEXT:    call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]])
1094 // CHECK1-NEXT:    ret void
1095 //
1096 //
1097 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5
1098 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
1099 // CHECK1-NEXT:  entry:
1100 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1101 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1102 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1103 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1104 // CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1105 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1106 // CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
1107 // CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
1108 // CHECK1-NEXT:    [[TMP:%.*]] = alloca %struct.S.0*, align 8
1109 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1110 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1111 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1112 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1113 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1114 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1115 // CHECK1-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 4
1116 // CHECK1-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4
1117 // CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1118 // CHECK1-NEXT:    [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1119 // CHECK1-NEXT:    [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
1120 // CHECK1-NEXT:    [[_TMP9:%.*]] = alloca %struct.S.0*, align 8
1121 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1122 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1123 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1124 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1125 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1126 // CHECK1-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1127 // CHECK1-NEXT:    store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1128 // CHECK1-NEXT:    store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1129 // CHECK1-NEXT:    store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
1130 // CHECK1-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1131 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1132 // CHECK1-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1133 // CHECK1-NEXT:    [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
1134 // CHECK1-NEXT:    store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
1135 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1136 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
1137 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1138 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
1139 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1140 // CHECK1-NEXT:    [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
1141 // CHECK1-NEXT:    store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
1142 // CHECK1-NEXT:    store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
1143 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1144 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1145 // CHECK1-NEXT:    [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
1146 // CHECK1-NEXT:    [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1147 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false)
1148 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
1149 // CHECK1-NEXT:    [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
1150 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1151 // CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
1152 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1153 // CHECK1:       omp.arraycpy.body:
1154 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1155 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1156 // CHECK1-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1157 // CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]])
1158 // CHECK1-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1159 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1160 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1161 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
1162 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
1163 // CHECK1:       omp.arraycpy.done6:
1164 // CHECK1-NEXT:    [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1165 // CHECK1-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]])
1166 // CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP8]])
1167 // CHECK1-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]]
1168 // CHECK1-NEXT:    store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8
1169 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1170 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
1171 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1172 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1173 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
1174 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1175 // CHECK1:       cond.true:
1176 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1177 // CHECK1:       cond.false:
1178 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1179 // CHECK1-NEXT:    br label [[COND_END]]
1180 // CHECK1:       cond.end:
1181 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
1182 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1183 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1184 // CHECK1-NEXT:    store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
1185 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1186 // CHECK1:       omp.inner.for.cond:
1187 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
1188 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17
1189 // CHECK1-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
1190 // CHECK1-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1191 // CHECK1:       omp.inner.for.cond.cleanup:
1192 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1193 // CHECK1:       omp.inner.for.body:
1194 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
1195 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
1196 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1197 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
1198 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !17
1199 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
1200 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
1201 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
1202 // CHECK1-NEXT:    store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
1203 // CHECK1-NEXT:    [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17
1204 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
1205 // CHECK1-NEXT:    [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
1206 // CHECK1-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
1207 // CHECK1-NEXT:    [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8*
1208 // CHECK1-NEXT:    [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8*
1209 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false), !llvm.access.group !17
1210 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1211 // CHECK1:       omp.body.continue:
1212 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1213 // CHECK1:       omp.inner.for.inc:
1214 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
1215 // CHECK1-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
1216 // CHECK1-NEXT:    store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
1217 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
1218 // CHECK1:       omp.inner.for.end:
1219 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1220 // CHECK1:       omp.loop.exit:
1221 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1222 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
1223 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
1224 // CHECK1-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1225 // CHECK1-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
1226 // CHECK1-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1227 // CHECK1:       .omp.final.then:
1228 // CHECK1-NEXT:    store i32 2, i32* [[I]], align 4
1229 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1230 // CHECK1:       .omp.final.done:
1231 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]]
1232 // CHECK1-NEXT:    [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
1233 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2
1234 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1235 // CHECK1:       arraydestroy.body:
1236 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1237 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1238 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1239 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
1240 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
1241 // CHECK1:       arraydestroy.done15:
1242 // CHECK1-NEXT:    ret void
1243 //
1244 //
1245 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1246 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1247 // CHECK1-NEXT:  entry:
1248 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1249 // CHECK1-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1250 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1251 // CHECK1-NEXT:    call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1252 // CHECK1-NEXT:    ret void
1253 //
1254 //
1255 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1256 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1257 // CHECK1-NEXT:  entry:
1258 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1259 // CHECK1-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1260 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1261 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1262 // CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1263 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[F]], align 4
1264 // CHECK1-NEXT:    ret void
1265 //
1266 //
1267 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1268 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1269 // CHECK1-NEXT:  entry:
1270 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1271 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1272 // CHECK1-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1273 // CHECK1-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
1274 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1275 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1276 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1277 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1278 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1279 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[F]], align 4
1280 // CHECK1-NEXT:    ret void
1281 //
1282 //
1283 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
1284 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1285 // CHECK1-NEXT:  entry:
1286 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1287 // CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
1288 // CHECK1-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1289 // CHECK1-NEXT:    store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
1290 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1291 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1292 // CHECK1-NEXT:    [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
1293 // CHECK1-NEXT:    [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
1294 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
1295 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
1296 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
1297 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
1298 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[F]], align 4
1299 // CHECK1-NEXT:    ret void
1300 //
1301 //
1302 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1303 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1304 // CHECK1-NEXT:  entry:
1305 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1306 // CHECK1-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1307 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1308 // CHECK1-NEXT:    ret void
1309 //
1310 //
1311 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
1312 // CHECK1-SAME: () #[[ATTR0]] {
1313 // CHECK1-NEXT:  entry:
1314 // CHECK1-NEXT:    call void @__cxx_global_var_init()
1315 // CHECK1-NEXT:    call void @__cxx_global_var_init.1()
1316 // CHECK1-NEXT:    call void @__cxx_global_var_init.2()
1317 // CHECK1-NEXT:    ret void
1318 //
1319 //
1320 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1321 // CHECK1-SAME: () #[[ATTR0]] {
1322 // CHECK1-NEXT:  entry:
1323 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
1324 // CHECK1-NEXT:    ret void
1325 //
1326 //
1327 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
1328 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
1329 // CHECK3-NEXT:  entry:
1330 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
1331 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1332 // CHECK3-NEXT:    ret void
1333 //
1334 //
1335 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1336 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1337 // CHECK3-NEXT:  entry:
1338 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1339 // CHECK3-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1340 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1341 // CHECK3-NEXT:    call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1342 // CHECK3-NEXT:    ret void
1343 //
1344 //
1345 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1346 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1347 // CHECK3-NEXT:  entry:
1348 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1349 // CHECK3-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1350 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1351 // CHECK3-NEXT:    call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1352 // CHECK3-NEXT:    ret void
1353 //
1354 //
1355 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1356 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1357 // CHECK3-NEXT:  entry:
1358 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1359 // CHECK3-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1360 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1361 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1362 // CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1363 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1364 // CHECK3-NEXT:    store float [[CONV]], float* [[F]], align 4
1365 // CHECK3-NEXT:    ret void
1366 //
1367 //
1368 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1369 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1370 // CHECK3-NEXT:  entry:
1371 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1372 // CHECK3-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1373 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1374 // CHECK3-NEXT:    ret void
1375 //
1376 //
1377 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1378 // CHECK3-SAME: () #[[ATTR0]] {
1379 // CHECK3-NEXT:  entry:
1380 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00)
1381 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00)
1382 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
1383 // CHECK3-NEXT:    ret void
1384 //
1385 //
1386 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1387 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1388 // CHECK3-NEXT:  entry:
1389 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1390 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1391 // CHECK3-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1392 // CHECK3-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
1393 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1394 // CHECK3-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1395 // CHECK3-NEXT:    call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1396 // CHECK3-NEXT:    ret void
1397 //
1398 //
1399 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1400 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
1401 // CHECK3-NEXT:  entry:
1402 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 4
1403 // CHECK3-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 4
1404 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1405 // CHECK3:       arraydestroy.body:
1406 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1407 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1408 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1409 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
1410 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1411 // CHECK3:       arraydestroy.done1:
1412 // CHECK3-NEXT:    ret void
1413 //
1414 //
1415 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1416 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1417 // CHECK3-NEXT:  entry:
1418 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1419 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1420 // CHECK3-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1421 // CHECK3-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
1422 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1423 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1424 // CHECK3-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1425 // CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1426 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1427 // CHECK3-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1428 // CHECK3-NEXT:    store float [[ADD]], float* [[F]], align 4
1429 // CHECK3-NEXT:    ret void
1430 //
1431 //
1432 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1433 // CHECK3-SAME: () #[[ATTR0]] {
1434 // CHECK3-NEXT:  entry:
1435 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1436 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1437 // CHECK3-NEXT:    ret void
1438 //
1439 //
1440 // CHECK3-LABEL: define {{[^@]+}}@main
1441 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
1442 // CHECK3-NEXT:  entry:
1443 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1444 // CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1445 // CHECK3-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 4
1446 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
1447 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
1448 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
1449 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1450 // CHECK3-NEXT:    store i32 0, i32* [[RETVAL]], align 4
1451 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* @t_var, align 4
1452 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4
1453 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
1454 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
1455 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4
1456 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
1457 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1458 // CHECK3-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to [2 x i32]**
1459 // CHECK3-NEXT:    store [2 x i32]* @vec, [2 x i32]** [[TMP5]], align 4
1460 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1461 // CHECK3-NEXT:    [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]**
1462 // CHECK3-NEXT:    store [2 x i32]* @vec, [2 x i32]** [[TMP7]], align 4
1463 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1464 // CHECK3-NEXT:    store i8* null, i8** [[TMP8]], align 4
1465 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1466 // CHECK3-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
1467 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
1468 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1469 // CHECK3-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
1470 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP12]], align 4
1471 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1472 // CHECK3-NEXT:    store i8* null, i8** [[TMP13]], align 4
1473 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1474 // CHECK3-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]**
1475 // CHECK3-NEXT:    store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 4
1476 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1477 // CHECK3-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]**
1478 // CHECK3-NEXT:    store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 4
1479 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1480 // CHECK3-NEXT:    store i8* null, i8** [[TMP18]], align 4
1481 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1482 // CHECK3-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S**
1483 // CHECK3-NEXT:    store %struct.S* @var, %struct.S** [[TMP20]], align 4
1484 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1485 // CHECK3-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S**
1486 // CHECK3-NEXT:    store %struct.S* @var, %struct.S** [[TMP22]], align 4
1487 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1488 // CHECK3-NEXT:    store i8* null, i8** [[TMP23]], align 4
1489 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1490 // CHECK3-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
1491 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP25]], align 4
1492 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1493 // CHECK3-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
1494 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP27]], align 4
1495 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1496 // CHECK3-NEXT:    store i8* null, i8** [[TMP28]], align 4
1497 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1498 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1499 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1500 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1501 // CHECK3-NEXT:    store i32 1, i32* [[TMP31]], align 4
1502 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1503 // CHECK3-NEXT:    store i32 5, i32* [[TMP32]], align 4
1504 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1505 // CHECK3-NEXT:    store i8** [[TMP29]], i8*** [[TMP33]], align 4
1506 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1507 // CHECK3-NEXT:    store i8** [[TMP30]], i8*** [[TMP34]], align 4
1508 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1509 // CHECK3-NEXT:    store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP35]], align 4
1510 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1511 // CHECK3-NEXT:    store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP36]], align 4
1512 // CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1513 // CHECK3-NEXT:    store i8** null, i8*** [[TMP37]], align 4
1514 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1515 // CHECK3-NEXT:    store i8** null, i8*** [[TMP38]], align 4
1516 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1517 // CHECK3-NEXT:    store i64 2, i64* [[TMP39]], align 8
1518 // CHECK3-NEXT:    [[TMP40:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1519 // CHECK3-NEXT:    [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
1520 // CHECK3-NEXT:    br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1521 // CHECK3:       omp_offload.failed:
1522 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122([2 x i32]* @vec, i32 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]]
1523 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1524 // CHECK3:       omp_offload.cont:
1525 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1526 // CHECK3-NEXT:    ret i32 [[CALL]]
1527 //
1528 //
1529 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122
1530 // CHECK3-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
1531 // CHECK3-NEXT:  entry:
1532 // CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
1533 // CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1534 // CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
1535 // CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
1536 // CHECK3-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 4
1537 // CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1538 // CHECK3-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 4
1539 // CHECK3-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
1540 // CHECK3-NEXT:    store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
1541 // CHECK3-NEXT:    store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
1542 // CHECK3-NEXT:    store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
1543 // CHECK3-NEXT:    store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
1544 // CHECK3-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
1545 // CHECK3-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
1546 // CHECK3-NEXT:    [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
1547 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
1548 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
1549 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
1550 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
1551 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4
1552 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
1553 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]])
1554 // CHECK3-NEXT:    ret void
1555 //
1556 //
1557 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
1558 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] {
1559 // CHECK3-NEXT:  entry:
1560 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1561 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1562 // CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
1563 // CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1564 // CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
1565 // CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
1566 // CHECK3-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 4
1567 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1568 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1569 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1570 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1571 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1572 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1573 // CHECK3-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 4
1574 // CHECK3-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
1575 // CHECK3-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1576 // CHECK3-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1577 // CHECK3-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
1578 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1579 // CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1580 // CHECK3-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 4
1581 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1582 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1583 // CHECK3-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
1584 // CHECK3-NEXT:    store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
1585 // CHECK3-NEXT:    store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
1586 // CHECK3-NEXT:    store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
1587 // CHECK3-NEXT:    store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
1588 // CHECK3-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
1589 // CHECK3-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
1590 // CHECK3-NEXT:    [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
1591 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1592 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1593 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1594 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1595 // CHECK3-NEXT:    [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
1596 // CHECK3-NEXT:    [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1597 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
1598 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
1599 // CHECK3-NEXT:    [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
1600 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
1601 // CHECK3-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
1602 // CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1603 // CHECK3:       omp.arraycpy.body:
1604 // CHECK3-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1605 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1606 // CHECK3-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1607 // CHECK3-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]])
1608 // CHECK3-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1609 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1610 // CHECK3-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1611 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
1612 // CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
1613 // CHECK3:       omp.arraycpy.done3:
1614 // CHECK3-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
1615 // CHECK3-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]])
1616 // CHECK3-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
1617 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1618 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
1619 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1620 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1621 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
1622 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1623 // CHECK3:       cond.true:
1624 // CHECK3-NEXT:    br label [[COND_END:%.*]]
1625 // CHECK3:       cond.false:
1626 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1627 // CHECK3-NEXT:    br label [[COND_END]]
1628 // CHECK3:       cond.end:
1629 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
1630 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1631 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1632 // CHECK3-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
1633 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1634 // CHECK3:       omp.inner.for.cond:
1635 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1636 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
1637 // CHECK3-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
1638 // CHECK3-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1639 // CHECK3:       omp.inner.for.cond.cleanup:
1640 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1641 // CHECK3:       omp.inner.for.body:
1642 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
1643 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
1644 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !6
1645 // CHECK3-NEXT:    store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !6
1646 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !6
1647 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !6
1648 // CHECK3-NEXT:    store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4, !llvm.access.group !6
1649 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4, !llvm.access.group !6
1650 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]), !llvm.access.group !6
1651 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1652 // CHECK3:       omp.inner.for.inc:
1653 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1654 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
1655 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
1656 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1657 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1658 // CHECK3:       omp.inner.for.end:
1659 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1660 // CHECK3:       omp.loop.exit:
1661 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1662 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
1663 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
1664 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1665 // CHECK3-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
1666 // CHECK3-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1667 // CHECK3:       .omp.final.then:
1668 // CHECK3-NEXT:    store i32 2, i32* [[I]], align 4
1669 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1670 // CHECK3:       .omp.final.done:
1671 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
1672 // CHECK3-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
1673 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2
1674 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1675 // CHECK3:       arraydestroy.body:
1676 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1677 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1678 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1679 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
1680 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
1681 // CHECK3:       arraydestroy.done8:
1682 // CHECK3-NEXT:    ret void
1683 //
1684 //
1685 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev
1686 // CHECK3-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1687 // CHECK3-NEXT:  entry:
1688 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
1689 // CHECK3-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
1690 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
1691 // CHECK3-NEXT:    call void @_ZN2StC2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]])
1692 // CHECK3-NEXT:    ret void
1693 //
1694 //
1695 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
1696 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1697 // CHECK3-NEXT:  entry:
1698 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1699 // CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca %struct.S*, align 4
1700 // CHECK3-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1701 // CHECK3-NEXT:    store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
1702 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1703 // CHECK3-NEXT:    [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
1704 // CHECK3-NEXT:    call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]])
1705 // CHECK3-NEXT:    ret void
1706 //
1707 //
1708 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev
1709 // CHECK3-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1710 // CHECK3-NEXT:  entry:
1711 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
1712 // CHECK3-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
1713 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
1714 // CHECK3-NEXT:    call void @_ZN2StD2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
1715 // CHECK3-NEXT:    ret void
1716 //
1717 //
1718 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
1719 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] {
1720 // CHECK3-NEXT:  entry:
1721 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1722 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1723 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
1724 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
1725 // CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
1726 // CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1727 // CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
1728 // CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
1729 // CHECK3-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 4
1730 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1731 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1732 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1733 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1734 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1735 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1736 // CHECK3-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 4
1737 // CHECK3-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
1738 // CHECK3-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1739 // CHECK3-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1740 // CHECK3-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
1741 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1742 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1743 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1744 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1745 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1746 // CHECK3-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
1747 // CHECK3-NEXT:    store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
1748 // CHECK3-NEXT:    store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
1749 // CHECK3-NEXT:    store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
1750 // CHECK3-NEXT:    store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
1751 // CHECK3-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
1752 // CHECK3-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
1753 // CHECK3-NEXT:    [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
1754 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1755 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
1756 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1757 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1758 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
1759 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
1760 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1761 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1762 // CHECK3-NEXT:    [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
1763 // CHECK3-NEXT:    [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1764 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false)
1765 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
1766 // CHECK3-NEXT:    [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
1767 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
1768 // CHECK3-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]]
1769 // CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1770 // CHECK3:       omp.arraycpy.body:
1771 // CHECK3-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1772 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1773 // CHECK3-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1774 // CHECK3-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]])
1775 // CHECK3-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1776 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1777 // CHECK3-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1778 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
1779 // CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
1780 // CHECK3:       omp.arraycpy.done3:
1781 // CHECK3-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
1782 // CHECK3-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]])
1783 // CHECK3-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
1784 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1785 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
1786 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1787 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1788 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1
1789 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1790 // CHECK3:       cond.true:
1791 // CHECK3-NEXT:    br label [[COND_END:%.*]]
1792 // CHECK3:       cond.false:
1793 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1794 // CHECK3-NEXT:    br label [[COND_END]]
1795 // CHECK3:       cond.end:
1796 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
1797 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1798 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1799 // CHECK3-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
1800 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1801 // CHECK3:       omp.inner.for.cond:
1802 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
1803 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
1804 // CHECK3-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
1805 // CHECK3-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1806 // CHECK3:       omp.inner.for.cond.cleanup:
1807 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1808 // CHECK3:       omp.inner.for.body:
1809 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
1810 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
1811 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1812 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
1813 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !10
1814 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
1815 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]]
1816 // CHECK3-NEXT:    store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
1817 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
1818 // CHECK3-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]]
1819 // CHECK3-NEXT:    [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
1820 // CHECK3-NEXT:    [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8*
1821 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !10
1822 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
1823 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !10
1824 // CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
1825 // CHECK3-NEXT:    store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !10
1826 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1827 // CHECK3:       omp.body.continue:
1828 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1829 // CHECK3:       omp.inner.for.inc:
1830 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
1831 // CHECK3-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1
1832 // CHECK3-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
1833 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
1834 // CHECK3:       omp.inner.for.end:
1835 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1836 // CHECK3:       omp.loop.exit:
1837 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1838 // CHECK3-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
1839 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
1840 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1841 // CHECK3-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
1842 // CHECK3-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1843 // CHECK3:       .omp.final.then:
1844 // CHECK3-NEXT:    store i32 2, i32* [[I]], align 4
1845 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1846 // CHECK3:       .omp.final.done:
1847 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
1848 // CHECK3-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
1849 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2
1850 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1851 // CHECK3:       arraydestroy.body:
1852 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1853 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1854 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1855 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1856 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1857 // CHECK3:       arraydestroy.done11:
1858 // CHECK3-NEXT:    ret void
1859 //
1860 //
1861 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1862 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat {
1863 // CHECK3-NEXT:  entry:
1864 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1865 // CHECK3-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1866 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1867 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1868 // CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1869 // CHECK3-NEXT:    [[VAR:%.*]] = alloca %struct.S.0*, align 4
1870 // CHECK3-NEXT:    [[TMP:%.*]] = alloca %struct.S.0*, align 4
1871 // CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1872 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
1873 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
1874 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
1875 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1876 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
1877 // CHECK3-NEXT:    store i32 0, i32* [[T_VAR]], align 4
1878 // CHECK3-NEXT:    [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1879 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
1880 // CHECK3-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1881 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
1882 // CHECK3-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
1883 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
1884 // CHECK3-NEXT:    store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
1885 // CHECK3-NEXT:    [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
1886 // CHECK3-NEXT:    store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4
1887 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
1888 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4
1889 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
1890 // CHECK3-NEXT:    [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
1891 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1892 // CHECK3-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]**
1893 // CHECK3-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 4
1894 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1895 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]**
1896 // CHECK3-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4
1897 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1898 // CHECK3-NEXT:    store i8* null, i8** [[TMP9]], align 4
1899 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1900 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
1901 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
1902 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1903 // CHECK3-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
1904 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
1905 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1906 // CHECK3-NEXT:    store i8* null, i8** [[TMP14]], align 4
1907 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1908 // CHECK3-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]**
1909 // CHECK3-NEXT:    store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 4
1910 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1911 // CHECK3-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
1912 // CHECK3-NEXT:    store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4
1913 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1914 // CHECK3-NEXT:    store i8* null, i8** [[TMP19]], align 4
1915 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1916 // CHECK3-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0**
1917 // CHECK3-NEXT:    store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 4
1918 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1919 // CHECK3-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
1920 // CHECK3-NEXT:    store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 4
1921 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1922 // CHECK3-NEXT:    store i8* null, i8** [[TMP24]], align 4
1923 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1924 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1925 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1926 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1927 // CHECK3-NEXT:    store i32 1, i32* [[TMP27]], align 4
1928 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1929 // CHECK3-NEXT:    store i32 4, i32* [[TMP28]], align 4
1930 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1931 // CHECK3-NEXT:    store i8** [[TMP25]], i8*** [[TMP29]], align 4
1932 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1933 // CHECK3-NEXT:    store i8** [[TMP26]], i8*** [[TMP30]], align 4
1934 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1935 // CHECK3-NEXT:    store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.6, i32 0, i32 0), i64** [[TMP31]], align 4
1936 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1937 // CHECK3-NEXT:    store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i64** [[TMP32]], align 4
1938 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1939 // CHECK3-NEXT:    store i8** null, i8*** [[TMP33]], align 4
1940 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1941 // CHECK3-NEXT:    store i8** null, i8*** [[TMP34]], align 4
1942 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1943 // CHECK3-NEXT:    store i64 2, i64* [[TMP35]], align 8
1944 // CHECK3-NEXT:    [[TMP36:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1945 // CHECK3-NEXT:    [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0
1946 // CHECK3-NEXT:    br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1947 // CHECK3:       omp_offload.failed:
1948 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]]
1949 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1950 // CHECK3:       omp_offload.cont:
1951 // CHECK3-NEXT:    store i32 0, i32* [[RETVAL]], align 4
1952 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1953 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1954 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1955 // CHECK3:       arraydestroy.body:
1956 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1957 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1958 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1959 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1960 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1961 // CHECK3:       arraydestroy.done2:
1962 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1963 // CHECK3-NEXT:    [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4
1964 // CHECK3-NEXT:    ret i32 [[TMP39]]
1965 //
1966 //
1967 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev
1968 // CHECK3-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1969 // CHECK3-NEXT:  entry:
1970 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
1971 // CHECK3-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
1972 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
1973 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
1974 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
1975 // CHECK3-NEXT:    [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
1976 // CHECK3-NEXT:    store i32 0, i32* [[B]], align 4
1977 // CHECK3-NEXT:    ret void
1978 //
1979 //
1980 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
1981 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1982 // CHECK3-NEXT:  entry:
1983 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1984 // CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca %struct.S*, align 4
1985 // CHECK3-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1986 // CHECK3-NEXT:    store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
1987 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1988 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1989 // CHECK3-NEXT:    [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
1990 // CHECK3-NEXT:    [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
1991 // CHECK3-NEXT:    [[TMP1:%.*]] = load float, float* [[F2]], align 4
1992 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
1993 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
1994 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
1995 // CHECK3-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
1996 // CHECK3-NEXT:    store float [[ADD]], float* [[F]], align 4
1997 // CHECK3-NEXT:    ret void
1998 //
1999 //
2000 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev
2001 // CHECK3-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2002 // CHECK3-NEXT:  entry:
2003 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
2004 // CHECK3-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
2005 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
2006 // CHECK3-NEXT:    ret void
2007 //
2008 //
2009 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2010 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2011 // CHECK3-NEXT:  entry:
2012 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2013 // CHECK3-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2014 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2015 // CHECK3-NEXT:    call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2016 // CHECK3-NEXT:    ret void
2017 //
2018 //
2019 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2020 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2021 // CHECK3-NEXT:  entry:
2022 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2023 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2024 // CHECK3-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2025 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2026 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2027 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2028 // CHECK3-NEXT:    call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
2029 // CHECK3-NEXT:    ret void
2030 //
2031 //
2032 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81
2033 // CHECK3-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
2034 // CHECK3-NEXT:  entry:
2035 // CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2036 // CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2037 // CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
2038 // CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
2039 // CHECK3-NEXT:    [[TMP:%.*]] = alloca %struct.S.0*, align 4
2040 // CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2041 // CHECK3-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2042 // CHECK3-NEXT:    store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2043 // CHECK3-NEXT:    store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2044 // CHECK3-NEXT:    store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
2045 // CHECK3-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2046 // CHECK3-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2047 // CHECK3-NEXT:    [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
2048 // CHECK3-NEXT:    store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
2049 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
2050 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
2051 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2052 // CHECK3-NEXT:    [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2053 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
2054 // CHECK3-NEXT:    ret void
2055 //
2056 //
2057 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
2058 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
2059 // CHECK3-NEXT:  entry:
2060 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2061 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2062 // CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2063 // CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2064 // CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
2065 // CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
2066 // CHECK3-NEXT:    [[TMP:%.*]] = alloca %struct.S.0*, align 4
2067 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2068 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2069 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2070 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2071 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2072 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2073 // CHECK3-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 4
2074 // CHECK3-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
2075 // CHECK3-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
2076 // CHECK3-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2077 // CHECK3-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
2078 // CHECK3-NEXT:    [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
2079 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
2080 // CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2081 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2082 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2083 // CHECK3-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2084 // CHECK3-NEXT:    store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2085 // CHECK3-NEXT:    store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2086 // CHECK3-NEXT:    store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
2087 // CHECK3-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2088 // CHECK3-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2089 // CHECK3-NEXT:    [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
2090 // CHECK3-NEXT:    store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
2091 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2092 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
2093 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2094 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2095 // CHECK3-NEXT:    [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
2096 // CHECK3-NEXT:    [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2097 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
2098 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
2099 // CHECK3-NEXT:    [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
2100 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2101 // CHECK3-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
2102 // CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2103 // CHECK3:       omp.arraycpy.body:
2104 // CHECK3-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2105 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2106 // CHECK3-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2107 // CHECK3-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]])
2108 // CHECK3-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2109 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2110 // CHECK3-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2111 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
2112 // CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
2113 // CHECK3:       omp.arraycpy.done4:
2114 // CHECK3-NEXT:    [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2115 // CHECK3-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
2116 // CHECK3-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]])
2117 // CHECK3-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
2118 // CHECK3-NEXT:    store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
2119 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2120 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
2121 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2122 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2123 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
2124 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2125 // CHECK3:       cond.true:
2126 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2127 // CHECK3:       cond.false:
2128 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2129 // CHECK3-NEXT:    br label [[COND_END]]
2130 // CHECK3:       cond.end:
2131 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
2132 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2133 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2134 // CHECK3-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
2135 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2136 // CHECK3:       omp.inner.for.cond:
2137 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
2138 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
2139 // CHECK3-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
2140 // CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2141 // CHECK3:       omp.inner.for.cond.cleanup:
2142 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2143 // CHECK3:       omp.inner.for.body:
2144 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
2145 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
2146 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !15
2147 // CHECK3-NEXT:    store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !15
2148 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !15
2149 // CHECK3-NEXT:    [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !15
2150 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]), !llvm.access.group !15
2151 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2152 // CHECK3:       omp.inner.for.inc:
2153 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
2154 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
2155 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
2156 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
2157 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
2158 // CHECK3:       omp.inner.for.end:
2159 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2160 // CHECK3:       omp.loop.exit:
2161 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2162 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
2163 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
2164 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2165 // CHECK3-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
2166 // CHECK3-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2167 // CHECK3:       .omp.final.then:
2168 // CHECK3-NEXT:    store i32 2, i32* [[I]], align 4
2169 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2170 // CHECK3:       .omp.final.done:
2171 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
2172 // CHECK3-NEXT:    [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
2173 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2
2174 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2175 // CHECK3:       arraydestroy.body:
2176 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2177 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2178 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2179 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
2180 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
2181 // CHECK3:       arraydestroy.done10:
2182 // CHECK3-NEXT:    ret void
2183 //
2184 //
2185 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
2186 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2187 // CHECK3-NEXT:  entry:
2188 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2189 // CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
2190 // CHECK3-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2191 // CHECK3-NEXT:    store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
2192 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2193 // CHECK3-NEXT:    [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
2194 // CHECK3-NEXT:    call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]])
2195 // CHECK3-NEXT:    ret void
2196 //
2197 //
2198 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5
2199 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
2200 // CHECK3-NEXT:  entry:
2201 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2202 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2203 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2204 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2205 // CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2206 // CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2207 // CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
2208 // CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
2209 // CHECK3-NEXT:    [[TMP:%.*]] = alloca %struct.S.0*, align 4
2210 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2211 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2212 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2213 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2214 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2215 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2216 // CHECK3-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 4
2217 // CHECK3-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
2218 // CHECK3-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
2219 // CHECK3-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2220 // CHECK3-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
2221 // CHECK3-NEXT:    [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
2222 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
2223 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2224 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2225 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2226 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2227 // CHECK3-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2228 // CHECK3-NEXT:    store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2229 // CHECK3-NEXT:    store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2230 // CHECK3-NEXT:    store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
2231 // CHECK3-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2232 // CHECK3-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2233 // CHECK3-NEXT:    [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
2234 // CHECK3-NEXT:    store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
2235 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2236 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
2237 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2238 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2239 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
2240 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
2241 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2242 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2243 // CHECK3-NEXT:    [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
2244 // CHECK3-NEXT:    [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2245 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false)
2246 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
2247 // CHECK3-NEXT:    [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
2248 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2249 // CHECK3-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
2250 // CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2251 // CHECK3:       omp.arraycpy.body:
2252 // CHECK3-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2253 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2254 // CHECK3-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2255 // CHECK3-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]])
2256 // CHECK3-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2257 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2258 // CHECK3-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2259 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
2260 // CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
2261 // CHECK3:       omp.arraycpy.done4:
2262 // CHECK3-NEXT:    [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2263 // CHECK3-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
2264 // CHECK3-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP6]])
2265 // CHECK3-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
2266 // CHECK3-NEXT:    store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
2267 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2268 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
2269 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2270 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2271 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
2272 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2273 // CHECK3:       cond.true:
2274 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2275 // CHECK3:       cond.false:
2276 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2277 // CHECK3-NEXT:    br label [[COND_END]]
2278 // CHECK3:       cond.end:
2279 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
2280 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2281 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2282 // CHECK3-NEXT:    store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
2283 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2284 // CHECK3:       omp.inner.for.cond:
2285 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
2286 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
2287 // CHECK3-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
2288 // CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2289 // CHECK3:       omp.inner.for.cond.cleanup:
2290 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2291 // CHECK3:       omp.inner.for.body:
2292 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
2293 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
2294 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2295 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
2296 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !18
2297 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
2298 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]]
2299 // CHECK3-NEXT:    store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
2300 // CHECK3-NEXT:    [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !18
2301 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
2302 // CHECK3-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]]
2303 // CHECK3-NEXT:    [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8*
2304 // CHECK3-NEXT:    [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8*
2305 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false), !llvm.access.group !18
2306 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2307 // CHECK3:       omp.body.continue:
2308 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2309 // CHECK3:       omp.inner.for.inc:
2310 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
2311 // CHECK3-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
2312 // CHECK3-NEXT:    store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
2313 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
2314 // CHECK3:       omp.inner.for.end:
2315 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2316 // CHECK3:       omp.loop.exit:
2317 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2318 // CHECK3-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
2319 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
2320 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2321 // CHECK3-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
2322 // CHECK3-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2323 // CHECK3:       .omp.final.then:
2324 // CHECK3-NEXT:    store i32 2, i32* [[I]], align 4
2325 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2326 // CHECK3:       .omp.final.done:
2327 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
2328 // CHECK3-NEXT:    [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
2329 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
2330 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2331 // CHECK3:       arraydestroy.body:
2332 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2333 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2334 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2335 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
2336 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
2337 // CHECK3:       arraydestroy.done12:
2338 // CHECK3-NEXT:    ret void
2339 //
2340 //
2341 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2342 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2343 // CHECK3-NEXT:  entry:
2344 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2345 // CHECK3-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2346 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2347 // CHECK3-NEXT:    call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2348 // CHECK3-NEXT:    ret void
2349 //
2350 //
2351 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2352 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2353 // CHECK3-NEXT:  entry:
2354 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2355 // CHECK3-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2356 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2357 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2358 // CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2359 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[F]], align 4
2360 // CHECK3-NEXT:    ret void
2361 //
2362 //
2363 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2364 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2365 // CHECK3-NEXT:  entry:
2366 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2367 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2368 // CHECK3-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2369 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2370 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2371 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2372 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2373 // CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2374 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2375 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[F]], align 4
2376 // CHECK3-NEXT:    ret void
2377 //
2378 //
2379 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
2380 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2381 // CHECK3-NEXT:  entry:
2382 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2383 // CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
2384 // CHECK3-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2385 // CHECK3-NEXT:    store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
2386 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2387 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2388 // CHECK3-NEXT:    [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
2389 // CHECK3-NEXT:    [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
2390 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
2391 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
2392 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
2393 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
2394 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[F]], align 4
2395 // CHECK3-NEXT:    ret void
2396 //
2397 //
2398 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2399 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2400 // CHECK3-NEXT:  entry:
2401 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2402 // CHECK3-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2403 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2404 // CHECK3-NEXT:    ret void
2405 //
2406 //
2407 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
2408 // CHECK3-SAME: () #[[ATTR0]] {
2409 // CHECK3-NEXT:  entry:
2410 // CHECK3-NEXT:    call void @__cxx_global_var_init()
2411 // CHECK3-NEXT:    call void @__cxx_global_var_init.1()
2412 // CHECK3-NEXT:    call void @__cxx_global_var_init.2()
2413 // CHECK3-NEXT:    ret void
2414 //
2415 //
2416 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2417 // CHECK3-SAME: () #[[ATTR0]] {
2418 // CHECK3-NEXT:  entry:
2419 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
2420 // CHECK3-NEXT:    ret void
2421 //
2422 //
2423 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init
2424 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
2425 // CHECK5-NEXT:  entry:
2426 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
2427 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2428 // CHECK5-NEXT:    ret void
2429 //
2430 //
2431 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2432 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2433 // CHECK5-NEXT:  entry:
2434 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2435 // CHECK5-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2436 // CHECK5-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2437 // CHECK5-NEXT:    call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2438 // CHECK5-NEXT:    ret void
2439 //
2440 //
2441 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2442 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2443 // CHECK5-NEXT:  entry:
2444 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2445 // CHECK5-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2446 // CHECK5-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2447 // CHECK5-NEXT:    call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2448 // CHECK5-NEXT:    ret void
2449 //
2450 //
2451 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2452 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2453 // CHECK5-NEXT:  entry:
2454 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2455 // CHECK5-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2456 // CHECK5-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2457 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2458 // CHECK5-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2459 // CHECK5-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2460 // CHECK5-NEXT:    store float [[CONV]], float* [[F]], align 4
2461 // CHECK5-NEXT:    ret void
2462 //
2463 //
2464 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2465 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2466 // CHECK5-NEXT:  entry:
2467 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2468 // CHECK5-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2469 // CHECK5-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2470 // CHECK5-NEXT:    ret void
2471 //
2472 //
2473 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2474 // CHECK5-SAME: () #[[ATTR0]] {
2475 // CHECK5-NEXT:  entry:
2476 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
2477 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
2478 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2479 // CHECK5-NEXT:    ret void
2480 //
2481 //
2482 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2483 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2484 // CHECK5-NEXT:  entry:
2485 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2486 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2487 // CHECK5-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2488 // CHECK5-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
2489 // CHECK5-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2490 // CHECK5-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2491 // CHECK5-NEXT:    call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2492 // CHECK5-NEXT:    ret void
2493 //
2494 //
2495 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2496 // CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
2497 // CHECK5-NEXT:  entry:
2498 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
2499 // CHECK5-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2500 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2501 // CHECK5:       arraydestroy.body:
2502 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2503 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2504 // CHECK5-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2505 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2506 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2507 // CHECK5:       arraydestroy.done1:
2508 // CHECK5-NEXT:    ret void
2509 //
2510 //
2511 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2512 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2513 // CHECK5-NEXT:  entry:
2514 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2515 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2516 // CHECK5-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2517 // CHECK5-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
2518 // CHECK5-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2519 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2520 // CHECK5-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2521 // CHECK5-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2522 // CHECK5-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2523 // CHECK5-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2524 // CHECK5-NEXT:    store float [[ADD]], float* [[F]], align 4
2525 // CHECK5-NEXT:    ret void
2526 //
2527 //
2528 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2529 // CHECK5-SAME: () #[[ATTR0]] {
2530 // CHECK5-NEXT:  entry:
2531 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2532 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2533 // CHECK5-NEXT:    ret void
2534 //
2535 //
2536 // CHECK5-LABEL: define {{[^@]+}}@main
2537 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] {
2538 // CHECK5-NEXT:  entry:
2539 // CHECK5-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2540 // CHECK5-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
2541 // CHECK5-NEXT:    store i32 0, i32* [[RETVAL]], align 4
2542 // CHECK5-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
2543 // CHECK5-NEXT:    ret i32 0
2544 //
2545 //
2546 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99
2547 // CHECK5-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] {
2548 // CHECK5-NEXT:  entry:
2549 // CHECK5-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 8
2550 // CHECK5-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8
2551 // CHECK5-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
2552 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32*, align 8
2553 // CHECK5-NEXT:    [[G_CASTED:%.*]] = alloca i64, align 8
2554 // CHECK5-NEXT:    [[G1_CASTED:%.*]] = alloca i64, align 8
2555 // CHECK5-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8
2556 // CHECK5-NEXT:    store i64 [[G]], i64* [[G_ADDR]], align 8
2557 // CHECK5-NEXT:    store i64 [[G1]], i64* [[G1_ADDR]], align 8
2558 // CHECK5-NEXT:    store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
2559 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
2560 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
2561 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
2562 // CHECK5-NEXT:    store i32* [[CONV1]], i32** [[TMP]], align 8
2563 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
2564 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
2565 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[CONV3]], align 4
2566 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
2567 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
2568 // CHECK5-NEXT:    [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
2569 // CHECK5-NEXT:    [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
2570 // CHECK5-NEXT:    store i32 [[TMP3]], i32* [[CONV4]], align 4
2571 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
2572 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
2573 // CHECK5-NEXT:    [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
2574 // CHECK5-NEXT:    store i32 [[TMP5]], i32* [[CONV5]], align 4
2575 // CHECK5-NEXT:    [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
2576 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
2577 // CHECK5-NEXT:    ret void
2578 //
2579 //
2580 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
2581 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] {
2582 // CHECK5-NEXT:  entry:
2583 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2584 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2585 // CHECK5-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 8
2586 // CHECK5-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8
2587 // CHECK5-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
2588 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32*, align 8
2589 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2590 // CHECK5-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
2591 // CHECK5-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2592 // CHECK5-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2593 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2594 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2595 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
2596 // CHECK5-NEXT:    [[G_CASTED:%.*]] = alloca i64, align 8
2597 // CHECK5-NEXT:    [[G1_CASTED:%.*]] = alloca i64, align 8
2598 // CHECK5-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8
2599 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2600 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2601 // CHECK5-NEXT:    store i64 [[G]], i64* [[G_ADDR]], align 8
2602 // CHECK5-NEXT:    store i64 [[G1]], i64* [[G1_ADDR]], align 8
2603 // CHECK5-NEXT:    store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
2604 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
2605 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
2606 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
2607 // CHECK5-NEXT:    store i32* [[CONV1]], i32** [[TMP]], align 8
2608 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2609 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
2610 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2611 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2612 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2613 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2614 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2615 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2616 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
2617 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2618 // CHECK5:       cond.true:
2619 // CHECK5-NEXT:    br label [[COND_END:%.*]]
2620 // CHECK5:       cond.false:
2621 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2622 // CHECK5-NEXT:    br label [[COND_END]]
2623 // CHECK5:       cond.end:
2624 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2625 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2626 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2627 // CHECK5-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2628 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2629 // CHECK5:       omp.inner.for.cond:
2630 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
2631 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
2632 // CHECK5-NEXT:    [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2633 // CHECK5-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2634 // CHECK5:       omp.inner.for.body:
2635 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
2636 // CHECK5-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
2637 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
2638 // CHECK5-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
2639 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !4
2640 // CHECK5-NEXT:    [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
2641 // CHECK5-NEXT:    store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4
2642 // CHECK5-NEXT:    [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4
2643 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4
2644 // CHECK5-NEXT:    [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4, !llvm.access.group !4
2645 // CHECK5-NEXT:    [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
2646 // CHECK5-NEXT:    store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4
2647 // CHECK5-NEXT:    [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4
2648 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4, !llvm.access.group !4
2649 // CHECK5-NEXT:    [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
2650 // CHECK5-NEXT:    store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4
2651 // CHECK5-NEXT:    [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !4
2652 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4
2653 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2654 // CHECK5:       omp.inner.for.inc:
2655 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
2656 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
2657 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
2658 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
2659 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
2660 // CHECK5:       omp.inner.for.end:
2661 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2662 // CHECK5:       omp.loop.exit:
2663 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2664 // CHECK5-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2665 // CHECK5-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
2666 // CHECK5-NEXT:    br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2667 // CHECK5:       .omp.final.then:
2668 // CHECK5-NEXT:    store i32 2, i32* [[I]], align 4
2669 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2670 // CHECK5:       .omp.final.done:
2671 // CHECK5-NEXT:    ret void
2672 //
2673 //
2674 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3
2675 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] {
2676 // CHECK5-NEXT:  entry:
2677 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2678 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2679 // CHECK5-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2680 // CHECK5-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2681 // CHECK5-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 8
2682 // CHECK5-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8
2683 // CHECK5-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
2684 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32*, align 8
2685 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2686 // CHECK5-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
2687 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2688 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2689 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2690 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2691 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
2692 // CHECK5-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
2693 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2694 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2695 // CHECK5-NEXT:    store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2696 // CHECK5-NEXT:    store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2697 // CHECK5-NEXT:    store i64 [[G]], i64* [[G_ADDR]], align 8
2698 // CHECK5-NEXT:    store i64 [[G1]], i64* [[G1_ADDR]], align 8
2699 // CHECK5-NEXT:    store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
2700 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
2701 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
2702 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
2703 // CHECK5-NEXT:    store i32* [[CONV1]], i32** [[TMP]], align 8
2704 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2705 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
2706 // CHECK5-NEXT:    [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2707 // CHECK5-NEXT:    [[CONV4:%.*]] = trunc i64 [[TMP0]] to i32
2708 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2709 // CHECK5-NEXT:    [[CONV5:%.*]] = trunc i64 [[TMP1]] to i32
2710 // CHECK5-NEXT:    store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
2711 // CHECK5-NEXT:    store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
2712 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2713 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2714 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2715 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2716 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2717 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2718 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
2719 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2720 // CHECK5:       cond.true:
2721 // CHECK5-NEXT:    br label [[COND_END:%.*]]
2722 // CHECK5:       cond.false:
2723 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2724 // CHECK5-NEXT:    br label [[COND_END]]
2725 // CHECK5:       cond.end:
2726 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2727 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2728 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2729 // CHECK5-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2730 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2731 // CHECK5:       omp.inner.for.cond:
2732 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
2733 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8
2734 // CHECK5-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2735 // CHECK5-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2736 // CHECK5:       omp.inner.for.body:
2737 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
2738 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2739 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2740 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
2741 // CHECK5-NEXT:    store i32 1, i32* [[CONV]], align 4, !llvm.access.group !8
2742 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8
2743 // CHECK5-NEXT:    store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8
2744 // CHECK5-NEXT:    store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !8
2745 // CHECK5-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
2746 // CHECK5-NEXT:    store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8
2747 // CHECK5-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
2748 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8
2749 // CHECK5-NEXT:    store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8
2750 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
2751 // CHECK5-NEXT:    store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8
2752 // CHECK5-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !8
2753 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2754 // CHECK5:       omp.body.continue:
2755 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2756 // CHECK5:       omp.inner.for.inc:
2757 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
2758 // CHECK5-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1
2759 // CHECK5-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
2760 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
2761 // CHECK5:       omp.inner.for.end:
2762 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2763 // CHECK5:       omp.loop.exit:
2764 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
2765 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2766 // CHECK5-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
2767 // CHECK5-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2768 // CHECK5:       .omp.final.then:
2769 // CHECK5-NEXT:    store i32 2, i32* [[I]], align 4
2770 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2771 // CHECK5:       .omp.final.done:
2772 // CHECK5-NEXT:    ret void
2773 //
2774 //
2775 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
2776 // CHECK5-SAME: () #[[ATTR0]] {
2777 // CHECK5-NEXT:  entry:
2778 // CHECK5-NEXT:    call void @__cxx_global_var_init()
2779 // CHECK5-NEXT:    call void @__cxx_global_var_init.1()
2780 // CHECK5-NEXT:    call void @__cxx_global_var_init.2()
2781 // CHECK5-NEXT:    ret void
2782 //
2783 //
2784 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2785 // CHECK5-SAME: () #[[ATTR0]] {
2786 // CHECK5-NEXT:  entry:
2787 // CHECK5-NEXT:    call void @__tgt_register_requires(i64 1)
2788 // CHECK5-NEXT:    ret void
2789 //
2790 //
2791 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init
2792 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
2793 // CHECK7-NEXT:  entry:
2794 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
2795 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2796 // CHECK7-NEXT:    ret void
2797 //
2798 //
2799 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2800 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2801 // CHECK7-NEXT:  entry:
2802 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2803 // CHECK7-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2804 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2805 // CHECK7-NEXT:    call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2806 // CHECK7-NEXT:    ret void
2807 //
2808 //
2809 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2810 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2811 // CHECK7-NEXT:  entry:
2812 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2813 // CHECK7-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2814 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2815 // CHECK7-NEXT:    call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2816 // CHECK7-NEXT:    ret void
2817 //
2818 //
2819 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2820 // CHECK7-SAME: () #[[ATTR0]] {
2821 // CHECK7-NEXT:  entry:
2822 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
2823 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
2824 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2825 // CHECK7-NEXT:    ret void
2826 //
2827 //
2828 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2829 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2830 // CHECK7-NEXT:  entry:
2831 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2832 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2833 // CHECK7-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2834 // CHECK7-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
2835 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2836 // CHECK7-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2837 // CHECK7-NEXT:    call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2838 // CHECK7-NEXT:    ret void
2839 //
2840 //
2841 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2842 // CHECK7-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
2843 // CHECK7-NEXT:  entry:
2844 // CHECK7-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
2845 // CHECK7-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2846 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2847 // CHECK7:       arraydestroy.body:
2848 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2849 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2850 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2851 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2852 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2853 // CHECK7:       arraydestroy.done1:
2854 // CHECK7-NEXT:    ret void
2855 //
2856 //
2857 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2858 // CHECK7-SAME: () #[[ATTR0]] {
2859 // CHECK7-NEXT:  entry:
2860 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2861 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2862 // CHECK7-NEXT:    ret void
2863 //
2864 //
2865 // CHECK7-LABEL: define {{[^@]+}}@main
2866 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] {
2867 // CHECK7-NEXT:  entry:
2868 // CHECK7-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2869 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2870 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2871 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2872 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2873 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
2874 // CHECK7-NEXT:    store i32 0, i32* [[RETVAL]], align 4
2875 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2876 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
2877 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2878 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
2879 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2880 // CHECK7:       omp.inner.for.cond:
2881 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2882 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
2883 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
2884 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2885 // CHECK7:       omp.inner.for.body:
2886 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2887 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
2888 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2889 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
2890 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* @t_var, align 4, !llvm.access.group !2
2891 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
2892 // CHECK7-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
2893 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]]
2894 // CHECK7-NEXT:    store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2
2895 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
2896 // CHECK7-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64
2897 // CHECK7-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]]
2898 // CHECK7-NEXT:    [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
2899 // CHECK7-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false), !llvm.access.group !2
2900 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
2901 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !2
2902 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], [[TMP8]]
2903 // CHECK7-NEXT:    store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !2
2904 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2905 // CHECK7:       omp.body.continue:
2906 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2907 // CHECK7:       omp.inner.for.inc:
2908 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2909 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
2910 // CHECK7-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2911 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
2912 // CHECK7:       omp.inner.for.end:
2913 // CHECK7-NEXT:    store i32 2, i32* [[I]], align 4
2914 // CHECK7-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
2915 // CHECK7-NEXT:    ret i32 [[CALL]]
2916 //
2917 //
2918 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2919 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat {
2920 // CHECK7-NEXT:  entry:
2921 // CHECK7-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2922 // CHECK7-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2923 // CHECK7-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2924 // CHECK7-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2925 // CHECK7-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2926 // CHECK7-NEXT:    [[VAR:%.*]] = alloca %struct.S.0*, align 8
2927 // CHECK7-NEXT:    [[TMP:%.*]] = alloca %struct.S.0*, align 8
2928 // CHECK7-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2929 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2930 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2931 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2932 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
2933 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
2934 // CHECK7-NEXT:    store i32 0, i32* [[T_VAR]], align 4
2935 // CHECK7-NEXT:    [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
2936 // CHECK7-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
2937 // CHECK7-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
2938 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
2939 // CHECK7-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
2940 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
2941 // CHECK7-NEXT:    store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
2942 // CHECK7-NEXT:    [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
2943 // CHECK7-NEXT:    store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8
2944 // CHECK7-NEXT:    [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
2945 // CHECK7-NEXT:    [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
2946 // CHECK7-NEXT:    [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
2947 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2948 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
2949 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2950 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
2951 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2952 // CHECK7:       omp.inner.for.cond:
2953 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2954 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
2955 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
2956 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2957 // CHECK7:       omp.inner.for.body:
2958 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2959 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
2960 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2961 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
2962 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6
2963 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
2964 // CHECK7-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64
2965 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
2966 // CHECK7-NEXT:    store i32 [[TMP9]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
2967 // CHECK7-NEXT:    [[TMP11:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8, !llvm.access.group !6
2968 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
2969 // CHECK7-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP12]] to i64
2970 // CHECK7-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]]
2971 // CHECK7-NEXT:    [[TMP13:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8*
2972 // CHECK7-NEXT:    [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP11]] to i8*
2973 // CHECK7-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false), !llvm.access.group !6
2974 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2975 // CHECK7:       omp.body.continue:
2976 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2977 // CHECK7:       omp.inner.for.inc:
2978 // CHECK7-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2979 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1
2980 // CHECK7-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2981 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
2982 // CHECK7:       omp.inner.for.end:
2983 // CHECK7-NEXT:    store i32 2, i32* [[I]], align 4
2984 // CHECK7-NEXT:    store i32 0, i32* [[RETVAL]], align 4
2985 // CHECK7-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2986 // CHECK7-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
2987 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2988 // CHECK7:       arraydestroy.body:
2989 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2990 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2991 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2992 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2993 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
2994 // CHECK7:       arraydestroy.done5:
2995 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
2996 // CHECK7-NEXT:    [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4
2997 // CHECK7-NEXT:    ret i32 [[TMP17]]
2998 //
2999 //
3000 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3001 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3002 // CHECK7-NEXT:  entry:
3003 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3004 // CHECK7-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3005 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3006 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3007 // CHECK7-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3008 // CHECK7-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3009 // CHECK7-NEXT:    store float [[CONV]], float* [[F]], align 4
3010 // CHECK7-NEXT:    ret void
3011 //
3012 //
3013 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3014 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3015 // CHECK7-NEXT:  entry:
3016 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3017 // CHECK7-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3018 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3019 // CHECK7-NEXT:    ret void
3020 //
3021 //
3022 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3023 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3024 // CHECK7-NEXT:  entry:
3025 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3026 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
3027 // CHECK7-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3028 // CHECK7-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
3029 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3030 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3031 // CHECK7-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3032 // CHECK7-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3033 // CHECK7-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3034 // CHECK7-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3035 // CHECK7-NEXT:    store float [[ADD]], float* [[F]], align 4
3036 // CHECK7-NEXT:    ret void
3037 //
3038 //
3039 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
3040 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3041 // CHECK7-NEXT:  entry:
3042 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3043 // CHECK7-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3044 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3045 // CHECK7-NEXT:    call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
3046 // CHECK7-NEXT:    ret void
3047 //
3048 //
3049 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
3050 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3051 // CHECK7-NEXT:  entry:
3052 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3053 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3054 // CHECK7-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3055 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3056 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3057 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3058 // CHECK7-NEXT:    call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
3059 // CHECK7-NEXT:    ret void
3060 //
3061 //
3062 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
3063 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3064 // CHECK7-NEXT:  entry:
3065 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3066 // CHECK7-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3067 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3068 // CHECK7-NEXT:    call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3069 // CHECK7-NEXT:    ret void
3070 //
3071 //
3072 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
3073 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3074 // CHECK7-NEXT:  entry:
3075 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3076 // CHECK7-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3077 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3078 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3079 // CHECK7-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3080 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[F]], align 4
3081 // CHECK7-NEXT:    ret void
3082 //
3083 //
3084 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
3085 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3086 // CHECK7-NEXT:  entry:
3087 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3088 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3089 // CHECK7-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3090 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3091 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3092 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3093 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3094 // CHECK7-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3095 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
3096 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[F]], align 4
3097 // CHECK7-NEXT:    ret void
3098 //
3099 //
3100 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
3101 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3102 // CHECK7-NEXT:  entry:
3103 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3104 // CHECK7-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3105 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3106 // CHECK7-NEXT:    ret void
3107 //
3108 //
3109 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
3110 // CHECK7-SAME: () #[[ATTR0]] {
3111 // CHECK7-NEXT:  entry:
3112 // CHECK7-NEXT:    call void @__cxx_global_var_init()
3113 // CHECK7-NEXT:    call void @__cxx_global_var_init.1()
3114 // CHECK7-NEXT:    call void @__cxx_global_var_init.2()
3115 // CHECK7-NEXT:    ret void
3116 //
3117 //
3118 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init
3119 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
3120 // CHECK9-NEXT:  entry:
3121 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
3122 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
3123 // CHECK9-NEXT:    ret void
3124 //
3125 //
3126 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3127 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3128 // CHECK9-NEXT:  entry:
3129 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3130 // CHECK9-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3131 // CHECK9-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3132 // CHECK9-NEXT:    call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
3133 // CHECK9-NEXT:    ret void
3134 //
3135 //
3136 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3137 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3138 // CHECK9-NEXT:  entry:
3139 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3140 // CHECK9-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3141 // CHECK9-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3142 // CHECK9-NEXT:    call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3143 // CHECK9-NEXT:    ret void
3144 //
3145 //
3146 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3147 // CHECK9-SAME: () #[[ATTR0]] {
3148 // CHECK9-NEXT:  entry:
3149 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00)
3150 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00)
3151 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
3152 // CHECK9-NEXT:    ret void
3153 //
3154 //
3155 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3156 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3157 // CHECK9-NEXT:  entry:
3158 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3159 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
3160 // CHECK9-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3161 // CHECK9-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
3162 // CHECK9-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3163 // CHECK9-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3164 // CHECK9-NEXT:    call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
3165 // CHECK9-NEXT:    ret void
3166 //
3167 //
3168 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3169 // CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
3170 // CHECK9-NEXT:  entry:
3171 // CHECK9-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 4
3172 // CHECK9-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 4
3173 // CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
3174 // CHECK9:       arraydestroy.body:
3175 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3176 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3177 // CHECK9-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3178 // CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
3179 // CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3180 // CHECK9:       arraydestroy.done1:
3181 // CHECK9-NEXT:    ret void
3182 //
3183 //
3184 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3185 // CHECK9-SAME: () #[[ATTR0]] {
3186 // CHECK9-NEXT:  entry:
3187 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
3188 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
3189 // CHECK9-NEXT:    ret void
3190 //
3191 //
3192 // CHECK9-LABEL: define {{[^@]+}}@main
3193 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
3194 // CHECK9-NEXT:  entry:
3195 // CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
3196 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3197 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3198 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3199 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3200 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
3201 // CHECK9-NEXT:    store i32 0, i32* [[RETVAL]], align 4
3202 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
3203 // CHECK9-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
3204 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3205 // CHECK9-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
3206 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3207 // CHECK9:       omp.inner.for.cond:
3208 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3209 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
3210 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
3211 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3212 // CHECK9:       omp.inner.for.body:
3213 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3214 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
3215 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3216 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
3217 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* @t_var, align 4, !llvm.access.group !3
3218 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
3219 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP5]]
3220 // CHECK9-NEXT:    store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3
3221 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
3222 // CHECK9-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP6]]
3223 // CHECK9-NEXT:    [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8*
3224 // CHECK9-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false), !llvm.access.group !3
3225 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
3226 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !3
3227 // CHECK9-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], [[TMP8]]
3228 // CHECK9-NEXT:    store i32 [[ADD2]], i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !3
3229 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3230 // CHECK9:       omp.body.continue:
3231 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3232 // CHECK9:       omp.inner.for.inc:
3233 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3234 // CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
3235 // CHECK9-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3236 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
3237 // CHECK9:       omp.inner.for.end:
3238 // CHECK9-NEXT:    store i32 2, i32* [[I]], align 4
3239 // CHECK9-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
3240 // CHECK9-NEXT:    ret i32 [[CALL]]
3241 //
3242 //
3243 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
3244 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat {
3245 // CHECK9-NEXT:  entry:
3246 // CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
3247 // CHECK9-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3248 // CHECK9-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
3249 // CHECK9-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
3250 // CHECK9-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
3251 // CHECK9-NEXT:    [[VAR:%.*]] = alloca %struct.S.0*, align 4
3252 // CHECK9-NEXT:    [[TMP:%.*]] = alloca %struct.S.0*, align 4
3253 // CHECK9-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
3254 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3255 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3256 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3257 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
3258 // CHECK9-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
3259 // CHECK9-NEXT:    store i32 0, i32* [[T_VAR]], align 4
3260 // CHECK9-NEXT:    [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
3261 // CHECK9-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
3262 // CHECK9-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3263 // CHECK9-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
3264 // CHECK9-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
3265 // CHECK9-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
3266 // CHECK9-NEXT:    store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
3267 // CHECK9-NEXT:    [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
3268 // CHECK9-NEXT:    store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4
3269 // CHECK9-NEXT:    [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
3270 // CHECK9-NEXT:    [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
3271 // CHECK9-NEXT:    [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
3272 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
3273 // CHECK9-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
3274 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3275 // CHECK9-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
3276 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3277 // CHECK9:       omp.inner.for.cond:
3278 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3279 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
3280 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
3281 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3282 // CHECK9:       omp.inner.for.body:
3283 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3284 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
3285 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3286 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
3287 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !7
3288 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
3289 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP10]]
3290 // CHECK9-NEXT:    store i32 [[TMP9]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
3291 // CHECK9-NEXT:    [[TMP11:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4, !llvm.access.group !7
3292 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
3293 // CHECK9-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP12]]
3294 // CHECK9-NEXT:    [[TMP13:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8*
3295 // CHECK9-NEXT:    [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP11]] to i8*
3296 // CHECK9-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false), !llvm.access.group !7
3297 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3298 // CHECK9:       omp.body.continue:
3299 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3300 // CHECK9:       omp.inner.for.inc:
3301 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3302 // CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP15]], 1
3303 // CHECK9-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3304 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
3305 // CHECK9:       omp.inner.for.end:
3306 // CHECK9-NEXT:    store i32 2, i32* [[I]], align 4
3307 // CHECK9-NEXT:    store i32 0, i32* [[RETVAL]], align 4
3308 // CHECK9-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3309 // CHECK9-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
3310 // CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
3311 // CHECK9:       arraydestroy.body:
3312 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3313 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3314 // CHECK9-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3315 // CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
3316 // CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]]
3317 // CHECK9:       arraydestroy.done4:
3318 // CHECK9-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
3319 // CHECK9-NEXT:    [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4
3320 // CHECK9-NEXT:    ret i32 [[TMP17]]
3321 //
3322 //
3323 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3324 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3325 // CHECK9-NEXT:  entry:
3326 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3327 // CHECK9-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3328 // CHECK9-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3329 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3330 // CHECK9-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3331 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3332 // CHECK9-NEXT:    store float [[CONV]], float* [[F]], align 4
3333 // CHECK9-NEXT:    ret void
3334 //
3335 //
3336 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3337 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3338 // CHECK9-NEXT:  entry:
3339 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3340 // CHECK9-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3341 // CHECK9-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3342 // CHECK9-NEXT:    ret void
3343 //
3344 //
3345 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3346 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3347 // CHECK9-NEXT:  entry:
3348 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3349 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
3350 // CHECK9-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3351 // CHECK9-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
3352 // CHECK9-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3353 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3354 // CHECK9-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3355 // CHECK9-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3356 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3357 // CHECK9-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3358 // CHECK9-NEXT:    store float [[ADD]], float* [[F]], align 4
3359 // CHECK9-NEXT:    ret void
3360 //
3361 //
3362 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
3363 // CHECK9-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3364 // CHECK9-NEXT:  entry:
3365 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3366 // CHECK9-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3367 // CHECK9-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3368 // CHECK9-NEXT:    call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
3369 // CHECK9-NEXT:    ret void
3370 //
3371 //
3372 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
3373 // CHECK9-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3374 // CHECK9-NEXT:  entry:
3375 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3376 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3377 // CHECK9-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3378 // CHECK9-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3379 // CHECK9-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3380 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3381 // CHECK9-NEXT:    call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
3382 // CHECK9-NEXT:    ret void
3383 //
3384 //
3385 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
3386 // CHECK9-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3387 // CHECK9-NEXT:  entry:
3388 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3389 // CHECK9-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3390 // CHECK9-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3391 // CHECK9-NEXT:    call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3392 // CHECK9-NEXT:    ret void
3393 //
3394 //
3395 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
3396 // CHECK9-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3397 // CHECK9-NEXT:  entry:
3398 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3399 // CHECK9-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3400 // CHECK9-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3401 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3402 // CHECK9-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3403 // CHECK9-NEXT:    store i32 [[TMP0]], i32* [[F]], align 4
3404 // CHECK9-NEXT:    ret void
3405 //
3406 //
3407 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
3408 // CHECK9-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3409 // CHECK9-NEXT:  entry:
3410 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3411 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3412 // CHECK9-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3413 // CHECK9-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3414 // CHECK9-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3415 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3416 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3417 // CHECK9-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3418 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
3419 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[F]], align 4
3420 // CHECK9-NEXT:    ret void
3421 //
3422 //
3423 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
3424 // CHECK9-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3425 // CHECK9-NEXT:  entry:
3426 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3427 // CHECK9-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3428 // CHECK9-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3429 // CHECK9-NEXT:    ret void
3430 //
3431 //
3432 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
3433 // CHECK9-SAME: () #[[ATTR0]] {
3434 // CHECK9-NEXT:  entry:
3435 // CHECK9-NEXT:    call void @__cxx_global_var_init()
3436 // CHECK9-NEXT:    call void @__cxx_global_var_init.1()
3437 // CHECK9-NEXT:    call void @__cxx_global_var_init.2()
3438 // CHECK9-NEXT:    ret void
3439 //
3440 //
3441 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init
3442 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
3443 // CHECK11-NEXT:  entry:
3444 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
3445 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
3446 // CHECK11-NEXT:    ret void
3447 //
3448 //
3449 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3450 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3451 // CHECK11-NEXT:  entry:
3452 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3453 // CHECK11-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3454 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3455 // CHECK11-NEXT:    call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
3456 // CHECK11-NEXT:    ret void
3457 //
3458 //
3459 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3460 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3461 // CHECK11-NEXT:  entry:
3462 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3463 // CHECK11-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3464 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3465 // CHECK11-NEXT:    call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3466 // CHECK11-NEXT:    ret void
3467 //
3468 //
3469 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3470 // CHECK11-SAME: () #[[ATTR0]] {
3471 // CHECK11-NEXT:  entry:
3472 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
3473 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
3474 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
3475 // CHECK11-NEXT:    ret void
3476 //
3477 //
3478 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3479 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3480 // CHECK11-NEXT:  entry:
3481 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3482 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
3483 // CHECK11-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3484 // CHECK11-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
3485 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3486 // CHECK11-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3487 // CHECK11-NEXT:    call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
3488 // CHECK11-NEXT:    ret void
3489 //
3490 //
3491 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3492 // CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
3493 // CHECK11-NEXT:  entry:
3494 // CHECK11-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
3495 // CHECK11-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
3496 // CHECK11-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
3497 // CHECK11:       arraydestroy.body:
3498 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3499 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3500 // CHECK11-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3501 // CHECK11-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
3502 // CHECK11-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3503 // CHECK11:       arraydestroy.done1:
3504 // CHECK11-NEXT:    ret void
3505 //
3506 //
3507 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3508 // CHECK11-SAME: () #[[ATTR0]] {
3509 // CHECK11-NEXT:  entry:
3510 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
3511 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
3512 // CHECK11-NEXT:    ret void
3513 //
3514 //
3515 // CHECK11-LABEL: define {{[^@]+}}@main
3516 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
3517 // CHECK11-NEXT:  entry:
3518 // CHECK11-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
3519 // CHECK11-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
3520 // CHECK11-NEXT:    store i32 0, i32* [[RETVAL]], align 4
3521 // CHECK11-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
3522 // CHECK11-NEXT:    ret i32 0
3523 //
3524 //
3525 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3526 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3527 // CHECK11-NEXT:  entry:
3528 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3529 // CHECK11-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3530 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3531 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3532 // CHECK11-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3533 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3534 // CHECK11-NEXT:    store float [[CONV]], float* [[F]], align 4
3535 // CHECK11-NEXT:    ret void
3536 //
3537 //
3538 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3539 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3540 // CHECK11-NEXT:  entry:
3541 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3542 // CHECK11-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3543 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3544 // CHECK11-NEXT:    ret void
3545 //
3546 //
3547 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3548 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3549 // CHECK11-NEXT:  entry:
3550 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3551 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
3552 // CHECK11-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3553 // CHECK11-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
3554 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3555 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3556 // CHECK11-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3557 // CHECK11-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3558 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3559 // CHECK11-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3560 // CHECK11-NEXT:    store float [[ADD]], float* [[F]], align 4
3561 // CHECK11-NEXT:    ret void
3562 //
3563 //
3564 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
3565 // CHECK11-SAME: () #[[ATTR0]] {
3566 // CHECK11-NEXT:  entry:
3567 // CHECK11-NEXT:    call void @__cxx_global_var_init()
3568 // CHECK11-NEXT:    call void @__cxx_global_var_init.1()
3569 // CHECK11-NEXT:    call void @__cxx_global_var_init.2()
3570 // CHECK11-NEXT:    ret void
3571 //
3572 //
3573 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122
3574 // CHECK13-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] {
3575 // CHECK13-NEXT:  entry:
3576 // CHECK13-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
3577 // CHECK13-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
3578 // CHECK13-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
3579 // CHECK13-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
3580 // CHECK13-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
3581 // CHECK13-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
3582 // CHECK13-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8
3583 // CHECK13-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
3584 // CHECK13-NEXT:    store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
3585 // CHECK13-NEXT:    store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
3586 // CHECK13-NEXT:    store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
3587 // CHECK13-NEXT:    store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
3588 // CHECK13-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
3589 // CHECK13-NEXT:    [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
3590 // CHECK13-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
3591 // CHECK13-NEXT:    [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
3592 // CHECK13-NEXT:    [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
3593 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
3594 // CHECK13-NEXT:    [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
3595 // CHECK13-NEXT:    store i32 [[TMP3]], i32* [[CONV2]], align 4
3596 // CHECK13-NEXT:    [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
3597 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
3598 // CHECK13-NEXT:    [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
3599 // CHECK13-NEXT:    store i32 [[TMP5]], i32* [[CONV3]], align 4
3600 // CHECK13-NEXT:    [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
3601 // CHECK13-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
3602 // CHECK13-NEXT:    ret void
3603 //
3604 //
3605 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined.
3606 // CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] {
3607 // CHECK13-NEXT:  entry:
3608 // CHECK13-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3609 // CHECK13-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3610 // CHECK13-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
3611 // CHECK13-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
3612 // CHECK13-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
3613 // CHECK13-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
3614 // CHECK13-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
3615 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3616 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3617 // CHECK13-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3618 // CHECK13-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3619 // CHECK13-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3620 // CHECK13-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3621 // CHECK13-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 4
3622 // CHECK13-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4
3623 // CHECK13-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
3624 // CHECK13-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
3625 // CHECK13-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
3626 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
3627 // CHECK13-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
3628 // CHECK13-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8
3629 // CHECK13-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3630 // CHECK13-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3631 // CHECK13-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
3632 // CHECK13-NEXT:    store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
3633 // CHECK13-NEXT:    store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
3634 // CHECK13-NEXT:    store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
3635 // CHECK13-NEXT:    store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
3636 // CHECK13-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
3637 // CHECK13-NEXT:    [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
3638 // CHECK13-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
3639 // CHECK13-NEXT:    [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
3640 // CHECK13-NEXT:    [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
3641 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
3642 // CHECK13-NEXT:    store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
3643 // CHECK13-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3644 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3645 // CHECK13-NEXT:    [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
3646 // CHECK13-NEXT:    [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
3647 // CHECK13-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
3648 // CHECK13-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
3649 // CHECK13-NEXT:    [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
3650 // CHECK13-NEXT:    [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
3651 // CHECK13-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
3652 // CHECK13-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
3653 // CHECK13:       omp.arraycpy.body:
3654 // CHECK13-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3655 // CHECK13-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3656 // CHECK13-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]]
3657 // CHECK13-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]]
3658 // CHECK13-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]]
3659 // CHECK13-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
3660 // CHECK13-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
3661 // CHECK13-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
3662 // CHECK13-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
3663 // CHECK13:       omp.arraycpy.done4:
3664 // CHECK13-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
3665 // CHECK13-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]]
3666 // CHECK13-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]]
3667 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3668 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
3669 // CHECK13-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3670 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3671 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
3672 // CHECK13-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3673 // CHECK13:       cond.true:
3674 // CHECK13-NEXT:    br label [[COND_END:%.*]]
3675 // CHECK13:       cond.false:
3676 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3677 // CHECK13-NEXT:    br label [[COND_END]]
3678 // CHECK13:       cond.end:
3679 // CHECK13-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
3680 // CHECK13-NEXT:    store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
3681 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3682 // CHECK13-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
3683 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3684 // CHECK13:       omp.inner.for.cond:
3685 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3686 // CHECK13-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
3687 // CHECK13-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
3688 // CHECK13-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3689 // CHECK13:       omp.inner.for.cond.cleanup:
3690 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
3691 // CHECK13:       omp.inner.for.body:
3692 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
3693 // CHECK13-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
3694 // CHECK13-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
3695 // CHECK13-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
3696 // CHECK13-NEXT:    [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !6
3697 // CHECK13-NEXT:    [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
3698 // CHECK13-NEXT:    store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !6
3699 // CHECK13-NEXT:    [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !6
3700 // CHECK13-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !6
3701 // CHECK13-NEXT:    [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
3702 // CHECK13-NEXT:    store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !6
3703 // CHECK13-NEXT:    [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !6
3704 // CHECK13-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !6
3705 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3706 // CHECK13:       omp.inner.for.inc:
3707 // CHECK13-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3708 // CHECK13-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
3709 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
3710 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3711 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
3712 // CHECK13:       omp.inner.for.end:
3713 // CHECK13-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3714 // CHECK13:       omp.loop.exit:
3715 // CHECK13-NEXT:    [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3716 // CHECK13-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4
3717 // CHECK13-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]])
3718 // CHECK13-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3719 // CHECK13-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
3720 // CHECK13-NEXT:    br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3721 // CHECK13:       .omp.final.then:
3722 // CHECK13-NEXT:    store i32 2, i32* [[I]], align 4
3723 // CHECK13-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3724 // CHECK13:       .omp.final.done:
3725 // CHECK13-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]]
3726 // CHECK13-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
3727 // CHECK13-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2
3728 // CHECK13-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
3729 // CHECK13:       arraydestroy.body:
3730 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3731 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3732 // CHECK13-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
3733 // CHECK13-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
3734 // CHECK13-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
3735 // CHECK13:       arraydestroy.done11:
3736 // CHECK13-NEXT:    ret void
3737 //
3738 //
3739 // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC1Ev
3740 // CHECK13-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 {
3741 // CHECK13-NEXT:  entry:
3742 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
3743 // CHECK13-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
3744 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
3745 // CHECK13-NEXT:    call void @_ZN2StC2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
3746 // CHECK13-NEXT:    ret void
3747 //
3748 //
3749 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
3750 // CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
3751 // CHECK13-NEXT:  entry:
3752 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3753 // CHECK13-NEXT:    [[S_ADDR:%.*]] = alloca %struct.S*, align 8
3754 // CHECK13-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3755 // CHECK13-NEXT:    store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
3756 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3757 // CHECK13-NEXT:    [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
3758 // CHECK13-NEXT:    call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]]
3759 // CHECK13-NEXT:    ret void
3760 //
3761 //
3762 // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD1Ev
3763 // CHECK13-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
3764 // CHECK13-NEXT:  entry:
3765 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
3766 // CHECK13-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
3767 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
3768 // CHECK13-NEXT:    call void @_ZN2StD2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]]
3769 // CHECK13-NEXT:    ret void
3770 //
3771 //
3772 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1
3773 // CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] {
3774 // CHECK13-NEXT:  entry:
3775 // CHECK13-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3776 // CHECK13-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3777 // CHECK13-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
3778 // CHECK13-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
3779 // CHECK13-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
3780 // CHECK13-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
3781 // CHECK13-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
3782 // CHECK13-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
3783 // CHECK13-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
3784 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3785 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3786 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3787 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3788 // CHECK13-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3789 // CHECK13-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3790 // CHECK13-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 4
3791 // CHECK13-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4
3792 // CHECK13-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
3793 // CHECK13-NEXT:    [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4
3794 // CHECK13-NEXT:    [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
3795 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
3796 // CHECK13-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3797 // CHECK13-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3798 // CHECK13-NEXT:    store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
3799 // CHECK13-NEXT:    store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
3800 // CHECK13-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
3801 // CHECK13-NEXT:    store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
3802 // CHECK13-NEXT:    store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
3803 // CHECK13-NEXT:    store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
3804 // CHECK13-NEXT:    store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
3805 // CHECK13-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
3806 // CHECK13-NEXT:    [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
3807 // CHECK13-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
3808 // CHECK13-NEXT:    [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
3809 // CHECK13-NEXT:    [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
3810 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
3811 // CHECK13-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
3812 // CHECK13-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
3813 // CHECK13-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
3814 // CHECK13-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
3815 // CHECK13-NEXT:    [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
3816 // CHECK13-NEXT:    store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
3817 // CHECK13-NEXT:    store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
3818 // CHECK13-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3819 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3820 // CHECK13-NEXT:    [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
3821 // CHECK13-NEXT:    [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
3822 // CHECK13-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false)
3823 // CHECK13-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
3824 // CHECK13-NEXT:    [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
3825 // CHECK13-NEXT:    [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
3826 // CHECK13-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]]
3827 // CHECK13-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
3828 // CHECK13:       omp.arraycpy.body:
3829 // CHECK13-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3830 // CHECK13-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3831 // CHECK13-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
3832 // CHECK13-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]]
3833 // CHECK13-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]]
3834 // CHECK13-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
3835 // CHECK13-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
3836 // CHECK13-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
3837 // CHECK13-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
3838 // CHECK13:       omp.arraycpy.done6:
3839 // CHECK13-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]]
3840 // CHECK13-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]]
3841 // CHECK13-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]]
3842 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3843 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
3844 // CHECK13-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3845 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3846 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1
3847 // CHECK13-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3848 // CHECK13:       cond.true:
3849 // CHECK13-NEXT:    br label [[COND_END:%.*]]
3850 // CHECK13:       cond.false:
3851 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3852 // CHECK13-NEXT:    br label [[COND_END]]
3853 // CHECK13:       cond.end:
3854 // CHECK13-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
3855 // CHECK13-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3856 // CHECK13-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3857 // CHECK13-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
3858 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3859 // CHECK13:       omp.inner.for.cond:
3860 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
3861 // CHECK13-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
3862 // CHECK13-NEXT:    [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
3863 // CHECK13-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3864 // CHECK13:       omp.inner.for.cond.cleanup:
3865 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
3866 // CHECK13:       omp.inner.for.body:
3867 // CHECK13-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
3868 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
3869 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3870 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
3871 // CHECK13-NEXT:    [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !10
3872 // CHECK13-NEXT:    [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
3873 // CHECK13-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
3874 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
3875 // CHECK13-NEXT:    store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
3876 // CHECK13-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
3877 // CHECK13-NEXT:    [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
3878 // CHECK13-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
3879 // CHECK13-NEXT:    [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
3880 // CHECK13-NEXT:    [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
3881 // CHECK13-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !10
3882 // CHECK13-NEXT:    [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
3883 // CHECK13-NEXT:    [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !10
3884 // CHECK13-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
3885 // CHECK13-NEXT:    store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !10
3886 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3887 // CHECK13:       omp.body.continue:
3888 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3889 // CHECK13:       omp.inner.for.inc:
3890 // CHECK13-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
3891 // CHECK13-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
3892 // CHECK13-NEXT:    store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
3893 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
3894 // CHECK13:       omp.inner.for.end:
3895 // CHECK13-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3896 // CHECK13:       omp.loop.exit:
3897 // CHECK13-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3898 // CHECK13-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
3899 // CHECK13-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
3900 // CHECK13-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3901 // CHECK13-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
3902 // CHECK13-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3903 // CHECK13:       .omp.final.then:
3904 // CHECK13-NEXT:    store i32 2, i32* [[I]], align 4
3905 // CHECK13-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3906 // CHECK13:       .omp.final.done:
3907 // CHECK13-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]]
3908 // CHECK13-NEXT:    [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
3909 // CHECK13-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2
3910 // CHECK13-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
3911 // CHECK13:       arraydestroy.body:
3912 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3913 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3914 // CHECK13-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
3915 // CHECK13-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
3916 // CHECK13-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
3917 // CHECK13:       arraydestroy.done15:
3918 // CHECK13-NEXT:    ret void
3919 //
3920 //
3921 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3922 // CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
3923 // CHECK13-NEXT:  entry:
3924 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3925 // CHECK13-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3926 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3927 // CHECK13-NEXT:    call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
3928 // CHECK13-NEXT:    ret void
3929 //
3930 //
3931 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81
3932 // CHECK13-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] {
3933 // CHECK13-NEXT:  entry:
3934 // CHECK13-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
3935 // CHECK13-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
3936 // CHECK13-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
3937 // CHECK13-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
3938 // CHECK13-NEXT:    [[TMP:%.*]] = alloca %struct.S.0*, align 8
3939 // CHECK13-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
3940 // CHECK13-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
3941 // CHECK13-NEXT:    store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
3942 // CHECK13-NEXT:    store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
3943 // CHECK13-NEXT:    store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
3944 // CHECK13-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
3945 // CHECK13-NEXT:    [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
3946 // CHECK13-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
3947 // CHECK13-NEXT:    [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
3948 // CHECK13-NEXT:    store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
3949 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
3950 // CHECK13-NEXT:    [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
3951 // CHECK13-NEXT:    store i32 [[TMP3]], i32* [[CONV1]], align 4
3952 // CHECK13-NEXT:    [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
3953 // CHECK13-NEXT:    [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
3954 // CHECK13-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
3955 // CHECK13-NEXT:    ret void
3956 //
3957 //
3958 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2
3959 // CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] {
3960 // CHECK13-NEXT:  entry:
3961 // CHECK13-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3962 // CHECK13-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3963 // CHECK13-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
3964 // CHECK13-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
3965 // CHECK13-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
3966 // CHECK13-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
3967 // CHECK13-NEXT:    [[TMP:%.*]] = alloca %struct.S.0*, align 8
3968 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3969 // CHECK13-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
3970 // CHECK13-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3971 // CHECK13-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3972 // CHECK13-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3973 // CHECK13-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3974 // CHECK13-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 4
3975 // CHECK13-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
3976 // CHECK13-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
3977 // CHECK13-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3978 // CHECK13-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
3979 // CHECK13-NEXT:    [[_TMP7:%.*]] = alloca %struct.S.0*, align 8
3980 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
3981 // CHECK13-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
3982 // CHECK13-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3983 // CHECK13-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3984 // CHECK13-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
3985 // CHECK13-NEXT:    store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
3986 // CHECK13-NEXT:    store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
3987 // CHECK13-NEXT:    store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
3988 // CHECK13-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
3989 // CHECK13-NEXT:    [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
3990 // CHECK13-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
3991 // CHECK13-NEXT:    [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
3992 // CHECK13-NEXT:    store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
3993 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
3994 // CHECK13-NEXT:    store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
3995 // CHECK13-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3996 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3997 // CHECK13-NEXT:    [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
3998 // CHECK13-NEXT:    [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
3999 // CHECK13-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
4000 // CHECK13-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
4001 // CHECK13-NEXT:    [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
4002 // CHECK13-NEXT:    [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
4003 // CHECK13-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
4004 // CHECK13-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
4005 // CHECK13:       omp.arraycpy.body:
4006 // CHECK13-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4007 // CHECK13-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4008 // CHECK13-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
4009 // CHECK13-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]]
4010 // CHECK13-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]]
4011 // CHECK13-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
4012 // CHECK13-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
4013 // CHECK13-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
4014 // CHECK13-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
4015 // CHECK13:       omp.arraycpy.done4:
4016 // CHECK13-NEXT:    [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
4017 // CHECK13-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
4018 // CHECK13-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]]
4019 // CHECK13-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]]
4020 // CHECK13-NEXT:    store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8
4021 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4022 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
4023 // CHECK13-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4024 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4025 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
4026 // CHECK13-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4027 // CHECK13:       cond.true:
4028 // CHECK13-NEXT:    br label [[COND_END:%.*]]
4029 // CHECK13:       cond.false:
4030 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4031 // CHECK13-NEXT:    br label [[COND_END]]
4032 // CHECK13:       cond.end:
4033 // CHECK13-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
4034 // CHECK13-NEXT:    store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
4035 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
4036 // CHECK13-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
4037 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4038 // CHECK13:       omp.inner.for.cond:
4039 // CHECK13-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
4040 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
4041 // CHECK13-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
4042 // CHECK13-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
4043 // CHECK13:       omp.inner.for.cond.cleanup:
4044 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
4045 // CHECK13:       omp.inner.for.body:
4046 // CHECK13-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
4047 // CHECK13-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
4048 // CHECK13-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
4049 // CHECK13-NEXT:    [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
4050 // CHECK13-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !15
4051 // CHECK13-NEXT:    [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
4052 // CHECK13-NEXT:    store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !15
4053 // CHECK13-NEXT:    [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !15
4054 // CHECK13-NEXT:    [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !15
4055 // CHECK13-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !15
4056 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4057 // CHECK13:       omp.inner.for.inc:
4058 // CHECK13-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
4059 // CHECK13-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
4060 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
4061 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
4062 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
4063 // CHECK13:       omp.inner.for.end:
4064 // CHECK13-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4065 // CHECK13:       omp.loop.exit:
4066 // CHECK13-NEXT:    [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4067 // CHECK13-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4
4068 // CHECK13-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]])
4069 // CHECK13-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4070 // CHECK13-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
4071 // CHECK13-NEXT:    br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4072 // CHECK13:       .omp.final.then:
4073 // CHECK13-NEXT:    store i32 2, i32* [[I]], align 4
4074 // CHECK13-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4075 // CHECK13:       .omp.final.done:
4076 // CHECK13-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]]
4077 // CHECK13-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
4078 // CHECK13-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2
4079 // CHECK13-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
4080 // CHECK13:       arraydestroy.body:
4081 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4082 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4083 // CHECK13-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
4084 // CHECK13-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
4085 // CHECK13-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
4086 // CHECK13:       arraydestroy.done11:
4087 // CHECK13-NEXT:    ret void
4088 //
4089 //
4090 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
4091 // CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4092 // CHECK13-NEXT:  entry:
4093 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
4094 // CHECK13-NEXT:    [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
4095 // CHECK13-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
4096 // CHECK13-NEXT:    store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
4097 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
4098 // CHECK13-NEXT:    [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
4099 // CHECK13-NEXT:    call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]]
4100 // CHECK13-NEXT:    ret void
4101 //
4102 //
4103 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3
4104 // CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] {
4105 // CHECK13-NEXT:  entry:
4106 // CHECK13-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4107 // CHECK13-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4108 // CHECK13-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
4109 // CHECK13-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
4110 // CHECK13-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
4111 // CHECK13-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
4112 // CHECK13-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
4113 // CHECK13-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
4114 // CHECK13-NEXT:    [[TMP:%.*]] = alloca %struct.S.0*, align 8
4115 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4116 // CHECK13-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
4117 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4118 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4119 // CHECK13-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4120 // CHECK13-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4121 // CHECK13-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 4
4122 // CHECK13-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4
4123 // CHECK13-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
4124 // CHECK13-NEXT:    [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
4125 // CHECK13-NEXT:    [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
4126 // CHECK13-NEXT:    [[_TMP9:%.*]] = alloca %struct.S.0*, align 8
4127 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
4128 // CHECK13-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4129 // CHECK13-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4130 // CHECK13-NEXT:    store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
4131 // CHECK13-NEXT:    store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
4132 // CHECK13-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
4133 // CHECK13-NEXT:    store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
4134 // CHECK13-NEXT:    store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
4135 // CHECK13-NEXT:    store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
4136 // CHECK13-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
4137 // CHECK13-NEXT:    [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
4138 // CHECK13-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
4139 // CHECK13-NEXT:    [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
4140 // CHECK13-NEXT:    store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
4141 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4142 // CHECK13-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
4143 // CHECK13-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
4144 // CHECK13-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
4145 // CHECK13-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
4146 // CHECK13-NEXT:    [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
4147 // CHECK13-NEXT:    store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
4148 // CHECK13-NEXT:    store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
4149 // CHECK13-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4150 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4151 // CHECK13-NEXT:    [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
4152 // CHECK13-NEXT:    [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
4153 // CHECK13-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false)
4154 // CHECK13-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
4155 // CHECK13-NEXT:    [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
4156 // CHECK13-NEXT:    [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
4157 // CHECK13-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
4158 // CHECK13-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
4159 // CHECK13:       omp.arraycpy.body:
4160 // CHECK13-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4161 // CHECK13-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4162 // CHECK13-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
4163 // CHECK13-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]]
4164 // CHECK13-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]]
4165 // CHECK13-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
4166 // CHECK13-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
4167 // CHECK13-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
4168 // CHECK13-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
4169 // CHECK13:       omp.arraycpy.done6:
4170 // CHECK13-NEXT:    [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
4171 // CHECK13-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]]
4172 // CHECK13-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]]
4173 // CHECK13-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]]
4174 // CHECK13-NEXT:    store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8
4175 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4176 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
4177 // CHECK13-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4178 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4179 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
4180 // CHECK13-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4181 // CHECK13:       cond.true:
4182 // CHECK13-NEXT:    br label [[COND_END:%.*]]
4183 // CHECK13:       cond.false:
4184 // CHECK13-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4185 // CHECK13-NEXT:    br label [[COND_END]]
4186 // CHECK13:       cond.end:
4187 // CHECK13-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
4188 // CHECK13-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4189 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4190 // CHECK13-NEXT:    store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
4191 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4192 // CHECK13:       omp.inner.for.cond:
4193 // CHECK13-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
4194 // CHECK13-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
4195 // CHECK13-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
4196 // CHECK13-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
4197 // CHECK13:       omp.inner.for.cond.cleanup:
4198 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
4199 // CHECK13:       omp.inner.for.body:
4200 // CHECK13-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
4201 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
4202 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4203 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
4204 // CHECK13-NEXT:    [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !18
4205 // CHECK13-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
4206 // CHECK13-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
4207 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
4208 // CHECK13-NEXT:    store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
4209 // CHECK13-NEXT:    [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !18
4210 // CHECK13-NEXT:    [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
4211 // CHECK13-NEXT:    [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
4212 // CHECK13-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
4213 // CHECK13-NEXT:    [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8*
4214 // CHECK13-NEXT:    [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8*
4215 // CHECK13-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false), !llvm.access.group !18
4216 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4217 // CHECK13:       omp.body.continue:
4218 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4219 // CHECK13:       omp.inner.for.inc:
4220 // CHECK13-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
4221 // CHECK13-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
4222 // CHECK13-NEXT:    store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
4223 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
4224 // CHECK13:       omp.inner.for.end:
4225 // CHECK13-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4226 // CHECK13:       omp.loop.exit:
4227 // CHECK13-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4228 // CHECK13-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
4229 // CHECK13-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
4230 // CHECK13-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4231 // CHECK13-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
4232 // CHECK13-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4233 // CHECK13:       .omp.final.then:
4234 // CHECK13-NEXT:    store i32 2, i32* [[I]], align 4
4235 // CHECK13-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4236 // CHECK13:       .omp.final.done:
4237 // CHECK13-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]]
4238 // CHECK13-NEXT:    [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
4239 // CHECK13-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2
4240 // CHECK13-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
4241 // CHECK13:       arraydestroy.body:
4242 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4243 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4244 // CHECK13-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
4245 // CHECK13-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
4246 // CHECK13-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
4247 // CHECK13:       arraydestroy.done15:
4248 // CHECK13-NEXT:    ret void
4249 //
4250 //
4251 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
4252 // CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4253 // CHECK13-NEXT:  entry:
4254 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
4255 // CHECK13-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
4256 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
4257 // CHECK13-NEXT:    call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
4258 // CHECK13-NEXT:    ret void
4259 //
4260 //
4261 // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC2Ev
4262 // CHECK13-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4263 // CHECK13-NEXT:  entry:
4264 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
4265 // CHECK13-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
4266 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
4267 // CHECK13-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
4268 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
4269 // CHECK13-NEXT:    [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
4270 // CHECK13-NEXT:    store i32 0, i32* [[B]], align 4
4271 // CHECK13-NEXT:    ret void
4272 //
4273 //
4274 // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD2Ev
4275 // CHECK13-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4276 // CHECK13-NEXT:  entry:
4277 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
4278 // CHECK13-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
4279 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
4280 // CHECK13-NEXT:    ret void
4281 //
4282 //
4283 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
4284 // CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4285 // CHECK13-NEXT:  entry:
4286 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4287 // CHECK13-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4288 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4289 // CHECK13-NEXT:    ret void
4290 //
4291 //
4292 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
4293 // CHECK13-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4294 // CHECK13-NEXT:  entry:
4295 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4296 // CHECK13-NEXT:    [[S_ADDR:%.*]] = alloca %struct.S*, align 8
4297 // CHECK13-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4298 // CHECK13-NEXT:    store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
4299 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4300 // CHECK13-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4301 // CHECK13-NEXT:    [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
4302 // CHECK13-NEXT:    [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
4303 // CHECK13-NEXT:    [[TMP1:%.*]] = load float, float* [[F2]], align 4
4304 // CHECK13-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
4305 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
4306 // CHECK13-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
4307 // CHECK13-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
4308 // CHECK13-NEXT:    store float [[ADD]], float* [[F]], align 4
4309 // CHECK13-NEXT:    ret void
4310 //
4311 //
4312 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
4313 // CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4314 // CHECK13-NEXT:  entry:
4315 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
4316 // CHECK13-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
4317 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
4318 // CHECK13-NEXT:    ret void
4319 //
4320 //
4321 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
4322 // CHECK13-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4323 // CHECK13-NEXT:  entry:
4324 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
4325 // CHECK13-NEXT:    [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
4326 // CHECK13-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
4327 // CHECK13-NEXT:    store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
4328 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
4329 // CHECK13-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4330 // CHECK13-NEXT:    [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
4331 // CHECK13-NEXT:    [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
4332 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
4333 // CHECK13-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
4334 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
4335 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
4336 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[F]], align 4
4337 // CHECK13-NEXT:    ret void
4338 //
4339 //
4340 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122
4341 // CHECK15-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] {
4342 // CHECK15-NEXT:  entry:
4343 // CHECK15-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
4344 // CHECK15-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
4345 // CHECK15-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
4346 // CHECK15-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
4347 // CHECK15-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 4
4348 // CHECK15-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
4349 // CHECK15-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 4
4350 // CHECK15-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
4351 // CHECK15-NEXT:    store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
4352 // CHECK15-NEXT:    store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
4353 // CHECK15-NEXT:    store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
4354 // CHECK15-NEXT:    store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
4355 // CHECK15-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
4356 // CHECK15-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
4357 // CHECK15-NEXT:    [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
4358 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
4359 // CHECK15-NEXT:    store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
4360 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
4361 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
4362 // CHECK15-NEXT:    store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4
4363 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
4364 // CHECK15-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]])
4365 // CHECK15-NEXT:    ret void
4366 //
4367 //
4368 // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined.
4369 // CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0]] {
4370 // CHECK15-NEXT:  entry:
4371 // CHECK15-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4372 // CHECK15-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4373 // CHECK15-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
4374 // CHECK15-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
4375 // CHECK15-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
4376 // CHECK15-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
4377 // CHECK15-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 4
4378 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4379 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4380 // CHECK15-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
4381 // CHECK15-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
4382 // CHECK15-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4383 // CHECK15-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4384 // CHECK15-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 4
4385 // CHECK15-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
4386 // CHECK15-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
4387 // CHECK15-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
4388 // CHECK15-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
4389 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
4390 // CHECK15-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
4391 // CHECK15-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 4
4392 // CHECK15-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4393 // CHECK15-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4394 // CHECK15-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
4395 // CHECK15-NEXT:    store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
4396 // CHECK15-NEXT:    store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
4397 // CHECK15-NEXT:    store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
4398 // CHECK15-NEXT:    store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
4399 // CHECK15-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
4400 // CHECK15-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
4401 // CHECK15-NEXT:    [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
4402 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
4403 // CHECK15-NEXT:    store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
4404 // CHECK15-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4405 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4406 // CHECK15-NEXT:    [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
4407 // CHECK15-NEXT:    [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
4408 // CHECK15-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
4409 // CHECK15-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
4410 // CHECK15-NEXT:    [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
4411 // CHECK15-NEXT:    [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
4412 // CHECK15-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
4413 // CHECK15-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
4414 // CHECK15:       omp.arraycpy.body:
4415 // CHECK15-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4416 // CHECK15-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4417 // CHECK15-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]]
4418 // CHECK15-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]]
4419 // CHECK15-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]]
4420 // CHECK15-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
4421 // CHECK15-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
4422 // CHECK15-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
4423 // CHECK15-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
4424 // CHECK15:       omp.arraycpy.done3:
4425 // CHECK15-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]
4426 // CHECK15-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]]
4427 // CHECK15-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]]
4428 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4429 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
4430 // CHECK15-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4431 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4432 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
4433 // CHECK15-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4434 // CHECK15:       cond.true:
4435 // CHECK15-NEXT:    br label [[COND_END:%.*]]
4436 // CHECK15:       cond.false:
4437 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4438 // CHECK15-NEXT:    br label [[COND_END]]
4439 // CHECK15:       cond.end:
4440 // CHECK15-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
4441 // CHECK15-NEXT:    store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
4442 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
4443 // CHECK15-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
4444 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4445 // CHECK15:       omp.inner.for.cond:
4446 // CHECK15-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4447 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7
4448 // CHECK15-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
4449 // CHECK15-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
4450 // CHECK15:       omp.inner.for.cond.cleanup:
4451 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
4452 // CHECK15:       omp.inner.for.body:
4453 // CHECK15-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !7
4454 // CHECK15-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7
4455 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !7
4456 // CHECK15-NEXT:    store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !7
4457 // CHECK15-NEXT:    [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !7
4458 // CHECK15-NEXT:    [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !7
4459 // CHECK15-NEXT:    store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4, !llvm.access.group !7
4460 // CHECK15-NEXT:    [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4, !llvm.access.group !7
4461 // CHECK15-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]), !llvm.access.group !7
4462 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4463 // CHECK15:       omp.inner.for.inc:
4464 // CHECK15-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4465 // CHECK15-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !7
4466 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
4467 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4468 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
4469 // CHECK15:       omp.inner.for.end:
4470 // CHECK15-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4471 // CHECK15:       omp.loop.exit:
4472 // CHECK15-NEXT:    [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4473 // CHECK15-NEXT:    [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
4474 // CHECK15-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
4475 // CHECK15-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4476 // CHECK15-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
4477 // CHECK15-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4478 // CHECK15:       .omp.final.then:
4479 // CHECK15-NEXT:    store i32 2, i32* [[I]], align 4
4480 // CHECK15-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4481 // CHECK15:       .omp.final.done:
4482 // CHECK15-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]]
4483 // CHECK15-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
4484 // CHECK15-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2
4485 // CHECK15-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
4486 // CHECK15:       arraydestroy.body:
4487 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4488 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4489 // CHECK15-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
4490 // CHECK15-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
4491 // CHECK15-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
4492 // CHECK15:       arraydestroy.done8:
4493 // CHECK15-NEXT:    ret void
4494 //
4495 //
4496 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC1Ev
4497 // CHECK15-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 {
4498 // CHECK15-NEXT:  entry:
4499 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
4500 // CHECK15-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
4501 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
4502 // CHECK15-NEXT:    call void @_ZN2StC2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
4503 // CHECK15-NEXT:    ret void
4504 //
4505 //
4506 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
4507 // CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4508 // CHECK15-NEXT:  entry:
4509 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4510 // CHECK15-NEXT:    [[S_ADDR:%.*]] = alloca %struct.S*, align 4
4511 // CHECK15-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4512 // CHECK15-NEXT:    store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
4513 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4514 // CHECK15-NEXT:    [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
4515 // CHECK15-NEXT:    call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]]
4516 // CHECK15-NEXT:    ret void
4517 //
4518 //
4519 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD1Ev
4520 // CHECK15-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4521 // CHECK15-NEXT:  entry:
4522 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
4523 // CHECK15-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
4524 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
4525 // CHECK15-NEXT:    call void @_ZN2StD2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]]
4526 // CHECK15-NEXT:    ret void
4527 //
4528 //
4529 // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1
4530 // CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0]] {
4531 // CHECK15-NEXT:  entry:
4532 // CHECK15-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4533 // CHECK15-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4534 // CHECK15-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
4535 // CHECK15-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
4536 // CHECK15-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
4537 // CHECK15-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
4538 // CHECK15-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
4539 // CHECK15-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
4540 // CHECK15-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 4
4541 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4542 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4543 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4544 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4545 // CHECK15-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4546 // CHECK15-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4547 // CHECK15-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 4
4548 // CHECK15-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
4549 // CHECK15-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
4550 // CHECK15-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
4551 // CHECK15-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
4552 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
4553 // CHECK15-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4554 // CHECK15-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4555 // CHECK15-NEXT:    store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
4556 // CHECK15-NEXT:    store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
4557 // CHECK15-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
4558 // CHECK15-NEXT:    store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
4559 // CHECK15-NEXT:    store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
4560 // CHECK15-NEXT:    store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
4561 // CHECK15-NEXT:    store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
4562 // CHECK15-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
4563 // CHECK15-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
4564 // CHECK15-NEXT:    [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
4565 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4566 // CHECK15-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
4567 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
4568 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
4569 // CHECK15-NEXT:    store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
4570 // CHECK15-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
4571 // CHECK15-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4572 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4573 // CHECK15-NEXT:    [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
4574 // CHECK15-NEXT:    [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
4575 // CHECK15-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false)
4576 // CHECK15-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
4577 // CHECK15-NEXT:    [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
4578 // CHECK15-NEXT:    [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
4579 // CHECK15-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]]
4580 // CHECK15-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
4581 // CHECK15:       omp.arraycpy.body:
4582 // CHECK15-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4583 // CHECK15-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4584 // CHECK15-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
4585 // CHECK15-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]]
4586 // CHECK15-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]]
4587 // CHECK15-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
4588 // CHECK15-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
4589 // CHECK15-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
4590 // CHECK15-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
4591 // CHECK15:       omp.arraycpy.done3:
4592 // CHECK15-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]
4593 // CHECK15-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]]
4594 // CHECK15-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]]
4595 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4596 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
4597 // CHECK15-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4598 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4599 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1
4600 // CHECK15-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4601 // CHECK15:       cond.true:
4602 // CHECK15-NEXT:    br label [[COND_END:%.*]]
4603 // CHECK15:       cond.false:
4604 // CHECK15-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4605 // CHECK15-NEXT:    br label [[COND_END]]
4606 // CHECK15:       cond.end:
4607 // CHECK15-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
4608 // CHECK15-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4609 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4610 // CHECK15-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
4611 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4612 // CHECK15:       omp.inner.for.cond:
4613 // CHECK15-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
4614 // CHECK15-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
4615 // CHECK15-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
4616 // CHECK15-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
4617 // CHECK15:       omp.inner.for.cond.cleanup:
4618 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
4619 // CHECK15:       omp.inner.for.body:
4620 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
4621 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
4622 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4623 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
4624 // CHECK15-NEXT:    [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !11
4625 // CHECK15-NEXT:    [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
4626 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]]
4627 // CHECK15-NEXT:    store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
4628 // CHECK15-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
4629 // CHECK15-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]]
4630 // CHECK15-NEXT:    [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
4631 // CHECK15-NEXT:    [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8*
4632 // CHECK15-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !11
4633 // CHECK15-NEXT:    [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
4634 // CHECK15-NEXT:    [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !11
4635 // CHECK15-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
4636 // CHECK15-NEXT:    store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !11
4637 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4638 // CHECK15:       omp.body.continue:
4639 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4640 // CHECK15:       omp.inner.for.inc:
4641 // CHECK15-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
4642 // CHECK15-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1
4643 // CHECK15-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
4644 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
4645 // CHECK15:       omp.inner.for.end:
4646 // CHECK15-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4647 // CHECK15:       omp.loop.exit:
4648 // CHECK15-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4649 // CHECK15-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
4650 // CHECK15-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
4651 // CHECK15-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4652 // CHECK15-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
4653 // CHECK15-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4654 // CHECK15:       .omp.final.then:
4655 // CHECK15-NEXT:    store i32 2, i32* [[I]], align 4
4656 // CHECK15-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4657 // CHECK15:       .omp.final.done:
4658 // CHECK15-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]]
4659 // CHECK15-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
4660 // CHECK15-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2
4661 // CHECK15-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
4662 // CHECK15:       arraydestroy.body:
4663 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4664 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4665 // CHECK15-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
4666 // CHECK15-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
4667 // CHECK15-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
4668 // CHECK15:       arraydestroy.done11:
4669 // CHECK15-NEXT:    ret void
4670 //
4671 //
4672 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
4673 // CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4674 // CHECK15-NEXT:  entry:
4675 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4676 // CHECK15-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4677 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4678 // CHECK15-NEXT:    call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
4679 // CHECK15-NEXT:    ret void
4680 //
4681 //
4682 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81
4683 // CHECK15-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] {
4684 // CHECK15-NEXT:  entry:
4685 // CHECK15-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
4686 // CHECK15-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
4687 // CHECK15-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
4688 // CHECK15-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
4689 // CHECK15-NEXT:    [[TMP:%.*]] = alloca %struct.S.0*, align 4
4690 // CHECK15-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
4691 // CHECK15-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
4692 // CHECK15-NEXT:    store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
4693 // CHECK15-NEXT:    store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4694 // CHECK15-NEXT:    store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
4695 // CHECK15-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
4696 // CHECK15-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4697 // CHECK15-NEXT:    [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
4698 // CHECK15-NEXT:    store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
4699 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
4700 // CHECK15-NEXT:    store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
4701 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
4702 // CHECK15-NEXT:    [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
4703 // CHECK15-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
4704 // CHECK15-NEXT:    ret void
4705 //
4706 //
4707 // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2
4708 // CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] {
4709 // CHECK15-NEXT:  entry:
4710 // CHECK15-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4711 // CHECK15-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4712 // CHECK15-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
4713 // CHECK15-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
4714 // CHECK15-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
4715 // CHECK15-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
4716 // CHECK15-NEXT:    [[TMP:%.*]] = alloca %struct.S.0*, align 4
4717 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4718 // CHECK15-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
4719 // CHECK15-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
4720 // CHECK15-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
4721 // CHECK15-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4722 // CHECK15-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4723 // CHECK15-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 4
4724 // CHECK15-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
4725 // CHECK15-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
4726 // CHECK15-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
4727 // CHECK15-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
4728 // CHECK15-NEXT:    [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
4729 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
4730 // CHECK15-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
4731 // CHECK15-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4732 // CHECK15-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4733 // CHECK15-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
4734 // CHECK15-NEXT:    store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
4735 // CHECK15-NEXT:    store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4736 // CHECK15-NEXT:    store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
4737 // CHECK15-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
4738 // CHECK15-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4739 // CHECK15-NEXT:    [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
4740 // CHECK15-NEXT:    store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
4741 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
4742 // CHECK15-NEXT:    store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
4743 // CHECK15-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4744 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4745 // CHECK15-NEXT:    [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
4746 // CHECK15-NEXT:    [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
4747 // CHECK15-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
4748 // CHECK15-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
4749 // CHECK15-NEXT:    [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
4750 // CHECK15-NEXT:    [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
4751 // CHECK15-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
4752 // CHECK15-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
4753 // CHECK15:       omp.arraycpy.body:
4754 // CHECK15-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4755 // CHECK15-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4756 // CHECK15-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
4757 // CHECK15-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]]
4758 // CHECK15-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]]
4759 // CHECK15-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
4760 // CHECK15-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
4761 // CHECK15-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
4762 // CHECK15-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
4763 // CHECK15:       omp.arraycpy.done4:
4764 // CHECK15-NEXT:    [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
4765 // CHECK15-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
4766 // CHECK15-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]]
4767 // CHECK15-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]]
4768 // CHECK15-NEXT:    store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
4769 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4770 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
4771 // CHECK15-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4772 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4773 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
4774 // CHECK15-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4775 // CHECK15:       cond.true:
4776 // CHECK15-NEXT:    br label [[COND_END:%.*]]
4777 // CHECK15:       cond.false:
4778 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4779 // CHECK15-NEXT:    br label [[COND_END]]
4780 // CHECK15:       cond.end:
4781 // CHECK15-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
4782 // CHECK15-NEXT:    store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
4783 // CHECK15-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
4784 // CHECK15-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
4785 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4786 // CHECK15:       omp.inner.for.cond:
4787 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
4788 // CHECK15-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16
4789 // CHECK15-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
4790 // CHECK15-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
4791 // CHECK15:       omp.inner.for.cond.cleanup:
4792 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
4793 // CHECK15:       omp.inner.for.body:
4794 // CHECK15-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !16
4795 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16
4796 // CHECK15-NEXT:    [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !16
4797 // CHECK15-NEXT:    store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !16
4798 // CHECK15-NEXT:    [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !16
4799 // CHECK15-NEXT:    [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !16
4800 // CHECK15-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]), !llvm.access.group !16
4801 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4802 // CHECK15:       omp.inner.for.inc:
4803 // CHECK15-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
4804 // CHECK15-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !16
4805 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
4806 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
4807 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
4808 // CHECK15:       omp.inner.for.end:
4809 // CHECK15-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4810 // CHECK15:       omp.loop.exit:
4811 // CHECK15-NEXT:    [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4812 // CHECK15-NEXT:    [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
4813 // CHECK15-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
4814 // CHECK15-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4815 // CHECK15-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
4816 // CHECK15-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4817 // CHECK15:       .omp.final.then:
4818 // CHECK15-NEXT:    store i32 2, i32* [[I]], align 4
4819 // CHECK15-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4820 // CHECK15:       .omp.final.done:
4821 // CHECK15-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]]
4822 // CHECK15-NEXT:    [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
4823 // CHECK15-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2
4824 // CHECK15-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
4825 // CHECK15:       arraydestroy.body:
4826 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4827 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4828 // CHECK15-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
4829 // CHECK15-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
4830 // CHECK15-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
4831 // CHECK15:       arraydestroy.done10:
4832 // CHECK15-NEXT:    ret void
4833 //
4834 //
4835 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
4836 // CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4837 // CHECK15-NEXT:  entry:
4838 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4839 // CHECK15-NEXT:    [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
4840 // CHECK15-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4841 // CHECK15-NEXT:    store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
4842 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4843 // CHECK15-NEXT:    [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
4844 // CHECK15-NEXT:    call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]]
4845 // CHECK15-NEXT:    ret void
4846 //
4847 //
4848 // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3
4849 // CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] {
4850 // CHECK15-NEXT:  entry:
4851 // CHECK15-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4852 // CHECK15-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4853 // CHECK15-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
4854 // CHECK15-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
4855 // CHECK15-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
4856 // CHECK15-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
4857 // CHECK15-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
4858 // CHECK15-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
4859 // CHECK15-NEXT:    [[TMP:%.*]] = alloca %struct.S.0*, align 4
4860 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4861 // CHECK15-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
4862 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4863 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4864 // CHECK15-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4865 // CHECK15-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4866 // CHECK15-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 4
4867 // CHECK15-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
4868 // CHECK15-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
4869 // CHECK15-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
4870 // CHECK15-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
4871 // CHECK15-NEXT:    [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
4872 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
4873 // CHECK15-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4874 // CHECK15-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4875 // CHECK15-NEXT:    store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
4876 // CHECK15-NEXT:    store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
4877 // CHECK15-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
4878 // CHECK15-NEXT:    store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
4879 // CHECK15-NEXT:    store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4880 // CHECK15-NEXT:    store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
4881 // CHECK15-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
4882 // CHECK15-NEXT:    [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4883 // CHECK15-NEXT:    [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
4884 // CHECK15-NEXT:    store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
4885 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4886 // CHECK15-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
4887 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
4888 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
4889 // CHECK15-NEXT:    store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
4890 // CHECK15-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
4891 // CHECK15-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4892 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4893 // CHECK15-NEXT:    [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
4894 // CHECK15-NEXT:    [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
4895 // CHECK15-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false)
4896 // CHECK15-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
4897 // CHECK15-NEXT:    [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
4898 // CHECK15-NEXT:    [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
4899 // CHECK15-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
4900 // CHECK15-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
4901 // CHECK15:       omp.arraycpy.body:
4902 // CHECK15-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4903 // CHECK15-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4904 // CHECK15-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
4905 // CHECK15-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]]
4906 // CHECK15-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]]
4907 // CHECK15-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
4908 // CHECK15-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
4909 // CHECK15-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
4910 // CHECK15-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
4911 // CHECK15:       omp.arraycpy.done4:
4912 // CHECK15-NEXT:    [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
4913 // CHECK15-NEXT:    call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
4914 // CHECK15-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]]
4915 // CHECK15-NEXT:    call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]]
4916 // CHECK15-NEXT:    store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
4917 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4918 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
4919 // CHECK15-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4920 // CHECK15-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4921 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
4922 // CHECK15-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4923 // CHECK15:       cond.true:
4924 // CHECK15-NEXT:    br label [[COND_END:%.*]]
4925 // CHECK15:       cond.false:
4926 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4927 // CHECK15-NEXT:    br label [[COND_END]]
4928 // CHECK15:       cond.end:
4929 // CHECK15-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
4930 // CHECK15-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4931 // CHECK15-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4932 // CHECK15-NEXT:    store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
4933 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4934 // CHECK15:       omp.inner.for.cond:
4935 // CHECK15-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
4936 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
4937 // CHECK15-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
4938 // CHECK15-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
4939 // CHECK15:       omp.inner.for.cond.cleanup:
4940 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
4941 // CHECK15:       omp.inner.for.body:
4942 // CHECK15-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
4943 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
4944 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4945 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
4946 // CHECK15-NEXT:    [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !19
4947 // CHECK15-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
4948 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]]
4949 // CHECK15-NEXT:    store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !19
4950 // CHECK15-NEXT:    [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !19
4951 // CHECK15-NEXT:    [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
4952 // CHECK15-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]]
4953 // CHECK15-NEXT:    [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8*
4954 // CHECK15-NEXT:    [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8*
4955 // CHECK15-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false), !llvm.access.group !19
4956 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4957 // CHECK15:       omp.body.continue:
4958 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4959 // CHECK15:       omp.inner.for.inc:
4960 // CHECK15-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
4961 // CHECK15-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
4962 // CHECK15-NEXT:    store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
4963 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
4964 // CHECK15:       omp.inner.for.end:
4965 // CHECK15-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4966 // CHECK15:       omp.loop.exit:
4967 // CHECK15-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4968 // CHECK15-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
4969 // CHECK15-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
4970 // CHECK15-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4971 // CHECK15-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
4972 // CHECK15-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4973 // CHECK15:       .omp.final.then:
4974 // CHECK15-NEXT:    store i32 2, i32* [[I]], align 4
4975 // CHECK15-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4976 // CHECK15:       .omp.final.done:
4977 // CHECK15-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]]
4978 // CHECK15-NEXT:    [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
4979 // CHECK15-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
4980 // CHECK15-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
4981 // CHECK15:       arraydestroy.body:
4982 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4983 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4984 // CHECK15-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
4985 // CHECK15-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
4986 // CHECK15-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
4987 // CHECK15:       arraydestroy.done12:
4988 // CHECK15-NEXT:    ret void
4989 //
4990 //
4991 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
4992 // CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4993 // CHECK15-NEXT:  entry:
4994 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4995 // CHECK15-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4996 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4997 // CHECK15-NEXT:    call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
4998 // CHECK15-NEXT:    ret void
4999 //
5000 //
5001 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC2Ev
5002 // CHECK15-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5003 // CHECK15-NEXT:  entry:
5004 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
5005 // CHECK15-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
5006 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
5007 // CHECK15-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
5008 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
5009 // CHECK15-NEXT:    [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
5010 // CHECK15-NEXT:    store i32 0, i32* [[B]], align 4
5011 // CHECK15-NEXT:    ret void
5012 //
5013 //
5014 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD2Ev
5015 // CHECK15-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5016 // CHECK15-NEXT:  entry:
5017 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
5018 // CHECK15-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
5019 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
5020 // CHECK15-NEXT:    ret void
5021 //
5022 //
5023 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
5024 // CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5025 // CHECK15-NEXT:  entry:
5026 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
5027 // CHECK15-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
5028 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
5029 // CHECK15-NEXT:    ret void
5030 //
5031 //
5032 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
5033 // CHECK15-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5034 // CHECK15-NEXT:  entry:
5035 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
5036 // CHECK15-NEXT:    [[S_ADDR:%.*]] = alloca %struct.S*, align 4
5037 // CHECK15-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
5038 // CHECK15-NEXT:    store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
5039 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
5040 // CHECK15-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5041 // CHECK15-NEXT:    [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
5042 // CHECK15-NEXT:    [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
5043 // CHECK15-NEXT:    [[TMP1:%.*]] = load float, float* [[F2]], align 4
5044 // CHECK15-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
5045 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
5046 // CHECK15-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
5047 // CHECK15-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
5048 // CHECK15-NEXT:    store float [[ADD]], float* [[F]], align 4
5049 // CHECK15-NEXT:    ret void
5050 //
5051 //
5052 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
5053 // CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5054 // CHECK15-NEXT:  entry:
5055 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
5056 // CHECK15-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
5057 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
5058 // CHECK15-NEXT:    ret void
5059 //
5060 //
5061 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
5062 // CHECK15-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5063 // CHECK15-NEXT:  entry:
5064 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
5065 // CHECK15-NEXT:    [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
5066 // CHECK15-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
5067 // CHECK15-NEXT:    store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
5068 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
5069 // CHECK15-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
5070 // CHECK15-NEXT:    [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
5071 // CHECK15-NEXT:    [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
5072 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
5073 // CHECK15-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
5074 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
5075 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
5076 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[F]], align 4
5077 // CHECK15-NEXT:    ret void
5078 //
5079 //
5080 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99
5081 // CHECK17-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] {
5082 // CHECK17-NEXT:  entry:
5083 // CHECK17-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 8
5084 // CHECK17-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8
5085 // CHECK17-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
5086 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32*, align 8
5087 // CHECK17-NEXT:    [[G_CASTED:%.*]] = alloca i64, align 8
5088 // CHECK17-NEXT:    [[G1_CASTED:%.*]] = alloca i64, align 8
5089 // CHECK17-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8
5090 // CHECK17-NEXT:    store i64 [[G]], i64* [[G_ADDR]], align 8
5091 // CHECK17-NEXT:    store i64 [[G1]], i64* [[G1_ADDR]], align 8
5092 // CHECK17-NEXT:    store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
5093 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
5094 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
5095 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
5096 // CHECK17-NEXT:    store i32* [[CONV1]], i32** [[TMP]], align 8
5097 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
5098 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
5099 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[CONV3]], align 4
5100 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
5101 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
5102 // CHECK17-NEXT:    [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
5103 // CHECK17-NEXT:    [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
5104 // CHECK17-NEXT:    store i32 [[TMP3]], i32* [[CONV4]], align 4
5105 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
5106 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
5107 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
5108 // CHECK17-NEXT:    store i32 [[TMP5]], i32* [[CONV5]], align 4
5109 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
5110 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
5111 // CHECK17-NEXT:    ret void
5112 //
5113 //
5114 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
5115 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] {
5116 // CHECK17-NEXT:  entry:
5117 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5118 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5119 // CHECK17-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 8
5120 // CHECK17-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8
5121 // CHECK17-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
5122 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32*, align 8
5123 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5124 // CHECK17-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
5125 // CHECK17-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
5126 // CHECK17-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
5127 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5128 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5129 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
5130 // CHECK17-NEXT:    [[G_CASTED:%.*]] = alloca i64, align 8
5131 // CHECK17-NEXT:    [[G1_CASTED:%.*]] = alloca i64, align 8
5132 // CHECK17-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8
5133 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5134 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5135 // CHECK17-NEXT:    store i64 [[G]], i64* [[G_ADDR]], align 8
5136 // CHECK17-NEXT:    store i64 [[G1]], i64* [[G1_ADDR]], align 8
5137 // CHECK17-NEXT:    store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
5138 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
5139 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
5140 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
5141 // CHECK17-NEXT:    store i32* [[CONV1]], i32** [[TMP]], align 8
5142 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
5143 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
5144 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5145 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5146 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5147 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
5148 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5149 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5150 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
5151 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5152 // CHECK17:       cond.true:
5153 // CHECK17-NEXT:    br label [[COND_END:%.*]]
5154 // CHECK17:       cond.false:
5155 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5156 // CHECK17-NEXT:    br label [[COND_END]]
5157 // CHECK17:       cond.end:
5158 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
5159 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
5160 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
5161 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
5162 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5163 // CHECK17:       omp.inner.for.cond:
5164 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
5165 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
5166 // CHECK17-NEXT:    [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
5167 // CHECK17-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5168 // CHECK17:       omp.inner.for.body:
5169 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
5170 // CHECK17-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
5171 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
5172 // CHECK17-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
5173 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
5174 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
5175 // CHECK17-NEXT:    store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !5
5176 // CHECK17-NEXT:    [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !5
5177 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !5
5178 // CHECK17-NEXT:    [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4, !llvm.access.group !5
5179 // CHECK17-NEXT:    [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
5180 // CHECK17-NEXT:    store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !5
5181 // CHECK17-NEXT:    [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !5
5182 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4, !llvm.access.group !5
5183 // CHECK17-NEXT:    [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
5184 // CHECK17-NEXT:    store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !5
5185 // CHECK17-NEXT:    [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5
5186 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !5
5187 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5188 // CHECK17:       omp.inner.for.inc:
5189 // CHECK17-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
5190 // CHECK17-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
5191 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
5192 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
5193 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
5194 // CHECK17:       omp.inner.for.end:
5195 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5196 // CHECK17:       omp.loop.exit:
5197 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
5198 // CHECK17-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5199 // CHECK17-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
5200 // CHECK17-NEXT:    br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5201 // CHECK17:       .omp.final.then:
5202 // CHECK17-NEXT:    store i32 2, i32* [[I]], align 4
5203 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5204 // CHECK17:       .omp.final.done:
5205 // CHECK17-NEXT:    ret void
5206 //
5207 //
5208 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1
5209 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] {
5210 // CHECK17-NEXT:  entry:
5211 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5212 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5213 // CHECK17-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
5214 // CHECK17-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
5215 // CHECK17-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 8
5216 // CHECK17-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8
5217 // CHECK17-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
5218 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32*, align 8
5219 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5220 // CHECK17-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
5221 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5222 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5223 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5224 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5225 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
5226 // CHECK17-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
5227 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5228 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5229 // CHECK17-NEXT:    store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
5230 // CHECK17-NEXT:    store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
5231 // CHECK17-NEXT:    store i64 [[G]], i64* [[G_ADDR]], align 8
5232 // CHECK17-NEXT:    store i64 [[G1]], i64* [[G1_ADDR]], align 8
5233 // CHECK17-NEXT:    store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
5234 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
5235 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
5236 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
5237 // CHECK17-NEXT:    store i32* [[CONV1]], i32** [[TMP]], align 8
5238 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5239 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_UB]], align 4
5240 // CHECK17-NEXT:    [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
5241 // CHECK17-NEXT:    [[CONV4:%.*]] = trunc i64 [[TMP0]] to i32
5242 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
5243 // CHECK17-NEXT:    [[CONV5:%.*]] = trunc i64 [[TMP1]] to i32
5244 // CHECK17-NEXT:    store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
5245 // CHECK17-NEXT:    store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
5246 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5247 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5248 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5249 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
5250 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5251 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5252 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
5253 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5254 // CHECK17:       cond.true:
5255 // CHECK17-NEXT:    br label [[COND_END:%.*]]
5256 // CHECK17:       cond.false:
5257 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5258 // CHECK17-NEXT:    br label [[COND_END]]
5259 // CHECK17:       cond.end:
5260 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
5261 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5262 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5263 // CHECK17-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
5264 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5265 // CHECK17:       omp.inner.for.cond:
5266 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
5267 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
5268 // CHECK17-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
5269 // CHECK17-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5270 // CHECK17:       omp.inner.for.body:
5271 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
5272 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
5273 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5274 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
5275 // CHECK17-NEXT:    store i32 1, i32* [[CONV]], align 4, !llvm.access.group !9
5276 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !9
5277 // CHECK17-NEXT:    store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !9
5278 // CHECK17-NEXT:    store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !9
5279 // CHECK17-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0
5280 // CHECK17-NEXT:    store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !9
5281 // CHECK17-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1
5282 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !9
5283 // CHECK17-NEXT:    store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !9
5284 // CHECK17-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2
5285 // CHECK17-NEXT:    store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !9
5286 // CHECK17-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]], !llvm.access.group !9
5287 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5288 // CHECK17:       omp.body.continue:
5289 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5290 // CHECK17:       omp.inner.for.inc:
5291 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
5292 // CHECK17-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1
5293 // CHECK17-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
5294 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
5295 // CHECK17:       omp.inner.for.end:
5296 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5297 // CHECK17:       omp.loop.exit:
5298 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
5299 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5300 // CHECK17-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
5301 // CHECK17-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5302 // CHECK17:       .omp.final.then:
5303 // CHECK17-NEXT:    store i32 2, i32* [[I]], align 4
5304 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5305 // CHECK17:       .omp.final.done:
5306 // CHECK17-NEXT:    ret void
5307 //
5308