1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
8
9 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5
12
13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
15 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
16 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
17 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
19
20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
23
24 // expected-no-diagnostics
25 #ifndef HEADER
26 #define HEADER
27
28 template <typename T>
tmain()29 T tmain() {
30 T t_var = T();
31 T vec[] = {1, 2};
32 #pragma omp target teams distribute parallel for reduction(+: t_var)
33 for (int i = 0; i < 2; ++i) {
34 t_var += (T) i;
35 }
36 return T();
37 }
38
main()39 int main() {
40 static int sivar;
41 #ifdef LAMBDA
42
43 [&]() {
44 #pragma omp target teams distribute parallel for reduction(+: sivar)
45 for (int i = 0; i < 2; ++i) {
46
47 // Skip global and bound tid vars
48
49
50
51 // Skip global and bound tid vars, and prev lb and ub vars
52 // skip loop vars
53
54
55 sivar += i;
56
57 [&]() {
58
59 sivar += 4;
60
61 }();
62 }
63 }();
64 return 0;
65 #else
66 #pragma omp target teams distribute parallel for reduction(+: sivar)
67 for (int i = 0; i < 2; ++i) {
68 sivar += i;
69 }
70 return tmain<int>();
71 #endif
72 }
73
74
75
76
77 // Skip global and bound tid vars
78
79
80 // Skip global and bound tid vars, and prev lb and ub
81 // skip loop vars
82
83
84
85
86 // Skip global and bound tid vars
87
88
89 // Skip global and bound tid vars, and prev lb and ub vars
90 // skip loop vars
91
92 #endif
93 // CHECK1-LABEL: define {{[^@]+}}@main
94 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
95 // CHECK1-NEXT: entry:
96 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
97 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
98 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
99 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
100 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
101 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
102 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
103 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to i32**
104 // CHECK1-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP1]], align 8
105 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
106 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32**
107 // CHECK1-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP3]], align 8
108 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
109 // CHECK1-NEXT: store i8* null, i8** [[TMP4]], align 8
110 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
111 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
112 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
113 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
114 // CHECK1-NEXT: store i32 1, i32* [[TMP7]], align 4
115 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
116 // CHECK1-NEXT: store i32 1, i32* [[TMP8]], align 4
117 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
118 // CHECK1-NEXT: store i8** [[TMP5]], i8*** [[TMP9]], align 8
119 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
120 // CHECK1-NEXT: store i8** [[TMP6]], i8*** [[TMP10]], align 8
121 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
122 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP11]], align 8
123 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
124 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP12]], align 8
125 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
126 // CHECK1-NEXT: store i8** null, i8*** [[TMP13]], align 8
127 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
128 // CHECK1-NEXT: store i8** null, i8*** [[TMP14]], align 8
129 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
130 // CHECK1-NEXT: store i64 2, i64* [[TMP15]], align 8
131 // CHECK1-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
132 // CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
133 // CHECK1-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
134 // CHECK1: omp_offload.failed:
135 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66(i32* @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]]
136 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
137 // CHECK1: omp_offload.cont:
138 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
139 // CHECK1-NEXT: ret i32 [[CALL]]
140 //
141 //
142 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66
143 // CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] {
144 // CHECK1-NEXT: entry:
145 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8
146 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8
147 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8
148 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]])
149 // CHECK1-NEXT: ret void
150 //
151 //
152 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
153 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] {
154 // CHECK1-NEXT: entry:
155 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
156 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
157 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8
158 // CHECK1-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4
159 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
160 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
161 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
162 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
163 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
164 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
165 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
166 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8
167 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
168 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
169 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8
170 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8
171 // CHECK1-NEXT: store i32 0, i32* [[SIVAR1]], align 4
172 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
173 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
174 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
175 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
176 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
177 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
178 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
179 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
180 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
181 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
182 // CHECK1: cond.true:
183 // CHECK1-NEXT: br label [[COND_END:%.*]]
184 // CHECK1: cond.false:
185 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
186 // CHECK1-NEXT: br label [[COND_END]]
187 // CHECK1: cond.end:
188 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
189 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
190 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
191 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
192 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
193 // CHECK1: omp.inner.for.cond:
194 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
195 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
196 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
197 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
198 // CHECK1: omp.inner.for.body:
199 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
200 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
201 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
202 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
203 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]])
204 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
205 // CHECK1: omp.inner.for.inc:
206 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
207 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
208 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
209 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
210 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
211 // CHECK1: omp.inner.for.end:
212 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
213 // CHECK1: omp.loop.exit:
214 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
215 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
216 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8*
217 // CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8
218 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
219 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var)
220 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
221 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
222 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
223 // CHECK1-NEXT: ]
224 // CHECK1: .omp.reduction.case1:
225 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4
226 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4
227 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
228 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[TMP0]], align 4
229 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
230 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
231 // CHECK1: .omp.reduction.case2:
232 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4
233 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4
234 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
235 // CHECK1: .omp.reduction.default:
236 // CHECK1-NEXT: ret void
237 //
238 //
239 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
240 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] {
241 // CHECK1-NEXT: entry:
242 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
243 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
244 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
245 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
246 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8
247 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
248 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
249 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
250 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
251 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
252 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
253 // CHECK1-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4
254 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
255 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8
256 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
257 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
258 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
259 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
260 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8
261 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8
262 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
263 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
264 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
265 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
266 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
267 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32
268 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
269 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
270 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
271 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
272 // CHECK1-NEXT: store i32 0, i32* [[SIVAR2]], align 4
273 // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
274 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
275 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
276 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
277 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
278 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
279 // CHECK1: cond.true:
280 // CHECK1-NEXT: br label [[COND_END:%.*]]
281 // CHECK1: cond.false:
282 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
283 // CHECK1-NEXT: br label [[COND_END]]
284 // CHECK1: cond.end:
285 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
286 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
287 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
288 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
289 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
290 // CHECK1: omp.inner.for.cond:
291 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
292 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
293 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
294 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
295 // CHECK1: omp.inner.for.body:
296 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
297 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
298 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
299 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
300 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
301 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4
302 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
303 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4
304 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
305 // CHECK1: omp.body.continue:
306 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
307 // CHECK1: omp.inner.for.inc:
308 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
309 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1
310 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
311 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
312 // CHECK1: omp.inner.for.end:
313 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
314 // CHECK1: omp.loop.exit:
315 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
316 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
317 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR2]] to i8*
318 // CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8
319 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
320 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var)
321 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
322 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
323 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
324 // CHECK1-NEXT: ]
325 // CHECK1: .omp.reduction.case1:
326 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4
327 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR2]], align 4
328 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
329 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[TMP0]], align 4
330 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], [8 x i32]* @.gomp_critical_user_.reduction.var)
331 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
332 // CHECK1: .omp.reduction.case2:
333 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR2]], align 4
334 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4
335 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
336 // CHECK1: .omp.reduction.default:
337 // CHECK1-NEXT: ret void
338 //
339 //
340 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
341 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
342 // CHECK1-NEXT: entry:
343 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
344 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8
345 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
346 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8
347 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8
348 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
349 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8
350 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
351 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0
352 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
353 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
354 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0
355 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8
356 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
357 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
358 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
359 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
360 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
361 // CHECK1-NEXT: ret void
362 //
363 //
364 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2
365 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] {
366 // CHECK1-NEXT: entry:
367 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
368 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8
369 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
370 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8
371 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8
372 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
373 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8
374 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
375 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0
376 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
377 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
378 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0
379 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8
380 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
381 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
382 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
383 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
384 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
385 // CHECK1-NEXT: ret void
386 //
387 //
388 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
389 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] comdat {
390 // CHECK1-NEXT: entry:
391 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
392 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
393 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
394 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
395 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
396 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
397 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4
398 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
399 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
400 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
401 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32**
402 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 8
403 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
404 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32**
405 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 8
406 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
407 // CHECK1-NEXT: store i8* null, i8** [[TMP5]], align 8
408 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
409 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
410 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
411 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
412 // CHECK1-NEXT: store i32 1, i32* [[TMP8]], align 4
413 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
414 // CHECK1-NEXT: store i32 1, i32* [[TMP9]], align 4
415 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
416 // CHECK1-NEXT: store i8** [[TMP6]], i8*** [[TMP10]], align 8
417 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
418 // CHECK1-NEXT: store i8** [[TMP7]], i8*** [[TMP11]], align 8
419 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
420 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP12]], align 8
421 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
422 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP13]], align 8
423 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
424 // CHECK1-NEXT: store i8** null, i8*** [[TMP14]], align 8
425 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
426 // CHECK1-NEXT: store i8** null, i8*** [[TMP15]], align 8
427 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
428 // CHECK1-NEXT: store i64 2, i64* [[TMP16]], align 8
429 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB4]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
430 // CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
431 // CHECK1-NEXT: br i1 [[TMP18]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
432 // CHECK1: omp_offload.failed:
433 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32* [[T_VAR]]) #[[ATTR2]]
434 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
435 // CHECK1: omp_offload.cont:
436 // CHECK1-NEXT: ret i32 0
437 //
438 //
439 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32
440 // CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {
441 // CHECK1-NEXT: entry:
442 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
443 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
444 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
445 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[TMP0]])
446 // CHECK1-NEXT: ret void
447 //
448 //
449 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
450 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {
451 // CHECK1-NEXT: entry:
452 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
453 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
454 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
455 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4
456 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
457 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
458 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
459 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
460 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
461 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
462 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
463 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8
464 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
465 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
466 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
467 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
468 // CHECK1-NEXT: store i32 0, i32* [[T_VAR1]], align 4
469 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
470 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
471 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
472 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
473 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
474 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
475 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
476 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
477 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
478 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
479 // CHECK1: cond.true:
480 // CHECK1-NEXT: br label [[COND_END:%.*]]
481 // CHECK1: cond.false:
482 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
483 // CHECK1-NEXT: br label [[COND_END]]
484 // CHECK1: cond.end:
485 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
486 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
487 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
488 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
489 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
490 // CHECK1: omp.inner.for.cond:
491 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
492 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
493 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
494 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
495 // CHECK1: omp.inner.for.body:
496 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
497 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
498 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
499 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
500 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[T_VAR1]])
501 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
502 // CHECK1: omp.inner.for.inc:
503 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
504 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
505 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
506 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
507 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
508 // CHECK1: omp.inner.for.end:
509 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
510 // CHECK1: omp.loop.exit:
511 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
512 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
513 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i32* [[T_VAR1]] to i8*
514 // CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8
515 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
516 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.6, [8 x i32]* @.gomp_critical_user_.reduction.var)
517 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
518 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
519 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
520 // CHECK1-NEXT: ]
521 // CHECK1: .omp.reduction.case1:
522 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4
523 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR1]], align 4
524 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
525 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[TMP0]], align 4
526 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
527 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
528 // CHECK1: .omp.reduction.case2:
529 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[T_VAR1]], align 4
530 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4
531 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
532 // CHECK1: .omp.reduction.default:
533 // CHECK1-NEXT: ret void
534 //
535 //
536 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
537 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {
538 // CHECK1-NEXT: entry:
539 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
540 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
541 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
542 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
543 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
544 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
545 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
546 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
547 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
548 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
549 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
550 // CHECK1-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
551 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
552 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8
553 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
554 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
555 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
556 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
557 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
558 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
559 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
560 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
561 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
562 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
563 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
564 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32
565 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
566 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
567 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
568 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
569 // CHECK1-NEXT: store i32 0, i32* [[T_VAR2]], align 4
570 // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
571 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
572 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
573 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
574 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
575 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
576 // CHECK1: cond.true:
577 // CHECK1-NEXT: br label [[COND_END:%.*]]
578 // CHECK1: cond.false:
579 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
580 // CHECK1-NEXT: br label [[COND_END]]
581 // CHECK1: cond.end:
582 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
583 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
584 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
585 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
586 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
587 // CHECK1: omp.inner.for.cond:
588 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
589 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
590 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
591 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
592 // CHECK1: omp.inner.for.body:
593 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
594 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
595 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
596 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
597 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
598 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4
599 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
600 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[T_VAR2]], align 4
601 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
602 // CHECK1: omp.body.continue:
603 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
604 // CHECK1: omp.inner.for.inc:
605 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
606 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1
607 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
608 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
609 // CHECK1: omp.inner.for.end:
610 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
611 // CHECK1: omp.loop.exit:
612 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
613 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
614 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i32* [[T_VAR2]] to i8*
615 // CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8
616 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
617 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.5, [8 x i32]* @.gomp_critical_user_.reduction.var)
618 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
619 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
620 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
621 // CHECK1-NEXT: ]
622 // CHECK1: .omp.reduction.case1:
623 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4
624 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR2]], align 4
625 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
626 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[TMP0]], align 4
627 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], [8 x i32]* @.gomp_critical_user_.reduction.var)
628 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
629 // CHECK1: .omp.reduction.case2:
630 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[T_VAR2]], align 4
631 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4
632 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
633 // CHECK1: .omp.reduction.default:
634 // CHECK1-NEXT: ret void
635 //
636 //
637 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5
638 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] {
639 // CHECK1-NEXT: entry:
640 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
641 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8
642 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
643 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8
644 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8
645 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
646 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8
647 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
648 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0
649 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
650 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
651 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0
652 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8
653 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
654 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
655 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
656 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
657 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
658 // CHECK1-NEXT: ret void
659 //
660 //
661 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6
662 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] {
663 // CHECK1-NEXT: entry:
664 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
665 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8
666 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
667 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8
668 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8
669 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
670 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8
671 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
672 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0
673 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
674 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
675 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0
676 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8
677 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
678 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
679 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
680 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
681 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
682 // CHECK1-NEXT: ret void
683 //
684 //
685 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
686 // CHECK1-SAME: () #[[ATTR7:[0-9]+]] {
687 // CHECK1-NEXT: entry:
688 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
689 // CHECK1-NEXT: ret void
690 //
691 //
692 // CHECK3-LABEL: define {{[^@]+}}@main
693 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
694 // CHECK3-NEXT: entry:
695 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
696 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
697 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
698 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
699 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
700 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
701 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
702 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to i32**
703 // CHECK3-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP1]], align 4
704 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
705 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32**
706 // CHECK3-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP3]], align 4
707 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
708 // CHECK3-NEXT: store i8* null, i8** [[TMP4]], align 4
709 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
710 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
711 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
712 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
713 // CHECK3-NEXT: store i32 1, i32* [[TMP7]], align 4
714 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
715 // CHECK3-NEXT: store i32 1, i32* [[TMP8]], align 4
716 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
717 // CHECK3-NEXT: store i8** [[TMP5]], i8*** [[TMP9]], align 4
718 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
719 // CHECK3-NEXT: store i8** [[TMP6]], i8*** [[TMP10]], align 4
720 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
721 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP11]], align 4
722 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
723 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP12]], align 4
724 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
725 // CHECK3-NEXT: store i8** null, i8*** [[TMP13]], align 4
726 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
727 // CHECK3-NEXT: store i8** null, i8*** [[TMP14]], align 4
728 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
729 // CHECK3-NEXT: store i64 2, i64* [[TMP15]], align 8
730 // CHECK3-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
731 // CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
732 // CHECK3-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
733 // CHECK3: omp_offload.failed:
734 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66(i32* @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]]
735 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
736 // CHECK3: omp_offload.cont:
737 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
738 // CHECK3-NEXT: ret i32 [[CALL]]
739 //
740 //
741 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66
742 // CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] {
743 // CHECK3-NEXT: entry:
744 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4
745 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4
746 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4
747 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]])
748 // CHECK3-NEXT: ret void
749 //
750 //
751 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
752 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] {
753 // CHECK3-NEXT: entry:
754 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
755 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
756 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4
757 // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4
758 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
759 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
760 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
761 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
762 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
763 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
764 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
765 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4
766 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
767 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
768 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4
769 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4
770 // CHECK3-NEXT: store i32 0, i32* [[SIVAR1]], align 4
771 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
772 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
773 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
774 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
775 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
776 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
777 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
778 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
779 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
780 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
781 // CHECK3: cond.true:
782 // CHECK3-NEXT: br label [[COND_END:%.*]]
783 // CHECK3: cond.false:
784 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
785 // CHECK3-NEXT: br label [[COND_END]]
786 // CHECK3: cond.end:
787 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
788 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
789 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
790 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
791 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
792 // CHECK3: omp.inner.for.cond:
793 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
794 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
795 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
796 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
797 // CHECK3: omp.inner.for.body:
798 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
799 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
800 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[SIVAR1]])
801 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
802 // CHECK3: omp.inner.for.inc:
803 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
804 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
805 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
806 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
807 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
808 // CHECK3: omp.inner.for.end:
809 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
810 // CHECK3: omp.loop.exit:
811 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
812 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0
813 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i32* [[SIVAR1]] to i8*
814 // CHECK3-NEXT: store i8* [[TMP13]], i8** [[TMP12]], align 4
815 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
816 // CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i32 4, i8* [[TMP14]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var)
817 // CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
818 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
819 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
820 // CHECK3-NEXT: ]
821 // CHECK3: .omp.reduction.case1:
822 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP0]], align 4
823 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[SIVAR1]], align 4
824 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
825 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[TMP0]], align 4
826 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
827 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
828 // CHECK3: .omp.reduction.case2:
829 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR1]], align 4
830 // CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP18]] monotonic, align 4
831 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
832 // CHECK3: .omp.reduction.default:
833 // CHECK3-NEXT: ret void
834 //
835 //
836 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
837 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] {
838 // CHECK3-NEXT: entry:
839 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
840 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
841 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
842 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
843 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4
844 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
845 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
846 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
847 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
848 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
849 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
850 // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4
851 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
852 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4
853 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
854 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
855 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
856 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
857 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4
858 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4
859 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
860 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
861 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
862 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
863 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4
864 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
865 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
866 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
867 // CHECK3-NEXT: store i32 0, i32* [[SIVAR1]], align 4
868 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
869 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
870 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
871 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
872 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
873 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
874 // CHECK3: cond.true:
875 // CHECK3-NEXT: br label [[COND_END:%.*]]
876 // CHECK3: cond.false:
877 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
878 // CHECK3-NEXT: br label [[COND_END]]
879 // CHECK3: cond.end:
880 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
881 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
882 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
883 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
884 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
885 // CHECK3: omp.inner.for.cond:
886 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
887 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
888 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
889 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
890 // CHECK3: omp.inner.for.body:
891 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
892 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
893 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
894 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
895 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
896 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR1]], align 4
897 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
898 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4
899 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
900 // CHECK3: omp.body.continue:
901 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
902 // CHECK3: omp.inner.for.inc:
903 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
904 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
905 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
906 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
907 // CHECK3: omp.inner.for.end:
908 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
909 // CHECK3: omp.loop.exit:
910 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
911 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0
912 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8*
913 // CHECK3-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 4
914 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
915 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var)
916 // CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
917 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
918 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
919 // CHECK3-NEXT: ]
920 // CHECK3: .omp.reduction.case1:
921 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4
922 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4
923 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
924 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4
925 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], [8 x i32]* @.gomp_critical_user_.reduction.var)
926 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
927 // CHECK3: .omp.reduction.case2:
928 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4
929 // CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4
930 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
931 // CHECK3: .omp.reduction.default:
932 // CHECK3-NEXT: ret void
933 //
934 //
935 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
936 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
937 // CHECK3-NEXT: entry:
938 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
939 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4
940 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
941 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4
942 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4
943 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
944 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4
945 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
946 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0
947 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
948 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
949 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0
950 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4
951 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
952 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
953 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
954 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
955 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
956 // CHECK3-NEXT: ret void
957 //
958 //
959 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2
960 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] {
961 // CHECK3-NEXT: entry:
962 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
963 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4
964 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
965 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4
966 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4
967 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
968 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4
969 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
970 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0
971 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
972 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
973 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0
974 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4
975 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
976 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
977 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
978 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
979 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
980 // CHECK3-NEXT: ret void
981 //
982 //
983 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
984 // CHECK3-SAME: () #[[ATTR5:[0-9]+]] comdat {
985 // CHECK3-NEXT: entry:
986 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
987 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
988 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
989 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
990 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
991 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
992 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4
993 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
994 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
995 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
996 // CHECK3-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32**
997 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 4
998 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
999 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32**
1000 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 4
1001 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1002 // CHECK3-NEXT: store i8* null, i8** [[TMP5]], align 4
1003 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1004 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1005 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1006 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1007 // CHECK3-NEXT: store i32 1, i32* [[TMP8]], align 4
1008 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1009 // CHECK3-NEXT: store i32 1, i32* [[TMP9]], align 4
1010 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1011 // CHECK3-NEXT: store i8** [[TMP6]], i8*** [[TMP10]], align 4
1012 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1013 // CHECK3-NEXT: store i8** [[TMP7]], i8*** [[TMP11]], align 4
1014 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1015 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP12]], align 4
1016 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1017 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP13]], align 4
1018 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1019 // CHECK3-NEXT: store i8** null, i8*** [[TMP14]], align 4
1020 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1021 // CHECK3-NEXT: store i8** null, i8*** [[TMP15]], align 4
1022 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1023 // CHECK3-NEXT: store i64 2, i64* [[TMP16]], align 8
1024 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB4]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1025 // CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
1026 // CHECK3-NEXT: br i1 [[TMP18]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1027 // CHECK3: omp_offload.failed:
1028 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32* [[T_VAR]]) #[[ATTR2]]
1029 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1030 // CHECK3: omp_offload.cont:
1031 // CHECK3-NEXT: ret i32 0
1032 //
1033 //
1034 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32
1035 // CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {
1036 // CHECK3-NEXT: entry:
1037 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4
1038 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4
1039 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4
1040 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[TMP0]])
1041 // CHECK3-NEXT: ret void
1042 //
1043 //
1044 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
1045 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {
1046 // CHECK3-NEXT: entry:
1047 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1048 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1049 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4
1050 // CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4
1051 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1052 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1053 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1054 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1055 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1056 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1057 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1058 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4
1059 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1060 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1061 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4
1062 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4
1063 // CHECK3-NEXT: store i32 0, i32* [[T_VAR1]], align 4
1064 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1065 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1066 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1067 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1068 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1069 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
1070 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1071 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1072 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
1073 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1074 // CHECK3: cond.true:
1075 // CHECK3-NEXT: br label [[COND_END:%.*]]
1076 // CHECK3: cond.false:
1077 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1078 // CHECK3-NEXT: br label [[COND_END]]
1079 // CHECK3: cond.end:
1080 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1081 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1082 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1083 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
1084 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1085 // CHECK3: omp.inner.for.cond:
1086 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1087 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1088 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
1089 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1090 // CHECK3: omp.inner.for.body:
1091 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1092 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1093 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[T_VAR1]])
1094 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1095 // CHECK3: omp.inner.for.inc:
1096 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1097 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1098 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
1099 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1100 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
1101 // CHECK3: omp.inner.for.end:
1102 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1103 // CHECK3: omp.loop.exit:
1104 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
1105 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0
1106 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i32* [[T_VAR1]] to i8*
1107 // CHECK3-NEXT: store i8* [[TMP13]], i8** [[TMP12]], align 4
1108 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
1109 // CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 1, i32 4, i8* [[TMP14]], void (i8*, i8*)* @.omp.reduction.reduction_func.6, [8 x i32]* @.gomp_critical_user_.reduction.var)
1110 // CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
1111 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
1112 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
1113 // CHECK3-NEXT: ]
1114 // CHECK3: .omp.reduction.case1:
1115 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP0]], align 4
1116 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR1]], align 4
1117 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
1118 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[TMP0]], align 4
1119 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
1120 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
1121 // CHECK3: .omp.reduction.case2:
1122 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR1]], align 4
1123 // CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP18]] monotonic, align 4
1124 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
1125 // CHECK3: .omp.reduction.default:
1126 // CHECK3-NEXT: ret void
1127 //
1128 //
1129 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
1130 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {
1131 // CHECK3-NEXT: entry:
1132 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1133 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1134 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
1135 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
1136 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4
1137 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1138 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1139 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1140 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1141 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1142 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1143 // CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4
1144 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1145 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4
1146 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1147 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1148 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1149 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1150 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4
1151 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4
1152 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1153 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1154 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1155 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1156 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4
1157 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
1158 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1159 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1160 // CHECK3-NEXT: store i32 0, i32* [[T_VAR1]], align 4
1161 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1162 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
1163 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1164 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1165 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
1166 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1167 // CHECK3: cond.true:
1168 // CHECK3-NEXT: br label [[COND_END:%.*]]
1169 // CHECK3: cond.false:
1170 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1171 // CHECK3-NEXT: br label [[COND_END]]
1172 // CHECK3: cond.end:
1173 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
1174 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1175 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1176 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
1177 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1178 // CHECK3: omp.inner.for.cond:
1179 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1180 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1181 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
1182 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1183 // CHECK3: omp.inner.for.body:
1184 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1185 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
1186 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1187 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1188 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
1189 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR1]], align 4
1190 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
1191 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4
1192 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1193 // CHECK3: omp.body.continue:
1194 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1195 // CHECK3: omp.inner.for.inc:
1196 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1197 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
1198 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
1199 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
1200 // CHECK3: omp.inner.for.end:
1201 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1202 // CHECK3: omp.loop.exit:
1203 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
1204 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0
1205 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i32* [[T_VAR1]] to i8*
1206 // CHECK3-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 4
1207 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
1208 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.5, [8 x i32]* @.gomp_critical_user_.reduction.var)
1209 // CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
1210 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
1211 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
1212 // CHECK3-NEXT: ]
1213 // CHECK3: .omp.reduction.case1:
1214 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4
1215 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR1]], align 4
1216 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
1217 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4
1218 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], [8 x i32]* @.gomp_critical_user_.reduction.var)
1219 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
1220 // CHECK3: .omp.reduction.case2:
1221 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[T_VAR1]], align 4
1222 // CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4
1223 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
1224 // CHECK3: .omp.reduction.default:
1225 // CHECK3-NEXT: ret void
1226 //
1227 //
1228 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5
1229 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] {
1230 // CHECK3-NEXT: entry:
1231 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
1232 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4
1233 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
1234 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4
1235 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4
1236 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
1237 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4
1238 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
1239 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0
1240 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
1241 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
1242 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0
1243 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4
1244 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
1245 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
1246 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
1247 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
1248 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
1249 // CHECK3-NEXT: ret void
1250 //
1251 //
1252 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6
1253 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] {
1254 // CHECK3-NEXT: entry:
1255 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
1256 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4
1257 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
1258 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4
1259 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4
1260 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
1261 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4
1262 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
1263 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0
1264 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
1265 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
1266 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0
1267 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4
1268 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
1269 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
1270 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
1271 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
1272 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
1273 // CHECK3-NEXT: ret void
1274 //
1275 //
1276 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1277 // CHECK3-SAME: () #[[ATTR7:[0-9]+]] {
1278 // CHECK3-NEXT: entry:
1279 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
1280 // CHECK3-NEXT: ret void
1281 //
1282 //
1283 // CHECK5-LABEL: define {{[^@]+}}@main
1284 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
1285 // CHECK5-NEXT: entry:
1286 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1287 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
1288 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
1289 // CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
1290 // CHECK5-NEXT: ret i32 0
1291 //
1292 //
1293 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44
1294 // CHECK5-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] {
1295 // CHECK5-NEXT: entry:
1296 // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8
1297 // CHECK5-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8
1298 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8
1299 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]])
1300 // CHECK5-NEXT: ret void
1301 //
1302 //
1303 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
1304 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] {
1305 // CHECK5-NEXT: entry:
1306 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1307 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1308 // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8
1309 // CHECK5-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4
1310 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1311 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1312 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1313 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1314 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1315 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1316 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1317 // CHECK5-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8
1318 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1319 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1320 // CHECK5-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8
1321 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8
1322 // CHECK5-NEXT: store i32 0, i32* [[SIVAR1]], align 4
1323 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1324 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1325 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1326 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1327 // CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1328 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
1329 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1330 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1331 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
1332 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1333 // CHECK5: cond.true:
1334 // CHECK5-NEXT: br label [[COND_END:%.*]]
1335 // CHECK5: cond.false:
1336 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1337 // CHECK5-NEXT: br label [[COND_END]]
1338 // CHECK5: cond.end:
1339 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1340 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1341 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1342 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
1343 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1344 // CHECK5: omp.inner.for.cond:
1345 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1346 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1347 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
1348 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1349 // CHECK5: omp.inner.for.body:
1350 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1351 // CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
1352 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1353 // CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
1354 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]])
1355 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1356 // CHECK5: omp.inner.for.inc:
1357 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1358 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1359 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
1360 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1361 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
1362 // CHECK5: omp.inner.for.end:
1363 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1364 // CHECK5: omp.loop.exit:
1365 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
1366 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
1367 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8*
1368 // CHECK5-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8
1369 // CHECK5-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
1370 // CHECK5-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var)
1371 // CHECK5-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
1372 // CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
1373 // CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
1374 // CHECK5-NEXT: ]
1375 // CHECK5: .omp.reduction.case1:
1376 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4
1377 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4
1378 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
1379 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[TMP0]], align 4
1380 // CHECK5-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
1381 // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
1382 // CHECK5: .omp.reduction.case2:
1383 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4
1384 // CHECK5-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4
1385 // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
1386 // CHECK5: .omp.reduction.default:
1387 // CHECK5-NEXT: ret void
1388 //
1389 //
1390 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1
1391 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] {
1392 // CHECK5-NEXT: entry:
1393 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1394 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1395 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1396 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1397 // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8
1398 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1399 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1400 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1401 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1402 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1403 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1404 // CHECK5-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4
1405 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1406 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
1407 // CHECK5-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8
1408 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1409 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1410 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1411 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1412 // CHECK5-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8
1413 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8
1414 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1415 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1416 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1417 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
1418 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1419 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32
1420 // CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
1421 // CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
1422 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1423 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1424 // CHECK5-NEXT: store i32 0, i32* [[SIVAR2]], align 4
1425 // CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1426 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
1427 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1428 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1429 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
1430 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1431 // CHECK5: cond.true:
1432 // CHECK5-NEXT: br label [[COND_END:%.*]]
1433 // CHECK5: cond.false:
1434 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1435 // CHECK5-NEXT: br label [[COND_END]]
1436 // CHECK5: cond.end:
1437 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
1438 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1439 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1440 // CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
1441 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1442 // CHECK5: omp.inner.for.cond:
1443 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1444 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1445 // CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
1446 // CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1447 // CHECK5: omp.inner.for.body:
1448 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1449 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
1450 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1451 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1452 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
1453 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4
1454 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
1455 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4
1456 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
1457 // CHECK5-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8
1458 // CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(8) [[REF_TMP]])
1459 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1460 // CHECK5: omp.body.continue:
1461 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1462 // CHECK5: omp.inner.for.inc:
1463 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1464 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
1465 // CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
1466 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
1467 // CHECK5: omp.inner.for.end:
1468 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1469 // CHECK5: omp.loop.exit:
1470 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
1471 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
1472 // CHECK5-NEXT: [[TMP16:%.*]] = bitcast i32* [[SIVAR2]] to i8*
1473 // CHECK5-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8
1474 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
1475 // CHECK5-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, i8* [[TMP17]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var)
1476 // CHECK5-NEXT: switch i32 [[TMP18]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
1477 // CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
1478 // CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
1479 // CHECK5-NEXT: ]
1480 // CHECK5: .omp.reduction.case1:
1481 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP0]], align 4
1482 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR2]], align 4
1483 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], [[TMP20]]
1484 // CHECK5-NEXT: store i32 [[ADD6]], i32* [[TMP0]], align 4
1485 // CHECK5-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP4]], [8 x i32]* @.gomp_critical_user_.reduction.var)
1486 // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
1487 // CHECK5: .omp.reduction.case2:
1488 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR2]], align 4
1489 // CHECK5-NEXT: [[TMP22:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP21]] monotonic, align 4
1490 // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
1491 // CHECK5: .omp.reduction.default:
1492 // CHECK5-NEXT: ret void
1493 //
1494 //
1495 // CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
1496 // CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
1497 // CHECK5-NEXT: entry:
1498 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
1499 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8
1500 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1501 // CHECK5-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8
1502 // CHECK5-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8
1503 // CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
1504 // CHECK5-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8
1505 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
1506 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0
1507 // CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
1508 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
1509 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0
1510 // CHECK5-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8
1511 // CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
1512 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
1513 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
1514 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
1515 // CHECK5-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
1516 // CHECK5-NEXT: ret void
1517 //
1518 //
1519 // CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2
1520 // CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] {
1521 // CHECK5-NEXT: entry:
1522 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
1523 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8
1524 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1525 // CHECK5-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8
1526 // CHECK5-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8
1527 // CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
1528 // CHECK5-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8
1529 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
1530 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0
1531 // CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
1532 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
1533 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0
1534 // CHECK5-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8
1535 // CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
1536 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
1537 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
1538 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
1539 // CHECK5-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
1540 // CHECK5-NEXT: ret void
1541 //
1542 //
1543 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1544 // CHECK5-SAME: () #[[ATTR6:[0-9]+]] {
1545 // CHECK5-NEXT: entry:
1546 // CHECK5-NEXT: call void @__tgt_register_requires(i64 1)
1547 // CHECK5-NEXT: ret void
1548 //
1549