1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
5
6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
9 // REQUIRES: powerpc-registered-target
10
11 // expected-no-diagnostics
12 #ifndef HEADER
13 #define HEADER
14
gtid_test()15 void gtid_test() {
16 #pragma omp target teams distribute parallel for order(concurrent)
17 for(int i = 0 ; i < 100; i++) {}
18 }
19
20
21
22
23 #endif
24 // CHECK1-LABEL: define {{[^@]+}}@_Z9gtid_testv
25 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
26 // CHECK1-NEXT: entry:
27 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
28 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
29 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
30 // CHECK1-NEXT: store i32 1, i32* [[TMP0]], align 4
31 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
32 // CHECK1-NEXT: store i32 0, i32* [[TMP1]], align 4
33 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
34 // CHECK1-NEXT: store i8** null, i8*** [[TMP2]], align 8
35 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
36 // CHECK1-NEXT: store i8** null, i8*** [[TMP3]], align 8
37 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
38 // CHECK1-NEXT: store i64* null, i64** [[TMP4]], align 8
39 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
40 // CHECK1-NEXT: store i64* null, i64** [[TMP5]], align 8
41 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
42 // CHECK1-NEXT: store i8** null, i8*** [[TMP6]], align 8
43 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
44 // CHECK1-NEXT: store i8** null, i8*** [[TMP7]], align 8
45 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
46 // CHECK1-NEXT: store i64 100, i64* [[TMP8]], align 8
47 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l16.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
48 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
49 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
50 // CHECK1: omp_offload.failed:
51 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l16() #[[ATTR2:[0-9]+]]
52 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
53 // CHECK1: omp_offload.cont:
54 // CHECK1-NEXT: ret void
55 //
56 //
57 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l16
58 // CHECK1-SAME: () #[[ATTR1:[0-9]+]] {
59 // CHECK1-NEXT: entry:
60 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
61 // CHECK1-NEXT: ret void
62 //
63 //
64 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
65 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
66 // CHECK1-NEXT: entry:
67 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
68 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
69 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
70 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
71 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
72 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
73 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
74 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
75 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
76 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
77 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
78 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
79 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
80 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
81 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
82 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
83 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
84 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
85 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
86 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
87 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
88 // CHECK1: cond.true:
89 // CHECK1-NEXT: br label [[COND_END:%.*]]
90 // CHECK1: cond.false:
91 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
92 // CHECK1-NEXT: br label [[COND_END]]
93 // CHECK1: cond.end:
94 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
95 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
96 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
97 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
98 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
99 // CHECK1: omp.inner.for.cond:
100 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
101 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
102 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
103 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
104 // CHECK1: omp.inner.for.body:
105 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
106 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
107 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
108 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
109 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
110 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
111 // CHECK1: omp.inner.for.inc:
112 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
113 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
114 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
115 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
116 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
117 // CHECK1: omp.inner.for.end:
118 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
119 // CHECK1: omp.loop.exit:
120 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
121 // CHECK1-NEXT: ret void
122 //
123 //
124 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
125 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] {
126 // CHECK1-NEXT: entry:
127 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
128 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
129 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
130 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
131 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
132 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
133 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
134 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
135 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
136 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
137 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
138 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
139 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
140 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
141 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
142 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
143 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
144 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
145 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
146 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
147 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
148 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
149 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
150 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
151 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
152 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
153 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
154 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
155 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
156 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
157 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
158 // CHECK1: cond.true:
159 // CHECK1-NEXT: br label [[COND_END:%.*]]
160 // CHECK1: cond.false:
161 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
162 // CHECK1-NEXT: br label [[COND_END]]
163 // CHECK1: cond.end:
164 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
165 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
166 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
167 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
168 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
169 // CHECK1: omp.inner.for.cond:
170 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
171 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4
172 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
173 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
174 // CHECK1: omp.inner.for.body:
175 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
176 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
177 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
178 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
179 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
180 // CHECK1: omp.body.continue:
181 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
182 // CHECK1: omp.inner.for.inc:
183 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
184 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
185 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
186 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
187 // CHECK1: omp.inner.for.end:
188 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
189 // CHECK1: omp.loop.exit:
190 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
191 // CHECK1-NEXT: ret void
192 //
193 //
194 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
195 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] section ".text.startup" {
196 // CHECK1-NEXT: entry:
197 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
198 // CHECK1-NEXT: ret void
199 //
200