1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
8
9 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5
12 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7
15
16 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
17 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
19 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
22
23 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
24 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
25 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
26 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
27 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
28 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
29
30 // expected-no-diagnostics
31 #ifndef HEADER
32 #define HEADER
33
34 template <class T>
35 struct S {
36 T f;
SS37 S(T a) : f(a) {}
SS38 S() : f() {}
operator TS39 operator T() { return T(); }
~SS40 ~S() {}
41 };
42
43 template <typename T>
tmain()44 T tmain() {
45 S<T> test;
46 T t_var = T();
47 T vec[] = {1, 2};
48 S<T> s_arr[] = {1, 2};
49 S<T> &var = test;
50 #pragma omp target teams distribute parallel for lastprivate(t_var, vec, s_arr, s_arr, var, var)
51 for (int i = 0; i < 2; ++i) {
52 vec[i] = t_var;
53 s_arr[i] = var;
54 }
55 return T();
56 }
57
main()58 int main() {
59 static int svar;
60 volatile double g;
61 volatile double &g1 = g;
62
63 #ifdef LAMBDA
64 [&]() {
65 static float sfvar;
66
67 #pragma omp target teams distribute parallel for lastprivate(g, g1, svar, sfvar)
68 for (int i = 0; i < 2; ++i) {
69 // skip gbl and bound tid
70 // loop variables
71
72
73
74 g1 = 1;
75 svar = 3;
76 sfvar = 4.0;
77
78
79
80 // skip tid and prev variables
81 // loop variables
82
83
84
85
86
87
88
89 [&]() {
90 g = 2;
91 g1 = 2;
92 svar = 4;
93 sfvar = 8.0;
94
95 }();
96 }
97 }();
98 return 0;
99 #else
100 S<float> test;
101 int t_var = 0;
102 int vec[] = {1, 2};
103 S<float> s_arr[] = {1, 2};
104 S<float> &var = test;
105
106 #pragma omp target teams distribute parallel for lastprivate(t_var, vec, s_arr, s_arr, var, var, svar)
107 for (int i = 0; i < 2; ++i) {
108 vec[i] = t_var;
109 s_arr[i] = var;
110 }
111 int i;
112
113 return tmain<int>();
114 #endif
115 }
116
117
118 // skip loop variables
119
120 // copy from parameters to local address variables
121
122 // prepare lastprivate targets
123
124 // the distribute loop
125
126 // lastprivates
127
128
129
130 // gbl and bound tid vars, prev lb and ub vars
131
132 // skip loop variables
133
134 // copy from parameters to local address variables
135
136 // prepare lastprivate targets
137
138 // the distribute loop
139 // skip body: code generation routine is same as distribute parallel for lastprivate
140
141 // lastprivates
142
143
144 // template tmain
145
146
147 // skip alloca of global_tid and bound_tid
148 // skip loop variables
149
150 // copy from parameters to local address variables
151
152 // prepare lastprivate targets
153
154
155 // lastprivates
156
157
158 // skip alloca of global_tid and bound_tid, and prev lb and ub vars
159
160 // skip loop variables
161
162 // copy from parameters to local address variables
163
164 // prepare lastprivate targets
165
166 // skip body: code generation routine is same as distribute parallel for lastprivate
167
168 // lastprivates
169
170
171 #endif
172 // CHECK1-LABEL: define {{[^@]+}}@main
173 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
174 // CHECK1-NEXT: entry:
175 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
176 // CHECK1-NEXT: [[G:%.*]] = alloca double, align 8
177 // CHECK1-NEXT: [[G1:%.*]] = alloca double*, align 8
178 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
179 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
180 // CHECK1-NEXT: store double* [[G]], double** [[G1]], align 8
181 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0
182 // CHECK1-NEXT: store double* [[G]], double** [[TMP0]], align 8
183 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1
184 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8
185 // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8
186 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])
187 // CHECK1-NEXT: ret i32 0
188 //
189 //
190 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67
191 // CHECK1-SAME: (i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2:[0-9]+]] {
192 // CHECK1-NEXT: entry:
193 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
194 // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
195 // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8
196 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
197 // CHECK1-NEXT: [[TMP:%.*]] = alloca double*, align 8
198 // CHECK1-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
199 // CHECK1-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
200 // CHECK1-NEXT: [[SFVAR_CASTED:%.*]] = alloca i64, align 8
201 // CHECK1-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
202 // CHECK1-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
203 // CHECK1-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
204 // CHECK1-NEXT: store i64 [[SFVAR]], i64* [[SFVAR_ADDR]], align 8
205 // CHECK1-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
206 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to double*
207 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
208 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float*
209 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_ADDR]] to double*
210 // CHECK1-NEXT: store double* [[CONV]], double** [[TMP]], align 8
211 // CHECK1-NEXT: [[TMP0:%.*]] = load double*, double** [[TMP]], align 8
212 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile double, double* [[TMP0]], align 8
213 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to double*
214 // CHECK1-NEXT: store double [[TMP1]], double* [[CONV4]], align 8
215 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[G1_CASTED]], align 8
216 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
217 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
218 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
219 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
220 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 4
221 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
222 // CHECK1-NEXT: store float [[TMP5]], float* [[CONV6]], align 4
223 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
224 // CHECK1-NEXT: [[TMP7:%.*]] = load double, double* [[CONV3]], align 8
225 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[G_CASTED]] to double*
226 // CHECK1-NEXT: store double [[TMP7]], double* [[CONV7]], align 8
227 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[G_CASTED]], align 8
228 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]])
229 // CHECK1-NEXT: ret void
230 //
231 //
232 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
233 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2]] {
234 // CHECK1-NEXT: entry:
235 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
236 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
237 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
238 // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
239 // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8
240 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
241 // CHECK1-NEXT: [[TMP:%.*]] = alloca double*, align 8
242 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
243 // CHECK1-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
244 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
245 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
246 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
247 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
248 // CHECK1-NEXT: [[G5:%.*]] = alloca double, align 8
249 // CHECK1-NEXT: [[G16:%.*]] = alloca double, align 8
250 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca double*, align 8
251 // CHECK1-NEXT: [[SVAR8:%.*]] = alloca i32, align 4
252 // CHECK1-NEXT: [[SFVAR9:%.*]] = alloca float, align 4
253 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
254 // CHECK1-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
255 // CHECK1-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
256 // CHECK1-NEXT: [[SFVAR_CASTED:%.*]] = alloca i64, align 8
257 // CHECK1-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
258 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
259 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
260 // CHECK1-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
261 // CHECK1-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
262 // CHECK1-NEXT: store i64 [[SFVAR]], i64* [[SFVAR_ADDR]], align 8
263 // CHECK1-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
264 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to double*
265 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
266 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float*
267 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_ADDR]] to double*
268 // CHECK1-NEXT: store double* [[CONV]], double** [[TMP]], align 8
269 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
270 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
271 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
272 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
273 // CHECK1-NEXT: [[TMP0:%.*]] = load double*, double** [[TMP]], align 8
274 // CHECK1-NEXT: store double* [[G16]], double** [[_TMP7]], align 8
275 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
276 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
277 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
278 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
279 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
280 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
281 // CHECK1: cond.true:
282 // CHECK1-NEXT: br label [[COND_END:%.*]]
283 // CHECK1: cond.false:
284 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
285 // CHECK1-NEXT: br label [[COND_END]]
286 // CHECK1: cond.end:
287 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
288 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
289 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
290 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
291 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
292 // CHECK1: omp.inner.for.cond:
293 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
294 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
295 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
296 // CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
297 // CHECK1: omp.inner.for.body:
298 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
299 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
300 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
301 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
302 // CHECK1-NEXT: [[TMP12:%.*]] = load double*, double** [[_TMP7]], align 8
303 // CHECK1-NEXT: [[TMP13:%.*]] = load volatile double, double* [[TMP12]], align 8
304 // CHECK1-NEXT: [[CONV11:%.*]] = bitcast i64* [[G1_CASTED]] to double*
305 // CHECK1-NEXT: store double [[TMP13]], double* [[CONV11]], align 8
306 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[G1_CASTED]], align 8
307 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[SVAR8]], align 4
308 // CHECK1-NEXT: [[CONV12:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
309 // CHECK1-NEXT: store i32 [[TMP15]], i32* [[CONV12]], align 4
310 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
311 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[SFVAR9]], align 4
312 // CHECK1-NEXT: [[CONV13:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
313 // CHECK1-NEXT: store float [[TMP17]], float* [[CONV13]], align 4
314 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
315 // CHECK1-NEXT: [[TMP19:%.*]] = load double, double* [[G5]], align 8
316 // CHECK1-NEXT: [[CONV14:%.*]] = bitcast i64* [[G_CASTED]] to double*
317 // CHECK1-NEXT: store double [[TMP19]], double* [[CONV14]], align 8
318 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[G_CASTED]], align 8
319 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP14]], i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]])
320 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
321 // CHECK1: omp.inner.for.inc:
322 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
323 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
324 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
325 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
326 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
327 // CHECK1: omp.inner.for.end:
328 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
329 // CHECK1: omp.loop.exit:
330 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
331 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
332 // CHECK1-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
333 // CHECK1-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
334 // CHECK1: .omp.lastprivate.then:
335 // CHECK1-NEXT: [[TMP25:%.*]] = load double, double* [[G5]], align 8
336 // CHECK1-NEXT: store volatile double [[TMP25]], double* [[CONV3]], align 8
337 // CHECK1-NEXT: [[TMP26:%.*]] = load double*, double** [[_TMP7]], align 8
338 // CHECK1-NEXT: [[TMP27:%.*]] = load double, double* [[TMP26]], align 8
339 // CHECK1-NEXT: store volatile double [[TMP27]], double* [[TMP0]], align 8
340 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[SVAR8]], align 4
341 // CHECK1-NEXT: store i32 [[TMP28]], i32* [[CONV1]], align 4
342 // CHECK1-NEXT: [[TMP29:%.*]] = load float, float* [[SFVAR9]], align 4
343 // CHECK1-NEXT: store float [[TMP29]], float* [[CONV2]], align 4
344 // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
345 // CHECK1: .omp.lastprivate.done:
346 // CHECK1-NEXT: ret void
347 //
348 //
349 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
350 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2]] {
351 // CHECK1-NEXT: entry:
352 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
353 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
354 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
355 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
356 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
357 // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
358 // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8
359 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
360 // CHECK1-NEXT: [[TMP:%.*]] = alloca double*, align 8
361 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
362 // CHECK1-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
363 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
364 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
365 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
366 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
367 // CHECK1-NEXT: [[G7:%.*]] = alloca double, align 8
368 // CHECK1-NEXT: [[G18:%.*]] = alloca double, align 8
369 // CHECK1-NEXT: [[_TMP9:%.*]] = alloca double*, align 8
370 // CHECK1-NEXT: [[SVAR10:%.*]] = alloca i32, align 4
371 // CHECK1-NEXT: [[SFVAR11:%.*]] = alloca float, align 4
372 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
373 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
374 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
375 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
376 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
377 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
378 // CHECK1-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
379 // CHECK1-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
380 // CHECK1-NEXT: store i64 [[SFVAR]], i64* [[SFVAR_ADDR]], align 8
381 // CHECK1-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
382 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to double*
383 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
384 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float*
385 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_ADDR]] to double*
386 // CHECK1-NEXT: store double* [[CONV]], double** [[TMP]], align 8
387 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
388 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
389 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
390 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP0]] to i32
391 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
392 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP1]] to i32
393 // CHECK1-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4
394 // CHECK1-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
395 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
396 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
397 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 8
398 // CHECK1-NEXT: store double* [[G18]], double** [[_TMP9]], align 8
399 // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
400 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
401 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
402 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
403 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
404 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
405 // CHECK1: cond.true:
406 // CHECK1-NEXT: br label [[COND_END:%.*]]
407 // CHECK1: cond.false:
408 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
409 // CHECK1-NEXT: br label [[COND_END]]
410 // CHECK1: cond.end:
411 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
412 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
413 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
414 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
415 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
416 // CHECK1: omp.inner.for.cond:
417 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
418 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
419 // CHECK1-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
420 // CHECK1-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
421 // CHECK1: omp.inner.for.body:
422 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
423 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
424 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
425 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
426 // CHECK1-NEXT: [[TMP11:%.*]] = load double*, double** [[_TMP9]], align 8
427 // CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP11]], align 8
428 // CHECK1-NEXT: store i32 3, i32* [[SVAR10]], align 4
429 // CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR11]], align 4
430 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
431 // CHECK1-NEXT: store double* [[G7]], double** [[TMP12]], align 8
432 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
433 // CHECK1-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP9]], align 8
434 // CHECK1-NEXT: store double* [[TMP14]], double** [[TMP13]], align 8
435 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
436 // CHECK1-NEXT: store i32* [[SVAR10]], i32** [[TMP15]], align 8
437 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3
438 // CHECK1-NEXT: store float* [[SFVAR11]], float** [[TMP16]], align 8
439 // CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(32) [[REF_TMP]])
440 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
441 // CHECK1: omp.body.continue:
442 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
443 // CHECK1: omp.inner.for.inc:
444 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
445 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP17]], 1
446 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
447 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
448 // CHECK1: omp.inner.for.end:
449 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
450 // CHECK1: omp.loop.exit:
451 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
452 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
453 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
454 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
455 // CHECK1: .omp.lastprivate.then:
456 // CHECK1-NEXT: [[TMP20:%.*]] = load double, double* [[G7]], align 8
457 // CHECK1-NEXT: store volatile double [[TMP20]], double* [[CONV3]], align 8
458 // CHECK1-NEXT: [[TMP21:%.*]] = load double*, double** [[_TMP9]], align 8
459 // CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[TMP21]], align 8
460 // CHECK1-NEXT: store volatile double [[TMP22]], double* [[TMP2]], align 8
461 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR10]], align 4
462 // CHECK1-NEXT: store i32 [[TMP23]], i32* [[CONV1]], align 4
463 // CHECK1-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR11]], align 4
464 // CHECK1-NEXT: store float [[TMP24]], float* [[CONV2]], align 4
465 // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
466 // CHECK1: .omp.lastprivate.done:
467 // CHECK1-NEXT: ret void
468 //
469 //
470 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
471 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
472 // CHECK1-NEXT: entry:
473 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
474 // CHECK1-NEXT: ret void
475 //
476 //
477 // CHECK3-LABEL: define {{[^@]+}}@main
478 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
479 // CHECK3-NEXT: entry:
480 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
481 // CHECK3-NEXT: [[G:%.*]] = alloca double, align 8
482 // CHECK3-NEXT: [[G1:%.*]] = alloca double*, align 4
483 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4
484 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
485 // CHECK3-NEXT: store double* [[G]], double** [[G1]], align 4
486 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0
487 // CHECK3-NEXT: store double* [[G]], double** [[TMP0]], align 4
488 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1
489 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4
490 // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4
491 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 4 dereferenceable(8) [[REF_TMP]])
492 // CHECK3-NEXT: ret i32 0
493 //
494 //
495 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67
496 // CHECK3-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2:[0-9]+]] {
497 // CHECK3-NEXT: entry:
498 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4
499 // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
500 // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4
501 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4
502 // CHECK3-NEXT: [[TMP:%.*]] = alloca double*, align 4
503 // CHECK3-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
504 // CHECK3-NEXT: [[SFVAR_CASTED:%.*]] = alloca i32, align 4
505 // CHECK3-NEXT: store double* [[G1]], double** [[G1_ADDR]], align 4
506 // CHECK3-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4
507 // CHECK3-NEXT: store i32 [[SFVAR]], i32* [[SFVAR_ADDR]], align 4
508 // CHECK3-NEXT: store double* [[G]], double** [[G_ADDR]], align 4
509 // CHECK3-NEXT: [[TMP0:%.*]] = load double*, double** [[G1_ADDR]], align 4
510 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[SFVAR_ADDR]] to float*
511 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[G_ADDR]], align 4
512 // CHECK3-NEXT: store double* [[TMP0]], double** [[TMP]], align 4
513 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 4
514 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[SVAR_ADDR]], align 4
515 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[SVAR_CASTED]], align 4
516 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4
517 // CHECK3-NEXT: [[TMP5:%.*]] = load float, float* [[CONV]], align 4
518 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SFVAR_CASTED]] to float*
519 // CHECK3-NEXT: store float [[TMP5]], float* [[CONV1]], align 4
520 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[SFVAR_CASTED]], align 4
521 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, double*, i32, i32, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), double* [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], double* [[TMP1]])
522 // CHECK3-NEXT: ret void
523 //
524 //
525 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
526 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] {
527 // CHECK3-NEXT: entry:
528 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
529 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
530 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4
531 // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
532 // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4
533 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4
534 // CHECK3-NEXT: [[TMP:%.*]] = alloca double*, align 4
535 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
536 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
537 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
538 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
539 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
540 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
541 // CHECK3-NEXT: [[G2:%.*]] = alloca double, align 8
542 // CHECK3-NEXT: [[G13:%.*]] = alloca double, align 8
543 // CHECK3-NEXT: [[_TMP4:%.*]] = alloca double*, align 4
544 // CHECK3-NEXT: [[SVAR5:%.*]] = alloca i32, align 4
545 // CHECK3-NEXT: [[SFVAR6:%.*]] = alloca float, align 4
546 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
547 // CHECK3-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
548 // CHECK3-NEXT: [[SFVAR_CASTED:%.*]] = alloca i32, align 4
549 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
550 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
551 // CHECK3-NEXT: store double* [[G1]], double** [[G1_ADDR]], align 4
552 // CHECK3-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4
553 // CHECK3-NEXT: store i32 [[SFVAR]], i32* [[SFVAR_ADDR]], align 4
554 // CHECK3-NEXT: store double* [[G]], double** [[G_ADDR]], align 4
555 // CHECK3-NEXT: [[TMP0:%.*]] = load double*, double** [[G1_ADDR]], align 4
556 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[SFVAR_ADDR]] to float*
557 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[G_ADDR]], align 4
558 // CHECK3-NEXT: store double* [[TMP0]], double** [[TMP]], align 4
559 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
560 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
561 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
562 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
563 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 4
564 // CHECK3-NEXT: store double* [[G13]], double** [[_TMP4]], align 4
565 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
566 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
567 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
568 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
569 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
570 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
571 // CHECK3: cond.true:
572 // CHECK3-NEXT: br label [[COND_END:%.*]]
573 // CHECK3: cond.false:
574 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
575 // CHECK3-NEXT: br label [[COND_END]]
576 // CHECK3: cond.end:
577 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
578 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
579 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
580 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
581 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
582 // CHECK3: omp.inner.for.cond:
583 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
584 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
585 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
586 // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
587 // CHECK3: omp.inner.for.body:
588 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
589 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
590 // CHECK3-NEXT: [[TMP12:%.*]] = load double*, double** [[_TMP4]], align 4
591 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[SVAR5]], align 4
592 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[SVAR_CASTED]], align 4
593 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4
594 // CHECK3-NEXT: [[TMP15:%.*]] = load float, float* [[SFVAR6]], align 4
595 // CHECK3-NEXT: [[CONV8:%.*]] = bitcast i32* [[SFVAR_CASTED]] to float*
596 // CHECK3-NEXT: store float [[TMP15]], float* [[CONV8]], align 4
597 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[SFVAR_CASTED]], align 4
598 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, i32, i32, double*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP10]], i32 [[TMP11]], double* [[TMP12]], i32 [[TMP14]], i32 [[TMP16]], double* [[G2]])
599 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
600 // CHECK3: omp.inner.for.inc:
601 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
602 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
603 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
604 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
605 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
606 // CHECK3: omp.inner.for.end:
607 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
608 // CHECK3: omp.loop.exit:
609 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
610 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
611 // CHECK3-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
612 // CHECK3-NEXT: br i1 [[TMP20]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
613 // CHECK3: .omp.lastprivate.then:
614 // CHECK3-NEXT: [[TMP21:%.*]] = load double, double* [[G2]], align 8
615 // CHECK3-NEXT: store volatile double [[TMP21]], double* [[TMP1]], align 8
616 // CHECK3-NEXT: [[TMP22:%.*]] = load double*, double** [[_TMP4]], align 4
617 // CHECK3-NEXT: [[TMP23:%.*]] = load double, double* [[TMP22]], align 4
618 // CHECK3-NEXT: store volatile double [[TMP23]], double* [[TMP2]], align 4
619 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[SVAR5]], align 4
620 // CHECK3-NEXT: store i32 [[TMP24]], i32* [[SVAR_ADDR]], align 4
621 // CHECK3-NEXT: [[TMP25:%.*]] = load float, float* [[SFVAR6]], align 4
622 // CHECK3-NEXT: store float [[TMP25]], float* [[CONV]], align 4
623 // CHECK3-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
624 // CHECK3: .omp.lastprivate.done:
625 // CHECK3-NEXT: ret void
626 //
627 //
628 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
629 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] {
630 // CHECK3-NEXT: entry:
631 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
632 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
633 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
634 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
635 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4
636 // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
637 // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4
638 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4
639 // CHECK3-NEXT: [[TMP:%.*]] = alloca double*, align 4
640 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
641 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
642 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
643 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
644 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
645 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
646 // CHECK3-NEXT: [[G2:%.*]] = alloca double, align 8
647 // CHECK3-NEXT: [[G13:%.*]] = alloca double, align 8
648 // CHECK3-NEXT: [[_TMP4:%.*]] = alloca double*, align 4
649 // CHECK3-NEXT: [[SVAR5:%.*]] = alloca i32, align 4
650 // CHECK3-NEXT: [[SFVAR6:%.*]] = alloca float, align 4
651 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
652 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4
653 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
654 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
655 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
656 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
657 // CHECK3-NEXT: store double* [[G1]], double** [[G1_ADDR]], align 4
658 // CHECK3-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4
659 // CHECK3-NEXT: store i32 [[SFVAR]], i32* [[SFVAR_ADDR]], align 4
660 // CHECK3-NEXT: store double* [[G]], double** [[G_ADDR]], align 4
661 // CHECK3-NEXT: [[TMP0:%.*]] = load double*, double** [[G1_ADDR]], align 4
662 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[SFVAR_ADDR]] to float*
663 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[G_ADDR]], align 4
664 // CHECK3-NEXT: store double* [[TMP0]], double** [[TMP]], align 4
665 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
666 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
667 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
668 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
669 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_LB]], align 4
670 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_UB]], align 4
671 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
672 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
673 // CHECK3-NEXT: [[TMP4:%.*]] = load double*, double** [[TMP]], align 4
674 // CHECK3-NEXT: store double* [[G13]], double** [[_TMP4]], align 4
675 // CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
676 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
677 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
678 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
679 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1
680 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
681 // CHECK3: cond.true:
682 // CHECK3-NEXT: br label [[COND_END:%.*]]
683 // CHECK3: cond.false:
684 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
685 // CHECK3-NEXT: br label [[COND_END]]
686 // CHECK3: cond.end:
687 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
688 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
689 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
690 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
691 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
692 // CHECK3: omp.inner.for.cond:
693 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
694 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
695 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
696 // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
697 // CHECK3: omp.inner.for.body:
698 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
699 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
700 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
701 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
702 // CHECK3-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP4]], align 4
703 // CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 4
704 // CHECK3-NEXT: store i32 3, i32* [[SVAR5]], align 4
705 // CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4
706 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
707 // CHECK3-NEXT: store double* [[G2]], double** [[TMP14]], align 4
708 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
709 // CHECK3-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 4
710 // CHECK3-NEXT: store double* [[TMP16]], double** [[TMP15]], align 4
711 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
712 // CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4
713 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3
714 // CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4
715 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 4 dereferenceable(16) [[REF_TMP]])
716 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
717 // CHECK3: omp.body.continue:
718 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
719 // CHECK3: omp.inner.for.inc:
720 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
721 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
722 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
723 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
724 // CHECK3: omp.inner.for.end:
725 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
726 // CHECK3: omp.loop.exit:
727 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
728 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
729 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
730 // CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
731 // CHECK3: .omp.lastprivate.then:
732 // CHECK3-NEXT: [[TMP22:%.*]] = load double, double* [[G2]], align 8
733 // CHECK3-NEXT: store volatile double [[TMP22]], double* [[TMP1]], align 8
734 // CHECK3-NEXT: [[TMP23:%.*]] = load double*, double** [[_TMP4]], align 4
735 // CHECK3-NEXT: [[TMP24:%.*]] = load double, double* [[TMP23]], align 4
736 // CHECK3-NEXT: store volatile double [[TMP24]], double* [[TMP4]], align 4
737 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[SVAR5]], align 4
738 // CHECK3-NEXT: store i32 [[TMP25]], i32* [[SVAR_ADDR]], align 4
739 // CHECK3-NEXT: [[TMP26:%.*]] = load float, float* [[SFVAR6]], align 4
740 // CHECK3-NEXT: store float [[TMP26]], float* [[CONV]], align 4
741 // CHECK3-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
742 // CHECK3: .omp.lastprivate.done:
743 // CHECK3-NEXT: ret void
744 //
745 //
746 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
747 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
748 // CHECK3-NEXT: entry:
749 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
750 // CHECK3-NEXT: ret void
751 //
752 //
753 // CHECK5-LABEL: define {{[^@]+}}@main
754 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
755 // CHECK5-NEXT: entry:
756 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
757 // CHECK5-NEXT: [[G:%.*]] = alloca double, align 8
758 // CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8
759 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
760 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
761 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
762 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
763 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8
764 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8
765 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
766 // CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
767 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
768 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
769 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
770 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
771 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
772 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
773 // CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8
774 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[TEST]])
775 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4
776 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
777 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false)
778 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0
779 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00)
780 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1
781 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
782 // CHECK5-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8
783 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8
784 // CHECK5-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8
785 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
786 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
787 // CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4
788 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
789 // CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
790 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4
791 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
792 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4
793 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
794 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
795 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]**
796 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8
797 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
798 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]**
799 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP10]], align 8
800 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
801 // CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8
802 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
803 // CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
804 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
805 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
806 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
807 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8
808 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
809 // CHECK5-NEXT: store i8* null, i8** [[TMP16]], align 8
810 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
811 // CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]**
812 // CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 8
813 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
814 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]**
815 // CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8
816 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
817 // CHECK5-NEXT: store i8* null, i8** [[TMP21]], align 8
818 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
819 // CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S**
820 // CHECK5-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP23]], align 8
821 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
822 // CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S**
823 // CHECK5-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP25]], align 8
824 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
825 // CHECK5-NEXT: store i8* null, i8** [[TMP26]], align 8
826 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
827 // CHECK5-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
828 // CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP28]], align 8
829 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
830 // CHECK5-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64*
831 // CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8
832 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
833 // CHECK5-NEXT: store i8* null, i8** [[TMP31]], align 8
834 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
835 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
836 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
837 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
838 // CHECK5-NEXT: store i32 1, i32* [[TMP34]], align 4
839 // CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
840 // CHECK5-NEXT: store i32 5, i32* [[TMP35]], align 4
841 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
842 // CHECK5-NEXT: store i8** [[TMP32]], i8*** [[TMP36]], align 8
843 // CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
844 // CHECK5-NEXT: store i8** [[TMP33]], i8*** [[TMP37]], align 8
845 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
846 // CHECK5-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP38]], align 8
847 // CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
848 // CHECK5-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP39]], align 8
849 // CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
850 // CHECK5-NEXT: store i8** null, i8*** [[TMP40]], align 8
851 // CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
852 // CHECK5-NEXT: store i8** null, i8*** [[TMP41]], align 8
853 // CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
854 // CHECK5-NEXT: store i64 2, i64* [[TMP42]], align 8
855 // CHECK5-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
856 // CHECK5-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
857 // CHECK5-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
858 // CHECK5: omp_offload.failed:
859 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]]
860 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
861 // CHECK5: omp_offload.cont:
862 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
863 // CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
864 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
865 // CHECK5-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
866 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
867 // CHECK5: arraydestroy.body:
868 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
869 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
870 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
871 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
872 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
873 // CHECK5: arraydestroy.done3:
874 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
875 // CHECK5-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4
876 // CHECK5-NEXT: ret i32 [[TMP46]]
877 //
878 //
879 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
880 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
881 // CHECK5-NEXT: entry:
882 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
883 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
884 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
885 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
886 // CHECK5-NEXT: ret void
887 //
888 //
889 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
890 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
891 // CHECK5-NEXT: entry:
892 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
893 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
894 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
895 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
896 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
897 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
898 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
899 // CHECK5-NEXT: ret void
900 //
901 //
902 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106
903 // CHECK5-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {
904 // CHECK5-NEXT: entry:
905 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
906 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
907 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
908 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
909 // CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
910 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8
911 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
912 // CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
913 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
914 // CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
915 // CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
916 // CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
917 // CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
918 // CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
919 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
920 // CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
921 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
922 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
923 // CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
924 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
925 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
926 // CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
927 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
928 // CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
929 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
930 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
931 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
932 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
933 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]])
934 // CHECK5-NEXT: ret void
935 //
936 //
937 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
938 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] {
939 // CHECK5-NEXT: entry:
940 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
941 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
942 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
943 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
944 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
945 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
946 // CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
947 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8
948 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
949 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
950 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
951 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
952 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
953 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
954 // CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4
955 // CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
956 // CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4
957 // CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4
958 // CHECK5-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8
959 // CHECK5-NEXT: [[SVAR8:%.*]] = alloca i32, align 4
960 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
961 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
962 // CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
963 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
964 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
965 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
966 // CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
967 // CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
968 // CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
969 // CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
970 // CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
971 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
972 // CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
973 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
974 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
975 // CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
976 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
977 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
978 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
979 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
980 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
981 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
982 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
983 // CHECK5: arrayctor.loop:
984 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
985 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
986 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
987 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
988 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
989 // CHECK5: arrayctor.cont:
990 // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
991 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR6]])
992 // CHECK5-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8
993 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
994 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
995 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
996 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
997 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
998 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
999 // CHECK5: cond.true:
1000 // CHECK5-NEXT: br label [[COND_END:%.*]]
1001 // CHECK5: cond.false:
1002 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1003 // CHECK5-NEXT: br label [[COND_END]]
1004 // CHECK5: cond.end:
1005 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1006 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1007 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1008 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
1009 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1010 // CHECK5: omp.inner.for.cond:
1011 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1012 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1013 // CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1014 // CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1015 // CHECK5: omp.inner.for.cond.cleanup:
1016 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1017 // CHECK5: omp.inner.for.body:
1018 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1019 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
1020 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1021 // CHECK5-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
1022 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4
1023 // CHECK5-NEXT: [[CONV10:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1024 // CHECK5-NEXT: store i32 [[TMP15]], i32* [[CONV10]], align 4
1025 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1026 // CHECK5-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8
1027 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[SVAR8]], align 4
1028 // CHECK5-NEXT: [[CONV11:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
1029 // CHECK5-NEXT: store i32 [[TMP18]], i32* [[CONV11]], align 4
1030 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
1031 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP12]], i64 [[TMP14]], [2 x i32]* [[VEC4]], i64 [[TMP16]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP17]], i64 [[TMP19]])
1032 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1033 // CHECK5: omp.inner.for.inc:
1034 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1035 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1036 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
1037 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1038 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
1039 // CHECK5: omp.inner.for.end:
1040 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1041 // CHECK5: omp.loop.exit:
1042 // CHECK5-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1043 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
1044 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
1045 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1046 // CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
1047 // CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1048 // CHECK5: .omp.lastprivate.then:
1049 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4
1050 // CHECK5-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 4
1051 // CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1052 // CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
1053 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false)
1054 // CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
1055 // CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S*
1056 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2
1057 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP30]]
1058 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1059 // CHECK5: omp.arraycpy.body:
1060 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1061 // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1062 // CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
1063 // CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
1064 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false)
1065 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1066 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1067 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]]
1068 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]]
1069 // CHECK5: omp.arraycpy.done13:
1070 // CHECK5-NEXT: [[TMP33:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8
1071 // CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP3]] to i8*
1072 // CHECK5-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP33]] to i8*
1073 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false)
1074 // CHECK5-NEXT: [[TMP36:%.*]] = load i32, i32* [[SVAR8]], align 4
1075 // CHECK5-NEXT: store i32 [[TMP36]], i32* [[CONV1]], align 4
1076 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
1077 // CHECK5: .omp.lastprivate.done:
1078 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
1079 // CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
1080 // CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2
1081 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1082 // CHECK5: arraydestroy.body:
1083 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1084 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1085 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1086 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
1087 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
1088 // CHECK5: arraydestroy.done15:
1089 // CHECK5-NEXT: ret void
1090 //
1091 //
1092 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1
1093 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] {
1094 // CHECK5-NEXT: entry:
1095 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1096 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1097 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1098 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1099 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1100 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1101 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
1102 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
1103 // CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
1104 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8
1105 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1106 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
1107 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1108 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1109 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1110 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1111 // CHECK5-NEXT: [[T_VAR5:%.*]] = alloca i32, align 4
1112 // CHECK5-NEXT: [[VEC6:%.*]] = alloca [2 x i32], align 4
1113 // CHECK5-NEXT: [[S_ARR7:%.*]] = alloca [2 x %struct.S], align 4
1114 // CHECK5-NEXT: [[VAR8:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1115 // CHECK5-NEXT: [[_TMP9:%.*]] = alloca %struct.S*, align 8
1116 // CHECK5-NEXT: [[SVAR10:%.*]] = alloca i32, align 4
1117 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1118 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1119 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1120 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1121 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1122 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1123 // CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1124 // CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1125 // CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
1126 // CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
1127 // CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1128 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1129 // CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1130 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
1131 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
1132 // CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
1133 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1134 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1135 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1136 // CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP3]] to i32
1137 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1138 // CHECK5-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP4]] to i32
1139 // CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4
1140 // CHECK5-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4
1141 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1142 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1143 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i32 0, i32 0
1144 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
1145 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1146 // CHECK5: arrayctor.loop:
1147 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1148 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1149 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
1150 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1151 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1152 // CHECK5: arrayctor.cont:
1153 // CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
1154 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR8]])
1155 // CHECK5-NEXT: store %struct.S* [[VAR8]], %struct.S** [[_TMP9]], align 8
1156 // CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1157 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
1158 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1159 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1160 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
1161 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1162 // CHECK5: cond.true:
1163 // CHECK5-NEXT: br label [[COND_END:%.*]]
1164 // CHECK5: cond.false:
1165 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1166 // CHECK5-NEXT: br label [[COND_END]]
1167 // CHECK5: cond.end:
1168 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
1169 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1170 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1171 // CHECK5-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
1172 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1173 // CHECK5: omp.inner.for.cond:
1174 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1175 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1176 // CHECK5-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
1177 // CHECK5-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1178 // CHECK5: omp.inner.for.cond.cleanup:
1179 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1180 // CHECK5: omp.inner.for.body:
1181 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1182 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
1183 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1184 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1185 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR5]], align 4
1186 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
1187 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
1188 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC6]], i64 0, i64 [[IDXPROM]]
1189 // CHECK5-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4
1190 // CHECK5-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8
1191 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
1192 // CHECK5-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP17]] to i64
1193 // CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i64 0, i64 [[IDXPROM12]]
1194 // CHECK5-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX13]] to i8*
1195 // CHECK5-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8*
1196 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)
1197 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1198 // CHECK5: omp.body.continue:
1199 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1200 // CHECK5: omp.inner.for.inc:
1201 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1202 // CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP20]], 1
1203 // CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4
1204 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
1205 // CHECK5: omp.inner.for.end:
1206 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1207 // CHECK5: omp.loop.exit:
1208 // CHECK5-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1209 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4
1210 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
1211 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1212 // CHECK5-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
1213 // CHECK5-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1214 // CHECK5: .omp.lastprivate.then:
1215 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR5]], align 4
1216 // CHECK5-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 4
1217 // CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1218 // CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC6]] to i8*
1219 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
1220 // CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
1221 // CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR7]] to %struct.S*
1222 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2
1223 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN15]], [[TMP29]]
1224 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE16:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1225 // CHECK5: omp.arraycpy.body:
1226 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1227 // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN15]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1228 // CHECK5-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
1229 // CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
1230 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false)
1231 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1232 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1233 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]]
1234 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE16]], label [[OMP_ARRAYCPY_BODY]]
1235 // CHECK5: omp.arraycpy.done16:
1236 // CHECK5-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8
1237 // CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP5]] to i8*
1238 // CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8*
1239 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false)
1240 // CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR10]], align 4
1241 // CHECK5-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 4
1242 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
1243 // CHECK5: .omp.lastprivate.done:
1244 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]]
1245 // CHECK5-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i32 0, i32 0
1246 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2
1247 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1248 // CHECK5: arraydestroy.body:
1249 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1250 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1251 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1252 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN17]]
1253 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY]]
1254 // CHECK5: arraydestroy.done18:
1255 // CHECK5-NEXT: ret void
1256 //
1257 //
1258 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1259 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1260 // CHECK5-NEXT: entry:
1261 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1262 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1263 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1264 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
1265 // CHECK5-NEXT: ret void
1266 //
1267 //
1268 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1269 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat {
1270 // CHECK5-NEXT: entry:
1271 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1272 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1273 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1274 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1275 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1276 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
1277 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
1278 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1279 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
1280 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
1281 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
1282 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1283 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
1284 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4
1285 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1286 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
1287 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
1288 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
1289 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
1290 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
1291 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
1292 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
1293 // CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8
1294 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
1295 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1296 // CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4
1297 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1298 // CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1299 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1300 // CHECK5-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]**
1301 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 8
1302 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1303 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]**
1304 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8
1305 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1306 // CHECK5-NEXT: store i8* null, i8** [[TMP9]], align 8
1307 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1308 // CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
1309 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
1310 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1311 // CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1312 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
1313 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1314 // CHECK5-NEXT: store i8* null, i8** [[TMP14]], align 8
1315 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1316 // CHECK5-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]**
1317 // CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 8
1318 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1319 // CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
1320 // CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8
1321 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1322 // CHECK5-NEXT: store i8* null, i8** [[TMP19]], align 8
1323 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1324 // CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0**
1325 // CHECK5-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 8
1326 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1327 // CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
1328 // CHECK5-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 8
1329 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1330 // CHECK5-NEXT: store i8* null, i8** [[TMP24]], align 8
1331 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1332 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1333 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1334 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1335 // CHECK5-NEXT: store i32 1, i32* [[TMP27]], align 4
1336 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1337 // CHECK5-NEXT: store i32 4, i32* [[TMP28]], align 4
1338 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1339 // CHECK5-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 8
1340 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1341 // CHECK5-NEXT: store i8** [[TMP26]], i8*** [[TMP30]], align 8
1342 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1343 // CHECK5-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64** [[TMP31]], align 8
1344 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1345 // CHECK5-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i64** [[TMP32]], align 8
1346 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1347 // CHECK5-NEXT: store i8** null, i8*** [[TMP33]], align 8
1348 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1349 // CHECK5-NEXT: store i8** null, i8*** [[TMP34]], align 8
1350 // CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1351 // CHECK5-NEXT: store i64 2, i64* [[TMP35]], align 8
1352 // CHECK5-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1353 // CHECK5-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0
1354 // CHECK5-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1355 // CHECK5: omp_offload.failed:
1356 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]]
1357 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
1358 // CHECK5: omp_offload.cont:
1359 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
1360 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1361 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1362 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1363 // CHECK5: arraydestroy.body:
1364 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1365 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1366 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1367 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1368 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1369 // CHECK5: arraydestroy.done2:
1370 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1371 // CHECK5-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4
1372 // CHECK5-NEXT: ret i32 [[TMP39]]
1373 //
1374 //
1375 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1376 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1377 // CHECK5-NEXT: entry:
1378 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1379 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1380 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1381 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1382 // CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4
1383 // CHECK5-NEXT: ret void
1384 //
1385 //
1386 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1387 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1388 // CHECK5-NEXT: entry:
1389 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1390 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1391 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1392 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1393 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1394 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1395 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1396 // CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4
1397 // CHECK5-NEXT: ret void
1398 //
1399 //
1400 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1401 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1402 // CHECK5-NEXT: entry:
1403 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1404 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1405 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1406 // CHECK5-NEXT: ret void
1407 //
1408 //
1409 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1410 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1411 // CHECK5-NEXT: entry:
1412 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1413 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1414 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1415 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1416 // CHECK5-NEXT: ret void
1417 //
1418 //
1419 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1420 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1421 // CHECK5-NEXT: entry:
1422 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1423 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1424 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1425 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1426 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1427 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1428 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
1429 // CHECK5-NEXT: ret void
1430 //
1431 //
1432 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50
1433 // CHECK5-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1434 // CHECK5-NEXT: entry:
1435 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1436 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1437 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
1438 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
1439 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
1440 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1441 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1442 // CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1443 // CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1444 // CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
1445 // CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1446 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1447 // CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1448 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
1449 // CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
1450 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
1451 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1452 // CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
1453 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1454 // CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1455 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
1456 // CHECK5-NEXT: ret void
1457 //
1458 //
1459 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2
1460 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1461 // CHECK5-NEXT: entry:
1462 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1463 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1464 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1465 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1466 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
1467 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
1468 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
1469 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1470 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1471 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1472 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1473 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1474 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1475 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
1476 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
1477 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
1478 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1479 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8
1480 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1481 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1482 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1483 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1484 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1485 // CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1486 // CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1487 // CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
1488 // CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1489 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1490 // CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1491 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
1492 // CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
1493 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1494 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1495 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1496 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1497 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
1498 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1499 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1500 // CHECK5: arrayctor.loop:
1501 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1502 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1503 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
1504 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1505 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1506 // CHECK5: arrayctor.cont:
1507 // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1508 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]])
1509 // CHECK5-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8
1510 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1511 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
1512 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1513 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1514 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
1515 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1516 // CHECK5: cond.true:
1517 // CHECK5-NEXT: br label [[COND_END:%.*]]
1518 // CHECK5: cond.false:
1519 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1520 // CHECK5-NEXT: br label [[COND_END]]
1521 // CHECK5: cond.end:
1522 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1523 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1524 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1525 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
1526 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1527 // CHECK5: omp.inner.for.cond:
1528 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1529 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1530 // CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1531 // CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1532 // CHECK5: omp.inner.for.cond.cleanup:
1533 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1534 // CHECK5: omp.inner.for.body:
1535 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1536 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
1537 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1538 // CHECK5-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
1539 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4
1540 // CHECK5-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1541 // CHECK5-NEXT: store i32 [[TMP15]], i32* [[CONV8]], align 4
1542 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1543 // CHECK5-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8
1544 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP12]], i64 [[TMP14]], [2 x i32]* [[VEC3]], i64 [[TMP16]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP17]])
1545 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1546 // CHECK5: omp.inner.for.inc:
1547 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1548 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1549 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
1550 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1551 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
1552 // CHECK5: omp.inner.for.end:
1553 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1554 // CHECK5: omp.loop.exit:
1555 // CHECK5-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1556 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4
1557 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])
1558 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1559 // CHECK5-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
1560 // CHECK5-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1561 // CHECK5: .omp.lastprivate.then:
1562 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4
1563 // CHECK5-NEXT: store i32 [[TMP24]], i32* [[CONV]], align 4
1564 // CHECK5-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1565 // CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
1566 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false)
1567 // CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
1568 // CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0*
1569 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2
1570 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP28]]
1571 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1572 // CHECK5: omp.arraycpy.body:
1573 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1574 // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1575 // CHECK5-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
1576 // CHECK5-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
1577 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false)
1578 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1579 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1580 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]]
1581 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]]
1582 // CHECK5: omp.arraycpy.done10:
1583 // CHECK5-NEXT: [[TMP31:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8
1584 // CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8*
1585 // CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP31]] to i8*
1586 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false)
1587 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
1588 // CHECK5: .omp.lastprivate.done:
1589 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
1590 // CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
1591 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2
1592 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1593 // CHECK5: arraydestroy.body:
1594 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1595 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1596 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1597 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
1598 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
1599 // CHECK5: arraydestroy.done12:
1600 // CHECK5-NEXT: ret void
1601 //
1602 //
1603 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3
1604 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1605 // CHECK5-NEXT: entry:
1606 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1607 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1608 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1609 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1610 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1611 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1612 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
1613 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
1614 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
1615 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1616 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1617 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1618 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1619 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1620 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1621 // CHECK5-NEXT: [[T_VAR4:%.*]] = alloca i32, align 4
1622 // CHECK5-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4
1623 // CHECK5-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S.0], align 4
1624 // CHECK5-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1625 // CHECK5-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8
1626 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1627 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1628 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1629 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1630 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1631 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1632 // CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1633 // CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1634 // CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
1635 // CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1636 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1637 // CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1638 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
1639 // CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
1640 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1641 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1642 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1643 // CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
1644 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1645 // CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
1646 // CHECK5-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
1647 // CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
1648 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1649 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1650 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i32 0, i32 0
1651 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1652 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1653 // CHECK5: arrayctor.loop:
1654 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1655 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1656 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
1657 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1658 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1659 // CHECK5: arrayctor.cont:
1660 // CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1661 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR7]])
1662 // CHECK5-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8
1663 // CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1664 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
1665 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1666 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1667 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
1668 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1669 // CHECK5: cond.true:
1670 // CHECK5-NEXT: br label [[COND_END:%.*]]
1671 // CHECK5: cond.false:
1672 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1673 // CHECK5-NEXT: br label [[COND_END]]
1674 // CHECK5: cond.end:
1675 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
1676 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1677 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1678 // CHECK5-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
1679 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1680 // CHECK5: omp.inner.for.cond:
1681 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1682 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1683 // CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
1684 // CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1685 // CHECK5: omp.inner.for.cond.cleanup:
1686 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1687 // CHECK5: omp.inner.for.body:
1688 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1689 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
1690 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1691 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1692 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR4]], align 4
1693 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
1694 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
1695 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]]
1696 // CHECK5-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4
1697 // CHECK5-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8
1698 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
1699 // CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP17]] to i64
1700 // CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i64 0, i64 [[IDXPROM10]]
1701 // CHECK5-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8*
1702 // CHECK5-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8*
1703 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)
1704 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1705 // CHECK5: omp.body.continue:
1706 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1707 // CHECK5: omp.inner.for.inc:
1708 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1709 // CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP20]], 1
1710 // CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4
1711 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
1712 // CHECK5: omp.inner.for.end:
1713 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1714 // CHECK5: omp.loop.exit:
1715 // CHECK5-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1716 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4
1717 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
1718 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1719 // CHECK5-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
1720 // CHECK5-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1721 // CHECK5: .omp.lastprivate.then:
1722 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR4]], align 4
1723 // CHECK5-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 4
1724 // CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1725 // CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8*
1726 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
1727 // CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
1728 // CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR6]] to %struct.S.0*
1729 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2
1730 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN13]], [[TMP29]]
1731 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1732 // CHECK5: omp.arraycpy.body:
1733 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1734 // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1735 // CHECK5-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
1736 // CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
1737 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false)
1738 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1739 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1740 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]]
1741 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]]
1742 // CHECK5: omp.arraycpy.done14:
1743 // CHECK5-NEXT: [[TMP32:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8
1744 // CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8*
1745 // CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP32]] to i8*
1746 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false)
1747 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
1748 // CHECK5: .omp.lastprivate.done:
1749 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]
1750 // CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i32 0, i32 0
1751 // CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN15]], i64 2
1752 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1753 // CHECK5: arraydestroy.body:
1754 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1755 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1756 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1757 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]]
1758 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]]
1759 // CHECK5: arraydestroy.done16:
1760 // CHECK5-NEXT: ret void
1761 //
1762 //
1763 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1764 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1765 // CHECK5-NEXT: entry:
1766 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1767 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1768 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1769 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
1770 // CHECK5-NEXT: ret void
1771 //
1772 //
1773 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1774 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1775 // CHECK5-NEXT: entry:
1776 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1777 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1778 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1779 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1780 // CHECK5-NEXT: store i32 0, i32* [[F]], align 4
1781 // CHECK5-NEXT: ret void
1782 //
1783 //
1784 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1785 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1786 // CHECK5-NEXT: entry:
1787 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1788 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1789 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1790 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1791 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1792 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1793 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1794 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1795 // CHECK5-NEXT: ret void
1796 //
1797 //
1798 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1799 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1800 // CHECK5-NEXT: entry:
1801 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1802 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1803 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1804 // CHECK5-NEXT: ret void
1805 //
1806 //
1807 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1808 // CHECK5-SAME: () #[[ATTR6:[0-9]+]] {
1809 // CHECK5-NEXT: entry:
1810 // CHECK5-NEXT: call void @__tgt_register_requires(i64 1)
1811 // CHECK5-NEXT: ret void
1812 //
1813 //
1814 // CHECK7-LABEL: define {{[^@]+}}@main
1815 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
1816 // CHECK7-NEXT: entry:
1817 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1818 // CHECK7-NEXT: [[G:%.*]] = alloca double, align 8
1819 // CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4
1820 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1821 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1822 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1823 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1824 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4
1825 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4
1826 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1827 // CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
1828 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
1829 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
1830 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
1831 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1832 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
1833 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
1834 // CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4
1835 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[TEST]])
1836 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4
1837 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1838 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false)
1839 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1840 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00)
1841 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1
1842 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
1843 // CHECK7-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4
1844 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4
1845 // CHECK7-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4
1846 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
1847 // CHECK7-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4
1848 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
1849 // CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4
1850 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4
1851 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4
1852 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4
1853 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1854 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]**
1855 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4
1856 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1857 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]**
1858 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP10]], align 4
1859 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1860 // CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4
1861 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1862 // CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
1863 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
1864 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1865 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
1866 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4
1867 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1868 // CHECK7-NEXT: store i8* null, i8** [[TMP16]], align 4
1869 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1870 // CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]**
1871 // CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 4
1872 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1873 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]**
1874 // CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4
1875 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1876 // CHECK7-NEXT: store i8* null, i8** [[TMP21]], align 4
1877 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1878 // CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S**
1879 // CHECK7-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP23]], align 4
1880 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1881 // CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S**
1882 // CHECK7-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP25]], align 4
1883 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1884 // CHECK7-NEXT: store i8* null, i8** [[TMP26]], align 4
1885 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1886 // CHECK7-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
1887 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP28]], align 4
1888 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1889 // CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
1890 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4
1891 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1892 // CHECK7-NEXT: store i8* null, i8** [[TMP31]], align 4
1893 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1894 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1895 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1896 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1897 // CHECK7-NEXT: store i32 1, i32* [[TMP34]], align 4
1898 // CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1899 // CHECK7-NEXT: store i32 5, i32* [[TMP35]], align 4
1900 // CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1901 // CHECK7-NEXT: store i8** [[TMP32]], i8*** [[TMP36]], align 4
1902 // CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1903 // CHECK7-NEXT: store i8** [[TMP33]], i8*** [[TMP37]], align 4
1904 // CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1905 // CHECK7-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP38]], align 4
1906 // CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1907 // CHECK7-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP39]], align 4
1908 // CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1909 // CHECK7-NEXT: store i8** null, i8*** [[TMP40]], align 4
1910 // CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1911 // CHECK7-NEXT: store i8** null, i8*** [[TMP41]], align 4
1912 // CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1913 // CHECK7-NEXT: store i64 2, i64* [[TMP42]], align 8
1914 // CHECK7-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1915 // CHECK7-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
1916 // CHECK7-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1917 // CHECK7: omp_offload.failed:
1918 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]]
1919 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
1920 // CHECK7: omp_offload.cont:
1921 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1922 // CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
1923 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1924 // CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
1925 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1926 // CHECK7: arraydestroy.body:
1927 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1928 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1929 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1930 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1931 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1932 // CHECK7: arraydestroy.done2:
1933 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1934 // CHECK7-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4
1935 // CHECK7-NEXT: ret i32 [[TMP46]]
1936 //
1937 //
1938 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1939 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1940 // CHECK7-NEXT: entry:
1941 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1942 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1943 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1944 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1945 // CHECK7-NEXT: ret void
1946 //
1947 //
1948 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1949 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1950 // CHECK7-NEXT: entry:
1951 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1952 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1953 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1954 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1955 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1956 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1957 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1958 // CHECK7-NEXT: ret void
1959 //
1960 //
1961 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106
1962 // CHECK7-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {
1963 // CHECK7-NEXT: entry:
1964 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
1965 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1966 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
1967 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
1968 // CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
1969 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4
1970 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1971 // CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
1972 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
1973 // CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
1974 // CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
1975 // CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
1976 // CHECK7-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4
1977 // CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
1978 // CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
1979 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
1980 // CHECK7-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4
1981 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
1982 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
1983 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
1984 // CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4
1985 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_ADDR]], align 4
1986 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[SVAR_CASTED]], align 4
1987 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4
1988 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i32 [[TMP7]])
1989 // CHECK7-NEXT: ret void
1990 //
1991 //
1992 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined.
1993 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] {
1994 // CHECK7-NEXT: entry:
1995 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1996 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1997 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
1998 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1999 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
2000 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
2001 // CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
2002 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4
2003 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2004 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2005 // CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2006 // CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2007 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2008 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2009 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
2010 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
2011 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4
2012 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2013 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4
2014 // CHECK7-NEXT: [[SVAR7:%.*]] = alloca i32, align 4
2015 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
2016 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2017 // CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
2018 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2019 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2020 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2021 // CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2022 // CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2023 // CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
2024 // CHECK7-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4
2025 // CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2026 // CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2027 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
2028 // CHECK7-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4
2029 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2030 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
2031 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2032 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2033 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0
2034 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
2035 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2036 // CHECK7: arrayctor.loop:
2037 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2038 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2039 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
2040 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2041 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2042 // CHECK7: arrayctor.cont:
2043 // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4
2044 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR5]])
2045 // CHECK7-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4
2046 // CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2047 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
2048 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2049 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2050 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
2051 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2052 // CHECK7: cond.true:
2053 // CHECK7-NEXT: br label [[COND_END:%.*]]
2054 // CHECK7: cond.false:
2055 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2056 // CHECK7-NEXT: br label [[COND_END]]
2057 // CHECK7: cond.end:
2058 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
2059 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2060 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2061 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
2062 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2063 // CHECK7: omp.inner.for.cond:
2064 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2065 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2066 // CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
2067 // CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2068 // CHECK7: omp.inner.for.cond.cleanup:
2069 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2070 // CHECK7: omp.inner.for.body:
2071 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2072 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2073 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4
2074 // CHECK7-NEXT: store i32 [[TMP13]], i32* [[T_VAR_CASTED]], align 4
2075 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2076 // CHECK7-NEXT: [[TMP15:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4
2077 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[SVAR7]], align 4
2078 // CHECK7-NEXT: store i32 [[TMP16]], i32* [[SVAR_CASTED]], align 4
2079 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4
2080 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP11]], i32 [[TMP12]], [2 x i32]* [[VEC3]], i32 [[TMP14]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32 [[TMP17]])
2081 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2082 // CHECK7: omp.inner.for.inc:
2083 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2084 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2085 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
2086 // CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2087 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]]
2088 // CHECK7: omp.inner.for.end:
2089 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2090 // CHECK7: omp.loop.exit:
2091 // CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2092 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4
2093 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])
2094 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2095 // CHECK7-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
2096 // CHECK7-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
2097 // CHECK7: .omp.lastprivate.then:
2098 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4
2099 // CHECK7-NEXT: store i32 [[TMP24]], i32* [[T_VAR_ADDR]], align 4
2100 // CHECK7-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2101 // CHECK7-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
2102 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 8, i1 false)
2103 // CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
2104 // CHECK7-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S*
2105 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i32 2
2106 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN9]], [[TMP28]]
2107 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2108 // CHECK7: omp.arraycpy.body:
2109 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2110 // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2111 // CHECK7-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
2112 // CHECK7-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
2113 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false)
2114 // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2115 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2116 // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]]
2117 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]]
2118 // CHECK7: omp.arraycpy.done10:
2119 // CHECK7-NEXT: [[TMP31:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4
2120 // CHECK7-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP3]] to i8*
2121 // CHECK7-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP31]] to i8*
2122 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false)
2123 // CHECK7-NEXT: [[TMP34:%.*]] = load i32, i32* [[SVAR7]], align 4
2124 // CHECK7-NEXT: store i32 [[TMP34]], i32* [[SVAR_ADDR]], align 4
2125 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
2126 // CHECK7: .omp.lastprivate.done:
2127 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
2128 // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0
2129 // CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2
2130 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2131 // CHECK7: arraydestroy.body:
2132 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2133 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2134 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2135 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
2136 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
2137 // CHECK7: arraydestroy.done12:
2138 // CHECK7-NEXT: ret void
2139 //
2140 //
2141 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1
2142 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] {
2143 // CHECK7-NEXT: entry:
2144 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2145 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2146 // CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2147 // CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2148 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2149 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2150 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
2151 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
2152 // CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
2153 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4
2154 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2155 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2156 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2157 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2158 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2159 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2160 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
2161 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
2162 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4
2163 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2164 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4
2165 // CHECK7-NEXT: [[SVAR7:%.*]] = alloca i32, align 4
2166 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
2167 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2168 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2169 // CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2170 // CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2171 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2172 // CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2173 // CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2174 // CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
2175 // CHECK7-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4
2176 // CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2177 // CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2178 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
2179 // CHECK7-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4
2180 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2181 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2182 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2183 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2184 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
2185 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
2186 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2187 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2188 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0
2189 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
2190 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2191 // CHECK7: arrayctor.loop:
2192 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2193 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2194 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
2195 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2196 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2197 // CHECK7: arrayctor.cont:
2198 // CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4
2199 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR5]])
2200 // CHECK7-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4
2201 // CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2202 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
2203 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2204 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2205 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
2206 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2207 // CHECK7: cond.true:
2208 // CHECK7-NEXT: br label [[COND_END:%.*]]
2209 // CHECK7: cond.false:
2210 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2211 // CHECK7-NEXT: br label [[COND_END]]
2212 // CHECK7: cond.end:
2213 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
2214 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2215 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2216 // CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
2217 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2218 // CHECK7: omp.inner.for.cond:
2219 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2220 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2221 // CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
2222 // CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2223 // CHECK7: omp.inner.for.cond.cleanup:
2224 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2225 // CHECK7: omp.inner.for.body:
2226 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2227 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
2228 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2229 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2230 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4
2231 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
2232 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP15]]
2233 // CHECK7-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4
2234 // CHECK7-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4
2235 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
2236 // CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP17]]
2237 // CHECK7-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8*
2238 // CHECK7-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8*
2239 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false)
2240 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2241 // CHECK7: omp.body.continue:
2242 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2243 // CHECK7: omp.inner.for.inc:
2244 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2245 // CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
2246 // CHECK7-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4
2247 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]]
2248 // CHECK7: omp.inner.for.end:
2249 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2250 // CHECK7: omp.loop.exit:
2251 // CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2252 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4
2253 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
2254 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2255 // CHECK7-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
2256 // CHECK7-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
2257 // CHECK7: .omp.lastprivate.then:
2258 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4
2259 // CHECK7-NEXT: store i32 [[TMP25]], i32* [[T_VAR_ADDR]], align 4
2260 // CHECK7-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2261 // CHECK7-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
2262 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 8, i1 false)
2263 // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
2264 // CHECK7-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S*
2265 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2
2266 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP29]]
2267 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2268 // CHECK7: omp.arraycpy.body:
2269 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2270 // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2271 // CHECK7-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
2272 // CHECK7-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
2273 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false)
2274 // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2275 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2276 // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]]
2277 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]]
2278 // CHECK7: omp.arraycpy.done12:
2279 // CHECK7-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4
2280 // CHECK7-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP5]] to i8*
2281 // CHECK7-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8*
2282 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false)
2283 // CHECK7-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR7]], align 4
2284 // CHECK7-NEXT: store i32 [[TMP35]], i32* [[SVAR_ADDR]], align 4
2285 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
2286 // CHECK7: .omp.lastprivate.done:
2287 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
2288 // CHECK7-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0
2289 // CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2
2290 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2291 // CHECK7: arraydestroy.body:
2292 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2293 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2294 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2295 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
2296 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
2297 // CHECK7: arraydestroy.done14:
2298 // CHECK7-NEXT: ret void
2299 //
2300 //
2301 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2302 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2303 // CHECK7-NEXT: entry:
2304 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2305 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2306 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2307 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2308 // CHECK7-NEXT: ret void
2309 //
2310 //
2311 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2312 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat {
2313 // CHECK7-NEXT: entry:
2314 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2315 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2316 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2317 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2318 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2319 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
2320 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
2321 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2322 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
2323 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
2324 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
2325 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2326 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
2327 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4
2328 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
2329 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
2330 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2331 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
2332 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
2333 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
2334 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
2335 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
2336 // CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4
2337 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
2338 // CHECK7-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4
2339 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2340 // CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2341 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2342 // CHECK7-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]**
2343 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 4
2344 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2345 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]**
2346 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4
2347 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2348 // CHECK7-NEXT: store i8* null, i8** [[TMP9]], align 4
2349 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2350 // CHECK7-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
2351 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
2352 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2353 // CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
2354 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
2355 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2356 // CHECK7-NEXT: store i8* null, i8** [[TMP14]], align 4
2357 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2358 // CHECK7-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]**
2359 // CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 4
2360 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2361 // CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
2362 // CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4
2363 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2364 // CHECK7-NEXT: store i8* null, i8** [[TMP19]], align 4
2365 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2366 // CHECK7-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0**
2367 // CHECK7-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 4
2368 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2369 // CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
2370 // CHECK7-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 4
2371 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2372 // CHECK7-NEXT: store i8* null, i8** [[TMP24]], align 4
2373 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2374 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2375 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2376 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
2377 // CHECK7-NEXT: store i32 1, i32* [[TMP27]], align 4
2378 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
2379 // CHECK7-NEXT: store i32 4, i32* [[TMP28]], align 4
2380 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
2381 // CHECK7-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 4
2382 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
2383 // CHECK7-NEXT: store i8** [[TMP26]], i8*** [[TMP30]], align 4
2384 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
2385 // CHECK7-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64** [[TMP31]], align 4
2386 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
2387 // CHECK7-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i64** [[TMP32]], align 4
2388 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
2389 // CHECK7-NEXT: store i8** null, i8*** [[TMP33]], align 4
2390 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
2391 // CHECK7-NEXT: store i8** null, i8*** [[TMP34]], align 4
2392 // CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
2393 // CHECK7-NEXT: store i64 2, i64* [[TMP35]], align 8
2394 // CHECK7-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
2395 // CHECK7-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0
2396 // CHECK7-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2397 // CHECK7: omp_offload.failed:
2398 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]]
2399 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
2400 // CHECK7: omp_offload.cont:
2401 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
2402 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2403 // CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2404 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2405 // CHECK7: arraydestroy.body:
2406 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2407 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2408 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2409 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2410 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
2411 // CHECK7: arraydestroy.done2:
2412 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
2413 // CHECK7-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4
2414 // CHECK7-NEXT: ret i32 [[TMP39]]
2415 //
2416 //
2417 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2418 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2419 // CHECK7-NEXT: entry:
2420 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2421 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2422 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2423 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2424 // CHECK7-NEXT: store float 0.000000e+00, float* [[F]], align 4
2425 // CHECK7-NEXT: ret void
2426 //
2427 //
2428 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2429 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2430 // CHECK7-NEXT: entry:
2431 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2432 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2433 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2434 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2435 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2436 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2437 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2438 // CHECK7-NEXT: store float [[TMP0]], float* [[F]], align 4
2439 // CHECK7-NEXT: ret void
2440 //
2441 //
2442 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2443 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2444 // CHECK7-NEXT: entry:
2445 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2446 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2447 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2448 // CHECK7-NEXT: ret void
2449 //
2450 //
2451 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2452 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2453 // CHECK7-NEXT: entry:
2454 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2455 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2456 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2457 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2458 // CHECK7-NEXT: ret void
2459 //
2460 //
2461 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2462 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2463 // CHECK7-NEXT: entry:
2464 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2465 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2466 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2467 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2468 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2469 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2470 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
2471 // CHECK7-NEXT: ret void
2472 //
2473 //
2474 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50
2475 // CHECK7-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
2476 // CHECK7-NEXT: entry:
2477 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2478 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2479 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
2480 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
2481 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
2482 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2483 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2484 // CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2485 // CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2486 // CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
2487 // CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2488 // CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2489 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
2490 // CHECK7-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
2491 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
2492 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
2493 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2494 // CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2495 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
2496 // CHECK7-NEXT: ret void
2497 //
2498 //
2499 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2
2500 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
2501 // CHECK7-NEXT: entry:
2502 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2503 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2504 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2505 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2506 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
2507 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
2508 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
2509 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2510 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2511 // CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2512 // CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2513 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2514 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2515 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
2516 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
2517 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
2518 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2519 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4
2520 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
2521 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2522 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2523 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2524 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2525 // CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2526 // CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2527 // CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
2528 // CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2529 // CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2530 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
2531 // CHECK7-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
2532 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2533 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
2534 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2535 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2536 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
2537 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2538 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2539 // CHECK7: arrayctor.loop:
2540 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2541 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2542 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
2543 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2544 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2545 // CHECK7: arrayctor.cont:
2546 // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2547 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]])
2548 // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4
2549 // CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2550 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
2551 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2552 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2553 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
2554 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2555 // CHECK7: cond.true:
2556 // CHECK7-NEXT: br label [[COND_END:%.*]]
2557 // CHECK7: cond.false:
2558 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2559 // CHECK7-NEXT: br label [[COND_END]]
2560 // CHECK7: cond.end:
2561 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
2562 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2563 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2564 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
2565 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2566 // CHECK7: omp.inner.for.cond:
2567 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2568 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2569 // CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
2570 // CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2571 // CHECK7: omp.inner.for.cond.cleanup:
2572 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2573 // CHECK7: omp.inner.for.body:
2574 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2575 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2576 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4
2577 // CHECK7-NEXT: store i32 [[TMP13]], i32* [[T_VAR_CASTED]], align 4
2578 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2579 // CHECK7-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4
2580 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP11]], i32 [[TMP12]], [2 x i32]* [[VEC3]], i32 [[TMP14]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP15]])
2581 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2582 // CHECK7: omp.inner.for.inc:
2583 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2584 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2585 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
2586 // CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2587 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]]
2588 // CHECK7: omp.inner.for.end:
2589 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2590 // CHECK7: omp.loop.exit:
2591 // CHECK7-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2592 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4
2593 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
2594 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2595 // CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
2596 // CHECK7-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
2597 // CHECK7: .omp.lastprivate.then:
2598 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR2]], align 4
2599 // CHECK7-NEXT: store i32 [[TMP22]], i32* [[T_VAR_ADDR]], align 4
2600 // CHECK7-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2601 // CHECK7-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
2602 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i32 8, i1 false)
2603 // CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
2604 // CHECK7-NEXT: [[TMP25:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0*
2605 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2
2606 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN8]], [[TMP26]]
2607 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2608 // CHECK7: omp.arraycpy.body:
2609 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2610 // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN8]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2611 // CHECK7-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
2612 // CHECK7-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
2613 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false)
2614 // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2615 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2616 // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP26]]
2617 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]]
2618 // CHECK7: omp.arraycpy.done9:
2619 // CHECK7-NEXT: [[TMP29:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4
2620 // CHECK7-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8*
2621 // CHECK7-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP29]] to i8*
2622 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false)
2623 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
2624 // CHECK7: .omp.lastprivate.done:
2625 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
2626 // CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
2627 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2
2628 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2629 // CHECK7: arraydestroy.body:
2630 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2631 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2632 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2633 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
2634 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
2635 // CHECK7: arraydestroy.done11:
2636 // CHECK7-NEXT: ret void
2637 //
2638 //
2639 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3
2640 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
2641 // CHECK7-NEXT: entry:
2642 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2643 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2644 // CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2645 // CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2646 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2647 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2648 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
2649 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
2650 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
2651 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2652 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2653 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2654 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2655 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2656 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2657 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
2658 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
2659 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
2660 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2661 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4
2662 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
2663 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2664 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2665 // CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2666 // CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2667 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2668 // CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2669 // CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2670 // CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
2671 // CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2672 // CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2673 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
2674 // CHECK7-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
2675 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2676 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2677 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2678 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2679 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
2680 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
2681 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2682 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2683 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
2684 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2685 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2686 // CHECK7: arrayctor.loop:
2687 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2688 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2689 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
2690 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2691 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2692 // CHECK7: arrayctor.cont:
2693 // CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2694 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]])
2695 // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4
2696 // CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2697 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
2698 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2699 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2700 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
2701 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2702 // CHECK7: cond.true:
2703 // CHECK7-NEXT: br label [[COND_END:%.*]]
2704 // CHECK7: cond.false:
2705 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2706 // CHECK7-NEXT: br label [[COND_END]]
2707 // CHECK7: cond.end:
2708 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
2709 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2710 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2711 // CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
2712 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2713 // CHECK7: omp.inner.for.cond:
2714 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2715 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2716 // CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
2717 // CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2718 // CHECK7: omp.inner.for.cond.cleanup:
2719 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2720 // CHECK7: omp.inner.for.body:
2721 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2722 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
2723 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2724 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2725 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4
2726 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
2727 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP15]]
2728 // CHECK7-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4
2729 // CHECK7-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4
2730 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
2731 // CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP17]]
2732 // CHECK7-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8*
2733 // CHECK7-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8*
2734 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false)
2735 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2736 // CHECK7: omp.body.continue:
2737 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2738 // CHECK7: omp.inner.for.inc:
2739 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2740 // CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1
2741 // CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
2742 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]]
2743 // CHECK7: omp.inner.for.end:
2744 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2745 // CHECK7: omp.loop.exit:
2746 // CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2747 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4
2748 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
2749 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2750 // CHECK7-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
2751 // CHECK7-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
2752 // CHECK7: .omp.lastprivate.then:
2753 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4
2754 // CHECK7-NEXT: store i32 [[TMP25]], i32* [[T_VAR_ADDR]], align 4
2755 // CHECK7-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2756 // CHECK7-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
2757 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 8, i1 false)
2758 // CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
2759 // CHECK7-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0*
2760 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2
2761 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP29]]
2762 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2763 // CHECK7: omp.arraycpy.body:
2764 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2765 // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2766 // CHECK7-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
2767 // CHECK7-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
2768 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false)
2769 // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2770 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2771 // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]]
2772 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]]
2773 // CHECK7: omp.arraycpy.done11:
2774 // CHECK7-NEXT: [[TMP32:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4
2775 // CHECK7-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8*
2776 // CHECK7-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP32]] to i8*
2777 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false)
2778 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
2779 // CHECK7: .omp.lastprivate.done:
2780 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
2781 // CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
2782 // CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2
2783 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2784 // CHECK7: arraydestroy.body:
2785 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2786 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2787 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2788 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
2789 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
2790 // CHECK7: arraydestroy.done13:
2791 // CHECK7-NEXT: ret void
2792 //
2793 //
2794 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2795 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2796 // CHECK7-NEXT: entry:
2797 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2798 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2799 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2800 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2801 // CHECK7-NEXT: ret void
2802 //
2803 //
2804 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2805 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2806 // CHECK7-NEXT: entry:
2807 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2808 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2809 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2810 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2811 // CHECK7-NEXT: store i32 0, i32* [[F]], align 4
2812 // CHECK7-NEXT: ret void
2813 //
2814 //
2815 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2816 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2817 // CHECK7-NEXT: entry:
2818 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2819 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2820 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2821 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2822 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2823 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2824 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2825 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
2826 // CHECK7-NEXT: ret void
2827 //
2828 //
2829 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2830 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2831 // CHECK7-NEXT: entry:
2832 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2833 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2834 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2835 // CHECK7-NEXT: ret void
2836 //
2837 //
2838 // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2839 // CHECK7-SAME: () #[[ATTR6:[0-9]+]] {
2840 // CHECK7-NEXT: entry:
2841 // CHECK7-NEXT: call void @__tgt_register_requires(i64 1)
2842 // CHECK7-NEXT: ret void
2843 //
2844