1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2 6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 9 10 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 17 // Test target codegen - host bc file has to be created first. 18 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 19 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 22 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 23 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 24 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 25 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 26 27 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 28 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 29 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 30 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 31 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 32 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 33 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 34 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 35 36 // Test host codegen. 37 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 38 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 39 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK18 40 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 41 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 42 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK20 43 44 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 45 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 46 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 47 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 48 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 49 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 50 51 // Test target codegen - host bc file has to be created first. 52 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 53 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK25 54 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 55 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK26 56 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 57 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK27 58 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 59 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK28 60 61 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 62 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 63 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 64 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 65 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 66 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 67 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 68 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 69 70 // expected-no-diagnostics 71 #ifndef HEADER 72 #define HEADER 73 74 75 76 77 // We have 8 target regions, but only 7 that actually will generate offloading 78 // code, only 6 will have mapped arguments, and only 4 have all-constant map 79 // sizes. 80 81 82 83 // Check target registration is registered as a Ctor. 84 85 86 template<typename tx, typename ty> 87 struct TT{ 88 tx X; 89 ty Y; 90 }; 91 92 long long get_val() { return 0; } 93 94 int foo(int n) { 95 int a = 0; 96 short aa = 0; 97 float b[10]; 98 float bn[n]; 99 double c[5][10]; 100 double cn[5][n]; 101 TT<long long, char> d; 102 103 #pragma omp target parallel for 104 for (int i = 3; i < 32; i += 5) { 105 #pragma omp cancel for 106 #pragma omp cancellation point for 107 } 108 109 long long k = get_val(); 110 #pragma omp target parallel for if(target: 0) linear(k : 3) schedule(dynamic) 111 for (int i = 10; i > 1; i--) { 112 a += 1; 113 } 114 115 // CEHCK-32: [[FPSIZEGEP]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 0 116 // CEHCK-32: [[FPSIZEADDR:%.+]] = bitcast [3 x i64]* [[FPSIZEGEP]] to i8* 117 // CEHCK-32: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPSIZEADDR]], i8* align 8 bitcast ([3 x i64]* [[SIZET2]] to i8*), i64 24, i1 false) 118 // CEHCK-32: [[FPBPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 1 119 // CEHCK-32: [[FPBPADDR:%.+]] = bitcast [3 x i8*]* [[FPBPGEP]] to i8* 120 // CEHCK-32: [[BPCAST:%.+]] = bitcast i8** [[BPGEP]] to i8* 121 // CEHCK-32: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPBPADDR]], i8* align 8 [[BPCAST]], i64 24, i1 false) 122 // CEHCK-32: [[FPPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 2 123 // CEHCK-32: [[FPPADDR:%.+]] = bitcast [3 x i8*]* [[FPPGEP]] to i8* 124 // CEHCK-32: [[PCAST:%.+]] = bitcast i8** [[PGEP]] to i8* 125 // CEHCK-32: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPPADDR]], i8* align 8 [[BCAST]], i64 24, i1 false) 126 // CEHCK-64: [[FPBPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 0 127 // CEHCK-64: [[FPBPADDR:%.+]] = bitcast [3 x i8*]* [[FPBPGEP]] to i8* 128 // CEHCK-64: [[BPCAST:%.+]] = bitcast i8** [[BPGEP]] to i8* 129 // CEHCK-64: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPBPADDR]], i8* align 8 [[BPCAST]], i64 24, i1 false) 130 // CEHCK-64: [[FPPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 1 131 // CEHCK-64: [[FPPADDR:%.+]] = bitcast [3 x i8*]* [[FPPGEP]] to i8* 132 // CEHCK-64: [[PCAST:%.+]] = bitcast i8** [[PGEP]] to i8* 133 // CEHCK-64: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPPADDR]], i8* align 8 [[BCAST]], i64 24, i1 false) 134 // CEHCK-64: [[FPSIZEGEP]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 2 135 // CEHCK-64: [[FPSIZEADDR:%.+]] = bitcast [3 x i64]* [[FPSIZEGEP]] to i8* 136 // CEHCK-64: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPSIZEADDR]], i8* align 8 bitcast ([3 x i64]* [[SIZET2]] to i8*), i64 24, i1 false) 137 int lin = 12; 138 #pragma omp target parallel for if(target: 1) linear(lin, a : get_val()) nowait 139 for (unsigned long long it = 2000; it >= 600; it-=400) { 140 aa += 1; 141 } 142 143 144 145 146 #pragma omp target parallel for if(target: n>10) 147 for (short it = 6; it <= 20; it-=-4) { 148 a += 1; 149 aa += 1; 150 } 151 152 // We capture 3 VLA sizes in this target region 153 154 155 156 157 158 // The names below are not necessarily consistent with the names used for the 159 // addresses above as some are repeated. 160 161 162 163 164 165 166 167 168 169 170 #pragma omp target parallel for if(target: n>20) schedule(static, a) 171 for (unsigned char it = 'z'; it >= 'a'; it+=-1) { 172 a += 1; 173 b[2] += 1.0; 174 bn[3] += 1.0; 175 c[1][2] += 1.0; 176 cn[1][3] += 1.0; 177 d.X += 1; 178 d.Y += 1; 179 } 180 181 return a; 182 } 183 184 // Check that the offloading functions are emitted and that the arguments are 185 // correct and loaded correctly for the target regions in foo(). 186 187 188 // Create stack storage and store argument in there. 189 190 // Create stack storage and store argument in there. 191 192 193 // Create stack storage and store argument in there. 194 195 // Create local storage for each capture. 196 197 198 199 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 200 201 template<typename tx> 202 tx ftemplate(int n) { 203 tx a = 0; 204 short aa = 0; 205 tx b[10]; 206 207 #pragma omp target parallel for if(target: n>40) 208 for (long long i = -10; i < 10; i += 3) { 209 a += 1; 210 aa += 1; 211 b[2] += 1; 212 } 213 214 return a; 215 } 216 217 static 218 int fstatic(int n) { 219 int a = 0; 220 short aa = 0; 221 char aaa = 0; 222 int b[10]; 223 224 #pragma omp target parallel for if(target: n>50) 225 for (unsigned i=100; i<10; i+=10) { 226 a += 1; 227 aa += 1; 228 aaa += 1; 229 b[2] += 1; 230 } 231 232 return a; 233 } 234 235 struct S1 { 236 double a; 237 238 int r1(int n){ 239 int b = n+1; 240 short int c[2][n]; 241 242 #pragma omp target parallel for if(target: n>60) 243 for (unsigned long long it = 2000; it >= 600; it -= 400) { 244 this->a = (double)b + 1.5; 245 c[1][1] = ++a; 246 } 247 248 return c[1][1] + (int)b; 249 } 250 }; 251 252 int bar(int n){ 253 int a = 0; 254 255 a += foo(n); 256 257 S1 S; 258 a += S.r1(n); 259 260 a += fstatic(n); 261 262 a += ftemplate<int>(n); 263 264 return a; 265 } 266 267 268 269 // We capture 2 VLA sizes in this target region 270 271 272 // The names below are not necessarily consistent with the names used for the 273 // addresses above as some are repeated. 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 // Check that the offloading functions are emitted and that the arguments are 293 // correct and loaded correctly for the target regions of the callees of bar(). 294 295 // Create local storage for each capture. 296 // Store captures in the context. 297 298 299 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 300 301 302 // Create local storage for each capture. 303 // Store captures in the context. 304 305 306 307 308 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 309 310 // Create local storage for each capture. 311 // Store captures in the context. 312 313 314 315 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 316 317 318 #endif 319 // CHECK1-LABEL: define {{[^@]+}}@_Z7get_valv 320 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 321 // CHECK1-NEXT: entry: 322 // CHECK1-NEXT: ret i64 0 323 // 324 // 325 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 326 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 327 // CHECK1-NEXT: entry: 328 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 329 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 330 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 331 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 332 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 333 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 334 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 335 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 336 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 337 // CHECK1-NEXT: [[K:%.*]] = alloca i64, align 8 338 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 339 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 340 // CHECK1-NEXT: [[LIN:%.*]] = alloca i32, align 4 341 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 342 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 343 // CHECK1-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8 344 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 345 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 346 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 347 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 348 // CHECK1-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8 349 // CHECK1-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8 350 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 351 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 352 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 353 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 354 // CHECK1-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8 355 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 356 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8 357 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8 358 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8 359 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 360 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 361 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 362 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 363 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 364 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 365 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 366 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 367 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 368 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 369 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 370 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 371 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 372 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 373 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 374 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 375 // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 376 // CHECK1-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 377 // CHECK1-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 378 // CHECK1: omp_offload.failed: 379 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 380 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 381 // CHECK1: omp_offload.cont: 382 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 383 // CHECK1-NEXT: store i64 [[CALL]], i64* [[K]], align 8 384 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 385 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 386 // CHECK1-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4 387 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8 388 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[K]], align 8 389 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[K_CASTED]], align 8 390 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8 391 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR4]] 392 // CHECK1-NEXT: store i32 12, i32* [[LIN]], align 4 393 // CHECK1-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 394 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 395 // CHECK1-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 396 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 397 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4 398 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 399 // CHECK1-NEXT: store i32 [[TMP15]], i32* [[CONV3]], align 4 400 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 401 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 402 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32* 403 // CHECK1-NEXT: store i32 [[TMP17]], i32* [[CONV5]], align 4 404 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8 405 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 406 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 407 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP20]], align 8 408 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 409 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 410 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP22]], align 8 411 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 412 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 413 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 414 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 415 // CHECK1-NEXT: store i64 [[TMP16]], i64* [[TMP25]], align 8 416 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 417 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 418 // CHECK1-NEXT: store i64 [[TMP16]], i64* [[TMP27]], align 8 419 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 420 // CHECK1-NEXT: store i8* null, i8** [[TMP28]], align 8 421 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 422 // CHECK1-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 423 // CHECK1-NEXT: store i64 [[TMP18]], i64* [[TMP30]], align 8 424 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 425 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 426 // CHECK1-NEXT: store i64 [[TMP18]], i64* [[TMP32]], align 8 427 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 428 // CHECK1-NEXT: store i8* null, i8** [[TMP33]], align 8 429 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 430 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 431 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 432 // CHECK1-NEXT: [[TMP37:%.*]] = load i16, i16* [[AA]], align 2 433 // CHECK1-NEXT: store i16 [[TMP37]], i16* [[TMP36]], align 4 434 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 435 // CHECK1-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4 436 // CHECK1-NEXT: store i32 [[TMP39]], i32* [[TMP38]], align 4 437 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 438 // CHECK1-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 439 // CHECK1-NEXT: store i32 [[TMP41]], i32* [[TMP40]], align 4 440 // CHECK1-NEXT: [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 441 // CHECK1-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates* 442 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0 443 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0 444 // CHECK1-NEXT: [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8 445 // CHECK1-NEXT: [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 446 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false) 447 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1 448 // CHECK1-NEXT: [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon* 449 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0 450 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8* 451 // CHECK1-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8* 452 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false) 453 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1 454 // CHECK1-NEXT: [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8* 455 // CHECK1-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8* 456 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false) 457 // CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2 458 // CHECK1-NEXT: [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8* 459 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 460 // CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3 461 // CHECK1-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 462 // CHECK1-NEXT: store i16 [[TMP59]], i16* [[TMP58]], align 8 463 // CHECK1-NEXT: [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]]) 464 // CHECK1-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4 465 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32* 466 // CHECK1-NEXT: store i32 [[TMP61]], i32* [[CONV7]], align 4 467 // CHECK1-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8 468 // CHECK1-NEXT: [[TMP63:%.*]] = load i16, i16* [[AA]], align 2 469 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16* 470 // CHECK1-NEXT: store i16 [[TMP63]], i16* [[CONV9]], align 2 471 // CHECK1-NEXT: [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8 472 // CHECK1-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4 473 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10 474 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 475 // CHECK1: omp_if.then: 476 // CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 477 // CHECK1-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64* 478 // CHECK1-NEXT: store i64 [[TMP62]], i64* [[TMP67]], align 8 479 // CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 480 // CHECK1-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* 481 // CHECK1-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8 482 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 483 // CHECK1-NEXT: store i8* null, i8** [[TMP70]], align 8 484 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 485 // CHECK1-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* 486 // CHECK1-NEXT: store i64 [[TMP64]], i64* [[TMP72]], align 8 487 // CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 488 // CHECK1-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* 489 // CHECK1-NEXT: store i64 [[TMP64]], i64* [[TMP74]], align 8 490 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 491 // CHECK1-NEXT: store i8* null, i8** [[TMP75]], align 8 492 // CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 493 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 494 // CHECK1-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 495 // CHECK1-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0 496 // CHECK1-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]] 497 // CHECK1: omp_offload.failed13: 498 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 499 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT14]] 500 // CHECK1: omp_offload.cont14: 501 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 502 // CHECK1: omp_if.else: 503 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 504 // CHECK1-NEXT: br label [[OMP_IF_END]] 505 // CHECK1: omp_if.end: 506 // CHECK1-NEXT: [[TMP80:%.*]] = load i32, i32* [[A]], align 4 507 // CHECK1-NEXT: store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4 508 // CHECK1-NEXT: [[TMP81:%.*]] = load i32, i32* [[A]], align 4 509 // CHECK1-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32* 510 // CHECK1-NEXT: store i32 [[TMP81]], i32* [[CONV16]], align 4 511 // CHECK1-NEXT: [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8 512 // CHECK1-NEXT: [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 513 // CHECK1-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 514 // CHECK1-NEXT: store i32 [[TMP83]], i32* [[CONV17]], align 4 515 // CHECK1-NEXT: [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 516 // CHECK1-NEXT: [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4 517 // CHECK1-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20 518 // CHECK1-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 519 // CHECK1: omp_if.then19: 520 // CHECK1-NEXT: [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4 521 // CHECK1-NEXT: [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]] 522 // CHECK1-NEXT: [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8 523 // CHECK1-NEXT: [[TMP89:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 524 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP89]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i64 80, i1 false) 525 // CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 526 // CHECK1-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i64* 527 // CHECK1-NEXT: store i64 [[TMP82]], i64* [[TMP91]], align 8 528 // CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 529 // CHECK1-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to i64* 530 // CHECK1-NEXT: store i64 [[TMP82]], i64* [[TMP93]], align 8 531 // CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 532 // CHECK1-NEXT: store i8* null, i8** [[TMP94]], align 8 533 // CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 534 // CHECK1-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 535 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8 536 // CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 537 // CHECK1-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]** 538 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8 539 // CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 540 // CHECK1-NEXT: store i8* null, i8** [[TMP99]], align 8 541 // CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 542 // CHECK1-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64* 543 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP101]], align 8 544 // CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 545 // CHECK1-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i64* 546 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP103]], align 8 547 // CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 548 // CHECK1-NEXT: store i8* null, i8** [[TMP104]], align 8 549 // CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 550 // CHECK1-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** 551 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP106]], align 8 552 // CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 553 // CHECK1-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** 554 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP108]], align 8 555 // CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 556 // CHECK1-NEXT: store i64 [[TMP86]], i64* [[TMP109]], align 8 557 // CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 558 // CHECK1-NEXT: store i8* null, i8** [[TMP110]], align 8 559 // CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 560 // CHECK1-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** 561 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 8 562 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 563 // CHECK1-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** 564 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8 565 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 566 // CHECK1-NEXT: store i8* null, i8** [[TMP115]], align 8 567 // CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 568 // CHECK1-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64* 569 // CHECK1-NEXT: store i64 5, i64* [[TMP117]], align 8 570 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 571 // CHECK1-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i64* 572 // CHECK1-NEXT: store i64 5, i64* [[TMP119]], align 8 573 // CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5 574 // CHECK1-NEXT: store i8* null, i8** [[TMP120]], align 8 575 // CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 576 // CHECK1-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64* 577 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP122]], align 8 578 // CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 579 // CHECK1-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i64* 580 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP124]], align 8 581 // CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6 582 // CHECK1-NEXT: store i8* null, i8** [[TMP125]], align 8 583 // CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 584 // CHECK1-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** 585 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP127]], align 8 586 // CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 587 // CHECK1-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to double** 588 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP129]], align 8 589 // CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 590 // CHECK1-NEXT: store i64 [[TMP88]], i64* [[TMP130]], align 8 591 // CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7 592 // CHECK1-NEXT: store i8* null, i8** [[TMP131]], align 8 593 // CHECK1-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 594 // CHECK1-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT** 595 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 8 596 // CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 597 // CHECK1-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to %struct.TT** 598 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP135]], align 8 599 // CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8 600 // CHECK1-NEXT: store i8* null, i8** [[TMP136]], align 8 601 // CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9 602 // CHECK1-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i64* 603 // CHECK1-NEXT: store i64 [[TMP84]], i64* [[TMP138]], align 8 604 // CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9 605 // CHECK1-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to i64* 606 // CHECK1-NEXT: store i64 [[TMP84]], i64* [[TMP140]], align 8 607 // CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9 608 // CHECK1-NEXT: store i8* null, i8** [[TMP141]], align 8 609 // CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 610 // CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 611 // CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 612 // CHECK1-NEXT: [[TMP145:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP142]], i8** [[TMP143]], i64* [[TMP144]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 613 // CHECK1-NEXT: [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 0 614 // CHECK1-NEXT: br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 615 // CHECK1: omp_offload.failed23: 616 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 617 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT24]] 618 // CHECK1: omp_offload.cont24: 619 // CHECK1-NEXT: br label [[OMP_IF_END26:%.*]] 620 // CHECK1: omp_if.else25: 621 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 622 // CHECK1-NEXT: br label [[OMP_IF_END26]] 623 // CHECK1: omp_if.end26: 624 // CHECK1-NEXT: [[TMP147:%.*]] = load i32, i32* [[A]], align 4 625 // CHECK1-NEXT: [[TMP148:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 626 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP148]]) 627 // CHECK1-NEXT: ret i32 [[TMP147]] 628 // 629 // 630 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 631 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] { 632 // CHECK1-NEXT: entry: 633 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 634 // CHECK1-NEXT: ret void 635 // 636 // 637 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 638 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 639 // CHECK1-NEXT: entry: 640 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 641 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 642 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 643 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 644 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 645 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 646 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 647 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 648 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 649 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 650 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 651 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 652 // CHECK1-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 653 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 654 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 655 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 656 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 657 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 658 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 659 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 660 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 661 // CHECK1: cond.true: 662 // CHECK1-NEXT: br label [[COND_END:%.*]] 663 // CHECK1: cond.false: 664 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 665 // CHECK1-NEXT: br label [[COND_END]] 666 // CHECK1: cond.end: 667 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 668 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 669 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 670 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 671 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 672 // CHECK1: omp.inner.for.cond: 673 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 674 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 675 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 676 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 677 // CHECK1: omp.inner.for.body: 678 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 679 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 680 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 681 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 682 // CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 683 // CHECK1-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 684 // CHECK1-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 685 // CHECK1: .cancel.exit: 686 // CHECK1-NEXT: br label [[CANCEL_EXIT:%.*]] 687 // CHECK1: .cancel.continue: 688 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 689 // CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 690 // CHECK1-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 691 // CHECK1: .cancel.exit2: 692 // CHECK1-NEXT: br label [[CANCEL_EXIT]] 693 // CHECK1: .cancel.continue3: 694 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 695 // CHECK1: omp.body.continue: 696 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 697 // CHECK1: omp.inner.for.inc: 698 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 699 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 700 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 701 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 702 // CHECK1: omp.inner.for.end: 703 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 704 // CHECK1: omp.loop.exit: 705 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 706 // CHECK1-NEXT: br label [[CANCEL_CONT:%.*]] 707 // CHECK1: cancel.cont: 708 // CHECK1-NEXT: ret void 709 // CHECK1: cancel.exit: 710 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 711 // CHECK1-NEXT: br label [[CANCEL_CONT]] 712 // 713 // 714 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 715 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 716 // CHECK1-NEXT: entry: 717 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 718 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 719 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 720 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 721 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 722 // CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 723 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 724 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 725 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 726 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 727 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 728 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 729 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 730 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 731 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 732 // CHECK1-NEXT: ret void 733 // 734 // 735 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 736 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 737 // CHECK1-NEXT: entry: 738 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 739 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 740 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 741 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 742 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 743 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 744 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 745 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 746 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 747 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 748 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 749 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 750 // CHECK1-NEXT: [[K1:%.*]] = alloca i64, align 8 751 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 752 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 753 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 754 // CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 755 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 756 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8 757 // CHECK1-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8 758 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 759 // CHECK1-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 760 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 761 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 762 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 763 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 764 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 765 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1) 766 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 767 // CHECK1: omp.dispatch.cond: 768 // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 769 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 770 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 771 // CHECK1: omp.dispatch.body: 772 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 773 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 774 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 775 // CHECK1: omp.inner.for.cond: 776 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 777 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 778 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 779 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 780 // CHECK1: omp.inner.for.body: 781 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 782 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 783 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 784 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12 785 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12 786 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 787 // CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 788 // CHECK1-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 789 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] 790 // CHECK1-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12 791 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12 792 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 793 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12 794 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 795 // CHECK1: omp.body.continue: 796 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 797 // CHECK1: omp.inner.for.inc: 798 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 799 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 800 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 801 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 802 // CHECK1: omp.inner.for.end: 803 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 804 // CHECK1: omp.dispatch.inc: 805 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 806 // CHECK1: omp.dispatch.end: 807 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 808 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 809 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 810 // CHECK1: .omp.linear.pu: 811 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[K1]], align 8 812 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[K_ADDR]], align 8 813 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 814 // CHECK1: .omp.linear.pu.done: 815 // CHECK1-NEXT: ret void 816 // 817 // 818 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 819 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 820 // CHECK1-NEXT: entry: 821 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 822 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 823 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 824 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 825 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 826 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 827 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 828 // CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 829 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 830 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 831 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 832 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 833 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 834 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 835 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 836 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 837 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 838 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 839 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 840 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 841 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 842 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 843 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 844 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 845 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 846 // CHECK1-NEXT: ret void 847 // 848 // 849 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 850 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 851 // CHECK1-NEXT: entry: 852 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 853 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 854 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 855 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 856 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 857 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 858 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 859 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 860 // CHECK1-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 861 // CHECK1-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 862 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 863 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 864 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 865 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 866 // CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8 867 // CHECK1-NEXT: [[LIN4:%.*]] = alloca i32, align 4 868 // CHECK1-NEXT: [[A5:%.*]] = alloca i32, align 4 869 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 870 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 871 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 872 // CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 873 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 874 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 875 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 876 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 877 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 878 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 879 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 880 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 881 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 882 // CHECK1-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 883 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 884 // CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 885 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 886 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 887 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 888 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 889 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 890 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 891 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 892 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 893 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 894 // CHECK1: cond.true: 895 // CHECK1-NEXT: br label [[COND_END:%.*]] 896 // CHECK1: cond.false: 897 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 898 // CHECK1-NEXT: br label [[COND_END]] 899 // CHECK1: cond.end: 900 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 901 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 902 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 903 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 904 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 905 // CHECK1: omp.inner.for.cond: 906 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 907 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 908 // CHECK1-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 909 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 910 // CHECK1: omp.inner.for.body: 911 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 912 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 913 // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 914 // CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 915 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 916 // CHECK1-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 917 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 918 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 919 // CHECK1-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 920 // CHECK1-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 921 // CHECK1-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 922 // CHECK1-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 923 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 924 // CHECK1-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 925 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 926 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 927 // CHECK1-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 928 // CHECK1-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 929 // CHECK1-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 930 // CHECK1-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 931 // CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 932 // CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 933 // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 934 // CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 935 // CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 936 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 937 // CHECK1: omp.body.continue: 938 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 939 // CHECK1: omp.inner.for.inc: 940 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 941 // CHECK1-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 942 // CHECK1-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 943 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 944 // CHECK1: omp.inner.for.end: 945 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 946 // CHECK1: omp.loop.exit: 947 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 948 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 949 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 950 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 951 // CHECK1: .omp.linear.pu: 952 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 953 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 954 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 955 // CHECK1-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 956 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 957 // CHECK1: .omp.linear.pu.done: 958 // CHECK1-NEXT: ret void 959 // 960 // 961 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. 962 // CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 963 // CHECK1-NEXT: entry: 964 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 965 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 966 // CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 967 // CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 968 // CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 969 // CHECK1-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 970 // CHECK1-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 971 // CHECK1-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 972 // CHECK1-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 973 // CHECK1-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 974 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 975 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 976 // CHECK1-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 977 // CHECK1-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 978 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 979 // CHECK1-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 980 // CHECK1-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 981 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 982 // CHECK1-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 983 // CHECK1-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 984 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 985 // CHECK1-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 986 // CHECK1-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 987 // CHECK1-NEXT: ret void 988 // 989 // 990 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 991 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 992 // CHECK1-NEXT: entry: 993 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 994 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 995 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 996 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 997 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 998 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 999 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 1000 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 1001 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 1002 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 1003 // CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 1004 // CHECK1-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8 1005 // CHECK1-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8 1006 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 1007 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 1008 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 1009 // CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 1010 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 1011 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 1012 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 1013 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 1014 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 1015 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 1016 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 1017 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 1018 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 1019 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 1020 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 1021 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 1022 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 1023 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 1024 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 1025 // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24 1026 // CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 1027 // CHECK1-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 1028 // CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24 1029 // CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 1030 // CHECK1-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 1031 // CHECK1-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 1032 // CHECK1-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 1033 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 1034 // CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 1035 // CHECK1-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 1036 // CHECK1-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 1037 // CHECK1-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 1038 // CHECK1-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24 1039 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 1040 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 1041 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 1042 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 1043 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 1044 // CHECK1-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 1045 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 1046 // CHECK1-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 1047 // CHECK1: omp_offload.failed.i: 1048 // CHECK1-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 1049 // CHECK1-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 1050 // CHECK1-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24 1051 // CHECK1-NEXT: [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24 1052 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 1053 // CHECK1-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32* 1054 // CHECK1-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !24 1055 // CHECK1-NEXT: [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !24 1056 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 1057 // CHECK1-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32* 1058 // CHECK1-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !24 1059 // CHECK1-NEXT: [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !24 1060 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR4]] 1061 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 1062 // CHECK1: .omp_outlined..3.exit: 1063 // CHECK1-NEXT: ret i32 0 1064 // 1065 // 1066 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 1067 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1068 // CHECK1-NEXT: entry: 1069 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1070 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1071 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1072 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1073 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1074 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1075 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1076 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1077 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1078 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1079 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 1080 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1081 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1082 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1083 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 1084 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1085 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 1086 // CHECK1-NEXT: ret void 1087 // 1088 // 1089 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 1090 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 1091 // CHECK1-NEXT: entry: 1092 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1093 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1094 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1095 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1096 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1097 // CHECK1-NEXT: [[TMP:%.*]] = alloca i16, align 2 1098 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1099 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1100 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1101 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1102 // CHECK1-NEXT: [[IT:%.*]] = alloca i16, align 2 1103 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1104 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1105 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1106 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1107 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1108 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1109 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1110 // CHECK1-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 1111 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1112 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1113 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1114 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1115 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1116 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1117 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 1118 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1119 // CHECK1: cond.true: 1120 // CHECK1-NEXT: br label [[COND_END:%.*]] 1121 // CHECK1: cond.false: 1122 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1123 // CHECK1-NEXT: br label [[COND_END]] 1124 // CHECK1: cond.end: 1125 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1126 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1127 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1128 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1129 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1130 // CHECK1: omp.inner.for.cond: 1131 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1132 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1133 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1134 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1135 // CHECK1: omp.inner.for.body: 1136 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1137 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 1138 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 1139 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 1140 // CHECK1-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 1141 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 1142 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 1143 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 1144 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 1145 // CHECK1-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 1146 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 1147 // CHECK1-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 1148 // CHECK1-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 1149 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1150 // CHECK1: omp.body.continue: 1151 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1152 // CHECK1: omp.inner.for.inc: 1153 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1154 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 1155 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 1156 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1157 // CHECK1: omp.inner.for.end: 1158 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1159 // CHECK1: omp.loop.exit: 1160 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 1161 // CHECK1-NEXT: ret void 1162 // 1163 // 1164 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 1165 // CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 1166 // CHECK1-NEXT: entry: 1167 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1168 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1169 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1170 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1171 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1172 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1173 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1174 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1175 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1176 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1177 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1178 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1179 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1180 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1181 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1182 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1183 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1184 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1185 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1186 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1187 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1188 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 1189 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1190 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1191 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1192 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1193 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1194 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1195 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1196 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1197 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1198 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 1199 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 1200 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1201 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 1202 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 1203 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 1204 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 1205 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 1206 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 1207 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 1208 // CHECK1-NEXT: ret void 1209 // 1210 // 1211 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 1212 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 1213 // CHECK1-NEXT: entry: 1214 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1215 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1216 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1217 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1218 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1219 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1220 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1221 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1222 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1223 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1224 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1225 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1226 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1227 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 1228 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1229 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1230 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1231 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1232 // CHECK1-NEXT: [[IT:%.*]] = alloca i8, align 1 1233 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1234 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1235 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1236 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1237 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1238 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1239 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1240 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1241 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1242 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1243 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1244 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 1245 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1246 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1247 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1248 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1249 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1250 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1251 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1252 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1253 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1254 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 1255 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1256 // CHECK1-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 1257 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1258 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1259 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 1260 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1261 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 1262 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 1263 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1264 // CHECK1: omp.dispatch.cond: 1265 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1266 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 1267 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1268 // CHECK1: cond.true: 1269 // CHECK1-NEXT: br label [[COND_END:%.*]] 1270 // CHECK1: cond.false: 1271 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1272 // CHECK1-NEXT: br label [[COND_END]] 1273 // CHECK1: cond.end: 1274 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 1275 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1276 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1277 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 1278 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1279 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1280 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 1281 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1282 // CHECK1: omp.dispatch.body: 1283 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1284 // CHECK1: omp.inner.for.cond: 1285 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1286 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1287 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 1288 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1289 // CHECK1: omp.inner.for.body: 1290 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1291 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 1292 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 1293 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 1294 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 1295 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 1296 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 1297 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1298 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 1299 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 1300 // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 1301 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 1302 // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 1303 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 1304 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 1305 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 1306 // CHECK1-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 1307 // CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 1308 // CHECK1-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 1309 // CHECK1-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 1310 // CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 1311 // CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 1312 // CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 1313 // CHECK1-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 1314 // CHECK1-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 1315 // CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 1316 // CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 1317 // CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 1318 // CHECK1-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 1319 // CHECK1-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 1320 // CHECK1-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 1321 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 1322 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 1323 // CHECK1-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 1324 // CHECK1-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 1325 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 1326 // CHECK1-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 1327 // CHECK1-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 1328 // CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 1329 // CHECK1-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 1330 // CHECK1-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 1331 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1332 // CHECK1: omp.body.continue: 1333 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1334 // CHECK1: omp.inner.for.inc: 1335 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1336 // CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 1337 // CHECK1-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 1338 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1339 // CHECK1: omp.inner.for.end: 1340 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1341 // CHECK1: omp.dispatch.inc: 1342 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1343 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1344 // CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 1345 // CHECK1-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 1346 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1347 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1348 // CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 1349 // CHECK1-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 1350 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1351 // CHECK1: omp.dispatch.end: 1352 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 1353 // CHECK1-NEXT: ret void 1354 // 1355 // 1356 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 1357 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1358 // CHECK1-NEXT: entry: 1359 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1360 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1361 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1362 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1363 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1364 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1365 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 1366 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1367 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1368 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1369 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1370 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 1371 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1372 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1373 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1374 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1375 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 1376 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1377 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1378 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 1379 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1380 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 1381 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 1382 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1383 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 1384 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 1385 // CHECK1-NEXT: ret i32 [[TMP8]] 1386 // 1387 // 1388 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1389 // CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1390 // CHECK1-NEXT: entry: 1391 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1392 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1393 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 1394 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1395 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1396 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1397 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1398 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1399 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1400 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1401 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1402 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1403 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1404 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1405 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1406 // CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4 1407 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1408 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1409 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 1410 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 1411 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 1412 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 1413 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1414 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 1415 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1416 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 1417 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 1418 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 1419 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 1420 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1421 // CHECK1: omp_if.then: 1422 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 1423 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 1424 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 1425 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1426 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false) 1427 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1428 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 1429 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 1430 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1431 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 1432 // CHECK1-NEXT: store double* [[A]], double** [[TMP14]], align 8 1433 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1434 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8 1435 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1436 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 1437 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 1438 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1439 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1440 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 1441 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1442 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8 1443 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1444 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 1445 // CHECK1-NEXT: store i64 2, i64* [[TMP22]], align 8 1446 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1447 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 1448 // CHECK1-NEXT: store i64 2, i64* [[TMP24]], align 8 1449 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1450 // CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8 1451 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1452 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 1453 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 1454 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1455 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1456 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 1457 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1458 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8 1459 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1460 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 1461 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 1462 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1463 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 1464 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 1465 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1466 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 1467 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1468 // CHECK1-NEXT: store i8* null, i8** [[TMP36]], align 8 1469 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1470 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1471 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1472 // CHECK1-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1473 // CHECK1-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 1474 // CHECK1-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1475 // CHECK1: omp_offload.failed: 1476 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 1477 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1478 // CHECK1: omp_offload.cont: 1479 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1480 // CHECK1: omp_if.else: 1481 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 1482 // CHECK1-NEXT: br label [[OMP_IF_END]] 1483 // CHECK1: omp_if.end: 1484 // CHECK1-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 1485 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 1486 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1487 // CHECK1-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 1488 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 1489 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 1490 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 1491 // CHECK1-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1492 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 1493 // CHECK1-NEXT: ret i32 [[ADD4]] 1494 // 1495 // 1496 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 1497 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1498 // CHECK1-NEXT: entry: 1499 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1500 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1501 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1502 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 1503 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1504 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1505 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1506 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1507 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1508 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1509 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1510 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1511 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1512 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1513 // CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1 1514 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1515 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1516 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1517 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1518 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1519 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1520 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1521 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1522 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 1523 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1524 // CHECK1-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 1525 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1526 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1527 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 1528 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1529 // CHECK1: omp_if.then: 1530 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1531 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1532 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1533 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1534 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 1535 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 1536 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1537 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8 1538 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1539 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1540 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1541 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1542 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 1543 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 1544 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1545 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8 1546 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1547 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 1548 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 1549 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1550 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 1551 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 1552 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1553 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 1554 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1555 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 1556 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 1557 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1558 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 1559 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 1560 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1561 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8 1562 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1563 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1564 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1565 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1566 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1567 // CHECK1: omp_offload.failed: 1568 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 1569 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1570 // CHECK1: omp_offload.cont: 1571 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1572 // CHECK1: omp_if.else: 1573 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 1574 // CHECK1-NEXT: br label [[OMP_IF_END]] 1575 // CHECK1: omp_if.end: 1576 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 1577 // CHECK1-NEXT: ret i32 [[TMP31]] 1578 // 1579 // 1580 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1581 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1582 // CHECK1-NEXT: entry: 1583 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1584 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1585 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1586 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1587 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1588 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1589 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1590 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1591 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1592 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1593 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1594 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1595 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1596 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1597 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1598 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1599 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1600 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1601 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1602 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1603 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1604 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1605 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1606 // CHECK1: omp_if.then: 1607 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1608 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 1609 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 1610 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1611 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1612 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1613 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1614 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 1615 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1616 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 1617 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 1618 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1619 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1620 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1621 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1622 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 1623 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1624 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 1625 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 1626 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1627 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 1628 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 1629 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1630 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 1631 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1632 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1633 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1634 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 1635 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1636 // CHECK1: omp_offload.failed: 1637 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1638 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1639 // CHECK1: omp_offload.cont: 1640 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1641 // CHECK1: omp_if.else: 1642 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1643 // CHECK1-NEXT: br label [[OMP_IF_END]] 1644 // CHECK1: omp_if.end: 1645 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 1646 // CHECK1-NEXT: ret i32 [[TMP24]] 1647 // 1648 // 1649 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 1650 // CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1651 // CHECK1-NEXT: entry: 1652 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1653 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1654 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1655 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1656 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1657 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1658 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1659 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1660 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1661 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1662 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1663 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1664 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1665 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1666 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1667 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1668 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1669 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1670 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 1671 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 1672 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 1673 // CHECK1-NEXT: ret void 1674 // 1675 // 1676 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 1677 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 1678 // CHECK1-NEXT: entry: 1679 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1680 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1681 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1682 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1683 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1684 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1685 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1686 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1687 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 1688 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1689 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1690 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1691 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1692 // CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8 1693 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1694 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1695 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1696 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1697 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1698 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1699 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1700 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1701 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1702 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1703 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1704 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1705 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1706 // CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 1707 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1708 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1709 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1710 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1711 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1712 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1713 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 1714 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1715 // CHECK1: cond.true: 1716 // CHECK1-NEXT: br label [[COND_END:%.*]] 1717 // CHECK1: cond.false: 1718 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1719 // CHECK1-NEXT: br label [[COND_END]] 1720 // CHECK1: cond.end: 1721 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1722 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1723 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1724 // CHECK1-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 1725 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1726 // CHECK1: omp.inner.for.cond: 1727 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1728 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1729 // CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 1730 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1731 // CHECK1: omp.inner.for.body: 1732 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1733 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 1734 // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 1735 // CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 1736 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 1737 // CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 1738 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 1739 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1740 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 1741 // CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1742 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 1743 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 1744 // CHECK1-NEXT: store double [[INC]], double* [[A5]], align 8 1745 // CHECK1-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 1746 // CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 1747 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 1748 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1749 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 1750 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1751 // CHECK1: omp.body.continue: 1752 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1753 // CHECK1: omp.inner.for.inc: 1754 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1755 // CHECK1-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 1756 // CHECK1-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 1757 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1758 // CHECK1: omp.inner.for.end: 1759 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1760 // CHECK1: omp.loop.exit: 1761 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1762 // CHECK1-NEXT: ret void 1763 // 1764 // 1765 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 1766 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1767 // CHECK1-NEXT: entry: 1768 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1769 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1770 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1771 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1772 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1773 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1774 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1775 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1776 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1777 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1778 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1779 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1780 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1781 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1782 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1783 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1784 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1785 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 1786 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1787 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1788 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1789 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 1790 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1791 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 1792 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1793 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 1794 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1795 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 1796 // CHECK1-NEXT: ret void 1797 // 1798 // 1799 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 1800 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1801 // CHECK1-NEXT: entry: 1802 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1803 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1804 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1805 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1806 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1807 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1808 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1809 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1810 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1811 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1812 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1813 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1814 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1815 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1816 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1817 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1818 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1819 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1820 // CHECK1-NEXT: ret void 1821 // 1822 // 1823 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 1824 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1825 // CHECK1-NEXT: entry: 1826 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1827 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1828 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1829 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1830 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1831 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1832 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1833 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1834 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1835 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1836 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1837 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1838 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1839 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 1840 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1841 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1842 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1843 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 1844 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1845 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 1846 // CHECK1-NEXT: ret void 1847 // 1848 // 1849 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 1850 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1851 // CHECK1-NEXT: entry: 1852 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1853 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1854 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1855 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1856 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1857 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1858 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 1859 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1860 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1861 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1862 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1863 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 1864 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1865 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1866 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1867 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1868 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1869 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1870 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1871 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1872 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1873 // CHECK1-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 1874 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1875 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1876 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1877 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1878 // CHECK1-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1879 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1880 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 1881 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1882 // CHECK1: cond.true: 1883 // CHECK1-NEXT: br label [[COND_END:%.*]] 1884 // CHECK1: cond.false: 1885 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1886 // CHECK1-NEXT: br label [[COND_END]] 1887 // CHECK1: cond.end: 1888 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1889 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1890 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1891 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 1892 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1893 // CHECK1: omp.inner.for.cond: 1894 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1895 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1896 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 1897 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1898 // CHECK1: omp.inner.for.body: 1899 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1900 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 1901 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 1902 // CHECK1-NEXT: store i64 [[ADD]], i64* [[I]], align 8 1903 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 1904 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 1905 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 1906 // CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 1907 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 1908 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 1909 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 1910 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 1911 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1912 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1913 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 1914 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 1915 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1916 // CHECK1: omp.body.continue: 1917 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1918 // CHECK1: omp.inner.for.inc: 1919 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1920 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 1921 // CHECK1-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 1922 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1923 // CHECK1: omp.inner.for.end: 1924 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1925 // CHECK1: omp.loop.exit: 1926 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1927 // CHECK1-NEXT: ret void 1928 // 1929 // 1930 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1931 // CHECK1-SAME: () #[[ATTR6]] { 1932 // CHECK1-NEXT: entry: 1933 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1934 // CHECK1-NEXT: ret void 1935 // 1936 // 1937 // CHECK2-LABEL: define {{[^@]+}}@_Z7get_valv 1938 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 1939 // CHECK2-NEXT: entry: 1940 // CHECK2-NEXT: ret i64 0 1941 // 1942 // 1943 // CHECK2-LABEL: define {{[^@]+}}@_Z3fooi 1944 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1945 // CHECK2-NEXT: entry: 1946 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1947 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 1948 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 1949 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x float], align 4 1950 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1951 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1952 // CHECK2-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 1953 // CHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 1954 // CHECK2-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 1955 // CHECK2-NEXT: [[K:%.*]] = alloca i64, align 8 1956 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1957 // CHECK2-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 1958 // CHECK2-NEXT: [[LIN:%.*]] = alloca i32, align 4 1959 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1960 // CHECK2-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 1961 // CHECK2-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8 1962 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1963 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1964 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1965 // CHECK2-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 1966 // CHECK2-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8 1967 // CHECK2-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8 1968 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 1969 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 1970 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 1971 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1972 // CHECK2-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8 1973 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1974 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8 1975 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8 1976 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8 1977 // CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 1978 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 1979 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1980 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 1981 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 1982 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1983 // CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1984 // CHECK2-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 1985 // CHECK2-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 1986 // CHECK2-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 1987 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1988 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1989 // CHECK2-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 1990 // CHECK2-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 1991 // CHECK2-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 1992 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 1993 // CHECK2-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 1994 // CHECK2-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 1995 // CHECK2-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1996 // CHECK2: omp_offload.failed: 1997 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 1998 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1999 // CHECK2: omp_offload.cont: 2000 // CHECK2-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 2001 // CHECK2-NEXT: store i64 [[CALL]], i64* [[K]], align 8 2002 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 2003 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2004 // CHECK2-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4 2005 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8 2006 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[K]], align 8 2007 // CHECK2-NEXT: store i64 [[TMP11]], i64* [[K_CASTED]], align 8 2008 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8 2009 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR4]] 2010 // CHECK2-NEXT: store i32 12, i32* [[LIN]], align 4 2011 // CHECK2-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 2012 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2013 // CHECK2-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 2014 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2015 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4 2016 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 2017 // CHECK2-NEXT: store i32 [[TMP15]], i32* [[CONV3]], align 4 2018 // CHECK2-NEXT: [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 2019 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 2020 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32* 2021 // CHECK2-NEXT: store i32 [[TMP17]], i32* [[CONV5]], align 4 2022 // CHECK2-NEXT: [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8 2023 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2024 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 2025 // CHECK2-NEXT: store i64 [[TMP14]], i64* [[TMP20]], align 8 2026 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2027 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 2028 // CHECK2-NEXT: store i64 [[TMP14]], i64* [[TMP22]], align 8 2029 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2030 // CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8 2031 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2032 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 2033 // CHECK2-NEXT: store i64 [[TMP16]], i64* [[TMP25]], align 8 2034 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2035 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 2036 // CHECK2-NEXT: store i64 [[TMP16]], i64* [[TMP27]], align 8 2037 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2038 // CHECK2-NEXT: store i8* null, i8** [[TMP28]], align 8 2039 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2040 // CHECK2-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 2041 // CHECK2-NEXT: store i64 [[TMP18]], i64* [[TMP30]], align 8 2042 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2043 // CHECK2-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 2044 // CHECK2-NEXT: store i64 [[TMP18]], i64* [[TMP32]], align 8 2045 // CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2046 // CHECK2-NEXT: store i8* null, i8** [[TMP33]], align 8 2047 // CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2048 // CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2049 // CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 2050 // CHECK2-NEXT: [[TMP37:%.*]] = load i16, i16* [[AA]], align 2 2051 // CHECK2-NEXT: store i16 [[TMP37]], i16* [[TMP36]], align 4 2052 // CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 2053 // CHECK2-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4 2054 // CHECK2-NEXT: store i32 [[TMP39]], i32* [[TMP38]], align 4 2055 // CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 2056 // CHECK2-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 2057 // CHECK2-NEXT: store i32 [[TMP41]], i32* [[TMP40]], align 4 2058 // CHECK2-NEXT: [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 2059 // CHECK2-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates* 2060 // CHECK2-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0 2061 // CHECK2-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0 2062 // CHECK2-NEXT: [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8 2063 // CHECK2-NEXT: [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 2064 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false) 2065 // CHECK2-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1 2066 // CHECK2-NEXT: [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon* 2067 // CHECK2-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0 2068 // CHECK2-NEXT: [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8* 2069 // CHECK2-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8* 2070 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false) 2071 // CHECK2-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1 2072 // CHECK2-NEXT: [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8* 2073 // CHECK2-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8* 2074 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false) 2075 // CHECK2-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2 2076 // CHECK2-NEXT: [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8* 2077 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 2078 // CHECK2-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3 2079 // CHECK2-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 2080 // CHECK2-NEXT: store i16 [[TMP59]], i16* [[TMP58]], align 8 2081 // CHECK2-NEXT: [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]]) 2082 // CHECK2-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4 2083 // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32* 2084 // CHECK2-NEXT: store i32 [[TMP61]], i32* [[CONV7]], align 4 2085 // CHECK2-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8 2086 // CHECK2-NEXT: [[TMP63:%.*]] = load i16, i16* [[AA]], align 2 2087 // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16* 2088 // CHECK2-NEXT: store i16 [[TMP63]], i16* [[CONV9]], align 2 2089 // CHECK2-NEXT: [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8 2090 // CHECK2-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4 2091 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10 2092 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2093 // CHECK2: omp_if.then: 2094 // CHECK2-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 2095 // CHECK2-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64* 2096 // CHECK2-NEXT: store i64 [[TMP62]], i64* [[TMP67]], align 8 2097 // CHECK2-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 2098 // CHECK2-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* 2099 // CHECK2-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8 2100 // CHECK2-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 2101 // CHECK2-NEXT: store i8* null, i8** [[TMP70]], align 8 2102 // CHECK2-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 2103 // CHECK2-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* 2104 // CHECK2-NEXT: store i64 [[TMP64]], i64* [[TMP72]], align 8 2105 // CHECK2-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 2106 // CHECK2-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* 2107 // CHECK2-NEXT: store i64 [[TMP64]], i64* [[TMP74]], align 8 2108 // CHECK2-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 2109 // CHECK2-NEXT: store i8* null, i8** [[TMP75]], align 8 2110 // CHECK2-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 2111 // CHECK2-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 2112 // CHECK2-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2113 // CHECK2-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0 2114 // CHECK2-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]] 2115 // CHECK2: omp_offload.failed13: 2116 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 2117 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT14]] 2118 // CHECK2: omp_offload.cont14: 2119 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 2120 // CHECK2: omp_if.else: 2121 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 2122 // CHECK2-NEXT: br label [[OMP_IF_END]] 2123 // CHECK2: omp_if.end: 2124 // CHECK2-NEXT: [[TMP80:%.*]] = load i32, i32* [[A]], align 4 2125 // CHECK2-NEXT: store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4 2126 // CHECK2-NEXT: [[TMP81:%.*]] = load i32, i32* [[A]], align 4 2127 // CHECK2-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32* 2128 // CHECK2-NEXT: store i32 [[TMP81]], i32* [[CONV16]], align 4 2129 // CHECK2-NEXT: [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8 2130 // CHECK2-NEXT: [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2131 // CHECK2-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 2132 // CHECK2-NEXT: store i32 [[TMP83]], i32* [[CONV17]], align 4 2133 // CHECK2-NEXT: [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 2134 // CHECK2-NEXT: [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4 2135 // CHECK2-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20 2136 // CHECK2-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 2137 // CHECK2: omp_if.then19: 2138 // CHECK2-NEXT: [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4 2139 // CHECK2-NEXT: [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]] 2140 // CHECK2-NEXT: [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8 2141 // CHECK2-NEXT: [[TMP89:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2142 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP89]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i64 80, i1 false) 2143 // CHECK2-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 2144 // CHECK2-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i64* 2145 // CHECK2-NEXT: store i64 [[TMP82]], i64* [[TMP91]], align 8 2146 // CHECK2-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 2147 // CHECK2-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to i64* 2148 // CHECK2-NEXT: store i64 [[TMP82]], i64* [[TMP93]], align 8 2149 // CHECK2-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 2150 // CHECK2-NEXT: store i8* null, i8** [[TMP94]], align 8 2151 // CHECK2-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 2152 // CHECK2-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 2153 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8 2154 // CHECK2-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 2155 // CHECK2-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]** 2156 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8 2157 // CHECK2-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 2158 // CHECK2-NEXT: store i8* null, i8** [[TMP99]], align 8 2159 // CHECK2-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 2160 // CHECK2-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64* 2161 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP101]], align 8 2162 // CHECK2-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 2163 // CHECK2-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i64* 2164 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP103]], align 8 2165 // CHECK2-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 2166 // CHECK2-NEXT: store i8* null, i8** [[TMP104]], align 8 2167 // CHECK2-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 2168 // CHECK2-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** 2169 // CHECK2-NEXT: store float* [[VLA]], float** [[TMP106]], align 8 2170 // CHECK2-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 2171 // CHECK2-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** 2172 // CHECK2-NEXT: store float* [[VLA]], float** [[TMP108]], align 8 2173 // CHECK2-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 2174 // CHECK2-NEXT: store i64 [[TMP86]], i64* [[TMP109]], align 8 2175 // CHECK2-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 2176 // CHECK2-NEXT: store i8* null, i8** [[TMP110]], align 8 2177 // CHECK2-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 2178 // CHECK2-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** 2179 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 8 2180 // CHECK2-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 2181 // CHECK2-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** 2182 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8 2183 // CHECK2-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 2184 // CHECK2-NEXT: store i8* null, i8** [[TMP115]], align 8 2185 // CHECK2-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 2186 // CHECK2-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64* 2187 // CHECK2-NEXT: store i64 5, i64* [[TMP117]], align 8 2188 // CHECK2-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 2189 // CHECK2-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i64* 2190 // CHECK2-NEXT: store i64 5, i64* [[TMP119]], align 8 2191 // CHECK2-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5 2192 // CHECK2-NEXT: store i8* null, i8** [[TMP120]], align 8 2193 // CHECK2-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 2194 // CHECK2-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64* 2195 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP122]], align 8 2196 // CHECK2-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 2197 // CHECK2-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i64* 2198 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP124]], align 8 2199 // CHECK2-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6 2200 // CHECK2-NEXT: store i8* null, i8** [[TMP125]], align 8 2201 // CHECK2-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 2202 // CHECK2-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** 2203 // CHECK2-NEXT: store double* [[VLA1]], double** [[TMP127]], align 8 2204 // CHECK2-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 2205 // CHECK2-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to double** 2206 // CHECK2-NEXT: store double* [[VLA1]], double** [[TMP129]], align 8 2207 // CHECK2-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 2208 // CHECK2-NEXT: store i64 [[TMP88]], i64* [[TMP130]], align 8 2209 // CHECK2-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7 2210 // CHECK2-NEXT: store i8* null, i8** [[TMP131]], align 8 2211 // CHECK2-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 2212 // CHECK2-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT** 2213 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 8 2214 // CHECK2-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 2215 // CHECK2-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to %struct.TT** 2216 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP135]], align 8 2217 // CHECK2-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8 2218 // CHECK2-NEXT: store i8* null, i8** [[TMP136]], align 8 2219 // CHECK2-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9 2220 // CHECK2-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i64* 2221 // CHECK2-NEXT: store i64 [[TMP84]], i64* [[TMP138]], align 8 2222 // CHECK2-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9 2223 // CHECK2-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to i64* 2224 // CHECK2-NEXT: store i64 [[TMP84]], i64* [[TMP140]], align 8 2225 // CHECK2-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9 2226 // CHECK2-NEXT: store i8* null, i8** [[TMP141]], align 8 2227 // CHECK2-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 2228 // CHECK2-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 2229 // CHECK2-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2230 // CHECK2-NEXT: [[TMP145:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP142]], i8** [[TMP143]], i64* [[TMP144]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2231 // CHECK2-NEXT: [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 0 2232 // CHECK2-NEXT: br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 2233 // CHECK2: omp_offload.failed23: 2234 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 2235 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT24]] 2236 // CHECK2: omp_offload.cont24: 2237 // CHECK2-NEXT: br label [[OMP_IF_END26:%.*]] 2238 // CHECK2: omp_if.else25: 2239 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 2240 // CHECK2-NEXT: br label [[OMP_IF_END26]] 2241 // CHECK2: omp_if.end26: 2242 // CHECK2-NEXT: [[TMP147:%.*]] = load i32, i32* [[A]], align 4 2243 // CHECK2-NEXT: [[TMP148:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 2244 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP148]]) 2245 // CHECK2-NEXT: ret i32 [[TMP147]] 2246 // 2247 // 2248 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 2249 // CHECK2-SAME: () #[[ATTR2:[0-9]+]] { 2250 // CHECK2-NEXT: entry: 2251 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2252 // CHECK2-NEXT: ret void 2253 // 2254 // 2255 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 2256 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 2257 // CHECK2-NEXT: entry: 2258 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2259 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2260 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2261 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 2262 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2263 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2264 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2265 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2266 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 2267 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2268 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2269 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2270 // CHECK2-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 2271 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2272 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2273 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2274 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2275 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2276 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2277 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 2278 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2279 // CHECK2: cond.true: 2280 // CHECK2-NEXT: br label [[COND_END:%.*]] 2281 // CHECK2: cond.false: 2282 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2283 // CHECK2-NEXT: br label [[COND_END]] 2284 // CHECK2: cond.end: 2285 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2286 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2287 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2288 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2289 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2290 // CHECK2: omp.inner.for.cond: 2291 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2292 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2293 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2294 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2295 // CHECK2: omp.inner.for.body: 2296 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2297 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 2298 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 2299 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2300 // CHECK2-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 2301 // CHECK2-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 2302 // CHECK2-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 2303 // CHECK2: .cancel.exit: 2304 // CHECK2-NEXT: br label [[CANCEL_EXIT:%.*]] 2305 // CHECK2: .cancel.continue: 2306 // CHECK2-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 2307 // CHECK2-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 2308 // CHECK2-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 2309 // CHECK2: .cancel.exit2: 2310 // CHECK2-NEXT: br label [[CANCEL_EXIT]] 2311 // CHECK2: .cancel.continue3: 2312 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2313 // CHECK2: omp.body.continue: 2314 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2315 // CHECK2: omp.inner.for.inc: 2316 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2317 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 2318 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 2319 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 2320 // CHECK2: omp.inner.for.end: 2321 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2322 // CHECK2: omp.loop.exit: 2323 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2324 // CHECK2-NEXT: br label [[CANCEL_CONT:%.*]] 2325 // CHECK2: cancel.cont: 2326 // CHECK2-NEXT: ret void 2327 // CHECK2: cancel.exit: 2328 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2329 // CHECK2-NEXT: br label [[CANCEL_CONT]] 2330 // 2331 // 2332 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 2333 // CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 2334 // CHECK2-NEXT: entry: 2335 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2336 // CHECK2-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 2337 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2338 // CHECK2-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 2339 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2340 // CHECK2-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 2341 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2342 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 2343 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2344 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 2345 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 2346 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 2347 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 2348 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 2349 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 2350 // CHECK2-NEXT: ret void 2351 // 2352 // 2353 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 2354 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 2355 // CHECK2-NEXT: entry: 2356 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2357 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2358 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2359 // CHECK2-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 2360 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2361 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 2362 // CHECK2-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 2363 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2364 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2365 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2366 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2367 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 2368 // CHECK2-NEXT: [[K1:%.*]] = alloca i64, align 8 2369 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2370 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2371 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2372 // CHECK2-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 2373 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2374 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8 2375 // CHECK2-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8 2376 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2377 // CHECK2-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 2378 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2379 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2380 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2381 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2382 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 2383 // CHECK2-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1) 2384 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2385 // CHECK2: omp.dispatch.cond: 2386 // CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 2387 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 2388 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2389 // CHECK2: omp.dispatch.body: 2390 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2391 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2392 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2393 // CHECK2: omp.inner.for.cond: 2394 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2395 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 2396 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2397 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2398 // CHECK2: omp.inner.for.body: 2399 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2400 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2401 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 2402 // CHECK2-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12 2403 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12 2404 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2405 // CHECK2-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 2406 // CHECK2-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 2407 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] 2408 // CHECK2-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12 2409 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12 2410 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 2411 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12 2412 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2413 // CHECK2: omp.body.continue: 2414 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2415 // CHECK2: omp.inner.for.inc: 2416 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2417 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 2418 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2419 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 2420 // CHECK2: omp.inner.for.end: 2421 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2422 // CHECK2: omp.dispatch.inc: 2423 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 2424 // CHECK2: omp.dispatch.end: 2425 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2426 // CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 2427 // CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 2428 // CHECK2: .omp.linear.pu: 2429 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[K1]], align 8 2430 // CHECK2-NEXT: store i64 [[TMP14]], i64* [[K_ADDR]], align 8 2431 // CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 2432 // CHECK2: .omp.linear.pu.done: 2433 // CHECK2-NEXT: ret void 2434 // 2435 // 2436 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 2437 // CHECK2-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 2438 // CHECK2-NEXT: entry: 2439 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2440 // CHECK2-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 2441 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2442 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2443 // CHECK2-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 2444 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2445 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2446 // CHECK2-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 2447 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2448 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2449 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 2450 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2451 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2452 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2453 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 2454 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2455 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 2456 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 2457 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 2458 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 2459 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 2460 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2461 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 2462 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 2463 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 2464 // CHECK2-NEXT: ret void 2465 // 2466 // 2467 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 2468 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 2469 // CHECK2-NEXT: entry: 2470 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2471 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2472 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2473 // CHECK2-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 2474 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2475 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2476 // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 2477 // CHECK2-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 2478 // CHECK2-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 2479 // CHECK2-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 2480 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2481 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2482 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2483 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2484 // CHECK2-NEXT: [[IT:%.*]] = alloca i64, align 8 2485 // CHECK2-NEXT: [[LIN4:%.*]] = alloca i32, align 4 2486 // CHECK2-NEXT: [[A5:%.*]] = alloca i32, align 4 2487 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2488 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2489 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2490 // CHECK2-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 2491 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2492 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2493 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 2494 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2495 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 2496 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 2497 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 2498 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 2499 // CHECK2-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 2500 // CHECK2-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 2501 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2502 // CHECK2-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 2503 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2504 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2505 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2506 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2507 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 2508 // CHECK2-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 2509 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2510 // CHECK2-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 2511 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2512 // CHECK2: cond.true: 2513 // CHECK2-NEXT: br label [[COND_END:%.*]] 2514 // CHECK2: cond.false: 2515 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2516 // CHECK2-NEXT: br label [[COND_END]] 2517 // CHECK2: cond.end: 2518 // CHECK2-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2519 // CHECK2-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 2520 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2521 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 2522 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2523 // CHECK2: omp.inner.for.cond: 2524 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2525 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2526 // CHECK2-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 2527 // CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2528 // CHECK2: omp.inner.for.body: 2529 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2530 // CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 2531 // CHECK2-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 2532 // CHECK2-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 2533 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 2534 // CHECK2-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 2535 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2536 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 2537 // CHECK2-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 2538 // CHECK2-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 2539 // CHECK2-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 2540 // CHECK2-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 2541 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 2542 // CHECK2-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 2543 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2544 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 2545 // CHECK2-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 2546 // CHECK2-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 2547 // CHECK2-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 2548 // CHECK2-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 2549 // CHECK2-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 2550 // CHECK2-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 2551 // CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 2552 // CHECK2-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 2553 // CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 2554 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2555 // CHECK2: omp.body.continue: 2556 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2557 // CHECK2: omp.inner.for.inc: 2558 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2559 // CHECK2-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 2560 // CHECK2-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 2561 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 2562 // CHECK2: omp.inner.for.end: 2563 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2564 // CHECK2: omp.loop.exit: 2565 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 2566 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2567 // CHECK2-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 2568 // CHECK2-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 2569 // CHECK2: .omp.linear.pu: 2570 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 2571 // CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 2572 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 2573 // CHECK2-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 2574 // CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 2575 // CHECK2: .omp.linear.pu.done: 2576 // CHECK2-NEXT: ret void 2577 // 2578 // 2579 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. 2580 // CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 2581 // CHECK2-NEXT: entry: 2582 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 2583 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 2584 // CHECK2-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 2585 // CHECK2-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 2586 // CHECK2-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 2587 // CHECK2-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 2588 // CHECK2-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 2589 // CHECK2-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 2590 // CHECK2-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 2591 // CHECK2-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 2592 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 2593 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 2594 // CHECK2-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 2595 // CHECK2-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 2596 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 2597 // CHECK2-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 2598 // CHECK2-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 2599 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 2600 // CHECK2-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 2601 // CHECK2-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 2602 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 2603 // CHECK2-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 2604 // CHECK2-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 2605 // CHECK2-NEXT: ret void 2606 // 2607 // 2608 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. 2609 // CHECK2-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 2610 // CHECK2-NEXT: entry: 2611 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 2612 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 2613 // CHECK2-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 2614 // CHECK2-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 2615 // CHECK2-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 2616 // CHECK2-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 2617 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 2618 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 2619 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 2620 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 2621 // CHECK2-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 2622 // CHECK2-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8 2623 // CHECK2-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8 2624 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 2625 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 2626 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 2627 // CHECK2-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 2628 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 2629 // CHECK2-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 2630 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 2631 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 2632 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 2633 // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 2634 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 2635 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 2636 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 2637 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 2638 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 2639 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 2640 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 2641 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 2642 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 2643 // CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24 2644 // CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 2645 // CHECK2-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 2646 // CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24 2647 // CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 2648 // CHECK2-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 2649 // CHECK2-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 2650 // CHECK2-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 2651 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 2652 // CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 2653 // CHECK2-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 2654 // CHECK2-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 2655 // CHECK2-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 2656 // CHECK2-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24 2657 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 2658 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 2659 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 2660 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 2661 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 2662 // CHECK2-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 2663 // CHECK2-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 2664 // CHECK2-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 2665 // CHECK2: omp_offload.failed.i: 2666 // CHECK2-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 2667 // CHECK2-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 2668 // CHECK2-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24 2669 // CHECK2-NEXT: [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24 2670 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 2671 // CHECK2-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32* 2672 // CHECK2-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !24 2673 // CHECK2-NEXT: [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !24 2674 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 2675 // CHECK2-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32* 2676 // CHECK2-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !24 2677 // CHECK2-NEXT: [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !24 2678 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR4]] 2679 // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 2680 // CHECK2: .omp_outlined..3.exit: 2681 // CHECK2-NEXT: ret i32 0 2682 // 2683 // 2684 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 2685 // CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 2686 // CHECK2-NEXT: entry: 2687 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2688 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2689 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2690 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2691 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2692 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2693 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2694 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2695 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 2696 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2697 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 2698 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 2699 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 2700 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2701 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 2702 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2703 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 2704 // CHECK2-NEXT: ret void 2705 // 2706 // 2707 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 2708 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 2709 // CHECK2-NEXT: entry: 2710 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2711 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2712 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2713 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2714 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2715 // CHECK2-NEXT: [[TMP:%.*]] = alloca i16, align 2 2716 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2717 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2718 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2719 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2720 // CHECK2-NEXT: [[IT:%.*]] = alloca i16, align 2 2721 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2722 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2723 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2724 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2725 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2726 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2727 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2728 // CHECK2-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 2729 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2730 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2731 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2732 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2733 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2734 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2735 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 2736 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2737 // CHECK2: cond.true: 2738 // CHECK2-NEXT: br label [[COND_END:%.*]] 2739 // CHECK2: cond.false: 2740 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2741 // CHECK2-NEXT: br label [[COND_END]] 2742 // CHECK2: cond.end: 2743 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2744 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2745 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2746 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2747 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2748 // CHECK2: omp.inner.for.cond: 2749 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2750 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2751 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2752 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2753 // CHECK2: omp.inner.for.body: 2754 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2755 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 2756 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 2757 // CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 2758 // CHECK2-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 2759 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 2760 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 2761 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 2762 // CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 2763 // CHECK2-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 2764 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 2765 // CHECK2-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 2766 // CHECK2-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 2767 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2768 // CHECK2: omp.body.continue: 2769 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2770 // CHECK2: omp.inner.for.inc: 2771 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2772 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 2773 // CHECK2-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 2774 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 2775 // CHECK2: omp.inner.for.end: 2776 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2777 // CHECK2: omp.loop.exit: 2778 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2779 // CHECK2-NEXT: ret void 2780 // 2781 // 2782 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 2783 // CHECK2-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 2784 // CHECK2-NEXT: entry: 2785 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2786 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 2787 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2788 // CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 2789 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 2790 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2791 // CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 2792 // CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 2793 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 2794 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2795 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2796 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 2797 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2798 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 2799 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2800 // CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 2801 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 2802 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2803 // CHECK2-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 2804 // CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 2805 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 2806 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2807 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2808 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 2809 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2810 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 2811 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 2812 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2813 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 2814 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 2815 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 2816 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 2817 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 2818 // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2819 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 2820 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 2821 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 2822 // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 2823 // CHECK2-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 2824 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 2825 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 2826 // CHECK2-NEXT: ret void 2827 // 2828 // 2829 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 2830 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 2831 // CHECK2-NEXT: entry: 2832 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2833 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2834 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2835 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 2836 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2837 // CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 2838 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 2839 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2840 // CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 2841 // CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 2842 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 2843 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2844 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2845 // CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1 2846 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2847 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2848 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2849 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2850 // CHECK2-NEXT: [[IT:%.*]] = alloca i8, align 1 2851 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2852 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2853 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2854 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 2855 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2856 // CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 2857 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 2858 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2859 // CHECK2-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 2860 // CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 2861 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 2862 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2863 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2864 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 2865 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2866 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 2867 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 2868 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2869 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 2870 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 2871 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 2872 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 2873 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2874 // CHECK2-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 2875 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2876 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2877 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 2878 // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2879 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 2880 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 2881 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2882 // CHECK2: omp.dispatch.cond: 2883 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2884 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 2885 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2886 // CHECK2: cond.true: 2887 // CHECK2-NEXT: br label [[COND_END:%.*]] 2888 // CHECK2: cond.false: 2889 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2890 // CHECK2-NEXT: br label [[COND_END]] 2891 // CHECK2: cond.end: 2892 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 2893 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2894 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2895 // CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 2896 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2897 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2898 // CHECK2-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 2899 // CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2900 // CHECK2: omp.dispatch.body: 2901 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2902 // CHECK2: omp.inner.for.cond: 2903 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2904 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2905 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 2906 // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2907 // CHECK2: omp.inner.for.body: 2908 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2909 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 2910 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 2911 // CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 2912 // CHECK2-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 2913 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 2914 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 2915 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 2916 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 2917 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 2918 // CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 2919 // CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 2920 // CHECK2-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 2921 // CHECK2-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 2922 // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 2923 // CHECK2-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 2924 // CHECK2-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 2925 // CHECK2-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 2926 // CHECK2-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 2927 // CHECK2-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 2928 // CHECK2-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 2929 // CHECK2-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 2930 // CHECK2-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 2931 // CHECK2-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 2932 // CHECK2-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 2933 // CHECK2-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 2934 // CHECK2-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 2935 // CHECK2-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 2936 // CHECK2-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 2937 // CHECK2-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 2938 // CHECK2-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 2939 // CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 2940 // CHECK2-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 2941 // CHECK2-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 2942 // CHECK2-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 2943 // CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 2944 // CHECK2-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 2945 // CHECK2-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 2946 // CHECK2-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 2947 // CHECK2-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 2948 // CHECK2-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 2949 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2950 // CHECK2: omp.body.continue: 2951 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2952 // CHECK2: omp.inner.for.inc: 2953 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2954 // CHECK2-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 2955 // CHECK2-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 2956 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 2957 // CHECK2: omp.inner.for.end: 2958 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2959 // CHECK2: omp.dispatch.inc: 2960 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2961 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2962 // CHECK2-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 2963 // CHECK2-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 2964 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2965 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2966 // CHECK2-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 2967 // CHECK2-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 2968 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 2969 // CHECK2: omp.dispatch.end: 2970 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 2971 // CHECK2-NEXT: ret void 2972 // 2973 // 2974 // CHECK2-LABEL: define {{[^@]+}}@_Z3bari 2975 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 2976 // CHECK2-NEXT: entry: 2977 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2978 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 2979 // CHECK2-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 2980 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2981 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 2982 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2983 // CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 2984 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2985 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2986 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2987 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2988 // CHECK2-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 2989 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2990 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2991 // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2992 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2993 // CHECK2-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 2994 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2995 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2996 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2997 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2998 // CHECK2-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 2999 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 3000 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 3001 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 3002 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 3003 // CHECK2-NEXT: ret i32 [[TMP8]] 3004 // 3005 // 3006 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3007 // CHECK2-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3008 // CHECK2-NEXT: entry: 3009 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3010 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3011 // CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4 3012 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3013 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3014 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3015 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 3016 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 3017 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 3018 // CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 3019 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3020 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3021 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3022 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3023 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3024 // CHECK2-NEXT: store i32 [[ADD]], i32* [[B]], align 4 3025 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3026 // CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 3027 // CHECK2-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 3028 // CHECK2-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 3029 // CHECK2-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 3030 // CHECK2-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 3031 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 3032 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 3033 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 3034 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 3035 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 3036 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 3037 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 3038 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3039 // CHECK2: omp_if.then: 3040 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3041 // CHECK2-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 3042 // CHECK2-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 3043 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 3044 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false) 3045 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3046 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 3047 // CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 3048 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3049 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 3050 // CHECK2-NEXT: store double* [[A]], double** [[TMP14]], align 8 3051 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3052 // CHECK2-NEXT: store i8* null, i8** [[TMP15]], align 8 3053 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3054 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 3055 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 3056 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3057 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 3058 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 3059 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3060 // CHECK2-NEXT: store i8* null, i8** [[TMP20]], align 8 3061 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3062 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 3063 // CHECK2-NEXT: store i64 2, i64* [[TMP22]], align 8 3064 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3065 // CHECK2-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 3066 // CHECK2-NEXT: store i64 2, i64* [[TMP24]], align 8 3067 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3068 // CHECK2-NEXT: store i8* null, i8** [[TMP25]], align 8 3069 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3070 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 3071 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 3072 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3073 // CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 3074 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 3075 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 3076 // CHECK2-NEXT: store i8* null, i8** [[TMP30]], align 8 3077 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3078 // CHECK2-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 3079 // CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 3080 // CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3081 // CHECK2-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 3082 // CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 3083 // CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3084 // CHECK2-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 3085 // CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 3086 // CHECK2-NEXT: store i8* null, i8** [[TMP36]], align 8 3087 // CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3088 // CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3089 // CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3090 // CHECK2-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3091 // CHECK2-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 3092 // CHECK2-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3093 // CHECK2: omp_offload.failed: 3094 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 3095 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 3096 // CHECK2: omp_offload.cont: 3097 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 3098 // CHECK2: omp_if.else: 3099 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 3100 // CHECK2-NEXT: br label [[OMP_IF_END]] 3101 // CHECK2: omp_if.end: 3102 // CHECK2-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 3103 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 3104 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 3105 // CHECK2-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 3106 // CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 3107 // CHECK2-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 3108 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 3109 // CHECK2-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 3110 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 3111 // CHECK2-NEXT: ret i32 [[ADD4]] 3112 // 3113 // 3114 // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici 3115 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 3116 // CHECK2-NEXT: entry: 3117 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3118 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 3119 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 3120 // CHECK2-NEXT: [[AAA:%.*]] = alloca i8, align 1 3121 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3122 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3123 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3124 // CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 3125 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 3126 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 3127 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 3128 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3129 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 3130 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 3131 // CHECK2-NEXT: store i8 0, i8* [[AAA]], align 1 3132 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 3133 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3134 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 3135 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 3136 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 3137 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3138 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 3139 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3140 // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 3141 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 3142 // CHECK2-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 3143 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 3144 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3145 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 3146 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3147 // CHECK2: omp_if.then: 3148 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3149 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 3150 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 3151 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3152 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 3153 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 3154 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3155 // CHECK2-NEXT: store i8* null, i8** [[TMP11]], align 8 3156 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3157 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 3158 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 3159 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3160 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 3161 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 3162 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3163 // CHECK2-NEXT: store i8* null, i8** [[TMP16]], align 8 3164 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3165 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 3166 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 3167 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3168 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 3169 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 3170 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3171 // CHECK2-NEXT: store i8* null, i8** [[TMP21]], align 8 3172 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3173 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 3174 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 3175 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3176 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 3177 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 3178 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 3179 // CHECK2-NEXT: store i8* null, i8** [[TMP26]], align 8 3180 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3181 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3182 // CHECK2-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3183 // CHECK2-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 3184 // CHECK2-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3185 // CHECK2: omp_offload.failed: 3186 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 3187 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 3188 // CHECK2: omp_offload.cont: 3189 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 3190 // CHECK2: omp_if.else: 3191 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 3192 // CHECK2-NEXT: br label [[OMP_IF_END]] 3193 // CHECK2: omp_if.end: 3194 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 3195 // CHECK2-NEXT: ret i32 [[TMP31]] 3196 // 3197 // 3198 // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3199 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 3200 // CHECK2-NEXT: entry: 3201 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3202 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 3203 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 3204 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3205 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3206 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3207 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 3208 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 3209 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 3210 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3211 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 3212 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 3213 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 3214 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3215 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 3216 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 3217 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 3218 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3219 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 3220 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3221 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3222 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 3223 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3224 // CHECK2: omp_if.then: 3225 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3226 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 3227 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 3228 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3229 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 3230 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 3231 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3232 // CHECK2-NEXT: store i8* null, i8** [[TMP9]], align 8 3233 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3234 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 3235 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 3236 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3237 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 3238 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 3239 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3240 // CHECK2-NEXT: store i8* null, i8** [[TMP14]], align 8 3241 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3242 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 3243 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 3244 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3245 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 3246 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 3247 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3248 // CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8 3249 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3250 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3251 // CHECK2-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3252 // CHECK2-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 3253 // CHECK2-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3254 // CHECK2: omp_offload.failed: 3255 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 3256 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 3257 // CHECK2: omp_offload.cont: 3258 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 3259 // CHECK2: omp_if.else: 3260 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 3261 // CHECK2-NEXT: br label [[OMP_IF_END]] 3262 // CHECK2: omp_if.end: 3263 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 3264 // CHECK2-NEXT: ret i32 [[TMP24]] 3265 // 3266 // 3267 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 3268 // CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3269 // CHECK2-NEXT: entry: 3270 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3271 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3272 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3273 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 3274 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 3275 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3276 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3277 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3278 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3279 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 3280 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 3281 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3282 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 3283 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3284 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 3285 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 3286 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 3287 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 3288 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 3289 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 3290 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 3291 // CHECK2-NEXT: ret void 3292 // 3293 // 3294 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 3295 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 3296 // CHECK2-NEXT: entry: 3297 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3298 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3299 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3300 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3301 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3302 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 3303 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 3304 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3305 // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 3306 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3307 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3308 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3309 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3310 // CHECK2-NEXT: [[IT:%.*]] = alloca i64, align 8 3311 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3312 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3313 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3314 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3315 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3316 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 3317 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 3318 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3319 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 3320 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3321 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 3322 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 3323 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3324 // CHECK2-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 3325 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3326 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3327 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3328 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3329 // CHECK2-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 3330 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3331 // CHECK2-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 3332 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3333 // CHECK2: cond.true: 3334 // CHECK2-NEXT: br label [[COND_END:%.*]] 3335 // CHECK2: cond.false: 3336 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3337 // CHECK2-NEXT: br label [[COND_END]] 3338 // CHECK2: cond.end: 3339 // CHECK2-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3340 // CHECK2-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 3341 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3342 // CHECK2-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 3343 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3344 // CHECK2: omp.inner.for.cond: 3345 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3346 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3347 // CHECK2-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 3348 // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3349 // CHECK2: omp.inner.for.body: 3350 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3351 // CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 3352 // CHECK2-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 3353 // CHECK2-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 3354 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 3355 // CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 3356 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 3357 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3358 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8 3359 // CHECK2-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 3360 // CHECK2-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 3361 // CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 3362 // CHECK2-NEXT: store double [[INC]], double* [[A5]], align 8 3363 // CHECK2-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 3364 // CHECK2-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 3365 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 3366 // CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 3367 // CHECK2-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 3368 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3369 // CHECK2: omp.body.continue: 3370 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3371 // CHECK2: omp.inner.for.inc: 3372 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3373 // CHECK2-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 3374 // CHECK2-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 3375 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 3376 // CHECK2: omp.inner.for.end: 3377 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3378 // CHECK2: omp.loop.exit: 3379 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 3380 // CHECK2-NEXT: ret void 3381 // 3382 // 3383 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 3384 // CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3385 // CHECK2-NEXT: entry: 3386 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3387 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3388 // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 3389 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3390 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3391 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3392 // CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 3393 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3394 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3395 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 3396 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3397 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3398 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3399 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 3400 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3401 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 3402 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3403 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 3404 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 3405 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 3406 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3407 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 3408 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3409 // CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 3410 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 3411 // CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 3412 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 3413 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 3414 // CHECK2-NEXT: ret void 3415 // 3416 // 3417 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13 3418 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3419 // CHECK2-NEXT: entry: 3420 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3421 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3422 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3423 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3424 // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 3425 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3426 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3427 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 3428 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3429 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3430 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3431 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3432 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 3433 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3434 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3435 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3436 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 3437 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3438 // CHECK2-NEXT: ret void 3439 // 3440 // 3441 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 3442 // CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3443 // CHECK2-NEXT: entry: 3444 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3445 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3446 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3447 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3448 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3449 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3450 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3451 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3452 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3453 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3454 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3455 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 3456 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3457 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 3458 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 3459 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 3460 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3461 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 3462 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3463 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 3464 // CHECK2-NEXT: ret void 3465 // 3466 // 3467 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..16 3468 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3469 // CHECK2-NEXT: entry: 3470 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3471 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3472 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3473 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3474 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3475 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3476 // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 3477 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3478 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3479 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3480 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3481 // CHECK2-NEXT: [[I:%.*]] = alloca i64, align 8 3482 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3483 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3484 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3485 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3486 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3487 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3488 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3489 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3490 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3491 // CHECK2-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 3492 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3493 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3494 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3495 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 3496 // CHECK2-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 3497 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3498 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 3499 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3500 // CHECK2: cond.true: 3501 // CHECK2-NEXT: br label [[COND_END:%.*]] 3502 // CHECK2: cond.false: 3503 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3504 // CHECK2-NEXT: br label [[COND_END]] 3505 // CHECK2: cond.end: 3506 // CHECK2-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 3507 // CHECK2-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 3508 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3509 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 3510 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3511 // CHECK2: omp.inner.for.cond: 3512 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3513 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3514 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 3515 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3516 // CHECK2: omp.inner.for.body: 3517 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3518 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 3519 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 3520 // CHECK2-NEXT: store i64 [[ADD]], i64* [[I]], align 8 3521 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 3522 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 3523 // CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 3524 // CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 3525 // CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 3526 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 3527 // CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 3528 // CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 3529 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 3530 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3531 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 3532 // CHECK2-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 3533 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3534 // CHECK2: omp.body.continue: 3535 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3536 // CHECK2: omp.inner.for.inc: 3537 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3538 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 3539 // CHECK2-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 3540 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 3541 // CHECK2: omp.inner.for.end: 3542 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3543 // CHECK2: omp.loop.exit: 3544 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 3545 // CHECK2-NEXT: ret void 3546 // 3547 // 3548 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3549 // CHECK2-SAME: () #[[ATTR6]] { 3550 // CHECK2-NEXT: entry: 3551 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 3552 // CHECK2-NEXT: ret void 3553 // 3554 // 3555 // CHECK3-LABEL: define {{[^@]+}}@_Z7get_valv 3556 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 3557 // CHECK3-NEXT: entry: 3558 // CHECK3-NEXT: ret i64 0 3559 // 3560 // 3561 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 3562 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 3563 // CHECK3-NEXT: entry: 3564 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3565 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3566 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3567 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 3568 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 3569 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 3570 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 3571 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 3572 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 3573 // CHECK3-NEXT: [[K:%.*]] = alloca i64, align 8 3574 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3575 // CHECK3-NEXT: [[LIN:%.*]] = alloca i32, align 4 3576 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3577 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 3578 // CHECK3-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 3579 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 3580 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 3581 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 3582 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 3583 // CHECK3-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 3584 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 3585 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 3586 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 3587 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 3588 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3589 // CHECK3-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 3590 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 3591 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4 3592 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4 3593 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4 3594 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 3595 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 3596 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3597 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3598 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 3599 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3600 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3601 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 3602 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 3603 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 3604 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 3605 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 3606 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 3607 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 3608 // CHECK3-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 3609 // CHECK3-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 3610 // CHECK3-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3611 // CHECK3: omp_offload.failed: 3612 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 3613 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3614 // CHECK3: omp_offload.cont: 3615 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 3616 // CHECK3-NEXT: store i64 [[CALL]], i64* [[K]], align 8 3617 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 3618 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 3619 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4 3620 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR4]] 3621 // CHECK3-NEXT: store i32 12, i32* [[LIN]], align 4 3622 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 3623 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3624 // CHECK3-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 3625 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3626 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4 3627 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4 3628 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 3629 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 3630 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4 3631 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4 3632 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3633 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 3634 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4 3635 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3636 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 3637 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4 3638 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3639 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 3640 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3641 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 3642 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4 3643 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3644 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 3645 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4 3646 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3647 // CHECK3-NEXT: store i8* null, i8** [[TMP24]], align 4 3648 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3649 // CHECK3-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 3650 // CHECK3-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4 3651 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3652 // CHECK3-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 3653 // CHECK3-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4 3654 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3655 // CHECK3-NEXT: store i8* null, i8** [[TMP29]], align 4 3656 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3657 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3658 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 3659 // CHECK3-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 3660 // CHECK3-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 3661 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 3662 // CHECK3-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4 3663 // CHECK3-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 3664 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 3665 // CHECK3-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4 3666 // CHECK3-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 3667 // CHECK3-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 3668 // CHECK3-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 3669 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 3670 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 3671 // CHECK3-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4 3672 // CHECK3-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 3673 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false) 3674 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 3675 // CHECK3-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 3676 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 3677 // CHECK3-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8* 3678 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 3679 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 3680 // CHECK3-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8* 3681 // CHECK3-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8* 3682 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false) 3683 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 3684 // CHECK3-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8* 3685 // CHECK3-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8* 3686 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false) 3687 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 3688 // CHECK3-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 3689 // CHECK3-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4 3690 // CHECK3-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) 3691 // CHECK3-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 3692 // CHECK3-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4 3693 // CHECK3-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4 3694 // CHECK3-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 3695 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 3696 // CHECK3-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2 3697 // CHECK3-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 3698 // CHECK3-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4 3699 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10 3700 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3701 // CHECK3: omp_if.then: 3702 // CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 3703 // CHECK3-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* 3704 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4 3705 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 3706 // CHECK3-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32* 3707 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4 3708 // CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 3709 // CHECK3-NEXT: store i8* null, i8** [[TMP66]], align 4 3710 // CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 3711 // CHECK3-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32* 3712 // CHECK3-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4 3713 // CHECK3-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 3714 // CHECK3-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32* 3715 // CHECK3-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4 3716 // CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 3717 // CHECK3-NEXT: store i8* null, i8** [[TMP71]], align 4 3718 // CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 3719 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 3720 // CHECK3-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3721 // CHECK3-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0 3722 // CHECK3-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 3723 // CHECK3: omp_offload.failed9: 3724 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 3725 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT10]] 3726 // CHECK3: omp_offload.cont10: 3727 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3728 // CHECK3: omp_if.else: 3729 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 3730 // CHECK3-NEXT: br label [[OMP_IF_END]] 3731 // CHECK3: omp_if.end: 3732 // CHECK3-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4 3733 // CHECK3-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4 3734 // CHECK3-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4 3735 // CHECK3-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4 3736 // CHECK3-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4 3737 // CHECK3-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3738 // CHECK3-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 3739 // CHECK3-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 3740 // CHECK3-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4 3741 // CHECK3-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20 3742 // CHECK3-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]] 3743 // CHECK3: omp_if.then13: 3744 // CHECK3-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4 3745 // CHECK3-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64 3746 // CHECK3-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]] 3747 // CHECK3-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8 3748 // CHECK3-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64 3749 // CHECK3-NEXT: [[TMP87:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 3750 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP87]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i32 80, i1 false) 3751 // CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 3752 // CHECK3-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32* 3753 // CHECK3-NEXT: store i32 [[TMP78]], i32* [[TMP89]], align 4 3754 // CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 3755 // CHECK3-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32* 3756 // CHECK3-NEXT: store i32 [[TMP78]], i32* [[TMP91]], align 4 3757 // CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 3758 // CHECK3-NEXT: store i8* null, i8** [[TMP92]], align 4 3759 // CHECK3-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 3760 // CHECK3-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]** 3761 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4 3762 // CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 3763 // CHECK3-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 3764 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4 3765 // CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 3766 // CHECK3-NEXT: store i8* null, i8** [[TMP97]], align 4 3767 // CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 3768 // CHECK3-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* 3769 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP99]], align 4 3770 // CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 3771 // CHECK3-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32* 3772 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP101]], align 4 3773 // CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 3774 // CHECK3-NEXT: store i8* null, i8** [[TMP102]], align 4 3775 // CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 3776 // CHECK3-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to float** 3777 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP104]], align 4 3778 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 3779 // CHECK3-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** 3780 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP106]], align 4 3781 // CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 3782 // CHECK3-NEXT: store i64 [[TMP83]], i64* [[TMP107]], align 4 3783 // CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 3784 // CHECK3-NEXT: store i8* null, i8** [[TMP108]], align 4 3785 // CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 3786 // CHECK3-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to [5 x [10 x double]]** 3787 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP110]], align 4 3788 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 3789 // CHECK3-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** 3790 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4 3791 // CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 3792 // CHECK3-NEXT: store i8* null, i8** [[TMP113]], align 4 3793 // CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 3794 // CHECK3-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32* 3795 // CHECK3-NEXT: store i32 5, i32* [[TMP115]], align 4 3796 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 3797 // CHECK3-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32* 3798 // CHECK3-NEXT: store i32 5, i32* [[TMP117]], align 4 3799 // CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 3800 // CHECK3-NEXT: store i8* null, i8** [[TMP118]], align 4 3801 // CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 3802 // CHECK3-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32* 3803 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP120]], align 4 3804 // CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 3805 // CHECK3-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32* 3806 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP122]], align 4 3807 // CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 3808 // CHECK3-NEXT: store i8* null, i8** [[TMP123]], align 4 3809 // CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 3810 // CHECK3-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to double** 3811 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP125]], align 4 3812 // CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 3813 // CHECK3-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** 3814 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP127]], align 4 3815 // CHECK3-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 3816 // CHECK3-NEXT: store i64 [[TMP86]], i64* [[TMP128]], align 4 3817 // CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 3818 // CHECK3-NEXT: store i8* null, i8** [[TMP129]], align 4 3819 // CHECK3-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 3820 // CHECK3-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to %struct.TT** 3821 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP131]], align 4 3822 // CHECK3-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 3823 // CHECK3-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT** 3824 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 4 3825 // CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 3826 // CHECK3-NEXT: store i8* null, i8** [[TMP134]], align 4 3827 // CHECK3-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 3828 // CHECK3-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to i32* 3829 // CHECK3-NEXT: store i32 [[TMP80]], i32* [[TMP136]], align 4 3830 // CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 3831 // CHECK3-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i32* 3832 // CHECK3-NEXT: store i32 [[TMP80]], i32* [[TMP138]], align 4 3833 // CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 3834 // CHECK3-NEXT: store i8* null, i8** [[TMP139]], align 4 3835 // CHECK3-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 3836 // CHECK3-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 3837 // CHECK3-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3838 // CHECK3-NEXT: [[TMP143:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP140]], i8** [[TMP141]], i64* [[TMP142]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3839 // CHECK3-NEXT: [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 0 3840 // CHECK3-NEXT: br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] 3841 // CHECK3: omp_offload.failed17: 3842 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 3843 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT18]] 3844 // CHECK3: omp_offload.cont18: 3845 // CHECK3-NEXT: br label [[OMP_IF_END20:%.*]] 3846 // CHECK3: omp_if.else19: 3847 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 3848 // CHECK3-NEXT: br label [[OMP_IF_END20]] 3849 // CHECK3: omp_if.end20: 3850 // CHECK3-NEXT: [[TMP145:%.*]] = load i32, i32* [[A]], align 4 3851 // CHECK3-NEXT: [[TMP146:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 3852 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP146]]) 3853 // CHECK3-NEXT: ret i32 [[TMP145]] 3854 // 3855 // 3856 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 3857 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] { 3858 // CHECK3-NEXT: entry: 3859 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 3860 // CHECK3-NEXT: ret void 3861 // 3862 // 3863 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 3864 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 3865 // CHECK3-NEXT: entry: 3866 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3867 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3868 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3869 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3870 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3871 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3872 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3873 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3874 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 3875 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3876 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3877 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3878 // CHECK3-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 3879 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3880 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3881 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3882 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3883 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3884 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3885 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 3886 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3887 // CHECK3: cond.true: 3888 // CHECK3-NEXT: br label [[COND_END:%.*]] 3889 // CHECK3: cond.false: 3890 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3891 // CHECK3-NEXT: br label [[COND_END]] 3892 // CHECK3: cond.end: 3893 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3894 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3895 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3896 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 3897 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3898 // CHECK3: omp.inner.for.cond: 3899 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3900 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3901 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3902 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3903 // CHECK3: omp.inner.for.body: 3904 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3905 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 3906 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 3907 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3908 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 3909 // CHECK3-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 3910 // CHECK3-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 3911 // CHECK3: .cancel.exit: 3912 // CHECK3-NEXT: br label [[CANCEL_EXIT:%.*]] 3913 // CHECK3: .cancel.continue: 3914 // CHECK3-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 3915 // CHECK3-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 3916 // CHECK3-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 3917 // CHECK3: .cancel.exit2: 3918 // CHECK3-NEXT: br label [[CANCEL_EXIT]] 3919 // CHECK3: .cancel.continue3: 3920 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3921 // CHECK3: omp.body.continue: 3922 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3923 // CHECK3: omp.inner.for.inc: 3924 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3925 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 3926 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 3927 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 3928 // CHECK3: omp.inner.for.end: 3929 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3930 // CHECK3: omp.loop.exit: 3931 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 3932 // CHECK3-NEXT: br label [[CANCEL_CONT:%.*]] 3933 // CHECK3: cancel.cont: 3934 // CHECK3-NEXT: ret void 3935 // CHECK3: cancel.exit: 3936 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 3937 // CHECK3-NEXT: br label [[CANCEL_CONT]] 3938 // 3939 // 3940 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 3941 // CHECK3-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 3942 // CHECK3-NEXT: entry: 3943 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3944 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 3945 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3946 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3947 // CHECK3-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 3948 // CHECK3-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 3949 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3950 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3951 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3952 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) 3953 // CHECK3-NEXT: ret void 3954 // 3955 // 3956 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 3957 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 3958 // CHECK3-NEXT: entry: 3959 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3960 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3961 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3962 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 3963 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3964 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3965 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 3966 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3967 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3968 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3969 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3970 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 3971 // CHECK3-NEXT: [[K1:%.*]] = alloca i64, align 8 3972 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3973 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3974 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3975 // CHECK3-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 3976 // CHECK3-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 3977 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 3978 // CHECK3-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 3979 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3980 // CHECK3-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 3981 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3982 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3983 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3984 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 3985 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 3986 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1) 3987 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3988 // CHECK3: omp.dispatch.cond: 3989 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 3990 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 3991 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3992 // CHECK3: omp.dispatch.body: 3993 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3994 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 3995 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3996 // CHECK3: omp.inner.for.cond: 3997 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 3998 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 3999 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 4000 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4001 // CHECK3: omp.inner.for.body: 4002 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4003 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 4004 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 4005 // CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13 4006 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !13 4007 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4008 // CHECK3-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 4009 // CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 4010 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 4011 // CHECK3-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13 4012 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !13 4013 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 4014 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13 4015 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4016 // CHECK3: omp.body.continue: 4017 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4018 // CHECK3: omp.inner.for.inc: 4019 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4020 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 4021 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4022 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 4023 // CHECK3: omp.inner.for.end: 4024 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4025 // CHECK3: omp.dispatch.inc: 4026 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 4027 // CHECK3: omp.dispatch.end: 4028 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4029 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 4030 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 4031 // CHECK3: .omp.linear.pu: 4032 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[K1]], align 8 4033 // CHECK3-NEXT: store i64 [[TMP15]], i64* [[TMP0]], align 8 4034 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 4035 // CHECK3: .omp.linear.pu.done: 4036 // CHECK3-NEXT: ret void 4037 // 4038 // 4039 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 4040 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 4041 // CHECK3-NEXT: entry: 4042 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4043 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 4044 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4045 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4046 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 4047 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4048 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4049 // CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 4050 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4051 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4052 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 4053 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4054 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 4055 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4056 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 4057 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 4058 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 4059 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 4060 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 4061 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 4062 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 4063 // CHECK3-NEXT: ret void 4064 // 4065 // 4066 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 4067 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 4068 // CHECK3-NEXT: entry: 4069 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4070 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4071 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4072 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 4073 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4074 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4075 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 4076 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 4077 // CHECK3-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 4078 // CHECK3-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 4079 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4080 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4081 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4082 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4083 // CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8 4084 // CHECK3-NEXT: [[LIN2:%.*]] = alloca i32, align 4 4085 // CHECK3-NEXT: [[A3:%.*]] = alloca i32, align 4 4086 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4087 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4088 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4089 // CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 4090 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4091 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4092 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 4093 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 4094 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4095 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 4096 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 4097 // CHECK3-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 4098 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4099 // CHECK3-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 4100 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4101 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4102 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4103 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 4104 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 4105 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 4106 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4107 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 4108 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4109 // CHECK3: cond.true: 4110 // CHECK3-NEXT: br label [[COND_END:%.*]] 4111 // CHECK3: cond.false: 4112 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4113 // CHECK3-NEXT: br label [[COND_END]] 4114 // CHECK3: cond.end: 4115 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 4116 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 4117 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4118 // CHECK3-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 4119 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4120 // CHECK3: omp.inner.for.cond: 4121 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4122 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4123 // CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 4124 // CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4125 // CHECK3: omp.inner.for.body: 4126 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4127 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 4128 // CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 4129 // CHECK3-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 4130 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 4131 // CHECK3-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 4132 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4133 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 4134 // CHECK3-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 4135 // CHECK3-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 4136 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 4137 // CHECK3-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 4138 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 4139 // CHECK3-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 4140 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4141 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 4142 // CHECK3-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 4143 // CHECK3-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 4144 // CHECK3-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 4145 // CHECK3-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 4146 // CHECK3-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 4147 // CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 4148 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 4149 // CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 4150 // CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 4151 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4152 // CHECK3: omp.body.continue: 4153 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4154 // CHECK3: omp.inner.for.inc: 4155 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4156 // CHECK3-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 4157 // CHECK3-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 4158 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 4159 // CHECK3: omp.inner.for.end: 4160 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4161 // CHECK3: omp.loop.exit: 4162 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 4163 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4164 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 4165 // CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 4166 // CHECK3: .omp.linear.pu: 4167 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 4168 // CHECK3-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 4169 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 4170 // CHECK3-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 4171 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 4172 // CHECK3: .omp.linear.pu.done: 4173 // CHECK3-NEXT: ret void 4174 // 4175 // 4176 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. 4177 // CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 4178 // CHECK3-NEXT: entry: 4179 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 4180 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 4181 // CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 4182 // CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 4183 // CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 4184 // CHECK3-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 4185 // CHECK3-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 4186 // CHECK3-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 4187 // CHECK3-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 4188 // CHECK3-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 4189 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 4190 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 4191 // CHECK3-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 4192 // CHECK3-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 4193 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 4194 // CHECK3-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 4195 // CHECK3-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 4196 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 4197 // CHECK3-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 4198 // CHECK3-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 4199 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 4200 // CHECK3-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 4201 // CHECK3-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 4202 // CHECK3-NEXT: ret void 4203 // 4204 // 4205 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 4206 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 4207 // CHECK3-NEXT: entry: 4208 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 4209 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 4210 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 4211 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 4212 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 4213 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 4214 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 4215 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 4216 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 4217 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 4218 // CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 4219 // CHECK3-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4 4220 // CHECK3-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4 4221 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 4222 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 4223 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 4224 // CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 4225 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 4226 // CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 4227 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 4228 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 4229 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 4230 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 4231 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 4232 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 4233 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 4234 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 4235 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 4236 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 4237 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 4238 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 4239 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 4240 // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 4241 // CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 4242 // CHECK3-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 4243 // CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 4244 // CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 4245 // CHECK3-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 4246 // CHECK3-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 4247 // CHECK3-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 4248 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 4249 // CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 4250 // CHECK3-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 4251 // CHECK3-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 4252 // CHECK3-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 4253 // CHECK3-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 4254 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 4255 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 4256 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 4257 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 4258 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 4259 // CHECK3-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 4260 // CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 4261 // CHECK3-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 4262 // CHECK3: omp_offload.failed.i: 4263 // CHECK3-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 4264 // CHECK3-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 4265 // CHECK3-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25 4266 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 4267 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 4268 // CHECK3-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25 4269 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !25 4270 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 4271 // CHECK3-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25 4272 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !25 4273 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR4]] 4274 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 4275 // CHECK3: .omp_outlined..3.exit: 4276 // CHECK3-NEXT: ret i32 0 4277 // 4278 // 4279 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 4280 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 4281 // CHECK3-NEXT: entry: 4282 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4283 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4284 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4285 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4286 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4287 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4288 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4289 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4290 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4291 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4292 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 4293 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4294 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 4295 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4296 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 4297 // CHECK3-NEXT: ret void 4298 // 4299 // 4300 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 4301 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 4302 // CHECK3-NEXT: entry: 4303 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4304 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4305 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4306 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4307 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4308 // CHECK3-NEXT: [[TMP:%.*]] = alloca i16, align 2 4309 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4310 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4311 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4312 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4313 // CHECK3-NEXT: [[IT:%.*]] = alloca i16, align 2 4314 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4315 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4316 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4317 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4318 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4319 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4320 // CHECK3-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 4321 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4322 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4323 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4324 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4325 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4326 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4327 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 4328 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4329 // CHECK3: cond.true: 4330 // CHECK3-NEXT: br label [[COND_END:%.*]] 4331 // CHECK3: cond.false: 4332 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4333 // CHECK3-NEXT: br label [[COND_END]] 4334 // CHECK3: cond.end: 4335 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4336 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4337 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4338 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4339 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4340 // CHECK3: omp.inner.for.cond: 4341 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4342 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4343 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4344 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4345 // CHECK3: omp.inner.for.body: 4346 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4347 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 4348 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 4349 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 4350 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 4351 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 4352 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 4353 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 4354 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 4355 // CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 4356 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 4357 // CHECK3-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 4358 // CHECK3-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 4359 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4360 // CHECK3: omp.body.continue: 4361 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4362 // CHECK3: omp.inner.for.inc: 4363 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4364 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 4365 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 4366 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 4367 // CHECK3: omp.inner.for.end: 4368 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4369 // CHECK3: omp.loop.exit: 4370 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4371 // CHECK3-NEXT: ret void 4372 // 4373 // 4374 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 4375 // CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 4376 // CHECK3-NEXT: entry: 4377 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4378 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 4379 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4380 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 4381 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 4382 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4383 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 4384 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 4385 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 4386 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4387 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4388 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 4389 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4390 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 4391 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4392 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 4393 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 4394 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4395 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 4396 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 4397 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 4398 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4399 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 4400 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4401 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 4402 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 4403 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4404 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 4405 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 4406 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 4407 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 4408 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 4409 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 4410 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4411 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4412 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4413 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 4414 // CHECK3-NEXT: ret void 4415 // 4416 // 4417 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 4418 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 4419 // CHECK3-NEXT: entry: 4420 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4421 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4422 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4423 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 4424 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4425 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 4426 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 4427 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4428 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 4429 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 4430 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 4431 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4432 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4433 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 4434 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4435 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4436 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4437 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4438 // CHECK3-NEXT: [[IT:%.*]] = alloca i8, align 1 4439 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4440 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4441 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4442 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 4443 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4444 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 4445 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 4446 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4447 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 4448 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 4449 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 4450 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4451 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 4452 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4453 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 4454 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 4455 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4456 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 4457 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 4458 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 4459 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4460 // CHECK3-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 4461 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4462 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4463 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4464 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4465 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 4466 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 4467 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4468 // CHECK3: omp.dispatch.cond: 4469 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4470 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 4471 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4472 // CHECK3: cond.true: 4473 // CHECK3-NEXT: br label [[COND_END:%.*]] 4474 // CHECK3: cond.false: 4475 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4476 // CHECK3-NEXT: br label [[COND_END]] 4477 // CHECK3: cond.end: 4478 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 4479 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4480 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4481 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 4482 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4483 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4484 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 4485 // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4486 // CHECK3: omp.dispatch.body: 4487 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4488 // CHECK3: omp.inner.for.cond: 4489 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4490 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4491 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 4492 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4493 // CHECK3: omp.inner.for.body: 4494 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4495 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 4496 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 4497 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 4498 // CHECK3-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 4499 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 4500 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 4501 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4502 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 4503 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 4504 // CHECK3-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 4505 // CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 4506 // CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 4507 // CHECK3-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 4508 // CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 4509 // CHECK3-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 4510 // CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 4511 // CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 4512 // CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 4513 // CHECK3-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 4514 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 4515 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 4516 // CHECK3-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 4517 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 4518 // CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 4519 // CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 4520 // CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 4521 // CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 4522 // CHECK3-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 4523 // CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 4524 // CHECK3-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 4525 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 4526 // CHECK3-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 4527 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 4528 // CHECK3-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 4529 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 4530 // CHECK3-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 4531 // CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 4532 // CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 4533 // CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 4534 // CHECK3-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 4535 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4536 // CHECK3: omp.body.continue: 4537 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4538 // CHECK3: omp.inner.for.inc: 4539 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4540 // CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 4541 // CHECK3-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 4542 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 4543 // CHECK3: omp.inner.for.end: 4544 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4545 // CHECK3: omp.dispatch.inc: 4546 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4547 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4548 // CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 4549 // CHECK3-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 4550 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4551 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4552 // CHECK3-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 4553 // CHECK3-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 4554 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 4555 // CHECK3: omp.dispatch.end: 4556 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 4557 // CHECK3-NEXT: ret void 4558 // 4559 // 4560 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 4561 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 4562 // CHECK3-NEXT: entry: 4563 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4564 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 4565 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 4566 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4567 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 4568 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4569 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 4570 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 4571 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 4572 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 4573 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4574 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 4575 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 4576 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 4577 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 4578 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4579 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 4580 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 4581 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 4582 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 4583 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 4584 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 4585 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 4586 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 4587 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 4588 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 4589 // CHECK3-NEXT: ret i32 [[TMP8]] 4590 // 4591 // 4592 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 4593 // CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 4594 // CHECK3-NEXT: entry: 4595 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4596 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4597 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 4598 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 4599 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 4600 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4601 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 4602 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 4603 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 4604 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 4605 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4606 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4607 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4608 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4609 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4610 // CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4 4611 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 4612 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 4613 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 4614 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 4615 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 4616 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 4617 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 4618 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 4619 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 4620 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 4621 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 4622 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4623 // CHECK3: omp_if.then: 4624 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 4625 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 4626 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 4627 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 4628 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 4629 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false) 4630 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4631 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 4632 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 4633 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4634 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 4635 // CHECK3-NEXT: store double* [[A]], double** [[TMP14]], align 4 4636 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4637 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4 4638 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4639 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 4640 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 4641 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4642 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 4643 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 4644 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4645 // CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4 4646 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4647 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 4648 // CHECK3-NEXT: store i32 2, i32* [[TMP22]], align 4 4649 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4650 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 4651 // CHECK3-NEXT: store i32 2, i32* [[TMP24]], align 4 4652 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4653 // CHECK3-NEXT: store i8* null, i8** [[TMP25]], align 4 4654 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4655 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 4656 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 4657 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4658 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 4659 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 4660 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 4661 // CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4 4662 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 4663 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 4664 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 4665 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 4666 // CHECK3-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 4667 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 4668 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 4669 // CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 4670 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 4671 // CHECK3-NEXT: store i8* null, i8** [[TMP36]], align 4 4672 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4673 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4674 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4675 // CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 4676 // CHECK3-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 4677 // CHECK3-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4678 // CHECK3: omp_offload.failed: 4679 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 4680 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 4681 // CHECK3: omp_offload.cont: 4682 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 4683 // CHECK3: omp_if.else: 4684 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 4685 // CHECK3-NEXT: br label [[OMP_IF_END]] 4686 // CHECK3: omp_if.end: 4687 // CHECK3-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 4688 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 4689 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 4690 // CHECK3-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 4691 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 4692 // CHECK3-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 4693 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 4694 // CHECK3-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 4695 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 4696 // CHECK3-NEXT: ret i32 [[ADD3]] 4697 // 4698 // 4699 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 4700 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 4701 // CHECK3-NEXT: entry: 4702 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4703 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 4704 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 4705 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 4706 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4707 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4708 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4709 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 4710 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 4711 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 4712 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 4713 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4714 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 4715 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 4716 // CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1 4717 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 4718 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4719 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4720 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 4721 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4722 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 4723 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4724 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 4725 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 4726 // CHECK3-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 4727 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 4728 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 4729 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 4730 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4731 // CHECK3: omp_if.then: 4732 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4733 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 4734 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 4735 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4736 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 4737 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 4738 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4739 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4 4740 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4741 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 4742 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 4743 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4744 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 4745 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 4746 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4747 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4 4748 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4749 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 4750 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 4751 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4752 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 4753 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 4754 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4755 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 4756 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4757 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 4758 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 4759 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4760 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 4761 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 4762 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 4763 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4 4764 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4765 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4766 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 4767 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 4768 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4769 // CHECK3: omp_offload.failed: 4770 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 4771 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 4772 // CHECK3: omp_offload.cont: 4773 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 4774 // CHECK3: omp_if.else: 4775 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 4776 // CHECK3-NEXT: br label [[OMP_IF_END]] 4777 // CHECK3: omp_if.end: 4778 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 4779 // CHECK3-NEXT: ret i32 [[TMP31]] 4780 // 4781 // 4782 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 4783 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 4784 // CHECK3-NEXT: entry: 4785 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4786 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 4787 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 4788 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4789 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4790 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4791 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 4792 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 4793 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 4794 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4795 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 4796 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 4797 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 4798 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4799 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4800 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 4801 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4802 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 4803 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4804 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4805 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 4806 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4807 // CHECK3: omp_if.then: 4808 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4809 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 4810 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 4811 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4812 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 4813 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 4814 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4815 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 4816 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4817 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 4818 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 4819 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4820 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 4821 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 4822 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4823 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 4824 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4825 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 4826 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 4827 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4828 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 4829 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 4830 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4831 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 4832 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4833 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4834 // CHECK3-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 4835 // CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 4836 // CHECK3-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4837 // CHECK3: omp_offload.failed: 4838 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 4839 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 4840 // CHECK3: omp_offload.cont: 4841 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 4842 // CHECK3: omp_if.else: 4843 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 4844 // CHECK3-NEXT: br label [[OMP_IF_END]] 4845 // CHECK3: omp_if.end: 4846 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 4847 // CHECK3-NEXT: ret i32 [[TMP24]] 4848 // 4849 // 4850 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 4851 // CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 4852 // CHECK3-NEXT: entry: 4853 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4854 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4855 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4856 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4857 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 4858 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4859 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4860 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4861 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4862 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4863 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 4864 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4865 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4866 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4867 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 4868 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 4869 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 4870 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 4871 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 4872 // CHECK3-NEXT: ret void 4873 // 4874 // 4875 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 4876 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 4877 // CHECK3-NEXT: entry: 4878 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4879 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4880 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4881 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4882 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4883 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4884 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 4885 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4886 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 4887 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4888 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4889 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4890 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4891 // CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8 4892 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4893 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4894 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4895 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4896 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4897 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4898 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 4899 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4900 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4901 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4902 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 4903 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4904 // CHECK3-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 4905 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4906 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4907 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4908 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 4909 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 4910 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4911 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 4912 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4913 // CHECK3: cond.true: 4914 // CHECK3-NEXT: br label [[COND_END:%.*]] 4915 // CHECK3: cond.false: 4916 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4917 // CHECK3-NEXT: br label [[COND_END]] 4918 // CHECK3: cond.end: 4919 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 4920 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 4921 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4922 // CHECK3-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 4923 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4924 // CHECK3: omp.inner.for.cond: 4925 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4926 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4927 // CHECK3-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 4928 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4929 // CHECK3: omp.inner.for.body: 4930 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4931 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 4932 // CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 4933 // CHECK3-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 4934 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 4935 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 4936 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 4937 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4938 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4 4939 // CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 4940 // CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 4941 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 4942 // CHECK3-NEXT: store double [[INC]], double* [[A4]], align 4 4943 // CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 4944 // CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 4945 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 4946 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 4947 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 4948 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4949 // CHECK3: omp.body.continue: 4950 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4951 // CHECK3: omp.inner.for.inc: 4952 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4953 // CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 4954 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 4955 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 4956 // CHECK3: omp.inner.for.end: 4957 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4958 // CHECK3: omp.loop.exit: 4959 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 4960 // CHECK3-NEXT: ret void 4961 // 4962 // 4963 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 4964 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 4965 // CHECK3-NEXT: entry: 4966 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4967 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4968 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 4969 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4970 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4971 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4972 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 4973 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4974 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4975 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 4976 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4977 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4978 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 4979 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4980 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4981 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 4982 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 4983 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 4984 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4985 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 4986 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4987 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 4988 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 4989 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 4990 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 4991 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 4992 // CHECK3-NEXT: ret void 4993 // 4994 // 4995 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 4996 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 4997 // CHECK3-NEXT: entry: 4998 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4999 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5000 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5001 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5002 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 5003 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5004 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5005 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 5006 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5007 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5008 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5009 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5010 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 5011 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5012 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5013 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 5014 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5015 // CHECK3-NEXT: ret void 5016 // 5017 // 5018 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 5019 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5020 // CHECK3-NEXT: entry: 5021 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5022 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5023 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5024 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5025 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5026 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5027 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5028 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5029 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5030 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5031 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5032 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5033 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5034 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 5035 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5036 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 5037 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5038 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 5039 // CHECK3-NEXT: ret void 5040 // 5041 // 5042 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 5043 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 5044 // CHECK3-NEXT: entry: 5045 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5046 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5047 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5048 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5049 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5050 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5051 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 5052 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5053 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5054 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5055 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5056 // CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 5057 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5058 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5059 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5060 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5061 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5062 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5063 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5064 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 5065 // CHECK3-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 5066 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 5067 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5068 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5069 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 5070 // CHECK3-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 5071 // CHECK3-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5072 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 5073 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5074 // CHECK3: cond.true: 5075 // CHECK3-NEXT: br label [[COND_END:%.*]] 5076 // CHECK3: cond.false: 5077 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5078 // CHECK3-NEXT: br label [[COND_END]] 5079 // CHECK3: cond.end: 5080 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 5081 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 5082 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 5083 // CHECK3-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 5084 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5085 // CHECK3: omp.inner.for.cond: 5086 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5087 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5088 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 5089 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5090 // CHECK3: omp.inner.for.body: 5091 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5092 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 5093 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 5094 // CHECK3-NEXT: store i64 [[ADD]], i64* [[I]], align 8 5095 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 5096 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 5097 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 5098 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 5099 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 5100 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 5101 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 5102 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 5103 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 5104 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5105 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 5106 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 5107 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5108 // CHECK3: omp.body.continue: 5109 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5110 // CHECK3: omp.inner.for.inc: 5111 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5112 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 5113 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 5114 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 5115 // CHECK3: omp.inner.for.end: 5116 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5117 // CHECK3: omp.loop.exit: 5118 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 5119 // CHECK3-NEXT: ret void 5120 // 5121 // 5122 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 5123 // CHECK3-SAME: () #[[ATTR6]] { 5124 // CHECK3-NEXT: entry: 5125 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 5126 // CHECK3-NEXT: ret void 5127 // 5128 // 5129 // CHECK4-LABEL: define {{[^@]+}}@_Z7get_valv 5130 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 5131 // CHECK4-NEXT: entry: 5132 // CHECK4-NEXT: ret i64 0 5133 // 5134 // 5135 // CHECK4-LABEL: define {{[^@]+}}@_Z3fooi 5136 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 5137 // CHECK4-NEXT: entry: 5138 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5139 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 5140 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 5141 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x float], align 4 5142 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 5143 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5144 // CHECK4-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 5145 // CHECK4-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 5146 // CHECK4-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 5147 // CHECK4-NEXT: [[K:%.*]] = alloca i64, align 8 5148 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5149 // CHECK4-NEXT: [[LIN:%.*]] = alloca i32, align 4 5150 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5151 // CHECK4-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 5152 // CHECK4-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 5153 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 5154 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 5155 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 5156 // CHECK4-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 5157 // CHECK4-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 5158 // CHECK4-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 5159 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 5160 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 5161 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 5162 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5163 // CHECK4-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 5164 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 5165 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4 5166 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4 5167 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4 5168 // CHECK4-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 5169 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 5170 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5171 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 5172 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 5173 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5174 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 5175 // CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 5176 // CHECK4-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 5177 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 5178 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 5179 // CHECK4-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 5180 // CHECK4-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 5181 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 5182 // CHECK4-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 5183 // CHECK4-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 5184 // CHECK4-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5185 // CHECK4: omp_offload.failed: 5186 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 5187 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 5188 // CHECK4: omp_offload.cont: 5189 // CHECK4-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 5190 // CHECK4-NEXT: store i64 [[CALL]], i64* [[K]], align 8 5191 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 5192 // CHECK4-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 5193 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4 5194 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR4]] 5195 // CHECK4-NEXT: store i32 12, i32* [[LIN]], align 4 5196 // CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 5197 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5198 // CHECK4-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 5199 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5200 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4 5201 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4 5202 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 5203 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 5204 // CHECK4-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4 5205 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4 5206 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5207 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 5208 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4 5209 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5210 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 5211 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4 5212 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5213 // CHECK4-NEXT: store i8* null, i8** [[TMP19]], align 4 5214 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5215 // CHECK4-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 5216 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4 5217 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5218 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 5219 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4 5220 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5221 // CHECK4-NEXT: store i8* null, i8** [[TMP24]], align 4 5222 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5223 // CHECK4-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 5224 // CHECK4-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4 5225 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5226 // CHECK4-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 5227 // CHECK4-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4 5228 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5229 // CHECK4-NEXT: store i8* null, i8** [[TMP29]], align 4 5230 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5231 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5232 // CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 5233 // CHECK4-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 5234 // CHECK4-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 5235 // CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 5236 // CHECK4-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4 5237 // CHECK4-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 5238 // CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 5239 // CHECK4-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4 5240 // CHECK4-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 5241 // CHECK4-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 5242 // CHECK4-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 5243 // CHECK4-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 5244 // CHECK4-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 5245 // CHECK4-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4 5246 // CHECK4-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 5247 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false) 5248 // CHECK4-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 5249 // CHECK4-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 5250 // CHECK4-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 5251 // CHECK4-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8* 5252 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 5253 // CHECK4-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 5254 // CHECK4-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8* 5255 // CHECK4-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8* 5256 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false) 5257 // CHECK4-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 5258 // CHECK4-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8* 5259 // CHECK4-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8* 5260 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false) 5261 // CHECK4-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 5262 // CHECK4-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 5263 // CHECK4-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4 5264 // CHECK4-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) 5265 // CHECK4-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 5266 // CHECK4-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4 5267 // CHECK4-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4 5268 // CHECK4-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 5269 // CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 5270 // CHECK4-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2 5271 // CHECK4-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 5272 // CHECK4-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4 5273 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10 5274 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5275 // CHECK4: omp_if.then: 5276 // CHECK4-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 5277 // CHECK4-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* 5278 // CHECK4-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4 5279 // CHECK4-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 5280 // CHECK4-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32* 5281 // CHECK4-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4 5282 // CHECK4-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 5283 // CHECK4-NEXT: store i8* null, i8** [[TMP66]], align 4 5284 // CHECK4-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 5285 // CHECK4-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32* 5286 // CHECK4-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4 5287 // CHECK4-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 5288 // CHECK4-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32* 5289 // CHECK4-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4 5290 // CHECK4-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 5291 // CHECK4-NEXT: store i8* null, i8** [[TMP71]], align 4 5292 // CHECK4-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 5293 // CHECK4-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 5294 // CHECK4-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 5295 // CHECK4-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0 5296 // CHECK4-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 5297 // CHECK4: omp_offload.failed9: 5298 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 5299 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT10]] 5300 // CHECK4: omp_offload.cont10: 5301 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 5302 // CHECK4: omp_if.else: 5303 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 5304 // CHECK4-NEXT: br label [[OMP_IF_END]] 5305 // CHECK4: omp_if.end: 5306 // CHECK4-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4 5307 // CHECK4-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4 5308 // CHECK4-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4 5309 // CHECK4-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4 5310 // CHECK4-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4 5311 // CHECK4-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5312 // CHECK4-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 5313 // CHECK4-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 5314 // CHECK4-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4 5315 // CHECK4-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20 5316 // CHECK4-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]] 5317 // CHECK4: omp_if.then13: 5318 // CHECK4-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4 5319 // CHECK4-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64 5320 // CHECK4-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]] 5321 // CHECK4-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8 5322 // CHECK4-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64 5323 // CHECK4-NEXT: [[TMP87:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 5324 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP87]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i32 80, i1 false) 5325 // CHECK4-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 5326 // CHECK4-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32* 5327 // CHECK4-NEXT: store i32 [[TMP78]], i32* [[TMP89]], align 4 5328 // CHECK4-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 5329 // CHECK4-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32* 5330 // CHECK4-NEXT: store i32 [[TMP78]], i32* [[TMP91]], align 4 5331 // CHECK4-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 5332 // CHECK4-NEXT: store i8* null, i8** [[TMP92]], align 4 5333 // CHECK4-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 5334 // CHECK4-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]** 5335 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4 5336 // CHECK4-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 5337 // CHECK4-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 5338 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4 5339 // CHECK4-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 5340 // CHECK4-NEXT: store i8* null, i8** [[TMP97]], align 4 5341 // CHECK4-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 5342 // CHECK4-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* 5343 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP99]], align 4 5344 // CHECK4-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 5345 // CHECK4-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32* 5346 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP101]], align 4 5347 // CHECK4-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 5348 // CHECK4-NEXT: store i8* null, i8** [[TMP102]], align 4 5349 // CHECK4-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 5350 // CHECK4-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to float** 5351 // CHECK4-NEXT: store float* [[VLA]], float** [[TMP104]], align 4 5352 // CHECK4-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 5353 // CHECK4-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** 5354 // CHECK4-NEXT: store float* [[VLA]], float** [[TMP106]], align 4 5355 // CHECK4-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 5356 // CHECK4-NEXT: store i64 [[TMP83]], i64* [[TMP107]], align 4 5357 // CHECK4-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 5358 // CHECK4-NEXT: store i8* null, i8** [[TMP108]], align 4 5359 // CHECK4-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 5360 // CHECK4-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to [5 x [10 x double]]** 5361 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP110]], align 4 5362 // CHECK4-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 5363 // CHECK4-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** 5364 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4 5365 // CHECK4-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 5366 // CHECK4-NEXT: store i8* null, i8** [[TMP113]], align 4 5367 // CHECK4-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 5368 // CHECK4-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32* 5369 // CHECK4-NEXT: store i32 5, i32* [[TMP115]], align 4 5370 // CHECK4-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 5371 // CHECK4-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32* 5372 // CHECK4-NEXT: store i32 5, i32* [[TMP117]], align 4 5373 // CHECK4-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 5374 // CHECK4-NEXT: store i8* null, i8** [[TMP118]], align 4 5375 // CHECK4-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 5376 // CHECK4-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32* 5377 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP120]], align 4 5378 // CHECK4-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 5379 // CHECK4-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32* 5380 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP122]], align 4 5381 // CHECK4-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 5382 // CHECK4-NEXT: store i8* null, i8** [[TMP123]], align 4 5383 // CHECK4-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 5384 // CHECK4-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to double** 5385 // CHECK4-NEXT: store double* [[VLA1]], double** [[TMP125]], align 4 5386 // CHECK4-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 5387 // CHECK4-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** 5388 // CHECK4-NEXT: store double* [[VLA1]], double** [[TMP127]], align 4 5389 // CHECK4-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 5390 // CHECK4-NEXT: store i64 [[TMP86]], i64* [[TMP128]], align 4 5391 // CHECK4-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 5392 // CHECK4-NEXT: store i8* null, i8** [[TMP129]], align 4 5393 // CHECK4-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 5394 // CHECK4-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to %struct.TT** 5395 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP131]], align 4 5396 // CHECK4-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 5397 // CHECK4-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT** 5398 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 4 5399 // CHECK4-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 5400 // CHECK4-NEXT: store i8* null, i8** [[TMP134]], align 4 5401 // CHECK4-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 5402 // CHECK4-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to i32* 5403 // CHECK4-NEXT: store i32 [[TMP80]], i32* [[TMP136]], align 4 5404 // CHECK4-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 5405 // CHECK4-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i32* 5406 // CHECK4-NEXT: store i32 [[TMP80]], i32* [[TMP138]], align 4 5407 // CHECK4-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 5408 // CHECK4-NEXT: store i8* null, i8** [[TMP139]], align 4 5409 // CHECK4-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 5410 // CHECK4-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 5411 // CHECK4-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5412 // CHECK4-NEXT: [[TMP143:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP140]], i8** [[TMP141]], i64* [[TMP142]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 5413 // CHECK4-NEXT: [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 0 5414 // CHECK4-NEXT: br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] 5415 // CHECK4: omp_offload.failed17: 5416 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 5417 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT18]] 5418 // CHECK4: omp_offload.cont18: 5419 // CHECK4-NEXT: br label [[OMP_IF_END20:%.*]] 5420 // CHECK4: omp_if.else19: 5421 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 5422 // CHECK4-NEXT: br label [[OMP_IF_END20]] 5423 // CHECK4: omp_if.end20: 5424 // CHECK4-NEXT: [[TMP145:%.*]] = load i32, i32* [[A]], align 4 5425 // CHECK4-NEXT: [[TMP146:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 5426 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP146]]) 5427 // CHECK4-NEXT: ret i32 [[TMP145]] 5428 // 5429 // 5430 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 5431 // CHECK4-SAME: () #[[ATTR2:[0-9]+]] { 5432 // CHECK4-NEXT: entry: 5433 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 5434 // CHECK4-NEXT: ret void 5435 // 5436 // 5437 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 5438 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 5439 // CHECK4-NEXT: entry: 5440 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5441 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5442 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5443 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 5444 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5445 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5446 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5447 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5448 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 5449 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5450 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5451 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5452 // CHECK4-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 5453 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5454 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5455 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5456 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 5457 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5458 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5459 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 5460 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5461 // CHECK4: cond.true: 5462 // CHECK4-NEXT: br label [[COND_END:%.*]] 5463 // CHECK4: cond.false: 5464 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5465 // CHECK4-NEXT: br label [[COND_END]] 5466 // CHECK4: cond.end: 5467 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 5468 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5469 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5470 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 5471 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5472 // CHECK4: omp.inner.for.cond: 5473 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5474 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5475 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 5476 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5477 // CHECK4: omp.inner.for.body: 5478 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5479 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 5480 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 5481 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 5482 // CHECK4-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 5483 // CHECK4-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 5484 // CHECK4-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 5485 // CHECK4: .cancel.exit: 5486 // CHECK4-NEXT: br label [[CANCEL_EXIT:%.*]] 5487 // CHECK4: .cancel.continue: 5488 // CHECK4-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 5489 // CHECK4-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 5490 // CHECK4-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 5491 // CHECK4: .cancel.exit2: 5492 // CHECK4-NEXT: br label [[CANCEL_EXIT]] 5493 // CHECK4: .cancel.continue3: 5494 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5495 // CHECK4: omp.body.continue: 5496 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5497 // CHECK4: omp.inner.for.inc: 5498 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5499 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 5500 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 5501 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 5502 // CHECK4: omp.inner.for.end: 5503 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5504 // CHECK4: omp.loop.exit: 5505 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 5506 // CHECK4-NEXT: br label [[CANCEL_CONT:%.*]] 5507 // CHECK4: cancel.cont: 5508 // CHECK4-NEXT: ret void 5509 // CHECK4: cancel.exit: 5510 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 5511 // CHECK4-NEXT: br label [[CANCEL_CONT]] 5512 // 5513 // 5514 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 5515 // CHECK4-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 5516 // CHECK4-NEXT: entry: 5517 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5518 // CHECK4-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 5519 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5520 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5521 // CHECK4-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 5522 // CHECK4-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 5523 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5524 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5525 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5526 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) 5527 // CHECK4-NEXT: ret void 5528 // 5529 // 5530 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 5531 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 5532 // CHECK4-NEXT: entry: 5533 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5534 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5535 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5536 // CHECK4-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 5537 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5538 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 5539 // CHECK4-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 5540 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5541 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5542 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5543 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5544 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 5545 // CHECK4-NEXT: [[K1:%.*]] = alloca i64, align 8 5546 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5547 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5548 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5549 // CHECK4-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 5550 // CHECK4-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 5551 // CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 5552 // CHECK4-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 5553 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5554 // CHECK4-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 5555 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5556 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5557 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5558 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 5559 // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 5560 // CHECK4-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1) 5561 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 5562 // CHECK4: omp.dispatch.cond: 5563 // CHECK4-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 5564 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 5565 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 5566 // CHECK4: omp.dispatch.body: 5567 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5568 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 5569 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5570 // CHECK4: omp.inner.for.cond: 5571 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 5572 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 5573 // CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 5574 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5575 // CHECK4: omp.inner.for.body: 5576 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 5577 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 5578 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 5579 // CHECK4-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13 5580 // CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !13 5581 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 5582 // CHECK4-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 5583 // CHECK4-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 5584 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 5585 // CHECK4-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13 5586 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !13 5587 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 5588 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13 5589 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5590 // CHECK4: omp.body.continue: 5591 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5592 // CHECK4: omp.inner.for.inc: 5593 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 5594 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 5595 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 5596 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 5597 // CHECK4: omp.inner.for.end: 5598 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 5599 // CHECK4: omp.dispatch.inc: 5600 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 5601 // CHECK4: omp.dispatch.end: 5602 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5603 // CHECK4-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 5604 // CHECK4-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 5605 // CHECK4: .omp.linear.pu: 5606 // CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[K1]], align 8 5607 // CHECK4-NEXT: store i64 [[TMP15]], i64* [[TMP0]], align 8 5608 // CHECK4-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 5609 // CHECK4: .omp.linear.pu.done: 5610 // CHECK4-NEXT: ret void 5611 // 5612 // 5613 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 5614 // CHECK4-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 5615 // CHECK4-NEXT: entry: 5616 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5617 // CHECK4-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 5618 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5619 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5620 // CHECK4-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 5621 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5622 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5623 // CHECK4-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 5624 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5625 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5626 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 5627 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5628 // CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 5629 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5630 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 5631 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 5632 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 5633 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 5634 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 5635 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 5636 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 5637 // CHECK4-NEXT: ret void 5638 // 5639 // 5640 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 5641 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 5642 // CHECK4-NEXT: entry: 5643 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5644 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5645 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5646 // CHECK4-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 5647 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5648 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5649 // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 4 5650 // CHECK4-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 5651 // CHECK4-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 5652 // CHECK4-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 5653 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5654 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5655 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5656 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5657 // CHECK4-NEXT: [[IT:%.*]] = alloca i64, align 8 5658 // CHECK4-NEXT: [[LIN2:%.*]] = alloca i32, align 4 5659 // CHECK4-NEXT: [[A3:%.*]] = alloca i32, align 4 5660 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5661 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5662 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5663 // CHECK4-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 5664 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5665 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5666 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 5667 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 5668 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5669 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 5670 // CHECK4-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 5671 // CHECK4-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 5672 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 5673 // CHECK4-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 5674 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 5675 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5676 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5677 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 5678 // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 5679 // CHECK4-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 5680 // CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5681 // CHECK4-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 5682 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5683 // CHECK4: cond.true: 5684 // CHECK4-NEXT: br label [[COND_END:%.*]] 5685 // CHECK4: cond.false: 5686 // CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5687 // CHECK4-NEXT: br label [[COND_END]] 5688 // CHECK4: cond.end: 5689 // CHECK4-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 5690 // CHECK4-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 5691 // CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 5692 // CHECK4-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 5693 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5694 // CHECK4: omp.inner.for.cond: 5695 // CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5696 // CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5697 // CHECK4-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 5698 // CHECK4-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5699 // CHECK4: omp.inner.for.body: 5700 // CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5701 // CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 5702 // CHECK4-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 5703 // CHECK4-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 5704 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 5705 // CHECK4-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 5706 // CHECK4-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5707 // CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 5708 // CHECK4-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 5709 // CHECK4-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 5710 // CHECK4-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 5711 // CHECK4-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 5712 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 5713 // CHECK4-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 5714 // CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5715 // CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 5716 // CHECK4-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 5717 // CHECK4-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 5718 // CHECK4-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 5719 // CHECK4-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 5720 // CHECK4-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 5721 // CHECK4-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 5722 // CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 5723 // CHECK4-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 5724 // CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 5725 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5726 // CHECK4: omp.body.continue: 5727 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5728 // CHECK4: omp.inner.for.inc: 5729 // CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5730 // CHECK4-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 5731 // CHECK4-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 5732 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 5733 // CHECK4: omp.inner.for.end: 5734 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5735 // CHECK4: omp.loop.exit: 5736 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 5737 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5738 // CHECK4-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 5739 // CHECK4-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 5740 // CHECK4: .omp.linear.pu: 5741 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 5742 // CHECK4-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 5743 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 5744 // CHECK4-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 5745 // CHECK4-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 5746 // CHECK4: .omp.linear.pu.done: 5747 // CHECK4-NEXT: ret void 5748 // 5749 // 5750 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map. 5751 // CHECK4-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 5752 // CHECK4-NEXT: entry: 5753 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 5754 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 5755 // CHECK4-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 5756 // CHECK4-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 5757 // CHECK4-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 5758 // CHECK4-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 5759 // CHECK4-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 5760 // CHECK4-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 5761 // CHECK4-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 5762 // CHECK4-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 5763 // CHECK4-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 5764 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 5765 // CHECK4-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 5766 // CHECK4-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 5767 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 5768 // CHECK4-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 5769 // CHECK4-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 5770 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 5771 // CHECK4-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 5772 // CHECK4-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 5773 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 5774 // CHECK4-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 5775 // CHECK4-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 5776 // CHECK4-NEXT: ret void 5777 // 5778 // 5779 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry. 5780 // CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 5781 // CHECK4-NEXT: entry: 5782 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 5783 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 5784 // CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 5785 // CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 5786 // CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 5787 // CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 5788 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 5789 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 5790 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 5791 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 5792 // CHECK4-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 5793 // CHECK4-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4 5794 // CHECK4-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4 5795 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 5796 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 5797 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 5798 // CHECK4-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 5799 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 5800 // CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 5801 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 5802 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 5803 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 5804 // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 5805 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 5806 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 5807 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 5808 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 5809 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 5810 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 5811 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 5812 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 5813 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 5814 // CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 5815 // CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 5816 // CHECK4-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 5817 // CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 5818 // CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 5819 // CHECK4-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 5820 // CHECK4-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 5821 // CHECK4-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 5822 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 5823 // CHECK4-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 5824 // CHECK4-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 5825 // CHECK4-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 5826 // CHECK4-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 5827 // CHECK4-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 5828 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 5829 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 5830 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 5831 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 5832 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 5833 // CHECK4-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 5834 // CHECK4-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 5835 // CHECK4-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 5836 // CHECK4: omp_offload.failed.i: 5837 // CHECK4-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 5838 // CHECK4-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 5839 // CHECK4-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25 5840 // CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 5841 // CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 5842 // CHECK4-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25 5843 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !25 5844 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 5845 // CHECK4-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25 5846 // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !25 5847 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR4]] 5848 // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 5849 // CHECK4: .omp_outlined..3.exit: 5850 // CHECK4-NEXT: ret i32 0 5851 // 5852 // 5853 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 5854 // CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 5855 // CHECK4-NEXT: entry: 5856 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5857 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5858 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5859 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5860 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5861 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5862 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5863 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 5864 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 5865 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 5866 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 5867 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5868 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 5869 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5870 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 5871 // CHECK4-NEXT: ret void 5872 // 5873 // 5874 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 5875 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 5876 // CHECK4-NEXT: entry: 5877 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5878 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5879 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5880 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5881 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5882 // CHECK4-NEXT: [[TMP:%.*]] = alloca i16, align 2 5883 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5884 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5885 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5886 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5887 // CHECK4-NEXT: [[IT:%.*]] = alloca i16, align 2 5888 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5889 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5890 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5891 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5892 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5893 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5894 // CHECK4-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 5895 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5896 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5897 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5898 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 5899 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5900 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5901 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 5902 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5903 // CHECK4: cond.true: 5904 // CHECK4-NEXT: br label [[COND_END:%.*]] 5905 // CHECK4: cond.false: 5906 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5907 // CHECK4-NEXT: br label [[COND_END]] 5908 // CHECK4: cond.end: 5909 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 5910 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5911 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5912 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 5913 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5914 // CHECK4: omp.inner.for.cond: 5915 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5916 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5917 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 5918 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5919 // CHECK4: omp.inner.for.body: 5920 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5921 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 5922 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 5923 // CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 5924 // CHECK4-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 5925 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 5926 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 5927 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 5928 // CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 5929 // CHECK4-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 5930 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 5931 // CHECK4-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 5932 // CHECK4-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 5933 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5934 // CHECK4: omp.body.continue: 5935 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5936 // CHECK4: omp.inner.for.inc: 5937 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5938 // CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 5939 // CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 5940 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 5941 // CHECK4: omp.inner.for.end: 5942 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5943 // CHECK4: omp.loop.exit: 5944 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 5945 // CHECK4-NEXT: ret void 5946 // 5947 // 5948 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 5949 // CHECK4-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 5950 // CHECK4-NEXT: entry: 5951 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5952 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 5953 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5954 // CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 5955 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 5956 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5957 // CHECK4-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 5958 // CHECK4-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 5959 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 5960 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 5961 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5962 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 5963 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5964 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 5965 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5966 // CHECK4-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 5967 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 5968 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5969 // CHECK4-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 5970 // CHECK4-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 5971 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 5972 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5973 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 5974 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5975 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 5976 // CHECK4-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 5977 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5978 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 5979 // CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 5980 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 5981 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 5982 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 5983 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 5984 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5985 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 5986 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 5987 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 5988 // CHECK4-NEXT: ret void 5989 // 5990 // 5991 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 5992 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 5993 // CHECK4-NEXT: entry: 5994 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5995 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5996 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5997 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 5998 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5999 // CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 6000 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 6001 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6002 // CHECK4-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 6003 // CHECK4-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 6004 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 6005 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6006 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6007 // CHECK4-NEXT: [[TMP:%.*]] = alloca i8, align 1 6008 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6009 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6010 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6011 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6012 // CHECK4-NEXT: [[IT:%.*]] = alloca i8, align 1 6013 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6014 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6015 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6016 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 6017 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6018 // CHECK4-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 6019 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 6020 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6021 // CHECK4-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 6022 // CHECK4-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 6023 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 6024 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6025 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 6026 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6027 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 6028 // CHECK4-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 6029 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6030 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 6031 // CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 6032 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 6033 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6034 // CHECK4-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 6035 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6036 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6037 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6038 // CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6039 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 6040 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 6041 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6042 // CHECK4: omp.dispatch.cond: 6043 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6044 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 6045 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6046 // CHECK4: cond.true: 6047 // CHECK4-NEXT: br label [[COND_END:%.*]] 6048 // CHECK4: cond.false: 6049 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6050 // CHECK4-NEXT: br label [[COND_END]] 6051 // CHECK4: cond.end: 6052 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 6053 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6054 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6055 // CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 6056 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6057 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6058 // CHECK4-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 6059 // CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6060 // CHECK4: omp.dispatch.body: 6061 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6062 // CHECK4: omp.inner.for.cond: 6063 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6064 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6065 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 6066 // CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6067 // CHECK4: omp.inner.for.body: 6068 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6069 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 6070 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 6071 // CHECK4-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 6072 // CHECK4-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 6073 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 6074 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 6075 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 6076 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 6077 // CHECK4-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 6078 // CHECK4-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 6079 // CHECK4-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 6080 // CHECK4-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 6081 // CHECK4-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 6082 // CHECK4-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 6083 // CHECK4-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 6084 // CHECK4-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 6085 // CHECK4-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 6086 // CHECK4-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 6087 // CHECK4-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 6088 // CHECK4-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 6089 // CHECK4-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 6090 // CHECK4-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 6091 // CHECK4-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 6092 // CHECK4-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 6093 // CHECK4-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 6094 // CHECK4-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 6095 // CHECK4-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 6096 // CHECK4-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 6097 // CHECK4-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 6098 // CHECK4-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 6099 // CHECK4-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 6100 // CHECK4-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 6101 // CHECK4-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 6102 // CHECK4-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 6103 // CHECK4-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 6104 // CHECK4-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 6105 // CHECK4-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 6106 // CHECK4-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 6107 // CHECK4-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 6108 // CHECK4-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 6109 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6110 // CHECK4: omp.body.continue: 6111 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6112 // CHECK4: omp.inner.for.inc: 6113 // CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6114 // CHECK4-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 6115 // CHECK4-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 6116 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 6117 // CHECK4: omp.inner.for.end: 6118 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6119 // CHECK4: omp.dispatch.inc: 6120 // CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6121 // CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6122 // CHECK4-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 6123 // CHECK4-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 6124 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6125 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6126 // CHECK4-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 6127 // CHECK4-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 6128 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 6129 // CHECK4: omp.dispatch.end: 6130 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 6131 // CHECK4-NEXT: ret void 6132 // 6133 // 6134 // CHECK4-LABEL: define {{[^@]+}}@_Z3bari 6135 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 6136 // CHECK4-NEXT: entry: 6137 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6138 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 6139 // CHECK4-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 6140 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6141 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 6142 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6143 // CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 6144 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6145 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6146 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6147 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6148 // CHECK4-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 6149 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6150 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6151 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6152 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6153 // CHECK4-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 6154 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6155 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6156 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6157 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6158 // CHECK4-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 6159 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 6160 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 6161 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 6162 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 6163 // CHECK4-NEXT: ret i32 [[TMP8]] 6164 // 6165 // 6166 // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6167 // CHECK4-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6168 // CHECK4-NEXT: entry: 6169 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6170 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6171 // CHECK4-NEXT: [[B:%.*]] = alloca i32, align 4 6172 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 6173 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 6174 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6175 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 6176 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 6177 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 6178 // CHECK4-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 6179 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6180 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6181 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6182 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6183 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6184 // CHECK4-NEXT: store i32 [[ADD]], i32* [[B]], align 4 6185 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6186 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 6187 // CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 6188 // CHECK4-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 6189 // CHECK4-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 6190 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 6191 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 6192 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 6193 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 6194 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6195 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 6196 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6197 // CHECK4: omp_if.then: 6198 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6199 // CHECK4-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 6200 // CHECK4-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 6201 // CHECK4-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 6202 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 6203 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false) 6204 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6205 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 6206 // CHECK4-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 6207 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6208 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 6209 // CHECK4-NEXT: store double* [[A]], double** [[TMP14]], align 4 6210 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6211 // CHECK4-NEXT: store i8* null, i8** [[TMP15]], align 4 6212 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6213 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 6214 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 6215 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6216 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 6217 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 6218 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6219 // CHECK4-NEXT: store i8* null, i8** [[TMP20]], align 4 6220 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6221 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 6222 // CHECK4-NEXT: store i32 2, i32* [[TMP22]], align 4 6223 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6224 // CHECK4-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 6225 // CHECK4-NEXT: store i32 2, i32* [[TMP24]], align 4 6226 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6227 // CHECK4-NEXT: store i8* null, i8** [[TMP25]], align 4 6228 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6229 // CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 6230 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 6231 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6232 // CHECK4-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 6233 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 6234 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6235 // CHECK4-NEXT: store i8* null, i8** [[TMP30]], align 4 6236 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 6237 // CHECK4-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 6238 // CHECK4-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 6239 // CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 6240 // CHECK4-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 6241 // CHECK4-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 6242 // CHECK4-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 6243 // CHECK4-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 6244 // CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 6245 // CHECK4-NEXT: store i8* null, i8** [[TMP36]], align 4 6246 // CHECK4-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6247 // CHECK4-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6248 // CHECK4-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6249 // CHECK4-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6250 // CHECK4-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 6251 // CHECK4-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6252 // CHECK4: omp_offload.failed: 6253 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 6254 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 6255 // CHECK4: omp_offload.cont: 6256 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 6257 // CHECK4: omp_if.else: 6258 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 6259 // CHECK4-NEXT: br label [[OMP_IF_END]] 6260 // CHECK4: omp_if.end: 6261 // CHECK4-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 6262 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 6263 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 6264 // CHECK4-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 6265 // CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 6266 // CHECK4-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 6267 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 6268 // CHECK4-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 6269 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 6270 // CHECK4-NEXT: ret i32 [[ADD3]] 6271 // 6272 // 6273 // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici 6274 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 6275 // CHECK4-NEXT: entry: 6276 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6277 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 6278 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 6279 // CHECK4-NEXT: [[AAA:%.*]] = alloca i8, align 1 6280 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6281 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6282 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6283 // CHECK4-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 6284 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 6285 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 6286 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 6287 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6288 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 6289 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 6290 // CHECK4-NEXT: store i8 0, i8* [[AAA]], align 1 6291 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6292 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 6293 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 6294 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 6295 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6296 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 6297 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6298 // CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 6299 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 6300 // CHECK4-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 6301 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 6302 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6303 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 6304 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6305 // CHECK4: omp_if.then: 6306 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6307 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 6308 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 6309 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6310 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 6311 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 6312 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6313 // CHECK4-NEXT: store i8* null, i8** [[TMP11]], align 4 6314 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6315 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 6316 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 6317 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6318 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 6319 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 6320 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6321 // CHECK4-NEXT: store i8* null, i8** [[TMP16]], align 4 6322 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6323 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 6324 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 6325 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6326 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 6327 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 6328 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6329 // CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4 6330 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6331 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 6332 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 6333 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6334 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 6335 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 6336 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6337 // CHECK4-NEXT: store i8* null, i8** [[TMP26]], align 4 6338 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6339 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6340 // CHECK4-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6341 // CHECK4-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 6342 // CHECK4-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6343 // CHECK4: omp_offload.failed: 6344 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 6345 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 6346 // CHECK4: omp_offload.cont: 6347 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 6348 // CHECK4: omp_if.else: 6349 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 6350 // CHECK4-NEXT: br label [[OMP_IF_END]] 6351 // CHECK4: omp_if.end: 6352 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 6353 // CHECK4-NEXT: ret i32 [[TMP31]] 6354 // 6355 // 6356 // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6357 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 6358 // CHECK4-NEXT: entry: 6359 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6360 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 6361 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 6362 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6363 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6364 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6365 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 6366 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 6367 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 6368 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6369 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 6370 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 6371 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6372 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 6373 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 6374 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 6375 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6376 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 6377 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6378 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6379 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 6380 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6381 // CHECK4: omp_if.then: 6382 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6383 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 6384 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 6385 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6386 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 6387 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 6388 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6389 // CHECK4-NEXT: store i8* null, i8** [[TMP9]], align 4 6390 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6391 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 6392 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 6393 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6394 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 6395 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 6396 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6397 // CHECK4-NEXT: store i8* null, i8** [[TMP14]], align 4 6398 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6399 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 6400 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 6401 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6402 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 6403 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 6404 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6405 // CHECK4-NEXT: store i8* null, i8** [[TMP19]], align 4 6406 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6407 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6408 // CHECK4-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6409 // CHECK4-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 6410 // CHECK4-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6411 // CHECK4: omp_offload.failed: 6412 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 6413 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 6414 // CHECK4: omp_offload.cont: 6415 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 6416 // CHECK4: omp_if.else: 6417 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 6418 // CHECK4-NEXT: br label [[OMP_IF_END]] 6419 // CHECK4: omp_if.end: 6420 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 6421 // CHECK4-NEXT: ret i32 [[TMP24]] 6422 // 6423 // 6424 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 6425 // CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 6426 // CHECK4-NEXT: entry: 6427 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6428 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6429 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6430 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6431 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 6432 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6433 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6434 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6435 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6436 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6437 // CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 6438 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6439 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6440 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6441 // CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 6442 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 6443 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 6444 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 6445 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 6446 // CHECK4-NEXT: ret void 6447 // 6448 // 6449 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 6450 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 6451 // CHECK4-NEXT: entry: 6452 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6453 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6454 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6455 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6456 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6457 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6458 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 6459 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6460 // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 4 6461 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6462 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6463 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6464 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6465 // CHECK4-NEXT: [[IT:%.*]] = alloca i64, align 8 6466 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6467 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6468 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6469 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6470 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6471 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6472 // CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 6473 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6474 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6475 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6476 // CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 6477 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 6478 // CHECK4-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 6479 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 6480 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6481 // CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6482 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 6483 // CHECK4-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 6484 // CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6485 // CHECK4-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 6486 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6487 // CHECK4: cond.true: 6488 // CHECK4-NEXT: br label [[COND_END:%.*]] 6489 // CHECK4: cond.false: 6490 // CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6491 // CHECK4-NEXT: br label [[COND_END]] 6492 // CHECK4: cond.end: 6493 // CHECK4-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 6494 // CHECK4-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 6495 // CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6496 // CHECK4-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 6497 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6498 // CHECK4: omp.inner.for.cond: 6499 // CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6500 // CHECK4-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6501 // CHECK4-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 6502 // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6503 // CHECK4: omp.inner.for.body: 6504 // CHECK4-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6505 // CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 6506 // CHECK4-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 6507 // CHECK4-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 6508 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 6509 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 6510 // CHECK4-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 6511 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 6512 // CHECK4-NEXT: store double [[ADD]], double* [[A]], align 4 6513 // CHECK4-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 6514 // CHECK4-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 6515 // CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 6516 // CHECK4-NEXT: store double [[INC]], double* [[A4]], align 4 6517 // CHECK4-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 6518 // CHECK4-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 6519 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 6520 // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 6521 // CHECK4-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 6522 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6523 // CHECK4: omp.body.continue: 6524 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6525 // CHECK4: omp.inner.for.inc: 6526 // CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6527 // CHECK4-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 6528 // CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 6529 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 6530 // CHECK4: omp.inner.for.end: 6531 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6532 // CHECK4: omp.loop.exit: 6533 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 6534 // CHECK4-NEXT: ret void 6535 // 6536 // 6537 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 6538 // CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6539 // CHECK4-NEXT: entry: 6540 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6541 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6542 // CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 6543 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 6544 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6545 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6546 // CHECK4-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 6547 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6548 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6549 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 6550 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 6551 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6552 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 6553 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 6554 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 6555 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 6556 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 6557 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 6558 // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6559 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 6560 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6561 // CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 6562 // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 6563 // CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 6564 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 6565 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 6566 // CHECK4-NEXT: ret void 6567 // 6568 // 6569 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13 6570 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 6571 // CHECK4-NEXT: entry: 6572 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6573 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6574 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6575 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6576 // CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 6577 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 6578 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6579 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 6580 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6581 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6582 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6583 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6584 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 6585 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 6586 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6587 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 6588 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 6589 // CHECK4-NEXT: ret void 6590 // 6591 // 6592 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 6593 // CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6594 // CHECK4-NEXT: entry: 6595 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6596 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6597 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 6598 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6599 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6600 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6601 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6602 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 6603 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6604 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 6605 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 6606 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 6607 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 6608 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 6609 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6610 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 6611 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6612 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 6613 // CHECK4-NEXT: ret void 6614 // 6615 // 6616 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..16 6617 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 6618 // CHECK4-NEXT: entry: 6619 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6620 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6621 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6622 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6623 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 6624 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6625 // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 4 6626 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6627 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6628 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6629 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6630 // CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 6631 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6632 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6633 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6634 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6635 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 6636 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6637 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 6638 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 6639 // CHECK4-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 6640 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 6641 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6642 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6643 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 6644 // CHECK4-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 6645 // CHECK4-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6646 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 6647 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6648 // CHECK4: cond.true: 6649 // CHECK4-NEXT: br label [[COND_END:%.*]] 6650 // CHECK4: cond.false: 6651 // CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6652 // CHECK4-NEXT: br label [[COND_END]] 6653 // CHECK4: cond.end: 6654 // CHECK4-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 6655 // CHECK4-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 6656 // CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6657 // CHECK4-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 6658 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6659 // CHECK4: omp.inner.for.cond: 6660 // CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6661 // CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6662 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 6663 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6664 // CHECK4: omp.inner.for.body: 6665 // CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6666 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 6667 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 6668 // CHECK4-NEXT: store i64 [[ADD]], i64* [[I]], align 8 6669 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 6670 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 6671 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 6672 // CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 6673 // CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 6674 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 6675 // CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 6676 // CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 6677 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 6678 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 6679 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 6680 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 6681 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6682 // CHECK4: omp.body.continue: 6683 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6684 // CHECK4: omp.inner.for.inc: 6685 // CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6686 // CHECK4-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 6687 // CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 6688 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 6689 // CHECK4: omp.inner.for.end: 6690 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6691 // CHECK4: omp.loop.exit: 6692 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 6693 // CHECK4-NEXT: ret void 6694 // 6695 // 6696 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 6697 // CHECK4-SAME: () #[[ATTR6]] { 6698 // CHECK4-NEXT: entry: 6699 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 6700 // CHECK4-NEXT: ret void 6701 // 6702 // 6703 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 6704 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 6705 // CHECK9-NEXT: entry: 6706 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 6707 // CHECK9-NEXT: ret void 6708 // 6709 // 6710 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 6711 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 6712 // CHECK9-NEXT: entry: 6713 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6714 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6715 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6716 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 6717 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6718 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6719 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6720 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6721 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 6722 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6723 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6724 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6725 // CHECK9-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 6726 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6727 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6728 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6729 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 6730 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6731 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6732 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 6733 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6734 // CHECK9: cond.true: 6735 // CHECK9-NEXT: br label [[COND_END:%.*]] 6736 // CHECK9: cond.false: 6737 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6738 // CHECK9-NEXT: br label [[COND_END]] 6739 // CHECK9: cond.end: 6740 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 6741 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6742 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6743 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 6744 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6745 // CHECK9: omp.inner.for.cond: 6746 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6747 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6748 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 6749 // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6750 // CHECK9: omp.inner.for.body: 6751 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6752 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 6753 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 6754 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 6755 // CHECK9-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 6756 // CHECK9-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 6757 // CHECK9-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 6758 // CHECK9: .cancel.exit: 6759 // CHECK9-NEXT: br label [[CANCEL_EXIT:%.*]] 6760 // CHECK9: .cancel.continue: 6761 // CHECK9-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 6762 // CHECK9-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 6763 // CHECK9-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 6764 // CHECK9: .cancel.exit2: 6765 // CHECK9-NEXT: br label [[CANCEL_EXIT]] 6766 // CHECK9: .cancel.continue3: 6767 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6768 // CHECK9: omp.body.continue: 6769 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6770 // CHECK9: omp.inner.for.inc: 6771 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6772 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 6773 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 6774 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 6775 // CHECK9: omp.inner.for.end: 6776 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6777 // CHECK9: omp.loop.exit: 6778 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 6779 // CHECK9-NEXT: br label [[CANCEL_CONT:%.*]] 6780 // CHECK9: cancel.cont: 6781 // CHECK9-NEXT: ret void 6782 // CHECK9: cancel.exit: 6783 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 6784 // CHECK9-NEXT: br label [[CANCEL_CONT]] 6785 // 6786 // 6787 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 6788 // CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 6789 // CHECK9-NEXT: entry: 6790 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6791 // CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 6792 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6793 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6794 // CHECK9-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 6795 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6796 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6797 // CHECK9-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 6798 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6799 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6800 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 6801 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6802 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 6803 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6804 // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 6805 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6806 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 6807 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 6808 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 6809 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 6810 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 6811 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6812 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 6813 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 6814 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 6815 // CHECK9-NEXT: ret void 6816 // 6817 // 6818 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 6819 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 6820 // CHECK9-NEXT: entry: 6821 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6822 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6823 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6824 // CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 6825 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6826 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6827 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 6828 // CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 6829 // CHECK9-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 6830 // CHECK9-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 6831 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6832 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6833 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6834 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6835 // CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8 6836 // CHECK9-NEXT: [[LIN4:%.*]] = alloca i32, align 4 6837 // CHECK9-NEXT: [[A5:%.*]] = alloca i32, align 4 6838 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6839 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6840 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6841 // CHECK9-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 6842 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6843 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6844 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 6845 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6846 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 6847 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 6848 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 6849 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 6850 // CHECK9-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 6851 // CHECK9-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 6852 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 6853 // CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 6854 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 6855 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6856 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6857 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 6858 // CHECK9-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 6859 // CHECK9-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 6860 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6861 // CHECK9-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 6862 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6863 // CHECK9: cond.true: 6864 // CHECK9-NEXT: br label [[COND_END:%.*]] 6865 // CHECK9: cond.false: 6866 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6867 // CHECK9-NEXT: br label [[COND_END]] 6868 // CHECK9: cond.end: 6869 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 6870 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 6871 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6872 // CHECK9-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 6873 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6874 // CHECK9: omp.inner.for.cond: 6875 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6876 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6877 // CHECK9-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 6878 // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6879 // CHECK9: omp.inner.for.body: 6880 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6881 // CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 6882 // CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 6883 // CHECK9-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 6884 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 6885 // CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 6886 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6887 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 6888 // CHECK9-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 6889 // CHECK9-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 6890 // CHECK9-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 6891 // CHECK9-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 6892 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 6893 // CHECK9-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 6894 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6895 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 6896 // CHECK9-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 6897 // CHECK9-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 6898 // CHECK9-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 6899 // CHECK9-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 6900 // CHECK9-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 6901 // CHECK9-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 6902 // CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 6903 // CHECK9-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 6904 // CHECK9-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 6905 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6906 // CHECK9: omp.body.continue: 6907 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6908 // CHECK9: omp.inner.for.inc: 6909 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6910 // CHECK9-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 6911 // CHECK9-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 6912 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 6913 // CHECK9: omp.inner.for.end: 6914 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6915 // CHECK9: omp.loop.exit: 6916 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 6917 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6918 // CHECK9-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 6919 // CHECK9-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 6920 // CHECK9: .omp.linear.pu: 6921 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 6922 // CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 6923 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 6924 // CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 6925 // CHECK9-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 6926 // CHECK9: .omp.linear.pu.done: 6927 // CHECK9-NEXT: ret void 6928 // 6929 // 6930 // CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv 6931 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 6932 // CHECK9-NEXT: entry: 6933 // CHECK9-NEXT: ret i64 0 6934 // 6935 // 6936 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 6937 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 6938 // CHECK9-NEXT: entry: 6939 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6940 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6941 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6942 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6943 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6944 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6945 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6946 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6947 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 6948 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6949 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 6950 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 6951 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 6952 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6953 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 6954 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6955 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 6956 // CHECK9-NEXT: ret void 6957 // 6958 // 6959 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 6960 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 6961 // CHECK9-NEXT: entry: 6962 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6963 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6964 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6965 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6966 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6967 // CHECK9-NEXT: [[TMP:%.*]] = alloca i16, align 2 6968 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6969 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6970 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6971 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6972 // CHECK9-NEXT: [[IT:%.*]] = alloca i16, align 2 6973 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6974 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6975 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6976 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6977 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6978 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6979 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6980 // CHECK9-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 6981 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6982 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6983 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6984 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 6985 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6986 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6987 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 6988 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6989 // CHECK9: cond.true: 6990 // CHECK9-NEXT: br label [[COND_END:%.*]] 6991 // CHECK9: cond.false: 6992 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6993 // CHECK9-NEXT: br label [[COND_END]] 6994 // CHECK9: cond.end: 6995 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 6996 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6997 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6998 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 6999 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7000 // CHECK9: omp.inner.for.cond: 7001 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7002 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7003 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 7004 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7005 // CHECK9: omp.inner.for.body: 7006 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7007 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 7008 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 7009 // CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 7010 // CHECK9-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 7011 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 7012 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 7013 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 7014 // CHECK9-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 7015 // CHECK9-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 7016 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 7017 // CHECK9-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 7018 // CHECK9-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 7019 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7020 // CHECK9: omp.body.continue: 7021 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7022 // CHECK9: omp.inner.for.inc: 7023 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7024 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 7025 // CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 7026 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 7027 // CHECK9: omp.inner.for.end: 7028 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7029 // CHECK9: omp.loop.exit: 7030 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 7031 // CHECK9-NEXT: ret void 7032 // 7033 // 7034 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 7035 // CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 7036 // CHECK9-NEXT: entry: 7037 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7038 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 7039 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7040 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 7041 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 7042 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7043 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 7044 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 7045 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 7046 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 7047 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7048 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 7049 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7050 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 7051 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7052 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 7053 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 7054 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7055 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 7056 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 7057 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 7058 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 7059 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7060 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 7061 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7062 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 7063 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 7064 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7065 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 7066 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 7067 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 7068 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 7069 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 7070 // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7071 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 7072 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 7073 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 7074 // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 7075 // CHECK9-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 7076 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 7077 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 7078 // CHECK9-NEXT: ret void 7079 // 7080 // 7081 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 7082 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 7083 // CHECK9-NEXT: entry: 7084 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7085 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7086 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7087 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 7088 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7089 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 7090 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 7091 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7092 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 7093 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 7094 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 7095 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 7096 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7097 // CHECK9-NEXT: [[TMP:%.*]] = alloca i8, align 1 7098 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7099 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7100 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7101 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7102 // CHECK9-NEXT: [[IT:%.*]] = alloca i8, align 1 7103 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7104 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7105 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7106 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 7107 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7108 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 7109 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 7110 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7111 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 7112 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 7113 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 7114 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 7115 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7116 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 7117 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7118 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 7119 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 7120 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7121 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 7122 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 7123 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 7124 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 7125 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7126 // CHECK9-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 7127 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7128 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7129 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 7130 // CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7131 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 7132 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 7133 // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 7134 // CHECK9: omp.dispatch.cond: 7135 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7136 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 7137 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7138 // CHECK9: cond.true: 7139 // CHECK9-NEXT: br label [[COND_END:%.*]] 7140 // CHECK9: cond.false: 7141 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7142 // CHECK9-NEXT: br label [[COND_END]] 7143 // CHECK9: cond.end: 7144 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 7145 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7146 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7147 // CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 7148 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7149 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7150 // CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 7151 // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 7152 // CHECK9: omp.dispatch.body: 7153 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7154 // CHECK9: omp.inner.for.cond: 7155 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7156 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7157 // CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 7158 // CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7159 // CHECK9: omp.inner.for.body: 7160 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7161 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 7162 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 7163 // CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 7164 // CHECK9-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 7165 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 7166 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 7167 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 7168 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 7169 // CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 7170 // CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 7171 // CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 7172 // CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 7173 // CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 7174 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 7175 // CHECK9-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 7176 // CHECK9-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 7177 // CHECK9-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 7178 // CHECK9-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 7179 // CHECK9-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 7180 // CHECK9-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 7181 // CHECK9-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 7182 // CHECK9-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 7183 // CHECK9-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 7184 // CHECK9-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 7185 // CHECK9-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 7186 // CHECK9-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 7187 // CHECK9-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 7188 // CHECK9-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 7189 // CHECK9-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 7190 // CHECK9-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 7191 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 7192 // CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 7193 // CHECK9-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 7194 // CHECK9-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 7195 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 7196 // CHECK9-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 7197 // CHECK9-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 7198 // CHECK9-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 7199 // CHECK9-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 7200 // CHECK9-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 7201 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7202 // CHECK9: omp.body.continue: 7203 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7204 // CHECK9: omp.inner.for.inc: 7205 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7206 // CHECK9-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 7207 // CHECK9-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 7208 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 7209 // CHECK9: omp.inner.for.end: 7210 // CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 7211 // CHECK9: omp.dispatch.inc: 7212 // CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7213 // CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 7214 // CHECK9-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 7215 // CHECK9-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 7216 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7217 // CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 7218 // CHECK9-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 7219 // CHECK9-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 7220 // CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] 7221 // CHECK9: omp.dispatch.end: 7222 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 7223 // CHECK9-NEXT: ret void 7224 // 7225 // 7226 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 7227 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7228 // CHECK9-NEXT: entry: 7229 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7230 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7231 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 7232 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7233 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7234 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7235 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 7236 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7237 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7238 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 7239 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7240 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7241 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7242 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 7243 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7244 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 7245 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7246 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 7247 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 7248 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 7249 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7250 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 7251 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7252 // CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 7253 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 7254 // CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 7255 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 7256 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 7257 // CHECK9-NEXT: ret void 7258 // 7259 // 7260 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 7261 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 7262 // CHECK9-NEXT: entry: 7263 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7264 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7265 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7266 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7267 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 7268 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7269 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7270 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 7271 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7272 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7273 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7274 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7275 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 7276 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7277 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7278 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7279 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 7280 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7281 // CHECK9-NEXT: ret void 7282 // 7283 // 7284 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 7285 // CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 7286 // CHECK9-NEXT: entry: 7287 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 7288 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 7289 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7290 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7291 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 7292 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 7293 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 7294 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 7295 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7296 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7297 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 7298 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 7299 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 7300 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7301 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7302 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 7303 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 7304 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 7305 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 7306 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 7307 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 7308 // CHECK9-NEXT: ret void 7309 // 7310 // 7311 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 7312 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 7313 // CHECK9-NEXT: entry: 7314 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7315 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7316 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 7317 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 7318 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7319 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7320 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 7321 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7322 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 7323 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7324 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7325 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 7326 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7327 // CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8 7328 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7329 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7330 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 7331 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 7332 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7333 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7334 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 7335 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 7336 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 7337 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7338 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7339 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 7340 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 7341 // CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 7342 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 7343 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7344 // CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7345 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 7346 // CHECK9-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 7347 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7348 // CHECK9-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 7349 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7350 // CHECK9: cond.true: 7351 // CHECK9-NEXT: br label [[COND_END:%.*]] 7352 // CHECK9: cond.false: 7353 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7354 // CHECK9-NEXT: br label [[COND_END]] 7355 // CHECK9: cond.end: 7356 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 7357 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 7358 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 7359 // CHECK9-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 7360 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7361 // CHECK9: omp.inner.for.cond: 7362 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7363 // CHECK9-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7364 // CHECK9-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 7365 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7366 // CHECK9: omp.inner.for.body: 7367 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7368 // CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 7369 // CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 7370 // CHECK9-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 7371 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 7372 // CHECK9-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 7373 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 7374 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 7375 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 7376 // CHECK9-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 7377 // CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 7378 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 7379 // CHECK9-NEXT: store double [[INC]], double* [[A5]], align 8 7380 // CHECK9-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 7381 // CHECK9-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 7382 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 7383 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 7384 // CHECK9-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 7385 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7386 // CHECK9: omp.body.continue: 7387 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7388 // CHECK9: omp.inner.for.inc: 7389 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7390 // CHECK9-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 7391 // CHECK9-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 7392 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 7393 // CHECK9: omp.inner.for.end: 7394 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7395 // CHECK9: omp.loop.exit: 7396 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 7397 // CHECK9-NEXT: ret void 7398 // 7399 // 7400 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 7401 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7402 // CHECK9-NEXT: entry: 7403 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7404 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7405 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7406 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7407 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7408 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7409 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7410 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7411 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7412 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7413 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7414 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 7415 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7416 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 7417 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 7418 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 7419 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7420 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 7421 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7422 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 7423 // CHECK9-NEXT: ret void 7424 // 7425 // 7426 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 7427 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 7428 // CHECK9-NEXT: entry: 7429 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7430 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7431 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7432 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7433 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7434 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7435 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 7436 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7437 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7438 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 7439 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7440 // CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8 7441 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7442 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7443 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7444 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7445 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7446 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7447 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7448 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7449 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 7450 // CHECK9-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 7451 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 7452 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7453 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7454 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 7455 // CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 7456 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7457 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 7458 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7459 // CHECK9: cond.true: 7460 // CHECK9-NEXT: br label [[COND_END:%.*]] 7461 // CHECK9: cond.false: 7462 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7463 // CHECK9-NEXT: br label [[COND_END]] 7464 // CHECK9: cond.end: 7465 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 7466 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 7467 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 7468 // CHECK9-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 7469 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7470 // CHECK9: omp.inner.for.cond: 7471 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7472 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7473 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 7474 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7475 // CHECK9: omp.inner.for.body: 7476 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7477 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 7478 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 7479 // CHECK9-NEXT: store i64 [[ADD]], i64* [[I]], align 8 7480 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 7481 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 7482 // CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 7483 // CHECK9-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 7484 // CHECK9-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 7485 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 7486 // CHECK9-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 7487 // CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 7488 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 7489 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 7490 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 7491 // CHECK9-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 7492 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7493 // CHECK9: omp.body.continue: 7494 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7495 // CHECK9: omp.inner.for.inc: 7496 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7497 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 7498 // CHECK9-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 7499 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 7500 // CHECK9: omp.inner.for.end: 7501 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7502 // CHECK9: omp.loop.exit: 7503 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 7504 // CHECK9-NEXT: ret void 7505 // 7506 // 7507 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 7508 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 7509 // CHECK10-NEXT: entry: 7510 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 7511 // CHECK10-NEXT: ret void 7512 // 7513 // 7514 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 7515 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 7516 // CHECK10-NEXT: entry: 7517 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7518 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7519 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7520 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 7521 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7522 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7523 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7524 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7525 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 7526 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7527 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7528 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7529 // CHECK10-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 7530 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7531 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7532 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7533 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 7534 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 7535 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7536 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 7537 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7538 // CHECK10: cond.true: 7539 // CHECK10-NEXT: br label [[COND_END:%.*]] 7540 // CHECK10: cond.false: 7541 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7542 // CHECK10-NEXT: br label [[COND_END]] 7543 // CHECK10: cond.end: 7544 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 7545 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7546 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7547 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 7548 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7549 // CHECK10: omp.inner.for.cond: 7550 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7551 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7552 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 7553 // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7554 // CHECK10: omp.inner.for.body: 7555 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7556 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 7557 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 7558 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7559 // CHECK10-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 7560 // CHECK10-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 7561 // CHECK10-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 7562 // CHECK10: .cancel.exit: 7563 // CHECK10-NEXT: br label [[CANCEL_EXIT:%.*]] 7564 // CHECK10: .cancel.continue: 7565 // CHECK10-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 7566 // CHECK10-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 7567 // CHECK10-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 7568 // CHECK10: .cancel.exit2: 7569 // CHECK10-NEXT: br label [[CANCEL_EXIT]] 7570 // CHECK10: .cancel.continue3: 7571 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7572 // CHECK10: omp.body.continue: 7573 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7574 // CHECK10: omp.inner.for.inc: 7575 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7576 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 7577 // CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 7578 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 7579 // CHECK10: omp.inner.for.end: 7580 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7581 // CHECK10: omp.loop.exit: 7582 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 7583 // CHECK10-NEXT: br label [[CANCEL_CONT:%.*]] 7584 // CHECK10: cancel.cont: 7585 // CHECK10-NEXT: ret void 7586 // CHECK10: cancel.exit: 7587 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 7588 // CHECK10-NEXT: br label [[CANCEL_CONT]] 7589 // 7590 // 7591 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 7592 // CHECK10-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 7593 // CHECK10-NEXT: entry: 7594 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7595 // CHECK10-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 7596 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7597 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7598 // CHECK10-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 7599 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7600 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7601 // CHECK10-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 7602 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7603 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7604 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 7605 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7606 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 7607 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7608 // CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 7609 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7610 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 7611 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 7612 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 7613 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 7614 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 7615 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7616 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 7617 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 7618 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 7619 // CHECK10-NEXT: ret void 7620 // 7621 // 7622 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 7623 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 7624 // CHECK10-NEXT: entry: 7625 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7626 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7627 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7628 // CHECK10-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 7629 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7630 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7631 // CHECK10-NEXT: [[TMP:%.*]] = alloca i64, align 8 7632 // CHECK10-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 7633 // CHECK10-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 7634 // CHECK10-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 7635 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7636 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7637 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 7638 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7639 // CHECK10-NEXT: [[IT:%.*]] = alloca i64, align 8 7640 // CHECK10-NEXT: [[LIN4:%.*]] = alloca i32, align 4 7641 // CHECK10-NEXT: [[A5:%.*]] = alloca i32, align 4 7642 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7643 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7644 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7645 // CHECK10-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 7646 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7647 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7648 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 7649 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7650 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 7651 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 7652 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 7653 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 7654 // CHECK10-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 7655 // CHECK10-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 7656 // CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 7657 // CHECK10-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 7658 // CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 7659 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7660 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7661 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 7662 // CHECK10-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 7663 // CHECK10-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 7664 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7665 // CHECK10-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 7666 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7667 // CHECK10: cond.true: 7668 // CHECK10-NEXT: br label [[COND_END:%.*]] 7669 // CHECK10: cond.false: 7670 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7671 // CHECK10-NEXT: br label [[COND_END]] 7672 // CHECK10: cond.end: 7673 // CHECK10-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 7674 // CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 7675 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 7676 // CHECK10-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 7677 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7678 // CHECK10: omp.inner.for.cond: 7679 // CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7680 // CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7681 // CHECK10-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 7682 // CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7683 // CHECK10: omp.inner.for.body: 7684 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7685 // CHECK10-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 7686 // CHECK10-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 7687 // CHECK10-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 7688 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 7689 // CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 7690 // CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7691 // CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 7692 // CHECK10-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 7693 // CHECK10-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 7694 // CHECK10-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 7695 // CHECK10-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 7696 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 7697 // CHECK10-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 7698 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7699 // CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 7700 // CHECK10-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 7701 // CHECK10-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 7702 // CHECK10-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 7703 // CHECK10-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 7704 // CHECK10-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 7705 // CHECK10-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 7706 // CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 7707 // CHECK10-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 7708 // CHECK10-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 7709 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7710 // CHECK10: omp.body.continue: 7711 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7712 // CHECK10: omp.inner.for.inc: 7713 // CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7714 // CHECK10-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 7715 // CHECK10-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 7716 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 7717 // CHECK10: omp.inner.for.end: 7718 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7719 // CHECK10: omp.loop.exit: 7720 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 7721 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 7722 // CHECK10-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 7723 // CHECK10-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 7724 // CHECK10: .omp.linear.pu: 7725 // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 7726 // CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 7727 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 7728 // CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 7729 // CHECK10-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 7730 // CHECK10: .omp.linear.pu.done: 7731 // CHECK10-NEXT: ret void 7732 // 7733 // 7734 // CHECK10-LABEL: define {{[^@]+}}@_Z7get_valv 7735 // CHECK10-SAME: () #[[ATTR3:[0-9]+]] { 7736 // CHECK10-NEXT: entry: 7737 // CHECK10-NEXT: ret i64 0 7738 // 7739 // 7740 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 7741 // CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 7742 // CHECK10-NEXT: entry: 7743 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7744 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7745 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7746 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7747 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7748 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7749 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7750 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7751 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 7752 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7753 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 7754 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 7755 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 7756 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7757 // CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 7758 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7759 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 7760 // CHECK10-NEXT: ret void 7761 // 7762 // 7763 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 7764 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 7765 // CHECK10-NEXT: entry: 7766 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7767 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7768 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7769 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7770 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7771 // CHECK10-NEXT: [[TMP:%.*]] = alloca i16, align 2 7772 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7773 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7774 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7775 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7776 // CHECK10-NEXT: [[IT:%.*]] = alloca i16, align 2 7777 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7778 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7779 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7780 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7781 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7782 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7783 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7784 // CHECK10-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 7785 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7786 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7787 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7788 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 7789 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 7790 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7791 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 7792 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7793 // CHECK10: cond.true: 7794 // CHECK10-NEXT: br label [[COND_END:%.*]] 7795 // CHECK10: cond.false: 7796 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7797 // CHECK10-NEXT: br label [[COND_END]] 7798 // CHECK10: cond.end: 7799 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 7800 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7801 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7802 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 7803 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7804 // CHECK10: omp.inner.for.cond: 7805 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7806 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7807 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 7808 // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7809 // CHECK10: omp.inner.for.body: 7810 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7811 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 7812 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 7813 // CHECK10-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 7814 // CHECK10-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 7815 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 7816 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 7817 // CHECK10-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 7818 // CHECK10-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 7819 // CHECK10-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 7820 // CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 7821 // CHECK10-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 7822 // CHECK10-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 7823 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7824 // CHECK10: omp.body.continue: 7825 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7826 // CHECK10: omp.inner.for.inc: 7827 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7828 // CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 7829 // CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 7830 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 7831 // CHECK10: omp.inner.for.end: 7832 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7833 // CHECK10: omp.loop.exit: 7834 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 7835 // CHECK10-NEXT: ret void 7836 // 7837 // 7838 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 7839 // CHECK10-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 7840 // CHECK10-NEXT: entry: 7841 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7842 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 7843 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7844 // CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 7845 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 7846 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7847 // CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 7848 // CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 7849 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 7850 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 7851 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7852 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 7853 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7854 // CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 7855 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7856 // CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 7857 // CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 7858 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7859 // CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 7860 // CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 7861 // CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 7862 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 7863 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7864 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 7865 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7866 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 7867 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 7868 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7869 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 7870 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 7871 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 7872 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 7873 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 7874 // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7875 // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 7876 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 7877 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 7878 // CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 7879 // CHECK10-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 7880 // CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 7881 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 7882 // CHECK10-NEXT: ret void 7883 // 7884 // 7885 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 7886 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 7887 // CHECK10-NEXT: entry: 7888 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7889 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7890 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7891 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 7892 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7893 // CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 7894 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 7895 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7896 // CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 7897 // CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 7898 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 7899 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 7900 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7901 // CHECK10-NEXT: [[TMP:%.*]] = alloca i8, align 1 7902 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7903 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7904 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7905 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7906 // CHECK10-NEXT: [[IT:%.*]] = alloca i8, align 1 7907 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7908 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7909 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7910 // CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 7911 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7912 // CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 7913 // CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 7914 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7915 // CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 7916 // CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 7917 // CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 7918 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 7919 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7920 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 7921 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7922 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 7923 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 7924 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7925 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 7926 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 7927 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 7928 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 7929 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7930 // CHECK10-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 7931 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7932 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7933 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 7934 // CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7935 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 7936 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 7937 // CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 7938 // CHECK10: omp.dispatch.cond: 7939 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7940 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 7941 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7942 // CHECK10: cond.true: 7943 // CHECK10-NEXT: br label [[COND_END:%.*]] 7944 // CHECK10: cond.false: 7945 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7946 // CHECK10-NEXT: br label [[COND_END]] 7947 // CHECK10: cond.end: 7948 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 7949 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7950 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7951 // CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 7952 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7953 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7954 // CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 7955 // CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 7956 // CHECK10: omp.dispatch.body: 7957 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7958 // CHECK10: omp.inner.for.cond: 7959 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7960 // CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7961 // CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 7962 // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7963 // CHECK10: omp.inner.for.body: 7964 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7965 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 7966 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 7967 // CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 7968 // CHECK10-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 7969 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 7970 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 7971 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 7972 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 7973 // CHECK10-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 7974 // CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 7975 // CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 7976 // CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 7977 // CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 7978 // CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 7979 // CHECK10-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 7980 // CHECK10-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 7981 // CHECK10-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 7982 // CHECK10-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 7983 // CHECK10-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 7984 // CHECK10-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 7985 // CHECK10-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 7986 // CHECK10-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 7987 // CHECK10-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 7988 // CHECK10-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 7989 // CHECK10-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 7990 // CHECK10-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 7991 // CHECK10-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 7992 // CHECK10-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 7993 // CHECK10-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 7994 // CHECK10-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 7995 // CHECK10-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 7996 // CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 7997 // CHECK10-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 7998 // CHECK10-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 7999 // CHECK10-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 8000 // CHECK10-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 8001 // CHECK10-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 8002 // CHECK10-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 8003 // CHECK10-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 8004 // CHECK10-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 8005 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8006 // CHECK10: omp.body.continue: 8007 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8008 // CHECK10: omp.inner.for.inc: 8009 // CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8010 // CHECK10-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 8011 // CHECK10-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 8012 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 8013 // CHECK10: omp.inner.for.end: 8014 // CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 8015 // CHECK10: omp.dispatch.inc: 8016 // CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8017 // CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 8018 // CHECK10-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 8019 // CHECK10-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 8020 // CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8021 // CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 8022 // CHECK10-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 8023 // CHECK10-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 8024 // CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] 8025 // CHECK10: omp.dispatch.end: 8026 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 8027 // CHECK10-NEXT: ret void 8028 // 8029 // 8030 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 8031 // CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 8032 // CHECK10-NEXT: entry: 8033 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8034 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8035 // CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 8036 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 8037 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 8038 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 8039 // CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 8040 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8041 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8042 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 8043 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 8044 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8045 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8046 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 8047 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 8048 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 8049 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 8050 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 8051 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 8052 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 8053 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 8054 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 8055 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 8056 // CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 8057 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 8058 // CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 8059 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 8060 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 8061 // CHECK10-NEXT: ret void 8062 // 8063 // 8064 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 8065 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 8066 // CHECK10-NEXT: entry: 8067 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8068 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8069 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8070 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8071 // CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 8072 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 8073 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8074 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 8075 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8076 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8077 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8078 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8079 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 8080 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 8081 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8082 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8083 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 8084 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 8085 // CHECK10-NEXT: ret void 8086 // 8087 // 8088 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 8089 // CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 8090 // CHECK10-NEXT: entry: 8091 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 8092 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 8093 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 8094 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 8095 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 8096 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 8097 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 8098 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 8099 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 8100 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 8101 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 8102 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 8103 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 8104 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 8105 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 8106 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 8107 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 8108 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 8109 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 8110 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 8111 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 8112 // CHECK10-NEXT: ret void 8113 // 8114 // 8115 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 8116 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 8117 // CHECK10-NEXT: entry: 8118 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8119 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8120 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 8121 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 8122 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 8123 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 8124 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 8125 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8126 // CHECK10-NEXT: [[TMP:%.*]] = alloca i64, align 8 8127 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8128 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8129 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 8130 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8131 // CHECK10-NEXT: [[IT:%.*]] = alloca i64, align 8 8132 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8133 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8134 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 8135 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 8136 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 8137 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 8138 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 8139 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 8140 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 8141 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 8142 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 8143 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 8144 // CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8145 // CHECK10-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 8146 // CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 8147 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8148 // CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8149 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 8150 // CHECK10-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 8151 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8152 // CHECK10-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 8153 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8154 // CHECK10: cond.true: 8155 // CHECK10-NEXT: br label [[COND_END:%.*]] 8156 // CHECK10: cond.false: 8157 // CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8158 // CHECK10-NEXT: br label [[COND_END]] 8159 // CHECK10: cond.end: 8160 // CHECK10-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 8161 // CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 8162 // CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8163 // CHECK10-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 8164 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8165 // CHECK10: omp.inner.for.cond: 8166 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8167 // CHECK10-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8168 // CHECK10-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 8169 // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8170 // CHECK10: omp.inner.for.body: 8171 // CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8172 // CHECK10-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 8173 // CHECK10-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 8174 // CHECK10-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 8175 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 8176 // CHECK10-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 8177 // CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 8178 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 8179 // CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 8180 // CHECK10-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 8181 // CHECK10-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 8182 // CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 8183 // CHECK10-NEXT: store double [[INC]], double* [[A5]], align 8 8184 // CHECK10-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 8185 // CHECK10-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 8186 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 8187 // CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 8188 // CHECK10-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 8189 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8190 // CHECK10: omp.body.continue: 8191 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8192 // CHECK10: omp.inner.for.inc: 8193 // CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8194 // CHECK10-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 8195 // CHECK10-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 8196 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 8197 // CHECK10: omp.inner.for.end: 8198 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8199 // CHECK10: omp.loop.exit: 8200 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 8201 // CHECK10-NEXT: ret void 8202 // 8203 // 8204 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 8205 // CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 8206 // CHECK10-NEXT: entry: 8207 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8208 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8209 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 8210 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 8211 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 8212 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8213 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8214 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 8215 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8216 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8217 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 8218 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 8219 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 8220 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 8221 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 8222 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 8223 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 8224 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 8225 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 8226 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 8227 // CHECK10-NEXT: ret void 8228 // 8229 // 8230 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 8231 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 8232 // CHECK10-NEXT: entry: 8233 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8234 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8235 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8236 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8237 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 8238 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8239 // CHECK10-NEXT: [[TMP:%.*]] = alloca i64, align 8 8240 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8241 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8242 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 8243 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8244 // CHECK10-NEXT: [[I:%.*]] = alloca i64, align 8 8245 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8246 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8247 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8248 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8249 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 8250 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8251 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8252 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 8253 // CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8254 // CHECK10-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 8255 // CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 8256 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8257 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8258 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 8259 // CHECK10-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 8260 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8261 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 8262 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8263 // CHECK10: cond.true: 8264 // CHECK10-NEXT: br label [[COND_END:%.*]] 8265 // CHECK10: cond.false: 8266 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8267 // CHECK10-NEXT: br label [[COND_END]] 8268 // CHECK10: cond.end: 8269 // CHECK10-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 8270 // CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 8271 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8272 // CHECK10-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 8273 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8274 // CHECK10: omp.inner.for.cond: 8275 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8276 // CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8277 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 8278 // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8279 // CHECK10: omp.inner.for.body: 8280 // CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8281 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 8282 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 8283 // CHECK10-NEXT: store i64 [[ADD]], i64* [[I]], align 8 8284 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 8285 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 8286 // CHECK10-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 8287 // CHECK10-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 8288 // CHECK10-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 8289 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 8290 // CHECK10-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 8291 // CHECK10-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 8292 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 8293 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 8294 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 8295 // CHECK10-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 8296 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8297 // CHECK10: omp.body.continue: 8298 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8299 // CHECK10: omp.inner.for.inc: 8300 // CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8301 // CHECK10-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 8302 // CHECK10-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 8303 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 8304 // CHECK10: omp.inner.for.end: 8305 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8306 // CHECK10: omp.loop.exit: 8307 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 8308 // CHECK10-NEXT: ret void 8309 // 8310 // 8311 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 8312 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 8313 // CHECK11-NEXT: entry: 8314 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 8315 // CHECK11-NEXT: ret void 8316 // 8317 // 8318 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 8319 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 8320 // CHECK11-NEXT: entry: 8321 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8322 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8323 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8324 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 8325 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8326 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8327 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8328 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8329 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 8330 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8331 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8332 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8333 // CHECK11-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 8334 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8335 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8336 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 8337 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 8338 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 8339 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8340 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 8341 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8342 // CHECK11: cond.true: 8343 // CHECK11-NEXT: br label [[COND_END:%.*]] 8344 // CHECK11: cond.false: 8345 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8346 // CHECK11-NEXT: br label [[COND_END]] 8347 // CHECK11: cond.end: 8348 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 8349 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8350 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8351 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 8352 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8353 // CHECK11: omp.inner.for.cond: 8354 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8355 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8356 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 8357 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8358 // CHECK11: omp.inner.for.body: 8359 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8360 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 8361 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 8362 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 8363 // CHECK11-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 8364 // CHECK11-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 8365 // CHECK11-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 8366 // CHECK11: .cancel.exit: 8367 // CHECK11-NEXT: br label [[CANCEL_EXIT:%.*]] 8368 // CHECK11: .cancel.continue: 8369 // CHECK11-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 8370 // CHECK11-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 8371 // CHECK11-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 8372 // CHECK11: .cancel.exit2: 8373 // CHECK11-NEXT: br label [[CANCEL_EXIT]] 8374 // CHECK11: .cancel.continue3: 8375 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8376 // CHECK11: omp.body.continue: 8377 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8378 // CHECK11: omp.inner.for.inc: 8379 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8380 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 8381 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 8382 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 8383 // CHECK11: omp.inner.for.end: 8384 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8385 // CHECK11: omp.loop.exit: 8386 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 8387 // CHECK11-NEXT: br label [[CANCEL_CONT:%.*]] 8388 // CHECK11: cancel.cont: 8389 // CHECK11-NEXT: ret void 8390 // CHECK11: cancel.exit: 8391 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 8392 // CHECK11-NEXT: br label [[CANCEL_CONT]] 8393 // 8394 // 8395 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 8396 // CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 8397 // CHECK11-NEXT: entry: 8398 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8399 // CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 8400 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8401 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8402 // CHECK11-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 8403 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8404 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8405 // CHECK11-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 8406 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8407 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8408 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 8409 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8410 // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 8411 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8412 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 8413 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 8414 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 8415 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 8416 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 8417 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 8418 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 8419 // CHECK11-NEXT: ret void 8420 // 8421 // 8422 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 8423 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 8424 // CHECK11-NEXT: entry: 8425 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8426 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8427 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8428 // CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 8429 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8430 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8431 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 8432 // CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 8433 // CHECK11-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 8434 // CHECK11-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 8435 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8436 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8437 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 8438 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8439 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8 8440 // CHECK11-NEXT: [[LIN2:%.*]] = alloca i32, align 4 8441 // CHECK11-NEXT: [[A3:%.*]] = alloca i32, align 4 8442 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8443 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8444 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8445 // CHECK11-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 8446 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8447 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8448 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 8449 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 8450 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8451 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 8452 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 8453 // CHECK11-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 8454 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8455 // CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 8456 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 8457 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8458 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 8459 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 8460 // CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 8461 // CHECK11-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 8462 // CHECK11-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8463 // CHECK11-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 8464 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8465 // CHECK11: cond.true: 8466 // CHECK11-NEXT: br label [[COND_END:%.*]] 8467 // CHECK11: cond.false: 8468 // CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8469 // CHECK11-NEXT: br label [[COND_END]] 8470 // CHECK11: cond.end: 8471 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 8472 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 8473 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8474 // CHECK11-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 8475 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8476 // CHECK11: omp.inner.for.cond: 8477 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8478 // CHECK11-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8479 // CHECK11-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 8480 // CHECK11-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8481 // CHECK11: omp.inner.for.body: 8482 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8483 // CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 8484 // CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 8485 // CHECK11-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 8486 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 8487 // CHECK11-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 8488 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8489 // CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 8490 // CHECK11-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 8491 // CHECK11-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 8492 // CHECK11-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 8493 // CHECK11-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 8494 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 8495 // CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 8496 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8497 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 8498 // CHECK11-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 8499 // CHECK11-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 8500 // CHECK11-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 8501 // CHECK11-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 8502 // CHECK11-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 8503 // CHECK11-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 8504 // CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 8505 // CHECK11-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 8506 // CHECK11-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 8507 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8508 // CHECK11: omp.body.continue: 8509 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8510 // CHECK11: omp.inner.for.inc: 8511 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8512 // CHECK11-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 8513 // CHECK11-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 8514 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 8515 // CHECK11: omp.inner.for.end: 8516 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8517 // CHECK11: omp.loop.exit: 8518 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 8519 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 8520 // CHECK11-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 8521 // CHECK11-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 8522 // CHECK11: .omp.linear.pu: 8523 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 8524 // CHECK11-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 8525 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 8526 // CHECK11-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 8527 // CHECK11-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 8528 // CHECK11: .omp.linear.pu.done: 8529 // CHECK11-NEXT: ret void 8530 // 8531 // 8532 // CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv 8533 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 8534 // CHECK11-NEXT: entry: 8535 // CHECK11-NEXT: ret i64 0 8536 // 8537 // 8538 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 8539 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 8540 // CHECK11-NEXT: entry: 8541 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8542 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8543 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8544 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8545 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8546 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8547 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8548 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 8549 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 8550 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 8551 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 8552 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8553 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 8554 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8555 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 8556 // CHECK11-NEXT: ret void 8557 // 8558 // 8559 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 8560 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 8561 // CHECK11-NEXT: entry: 8562 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8563 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8564 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8565 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8566 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8567 // CHECK11-NEXT: [[TMP:%.*]] = alloca i16, align 2 8568 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8569 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8570 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8571 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8572 // CHECK11-NEXT: [[IT:%.*]] = alloca i16, align 2 8573 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8574 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8575 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8576 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8577 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8578 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8579 // CHECK11-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 8580 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8581 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8582 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 8583 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 8584 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 8585 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8586 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 8587 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8588 // CHECK11: cond.true: 8589 // CHECK11-NEXT: br label [[COND_END:%.*]] 8590 // CHECK11: cond.false: 8591 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8592 // CHECK11-NEXT: br label [[COND_END]] 8593 // CHECK11: cond.end: 8594 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 8595 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8596 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8597 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 8598 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8599 // CHECK11: omp.inner.for.cond: 8600 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8601 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8602 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 8603 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8604 // CHECK11: omp.inner.for.body: 8605 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8606 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 8607 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 8608 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 8609 // CHECK11-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 8610 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 8611 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 8612 // CHECK11-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 8613 // CHECK11-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 8614 // CHECK11-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 8615 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 8616 // CHECK11-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 8617 // CHECK11-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 8618 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8619 // CHECK11: omp.body.continue: 8620 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8621 // CHECK11: omp.inner.for.inc: 8622 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8623 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 8624 // CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 8625 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 8626 // CHECK11: omp.inner.for.end: 8627 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8628 // CHECK11: omp.loop.exit: 8629 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 8630 // CHECK11-NEXT: ret void 8631 // 8632 // 8633 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 8634 // CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 8635 // CHECK11-NEXT: entry: 8636 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8637 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 8638 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8639 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 8640 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 8641 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8642 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 8643 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 8644 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 8645 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 8646 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8647 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 8648 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8649 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 8650 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8651 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 8652 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 8653 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8654 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 8655 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 8656 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 8657 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 8658 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 8659 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8660 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 8661 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 8662 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8663 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 8664 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 8665 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 8666 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 8667 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 8668 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 8669 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 8670 // CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 8671 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 8672 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 8673 // CHECK11-NEXT: ret void 8674 // 8675 // 8676 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 8677 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 8678 // CHECK11-NEXT: entry: 8679 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8680 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8681 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8682 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 8683 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8684 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 8685 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 8686 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8687 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 8688 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 8689 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 8690 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 8691 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8692 // CHECK11-NEXT: [[TMP:%.*]] = alloca i8, align 1 8693 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8694 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8695 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8696 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8697 // CHECK11-NEXT: [[IT:%.*]] = alloca i8, align 1 8698 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8699 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8700 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8701 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 8702 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8703 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 8704 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 8705 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8706 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 8707 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 8708 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 8709 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 8710 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 8711 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8712 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 8713 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 8714 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8715 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 8716 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 8717 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 8718 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8719 // CHECK11-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 8720 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8721 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8722 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 8723 // CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 8724 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 8725 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 8726 // CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 8727 // CHECK11: omp.dispatch.cond: 8728 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8729 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 8730 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8731 // CHECK11: cond.true: 8732 // CHECK11-NEXT: br label [[COND_END:%.*]] 8733 // CHECK11: cond.false: 8734 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8735 // CHECK11-NEXT: br label [[COND_END]] 8736 // CHECK11: cond.end: 8737 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 8738 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8739 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8740 // CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 8741 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8742 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8743 // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 8744 // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 8745 // CHECK11: omp.dispatch.body: 8746 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8747 // CHECK11: omp.inner.for.cond: 8748 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8749 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8750 // CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 8751 // CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8752 // CHECK11: omp.inner.for.body: 8753 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8754 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 8755 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 8756 // CHECK11-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 8757 // CHECK11-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 8758 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 8759 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 8760 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 8761 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 8762 // CHECK11-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 8763 // CHECK11-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 8764 // CHECK11-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 8765 // CHECK11-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 8766 // CHECK11-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 8767 // CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 8768 // CHECK11-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 8769 // CHECK11-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 8770 // CHECK11-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 8771 // CHECK11-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 8772 // CHECK11-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 8773 // CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 8774 // CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 8775 // CHECK11-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 8776 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 8777 // CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 8778 // CHECK11-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 8779 // CHECK11-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 8780 // CHECK11-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 8781 // CHECK11-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 8782 // CHECK11-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 8783 // CHECK11-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 8784 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 8785 // CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 8786 // CHECK11-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 8787 // CHECK11-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 8788 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 8789 // CHECK11-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 8790 // CHECK11-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 8791 // CHECK11-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 8792 // CHECK11-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 8793 // CHECK11-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 8794 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8795 // CHECK11: omp.body.continue: 8796 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8797 // CHECK11: omp.inner.for.inc: 8798 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8799 // CHECK11-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 8800 // CHECK11-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 8801 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 8802 // CHECK11: omp.inner.for.end: 8803 // CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 8804 // CHECK11: omp.dispatch.inc: 8805 // CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8806 // CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 8807 // CHECK11-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 8808 // CHECK11-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 8809 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8810 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 8811 // CHECK11-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 8812 // CHECK11-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 8813 // CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] 8814 // CHECK11: omp.dispatch.end: 8815 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 8816 // CHECK11-NEXT: ret void 8817 // 8818 // 8819 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 8820 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 8821 // CHECK11-NEXT: entry: 8822 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8823 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8824 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 8825 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8826 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8827 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8828 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 8829 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8830 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8831 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 8832 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8833 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8834 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 8835 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8836 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8837 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 8838 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 8839 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 8840 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8841 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 8842 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8843 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 8844 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 8845 // CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 8846 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 8847 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 8848 // CHECK11-NEXT: ret void 8849 // 8850 // 8851 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 8852 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 8853 // CHECK11-NEXT: entry: 8854 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8855 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8856 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8857 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8858 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 8859 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8860 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8861 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 8862 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8863 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8864 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8865 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8866 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 8867 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8868 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8869 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 8870 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8871 // CHECK11-NEXT: ret void 8872 // 8873 // 8874 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 8875 // CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 8876 // CHECK11-NEXT: entry: 8877 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8878 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 8879 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8880 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8881 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 8882 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 8883 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8884 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 8885 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8886 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8887 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 8888 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 8889 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8890 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8891 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 8892 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 8893 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 8894 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 8895 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 8896 // CHECK11-NEXT: ret void 8897 // 8898 // 8899 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 8900 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 8901 // CHECK11-NEXT: entry: 8902 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8903 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8904 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8905 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 8906 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8907 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8908 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 8909 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8910 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 8911 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8912 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8913 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 8914 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8915 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8 8916 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8917 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8918 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8919 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 8920 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8921 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8922 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 8923 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 8924 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8925 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8926 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 8927 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8928 // CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 8929 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 8930 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8931 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 8932 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 8933 // CHECK11-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 8934 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8935 // CHECK11-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 8936 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8937 // CHECK11: cond.true: 8938 // CHECK11-NEXT: br label [[COND_END:%.*]] 8939 // CHECK11: cond.false: 8940 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8941 // CHECK11-NEXT: br label [[COND_END]] 8942 // CHECK11: cond.end: 8943 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 8944 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 8945 // CHECK11-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8946 // CHECK11-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 8947 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8948 // CHECK11: omp.inner.for.cond: 8949 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8950 // CHECK11-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8951 // CHECK11-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 8952 // CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8953 // CHECK11: omp.inner.for.body: 8954 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8955 // CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 8956 // CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 8957 // CHECK11-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 8958 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 8959 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 8960 // CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 8961 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 8962 // CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4 8963 // CHECK11-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 8964 // CHECK11-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 8965 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 8966 // CHECK11-NEXT: store double [[INC]], double* [[A4]], align 4 8967 // CHECK11-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 8968 // CHECK11-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 8969 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 8970 // CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 8971 // CHECK11-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 8972 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8973 // CHECK11: omp.body.continue: 8974 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8975 // CHECK11: omp.inner.for.inc: 8976 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8977 // CHECK11-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 8978 // CHECK11-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 8979 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 8980 // CHECK11: omp.inner.for.end: 8981 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8982 // CHECK11: omp.loop.exit: 8983 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 8984 // CHECK11-NEXT: ret void 8985 // 8986 // 8987 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 8988 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 8989 // CHECK11-NEXT: entry: 8990 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8991 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8992 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8993 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8994 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8995 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8996 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8997 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8998 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8999 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9000 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 9001 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 9002 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 9003 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 9004 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9005 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 9006 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9007 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 9008 // CHECK11-NEXT: ret void 9009 // 9010 // 9011 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 9012 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 9013 // CHECK11-NEXT: entry: 9014 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9015 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9016 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9017 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9018 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9019 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9020 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 9021 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9022 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9023 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9024 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9025 // CHECK11-NEXT: [[I:%.*]] = alloca i64, align 8 9026 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9027 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9028 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9029 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9030 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9031 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9032 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9033 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 9034 // CHECK11-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 9035 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 9036 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9037 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9038 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 9039 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 9040 // CHECK11-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9041 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 9042 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9043 // CHECK11: cond.true: 9044 // CHECK11-NEXT: br label [[COND_END:%.*]] 9045 // CHECK11: cond.false: 9046 // CHECK11-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9047 // CHECK11-NEXT: br label [[COND_END]] 9048 // CHECK11: cond.end: 9049 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 9050 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 9051 // CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 9052 // CHECK11-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 9053 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9054 // CHECK11: omp.inner.for.cond: 9055 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9056 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9057 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 9058 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9059 // CHECK11: omp.inner.for.body: 9060 // CHECK11-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9061 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 9062 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 9063 // CHECK11-NEXT: store i64 [[ADD]], i64* [[I]], align 8 9064 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 9065 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 9066 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 9067 // CHECK11-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 9068 // CHECK11-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 9069 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 9070 // CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 9071 // CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 9072 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 9073 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 9074 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 9075 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 9076 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9077 // CHECK11: omp.body.continue: 9078 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9079 // CHECK11: omp.inner.for.inc: 9080 // CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9081 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 9082 // CHECK11-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 9083 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 9084 // CHECK11: omp.inner.for.end: 9085 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9086 // CHECK11: omp.loop.exit: 9087 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 9088 // CHECK11-NEXT: ret void 9089 // 9090 // 9091 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 9092 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 9093 // CHECK12-NEXT: entry: 9094 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 9095 // CHECK12-NEXT: ret void 9096 // 9097 // 9098 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 9099 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 9100 // CHECK12-NEXT: entry: 9101 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9102 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9103 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9104 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 9105 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9106 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9107 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9108 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9109 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 9110 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9111 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9112 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9113 // CHECK12-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 9114 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9115 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9116 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9117 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 9118 // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9119 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9120 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 9121 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9122 // CHECK12: cond.true: 9123 // CHECK12-NEXT: br label [[COND_END:%.*]] 9124 // CHECK12: cond.false: 9125 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9126 // CHECK12-NEXT: br label [[COND_END]] 9127 // CHECK12: cond.end: 9128 // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9129 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9130 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9131 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 9132 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9133 // CHECK12: omp.inner.for.cond: 9134 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9135 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9136 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9137 // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9138 // CHECK12: omp.inner.for.body: 9139 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9140 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 9141 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 9142 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 9143 // CHECK12-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 9144 // CHECK12-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 9145 // CHECK12-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 9146 // CHECK12: .cancel.exit: 9147 // CHECK12-NEXT: br label [[CANCEL_EXIT:%.*]] 9148 // CHECK12: .cancel.continue: 9149 // CHECK12-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 9150 // CHECK12-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 9151 // CHECK12-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 9152 // CHECK12: .cancel.exit2: 9153 // CHECK12-NEXT: br label [[CANCEL_EXIT]] 9154 // CHECK12: .cancel.continue3: 9155 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9156 // CHECK12: omp.body.continue: 9157 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9158 // CHECK12: omp.inner.for.inc: 9159 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9160 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 9161 // CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 9162 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 9163 // CHECK12: omp.inner.for.end: 9164 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9165 // CHECK12: omp.loop.exit: 9166 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 9167 // CHECK12-NEXT: br label [[CANCEL_CONT:%.*]] 9168 // CHECK12: cancel.cont: 9169 // CHECK12-NEXT: ret void 9170 // CHECK12: cancel.exit: 9171 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 9172 // CHECK12-NEXT: br label [[CANCEL_CONT]] 9173 // 9174 // 9175 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 9176 // CHECK12-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 9177 // CHECK12-NEXT: entry: 9178 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9179 // CHECK12-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 9180 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9181 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9182 // CHECK12-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 9183 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9184 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9185 // CHECK12-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 9186 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9187 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9188 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 9189 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9190 // CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 9191 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9192 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 9193 // CHECK12-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 9194 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 9195 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 9196 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 9197 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 9198 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 9199 // CHECK12-NEXT: ret void 9200 // 9201 // 9202 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 9203 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 9204 // CHECK12-NEXT: entry: 9205 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9206 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9207 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9208 // CHECK12-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 9209 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9210 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9211 // CHECK12-NEXT: [[TMP:%.*]] = alloca i64, align 4 9212 // CHECK12-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 9213 // CHECK12-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 9214 // CHECK12-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 9215 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9216 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9217 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9218 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9219 // CHECK12-NEXT: [[IT:%.*]] = alloca i64, align 8 9220 // CHECK12-NEXT: [[LIN2:%.*]] = alloca i32, align 4 9221 // CHECK12-NEXT: [[A3:%.*]] = alloca i32, align 4 9222 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9223 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9224 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9225 // CHECK12-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 9226 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9227 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9228 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 9229 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 9230 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 9231 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 9232 // CHECK12-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 9233 // CHECK12-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 9234 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 9235 // CHECK12-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 9236 // CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 9237 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9238 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9239 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 9240 // CHECK12-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 9241 // CHECK12-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 9242 // CHECK12-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9243 // CHECK12-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 9244 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9245 // CHECK12: cond.true: 9246 // CHECK12-NEXT: br label [[COND_END:%.*]] 9247 // CHECK12: cond.false: 9248 // CHECK12-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9249 // CHECK12-NEXT: br label [[COND_END]] 9250 // CHECK12: cond.end: 9251 // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 9252 // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 9253 // CHECK12-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 9254 // CHECK12-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 9255 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9256 // CHECK12: omp.inner.for.cond: 9257 // CHECK12-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9258 // CHECK12-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9259 // CHECK12-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 9260 // CHECK12-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9261 // CHECK12: omp.inner.for.body: 9262 // CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9263 // CHECK12-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 9264 // CHECK12-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 9265 // CHECK12-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 9266 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 9267 // CHECK12-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 9268 // CHECK12-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9269 // CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 9270 // CHECK12-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 9271 // CHECK12-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 9272 // CHECK12-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 9273 // CHECK12-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 9274 // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 9275 // CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 9276 // CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9277 // CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 9278 // CHECK12-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 9279 // CHECK12-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 9280 // CHECK12-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 9281 // CHECK12-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 9282 // CHECK12-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 9283 // CHECK12-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 9284 // CHECK12-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 9285 // CHECK12-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 9286 // CHECK12-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 9287 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9288 // CHECK12: omp.body.continue: 9289 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9290 // CHECK12: omp.inner.for.inc: 9291 // CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9292 // CHECK12-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 9293 // CHECK12-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 9294 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 9295 // CHECK12: omp.inner.for.end: 9296 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9297 // CHECK12: omp.loop.exit: 9298 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 9299 // CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9300 // CHECK12-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 9301 // CHECK12-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 9302 // CHECK12: .omp.linear.pu: 9303 // CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 9304 // CHECK12-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 9305 // CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 9306 // CHECK12-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 9307 // CHECK12-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 9308 // CHECK12: .omp.linear.pu.done: 9309 // CHECK12-NEXT: ret void 9310 // 9311 // 9312 // CHECK12-LABEL: define {{[^@]+}}@_Z7get_valv 9313 // CHECK12-SAME: () #[[ATTR3:[0-9]+]] { 9314 // CHECK12-NEXT: entry: 9315 // CHECK12-NEXT: ret i64 0 9316 // 9317 // 9318 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 9319 // CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 9320 // CHECK12-NEXT: entry: 9321 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9322 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9323 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9324 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9325 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9326 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9327 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9328 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 9329 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 9330 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 9331 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 9332 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9333 // CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 9334 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9335 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 9336 // CHECK12-NEXT: ret void 9337 // 9338 // 9339 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 9340 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 9341 // CHECK12-NEXT: entry: 9342 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9343 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9344 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9345 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9346 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9347 // CHECK12-NEXT: [[TMP:%.*]] = alloca i16, align 2 9348 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9349 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9350 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9351 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9352 // CHECK12-NEXT: [[IT:%.*]] = alloca i16, align 2 9353 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9354 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9355 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9356 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9357 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9358 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9359 // CHECK12-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 9360 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9361 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9362 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9363 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 9364 // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9365 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9366 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 9367 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9368 // CHECK12: cond.true: 9369 // CHECK12-NEXT: br label [[COND_END:%.*]] 9370 // CHECK12: cond.false: 9371 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9372 // CHECK12-NEXT: br label [[COND_END]] 9373 // CHECK12: cond.end: 9374 // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9375 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9376 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9377 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 9378 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9379 // CHECK12: omp.inner.for.cond: 9380 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9381 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9382 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9383 // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9384 // CHECK12: omp.inner.for.body: 9385 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9386 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 9387 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 9388 // CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 9389 // CHECK12-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 9390 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 9391 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 9392 // CHECK12-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 9393 // CHECK12-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 9394 // CHECK12-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 9395 // CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 9396 // CHECK12-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 9397 // CHECK12-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 9398 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9399 // CHECK12: omp.body.continue: 9400 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9401 // CHECK12: omp.inner.for.inc: 9402 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9403 // CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 9404 // CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 9405 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 9406 // CHECK12: omp.inner.for.end: 9407 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9408 // CHECK12: omp.loop.exit: 9409 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 9410 // CHECK12-NEXT: ret void 9411 // 9412 // 9413 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 9414 // CHECK12-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 9415 // CHECK12-NEXT: entry: 9416 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9417 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 9418 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9419 // CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 9420 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 9421 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9422 // CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 9423 // CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 9424 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 9425 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 9426 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9427 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 9428 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9429 // CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 9430 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9431 // CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 9432 // CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 9433 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9434 // CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 9435 // CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 9436 // CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 9437 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 9438 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 9439 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9440 // CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 9441 // CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 9442 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9443 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 9444 // CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 9445 // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 9446 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 9447 // CHECK12-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 9448 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 9449 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 9450 // CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 9451 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 9452 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 9453 // CHECK12-NEXT: ret void 9454 // 9455 // 9456 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 9457 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 9458 // CHECK12-NEXT: entry: 9459 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9460 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9461 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9462 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 9463 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9464 // CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 9465 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 9466 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9467 // CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 9468 // CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 9469 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 9470 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 9471 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9472 // CHECK12-NEXT: [[TMP:%.*]] = alloca i8, align 1 9473 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9474 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9475 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9476 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9477 // CHECK12-NEXT: [[IT:%.*]] = alloca i8, align 1 9478 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9479 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9480 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9481 // CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 9482 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9483 // CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 9484 // CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 9485 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9486 // CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 9487 // CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 9488 // CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 9489 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 9490 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 9491 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9492 // CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 9493 // CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 9494 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9495 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 9496 // CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 9497 // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 9498 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9499 // CHECK12-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 9500 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9501 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9502 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 9503 // CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9504 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 9505 // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 9506 // CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 9507 // CHECK12: omp.dispatch.cond: 9508 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9509 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 9510 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9511 // CHECK12: cond.true: 9512 // CHECK12-NEXT: br label [[COND_END:%.*]] 9513 // CHECK12: cond.false: 9514 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9515 // CHECK12-NEXT: br label [[COND_END]] 9516 // CHECK12: cond.end: 9517 // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 9518 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9519 // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9520 // CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 9521 // CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9522 // CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9523 // CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 9524 // CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 9525 // CHECK12: omp.dispatch.body: 9526 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9527 // CHECK12: omp.inner.for.cond: 9528 // CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9529 // CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9530 // CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 9531 // CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9532 // CHECK12: omp.inner.for.body: 9533 // CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9534 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 9535 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 9536 // CHECK12-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 9537 // CHECK12-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 9538 // CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 9539 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 9540 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 9541 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 9542 // CHECK12-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 9543 // CHECK12-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 9544 // CHECK12-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 9545 // CHECK12-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 9546 // CHECK12-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 9547 // CHECK12-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 9548 // CHECK12-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 9549 // CHECK12-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 9550 // CHECK12-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 9551 // CHECK12-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 9552 // CHECK12-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 9553 // CHECK12-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 9554 // CHECK12-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 9555 // CHECK12-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 9556 // CHECK12-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 9557 // CHECK12-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 9558 // CHECK12-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 9559 // CHECK12-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 9560 // CHECK12-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 9561 // CHECK12-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 9562 // CHECK12-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 9563 // CHECK12-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 9564 // CHECK12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 9565 // CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 9566 // CHECK12-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 9567 // CHECK12-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 9568 // CHECK12-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 9569 // CHECK12-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 9570 // CHECK12-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 9571 // CHECK12-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 9572 // CHECK12-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 9573 // CHECK12-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 9574 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9575 // CHECK12: omp.body.continue: 9576 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9577 // CHECK12: omp.inner.for.inc: 9578 // CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9579 // CHECK12-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 9580 // CHECK12-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 9581 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 9582 // CHECK12: omp.inner.for.end: 9583 // CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 9584 // CHECK12: omp.dispatch.inc: 9585 // CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9586 // CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 9587 // CHECK12-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 9588 // CHECK12-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 9589 // CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9590 // CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 9591 // CHECK12-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 9592 // CHECK12-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 9593 // CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] 9594 // CHECK12: omp.dispatch.end: 9595 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 9596 // CHECK12-NEXT: ret void 9597 // 9598 // 9599 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 9600 // CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 9601 // CHECK12-NEXT: entry: 9602 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9603 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9604 // CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 9605 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9606 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9607 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9608 // CHECK12-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 9609 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9610 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9611 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 9612 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9613 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9614 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 9615 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9616 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 9617 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 9618 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 9619 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 9620 // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9621 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 9622 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9623 // CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 9624 // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 9625 // CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 9626 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 9627 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 9628 // CHECK12-NEXT: ret void 9629 // 9630 // 9631 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 9632 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 9633 // CHECK12-NEXT: entry: 9634 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9635 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9636 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9637 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9638 // CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 9639 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9640 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9641 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 9642 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9643 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9644 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9645 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9646 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 9647 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9648 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9649 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 9650 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9651 // CHECK12-NEXT: ret void 9652 // 9653 // 9654 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 9655 // CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 9656 // CHECK12-NEXT: entry: 9657 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 9658 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 9659 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9660 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9661 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 9662 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 9663 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 9664 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 9665 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9666 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9667 // CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 9668 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 9669 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9670 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9671 // CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 9672 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 9673 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 9674 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 9675 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 9676 // CHECK12-NEXT: ret void 9677 // 9678 // 9679 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 9680 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 9681 // CHECK12-NEXT: entry: 9682 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9683 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9684 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 9685 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 9686 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9687 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9688 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 9689 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9690 // CHECK12-NEXT: [[TMP:%.*]] = alloca i64, align 4 9691 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9692 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9693 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9694 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9695 // CHECK12-NEXT: [[IT:%.*]] = alloca i64, align 8 9696 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9697 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9698 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 9699 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 9700 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9701 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9702 // CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 9703 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 9704 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9705 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9706 // CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 9707 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 9708 // CHECK12-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 9709 // CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 9710 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9711 // CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9712 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 9713 // CHECK12-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 9714 // CHECK12-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9715 // CHECK12-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 9716 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9717 // CHECK12: cond.true: 9718 // CHECK12-NEXT: br label [[COND_END:%.*]] 9719 // CHECK12: cond.false: 9720 // CHECK12-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9721 // CHECK12-NEXT: br label [[COND_END]] 9722 // CHECK12: cond.end: 9723 // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 9724 // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 9725 // CHECK12-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 9726 // CHECK12-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 9727 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9728 // CHECK12: omp.inner.for.cond: 9729 // CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9730 // CHECK12-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9731 // CHECK12-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 9732 // CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9733 // CHECK12: omp.inner.for.body: 9734 // CHECK12-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9735 // CHECK12-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 9736 // CHECK12-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 9737 // CHECK12-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 9738 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 9739 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 9740 // CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 9741 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 9742 // CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4 9743 // CHECK12-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 9744 // CHECK12-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 9745 // CHECK12-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 9746 // CHECK12-NEXT: store double [[INC]], double* [[A4]], align 4 9747 // CHECK12-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 9748 // CHECK12-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 9749 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 9750 // CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 9751 // CHECK12-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 9752 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9753 // CHECK12: omp.body.continue: 9754 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9755 // CHECK12: omp.inner.for.inc: 9756 // CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9757 // CHECK12-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 9758 // CHECK12-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 9759 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 9760 // CHECK12: omp.inner.for.end: 9761 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9762 // CHECK12: omp.loop.exit: 9763 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 9764 // CHECK12-NEXT: ret void 9765 // 9766 // 9767 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 9768 // CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 9769 // CHECK12-NEXT: entry: 9770 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9771 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9772 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9773 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9774 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9775 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9776 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9777 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9778 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9779 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9780 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 9781 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 9782 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 9783 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 9784 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9785 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 9786 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9787 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 9788 // CHECK12-NEXT: ret void 9789 // 9790 // 9791 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 9792 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 9793 // CHECK12-NEXT: entry: 9794 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9795 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9796 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9797 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9798 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9799 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9800 // CHECK12-NEXT: [[TMP:%.*]] = alloca i64, align 4 9801 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9802 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9803 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9804 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9805 // CHECK12-NEXT: [[I:%.*]] = alloca i64, align 8 9806 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9807 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9808 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9809 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9810 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9811 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9812 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9813 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 9814 // CHECK12-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 9815 // CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 9816 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9817 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9818 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 9819 // CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 9820 // CHECK12-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9821 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 9822 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9823 // CHECK12: cond.true: 9824 // CHECK12-NEXT: br label [[COND_END:%.*]] 9825 // CHECK12: cond.false: 9826 // CHECK12-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9827 // CHECK12-NEXT: br label [[COND_END]] 9828 // CHECK12: cond.end: 9829 // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 9830 // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 9831 // CHECK12-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 9832 // CHECK12-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 9833 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9834 // CHECK12: omp.inner.for.cond: 9835 // CHECK12-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9836 // CHECK12-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9837 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 9838 // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9839 // CHECK12: omp.inner.for.body: 9840 // CHECK12-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9841 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 9842 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 9843 // CHECK12-NEXT: store i64 [[ADD]], i64* [[I]], align 8 9844 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 9845 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 9846 // CHECK12-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 9847 // CHECK12-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 9848 // CHECK12-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 9849 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 9850 // CHECK12-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 9851 // CHECK12-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 9852 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 9853 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 9854 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 9855 // CHECK12-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 9856 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9857 // CHECK12: omp.body.continue: 9858 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9859 // CHECK12: omp.inner.for.inc: 9860 // CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9861 // CHECK12-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 9862 // CHECK12-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 9863 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 9864 // CHECK12: omp.inner.for.end: 9865 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9866 // CHECK12: omp.loop.exit: 9867 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 9868 // CHECK12-NEXT: ret void 9869 // 9870 // 9871 // CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv 9872 // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { 9873 // CHECK17-NEXT: entry: 9874 // CHECK17-NEXT: ret i64 0 9875 // 9876 // 9877 // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi 9878 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 9879 // CHECK17-NEXT: entry: 9880 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9881 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 9882 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 9883 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 4 9884 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 9885 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 9886 // CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 9887 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 9888 // CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 9889 // CHECK17-NEXT: [[K:%.*]] = alloca i64, align 8 9890 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9891 // CHECK17-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 9892 // CHECK17-NEXT: [[LIN:%.*]] = alloca i32, align 4 9893 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9894 // CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 9895 // CHECK17-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8 9896 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 9897 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 9898 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 9899 // CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 9900 // CHECK17-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8 9901 // CHECK17-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8 9902 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 9903 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 9904 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 9905 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 9906 // CHECK17-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8 9907 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 9908 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8 9909 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8 9910 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8 9911 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 9912 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 9913 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9914 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 9915 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 9916 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 9917 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 9918 // CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 9919 // CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 9920 // CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 9921 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 9922 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 9923 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 9924 // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 9925 // CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 9926 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 9927 // CHECK17-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 9928 // CHECK17-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 9929 // CHECK17-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 9930 // CHECK17: omp_offload.failed: 9931 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 9932 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 9933 // CHECK17: omp_offload.cont: 9934 // CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 9935 // CHECK17-NEXT: store i64 [[CALL]], i64* [[K]], align 8 9936 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 9937 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9938 // CHECK17-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4 9939 // CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8 9940 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[K]], align 8 9941 // CHECK17-NEXT: store i64 [[TMP11]], i64* [[K_CASTED]], align 8 9942 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8 9943 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR4]] 9944 // CHECK17-NEXT: store i32 12, i32* [[LIN]], align 4 9945 // CHECK17-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 9946 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9947 // CHECK17-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 9948 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9949 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4 9950 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 9951 // CHECK17-NEXT: store i32 [[TMP15]], i32* [[CONV3]], align 4 9952 // CHECK17-NEXT: [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 9953 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 9954 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32* 9955 // CHECK17-NEXT: store i32 [[TMP17]], i32* [[CONV5]], align 4 9956 // CHECK17-NEXT: [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8 9957 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9958 // CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 9959 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP20]], align 8 9960 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9961 // CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 9962 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP22]], align 8 9963 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 9964 // CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8 9965 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 9966 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 9967 // CHECK17-NEXT: store i64 [[TMP16]], i64* [[TMP25]], align 8 9968 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 9969 // CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 9970 // CHECK17-NEXT: store i64 [[TMP16]], i64* [[TMP27]], align 8 9971 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 9972 // CHECK17-NEXT: store i8* null, i8** [[TMP28]], align 8 9973 // CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 9974 // CHECK17-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 9975 // CHECK17-NEXT: store i64 [[TMP18]], i64* [[TMP30]], align 8 9976 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 9977 // CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 9978 // CHECK17-NEXT: store i64 [[TMP18]], i64* [[TMP32]], align 8 9979 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 9980 // CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 9981 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9982 // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9983 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 9984 // CHECK17-NEXT: [[TMP37:%.*]] = load i16, i16* [[AA]], align 2 9985 // CHECK17-NEXT: store i16 [[TMP37]], i16* [[TMP36]], align 4 9986 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 9987 // CHECK17-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4 9988 // CHECK17-NEXT: store i32 [[TMP39]], i32* [[TMP38]], align 4 9989 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 9990 // CHECK17-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 9991 // CHECK17-NEXT: store i32 [[TMP41]], i32* [[TMP40]], align 4 9992 // CHECK17-NEXT: [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 9993 // CHECK17-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates* 9994 // CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0 9995 // CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0 9996 // CHECK17-NEXT: [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8 9997 // CHECK17-NEXT: [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 9998 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false) 9999 // CHECK17-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1 10000 // CHECK17-NEXT: [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon* 10001 // CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0 10002 // CHECK17-NEXT: [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8* 10003 // CHECK17-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8* 10004 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false) 10005 // CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1 10006 // CHECK17-NEXT: [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8* 10007 // CHECK17-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8* 10008 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false) 10009 // CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2 10010 // CHECK17-NEXT: [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8* 10011 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 10012 // CHECK17-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3 10013 // CHECK17-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 10014 // CHECK17-NEXT: store i16 [[TMP59]], i16* [[TMP58]], align 8 10015 // CHECK17-NEXT: [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]]) 10016 // CHECK17-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4 10017 // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32* 10018 // CHECK17-NEXT: store i32 [[TMP61]], i32* [[CONV7]], align 4 10019 // CHECK17-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8 10020 // CHECK17-NEXT: [[TMP63:%.*]] = load i16, i16* [[AA]], align 2 10021 // CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16* 10022 // CHECK17-NEXT: store i16 [[TMP63]], i16* [[CONV9]], align 2 10023 // CHECK17-NEXT: [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8 10024 // CHECK17-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4 10025 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10 10026 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 10027 // CHECK17: omp_if.then: 10028 // CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 10029 // CHECK17-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64* 10030 // CHECK17-NEXT: store i64 [[TMP62]], i64* [[TMP67]], align 8 10031 // CHECK17-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 10032 // CHECK17-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* 10033 // CHECK17-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8 10034 // CHECK17-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 10035 // CHECK17-NEXT: store i8* null, i8** [[TMP70]], align 8 10036 // CHECK17-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 10037 // CHECK17-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* 10038 // CHECK17-NEXT: store i64 [[TMP64]], i64* [[TMP72]], align 8 10039 // CHECK17-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 10040 // CHECK17-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* 10041 // CHECK17-NEXT: store i64 [[TMP64]], i64* [[TMP74]], align 8 10042 // CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 10043 // CHECK17-NEXT: store i8* null, i8** [[TMP75]], align 8 10044 // CHECK17-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 10045 // CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 10046 // CHECK17-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 10047 // CHECK17-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0 10048 // CHECK17-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]] 10049 // CHECK17: omp_offload.failed13: 10050 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 10051 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT14]] 10052 // CHECK17: omp_offload.cont14: 10053 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 10054 // CHECK17: omp_if.else: 10055 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 10056 // CHECK17-NEXT: br label [[OMP_IF_END]] 10057 // CHECK17: omp_if.end: 10058 // CHECK17-NEXT: [[TMP80:%.*]] = load i32, i32* [[A]], align 4 10059 // CHECK17-NEXT: store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4 10060 // CHECK17-NEXT: [[TMP81:%.*]] = load i32, i32* [[A]], align 4 10061 // CHECK17-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32* 10062 // CHECK17-NEXT: store i32 [[TMP81]], i32* [[CONV16]], align 4 10063 // CHECK17-NEXT: [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8 10064 // CHECK17-NEXT: [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 10065 // CHECK17-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 10066 // CHECK17-NEXT: store i32 [[TMP83]], i32* [[CONV17]], align 4 10067 // CHECK17-NEXT: [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 10068 // CHECK17-NEXT: [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4 10069 // CHECK17-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20 10070 // CHECK17-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 10071 // CHECK17: omp_if.then19: 10072 // CHECK17-NEXT: [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4 10073 // CHECK17-NEXT: [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]] 10074 // CHECK17-NEXT: [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8 10075 // CHECK17-NEXT: [[TMP89:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 10076 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP89]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i64 80, i1 false) 10077 // CHECK17-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 10078 // CHECK17-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i64* 10079 // CHECK17-NEXT: store i64 [[TMP82]], i64* [[TMP91]], align 8 10080 // CHECK17-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 10081 // CHECK17-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to i64* 10082 // CHECK17-NEXT: store i64 [[TMP82]], i64* [[TMP93]], align 8 10083 // CHECK17-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 10084 // CHECK17-NEXT: store i8* null, i8** [[TMP94]], align 8 10085 // CHECK17-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 10086 // CHECK17-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 10087 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8 10088 // CHECK17-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 10089 // CHECK17-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]** 10090 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8 10091 // CHECK17-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 10092 // CHECK17-NEXT: store i8* null, i8** [[TMP99]], align 8 10093 // CHECK17-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 10094 // CHECK17-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64* 10095 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP101]], align 8 10096 // CHECK17-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 10097 // CHECK17-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i64* 10098 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP103]], align 8 10099 // CHECK17-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 10100 // CHECK17-NEXT: store i8* null, i8** [[TMP104]], align 8 10101 // CHECK17-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 10102 // CHECK17-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** 10103 // CHECK17-NEXT: store float* [[VLA]], float** [[TMP106]], align 8 10104 // CHECK17-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 10105 // CHECK17-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** 10106 // CHECK17-NEXT: store float* [[VLA]], float** [[TMP108]], align 8 10107 // CHECK17-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 10108 // CHECK17-NEXT: store i64 [[TMP86]], i64* [[TMP109]], align 8 10109 // CHECK17-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 10110 // CHECK17-NEXT: store i8* null, i8** [[TMP110]], align 8 10111 // CHECK17-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 10112 // CHECK17-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** 10113 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 8 10114 // CHECK17-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 10115 // CHECK17-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** 10116 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8 10117 // CHECK17-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 10118 // CHECK17-NEXT: store i8* null, i8** [[TMP115]], align 8 10119 // CHECK17-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 10120 // CHECK17-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64* 10121 // CHECK17-NEXT: store i64 5, i64* [[TMP117]], align 8 10122 // CHECK17-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 10123 // CHECK17-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i64* 10124 // CHECK17-NEXT: store i64 5, i64* [[TMP119]], align 8 10125 // CHECK17-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5 10126 // CHECK17-NEXT: store i8* null, i8** [[TMP120]], align 8 10127 // CHECK17-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 10128 // CHECK17-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64* 10129 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP122]], align 8 10130 // CHECK17-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 10131 // CHECK17-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i64* 10132 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP124]], align 8 10133 // CHECK17-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6 10134 // CHECK17-NEXT: store i8* null, i8** [[TMP125]], align 8 10135 // CHECK17-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 10136 // CHECK17-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** 10137 // CHECK17-NEXT: store double* [[VLA1]], double** [[TMP127]], align 8 10138 // CHECK17-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 10139 // CHECK17-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to double** 10140 // CHECK17-NEXT: store double* [[VLA1]], double** [[TMP129]], align 8 10141 // CHECK17-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 10142 // CHECK17-NEXT: store i64 [[TMP88]], i64* [[TMP130]], align 8 10143 // CHECK17-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7 10144 // CHECK17-NEXT: store i8* null, i8** [[TMP131]], align 8 10145 // CHECK17-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 10146 // CHECK17-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT** 10147 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 8 10148 // CHECK17-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 10149 // CHECK17-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to %struct.TT** 10150 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP135]], align 8 10151 // CHECK17-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8 10152 // CHECK17-NEXT: store i8* null, i8** [[TMP136]], align 8 10153 // CHECK17-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9 10154 // CHECK17-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i64* 10155 // CHECK17-NEXT: store i64 [[TMP84]], i64* [[TMP138]], align 8 10156 // CHECK17-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9 10157 // CHECK17-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to i64* 10158 // CHECK17-NEXT: store i64 [[TMP84]], i64* [[TMP140]], align 8 10159 // CHECK17-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9 10160 // CHECK17-NEXT: store i8* null, i8** [[TMP141]], align 8 10161 // CHECK17-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 10162 // CHECK17-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 10163 // CHECK17-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 10164 // CHECK17-NEXT: [[TMP145:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP142]], i8** [[TMP143]], i64* [[TMP144]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 10165 // CHECK17-NEXT: [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 0 10166 // CHECK17-NEXT: br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 10167 // CHECK17: omp_offload.failed23: 10168 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 10169 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT24]] 10170 // CHECK17: omp_offload.cont24: 10171 // CHECK17-NEXT: br label [[OMP_IF_END26:%.*]] 10172 // CHECK17: omp_if.else25: 10173 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 10174 // CHECK17-NEXT: br label [[OMP_IF_END26]] 10175 // CHECK17: omp_if.end26: 10176 // CHECK17-NEXT: [[TMP147:%.*]] = load i32, i32* [[A]], align 4 10177 // CHECK17-NEXT: [[TMP148:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 10178 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP148]]) 10179 // CHECK17-NEXT: ret i32 [[TMP147]] 10180 // 10181 // 10182 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 10183 // CHECK17-SAME: () #[[ATTR2:[0-9]+]] { 10184 // CHECK17-NEXT: entry: 10185 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 10186 // CHECK17-NEXT: ret void 10187 // 10188 // 10189 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 10190 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 10191 // CHECK17-NEXT: entry: 10192 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10193 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10194 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10195 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 10196 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10197 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10198 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10199 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10200 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 10201 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10202 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10203 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10204 // CHECK17-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 10205 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10206 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10207 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10208 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 10209 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10210 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10211 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 10212 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10213 // CHECK17: cond.true: 10214 // CHECK17-NEXT: br label [[COND_END:%.*]] 10215 // CHECK17: cond.false: 10216 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10217 // CHECK17-NEXT: br label [[COND_END]] 10218 // CHECK17: cond.end: 10219 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10220 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10221 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10222 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 10223 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10224 // CHECK17: omp.inner.for.cond: 10225 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10226 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10227 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10228 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10229 // CHECK17: omp.inner.for.body: 10230 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10231 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 10232 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 10233 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 10234 // CHECK17-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 10235 // CHECK17-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 10236 // CHECK17-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 10237 // CHECK17: .cancel.exit: 10238 // CHECK17-NEXT: br label [[CANCEL_EXIT:%.*]] 10239 // CHECK17: .cancel.continue: 10240 // CHECK17-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 10241 // CHECK17-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 10242 // CHECK17-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 10243 // CHECK17: .cancel.exit2: 10244 // CHECK17-NEXT: br label [[CANCEL_EXIT]] 10245 // CHECK17: .cancel.continue3: 10246 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10247 // CHECK17: omp.body.continue: 10248 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10249 // CHECK17: omp.inner.for.inc: 10250 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10251 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 10252 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 10253 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 10254 // CHECK17: omp.inner.for.end: 10255 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10256 // CHECK17: omp.loop.exit: 10257 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 10258 // CHECK17-NEXT: br label [[CANCEL_CONT:%.*]] 10259 // CHECK17: cancel.cont: 10260 // CHECK17-NEXT: ret void 10261 // CHECK17: cancel.exit: 10262 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 10263 // CHECK17-NEXT: br label [[CANCEL_CONT]] 10264 // 10265 // 10266 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 10267 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 10268 // CHECK17-NEXT: entry: 10269 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10270 // CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 10271 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10272 // CHECK17-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 10273 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10274 // CHECK17-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 10275 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10276 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 10277 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10278 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 10279 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 10280 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 10281 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 10282 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 10283 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 10284 // CHECK17-NEXT: ret void 10285 // 10286 // 10287 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 10288 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 10289 // CHECK17-NEXT: entry: 10290 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10291 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10292 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10293 // CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 10294 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10295 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 10296 // CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 10297 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10298 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10299 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10300 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10301 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 10302 // CHECK17-NEXT: [[K1:%.*]] = alloca i64, align 8 10303 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10304 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10305 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10306 // CHECK17-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 10307 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10308 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8 10309 // CHECK17-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8 10310 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10311 // CHECK17-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 10312 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10313 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10314 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10315 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 10316 // CHECK17-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 10317 // CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 10318 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 10319 // CHECK17: omp.dispatch.cond: 10320 // CHECK17-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 10321 // CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 10322 // CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 10323 // CHECK17: omp.dispatch.body: 10324 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10325 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 10326 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10327 // CHECK17: omp.inner.for.cond: 10328 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 10329 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 10330 // CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10331 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10332 // CHECK17: omp.inner.for.body: 10333 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 10334 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 10335 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 10336 // CHECK17-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12 10337 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12 10338 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 10339 // CHECK17-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 10340 // CHECK17-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 10341 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] 10342 // CHECK17-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12 10343 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12 10344 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 10345 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12 10346 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10347 // CHECK17: omp.body.continue: 10348 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10349 // CHECK17: omp.inner.for.inc: 10350 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 10351 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 10352 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 10353 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 10354 // CHECK17: omp.inner.for.end: 10355 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 10356 // CHECK17: omp.dispatch.inc: 10357 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 10358 // CHECK17: omp.dispatch.end: 10359 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10360 // CHECK17-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 10361 // CHECK17-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 10362 // CHECK17: .omp.linear.pu: 10363 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[K1]], align 8 10364 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[K_ADDR]], align 8 10365 // CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 10366 // CHECK17: .omp.linear.pu.done: 10367 // CHECK17-NEXT: ret void 10368 // 10369 // 10370 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 10371 // CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 10372 // CHECK17-NEXT: entry: 10373 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10374 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 10375 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10376 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10377 // CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 10378 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10379 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10380 // CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 10381 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10382 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10383 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 10384 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10385 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 10386 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10387 // CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 10388 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10389 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 10390 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 10391 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 10392 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 10393 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 10394 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10395 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 10396 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 10397 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 10398 // CHECK17-NEXT: ret void 10399 // 10400 // 10401 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 10402 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 10403 // CHECK17-NEXT: entry: 10404 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10405 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10406 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10407 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 10408 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10409 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10410 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 10411 // CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 10412 // CHECK17-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 10413 // CHECK17-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 10414 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10415 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10416 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10417 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10418 // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 10419 // CHECK17-NEXT: [[LIN4:%.*]] = alloca i32, align 4 10420 // CHECK17-NEXT: [[A5:%.*]] = alloca i32, align 4 10421 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10422 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10423 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10424 // CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 10425 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10426 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10427 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 10428 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10429 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 10430 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 10431 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 10432 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 10433 // CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 10434 // CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 10435 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 10436 // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 10437 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 10438 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10439 // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10440 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 10441 // CHECK17-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 10442 // CHECK17-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 10443 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10444 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 10445 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10446 // CHECK17: cond.true: 10447 // CHECK17-NEXT: br label [[COND_END:%.*]] 10448 // CHECK17: cond.false: 10449 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10450 // CHECK17-NEXT: br label [[COND_END]] 10451 // CHECK17: cond.end: 10452 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 10453 // CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 10454 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 10455 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 10456 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10457 // CHECK17: omp.inner.for.cond: 10458 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 10459 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10460 // CHECK17-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 10461 // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10462 // CHECK17: omp.inner.for.body: 10463 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 10464 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 10465 // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 10466 // CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 10467 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 10468 // CHECK17-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 10469 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 10470 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 10471 // CHECK17-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 10472 // CHECK17-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 10473 // CHECK17-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 10474 // CHECK17-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 10475 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 10476 // CHECK17-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 10477 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 10478 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 10479 // CHECK17-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 10480 // CHECK17-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 10481 // CHECK17-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 10482 // CHECK17-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 10483 // CHECK17-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 10484 // CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 10485 // CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 10486 // CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 10487 // CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 10488 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10489 // CHECK17: omp.body.continue: 10490 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10491 // CHECK17: omp.inner.for.inc: 10492 // CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 10493 // CHECK17-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 10494 // CHECK17-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 10495 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 10496 // CHECK17: omp.inner.for.end: 10497 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10498 // CHECK17: omp.loop.exit: 10499 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 10500 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10501 // CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 10502 // CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 10503 // CHECK17: .omp.linear.pu: 10504 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 10505 // CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 10506 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 10507 // CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 10508 // CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 10509 // CHECK17: .omp.linear.pu.done: 10510 // CHECK17-NEXT: ret void 10511 // 10512 // 10513 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map. 10514 // CHECK17-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 10515 // CHECK17-NEXT: entry: 10516 // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 10517 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 10518 // CHECK17-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 10519 // CHECK17-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 10520 // CHECK17-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 10521 // CHECK17-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 10522 // CHECK17-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 10523 // CHECK17-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 10524 // CHECK17-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 10525 // CHECK17-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 10526 // CHECK17-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 10527 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 10528 // CHECK17-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 10529 // CHECK17-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 10530 // CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 10531 // CHECK17-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 10532 // CHECK17-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 10533 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 10534 // CHECK17-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 10535 // CHECK17-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 10536 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 10537 // CHECK17-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 10538 // CHECK17-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 10539 // CHECK17-NEXT: ret void 10540 // 10541 // 10542 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. 10543 // CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 10544 // CHECK17-NEXT: entry: 10545 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 10546 // CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 10547 // CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 10548 // CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 10549 // CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 10550 // CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 10551 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 10552 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 10553 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 10554 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 10555 // CHECK17-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 10556 // CHECK17-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8 10557 // CHECK17-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8 10558 // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 10559 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 10560 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 10561 // CHECK17-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 10562 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 10563 // CHECK17-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 10564 // CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 10565 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 10566 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 10567 // CHECK17-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 10568 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 10569 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 10570 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 10571 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 10572 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 10573 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 10574 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 10575 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 10576 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 10577 // CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24 10578 // CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 10579 // CHECK17-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 10580 // CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24 10581 // CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 10582 // CHECK17-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 10583 // CHECK17-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 10584 // CHECK17-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 10585 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 10586 // CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 10587 // CHECK17-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 10588 // CHECK17-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 10589 // CHECK17-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 10590 // CHECK17-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24 10591 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 10592 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 10593 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 10594 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 10595 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 10596 // CHECK17-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 10597 // CHECK17-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 10598 // CHECK17-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 10599 // CHECK17: omp_offload.failed.i: 10600 // CHECK17-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 10601 // CHECK17-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 10602 // CHECK17-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24 10603 // CHECK17-NEXT: [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24 10604 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 10605 // CHECK17-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32* 10606 // CHECK17-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !24 10607 // CHECK17-NEXT: [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !24 10608 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 10609 // CHECK17-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32* 10610 // CHECK17-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !24 10611 // CHECK17-NEXT: [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !24 10612 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR4]] 10613 // CHECK17-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 10614 // CHECK17: .omp_outlined..3.exit: 10615 // CHECK17-NEXT: ret i32 0 10616 // 10617 // 10618 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 10619 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 10620 // CHECK17-NEXT: entry: 10621 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10622 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10623 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10624 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10625 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10626 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10627 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10628 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10629 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 10630 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10631 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 10632 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 10633 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 10634 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10635 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 10636 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10637 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 10638 // CHECK17-NEXT: ret void 10639 // 10640 // 10641 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 10642 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 10643 // CHECK17-NEXT: entry: 10644 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10645 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10646 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10647 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10648 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10649 // CHECK17-NEXT: [[TMP:%.*]] = alloca i16, align 2 10650 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10651 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10652 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10653 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10654 // CHECK17-NEXT: [[IT:%.*]] = alloca i16, align 2 10655 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10656 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10657 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10658 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10659 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10660 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10661 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10662 // CHECK17-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 10663 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10664 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10665 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10666 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 10667 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10668 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10669 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 10670 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10671 // CHECK17: cond.true: 10672 // CHECK17-NEXT: br label [[COND_END:%.*]] 10673 // CHECK17: cond.false: 10674 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10675 // CHECK17-NEXT: br label [[COND_END]] 10676 // CHECK17: cond.end: 10677 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10678 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10679 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10680 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 10681 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10682 // CHECK17: omp.inner.for.cond: 10683 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10684 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10685 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10686 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10687 // CHECK17: omp.inner.for.body: 10688 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10689 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 10690 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 10691 // CHECK17-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 10692 // CHECK17-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 10693 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 10694 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 10695 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 10696 // CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 10697 // CHECK17-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 10698 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 10699 // CHECK17-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 10700 // CHECK17-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 10701 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10702 // CHECK17: omp.body.continue: 10703 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10704 // CHECK17: omp.inner.for.inc: 10705 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10706 // CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 10707 // CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 10708 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 10709 // CHECK17: omp.inner.for.end: 10710 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10711 // CHECK17: omp.loop.exit: 10712 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 10713 // CHECK17-NEXT: ret void 10714 // 10715 // 10716 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 10717 // CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 10718 // CHECK17-NEXT: entry: 10719 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10720 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 10721 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10722 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 10723 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 10724 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10725 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10726 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 10727 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 10728 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 10729 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10730 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 10731 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10732 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 10733 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10734 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 10735 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 10736 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10737 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 10738 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 10739 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 10740 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 10741 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10742 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 10743 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10744 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 10745 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 10746 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10747 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 10748 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 10749 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 10750 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 10751 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 10752 // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10753 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 10754 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 10755 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 10756 // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 10757 // CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 10758 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 10759 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 10760 // CHECK17-NEXT: ret void 10761 // 10762 // 10763 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 10764 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 10765 // CHECK17-NEXT: entry: 10766 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10767 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10768 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10769 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 10770 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10771 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 10772 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 10773 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10774 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10775 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 10776 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 10777 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 10778 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10779 // CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1 10780 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10781 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10782 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10783 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10784 // CHECK17-NEXT: [[IT:%.*]] = alloca i8, align 1 10785 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10786 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10787 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10788 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 10789 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10790 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 10791 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 10792 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10793 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 10794 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 10795 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 10796 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 10797 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10798 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 10799 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10800 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 10801 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 10802 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10803 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 10804 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 10805 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 10806 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 10807 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10808 // CHECK17-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 10809 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10810 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10811 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 10812 // CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10813 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 10814 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 10815 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 10816 // CHECK17: omp.dispatch.cond: 10817 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10818 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 10819 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10820 // CHECK17: cond.true: 10821 // CHECK17-NEXT: br label [[COND_END:%.*]] 10822 // CHECK17: cond.false: 10823 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10824 // CHECK17-NEXT: br label [[COND_END]] 10825 // CHECK17: cond.end: 10826 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 10827 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10828 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10829 // CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 10830 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10831 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10832 // CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 10833 // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 10834 // CHECK17: omp.dispatch.body: 10835 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10836 // CHECK17: omp.inner.for.cond: 10837 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10838 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10839 // CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 10840 // CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10841 // CHECK17: omp.inner.for.body: 10842 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10843 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 10844 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 10845 // CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 10846 // CHECK17-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 10847 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 10848 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 10849 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10850 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 10851 // CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 10852 // CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 10853 // CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 10854 // CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 10855 // CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 10856 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 10857 // CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 10858 // CHECK17-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 10859 // CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 10860 // CHECK17-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 10861 // CHECK17-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 10862 // CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 10863 // CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 10864 // CHECK17-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 10865 // CHECK17-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 10866 // CHECK17-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 10867 // CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 10868 // CHECK17-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 10869 // CHECK17-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 10870 // CHECK17-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 10871 // CHECK17-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 10872 // CHECK17-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 10873 // CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 10874 // CHECK17-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 10875 // CHECK17-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 10876 // CHECK17-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 10877 // CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 10878 // CHECK17-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 10879 // CHECK17-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 10880 // CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 10881 // CHECK17-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 10882 // CHECK17-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 10883 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10884 // CHECK17: omp.body.continue: 10885 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10886 // CHECK17: omp.inner.for.inc: 10887 // CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10888 // CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 10889 // CHECK17-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 10890 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 10891 // CHECK17: omp.inner.for.end: 10892 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 10893 // CHECK17: omp.dispatch.inc: 10894 // CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10895 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 10896 // CHECK17-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 10897 // CHECK17-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 10898 // CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10899 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 10900 // CHECK17-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 10901 // CHECK17-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 10902 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 10903 // CHECK17: omp.dispatch.end: 10904 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 10905 // CHECK17-NEXT: ret void 10906 // 10907 // 10908 // CHECK17-LABEL: define {{[^@]+}}@_Z3bari 10909 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 10910 // CHECK17-NEXT: entry: 10911 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 10912 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 10913 // CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 10914 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 10915 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 10916 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 10917 // CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 10918 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 10919 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 10920 // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 10921 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 10922 // CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 10923 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 10924 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 10925 // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 10926 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 10927 // CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 10928 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 10929 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 10930 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 10931 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 10932 // CHECK17-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 10933 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 10934 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 10935 // CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 10936 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 10937 // CHECK17-NEXT: ret i32 [[TMP8]] 10938 // 10939 // 10940 // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 10941 // CHECK17-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 10942 // CHECK17-NEXT: entry: 10943 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 10944 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 10945 // CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 10946 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 10947 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 10948 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 10949 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 10950 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 10951 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 10952 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 10953 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 10954 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 10955 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 10956 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 10957 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 10958 // CHECK17-NEXT: store i32 [[ADD]], i32* [[B]], align 4 10959 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 10960 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 10961 // CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 10962 // CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 10963 // CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 10964 // CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 10965 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 10966 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 10967 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 10968 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 10969 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 10970 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 10971 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 10972 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 10973 // CHECK17: omp_if.then: 10974 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 10975 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 10976 // CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 10977 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 10978 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false) 10979 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10980 // CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 10981 // CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 10982 // CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10983 // CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 10984 // CHECK17-NEXT: store double* [[A]], double** [[TMP14]], align 8 10985 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 10986 // CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 10987 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 10988 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 10989 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 10990 // CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 10991 // CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 10992 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 10993 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 10994 // CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 10995 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 10996 // CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 10997 // CHECK17-NEXT: store i64 2, i64* [[TMP22]], align 8 10998 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 10999 // CHECK17-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 11000 // CHECK17-NEXT: store i64 2, i64* [[TMP24]], align 8 11001 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 11002 // CHECK17-NEXT: store i8* null, i8** [[TMP25]], align 8 11003 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 11004 // CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 11005 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 11006 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 11007 // CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 11008 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 11009 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 11010 // CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8 11011 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 11012 // CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 11013 // CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 11014 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 11015 // CHECK17-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 11016 // CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 11017 // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 11018 // CHECK17-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 11019 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 11020 // CHECK17-NEXT: store i8* null, i8** [[TMP36]], align 8 11021 // CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11022 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11023 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 11024 // CHECK17-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 11025 // CHECK17-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 11026 // CHECK17-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 11027 // CHECK17: omp_offload.failed: 11028 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 11029 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 11030 // CHECK17: omp_offload.cont: 11031 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 11032 // CHECK17: omp_if.else: 11033 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 11034 // CHECK17-NEXT: br label [[OMP_IF_END]] 11035 // CHECK17: omp_if.end: 11036 // CHECK17-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 11037 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 11038 // CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 11039 // CHECK17-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 11040 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 11041 // CHECK17-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 11042 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 11043 // CHECK17-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 11044 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 11045 // CHECK17-NEXT: ret i32 [[ADD4]] 11046 // 11047 // 11048 // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici 11049 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 11050 // CHECK17-NEXT: entry: 11051 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 11052 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 11053 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 11054 // CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1 11055 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 11056 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11057 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11058 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 11059 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 11060 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 11061 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 11062 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 11063 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 11064 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 11065 // CHECK17-NEXT: store i8 0, i8* [[AAA]], align 1 11066 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 11067 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11068 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 11069 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 11070 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 11071 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11072 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 11073 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11074 // CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 11075 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 11076 // CHECK17-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 11077 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 11078 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 11079 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 11080 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11081 // CHECK17: omp_if.then: 11082 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11083 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 11084 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 11085 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11086 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 11087 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 11088 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 11089 // CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8 11090 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 11091 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 11092 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 11093 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 11094 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 11095 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 11096 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 11097 // CHECK17-NEXT: store i8* null, i8** [[TMP16]], align 8 11098 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 11099 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 11100 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 11101 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 11102 // CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 11103 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 11104 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 11105 // CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 11106 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 11107 // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 11108 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 11109 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 11110 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 11111 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 11112 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 11113 // CHECK17-NEXT: store i8* null, i8** [[TMP26]], align 8 11114 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11115 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11116 // CHECK17-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 11117 // CHECK17-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 11118 // CHECK17-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 11119 // CHECK17: omp_offload.failed: 11120 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 11121 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 11122 // CHECK17: omp_offload.cont: 11123 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 11124 // CHECK17: omp_if.else: 11125 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 11126 // CHECK17-NEXT: br label [[OMP_IF_END]] 11127 // CHECK17: omp_if.end: 11128 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 11129 // CHECK17-NEXT: ret i32 [[TMP31]] 11130 // 11131 // 11132 // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 11133 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 11134 // CHECK17-NEXT: entry: 11135 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 11136 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 11137 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 11138 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 11139 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11140 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11141 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 11142 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 11143 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 11144 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 11145 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 11146 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 11147 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 11148 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11149 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 11150 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 11151 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 11152 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11153 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 11154 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11155 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 11156 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 11157 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11158 // CHECK17: omp_if.then: 11159 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11160 // CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 11161 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 11162 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11163 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 11164 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 11165 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 11166 // CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8 11167 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 11168 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 11169 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 11170 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 11171 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 11172 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 11173 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 11174 // CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8 11175 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 11176 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 11177 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 11178 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 11179 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 11180 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 11181 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 11182 // CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 11183 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11184 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11185 // CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 11186 // CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 11187 // CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 11188 // CHECK17: omp_offload.failed: 11189 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 11190 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 11191 // CHECK17: omp_offload.cont: 11192 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 11193 // CHECK17: omp_if.else: 11194 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 11195 // CHECK17-NEXT: br label [[OMP_IF_END]] 11196 // CHECK17: omp_if.end: 11197 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 11198 // CHECK17-NEXT: ret i32 [[TMP24]] 11199 // 11200 // 11201 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 11202 // CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 11203 // CHECK17-NEXT: entry: 11204 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 11205 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 11206 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11207 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11208 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 11209 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 11210 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 11211 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 11212 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 11213 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 11214 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 11215 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 11216 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 11217 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 11218 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 11219 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 11220 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 11221 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 11222 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 11223 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 11224 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 11225 // CHECK17-NEXT: ret void 11226 // 11227 // 11228 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10 11229 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 11230 // CHECK17-NEXT: entry: 11231 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11232 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11233 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 11234 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 11235 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11236 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11237 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 11238 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11239 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 11240 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11241 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11242 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11243 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11244 // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 11245 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11246 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11247 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 11248 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 11249 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 11250 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 11251 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 11252 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 11253 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 11254 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 11255 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 11256 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 11257 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 11258 // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 11259 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 11260 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11261 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11262 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 11263 // CHECK17-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 11264 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11265 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 11266 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11267 // CHECK17: cond.true: 11268 // CHECK17-NEXT: br label [[COND_END:%.*]] 11269 // CHECK17: cond.false: 11270 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11271 // CHECK17-NEXT: br label [[COND_END]] 11272 // CHECK17: cond.end: 11273 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 11274 // CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 11275 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 11276 // CHECK17-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 11277 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11278 // CHECK17: omp.inner.for.cond: 11279 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11280 // CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11281 // CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 11282 // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11283 // CHECK17: omp.inner.for.body: 11284 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11285 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 11286 // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 11287 // CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 11288 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 11289 // CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 11290 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 11291 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 11292 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 11293 // CHECK17-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11294 // CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 11295 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 11296 // CHECK17-NEXT: store double [[INC]], double* [[A5]], align 8 11297 // CHECK17-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 11298 // CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 11299 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 11300 // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 11301 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 11302 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11303 // CHECK17: omp.body.continue: 11304 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11305 // CHECK17: omp.inner.for.inc: 11306 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11307 // CHECK17-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 11308 // CHECK17-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 11309 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 11310 // CHECK17: omp.inner.for.end: 11311 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11312 // CHECK17: omp.loop.exit: 11313 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 11314 // CHECK17-NEXT: ret void 11315 // 11316 // 11317 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 11318 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 11319 // CHECK17-NEXT: entry: 11320 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11321 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11322 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 11323 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11324 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11325 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11326 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 11327 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11328 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11329 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 11330 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11331 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11332 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11333 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 11334 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11335 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 11336 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11337 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 11338 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 11339 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 11340 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11341 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 11342 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11343 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 11344 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 11345 // CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 11346 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 11347 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 11348 // CHECK17-NEXT: ret void 11349 // 11350 // 11351 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..13 11352 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 11353 // CHECK17-NEXT: entry: 11354 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11355 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11356 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11357 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11358 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 11359 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11360 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11361 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 11362 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11363 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11364 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11365 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11366 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 11367 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11368 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11369 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11370 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 11371 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11372 // CHECK17-NEXT: ret void 11373 // 11374 // 11375 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 11376 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 11377 // CHECK17-NEXT: entry: 11378 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11379 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11380 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11381 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11382 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11383 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11384 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11385 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11386 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11387 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11388 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11389 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 11390 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11391 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 11392 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 11393 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 11394 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11395 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 11396 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11397 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 11398 // CHECK17-NEXT: ret void 11399 // 11400 // 11401 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..16 11402 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 11403 // CHECK17-NEXT: entry: 11404 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11405 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11406 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11407 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11408 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11409 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11410 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 11411 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11412 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11413 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11414 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11415 // CHECK17-NEXT: [[I:%.*]] = alloca i64, align 8 11416 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11417 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11418 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11419 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11420 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11421 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11422 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11423 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11424 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 11425 // CHECK17-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 11426 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 11427 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11428 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11429 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 11430 // CHECK17-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 11431 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11432 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 11433 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11434 // CHECK17: cond.true: 11435 // CHECK17-NEXT: br label [[COND_END:%.*]] 11436 // CHECK17: cond.false: 11437 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11438 // CHECK17-NEXT: br label [[COND_END]] 11439 // CHECK17: cond.end: 11440 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 11441 // CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 11442 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 11443 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 11444 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11445 // CHECK17: omp.inner.for.cond: 11446 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11447 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11448 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 11449 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11450 // CHECK17: omp.inner.for.body: 11451 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11452 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 11453 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 11454 // CHECK17-NEXT: store i64 [[ADD]], i64* [[I]], align 8 11455 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 11456 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 11457 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 11458 // CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 11459 // CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 11460 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 11461 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 11462 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 11463 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 11464 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 11465 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 11466 // CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 11467 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11468 // CHECK17: omp.body.continue: 11469 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11470 // CHECK17: omp.inner.for.inc: 11471 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11472 // CHECK17-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 11473 // CHECK17-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 11474 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 11475 // CHECK17: omp.inner.for.end: 11476 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11477 // CHECK17: omp.loop.exit: 11478 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 11479 // CHECK17-NEXT: ret void 11480 // 11481 // 11482 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 11483 // CHECK17-SAME: () #[[ATTR6]] { 11484 // CHECK17-NEXT: entry: 11485 // CHECK17-NEXT: call void @__tgt_register_requires(i64 1) 11486 // CHECK17-NEXT: ret void 11487 // 11488 // 11489 // CHECK18-LABEL: define {{[^@]+}}@_Z7get_valv 11490 // CHECK18-SAME: () #[[ATTR0:[0-9]+]] { 11491 // CHECK18-NEXT: entry: 11492 // CHECK18-NEXT: ret i64 0 11493 // 11494 // 11495 // CHECK18-LABEL: define {{[^@]+}}@_Z3fooi 11496 // CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 11497 // CHECK18-NEXT: entry: 11498 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 11499 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 11500 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 11501 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x float], align 4 11502 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 11503 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 11504 // CHECK18-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 11505 // CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 11506 // CHECK18-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 11507 // CHECK18-NEXT: [[K:%.*]] = alloca i64, align 8 11508 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11509 // CHECK18-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 11510 // CHECK18-NEXT: [[LIN:%.*]] = alloca i32, align 4 11511 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11512 // CHECK18-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 11513 // CHECK18-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8 11514 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 11515 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 11516 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 11517 // CHECK18-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 11518 // CHECK18-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8 11519 // CHECK18-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8 11520 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 11521 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 11522 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 11523 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 11524 // CHECK18-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8 11525 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 11526 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8 11527 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8 11528 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8 11529 // CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 11530 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 11531 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 11532 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 11533 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 11534 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 11535 // CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 11536 // CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 11537 // CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 11538 // CHECK18-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 11539 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 11540 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 11541 // CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 11542 // CHECK18-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 11543 // CHECK18-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 11544 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 11545 // CHECK18-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 11546 // CHECK18-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 11547 // CHECK18-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 11548 // CHECK18: omp_offload.failed: 11549 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 11550 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 11551 // CHECK18: omp_offload.cont: 11552 // CHECK18-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 11553 // CHECK18-NEXT: store i64 [[CALL]], i64* [[K]], align 8 11554 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 11555 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11556 // CHECK18-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4 11557 // CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8 11558 // CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[K]], align 8 11559 // CHECK18-NEXT: store i64 [[TMP11]], i64* [[K_CASTED]], align 8 11560 // CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8 11561 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR4]] 11562 // CHECK18-NEXT: store i32 12, i32* [[LIN]], align 4 11563 // CHECK18-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 11564 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11565 // CHECK18-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 11566 // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11567 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4 11568 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 11569 // CHECK18-NEXT: store i32 [[TMP15]], i32* [[CONV3]], align 4 11570 // CHECK18-NEXT: [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 11571 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 11572 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32* 11573 // CHECK18-NEXT: store i32 [[TMP17]], i32* [[CONV5]], align 4 11574 // CHECK18-NEXT: [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8 11575 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11576 // CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 11577 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP20]], align 8 11578 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11579 // CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 11580 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP22]], align 8 11581 // CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 11582 // CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8 11583 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 11584 // CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 11585 // CHECK18-NEXT: store i64 [[TMP16]], i64* [[TMP25]], align 8 11586 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 11587 // CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 11588 // CHECK18-NEXT: store i64 [[TMP16]], i64* [[TMP27]], align 8 11589 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 11590 // CHECK18-NEXT: store i8* null, i8** [[TMP28]], align 8 11591 // CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 11592 // CHECK18-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 11593 // CHECK18-NEXT: store i64 [[TMP18]], i64* [[TMP30]], align 8 11594 // CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 11595 // CHECK18-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 11596 // CHECK18-NEXT: store i64 [[TMP18]], i64* [[TMP32]], align 8 11597 // CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 11598 // CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 11599 // CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11600 // CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11601 // CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 11602 // CHECK18-NEXT: [[TMP37:%.*]] = load i16, i16* [[AA]], align 2 11603 // CHECK18-NEXT: store i16 [[TMP37]], i16* [[TMP36]], align 4 11604 // CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 11605 // CHECK18-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4 11606 // CHECK18-NEXT: store i32 [[TMP39]], i32* [[TMP38]], align 4 11607 // CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 11608 // CHECK18-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 11609 // CHECK18-NEXT: store i32 [[TMP41]], i32* [[TMP40]], align 4 11610 // CHECK18-NEXT: [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 11611 // CHECK18-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates* 11612 // CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0 11613 // CHECK18-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0 11614 // CHECK18-NEXT: [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8 11615 // CHECK18-NEXT: [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 11616 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false) 11617 // CHECK18-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1 11618 // CHECK18-NEXT: [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon* 11619 // CHECK18-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0 11620 // CHECK18-NEXT: [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8* 11621 // CHECK18-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8* 11622 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false) 11623 // CHECK18-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1 11624 // CHECK18-NEXT: [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8* 11625 // CHECK18-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8* 11626 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false) 11627 // CHECK18-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2 11628 // CHECK18-NEXT: [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8* 11629 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 11630 // CHECK18-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3 11631 // CHECK18-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 11632 // CHECK18-NEXT: store i16 [[TMP59]], i16* [[TMP58]], align 8 11633 // CHECK18-NEXT: [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]]) 11634 // CHECK18-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4 11635 // CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32* 11636 // CHECK18-NEXT: store i32 [[TMP61]], i32* [[CONV7]], align 4 11637 // CHECK18-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8 11638 // CHECK18-NEXT: [[TMP63:%.*]] = load i16, i16* [[AA]], align 2 11639 // CHECK18-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16* 11640 // CHECK18-NEXT: store i16 [[TMP63]], i16* [[CONV9]], align 2 11641 // CHECK18-NEXT: [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8 11642 // CHECK18-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4 11643 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10 11644 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11645 // CHECK18: omp_if.then: 11646 // CHECK18-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 11647 // CHECK18-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64* 11648 // CHECK18-NEXT: store i64 [[TMP62]], i64* [[TMP67]], align 8 11649 // CHECK18-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 11650 // CHECK18-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* 11651 // CHECK18-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8 11652 // CHECK18-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 11653 // CHECK18-NEXT: store i8* null, i8** [[TMP70]], align 8 11654 // CHECK18-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 11655 // CHECK18-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* 11656 // CHECK18-NEXT: store i64 [[TMP64]], i64* [[TMP72]], align 8 11657 // CHECK18-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 11658 // CHECK18-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* 11659 // CHECK18-NEXT: store i64 [[TMP64]], i64* [[TMP74]], align 8 11660 // CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 11661 // CHECK18-NEXT: store i8* null, i8** [[TMP75]], align 8 11662 // CHECK18-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 11663 // CHECK18-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 11664 // CHECK18-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 11665 // CHECK18-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0 11666 // CHECK18-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]] 11667 // CHECK18: omp_offload.failed13: 11668 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 11669 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT14]] 11670 // CHECK18: omp_offload.cont14: 11671 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 11672 // CHECK18: omp_if.else: 11673 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 11674 // CHECK18-NEXT: br label [[OMP_IF_END]] 11675 // CHECK18: omp_if.end: 11676 // CHECK18-NEXT: [[TMP80:%.*]] = load i32, i32* [[A]], align 4 11677 // CHECK18-NEXT: store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4 11678 // CHECK18-NEXT: [[TMP81:%.*]] = load i32, i32* [[A]], align 4 11679 // CHECK18-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32* 11680 // CHECK18-NEXT: store i32 [[TMP81]], i32* [[CONV16]], align 4 11681 // CHECK18-NEXT: [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8 11682 // CHECK18-NEXT: [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 11683 // CHECK18-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 11684 // CHECK18-NEXT: store i32 [[TMP83]], i32* [[CONV17]], align 4 11685 // CHECK18-NEXT: [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 11686 // CHECK18-NEXT: [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4 11687 // CHECK18-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20 11688 // CHECK18-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 11689 // CHECK18: omp_if.then19: 11690 // CHECK18-NEXT: [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4 11691 // CHECK18-NEXT: [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]] 11692 // CHECK18-NEXT: [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8 11693 // CHECK18-NEXT: [[TMP89:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 11694 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP89]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i64 80, i1 false) 11695 // CHECK18-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 11696 // CHECK18-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i64* 11697 // CHECK18-NEXT: store i64 [[TMP82]], i64* [[TMP91]], align 8 11698 // CHECK18-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 11699 // CHECK18-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to i64* 11700 // CHECK18-NEXT: store i64 [[TMP82]], i64* [[TMP93]], align 8 11701 // CHECK18-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 11702 // CHECK18-NEXT: store i8* null, i8** [[TMP94]], align 8 11703 // CHECK18-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 11704 // CHECK18-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 11705 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8 11706 // CHECK18-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 11707 // CHECK18-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]** 11708 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8 11709 // CHECK18-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 11710 // CHECK18-NEXT: store i8* null, i8** [[TMP99]], align 8 11711 // CHECK18-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 11712 // CHECK18-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64* 11713 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP101]], align 8 11714 // CHECK18-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 11715 // CHECK18-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i64* 11716 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP103]], align 8 11717 // CHECK18-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 11718 // CHECK18-NEXT: store i8* null, i8** [[TMP104]], align 8 11719 // CHECK18-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 11720 // CHECK18-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** 11721 // CHECK18-NEXT: store float* [[VLA]], float** [[TMP106]], align 8 11722 // CHECK18-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 11723 // CHECK18-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** 11724 // CHECK18-NEXT: store float* [[VLA]], float** [[TMP108]], align 8 11725 // CHECK18-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 11726 // CHECK18-NEXT: store i64 [[TMP86]], i64* [[TMP109]], align 8 11727 // CHECK18-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 11728 // CHECK18-NEXT: store i8* null, i8** [[TMP110]], align 8 11729 // CHECK18-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 11730 // CHECK18-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** 11731 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 8 11732 // CHECK18-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 11733 // CHECK18-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** 11734 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8 11735 // CHECK18-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 11736 // CHECK18-NEXT: store i8* null, i8** [[TMP115]], align 8 11737 // CHECK18-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 11738 // CHECK18-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64* 11739 // CHECK18-NEXT: store i64 5, i64* [[TMP117]], align 8 11740 // CHECK18-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 11741 // CHECK18-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i64* 11742 // CHECK18-NEXT: store i64 5, i64* [[TMP119]], align 8 11743 // CHECK18-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5 11744 // CHECK18-NEXT: store i8* null, i8** [[TMP120]], align 8 11745 // CHECK18-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 11746 // CHECK18-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64* 11747 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP122]], align 8 11748 // CHECK18-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 11749 // CHECK18-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i64* 11750 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP124]], align 8 11751 // CHECK18-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6 11752 // CHECK18-NEXT: store i8* null, i8** [[TMP125]], align 8 11753 // CHECK18-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 11754 // CHECK18-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** 11755 // CHECK18-NEXT: store double* [[VLA1]], double** [[TMP127]], align 8 11756 // CHECK18-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 11757 // CHECK18-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to double** 11758 // CHECK18-NEXT: store double* [[VLA1]], double** [[TMP129]], align 8 11759 // CHECK18-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 11760 // CHECK18-NEXT: store i64 [[TMP88]], i64* [[TMP130]], align 8 11761 // CHECK18-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7 11762 // CHECK18-NEXT: store i8* null, i8** [[TMP131]], align 8 11763 // CHECK18-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 11764 // CHECK18-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT** 11765 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 8 11766 // CHECK18-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 11767 // CHECK18-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to %struct.TT** 11768 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP135]], align 8 11769 // CHECK18-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8 11770 // CHECK18-NEXT: store i8* null, i8** [[TMP136]], align 8 11771 // CHECK18-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9 11772 // CHECK18-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i64* 11773 // CHECK18-NEXT: store i64 [[TMP84]], i64* [[TMP138]], align 8 11774 // CHECK18-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9 11775 // CHECK18-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to i64* 11776 // CHECK18-NEXT: store i64 [[TMP84]], i64* [[TMP140]], align 8 11777 // CHECK18-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9 11778 // CHECK18-NEXT: store i8* null, i8** [[TMP141]], align 8 11779 // CHECK18-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 11780 // CHECK18-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 11781 // CHECK18-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 11782 // CHECK18-NEXT: [[TMP145:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP142]], i8** [[TMP143]], i64* [[TMP144]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 11783 // CHECK18-NEXT: [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 0 11784 // CHECK18-NEXT: br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 11785 // CHECK18: omp_offload.failed23: 11786 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 11787 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT24]] 11788 // CHECK18: omp_offload.cont24: 11789 // CHECK18-NEXT: br label [[OMP_IF_END26:%.*]] 11790 // CHECK18: omp_if.else25: 11791 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 11792 // CHECK18-NEXT: br label [[OMP_IF_END26]] 11793 // CHECK18: omp_if.end26: 11794 // CHECK18-NEXT: [[TMP147:%.*]] = load i32, i32* [[A]], align 4 11795 // CHECK18-NEXT: [[TMP148:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 11796 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP148]]) 11797 // CHECK18-NEXT: ret i32 [[TMP147]] 11798 // 11799 // 11800 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 11801 // CHECK18-SAME: () #[[ATTR2:[0-9]+]] { 11802 // CHECK18-NEXT: entry: 11803 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 11804 // CHECK18-NEXT: ret void 11805 // 11806 // 11807 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. 11808 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 11809 // CHECK18-NEXT: entry: 11810 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11811 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11812 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11813 // CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 11814 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11815 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11816 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11817 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11818 // CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 11819 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11820 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11821 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 11822 // CHECK18-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 11823 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 11824 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11825 // CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11826 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 11827 // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 11828 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11829 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 11830 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11831 // CHECK18: cond.true: 11832 // CHECK18-NEXT: br label [[COND_END:%.*]] 11833 // CHECK18: cond.false: 11834 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11835 // CHECK18-NEXT: br label [[COND_END]] 11836 // CHECK18: cond.end: 11837 // CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 11838 // CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 11839 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 11840 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 11841 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11842 // CHECK18: omp.inner.for.cond: 11843 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 11844 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11845 // CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 11846 // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11847 // CHECK18: omp.inner.for.body: 11848 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 11849 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 11850 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 11851 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 11852 // CHECK18-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 11853 // CHECK18-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 11854 // CHECK18-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 11855 // CHECK18: .cancel.exit: 11856 // CHECK18-NEXT: br label [[CANCEL_EXIT:%.*]] 11857 // CHECK18: .cancel.continue: 11858 // CHECK18-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 11859 // CHECK18-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 11860 // CHECK18-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 11861 // CHECK18: .cancel.exit2: 11862 // CHECK18-NEXT: br label [[CANCEL_EXIT]] 11863 // CHECK18: .cancel.continue3: 11864 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11865 // CHECK18: omp.body.continue: 11866 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11867 // CHECK18: omp.inner.for.inc: 11868 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 11869 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 11870 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 11871 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] 11872 // CHECK18: omp.inner.for.end: 11873 // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11874 // CHECK18: omp.loop.exit: 11875 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 11876 // CHECK18-NEXT: br label [[CANCEL_CONT:%.*]] 11877 // CHECK18: cancel.cont: 11878 // CHECK18-NEXT: ret void 11879 // CHECK18: cancel.exit: 11880 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 11881 // CHECK18-NEXT: br label [[CANCEL_CONT]] 11882 // 11883 // 11884 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 11885 // CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 11886 // CHECK18-NEXT: entry: 11887 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11888 // CHECK18-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 11889 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11890 // CHECK18-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 11891 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11892 // CHECK18-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 11893 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11894 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 11895 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11896 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 11897 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 11898 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 11899 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 11900 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 11901 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 11902 // CHECK18-NEXT: ret void 11903 // 11904 // 11905 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 11906 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 11907 // CHECK18-NEXT: entry: 11908 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11909 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11910 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11911 // CHECK18-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 11912 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11913 // CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 11914 // CHECK18-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 11915 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11916 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11917 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11918 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11919 // CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 11920 // CHECK18-NEXT: [[K1:%.*]] = alloca i64, align 8 11921 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11922 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11923 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11924 // CHECK18-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 11925 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11926 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8 11927 // CHECK18-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8 11928 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 11929 // CHECK18-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 11930 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 11931 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11932 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11933 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 11934 // CHECK18-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 11935 // CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 11936 // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 11937 // CHECK18: omp.dispatch.cond: 11938 // CHECK18-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 11939 // CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 11940 // CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 11941 // CHECK18: omp.dispatch.body: 11942 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 11943 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 11944 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11945 // CHECK18: omp.inner.for.cond: 11946 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 11947 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 11948 // CHECK18-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 11949 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11950 // CHECK18: omp.inner.for.body: 11951 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 11952 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 11953 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 11954 // CHECK18-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12 11955 // CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12 11956 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 11957 // CHECK18-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 11958 // CHECK18-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 11959 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] 11960 // CHECK18-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12 11961 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12 11962 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 11963 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12 11964 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11965 // CHECK18: omp.body.continue: 11966 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11967 // CHECK18: omp.inner.for.inc: 11968 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 11969 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 11970 // CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 11971 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 11972 // CHECK18: omp.inner.for.end: 11973 // CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 11974 // CHECK18: omp.dispatch.inc: 11975 // CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] 11976 // CHECK18: omp.dispatch.end: 11977 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11978 // CHECK18-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 11979 // CHECK18-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 11980 // CHECK18: .omp.linear.pu: 11981 // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[K1]], align 8 11982 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[K_ADDR]], align 8 11983 // CHECK18-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 11984 // CHECK18: .omp.linear.pu.done: 11985 // CHECK18-NEXT: ret void 11986 // 11987 // 11988 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 11989 // CHECK18-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 11990 // CHECK18-NEXT: entry: 11991 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11992 // CHECK18-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 11993 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11994 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11995 // CHECK18-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 11996 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11997 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11998 // CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 11999 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12000 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 12001 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 12002 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12003 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 12004 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 12005 // CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 12006 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 12007 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 12008 // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 12009 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 12010 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 12011 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 12012 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 12013 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 12014 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 12015 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 12016 // CHECK18-NEXT: ret void 12017 // 12018 // 12019 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 12020 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 12021 // CHECK18-NEXT: entry: 12022 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 12023 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 12024 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 12025 // CHECK18-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 12026 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12027 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 12028 // CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8 12029 // CHECK18-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 12030 // CHECK18-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 12031 // CHECK18-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 12032 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 12033 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 12034 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 12035 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12036 // CHECK18-NEXT: [[IT:%.*]] = alloca i64, align 8 12037 // CHECK18-NEXT: [[LIN4:%.*]] = alloca i32, align 4 12038 // CHECK18-NEXT: [[A5:%.*]] = alloca i32, align 4 12039 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 12040 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 12041 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 12042 // CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 12043 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12044 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 12045 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 12046 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12047 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 12048 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 12049 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 12050 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 12051 // CHECK18-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 12052 // CHECK18-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 12053 // CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 12054 // CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 12055 // CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 12056 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12057 // CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 12058 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 12059 // CHECK18-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 12060 // CHECK18-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 12061 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 12062 // CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 12063 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12064 // CHECK18: cond.true: 12065 // CHECK18-NEXT: br label [[COND_END:%.*]] 12066 // CHECK18: cond.false: 12067 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 12068 // CHECK18-NEXT: br label [[COND_END]] 12069 // CHECK18: cond.end: 12070 // CHECK18-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 12071 // CHECK18-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 12072 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 12073 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 12074 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12075 // CHECK18: omp.inner.for.cond: 12076 // CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 12077 // CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 12078 // CHECK18-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 12079 // CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12080 // CHECK18: omp.inner.for.body: 12081 // CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 12082 // CHECK18-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 12083 // CHECK18-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 12084 // CHECK18-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 12085 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 12086 // CHECK18-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 12087 // CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 12088 // CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 12089 // CHECK18-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 12090 // CHECK18-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 12091 // CHECK18-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 12092 // CHECK18-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 12093 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 12094 // CHECK18-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 12095 // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 12096 // CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 12097 // CHECK18-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 12098 // CHECK18-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 12099 // CHECK18-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 12100 // CHECK18-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 12101 // CHECK18-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 12102 // CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 12103 // CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 12104 // CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 12105 // CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 12106 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12107 // CHECK18: omp.body.continue: 12108 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12109 // CHECK18: omp.inner.for.inc: 12110 // CHECK18-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 12111 // CHECK18-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 12112 // CHECK18-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 12113 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] 12114 // CHECK18: omp.inner.for.end: 12115 // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12116 // CHECK18: omp.loop.exit: 12117 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 12118 // CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 12119 // CHECK18-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 12120 // CHECK18-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 12121 // CHECK18: .omp.linear.pu: 12122 // CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 12123 // CHECK18-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 12124 // CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 12125 // CHECK18-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 12126 // CHECK18-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 12127 // CHECK18: .omp.linear.pu.done: 12128 // CHECK18-NEXT: ret void 12129 // 12130 // 12131 // CHECK18-LABEL: define {{[^@]+}}@.omp_task_privates_map. 12132 // CHECK18-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 12133 // CHECK18-NEXT: entry: 12134 // CHECK18-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 12135 // CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 12136 // CHECK18-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 12137 // CHECK18-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 12138 // CHECK18-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 12139 // CHECK18-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 12140 // CHECK18-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 12141 // CHECK18-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 12142 // CHECK18-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 12143 // CHECK18-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 12144 // CHECK18-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 12145 // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 12146 // CHECK18-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 12147 // CHECK18-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 12148 // CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 12149 // CHECK18-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 12150 // CHECK18-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 12151 // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 12152 // CHECK18-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 12153 // CHECK18-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 12154 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 12155 // CHECK18-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 12156 // CHECK18-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 12157 // CHECK18-NEXT: ret void 12158 // 12159 // 12160 // CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry. 12161 // CHECK18-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 12162 // CHECK18-NEXT: entry: 12163 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 12164 // CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 12165 // CHECK18-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 12166 // CHECK18-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 12167 // CHECK18-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 12168 // CHECK18-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 12169 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 12170 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 12171 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 12172 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 12173 // CHECK18-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 12174 // CHECK18-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8 12175 // CHECK18-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8 12176 // CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 12177 // CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 12178 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 12179 // CHECK18-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 12180 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 12181 // CHECK18-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 12182 // CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 12183 // CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 12184 // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 12185 // CHECK18-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 12186 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 12187 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 12188 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 12189 // CHECK18-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 12190 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 12191 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 12192 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 12193 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 12194 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 12195 // CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24 12196 // CHECK18-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 12197 // CHECK18-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 12198 // CHECK18-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24 12199 // CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 12200 // CHECK18-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 12201 // CHECK18-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 12202 // CHECK18-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 12203 // CHECK18-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 12204 // CHECK18-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 12205 // CHECK18-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 12206 // CHECK18-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 12207 // CHECK18-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 12208 // CHECK18-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24 12209 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 12210 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 12211 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 12212 // CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 12213 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 12214 // CHECK18-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 12215 // CHECK18-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 12216 // CHECK18-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 12217 // CHECK18: omp_offload.failed.i: 12218 // CHECK18-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 12219 // CHECK18-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 12220 // CHECK18-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24 12221 // CHECK18-NEXT: [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24 12222 // CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 12223 // CHECK18-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32* 12224 // CHECK18-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !24 12225 // CHECK18-NEXT: [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !24 12226 // CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 12227 // CHECK18-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32* 12228 // CHECK18-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !24 12229 // CHECK18-NEXT: [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !24 12230 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR4]] 12231 // CHECK18-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 12232 // CHECK18: .omp_outlined..3.exit: 12233 // CHECK18-NEXT: ret i32 0 12234 // 12235 // 12236 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 12237 // CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 12238 // CHECK18-NEXT: entry: 12239 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12240 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 12241 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 12242 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 12243 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12244 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 12245 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12246 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 12247 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 12248 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 12249 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 12250 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 12251 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 12252 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 12253 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 12254 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 12255 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 12256 // CHECK18-NEXT: ret void 12257 // 12258 // 12259 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 12260 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 12261 // CHECK18-NEXT: entry: 12262 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 12263 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 12264 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12265 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 12266 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 12267 // CHECK18-NEXT: [[TMP:%.*]] = alloca i16, align 2 12268 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 12269 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 12270 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 12271 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12272 // CHECK18-NEXT: [[IT:%.*]] = alloca i16, align 2 12273 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 12274 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 12275 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12276 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 12277 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12278 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 12279 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 12280 // CHECK18-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 12281 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 12282 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12283 // CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 12284 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 12285 // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 12286 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12287 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 12288 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12289 // CHECK18: cond.true: 12290 // CHECK18-NEXT: br label [[COND_END:%.*]] 12291 // CHECK18: cond.false: 12292 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12293 // CHECK18-NEXT: br label [[COND_END]] 12294 // CHECK18: cond.end: 12295 // CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 12296 // CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 12297 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 12298 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 12299 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12300 // CHECK18: omp.inner.for.cond: 12301 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 12302 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12303 // CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 12304 // CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12305 // CHECK18: omp.inner.for.body: 12306 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 12307 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 12308 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 12309 // CHECK18-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 12310 // CHECK18-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 12311 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 12312 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 12313 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 12314 // CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 12315 // CHECK18-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 12316 // CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 12317 // CHECK18-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 12318 // CHECK18-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 12319 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12320 // CHECK18: omp.body.continue: 12321 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12322 // CHECK18: omp.inner.for.inc: 12323 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 12324 // CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 12325 // CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 12326 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] 12327 // CHECK18: omp.inner.for.end: 12328 // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12329 // CHECK18: omp.loop.exit: 12330 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 12331 // CHECK18-NEXT: ret void 12332 // 12333 // 12334 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 12335 // CHECK18-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 12336 // CHECK18-NEXT: entry: 12337 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12338 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 12339 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 12340 // CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 12341 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 12342 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 12343 // CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 12344 // CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 12345 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 12346 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 12347 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 12348 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 12349 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12350 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 12351 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 12352 // CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 12353 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 12354 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 12355 // CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 12356 // CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 12357 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 12358 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 12359 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12360 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 12361 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 12362 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 12363 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 12364 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 12365 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 12366 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 12367 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 12368 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 12369 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 12370 // CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 12371 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 12372 // CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 12373 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 12374 // CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 12375 // CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 12376 // CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 12377 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 12378 // CHECK18-NEXT: ret void 12379 // 12380 // 12381 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 12382 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 12383 // CHECK18-NEXT: entry: 12384 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 12385 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 12386 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12387 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 12388 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 12389 // CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 12390 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 12391 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 12392 // CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 12393 // CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 12394 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 12395 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 12396 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 12397 // CHECK18-NEXT: [[TMP:%.*]] = alloca i8, align 1 12398 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 12399 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 12400 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 12401 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12402 // CHECK18-NEXT: [[IT:%.*]] = alloca i8, align 1 12403 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 12404 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 12405 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12406 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 12407 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 12408 // CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 12409 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 12410 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 12411 // CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 12412 // CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 12413 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 12414 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 12415 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12416 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 12417 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 12418 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 12419 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 12420 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 12421 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 12422 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 12423 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 12424 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 12425 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 12426 // CHECK18-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 12427 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 12428 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12429 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 12430 // CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 12431 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 12432 // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 12433 // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 12434 // CHECK18: omp.dispatch.cond: 12435 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12436 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 12437 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12438 // CHECK18: cond.true: 12439 // CHECK18-NEXT: br label [[COND_END:%.*]] 12440 // CHECK18: cond.false: 12441 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12442 // CHECK18-NEXT: br label [[COND_END]] 12443 // CHECK18: cond.end: 12444 // CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 12445 // CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 12446 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 12447 // CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 12448 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 12449 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12450 // CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 12451 // CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 12452 // CHECK18: omp.dispatch.body: 12453 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12454 // CHECK18: omp.inner.for.cond: 12455 // CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 12456 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12457 // CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 12458 // CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12459 // CHECK18: omp.inner.for.body: 12460 // CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 12461 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 12462 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 12463 // CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 12464 // CHECK18-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 12465 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 12466 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 12467 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 12468 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 12469 // CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 12470 // CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 12471 // CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 12472 // CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 12473 // CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 12474 // CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 12475 // CHECK18-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 12476 // CHECK18-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 12477 // CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 12478 // CHECK18-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 12479 // CHECK18-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 12480 // CHECK18-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 12481 // CHECK18-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 12482 // CHECK18-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 12483 // CHECK18-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 12484 // CHECK18-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 12485 // CHECK18-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 12486 // CHECK18-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 12487 // CHECK18-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 12488 // CHECK18-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 12489 // CHECK18-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 12490 // CHECK18-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 12491 // CHECK18-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 12492 // CHECK18-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 12493 // CHECK18-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 12494 // CHECK18-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 12495 // CHECK18-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 12496 // CHECK18-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 12497 // CHECK18-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 12498 // CHECK18-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 12499 // CHECK18-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 12500 // CHECK18-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 12501 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12502 // CHECK18: omp.body.continue: 12503 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12504 // CHECK18: omp.inner.for.inc: 12505 // CHECK18-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 12506 // CHECK18-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 12507 // CHECK18-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 12508 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] 12509 // CHECK18: omp.inner.for.end: 12510 // CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 12511 // CHECK18: omp.dispatch.inc: 12512 // CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 12513 // CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 12514 // CHECK18-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 12515 // CHECK18-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 12516 // CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12517 // CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 12518 // CHECK18-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 12519 // CHECK18-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 12520 // CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] 12521 // CHECK18: omp.dispatch.end: 12522 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 12523 // CHECK18-NEXT: ret void 12524 // 12525 // 12526 // CHECK18-LABEL: define {{[^@]+}}@_Z3bari 12527 // CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 12528 // CHECK18-NEXT: entry: 12529 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12530 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 12531 // CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 12532 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12533 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 12534 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 12535 // CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 12536 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 12537 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 12538 // CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 12539 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 12540 // CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 12541 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 12542 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 12543 // CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 12544 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 12545 // CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 12546 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 12547 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 12548 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 12549 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 12550 // CHECK18-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 12551 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 12552 // CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 12553 // CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 12554 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 12555 // CHECK18-NEXT: ret i32 [[TMP8]] 12556 // 12557 // 12558 // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 12559 // CHECK18-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 12560 // CHECK18-NEXT: entry: 12561 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 12562 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12563 // CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 12564 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 12565 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 12566 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 12567 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 12568 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 12569 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 12570 // CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 12571 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 12572 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12573 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 12574 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 12575 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 12576 // CHECK18-NEXT: store i32 [[ADD]], i32* [[B]], align 4 12577 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 12578 // CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 12579 // CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 12580 // CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 12581 // CHECK18-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 12582 // CHECK18-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 12583 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 12584 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 12585 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 12586 // CHECK18-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 12587 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 12588 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 12589 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 12590 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12591 // CHECK18: omp_if.then: 12592 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 12593 // CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 12594 // CHECK18-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 12595 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 12596 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false) 12597 // CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12598 // CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 12599 // CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 12600 // CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12601 // CHECK18-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 12602 // CHECK18-NEXT: store double* [[A]], double** [[TMP14]], align 8 12603 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 12604 // CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 12605 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 12606 // CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 12607 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 12608 // CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 12609 // CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 12610 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 12611 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 12612 // CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 12613 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 12614 // CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 12615 // CHECK18-NEXT: store i64 2, i64* [[TMP22]], align 8 12616 // CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 12617 // CHECK18-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 12618 // CHECK18-NEXT: store i64 2, i64* [[TMP24]], align 8 12619 // CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 12620 // CHECK18-NEXT: store i8* null, i8** [[TMP25]], align 8 12621 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 12622 // CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 12623 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 12624 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 12625 // CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 12626 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 12627 // CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 12628 // CHECK18-NEXT: store i8* null, i8** [[TMP30]], align 8 12629 // CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 12630 // CHECK18-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 12631 // CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 12632 // CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 12633 // CHECK18-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 12634 // CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 12635 // CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 12636 // CHECK18-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 12637 // CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 12638 // CHECK18-NEXT: store i8* null, i8** [[TMP36]], align 8 12639 // CHECK18-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12640 // CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12641 // CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 12642 // CHECK18-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 12643 // CHECK18-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 12644 // CHECK18-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 12645 // CHECK18: omp_offload.failed: 12646 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 12647 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 12648 // CHECK18: omp_offload.cont: 12649 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 12650 // CHECK18: omp_if.else: 12651 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 12652 // CHECK18-NEXT: br label [[OMP_IF_END]] 12653 // CHECK18: omp_if.end: 12654 // CHECK18-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 12655 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 12656 // CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 12657 // CHECK18-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 12658 // CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 12659 // CHECK18-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 12660 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 12661 // CHECK18-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 12662 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 12663 // CHECK18-NEXT: ret i32 [[ADD4]] 12664 // 12665 // 12666 // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici 12667 // CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 12668 // CHECK18-NEXT: entry: 12669 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12670 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 12671 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 12672 // CHECK18-NEXT: [[AAA:%.*]] = alloca i8, align 1 12673 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 12674 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 12675 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 12676 // CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 12677 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 12678 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 12679 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 12680 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12681 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 12682 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 12683 // CHECK18-NEXT: store i8 0, i8* [[AAA]], align 1 12684 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 12685 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 12686 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 12687 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 12688 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 12689 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 12690 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 12691 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 12692 // CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 12693 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 12694 // CHECK18-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 12695 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 12696 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 12697 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 12698 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12699 // CHECK18: omp_if.then: 12700 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12701 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 12702 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 12703 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12704 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 12705 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 12706 // CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 12707 // CHECK18-NEXT: store i8* null, i8** [[TMP11]], align 8 12708 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 12709 // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 12710 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 12711 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 12712 // CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 12713 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 12714 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 12715 // CHECK18-NEXT: store i8* null, i8** [[TMP16]], align 8 12716 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 12717 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 12718 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 12719 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 12720 // CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 12721 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 12722 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 12723 // CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8 12724 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 12725 // CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 12726 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 12727 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 12728 // CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 12729 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 12730 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 12731 // CHECK18-NEXT: store i8* null, i8** [[TMP26]], align 8 12732 // CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12733 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12734 // CHECK18-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 12735 // CHECK18-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 12736 // CHECK18-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 12737 // CHECK18: omp_offload.failed: 12738 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 12739 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 12740 // CHECK18: omp_offload.cont: 12741 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 12742 // CHECK18: omp_if.else: 12743 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 12744 // CHECK18-NEXT: br label [[OMP_IF_END]] 12745 // CHECK18: omp_if.end: 12746 // CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 12747 // CHECK18-NEXT: ret i32 [[TMP31]] 12748 // 12749 // 12750 // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 12751 // CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 12752 // CHECK18-NEXT: entry: 12753 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12754 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 12755 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 12756 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 12757 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 12758 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 12759 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 12760 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 12761 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 12762 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12763 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 12764 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 12765 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 12766 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 12767 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 12768 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 12769 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 12770 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 12771 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 12772 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 12773 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 12774 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 12775 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12776 // CHECK18: omp_if.then: 12777 // CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12778 // CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 12779 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 12780 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12781 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 12782 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 12783 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 12784 // CHECK18-NEXT: store i8* null, i8** [[TMP9]], align 8 12785 // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 12786 // CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 12787 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 12788 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 12789 // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 12790 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 12791 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 12792 // CHECK18-NEXT: store i8* null, i8** [[TMP14]], align 8 12793 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 12794 // CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 12795 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 12796 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 12797 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 12798 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 12799 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 12800 // CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 12801 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12802 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12803 // CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 12804 // CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 12805 // CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 12806 // CHECK18: omp_offload.failed: 12807 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 12808 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 12809 // CHECK18: omp_offload.cont: 12810 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 12811 // CHECK18: omp_if.else: 12812 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 12813 // CHECK18-NEXT: br label [[OMP_IF_END]] 12814 // CHECK18: omp_if.end: 12815 // CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 12816 // CHECK18-NEXT: ret i32 [[TMP24]] 12817 // 12818 // 12819 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 12820 // CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 12821 // CHECK18-NEXT: entry: 12822 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 12823 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 12824 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 12825 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 12826 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 12827 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 12828 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 12829 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 12830 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 12831 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 12832 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 12833 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 12834 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 12835 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 12836 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 12837 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 12838 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 12839 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 12840 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 12841 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 12842 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 12843 // CHECK18-NEXT: ret void 12844 // 12845 // 12846 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..10 12847 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 12848 // CHECK18-NEXT: entry: 12849 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 12850 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 12851 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 12852 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 12853 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 12854 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 12855 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 12856 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 12857 // CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8 12858 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 12859 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 12860 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 12861 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12862 // CHECK18-NEXT: [[IT:%.*]] = alloca i64, align 8 12863 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 12864 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 12865 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 12866 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 12867 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 12868 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 12869 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 12870 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 12871 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 12872 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 12873 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 12874 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 12875 // CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 12876 // CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 12877 // CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 12878 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12879 // CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 12880 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 12881 // CHECK18-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 12882 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 12883 // CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 12884 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12885 // CHECK18: cond.true: 12886 // CHECK18-NEXT: br label [[COND_END:%.*]] 12887 // CHECK18: cond.false: 12888 // CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 12889 // CHECK18-NEXT: br label [[COND_END]] 12890 // CHECK18: cond.end: 12891 // CHECK18-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 12892 // CHECK18-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 12893 // CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 12894 // CHECK18-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 12895 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12896 // CHECK18: omp.inner.for.cond: 12897 // CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 12898 // CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 12899 // CHECK18-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 12900 // CHECK18-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12901 // CHECK18: omp.inner.for.body: 12902 // CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 12903 // CHECK18-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 12904 // CHECK18-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 12905 // CHECK18-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 12906 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 12907 // CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 12908 // CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 12909 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 12910 // CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 12911 // CHECK18-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 12912 // CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 12913 // CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 12914 // CHECK18-NEXT: store double [[INC]], double* [[A5]], align 8 12915 // CHECK18-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 12916 // CHECK18-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 12917 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 12918 // CHECK18-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 12919 // CHECK18-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 12920 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12921 // CHECK18: omp.body.continue: 12922 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12923 // CHECK18: omp.inner.for.inc: 12924 // CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 12925 // CHECK18-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 12926 // CHECK18-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 12927 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] 12928 // CHECK18: omp.inner.for.end: 12929 // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12930 // CHECK18: omp.loop.exit: 12931 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 12932 // CHECK18-NEXT: ret void 12933 // 12934 // 12935 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 12936 // CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 12937 // CHECK18-NEXT: entry: 12938 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12939 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 12940 // CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 12941 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 12942 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 12943 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 12944 // CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 12945 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12946 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 12947 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 12948 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 12949 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12950 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 12951 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 12952 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 12953 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 12954 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 12955 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 12956 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 12957 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 12958 // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 12959 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 12960 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 12961 // CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 12962 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 12963 // CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 12964 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 12965 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 12966 // CHECK18-NEXT: ret void 12967 // 12968 // 12969 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..13 12970 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 12971 // CHECK18-NEXT: entry: 12972 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 12973 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 12974 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12975 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 12976 // CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 12977 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 12978 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 12979 // CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 12980 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 12981 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 12982 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12983 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 12984 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 12985 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 12986 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12987 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 12988 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 12989 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 12990 // CHECK18-NEXT: ret void 12991 // 12992 // 12993 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 12994 // CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 12995 // CHECK18-NEXT: entry: 12996 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12997 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 12998 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 12999 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 13000 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 13001 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 13002 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13003 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 13004 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 13005 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13006 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 13007 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 13008 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 13009 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 13010 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 13011 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 13012 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 13013 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 13014 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 13015 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 13016 // CHECK18-NEXT: ret void 13017 // 13018 // 13019 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..16 13020 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 13021 // CHECK18-NEXT: entry: 13022 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13023 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13024 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 13025 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13026 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 13027 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 13028 // CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8 13029 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 13030 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 13031 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 13032 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 13033 // CHECK18-NEXT: [[I:%.*]] = alloca i64, align 8 13034 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13035 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13036 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 13037 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13038 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 13039 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 13040 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13041 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 13042 // CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 13043 // CHECK18-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 13044 // CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 13045 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 13046 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 13047 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 13048 // CHECK18-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 13049 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 13050 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 13051 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 13052 // CHECK18: cond.true: 13053 // CHECK18-NEXT: br label [[COND_END:%.*]] 13054 // CHECK18: cond.false: 13055 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 13056 // CHECK18-NEXT: br label [[COND_END]] 13057 // CHECK18: cond.end: 13058 // CHECK18-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 13059 // CHECK18-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 13060 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 13061 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 13062 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 13063 // CHECK18: omp.inner.for.cond: 13064 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13065 // CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 13066 // CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 13067 // CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 13068 // CHECK18: omp.inner.for.body: 13069 // CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13070 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 13071 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 13072 // CHECK18-NEXT: store i64 [[ADD]], i64* [[I]], align 8 13073 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 13074 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 13075 // CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 13076 // CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 13077 // CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 13078 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 13079 // CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 13080 // CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 13081 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 13082 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 13083 // CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 13084 // CHECK18-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 13085 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 13086 // CHECK18: omp.body.continue: 13087 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 13088 // CHECK18: omp.inner.for.inc: 13089 // CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13090 // CHECK18-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 13091 // CHECK18-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 13092 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] 13093 // CHECK18: omp.inner.for.end: 13094 // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 13095 // CHECK18: omp.loop.exit: 13096 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 13097 // CHECK18-NEXT: ret void 13098 // 13099 // 13100 // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 13101 // CHECK18-SAME: () #[[ATTR6]] { 13102 // CHECK18-NEXT: entry: 13103 // CHECK18-NEXT: call void @__tgt_register_requires(i64 1) 13104 // CHECK18-NEXT: ret void 13105 // 13106 // 13107 // CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv 13108 // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { 13109 // CHECK19-NEXT: entry: 13110 // CHECK19-NEXT: ret i64 0 13111 // 13112 // 13113 // CHECK19-LABEL: define {{[^@]+}}@_Z3fooi 13114 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 13115 // CHECK19-NEXT: entry: 13116 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 13117 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 13118 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 13119 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 4 13120 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 13121 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 13122 // CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 13123 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 13124 // CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 13125 // CHECK19-NEXT: [[K:%.*]] = alloca i64, align 8 13126 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13127 // CHECK19-NEXT: [[LIN:%.*]] = alloca i32, align 4 13128 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 13129 // CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 13130 // CHECK19-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 13131 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 13132 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 13133 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 13134 // CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 13135 // CHECK19-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 13136 // CHECK19-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 13137 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 13138 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 13139 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 13140 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 13141 // CHECK19-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 13142 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 13143 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4 13144 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4 13145 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4 13146 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 13147 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 13148 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 13149 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 13150 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 13151 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 13152 // CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 13153 // CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 13154 // CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 13155 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 13156 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 13157 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 13158 // CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 13159 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 13160 // CHECK19-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 13161 // CHECK19-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 13162 // CHECK19-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 13163 // CHECK19: omp_offload.failed: 13164 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 13165 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 13166 // CHECK19: omp_offload.cont: 13167 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 13168 // CHECK19-NEXT: store i64 [[CALL]], i64* [[K]], align 8 13169 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 13170 // CHECK19-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 13171 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4 13172 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR4]] 13173 // CHECK19-NEXT: store i32 12, i32* [[LIN]], align 4 13174 // CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 13175 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 13176 // CHECK19-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 13177 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4 13178 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4 13179 // CHECK19-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4 13180 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 13181 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 13182 // CHECK19-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4 13183 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4 13184 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 13185 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 13186 // CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4 13187 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 13188 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 13189 // CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4 13190 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 13191 // CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 13192 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 13193 // CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 13194 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4 13195 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 13196 // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 13197 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4 13198 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 13199 // CHECK19-NEXT: store i8* null, i8** [[TMP24]], align 4 13200 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 13201 // CHECK19-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 13202 // CHECK19-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4 13203 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 13204 // CHECK19-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 13205 // CHECK19-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4 13206 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 13207 // CHECK19-NEXT: store i8* null, i8** [[TMP29]], align 4 13208 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 13209 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 13210 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 13211 // CHECK19-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 13212 // CHECK19-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 13213 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 13214 // CHECK19-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4 13215 // CHECK19-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 13216 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 13217 // CHECK19-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4 13218 // CHECK19-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 13219 // CHECK19-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 13220 // CHECK19-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 13221 // CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 13222 // CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 13223 // CHECK19-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4 13224 // CHECK19-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 13225 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false) 13226 // CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 13227 // CHECK19-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 13228 // CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 13229 // CHECK19-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8* 13230 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 13231 // CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 13232 // CHECK19-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8* 13233 // CHECK19-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8* 13234 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false) 13235 // CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 13236 // CHECK19-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8* 13237 // CHECK19-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8* 13238 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false) 13239 // CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 13240 // CHECK19-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 13241 // CHECK19-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4 13242 // CHECK19-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) 13243 // CHECK19-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 13244 // CHECK19-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4 13245 // CHECK19-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4 13246 // CHECK19-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 13247 // CHECK19-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 13248 // CHECK19-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2 13249 // CHECK19-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 13250 // CHECK19-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4 13251 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10 13252 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 13253 // CHECK19: omp_if.then: 13254 // CHECK19-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 13255 // CHECK19-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* 13256 // CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4 13257 // CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 13258 // CHECK19-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32* 13259 // CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4 13260 // CHECK19-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 13261 // CHECK19-NEXT: store i8* null, i8** [[TMP66]], align 4 13262 // CHECK19-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 13263 // CHECK19-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32* 13264 // CHECK19-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4 13265 // CHECK19-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 13266 // CHECK19-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32* 13267 // CHECK19-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4 13268 // CHECK19-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 13269 // CHECK19-NEXT: store i8* null, i8** [[TMP71]], align 4 13270 // CHECK19-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 13271 // CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 13272 // CHECK19-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 13273 // CHECK19-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0 13274 // CHECK19-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 13275 // CHECK19: omp_offload.failed9: 13276 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 13277 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT10]] 13278 // CHECK19: omp_offload.cont10: 13279 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 13280 // CHECK19: omp_if.else: 13281 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 13282 // CHECK19-NEXT: br label [[OMP_IF_END]] 13283 // CHECK19: omp_if.end: 13284 // CHECK19-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4 13285 // CHECK19-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4 13286 // CHECK19-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4 13287 // CHECK19-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4 13288 // CHECK19-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4 13289 // CHECK19-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 13290 // CHECK19-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 13291 // CHECK19-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 13292 // CHECK19-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4 13293 // CHECK19-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20 13294 // CHECK19-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]] 13295 // CHECK19: omp_if.then13: 13296 // CHECK19-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4 13297 // CHECK19-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64 13298 // CHECK19-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]] 13299 // CHECK19-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8 13300 // CHECK19-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64 13301 // CHECK19-NEXT: [[TMP87:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 13302 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP87]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i32 80, i1 false) 13303 // CHECK19-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 13304 // CHECK19-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32* 13305 // CHECK19-NEXT: store i32 [[TMP78]], i32* [[TMP89]], align 4 13306 // CHECK19-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 13307 // CHECK19-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32* 13308 // CHECK19-NEXT: store i32 [[TMP78]], i32* [[TMP91]], align 4 13309 // CHECK19-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 13310 // CHECK19-NEXT: store i8* null, i8** [[TMP92]], align 4 13311 // CHECK19-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 13312 // CHECK19-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]** 13313 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4 13314 // CHECK19-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 13315 // CHECK19-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 13316 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4 13317 // CHECK19-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 13318 // CHECK19-NEXT: store i8* null, i8** [[TMP97]], align 4 13319 // CHECK19-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 13320 // CHECK19-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* 13321 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP99]], align 4 13322 // CHECK19-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 13323 // CHECK19-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32* 13324 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP101]], align 4 13325 // CHECK19-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 13326 // CHECK19-NEXT: store i8* null, i8** [[TMP102]], align 4 13327 // CHECK19-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 13328 // CHECK19-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to float** 13329 // CHECK19-NEXT: store float* [[VLA]], float** [[TMP104]], align 4 13330 // CHECK19-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 13331 // CHECK19-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** 13332 // CHECK19-NEXT: store float* [[VLA]], float** [[TMP106]], align 4 13333 // CHECK19-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 13334 // CHECK19-NEXT: store i64 [[TMP83]], i64* [[TMP107]], align 4 13335 // CHECK19-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 13336 // CHECK19-NEXT: store i8* null, i8** [[TMP108]], align 4 13337 // CHECK19-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 13338 // CHECK19-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to [5 x [10 x double]]** 13339 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP110]], align 4 13340 // CHECK19-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 13341 // CHECK19-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** 13342 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4 13343 // CHECK19-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 13344 // CHECK19-NEXT: store i8* null, i8** [[TMP113]], align 4 13345 // CHECK19-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 13346 // CHECK19-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32* 13347 // CHECK19-NEXT: store i32 5, i32* [[TMP115]], align 4 13348 // CHECK19-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 13349 // CHECK19-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32* 13350 // CHECK19-NEXT: store i32 5, i32* [[TMP117]], align 4 13351 // CHECK19-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 13352 // CHECK19-NEXT: store i8* null, i8** [[TMP118]], align 4 13353 // CHECK19-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 13354 // CHECK19-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32* 13355 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP120]], align 4 13356 // CHECK19-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 13357 // CHECK19-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32* 13358 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP122]], align 4 13359 // CHECK19-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 13360 // CHECK19-NEXT: store i8* null, i8** [[TMP123]], align 4 13361 // CHECK19-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 13362 // CHECK19-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to double** 13363 // CHECK19-NEXT: store double* [[VLA1]], double** [[TMP125]], align 4 13364 // CHECK19-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 13365 // CHECK19-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** 13366 // CHECK19-NEXT: store double* [[VLA1]], double** [[TMP127]], align 4 13367 // CHECK19-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 13368 // CHECK19-NEXT: store i64 [[TMP86]], i64* [[TMP128]], align 4 13369 // CHECK19-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 13370 // CHECK19-NEXT: store i8* null, i8** [[TMP129]], align 4 13371 // CHECK19-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 13372 // CHECK19-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to %struct.TT** 13373 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP131]], align 4 13374 // CHECK19-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 13375 // CHECK19-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT** 13376 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 4 13377 // CHECK19-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 13378 // CHECK19-NEXT: store i8* null, i8** [[TMP134]], align 4 13379 // CHECK19-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 13380 // CHECK19-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to i32* 13381 // CHECK19-NEXT: store i32 [[TMP80]], i32* [[TMP136]], align 4 13382 // CHECK19-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 13383 // CHECK19-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i32* 13384 // CHECK19-NEXT: store i32 [[TMP80]], i32* [[TMP138]], align 4 13385 // CHECK19-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 13386 // CHECK19-NEXT: store i8* null, i8** [[TMP139]], align 4 13387 // CHECK19-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 13388 // CHECK19-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 13389 // CHECK19-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 13390 // CHECK19-NEXT: [[TMP143:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP140]], i8** [[TMP141]], i64* [[TMP142]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 13391 // CHECK19-NEXT: [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 0 13392 // CHECK19-NEXT: br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] 13393 // CHECK19: omp_offload.failed17: 13394 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 13395 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT18]] 13396 // CHECK19: omp_offload.cont18: 13397 // CHECK19-NEXT: br label [[OMP_IF_END20:%.*]] 13398 // CHECK19: omp_if.else19: 13399 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 13400 // CHECK19-NEXT: br label [[OMP_IF_END20]] 13401 // CHECK19: omp_if.end20: 13402 // CHECK19-NEXT: [[TMP145:%.*]] = load i32, i32* [[A]], align 4 13403 // CHECK19-NEXT: [[TMP146:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 13404 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP146]]) 13405 // CHECK19-NEXT: ret i32 [[TMP145]] 13406 // 13407 // 13408 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 13409 // CHECK19-SAME: () #[[ATTR2:[0-9]+]] { 13410 // CHECK19-NEXT: entry: 13411 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 13412 // CHECK19-NEXT: ret void 13413 // 13414 // 13415 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 13416 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 13417 // CHECK19-NEXT: entry: 13418 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13419 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13420 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 13421 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 13422 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 13423 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 13424 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 13425 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 13426 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 13427 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13428 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13429 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 13430 // CHECK19-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 13431 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 13432 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 13433 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 13434 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 13435 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 13436 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 13437 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 13438 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 13439 // CHECK19: cond.true: 13440 // CHECK19-NEXT: br label [[COND_END:%.*]] 13441 // CHECK19: cond.false: 13442 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 13443 // CHECK19-NEXT: br label [[COND_END]] 13444 // CHECK19: cond.end: 13445 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 13446 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 13447 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 13448 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 13449 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 13450 // CHECK19: omp.inner.for.cond: 13451 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 13452 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 13453 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 13454 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 13455 // CHECK19: omp.inner.for.body: 13456 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 13457 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 13458 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 13459 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 13460 // CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 13461 // CHECK19-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 13462 // CHECK19-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 13463 // CHECK19: .cancel.exit: 13464 // CHECK19-NEXT: br label [[CANCEL_EXIT:%.*]] 13465 // CHECK19: .cancel.continue: 13466 // CHECK19-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 13467 // CHECK19-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 13468 // CHECK19-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 13469 // CHECK19: .cancel.exit2: 13470 // CHECK19-NEXT: br label [[CANCEL_EXIT]] 13471 // CHECK19: .cancel.continue3: 13472 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 13473 // CHECK19: omp.body.continue: 13474 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 13475 // CHECK19: omp.inner.for.inc: 13476 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 13477 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 13478 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 13479 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 13480 // CHECK19: omp.inner.for.end: 13481 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 13482 // CHECK19: omp.loop.exit: 13483 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 13484 // CHECK19-NEXT: br label [[CANCEL_CONT:%.*]] 13485 // CHECK19: cancel.cont: 13486 // CHECK19-NEXT: ret void 13487 // CHECK19: cancel.exit: 13488 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 13489 // CHECK19-NEXT: br label [[CANCEL_CONT]] 13490 // 13491 // 13492 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 13493 // CHECK19-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 13494 // CHECK19-NEXT: entry: 13495 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13496 // CHECK19-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 13497 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13498 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13499 // CHECK19-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 13500 // CHECK19-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 13501 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 13502 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 13503 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 13504 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) 13505 // CHECK19-NEXT: ret void 13506 // 13507 // 13508 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 13509 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 13510 // CHECK19-NEXT: entry: 13511 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13512 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13513 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13514 // CHECK19-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 13515 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 13516 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 13517 // CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 13518 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 13519 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 13520 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 13521 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 13522 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 13523 // CHECK19-NEXT: [[K1:%.*]] = alloca i64, align 8 13524 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13525 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13526 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13527 // CHECK19-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 13528 // CHECK19-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 13529 // CHECK19-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 13530 // CHECK19-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 13531 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 13532 // CHECK19-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 13533 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 13534 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 13535 // CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 13536 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 13537 // CHECK19-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 13538 // CHECK19-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 13539 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 13540 // CHECK19: omp.dispatch.cond: 13541 // CHECK19-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 13542 // CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 13543 // CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 13544 // CHECK19: omp.dispatch.body: 13545 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 13546 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 13547 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 13548 // CHECK19: omp.inner.for.cond: 13549 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 13550 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 13551 // CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 13552 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 13553 // CHECK19: omp.inner.for.body: 13554 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 13555 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 13556 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 13557 // CHECK19-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13 13558 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !13 13559 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 13560 // CHECK19-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 13561 // CHECK19-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 13562 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 13563 // CHECK19-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13 13564 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !13 13565 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 13566 // CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13 13567 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 13568 // CHECK19: omp.body.continue: 13569 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 13570 // CHECK19: omp.inner.for.inc: 13571 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 13572 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 13573 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 13574 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 13575 // CHECK19: omp.inner.for.end: 13576 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 13577 // CHECK19: omp.dispatch.inc: 13578 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 13579 // CHECK19: omp.dispatch.end: 13580 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 13581 // CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 13582 // CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 13583 // CHECK19: .omp.linear.pu: 13584 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[K1]], align 8 13585 // CHECK19-NEXT: store i64 [[TMP15]], i64* [[TMP0]], align 8 13586 // CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 13587 // CHECK19: .omp.linear.pu.done: 13588 // CHECK19-NEXT: ret void 13589 // 13590 // 13591 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 13592 // CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 13593 // CHECK19-NEXT: entry: 13594 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13595 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 13596 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13597 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 13598 // CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 13599 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13600 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13601 // CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 13602 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13603 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13604 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 13605 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 13606 // CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 13607 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 13608 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 13609 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 13610 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 13611 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 13612 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 13613 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 13614 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 13615 // CHECK19-NEXT: ret void 13616 // 13617 // 13618 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 13619 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 13620 // CHECK19-NEXT: entry: 13621 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13622 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13623 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13624 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 13625 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13626 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 13627 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 13628 // CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 13629 // CHECK19-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 13630 // CHECK19-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 13631 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 13632 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 13633 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 13634 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 13635 // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 13636 // CHECK19-NEXT: [[LIN2:%.*]] = alloca i32, align 4 13637 // CHECK19-NEXT: [[A3:%.*]] = alloca i32, align 4 13638 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13639 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13640 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13641 // CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 13642 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13643 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13644 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 13645 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 13646 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 13647 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 13648 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 13649 // CHECK19-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 13650 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 13651 // CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 13652 // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 13653 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 13654 // CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 13655 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 13656 // CHECK19-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 13657 // CHECK19-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 13658 // CHECK19-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 13659 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 13660 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 13661 // CHECK19: cond.true: 13662 // CHECK19-NEXT: br label [[COND_END:%.*]] 13663 // CHECK19: cond.false: 13664 // CHECK19-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 13665 // CHECK19-NEXT: br label [[COND_END]] 13666 // CHECK19: cond.end: 13667 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 13668 // CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 13669 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 13670 // CHECK19-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 13671 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 13672 // CHECK19: omp.inner.for.cond: 13673 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13674 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 13675 // CHECK19-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 13676 // CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 13677 // CHECK19: omp.inner.for.body: 13678 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13679 // CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 13680 // CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 13681 // CHECK19-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 13682 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 13683 // CHECK19-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 13684 // CHECK19-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13685 // CHECK19-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 13686 // CHECK19-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 13687 // CHECK19-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 13688 // CHECK19-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 13689 // CHECK19-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 13690 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 13691 // CHECK19-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 13692 // CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13693 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 13694 // CHECK19-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 13695 // CHECK19-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 13696 // CHECK19-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 13697 // CHECK19-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 13698 // CHECK19-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 13699 // CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 13700 // CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 13701 // CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 13702 // CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 13703 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 13704 // CHECK19: omp.body.continue: 13705 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 13706 // CHECK19: omp.inner.for.inc: 13707 // CHECK19-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13708 // CHECK19-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 13709 // CHECK19-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 13710 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 13711 // CHECK19: omp.inner.for.end: 13712 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 13713 // CHECK19: omp.loop.exit: 13714 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 13715 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 13716 // CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 13717 // CHECK19-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 13718 // CHECK19: .omp.linear.pu: 13719 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 13720 // CHECK19-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 13721 // CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 13722 // CHECK19-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 13723 // CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 13724 // CHECK19: .omp.linear.pu.done: 13725 // CHECK19-NEXT: ret void 13726 // 13727 // 13728 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map. 13729 // CHECK19-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 13730 // CHECK19-NEXT: entry: 13731 // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 13732 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 13733 // CHECK19-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 13734 // CHECK19-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 13735 // CHECK19-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 13736 // CHECK19-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 13737 // CHECK19-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 13738 // CHECK19-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 13739 // CHECK19-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 13740 // CHECK19-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 13741 // CHECK19-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 13742 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 13743 // CHECK19-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 13744 // CHECK19-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 13745 // CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 13746 // CHECK19-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 13747 // CHECK19-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 13748 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 13749 // CHECK19-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 13750 // CHECK19-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 13751 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 13752 // CHECK19-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 13753 // CHECK19-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 13754 // CHECK19-NEXT: ret void 13755 // 13756 // 13757 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. 13758 // CHECK19-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 13759 // CHECK19-NEXT: entry: 13760 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 13761 // CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 13762 // CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 13763 // CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 13764 // CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 13765 // CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 13766 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 13767 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 13768 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 13769 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 13770 // CHECK19-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 13771 // CHECK19-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4 13772 // CHECK19-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4 13773 // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 13774 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 13775 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 13776 // CHECK19-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 13777 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 13778 // CHECK19-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 13779 // CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 13780 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 13781 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 13782 // CHECK19-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 13783 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 13784 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 13785 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 13786 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 13787 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 13788 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 13789 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 13790 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 13791 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 13792 // CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 13793 // CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 13794 // CHECK19-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 13795 // CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 13796 // CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 13797 // CHECK19-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 13798 // CHECK19-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 13799 // CHECK19-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 13800 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 13801 // CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 13802 // CHECK19-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 13803 // CHECK19-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 13804 // CHECK19-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 13805 // CHECK19-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 13806 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 13807 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 13808 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 13809 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 13810 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 13811 // CHECK19-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 13812 // CHECK19-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 13813 // CHECK19-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 13814 // CHECK19: omp_offload.failed.i: 13815 // CHECK19-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 13816 // CHECK19-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 13817 // CHECK19-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25 13818 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 13819 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 13820 // CHECK19-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25 13821 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !25 13822 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 13823 // CHECK19-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25 13824 // CHECK19-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !25 13825 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR4]] 13826 // CHECK19-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 13827 // CHECK19: .omp_outlined..3.exit: 13828 // CHECK19-NEXT: ret i32 0 13829 // 13830 // 13831 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 13832 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 13833 // CHECK19-NEXT: entry: 13834 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13835 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13836 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13837 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 13838 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13839 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13840 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13841 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 13842 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 13843 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 13844 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 13845 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 13846 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 13847 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 13848 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 13849 // CHECK19-NEXT: ret void 13850 // 13851 // 13852 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 13853 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 13854 // CHECK19-NEXT: entry: 13855 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13856 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13857 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13858 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13859 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 13860 // CHECK19-NEXT: [[TMP:%.*]] = alloca i16, align 2 13861 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 13862 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 13863 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 13864 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 13865 // CHECK19-NEXT: [[IT:%.*]] = alloca i16, align 2 13866 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13867 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13868 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13869 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13870 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13871 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 13872 // CHECK19-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 13873 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 13874 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 13875 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 13876 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 13877 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 13878 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 13879 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 13880 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 13881 // CHECK19: cond.true: 13882 // CHECK19-NEXT: br label [[COND_END:%.*]] 13883 // CHECK19: cond.false: 13884 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 13885 // CHECK19-NEXT: br label [[COND_END]] 13886 // CHECK19: cond.end: 13887 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 13888 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 13889 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 13890 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 13891 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 13892 // CHECK19: omp.inner.for.cond: 13893 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 13894 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 13895 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 13896 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 13897 // CHECK19: omp.inner.for.body: 13898 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 13899 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 13900 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 13901 // CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 13902 // CHECK19-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 13903 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 13904 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 13905 // CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 13906 // CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 13907 // CHECK19-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 13908 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 13909 // CHECK19-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 13910 // CHECK19-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 13911 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 13912 // CHECK19: omp.body.continue: 13913 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 13914 // CHECK19: omp.inner.for.inc: 13915 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 13916 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 13917 // CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 13918 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 13919 // CHECK19: omp.inner.for.end: 13920 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 13921 // CHECK19: omp.loop.exit: 13922 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 13923 // CHECK19-NEXT: ret void 13924 // 13925 // 13926 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 13927 // CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 13928 // CHECK19-NEXT: entry: 13929 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13930 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 13931 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 13932 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 13933 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 13934 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 13935 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 13936 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 13937 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 13938 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 13939 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13940 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 13941 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13942 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 13943 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 13944 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 13945 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 13946 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 13947 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 13948 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 13949 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 13950 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 13951 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 13952 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 13953 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 13954 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 13955 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 13956 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 13957 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 13958 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 13959 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 13960 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 13961 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 13962 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 13963 // CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 13964 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 13965 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 13966 // CHECK19-NEXT: ret void 13967 // 13968 // 13969 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 13970 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 13971 // CHECK19-NEXT: entry: 13972 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13973 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13974 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13975 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 13976 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 13977 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 13978 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 13979 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 13980 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 13981 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 13982 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 13983 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 13984 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 13985 // CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1 13986 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 13987 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 13988 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 13989 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 13990 // CHECK19-NEXT: [[IT:%.*]] = alloca i8, align 1 13991 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13992 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13993 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13994 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 13995 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 13996 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 13997 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 13998 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 13999 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 14000 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 14001 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 14002 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 14003 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 14004 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14005 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 14006 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 14007 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 14008 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 14009 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 14010 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 14011 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 14012 // CHECK19-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 14013 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 14014 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 14015 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 14016 // CHECK19-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 14017 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 14018 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 14019 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 14020 // CHECK19: omp.dispatch.cond: 14021 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 14022 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 14023 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 14024 // CHECK19: cond.true: 14025 // CHECK19-NEXT: br label [[COND_END:%.*]] 14026 // CHECK19: cond.false: 14027 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 14028 // CHECK19-NEXT: br label [[COND_END]] 14029 // CHECK19: cond.end: 14030 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 14031 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 14032 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 14033 // CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 14034 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 14035 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 14036 // CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 14037 // CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 14038 // CHECK19: omp.dispatch.body: 14039 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 14040 // CHECK19: omp.inner.for.cond: 14041 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 14042 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 14043 // CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 14044 // CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 14045 // CHECK19: omp.inner.for.body: 14046 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 14047 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 14048 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 14049 // CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 14050 // CHECK19-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 14051 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 14052 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 14053 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 14054 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 14055 // CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 14056 // CHECK19-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 14057 // CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 14058 // CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 14059 // CHECK19-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 14060 // CHECK19-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 14061 // CHECK19-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 14062 // CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 14063 // CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 14064 // CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 14065 // CHECK19-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 14066 // CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 14067 // CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 14068 // CHECK19-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 14069 // CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 14070 // CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 14071 // CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 14072 // CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 14073 // CHECK19-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 14074 // CHECK19-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 14075 // CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 14076 // CHECK19-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 14077 // CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 14078 // CHECK19-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 14079 // CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 14080 // CHECK19-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 14081 // CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 14082 // CHECK19-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 14083 // CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 14084 // CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 14085 // CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 14086 // CHECK19-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 14087 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 14088 // CHECK19: omp.body.continue: 14089 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 14090 // CHECK19: omp.inner.for.inc: 14091 // CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 14092 // CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 14093 // CHECK19-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 14094 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 14095 // CHECK19: omp.inner.for.end: 14096 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 14097 // CHECK19: omp.dispatch.inc: 14098 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 14099 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 14100 // CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 14101 // CHECK19-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 14102 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 14103 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 14104 // CHECK19-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 14105 // CHECK19-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 14106 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 14107 // CHECK19: omp.dispatch.end: 14108 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 14109 // CHECK19-NEXT: ret void 14110 // 14111 // 14112 // CHECK19-LABEL: define {{[^@]+}}@_Z3bari 14113 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 14114 // CHECK19-NEXT: entry: 14115 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 14116 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 14117 // CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 14118 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 14119 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 14120 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 14121 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 14122 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 14123 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 14124 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 14125 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 14126 // CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 14127 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 14128 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 14129 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 14130 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 14131 // CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 14132 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 14133 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 14134 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 14135 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 14136 // CHECK19-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 14137 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 14138 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 14139 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 14140 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 14141 // CHECK19-NEXT: ret i32 [[TMP8]] 14142 // 14143 // 14144 // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 14145 // CHECK19-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 14146 // CHECK19-NEXT: entry: 14147 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 14148 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 14149 // CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 14150 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 14151 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 14152 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 14153 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 14154 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 14155 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 14156 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 14157 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 14158 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 14159 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 14160 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 14161 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 14162 // CHECK19-NEXT: store i32 [[ADD]], i32* [[B]], align 4 14163 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 14164 // CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 14165 // CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 14166 // CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 14167 // CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 14168 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 14169 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 14170 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 14171 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 14172 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 14173 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 14174 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 14175 // CHECK19: omp_if.then: 14176 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 14177 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 14178 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 14179 // CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 14180 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 14181 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false) 14182 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14183 // CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 14184 // CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 14185 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14186 // CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 14187 // CHECK19-NEXT: store double* [[A]], double** [[TMP14]], align 4 14188 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 14189 // CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 14190 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 14191 // CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 14192 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 14193 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 14194 // CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 14195 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 14196 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 14197 // CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 14198 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 14199 // CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 14200 // CHECK19-NEXT: store i32 2, i32* [[TMP22]], align 4 14201 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 14202 // CHECK19-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 14203 // CHECK19-NEXT: store i32 2, i32* [[TMP24]], align 4 14204 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 14205 // CHECK19-NEXT: store i8* null, i8** [[TMP25]], align 4 14206 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 14207 // CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 14208 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 14209 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 14210 // CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 14211 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 14212 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 14213 // CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 14214 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 14215 // CHECK19-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 14216 // CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 14217 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 14218 // CHECK19-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 14219 // CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 14220 // CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 14221 // CHECK19-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 14222 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 14223 // CHECK19-NEXT: store i8* null, i8** [[TMP36]], align 4 14224 // CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14225 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14226 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 14227 // CHECK19-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 14228 // CHECK19-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 14229 // CHECK19-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 14230 // CHECK19: omp_offload.failed: 14231 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 14232 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 14233 // CHECK19: omp_offload.cont: 14234 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 14235 // CHECK19: omp_if.else: 14236 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 14237 // CHECK19-NEXT: br label [[OMP_IF_END]] 14238 // CHECK19: omp_if.end: 14239 // CHECK19-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 14240 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 14241 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 14242 // CHECK19-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 14243 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 14244 // CHECK19-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 14245 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 14246 // CHECK19-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 14247 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 14248 // CHECK19-NEXT: ret i32 [[ADD3]] 14249 // 14250 // 14251 // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici 14252 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 14253 // CHECK19-NEXT: entry: 14254 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 14255 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 14256 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 14257 // CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1 14258 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 14259 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14260 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14261 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 14262 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 14263 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 14264 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 14265 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 14266 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 14267 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 14268 // CHECK19-NEXT: store i8 0, i8* [[AAA]], align 1 14269 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 14270 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 14271 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 14272 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 14273 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14274 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 14275 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14276 // CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 14277 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 14278 // CHECK19-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 14279 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 14280 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 14281 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 14282 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 14283 // CHECK19: omp_if.then: 14284 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14285 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 14286 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 14287 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14288 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 14289 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 14290 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 14291 // CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4 14292 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 14293 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 14294 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 14295 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 14296 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 14297 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 14298 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 14299 // CHECK19-NEXT: store i8* null, i8** [[TMP16]], align 4 14300 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 14301 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 14302 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 14303 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 14304 // CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 14305 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 14306 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 14307 // CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 14308 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 14309 // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 14310 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 14311 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 14312 // CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 14313 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 14314 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 14315 // CHECK19-NEXT: store i8* null, i8** [[TMP26]], align 4 14316 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14317 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14318 // CHECK19-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 14319 // CHECK19-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 14320 // CHECK19-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 14321 // CHECK19: omp_offload.failed: 14322 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 14323 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 14324 // CHECK19: omp_offload.cont: 14325 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 14326 // CHECK19: omp_if.else: 14327 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 14328 // CHECK19-NEXT: br label [[OMP_IF_END]] 14329 // CHECK19: omp_if.end: 14330 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 14331 // CHECK19-NEXT: ret i32 [[TMP31]] 14332 // 14333 // 14334 // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 14335 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 14336 // CHECK19-NEXT: entry: 14337 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 14338 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 14339 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 14340 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 14341 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14342 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14343 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 14344 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 14345 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 14346 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 14347 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 14348 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 14349 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 14350 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 14351 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 14352 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 14353 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14354 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 14355 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14356 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 14357 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 14358 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 14359 // CHECK19: omp_if.then: 14360 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14361 // CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 14362 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 14363 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14364 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 14365 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 14366 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 14367 // CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4 14368 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 14369 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 14370 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 14371 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 14372 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 14373 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 14374 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 14375 // CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4 14376 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 14377 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 14378 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 14379 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 14380 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 14381 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 14382 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 14383 // CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 14384 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14385 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14386 // CHECK19-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 14387 // CHECK19-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 14388 // CHECK19-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 14389 // CHECK19: omp_offload.failed: 14390 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 14391 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 14392 // CHECK19: omp_offload.cont: 14393 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 14394 // CHECK19: omp_if.else: 14395 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 14396 // CHECK19-NEXT: br label [[OMP_IF_END]] 14397 // CHECK19: omp_if.end: 14398 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 14399 // CHECK19-NEXT: ret i32 [[TMP24]] 14400 // 14401 // 14402 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 14403 // CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 14404 // CHECK19-NEXT: entry: 14405 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 14406 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 14407 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 14408 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 14409 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 14410 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 14411 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 14412 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 14413 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 14414 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 14415 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 14416 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 14417 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14418 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 14419 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 14420 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 14421 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 14422 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 14423 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 14424 // CHECK19-NEXT: ret void 14425 // 14426 // 14427 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10 14428 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 14429 // CHECK19-NEXT: entry: 14430 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14431 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14432 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 14433 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 14434 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 14435 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 14436 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 14437 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 14438 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 14439 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 14440 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 14441 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 14442 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 14443 // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 14444 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14445 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14446 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 14447 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 14448 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 14449 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 14450 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 14451 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 14452 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14453 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 14454 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 14455 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 14456 // CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 14457 // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 14458 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 14459 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 14460 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 14461 // CHECK19-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 14462 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 14463 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 14464 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 14465 // CHECK19: cond.true: 14466 // CHECK19-NEXT: br label [[COND_END:%.*]] 14467 // CHECK19: cond.false: 14468 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 14469 // CHECK19-NEXT: br label [[COND_END]] 14470 // CHECK19: cond.end: 14471 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 14472 // CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 14473 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 14474 // CHECK19-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 14475 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 14476 // CHECK19: omp.inner.for.cond: 14477 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 14478 // CHECK19-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 14479 // CHECK19-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 14480 // CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 14481 // CHECK19: omp.inner.for.body: 14482 // CHECK19-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 14483 // CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 14484 // CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 14485 // CHECK19-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 14486 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 14487 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 14488 // CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 14489 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 14490 // CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 14491 // CHECK19-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 14492 // CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 14493 // CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 14494 // CHECK19-NEXT: store double [[INC]], double* [[A4]], align 4 14495 // CHECK19-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 14496 // CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 14497 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 14498 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 14499 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 14500 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 14501 // CHECK19: omp.body.continue: 14502 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 14503 // CHECK19: omp.inner.for.inc: 14504 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 14505 // CHECK19-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 14506 // CHECK19-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 14507 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 14508 // CHECK19: omp.inner.for.end: 14509 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 14510 // CHECK19: omp.loop.exit: 14511 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 14512 // CHECK19-NEXT: ret void 14513 // 14514 // 14515 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 14516 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 14517 // CHECK19-NEXT: entry: 14518 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14519 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14520 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 14521 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 14522 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14523 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14524 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 14525 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14526 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14527 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 14528 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 14529 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14530 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 14531 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 14532 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 14533 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 14534 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 14535 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 14536 // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14537 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 14538 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14539 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 14540 // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 14541 // CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 14542 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 14543 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 14544 // CHECK19-NEXT: ret void 14545 // 14546 // 14547 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..13 14548 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 14549 // CHECK19-NEXT: entry: 14550 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14551 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14552 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14553 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14554 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 14555 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 14556 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 14557 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 14558 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14559 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14560 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14561 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14562 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 14563 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 14564 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14565 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 14566 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 14567 // CHECK19-NEXT: ret void 14568 // 14569 // 14570 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 14571 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 14572 // CHECK19-NEXT: entry: 14573 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14574 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14575 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 14576 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14577 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14578 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14579 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14580 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 14581 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14582 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 14583 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 14584 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 14585 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 14586 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 14587 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14588 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 14589 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14590 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 14591 // CHECK19-NEXT: ret void 14592 // 14593 // 14594 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..16 14595 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 14596 // CHECK19-NEXT: entry: 14597 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14598 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14599 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14600 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14601 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 14602 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 14603 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 14604 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 14605 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 14606 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 14607 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 14608 // CHECK19-NEXT: [[I:%.*]] = alloca i64, align 8 14609 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14610 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14611 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14612 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14613 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 14614 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14615 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 14616 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 14617 // CHECK19-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 14618 // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 14619 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 14620 // CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 14621 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 14622 // CHECK19-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 14623 // CHECK19-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 14624 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 14625 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 14626 // CHECK19: cond.true: 14627 // CHECK19-NEXT: br label [[COND_END:%.*]] 14628 // CHECK19: cond.false: 14629 // CHECK19-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 14630 // CHECK19-NEXT: br label [[COND_END]] 14631 // CHECK19: cond.end: 14632 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 14633 // CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 14634 // CHECK19-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 14635 // CHECK19-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 14636 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 14637 // CHECK19: omp.inner.for.cond: 14638 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 14639 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 14640 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 14641 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 14642 // CHECK19: omp.inner.for.body: 14643 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 14644 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 14645 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 14646 // CHECK19-NEXT: store i64 [[ADD]], i64* [[I]], align 8 14647 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 14648 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 14649 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 14650 // CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 14651 // CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 14652 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 14653 // CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 14654 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 14655 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 14656 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 14657 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 14658 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 14659 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 14660 // CHECK19: omp.body.continue: 14661 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 14662 // CHECK19: omp.inner.for.inc: 14663 // CHECK19-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 14664 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 14665 // CHECK19-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 14666 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 14667 // CHECK19: omp.inner.for.end: 14668 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 14669 // CHECK19: omp.loop.exit: 14670 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 14671 // CHECK19-NEXT: ret void 14672 // 14673 // 14674 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 14675 // CHECK19-SAME: () #[[ATTR6]] { 14676 // CHECK19-NEXT: entry: 14677 // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) 14678 // CHECK19-NEXT: ret void 14679 // 14680 // 14681 // CHECK20-LABEL: define {{[^@]+}}@_Z7get_valv 14682 // CHECK20-SAME: () #[[ATTR0:[0-9]+]] { 14683 // CHECK20-NEXT: entry: 14684 // CHECK20-NEXT: ret i64 0 14685 // 14686 // 14687 // CHECK20-LABEL: define {{[^@]+}}@_Z3fooi 14688 // CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 14689 // CHECK20-NEXT: entry: 14690 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 14691 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 14692 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 14693 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x float], align 4 14694 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 14695 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 14696 // CHECK20-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 14697 // CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 14698 // CHECK20-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 14699 // CHECK20-NEXT: [[K:%.*]] = alloca i64, align 8 14700 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14701 // CHECK20-NEXT: [[LIN:%.*]] = alloca i32, align 4 14702 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14703 // CHECK20-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 14704 // CHECK20-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 14705 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 14706 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 14707 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 14708 // CHECK20-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 14709 // CHECK20-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 14710 // CHECK20-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 14711 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 14712 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 14713 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 14714 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 14715 // CHECK20-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 14716 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 14717 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4 14718 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4 14719 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4 14720 // CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 14721 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 14722 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 14723 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 14724 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 14725 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 14726 // CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 14727 // CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 14728 // CHECK20-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 14729 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 14730 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 14731 // CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 14732 // CHECK20-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 14733 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 14734 // CHECK20-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 14735 // CHECK20-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 14736 // CHECK20-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 14737 // CHECK20: omp_offload.failed: 14738 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 14739 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 14740 // CHECK20: omp_offload.cont: 14741 // CHECK20-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 14742 // CHECK20-NEXT: store i64 [[CALL]], i64* [[K]], align 8 14743 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 14744 // CHECK20-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 14745 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4 14746 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR4]] 14747 // CHECK20-NEXT: store i32 12, i32* [[LIN]], align 4 14748 // CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 14749 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14750 // CHECK20-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 14751 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14752 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4 14753 // CHECK20-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4 14754 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 14755 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 14756 // CHECK20-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4 14757 // CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4 14758 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14759 // CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 14760 // CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4 14761 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14762 // CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 14763 // CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4 14764 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 14765 // CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 14766 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 14767 // CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 14768 // CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4 14769 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 14770 // CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 14771 // CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4 14772 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 14773 // CHECK20-NEXT: store i8* null, i8** [[TMP24]], align 4 14774 // CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 14775 // CHECK20-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 14776 // CHECK20-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4 14777 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 14778 // CHECK20-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 14779 // CHECK20-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4 14780 // CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 14781 // CHECK20-NEXT: store i8* null, i8** [[TMP29]], align 4 14782 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14783 // CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14784 // CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 14785 // CHECK20-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 14786 // CHECK20-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 14787 // CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 14788 // CHECK20-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4 14789 // CHECK20-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 14790 // CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 14791 // CHECK20-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4 14792 // CHECK20-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 14793 // CHECK20-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 14794 // CHECK20-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 14795 // CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 14796 // CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 14797 // CHECK20-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4 14798 // CHECK20-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 14799 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false) 14800 // CHECK20-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 14801 // CHECK20-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 14802 // CHECK20-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 14803 // CHECK20-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8* 14804 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 14805 // CHECK20-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 14806 // CHECK20-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8* 14807 // CHECK20-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8* 14808 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false) 14809 // CHECK20-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 14810 // CHECK20-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8* 14811 // CHECK20-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8* 14812 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false) 14813 // CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 14814 // CHECK20-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 14815 // CHECK20-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4 14816 // CHECK20-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) 14817 // CHECK20-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 14818 // CHECK20-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4 14819 // CHECK20-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4 14820 // CHECK20-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 14821 // CHECK20-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 14822 // CHECK20-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2 14823 // CHECK20-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 14824 // CHECK20-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4 14825 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10 14826 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 14827 // CHECK20: omp_if.then: 14828 // CHECK20-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 14829 // CHECK20-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* 14830 // CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4 14831 // CHECK20-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 14832 // CHECK20-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32* 14833 // CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4 14834 // CHECK20-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 14835 // CHECK20-NEXT: store i8* null, i8** [[TMP66]], align 4 14836 // CHECK20-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 14837 // CHECK20-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32* 14838 // CHECK20-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4 14839 // CHECK20-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 14840 // CHECK20-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32* 14841 // CHECK20-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4 14842 // CHECK20-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 14843 // CHECK20-NEXT: store i8* null, i8** [[TMP71]], align 4 14844 // CHECK20-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 14845 // CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 14846 // CHECK20-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 14847 // CHECK20-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0 14848 // CHECK20-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 14849 // CHECK20: omp_offload.failed9: 14850 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 14851 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT10]] 14852 // CHECK20: omp_offload.cont10: 14853 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 14854 // CHECK20: omp_if.else: 14855 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 14856 // CHECK20-NEXT: br label [[OMP_IF_END]] 14857 // CHECK20: omp_if.end: 14858 // CHECK20-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4 14859 // CHECK20-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4 14860 // CHECK20-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4 14861 // CHECK20-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4 14862 // CHECK20-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4 14863 // CHECK20-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 14864 // CHECK20-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 14865 // CHECK20-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 14866 // CHECK20-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4 14867 // CHECK20-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20 14868 // CHECK20-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]] 14869 // CHECK20: omp_if.then13: 14870 // CHECK20-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4 14871 // CHECK20-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64 14872 // CHECK20-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]] 14873 // CHECK20-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8 14874 // CHECK20-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64 14875 // CHECK20-NEXT: [[TMP87:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 14876 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP87]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i32 80, i1 false) 14877 // CHECK20-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 14878 // CHECK20-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32* 14879 // CHECK20-NEXT: store i32 [[TMP78]], i32* [[TMP89]], align 4 14880 // CHECK20-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 14881 // CHECK20-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32* 14882 // CHECK20-NEXT: store i32 [[TMP78]], i32* [[TMP91]], align 4 14883 // CHECK20-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 14884 // CHECK20-NEXT: store i8* null, i8** [[TMP92]], align 4 14885 // CHECK20-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 14886 // CHECK20-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]** 14887 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4 14888 // CHECK20-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 14889 // CHECK20-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 14890 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4 14891 // CHECK20-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 14892 // CHECK20-NEXT: store i8* null, i8** [[TMP97]], align 4 14893 // CHECK20-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 14894 // CHECK20-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* 14895 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP99]], align 4 14896 // CHECK20-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 14897 // CHECK20-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32* 14898 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP101]], align 4 14899 // CHECK20-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 14900 // CHECK20-NEXT: store i8* null, i8** [[TMP102]], align 4 14901 // CHECK20-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 14902 // CHECK20-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to float** 14903 // CHECK20-NEXT: store float* [[VLA]], float** [[TMP104]], align 4 14904 // CHECK20-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 14905 // CHECK20-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** 14906 // CHECK20-NEXT: store float* [[VLA]], float** [[TMP106]], align 4 14907 // CHECK20-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 14908 // CHECK20-NEXT: store i64 [[TMP83]], i64* [[TMP107]], align 4 14909 // CHECK20-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 14910 // CHECK20-NEXT: store i8* null, i8** [[TMP108]], align 4 14911 // CHECK20-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 14912 // CHECK20-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to [5 x [10 x double]]** 14913 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP110]], align 4 14914 // CHECK20-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 14915 // CHECK20-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** 14916 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4 14917 // CHECK20-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 14918 // CHECK20-NEXT: store i8* null, i8** [[TMP113]], align 4 14919 // CHECK20-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 14920 // CHECK20-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32* 14921 // CHECK20-NEXT: store i32 5, i32* [[TMP115]], align 4 14922 // CHECK20-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 14923 // CHECK20-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32* 14924 // CHECK20-NEXT: store i32 5, i32* [[TMP117]], align 4 14925 // CHECK20-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 14926 // CHECK20-NEXT: store i8* null, i8** [[TMP118]], align 4 14927 // CHECK20-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 14928 // CHECK20-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32* 14929 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP120]], align 4 14930 // CHECK20-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 14931 // CHECK20-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32* 14932 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP122]], align 4 14933 // CHECK20-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 14934 // CHECK20-NEXT: store i8* null, i8** [[TMP123]], align 4 14935 // CHECK20-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 14936 // CHECK20-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to double** 14937 // CHECK20-NEXT: store double* [[VLA1]], double** [[TMP125]], align 4 14938 // CHECK20-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 14939 // CHECK20-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** 14940 // CHECK20-NEXT: store double* [[VLA1]], double** [[TMP127]], align 4 14941 // CHECK20-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 14942 // CHECK20-NEXT: store i64 [[TMP86]], i64* [[TMP128]], align 4 14943 // CHECK20-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 14944 // CHECK20-NEXT: store i8* null, i8** [[TMP129]], align 4 14945 // CHECK20-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 14946 // CHECK20-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to %struct.TT** 14947 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP131]], align 4 14948 // CHECK20-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 14949 // CHECK20-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT** 14950 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 4 14951 // CHECK20-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 14952 // CHECK20-NEXT: store i8* null, i8** [[TMP134]], align 4 14953 // CHECK20-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 14954 // CHECK20-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to i32* 14955 // CHECK20-NEXT: store i32 [[TMP80]], i32* [[TMP136]], align 4 14956 // CHECK20-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 14957 // CHECK20-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i32* 14958 // CHECK20-NEXT: store i32 [[TMP80]], i32* [[TMP138]], align 4 14959 // CHECK20-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 14960 // CHECK20-NEXT: store i8* null, i8** [[TMP139]], align 4 14961 // CHECK20-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 14962 // CHECK20-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 14963 // CHECK20-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 14964 // CHECK20-NEXT: [[TMP143:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP140]], i8** [[TMP141]], i64* [[TMP142]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 14965 // CHECK20-NEXT: [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 0 14966 // CHECK20-NEXT: br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] 14967 // CHECK20: omp_offload.failed17: 14968 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 14969 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT18]] 14970 // CHECK20: omp_offload.cont18: 14971 // CHECK20-NEXT: br label [[OMP_IF_END20:%.*]] 14972 // CHECK20: omp_if.else19: 14973 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 14974 // CHECK20-NEXT: br label [[OMP_IF_END20]] 14975 // CHECK20: omp_if.end20: 14976 // CHECK20-NEXT: [[TMP145:%.*]] = load i32, i32* [[A]], align 4 14977 // CHECK20-NEXT: [[TMP146:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 14978 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP146]]) 14979 // CHECK20-NEXT: ret i32 [[TMP145]] 14980 // 14981 // 14982 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 14983 // CHECK20-SAME: () #[[ATTR2:[0-9]+]] { 14984 // CHECK20-NEXT: entry: 14985 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 14986 // CHECK20-NEXT: ret void 14987 // 14988 // 14989 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. 14990 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 14991 // CHECK20-NEXT: entry: 14992 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14993 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14994 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 14995 // CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 14996 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 14997 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 14998 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 14999 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 15000 // CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 15001 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15002 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15003 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 15004 // CHECK20-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 15005 // CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 15006 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 15007 // CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 15008 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 15009 // CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 15010 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15011 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 15012 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 15013 // CHECK20: cond.true: 15014 // CHECK20-NEXT: br label [[COND_END:%.*]] 15015 // CHECK20: cond.false: 15016 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15017 // CHECK20-NEXT: br label [[COND_END]] 15018 // CHECK20: cond.end: 15019 // CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 15020 // CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 15021 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 15022 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 15023 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 15024 // CHECK20: omp.inner.for.cond: 15025 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15026 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15027 // CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 15028 // CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 15029 // CHECK20: omp.inner.for.body: 15030 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15031 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 15032 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 15033 // CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 15034 // CHECK20-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 15035 // CHECK20-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 15036 // CHECK20-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 15037 // CHECK20: .cancel.exit: 15038 // CHECK20-NEXT: br label [[CANCEL_EXIT:%.*]] 15039 // CHECK20: .cancel.continue: 15040 // CHECK20-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 15041 // CHECK20-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 15042 // CHECK20-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 15043 // CHECK20: .cancel.exit2: 15044 // CHECK20-NEXT: br label [[CANCEL_EXIT]] 15045 // CHECK20: .cancel.continue3: 15046 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 15047 // CHECK20: omp.body.continue: 15048 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 15049 // CHECK20: omp.inner.for.inc: 15050 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15051 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 15052 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 15053 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] 15054 // CHECK20: omp.inner.for.end: 15055 // CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 15056 // CHECK20: omp.loop.exit: 15057 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 15058 // CHECK20-NEXT: br label [[CANCEL_CONT:%.*]] 15059 // CHECK20: cancel.cont: 15060 // CHECK20-NEXT: ret void 15061 // CHECK20: cancel.exit: 15062 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 15063 // CHECK20-NEXT: br label [[CANCEL_CONT]] 15064 // 15065 // 15066 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 15067 // CHECK20-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 15068 // CHECK20-NEXT: entry: 15069 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15070 // CHECK20-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 15071 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 15072 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15073 // CHECK20-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 15074 // CHECK20-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 15075 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 15076 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 15077 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 15078 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) 15079 // CHECK20-NEXT: ret void 15080 // 15081 // 15082 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 15083 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 15084 // CHECK20-NEXT: entry: 15085 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15086 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15087 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15088 // CHECK20-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 15089 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 15090 // CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 15091 // CHECK20-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 15092 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 15093 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 15094 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 15095 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 15096 // CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 15097 // CHECK20-NEXT: [[K1:%.*]] = alloca i64, align 8 15098 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15099 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15100 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15101 // CHECK20-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 15102 // CHECK20-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 15103 // CHECK20-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 15104 // CHECK20-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 15105 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 15106 // CHECK20-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 15107 // CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 15108 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 15109 // CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 15110 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 15111 // CHECK20-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 15112 // CHECK20-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 15113 // CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 15114 // CHECK20: omp.dispatch.cond: 15115 // CHECK20-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 15116 // CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 15117 // CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 15118 // CHECK20: omp.dispatch.body: 15119 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 15120 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 15121 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 15122 // CHECK20: omp.inner.for.cond: 15123 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 15124 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 15125 // CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 15126 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 15127 // CHECK20: omp.inner.for.body: 15128 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 15129 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 15130 // CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 15131 // CHECK20-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13 15132 // CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !13 15133 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 15134 // CHECK20-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 15135 // CHECK20-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 15136 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 15137 // CHECK20-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13 15138 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !13 15139 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 15140 // CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13 15141 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 15142 // CHECK20: omp.body.continue: 15143 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 15144 // CHECK20: omp.inner.for.inc: 15145 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 15146 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 15147 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 15148 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 15149 // CHECK20: omp.inner.for.end: 15150 // CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 15151 // CHECK20: omp.dispatch.inc: 15152 // CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] 15153 // CHECK20: omp.dispatch.end: 15154 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 15155 // CHECK20-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 15156 // CHECK20-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 15157 // CHECK20: .omp.linear.pu: 15158 // CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[K1]], align 8 15159 // CHECK20-NEXT: store i64 [[TMP15]], i64* [[TMP0]], align 8 15160 // CHECK20-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 15161 // CHECK20: .omp.linear.pu.done: 15162 // CHECK20-NEXT: ret void 15163 // 15164 // 15165 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 15166 // CHECK20-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 15167 // CHECK20-NEXT: entry: 15168 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 15169 // CHECK20-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 15170 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15171 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 15172 // CHECK20-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 15173 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 15174 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 15175 // CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 15176 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15177 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 15178 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 15179 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 15180 // CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 15181 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 15182 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 15183 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 15184 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 15185 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 15186 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 15187 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 15188 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 15189 // CHECK20-NEXT: ret void 15190 // 15191 // 15192 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 15193 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 15194 // CHECK20-NEXT: entry: 15195 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15196 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15197 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 15198 // CHECK20-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 15199 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15200 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 15201 // CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 15202 // CHECK20-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 15203 // CHECK20-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 15204 // CHECK20-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 15205 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 15206 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 15207 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 15208 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 15209 // CHECK20-NEXT: [[IT:%.*]] = alloca i64, align 8 15210 // CHECK20-NEXT: [[LIN2:%.*]] = alloca i32, align 4 15211 // CHECK20-NEXT: [[A3:%.*]] = alloca i32, align 4 15212 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15213 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15214 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 15215 // CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 15216 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15217 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 15218 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 15219 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 15220 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 15221 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 15222 // CHECK20-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 15223 // CHECK20-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 15224 // CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 15225 // CHECK20-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 15226 // CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 15227 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 15228 // CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 15229 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 15230 // CHECK20-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 15231 // CHECK20-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 15232 // CHECK20-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 15233 // CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 15234 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 15235 // CHECK20: cond.true: 15236 // CHECK20-NEXT: br label [[COND_END:%.*]] 15237 // CHECK20: cond.false: 15238 // CHECK20-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 15239 // CHECK20-NEXT: br label [[COND_END]] 15240 // CHECK20: cond.end: 15241 // CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 15242 // CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 15243 // CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 15244 // CHECK20-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 15245 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 15246 // CHECK20: omp.inner.for.cond: 15247 // CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 15248 // CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 15249 // CHECK20-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 15250 // CHECK20-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 15251 // CHECK20: omp.inner.for.body: 15252 // CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 15253 // CHECK20-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 15254 // CHECK20-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 15255 // CHECK20-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 15256 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 15257 // CHECK20-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 15258 // CHECK20-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 15259 // CHECK20-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 15260 // CHECK20-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 15261 // CHECK20-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 15262 // CHECK20-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 15263 // CHECK20-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 15264 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 15265 // CHECK20-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 15266 // CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 15267 // CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 15268 // CHECK20-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 15269 // CHECK20-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 15270 // CHECK20-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 15271 // CHECK20-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 15272 // CHECK20-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 15273 // CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 15274 // CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 15275 // CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 15276 // CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 15277 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 15278 // CHECK20: omp.body.continue: 15279 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 15280 // CHECK20: omp.inner.for.inc: 15281 // CHECK20-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 15282 // CHECK20-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 15283 // CHECK20-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 15284 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] 15285 // CHECK20: omp.inner.for.end: 15286 // CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 15287 // CHECK20: omp.loop.exit: 15288 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 15289 // CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 15290 // CHECK20-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 15291 // CHECK20-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 15292 // CHECK20: .omp.linear.pu: 15293 // CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 15294 // CHECK20-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 15295 // CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 15296 // CHECK20-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 15297 // CHECK20-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 15298 // CHECK20: .omp.linear.pu.done: 15299 // CHECK20-NEXT: ret void 15300 // 15301 // 15302 // CHECK20-LABEL: define {{[^@]+}}@.omp_task_privates_map. 15303 // CHECK20-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 15304 // CHECK20-NEXT: entry: 15305 // CHECK20-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 15306 // CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 15307 // CHECK20-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 15308 // CHECK20-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 15309 // CHECK20-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 15310 // CHECK20-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 15311 // CHECK20-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 15312 // CHECK20-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 15313 // CHECK20-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 15314 // CHECK20-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 15315 // CHECK20-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 15316 // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 15317 // CHECK20-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 15318 // CHECK20-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 15319 // CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 15320 // CHECK20-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 15321 // CHECK20-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 15322 // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 15323 // CHECK20-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 15324 // CHECK20-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 15325 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 15326 // CHECK20-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 15327 // CHECK20-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 15328 // CHECK20-NEXT: ret void 15329 // 15330 // 15331 // CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry. 15332 // CHECK20-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 15333 // CHECK20-NEXT: entry: 15334 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 15335 // CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 15336 // CHECK20-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 15337 // CHECK20-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 15338 // CHECK20-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 15339 // CHECK20-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 15340 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 15341 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 15342 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 15343 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 15344 // CHECK20-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 15345 // CHECK20-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4 15346 // CHECK20-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4 15347 // CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 15348 // CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 15349 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 15350 // CHECK20-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 15351 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 15352 // CHECK20-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 15353 // CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 15354 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 15355 // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 15356 // CHECK20-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 15357 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 15358 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 15359 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 15360 // CHECK20-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 15361 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 15362 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 15363 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 15364 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 15365 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 15366 // CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 15367 // CHECK20-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 15368 // CHECK20-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 15369 // CHECK20-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 15370 // CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 15371 // CHECK20-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 15372 // CHECK20-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 15373 // CHECK20-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 15374 // CHECK20-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 15375 // CHECK20-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 15376 // CHECK20-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 15377 // CHECK20-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 15378 // CHECK20-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 15379 // CHECK20-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 15380 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 15381 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 15382 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 15383 // CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 15384 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 15385 // CHECK20-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 15386 // CHECK20-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 15387 // CHECK20-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 15388 // CHECK20: omp_offload.failed.i: 15389 // CHECK20-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 15390 // CHECK20-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 15391 // CHECK20-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25 15392 // CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 15393 // CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 15394 // CHECK20-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25 15395 // CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !25 15396 // CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 15397 // CHECK20-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25 15398 // CHECK20-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !25 15399 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR4]] 15400 // CHECK20-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 15401 // CHECK20: .omp_outlined..3.exit: 15402 // CHECK20-NEXT: ret i32 0 15403 // 15404 // 15405 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 15406 // CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 15407 // CHECK20-NEXT: entry: 15408 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15409 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 15410 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 15411 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 15412 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15413 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 15414 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 15415 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 15416 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 15417 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 15418 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 15419 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 15420 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 15421 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 15422 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 15423 // CHECK20-NEXT: ret void 15424 // 15425 // 15426 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 15427 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 15428 // CHECK20-NEXT: entry: 15429 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15430 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15431 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15432 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 15433 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 15434 // CHECK20-NEXT: [[TMP:%.*]] = alloca i16, align 2 15435 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 15436 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 15437 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 15438 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 15439 // CHECK20-NEXT: [[IT:%.*]] = alloca i16, align 2 15440 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15441 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15442 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15443 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 15444 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 15445 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 15446 // CHECK20-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 15447 // CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 15448 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 15449 // CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 15450 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 15451 // CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 15452 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15453 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 15454 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 15455 // CHECK20: cond.true: 15456 // CHECK20-NEXT: br label [[COND_END:%.*]] 15457 // CHECK20: cond.false: 15458 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15459 // CHECK20-NEXT: br label [[COND_END]] 15460 // CHECK20: cond.end: 15461 // CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 15462 // CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 15463 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 15464 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 15465 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 15466 // CHECK20: omp.inner.for.cond: 15467 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15468 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15469 // CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 15470 // CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 15471 // CHECK20: omp.inner.for.body: 15472 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15473 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 15474 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 15475 // CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 15476 // CHECK20-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 15477 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 15478 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 15479 // CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 15480 // CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 15481 // CHECK20-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 15482 // CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 15483 // CHECK20-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 15484 // CHECK20-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 15485 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 15486 // CHECK20: omp.body.continue: 15487 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 15488 // CHECK20: omp.inner.for.inc: 15489 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15490 // CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 15491 // CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 15492 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] 15493 // CHECK20: omp.inner.for.end: 15494 // CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 15495 // CHECK20: omp.loop.exit: 15496 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 15497 // CHECK20-NEXT: ret void 15498 // 15499 // 15500 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 15501 // CHECK20-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 15502 // CHECK20-NEXT: entry: 15503 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15504 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 15505 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 15506 // CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 15507 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 15508 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 15509 // CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 15510 // CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 15511 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 15512 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 15513 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 15514 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 15515 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15516 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 15517 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 15518 // CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 15519 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 15520 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 15521 // CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 15522 // CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 15523 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 15524 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 15525 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 15526 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 15527 // CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 15528 // CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 15529 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 15530 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 15531 // CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 15532 // CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 15533 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 15534 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 15535 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 15536 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 15537 // CHECK20-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 15538 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 15539 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 15540 // CHECK20-NEXT: ret void 15541 // 15542 // 15543 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 15544 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 15545 // CHECK20-NEXT: entry: 15546 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15547 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15548 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15549 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 15550 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 15551 // CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 15552 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 15553 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 15554 // CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 15555 // CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 15556 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 15557 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 15558 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 15559 // CHECK20-NEXT: [[TMP:%.*]] = alloca i8, align 1 15560 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 15561 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 15562 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 15563 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 15564 // CHECK20-NEXT: [[IT:%.*]] = alloca i8, align 1 15565 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15566 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15567 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15568 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 15569 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 15570 // CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 15571 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 15572 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 15573 // CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 15574 // CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 15575 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 15576 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 15577 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 15578 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 15579 // CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 15580 // CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 15581 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 15582 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 15583 // CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 15584 // CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 15585 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 15586 // CHECK20-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 15587 // CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 15588 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 15589 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 15590 // CHECK20-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 15591 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 15592 // CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 15593 // CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 15594 // CHECK20: omp.dispatch.cond: 15595 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15596 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 15597 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 15598 // CHECK20: cond.true: 15599 // CHECK20-NEXT: br label [[COND_END:%.*]] 15600 // CHECK20: cond.false: 15601 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15602 // CHECK20-NEXT: br label [[COND_END]] 15603 // CHECK20: cond.end: 15604 // CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 15605 // CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 15606 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 15607 // CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 15608 // CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15609 // CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15610 // CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 15611 // CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 15612 // CHECK20: omp.dispatch.body: 15613 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 15614 // CHECK20: omp.inner.for.cond: 15615 // CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15616 // CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15617 // CHECK20-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 15618 // CHECK20-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 15619 // CHECK20: omp.inner.for.body: 15620 // CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15621 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 15622 // CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 15623 // CHECK20-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 15624 // CHECK20-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 15625 // CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 15626 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 15627 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 15628 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 15629 // CHECK20-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 15630 // CHECK20-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 15631 // CHECK20-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 15632 // CHECK20-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 15633 // CHECK20-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 15634 // CHECK20-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 15635 // CHECK20-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 15636 // CHECK20-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 15637 // CHECK20-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 15638 // CHECK20-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 15639 // CHECK20-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 15640 // CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 15641 // CHECK20-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 15642 // CHECK20-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 15643 // CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 15644 // CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 15645 // CHECK20-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 15646 // CHECK20-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 15647 // CHECK20-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 15648 // CHECK20-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 15649 // CHECK20-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 15650 // CHECK20-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 15651 // CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 15652 // CHECK20-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 15653 // CHECK20-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 15654 // CHECK20-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 15655 // CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 15656 // CHECK20-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 15657 // CHECK20-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 15658 // CHECK20-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 15659 // CHECK20-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 15660 // CHECK20-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 15661 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 15662 // CHECK20: omp.body.continue: 15663 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 15664 // CHECK20: omp.inner.for.inc: 15665 // CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15666 // CHECK20-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 15667 // CHECK20-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 15668 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] 15669 // CHECK20: omp.inner.for.end: 15670 // CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 15671 // CHECK20: omp.dispatch.inc: 15672 // CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 15673 // CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 15674 // CHECK20-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 15675 // CHECK20-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 15676 // CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15677 // CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 15678 // CHECK20-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 15679 // CHECK20-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 15680 // CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] 15681 // CHECK20: omp.dispatch.end: 15682 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 15683 // CHECK20-NEXT: ret void 15684 // 15685 // 15686 // CHECK20-LABEL: define {{[^@]+}}@_Z3bari 15687 // CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 15688 // CHECK20-NEXT: entry: 15689 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15690 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 15691 // CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 15692 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15693 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 15694 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 15695 // CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 15696 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 15697 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 15698 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 15699 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 15700 // CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 15701 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 15702 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 15703 // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 15704 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 15705 // CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 15706 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 15707 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 15708 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 15709 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 15710 // CHECK20-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 15711 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 15712 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 15713 // CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 15714 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 15715 // CHECK20-NEXT: ret i32 [[TMP8]] 15716 // 15717 // 15718 // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 15719 // CHECK20-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 15720 // CHECK20-NEXT: entry: 15721 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 15722 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15723 // CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 15724 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 15725 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 15726 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 15727 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 15728 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 15729 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 15730 // CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 15731 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 15732 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15733 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 15734 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 15735 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 15736 // CHECK20-NEXT: store i32 [[ADD]], i32* [[B]], align 4 15737 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 15738 // CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 15739 // CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 15740 // CHECK20-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 15741 // CHECK20-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 15742 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 15743 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 15744 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 15745 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 15746 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 15747 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 15748 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 15749 // CHECK20: omp_if.then: 15750 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 15751 // CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 15752 // CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 15753 // CHECK20-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 15754 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 15755 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false) 15756 // CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 15757 // CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 15758 // CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 15759 // CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 15760 // CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 15761 // CHECK20-NEXT: store double* [[A]], double** [[TMP14]], align 4 15762 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 15763 // CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 15764 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 15765 // CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 15766 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 15767 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 15768 // CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 15769 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 15770 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 15771 // CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 15772 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 15773 // CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 15774 // CHECK20-NEXT: store i32 2, i32* [[TMP22]], align 4 15775 // CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 15776 // CHECK20-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 15777 // CHECK20-NEXT: store i32 2, i32* [[TMP24]], align 4 15778 // CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 15779 // CHECK20-NEXT: store i8* null, i8** [[TMP25]], align 4 15780 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 15781 // CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 15782 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 15783 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 15784 // CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 15785 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 15786 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 15787 // CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 15788 // CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 15789 // CHECK20-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 15790 // CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 15791 // CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 15792 // CHECK20-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 15793 // CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 15794 // CHECK20-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 15795 // CHECK20-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 15796 // CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 15797 // CHECK20-NEXT: store i8* null, i8** [[TMP36]], align 4 15798 // CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 15799 // CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 15800 // CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 15801 // CHECK20-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 15802 // CHECK20-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 15803 // CHECK20-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 15804 // CHECK20: omp_offload.failed: 15805 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 15806 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 15807 // CHECK20: omp_offload.cont: 15808 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 15809 // CHECK20: omp_if.else: 15810 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 15811 // CHECK20-NEXT: br label [[OMP_IF_END]] 15812 // CHECK20: omp_if.end: 15813 // CHECK20-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 15814 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 15815 // CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 15816 // CHECK20-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 15817 // CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 15818 // CHECK20-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 15819 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 15820 // CHECK20-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 15821 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 15822 // CHECK20-NEXT: ret i32 [[ADD3]] 15823 // 15824 // 15825 // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici 15826 // CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 15827 // CHECK20-NEXT: entry: 15828 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15829 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 15830 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 15831 // CHECK20-NEXT: [[AAA:%.*]] = alloca i8, align 1 15832 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 15833 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 15834 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 15835 // CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 15836 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 15837 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 15838 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 15839 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15840 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 15841 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 15842 // CHECK20-NEXT: store i8 0, i8* [[AAA]], align 1 15843 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 15844 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 15845 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 15846 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 15847 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 15848 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 15849 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 15850 // CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 15851 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 15852 // CHECK20-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 15853 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 15854 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 15855 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 15856 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 15857 // CHECK20: omp_if.then: 15858 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 15859 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 15860 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 15861 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 15862 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 15863 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 15864 // CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 15865 // CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4 15866 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 15867 // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 15868 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 15869 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 15870 // CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 15871 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 15872 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 15873 // CHECK20-NEXT: store i8* null, i8** [[TMP16]], align 4 15874 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 15875 // CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 15876 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 15877 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 15878 // CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 15879 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 15880 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 15881 // CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 15882 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 15883 // CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 15884 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 15885 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 15886 // CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 15887 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 15888 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 15889 // CHECK20-NEXT: store i8* null, i8** [[TMP26]], align 4 15890 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 15891 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 15892 // CHECK20-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 15893 // CHECK20-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 15894 // CHECK20-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 15895 // CHECK20: omp_offload.failed: 15896 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 15897 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 15898 // CHECK20: omp_offload.cont: 15899 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 15900 // CHECK20: omp_if.else: 15901 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 15902 // CHECK20-NEXT: br label [[OMP_IF_END]] 15903 // CHECK20: omp_if.end: 15904 // CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 15905 // CHECK20-NEXT: ret i32 [[TMP31]] 15906 // 15907 // 15908 // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 15909 // CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 15910 // CHECK20-NEXT: entry: 15911 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15912 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 15913 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 15914 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 15915 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 15916 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 15917 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 15918 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 15919 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 15920 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15921 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 15922 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 15923 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 15924 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 15925 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 15926 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 15927 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 15928 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 15929 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 15930 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 15931 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 15932 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 15933 // CHECK20: omp_if.then: 15934 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 15935 // CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 15936 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 15937 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 15938 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 15939 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 15940 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 15941 // CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4 15942 // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 15943 // CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 15944 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 15945 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 15946 // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 15947 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 15948 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 15949 // CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4 15950 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 15951 // CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 15952 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 15953 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 15954 // CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 15955 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 15956 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 15957 // CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 15958 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 15959 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 15960 // CHECK20-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 15961 // CHECK20-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 15962 // CHECK20-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 15963 // CHECK20: omp_offload.failed: 15964 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 15965 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 15966 // CHECK20: omp_offload.cont: 15967 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 15968 // CHECK20: omp_if.else: 15969 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 15970 // CHECK20-NEXT: br label [[OMP_IF_END]] 15971 // CHECK20: omp_if.end: 15972 // CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 15973 // CHECK20-NEXT: ret i32 [[TMP24]] 15974 // 15975 // 15976 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 15977 // CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 15978 // CHECK20-NEXT: entry: 15979 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 15980 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 15981 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 15982 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 15983 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 15984 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 15985 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 15986 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 15987 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 15988 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 15989 // CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 15990 // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 15991 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 15992 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 15993 // CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 15994 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 15995 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 15996 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 15997 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 15998 // CHECK20-NEXT: ret void 15999 // 16000 // 16001 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..10 16002 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 16003 // CHECK20-NEXT: entry: 16004 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 16005 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 16006 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 16007 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 16008 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 16009 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 16010 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 16011 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 16012 // CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 16013 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 16014 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 16015 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 16016 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 16017 // CHECK20-NEXT: [[IT:%.*]] = alloca i64, align 8 16018 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 16019 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 16020 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 16021 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 16022 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 16023 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 16024 // CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 16025 // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 16026 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 16027 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 16028 // CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 16029 // CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 16030 // CHECK20-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 16031 // CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 16032 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 16033 // CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 16034 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 16035 // CHECK20-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 16036 // CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16037 // CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 16038 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 16039 // CHECK20: cond.true: 16040 // CHECK20-NEXT: br label [[COND_END:%.*]] 16041 // CHECK20: cond.false: 16042 // CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16043 // CHECK20-NEXT: br label [[COND_END]] 16044 // CHECK20: cond.end: 16045 // CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 16046 // CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 16047 // CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 16048 // CHECK20-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 16049 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 16050 // CHECK20: omp.inner.for.cond: 16051 // CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16052 // CHECK20-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16053 // CHECK20-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 16054 // CHECK20-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 16055 // CHECK20: omp.inner.for.body: 16056 // CHECK20-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16057 // CHECK20-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 16058 // CHECK20-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 16059 // CHECK20-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 16060 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 16061 // CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 16062 // CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 16063 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 16064 // CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 16065 // CHECK20-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 16066 // CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 16067 // CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 16068 // CHECK20-NEXT: store double [[INC]], double* [[A4]], align 4 16069 // CHECK20-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 16070 // CHECK20-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 16071 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 16072 // CHECK20-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 16073 // CHECK20-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 16074 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 16075 // CHECK20: omp.body.continue: 16076 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 16077 // CHECK20: omp.inner.for.inc: 16078 // CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16079 // CHECK20-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 16080 // CHECK20-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 16081 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] 16082 // CHECK20: omp.inner.for.end: 16083 // CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 16084 // CHECK20: omp.loop.exit: 16085 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 16086 // CHECK20-NEXT: ret void 16087 // 16088 // 16089 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 16090 // CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 16091 // CHECK20-NEXT: entry: 16092 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 16093 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 16094 // CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 16095 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 16096 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 16097 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 16098 // CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 16099 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 16100 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 16101 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 16102 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 16103 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 16104 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 16105 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 16106 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 16107 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 16108 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 16109 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 16110 // CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 16111 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 16112 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 16113 // CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 16114 // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 16115 // CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 16116 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 16117 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 16118 // CHECK20-NEXT: ret void 16119 // 16120 // 16121 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..13 16122 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 16123 // CHECK20-NEXT: entry: 16124 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 16125 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 16126 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 16127 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 16128 // CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 16129 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 16130 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 16131 // CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 16132 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 16133 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 16134 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 16135 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 16136 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 16137 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 16138 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 16139 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 16140 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 16141 // CHECK20-NEXT: ret void 16142 // 16143 // 16144 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 16145 // CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 16146 // CHECK20-NEXT: entry: 16147 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 16148 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 16149 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 16150 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 16151 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 16152 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 16153 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 16154 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 16155 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 16156 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 16157 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 16158 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 16159 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 16160 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 16161 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 16162 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 16163 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 16164 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 16165 // CHECK20-NEXT: ret void 16166 // 16167 // 16168 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..16 16169 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 16170 // CHECK20-NEXT: entry: 16171 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 16172 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 16173 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 16174 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 16175 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 16176 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 16177 // CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 16178 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 16179 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 16180 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 16181 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 16182 // CHECK20-NEXT: [[I:%.*]] = alloca i64, align 8 16183 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 16184 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 16185 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 16186 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 16187 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 16188 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 16189 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 16190 // CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 16191 // CHECK20-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 16192 // CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 16193 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 16194 // CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 16195 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 16196 // CHECK20-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 16197 // CHECK20-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16198 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 16199 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 16200 // CHECK20: cond.true: 16201 // CHECK20-NEXT: br label [[COND_END:%.*]] 16202 // CHECK20: cond.false: 16203 // CHECK20-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16204 // CHECK20-NEXT: br label [[COND_END]] 16205 // CHECK20: cond.end: 16206 // CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 16207 // CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 16208 // CHECK20-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 16209 // CHECK20-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 16210 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 16211 // CHECK20: omp.inner.for.cond: 16212 // CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16213 // CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16214 // CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 16215 // CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 16216 // CHECK20: omp.inner.for.body: 16217 // CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16218 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 16219 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 16220 // CHECK20-NEXT: store i64 [[ADD]], i64* [[I]], align 8 16221 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 16222 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 16223 // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 16224 // CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 16225 // CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 16226 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 16227 // CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 16228 // CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 16229 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 16230 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 16231 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 16232 // CHECK20-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 16233 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 16234 // CHECK20: omp.body.continue: 16235 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 16236 // CHECK20: omp.inner.for.inc: 16237 // CHECK20-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16238 // CHECK20-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 16239 // CHECK20-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 16240 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] 16241 // CHECK20: omp.inner.for.end: 16242 // CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 16243 // CHECK20: omp.loop.exit: 16244 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 16245 // CHECK20-NEXT: ret void 16246 // 16247 // 16248 // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 16249 // CHECK20-SAME: () #[[ATTR6]] { 16250 // CHECK20-NEXT: entry: 16251 // CHECK20-NEXT: call void @__tgt_register_requires(i64 1) 16252 // CHECK20-NEXT: ret void 16253 // 16254 // 16255 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 16256 // CHECK25-SAME: () #[[ATTR0:[0-9]+]] { 16257 // CHECK25-NEXT: entry: 16258 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 16259 // CHECK25-NEXT: ret void 16260 // 16261 // 16262 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. 16263 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 16264 // CHECK25-NEXT: entry: 16265 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16266 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16267 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 16268 // CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 16269 // CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 16270 // CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 16271 // CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 16272 // CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 16273 // CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 16274 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16275 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16276 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 16277 // CHECK25-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 16278 // CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 16279 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 16280 // CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 16281 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 16282 // CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 16283 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16284 // CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 16285 // CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 16286 // CHECK25: cond.true: 16287 // CHECK25-NEXT: br label [[COND_END:%.*]] 16288 // CHECK25: cond.false: 16289 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16290 // CHECK25-NEXT: br label [[COND_END]] 16291 // CHECK25: cond.end: 16292 // CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 16293 // CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 16294 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 16295 // CHECK25-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 16296 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 16297 // CHECK25: omp.inner.for.cond: 16298 // CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16299 // CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16300 // CHECK25-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 16301 // CHECK25-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 16302 // CHECK25: omp.inner.for.body: 16303 // CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16304 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 16305 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 16306 // CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 16307 // CHECK25-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 16308 // CHECK25-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 16309 // CHECK25-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 16310 // CHECK25: .cancel.exit: 16311 // CHECK25-NEXT: br label [[CANCEL_EXIT:%.*]] 16312 // CHECK25: .cancel.continue: 16313 // CHECK25-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 16314 // CHECK25-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 16315 // CHECK25-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 16316 // CHECK25: .cancel.exit2: 16317 // CHECK25-NEXT: br label [[CANCEL_EXIT]] 16318 // CHECK25: .cancel.continue3: 16319 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 16320 // CHECK25: omp.body.continue: 16321 // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 16322 // CHECK25: omp.inner.for.inc: 16323 // CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16324 // CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 16325 // CHECK25-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 16326 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] 16327 // CHECK25: omp.inner.for.end: 16328 // CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 16329 // CHECK25: omp.loop.exit: 16330 // CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 16331 // CHECK25-NEXT: br label [[CANCEL_CONT:%.*]] 16332 // CHECK25: cancel.cont: 16333 // CHECK25-NEXT: ret void 16334 // CHECK25: cancel.exit: 16335 // CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 16336 // CHECK25-NEXT: br label [[CANCEL_CONT]] 16337 // 16338 // 16339 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 16340 // CHECK25-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 16341 // CHECK25-NEXT: entry: 16342 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16343 // CHECK25-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 16344 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16345 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 16346 // CHECK25-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 16347 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 16348 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16349 // CHECK25-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 16350 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16351 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16352 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 16353 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16354 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 16355 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 16356 // CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 16357 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 16358 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 16359 // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 16360 // CHECK25-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 16361 // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 16362 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 16363 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 16364 // CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 16365 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 16366 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 16367 // CHECK25-NEXT: ret void 16368 // 16369 // 16370 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 16371 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 16372 // CHECK25-NEXT: entry: 16373 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16374 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16375 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16376 // CHECK25-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 16377 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16378 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 16379 // CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8 16380 // CHECK25-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 16381 // CHECK25-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 16382 // CHECK25-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 16383 // CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 16384 // CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 16385 // CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 16386 // CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 16387 // CHECK25-NEXT: [[IT:%.*]] = alloca i64, align 8 16388 // CHECK25-NEXT: [[LIN4:%.*]] = alloca i32, align 4 16389 // CHECK25-NEXT: [[A5:%.*]] = alloca i32, align 4 16390 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16391 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16392 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16393 // CHECK25-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 16394 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16395 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16396 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 16397 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16398 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 16399 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 16400 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 16401 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 16402 // CHECK25-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 16403 // CHECK25-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 16404 // CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 16405 // CHECK25-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 16406 // CHECK25-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 16407 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 16408 // CHECK25-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 16409 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 16410 // CHECK25-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 16411 // CHECK25-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 16412 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16413 // CHECK25-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 16414 // CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 16415 // CHECK25: cond.true: 16416 // CHECK25-NEXT: br label [[COND_END:%.*]] 16417 // CHECK25: cond.false: 16418 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16419 // CHECK25-NEXT: br label [[COND_END]] 16420 // CHECK25: cond.end: 16421 // CHECK25-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 16422 // CHECK25-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 16423 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 16424 // CHECK25-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 16425 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 16426 // CHECK25: omp.inner.for.cond: 16427 // CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16428 // CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16429 // CHECK25-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 16430 // CHECK25-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 16431 // CHECK25: omp.inner.for.body: 16432 // CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16433 // CHECK25-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 16434 // CHECK25-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 16435 // CHECK25-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 16436 // CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 16437 // CHECK25-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 16438 // CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16439 // CHECK25-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 16440 // CHECK25-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 16441 // CHECK25-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 16442 // CHECK25-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 16443 // CHECK25-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 16444 // CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 16445 // CHECK25-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 16446 // CHECK25-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16447 // CHECK25-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 16448 // CHECK25-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 16449 // CHECK25-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 16450 // CHECK25-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 16451 // CHECK25-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 16452 // CHECK25-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 16453 // CHECK25-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 16454 // CHECK25-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 16455 // CHECK25-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 16456 // CHECK25-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 16457 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 16458 // CHECK25: omp.body.continue: 16459 // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 16460 // CHECK25: omp.inner.for.inc: 16461 // CHECK25-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16462 // CHECK25-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 16463 // CHECK25-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 16464 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] 16465 // CHECK25: omp.inner.for.end: 16466 // CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 16467 // CHECK25: omp.loop.exit: 16468 // CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 16469 // CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 16470 // CHECK25-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 16471 // CHECK25-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 16472 // CHECK25: .omp.linear.pu: 16473 // CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 16474 // CHECK25-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 16475 // CHECK25-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 16476 // CHECK25-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 16477 // CHECK25-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 16478 // CHECK25: .omp.linear.pu.done: 16479 // CHECK25-NEXT: ret void 16480 // 16481 // 16482 // CHECK25-LABEL: define {{[^@]+}}@_Z7get_valv 16483 // CHECK25-SAME: () #[[ATTR3:[0-9]+]] { 16484 // CHECK25-NEXT: entry: 16485 // CHECK25-NEXT: ret i64 0 16486 // 16487 // 16488 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 16489 // CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 16490 // CHECK25-NEXT: entry: 16491 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16492 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16493 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 16494 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 16495 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16496 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16497 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16498 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16499 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 16500 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 16501 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 16502 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 16503 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 16504 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 16505 // CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 16506 // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 16507 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 16508 // CHECK25-NEXT: ret void 16509 // 16510 // 16511 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 16512 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 16513 // CHECK25-NEXT: entry: 16514 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16515 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16516 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16517 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16518 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 16519 // CHECK25-NEXT: [[TMP:%.*]] = alloca i16, align 2 16520 // CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 16521 // CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 16522 // CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 16523 // CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 16524 // CHECK25-NEXT: [[IT:%.*]] = alloca i16, align 2 16525 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16526 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16527 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16528 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16529 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16530 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16531 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 16532 // CHECK25-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 16533 // CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 16534 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 16535 // CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 16536 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 16537 // CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 16538 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16539 // CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 16540 // CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 16541 // CHECK25: cond.true: 16542 // CHECK25-NEXT: br label [[COND_END:%.*]] 16543 // CHECK25: cond.false: 16544 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16545 // CHECK25-NEXT: br label [[COND_END]] 16546 // CHECK25: cond.end: 16547 // CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 16548 // CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 16549 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 16550 // CHECK25-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 16551 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 16552 // CHECK25: omp.inner.for.cond: 16553 // CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16554 // CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16555 // CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 16556 // CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 16557 // CHECK25: omp.inner.for.body: 16558 // CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16559 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 16560 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 16561 // CHECK25-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 16562 // CHECK25-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 16563 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 16564 // CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 16565 // CHECK25-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 16566 // CHECK25-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 16567 // CHECK25-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 16568 // CHECK25-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 16569 // CHECK25-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 16570 // CHECK25-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 16571 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 16572 // CHECK25: omp.body.continue: 16573 // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 16574 // CHECK25: omp.inner.for.inc: 16575 // CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16576 // CHECK25-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 16577 // CHECK25-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 16578 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] 16579 // CHECK25: omp.inner.for.end: 16580 // CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 16581 // CHECK25: omp.loop.exit: 16582 // CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 16583 // CHECK25-NEXT: ret void 16584 // 16585 // 16586 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 16587 // CHECK25-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 16588 // CHECK25-NEXT: entry: 16589 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16590 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 16591 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 16592 // CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 16593 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 16594 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 16595 // CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 16596 // CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 16597 // CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 16598 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 16599 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 16600 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 16601 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16602 // CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 16603 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 16604 // CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 16605 // CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 16606 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 16607 // CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 16608 // CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 16609 // CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 16610 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 16611 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16612 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 16613 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 16614 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 16615 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 16616 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 16617 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 16618 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 16619 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 16620 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 16621 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 16622 // CHECK25-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 16623 // CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 16624 // CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 16625 // CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 16626 // CHECK25-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 16627 // CHECK25-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 16628 // CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 16629 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 16630 // CHECK25-NEXT: ret void 16631 // 16632 // 16633 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 16634 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 16635 // CHECK25-NEXT: entry: 16636 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16637 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16638 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16639 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 16640 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 16641 // CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 16642 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 16643 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 16644 // CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 16645 // CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 16646 // CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 16647 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 16648 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 16649 // CHECK25-NEXT: [[TMP:%.*]] = alloca i8, align 1 16650 // CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 16651 // CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 16652 // CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 16653 // CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 16654 // CHECK25-NEXT: [[IT:%.*]] = alloca i8, align 1 16655 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16656 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16657 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16658 // CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 16659 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 16660 // CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 16661 // CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 16662 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 16663 // CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 16664 // CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 16665 // CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 16666 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 16667 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16668 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 16669 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 16670 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 16671 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 16672 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 16673 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 16674 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 16675 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 16676 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 16677 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 16678 // CHECK25-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 16679 // CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 16680 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 16681 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 16682 // CHECK25-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 16683 // CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 16684 // CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 16685 // CHECK25-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 16686 // CHECK25: omp.dispatch.cond: 16687 // CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16688 // CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 16689 // CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 16690 // CHECK25: cond.true: 16691 // CHECK25-NEXT: br label [[COND_END:%.*]] 16692 // CHECK25: cond.false: 16693 // CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16694 // CHECK25-NEXT: br label [[COND_END]] 16695 // CHECK25: cond.end: 16696 // CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 16697 // CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 16698 // CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 16699 // CHECK25-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 16700 // CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16701 // CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16702 // CHECK25-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 16703 // CHECK25-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 16704 // CHECK25: omp.dispatch.body: 16705 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 16706 // CHECK25: omp.inner.for.cond: 16707 // CHECK25-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16708 // CHECK25-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16709 // CHECK25-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 16710 // CHECK25-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 16711 // CHECK25: omp.inner.for.body: 16712 // CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16713 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 16714 // CHECK25-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 16715 // CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 16716 // CHECK25-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 16717 // CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 16718 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 16719 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 16720 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 16721 // CHECK25-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 16722 // CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 16723 // CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 16724 // CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 16725 // CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 16726 // CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 16727 // CHECK25-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 16728 // CHECK25-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 16729 // CHECK25-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 16730 // CHECK25-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 16731 // CHECK25-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 16732 // CHECK25-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 16733 // CHECK25-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 16734 // CHECK25-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 16735 // CHECK25-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 16736 // CHECK25-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 16737 // CHECK25-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 16738 // CHECK25-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 16739 // CHECK25-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 16740 // CHECK25-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 16741 // CHECK25-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 16742 // CHECK25-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 16743 // CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 16744 // CHECK25-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 16745 // CHECK25-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 16746 // CHECK25-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 16747 // CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 16748 // CHECK25-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 16749 // CHECK25-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 16750 // CHECK25-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 16751 // CHECK25-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 16752 // CHECK25-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 16753 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 16754 // CHECK25: omp.body.continue: 16755 // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 16756 // CHECK25: omp.inner.for.inc: 16757 // CHECK25-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16758 // CHECK25-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 16759 // CHECK25-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 16760 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] 16761 // CHECK25: omp.inner.for.end: 16762 // CHECK25-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 16763 // CHECK25: omp.dispatch.inc: 16764 // CHECK25-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 16765 // CHECK25-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 16766 // CHECK25-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 16767 // CHECK25-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 16768 // CHECK25-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16769 // CHECK25-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 16770 // CHECK25-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 16771 // CHECK25-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 16772 // CHECK25-NEXT: br label [[OMP_DISPATCH_COND]] 16773 // CHECK25: omp.dispatch.end: 16774 // CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 16775 // CHECK25-NEXT: ret void 16776 // 16777 // 16778 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 16779 // CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 16780 // CHECK25-NEXT: entry: 16781 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16782 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16783 // CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 16784 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 16785 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 16786 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 16787 // CHECK25-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 16788 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16789 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16790 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 16791 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 16792 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16793 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16794 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 16795 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 16796 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 16797 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 16798 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 16799 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 16800 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 16801 // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 16802 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 16803 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 16804 // CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 16805 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 16806 // CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 16807 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 16808 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 16809 // CHECK25-NEXT: ret void 16810 // 16811 // 16812 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 16813 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 16814 // CHECK25-NEXT: entry: 16815 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16816 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16817 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16818 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16819 // CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 16820 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 16821 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 16822 // CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 16823 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16824 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16825 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16826 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16827 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 16828 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 16829 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16830 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16831 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 16832 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 16833 // CHECK25-NEXT: ret void 16834 // 16835 // 16836 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 16837 // CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 16838 // CHECK25-NEXT: entry: 16839 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 16840 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 16841 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 16842 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 16843 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 16844 // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 16845 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 16846 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 16847 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 16848 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 16849 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 16850 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 16851 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 16852 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 16853 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 16854 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 16855 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 16856 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 16857 // CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 16858 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 16859 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 16860 // CHECK25-NEXT: ret void 16861 // 16862 // 16863 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 16864 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 16865 // CHECK25-NEXT: entry: 16866 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16867 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16868 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 16869 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 16870 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 16871 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 16872 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 16873 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 16874 // CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8 16875 // CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 16876 // CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 16877 // CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 16878 // CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 16879 // CHECK25-NEXT: [[IT:%.*]] = alloca i64, align 8 16880 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16881 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16882 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 16883 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 16884 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 16885 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 16886 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 16887 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 16888 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 16889 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 16890 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 16891 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 16892 // CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 16893 // CHECK25-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 16894 // CHECK25-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 16895 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 16896 // CHECK25-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 16897 // CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 16898 // CHECK25-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 16899 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16900 // CHECK25-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 16901 // CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 16902 // CHECK25: cond.true: 16903 // CHECK25-NEXT: br label [[COND_END:%.*]] 16904 // CHECK25: cond.false: 16905 // CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16906 // CHECK25-NEXT: br label [[COND_END]] 16907 // CHECK25: cond.end: 16908 // CHECK25-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 16909 // CHECK25-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 16910 // CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 16911 // CHECK25-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 16912 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 16913 // CHECK25: omp.inner.for.cond: 16914 // CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16915 // CHECK25-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16916 // CHECK25-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 16917 // CHECK25-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 16918 // CHECK25: omp.inner.for.body: 16919 // CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16920 // CHECK25-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 16921 // CHECK25-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 16922 // CHECK25-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 16923 // CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 16924 // CHECK25-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 16925 // CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 16926 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 16927 // CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 16928 // CHECK25-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 16929 // CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 16930 // CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 16931 // CHECK25-NEXT: store double [[INC]], double* [[A5]], align 8 16932 // CHECK25-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 16933 // CHECK25-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 16934 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 16935 // CHECK25-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 16936 // CHECK25-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 16937 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 16938 // CHECK25: omp.body.continue: 16939 // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 16940 // CHECK25: omp.inner.for.inc: 16941 // CHECK25-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16942 // CHECK25-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 16943 // CHECK25-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 16944 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] 16945 // CHECK25: omp.inner.for.end: 16946 // CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 16947 // CHECK25: omp.loop.exit: 16948 // CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 16949 // CHECK25-NEXT: ret void 16950 // 16951 // 16952 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 16953 // CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 16954 // CHECK25-NEXT: entry: 16955 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16956 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16957 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 16958 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 16959 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 16960 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16961 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16962 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 16963 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16964 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16965 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 16966 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 16967 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 16968 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 16969 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 16970 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 16971 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 16972 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 16973 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 16974 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 16975 // CHECK25-NEXT: ret void 16976 // 16977 // 16978 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 16979 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 16980 // CHECK25-NEXT: entry: 16981 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16982 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16983 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16984 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16985 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 16986 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 16987 // CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8 16988 // CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 16989 // CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 16990 // CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 16991 // CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 16992 // CHECK25-NEXT: [[I:%.*]] = alloca i64, align 8 16993 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16994 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16995 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16996 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16997 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 16998 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16999 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17000 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 17001 // CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 17002 // CHECK25-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 17003 // CHECK25-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 17004 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 17005 // CHECK25-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 17006 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 17007 // CHECK25-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 17008 // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17009 // CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 17010 // CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 17011 // CHECK25: cond.true: 17012 // CHECK25-NEXT: br label [[COND_END:%.*]] 17013 // CHECK25: cond.false: 17014 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17015 // CHECK25-NEXT: br label [[COND_END]] 17016 // CHECK25: cond.end: 17017 // CHECK25-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 17018 // CHECK25-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 17019 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 17020 // CHECK25-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 17021 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 17022 // CHECK25: omp.inner.for.cond: 17023 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17024 // CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17025 // CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 17026 // CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 17027 // CHECK25: omp.inner.for.body: 17028 // CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17029 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 17030 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 17031 // CHECK25-NEXT: store i64 [[ADD]], i64* [[I]], align 8 17032 // CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 17033 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 17034 // CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 17035 // CHECK25-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 17036 // CHECK25-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 17037 // CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 17038 // CHECK25-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 17039 // CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 17040 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 17041 // CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 17042 // CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 17043 // CHECK25-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 17044 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 17045 // CHECK25: omp.body.continue: 17046 // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 17047 // CHECK25: omp.inner.for.inc: 17048 // CHECK25-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17049 // CHECK25-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 17050 // CHECK25-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 17051 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] 17052 // CHECK25: omp.inner.for.end: 17053 // CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 17054 // CHECK25: omp.loop.exit: 17055 // CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 17056 // CHECK25-NEXT: ret void 17057 // 17058 // 17059 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 17060 // CHECK26-SAME: () #[[ATTR0:[0-9]+]] { 17061 // CHECK26-NEXT: entry: 17062 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 17063 // CHECK26-NEXT: ret void 17064 // 17065 // 17066 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. 17067 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 17068 // CHECK26-NEXT: entry: 17069 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17070 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17071 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 17072 // CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 17073 // CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 17074 // CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 17075 // CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 17076 // CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 17077 // CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 17078 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17079 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17080 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 17081 // CHECK26-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 17082 // CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 17083 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 17084 // CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 17085 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 17086 // CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 17087 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17088 // CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 17089 // CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 17090 // CHECK26: cond.true: 17091 // CHECK26-NEXT: br label [[COND_END:%.*]] 17092 // CHECK26: cond.false: 17093 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17094 // CHECK26-NEXT: br label [[COND_END]] 17095 // CHECK26: cond.end: 17096 // CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 17097 // CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 17098 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 17099 // CHECK26-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 17100 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 17101 // CHECK26: omp.inner.for.cond: 17102 // CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17103 // CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17104 // CHECK26-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 17105 // CHECK26-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 17106 // CHECK26: omp.inner.for.body: 17107 // CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17108 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 17109 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 17110 // CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 17111 // CHECK26-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 17112 // CHECK26-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 17113 // CHECK26-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 17114 // CHECK26: .cancel.exit: 17115 // CHECK26-NEXT: br label [[CANCEL_EXIT:%.*]] 17116 // CHECK26: .cancel.continue: 17117 // CHECK26-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 17118 // CHECK26-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 17119 // CHECK26-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 17120 // CHECK26: .cancel.exit2: 17121 // CHECK26-NEXT: br label [[CANCEL_EXIT]] 17122 // CHECK26: .cancel.continue3: 17123 // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 17124 // CHECK26: omp.body.continue: 17125 // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 17126 // CHECK26: omp.inner.for.inc: 17127 // CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17128 // CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 17129 // CHECK26-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 17130 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] 17131 // CHECK26: omp.inner.for.end: 17132 // CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 17133 // CHECK26: omp.loop.exit: 17134 // CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 17135 // CHECK26-NEXT: br label [[CANCEL_CONT:%.*]] 17136 // CHECK26: cancel.cont: 17137 // CHECK26-NEXT: ret void 17138 // CHECK26: cancel.exit: 17139 // CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 17140 // CHECK26-NEXT: br label [[CANCEL_CONT]] 17141 // 17142 // 17143 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 17144 // CHECK26-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 17145 // CHECK26-NEXT: entry: 17146 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17147 // CHECK26-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 17148 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17149 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 17150 // CHECK26-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 17151 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 17152 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17153 // CHECK26-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 17154 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17155 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17156 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 17157 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17158 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 17159 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 17160 // CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 17161 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 17162 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 17163 // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 17164 // CHECK26-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 17165 // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 17166 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 17167 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 17168 // CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 17169 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 17170 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 17171 // CHECK26-NEXT: ret void 17172 // 17173 // 17174 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 17175 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 17176 // CHECK26-NEXT: entry: 17177 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17178 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17179 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17180 // CHECK26-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 17181 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17182 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 17183 // CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8 17184 // CHECK26-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 17185 // CHECK26-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 17186 // CHECK26-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 17187 // CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 17188 // CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 17189 // CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 17190 // CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 17191 // CHECK26-NEXT: [[IT:%.*]] = alloca i64, align 8 17192 // CHECK26-NEXT: [[LIN4:%.*]] = alloca i32, align 4 17193 // CHECK26-NEXT: [[A5:%.*]] = alloca i32, align 4 17194 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17195 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17196 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17197 // CHECK26-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 17198 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17199 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17200 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 17201 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17202 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 17203 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 17204 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 17205 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 17206 // CHECK26-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 17207 // CHECK26-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 17208 // CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 17209 // CHECK26-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 17210 // CHECK26-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 17211 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 17212 // CHECK26-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 17213 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 17214 // CHECK26-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 17215 // CHECK26-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 17216 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17217 // CHECK26-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 17218 // CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 17219 // CHECK26: cond.true: 17220 // CHECK26-NEXT: br label [[COND_END:%.*]] 17221 // CHECK26: cond.false: 17222 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17223 // CHECK26-NEXT: br label [[COND_END]] 17224 // CHECK26: cond.end: 17225 // CHECK26-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 17226 // CHECK26-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 17227 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 17228 // CHECK26-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 17229 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 17230 // CHECK26: omp.inner.for.cond: 17231 // CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17232 // CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17233 // CHECK26-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 17234 // CHECK26-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 17235 // CHECK26: omp.inner.for.body: 17236 // CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17237 // CHECK26-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 17238 // CHECK26-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 17239 // CHECK26-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 17240 // CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 17241 // CHECK26-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 17242 // CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17243 // CHECK26-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 17244 // CHECK26-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 17245 // CHECK26-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 17246 // CHECK26-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 17247 // CHECK26-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 17248 // CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 17249 // CHECK26-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 17250 // CHECK26-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17251 // CHECK26-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 17252 // CHECK26-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 17253 // CHECK26-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 17254 // CHECK26-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 17255 // CHECK26-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 17256 // CHECK26-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 17257 // CHECK26-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 17258 // CHECK26-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 17259 // CHECK26-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 17260 // CHECK26-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 17261 // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 17262 // CHECK26: omp.body.continue: 17263 // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 17264 // CHECK26: omp.inner.for.inc: 17265 // CHECK26-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17266 // CHECK26-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 17267 // CHECK26-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 17268 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] 17269 // CHECK26: omp.inner.for.end: 17270 // CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 17271 // CHECK26: omp.loop.exit: 17272 // CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 17273 // CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 17274 // CHECK26-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 17275 // CHECK26-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 17276 // CHECK26: .omp.linear.pu: 17277 // CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 17278 // CHECK26-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 17279 // CHECK26-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 17280 // CHECK26-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 17281 // CHECK26-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 17282 // CHECK26: .omp.linear.pu.done: 17283 // CHECK26-NEXT: ret void 17284 // 17285 // 17286 // CHECK26-LABEL: define {{[^@]+}}@_Z7get_valv 17287 // CHECK26-SAME: () #[[ATTR3:[0-9]+]] { 17288 // CHECK26-NEXT: entry: 17289 // CHECK26-NEXT: ret i64 0 17290 // 17291 // 17292 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 17293 // CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 17294 // CHECK26-NEXT: entry: 17295 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17296 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17297 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 17298 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 17299 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17300 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17301 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17302 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17303 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 17304 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 17305 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 17306 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 17307 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 17308 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 17309 // CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 17310 // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 17311 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 17312 // CHECK26-NEXT: ret void 17313 // 17314 // 17315 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 17316 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 17317 // CHECK26-NEXT: entry: 17318 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17319 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17320 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17321 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17322 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 17323 // CHECK26-NEXT: [[TMP:%.*]] = alloca i16, align 2 17324 // CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 17325 // CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 17326 // CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 17327 // CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 17328 // CHECK26-NEXT: [[IT:%.*]] = alloca i16, align 2 17329 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17330 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17331 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17332 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17333 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17334 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17335 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 17336 // CHECK26-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 17337 // CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 17338 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 17339 // CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 17340 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 17341 // CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 17342 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17343 // CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 17344 // CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 17345 // CHECK26: cond.true: 17346 // CHECK26-NEXT: br label [[COND_END:%.*]] 17347 // CHECK26: cond.false: 17348 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17349 // CHECK26-NEXT: br label [[COND_END]] 17350 // CHECK26: cond.end: 17351 // CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 17352 // CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 17353 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 17354 // CHECK26-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 17355 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 17356 // CHECK26: omp.inner.for.cond: 17357 // CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17358 // CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17359 // CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 17360 // CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 17361 // CHECK26: omp.inner.for.body: 17362 // CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17363 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 17364 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 17365 // CHECK26-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 17366 // CHECK26-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 17367 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 17368 // CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 17369 // CHECK26-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 17370 // CHECK26-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 17371 // CHECK26-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 17372 // CHECK26-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 17373 // CHECK26-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 17374 // CHECK26-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 17375 // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 17376 // CHECK26: omp.body.continue: 17377 // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 17378 // CHECK26: omp.inner.for.inc: 17379 // CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17380 // CHECK26-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 17381 // CHECK26-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 17382 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] 17383 // CHECK26: omp.inner.for.end: 17384 // CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 17385 // CHECK26: omp.loop.exit: 17386 // CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 17387 // CHECK26-NEXT: ret void 17388 // 17389 // 17390 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 17391 // CHECK26-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 17392 // CHECK26-NEXT: entry: 17393 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17394 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 17395 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 17396 // CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 17397 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 17398 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 17399 // CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 17400 // CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 17401 // CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 17402 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 17403 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 17404 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 17405 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17406 // CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 17407 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 17408 // CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 17409 // CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 17410 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 17411 // CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 17412 // CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 17413 // CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 17414 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 17415 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17416 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 17417 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 17418 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 17419 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 17420 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 17421 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 17422 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 17423 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 17424 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 17425 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 17426 // CHECK26-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 17427 // CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 17428 // CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 17429 // CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 17430 // CHECK26-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 17431 // CHECK26-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 17432 // CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 17433 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 17434 // CHECK26-NEXT: ret void 17435 // 17436 // 17437 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 17438 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 17439 // CHECK26-NEXT: entry: 17440 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17441 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17442 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17443 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 17444 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 17445 // CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 17446 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 17447 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 17448 // CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 17449 // CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 17450 // CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 17451 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 17452 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 17453 // CHECK26-NEXT: [[TMP:%.*]] = alloca i8, align 1 17454 // CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 17455 // CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 17456 // CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 17457 // CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 17458 // CHECK26-NEXT: [[IT:%.*]] = alloca i8, align 1 17459 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17460 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17461 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17462 // CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 17463 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 17464 // CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 17465 // CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 17466 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 17467 // CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 17468 // CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 17469 // CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 17470 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 17471 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17472 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 17473 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 17474 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 17475 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 17476 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 17477 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 17478 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 17479 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 17480 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 17481 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 17482 // CHECK26-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 17483 // CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 17484 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 17485 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 17486 // CHECK26-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 17487 // CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 17488 // CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 17489 // CHECK26-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 17490 // CHECK26: omp.dispatch.cond: 17491 // CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17492 // CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 17493 // CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 17494 // CHECK26: cond.true: 17495 // CHECK26-NEXT: br label [[COND_END:%.*]] 17496 // CHECK26: cond.false: 17497 // CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17498 // CHECK26-NEXT: br label [[COND_END]] 17499 // CHECK26: cond.end: 17500 // CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 17501 // CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 17502 // CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 17503 // CHECK26-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 17504 // CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17505 // CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17506 // CHECK26-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 17507 // CHECK26-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 17508 // CHECK26: omp.dispatch.body: 17509 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 17510 // CHECK26: omp.inner.for.cond: 17511 // CHECK26-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17512 // CHECK26-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17513 // CHECK26-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 17514 // CHECK26-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 17515 // CHECK26: omp.inner.for.body: 17516 // CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17517 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 17518 // CHECK26-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 17519 // CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 17520 // CHECK26-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 17521 // CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 17522 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 17523 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 17524 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 17525 // CHECK26-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 17526 // CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 17527 // CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 17528 // CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 17529 // CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 17530 // CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 17531 // CHECK26-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 17532 // CHECK26-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 17533 // CHECK26-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 17534 // CHECK26-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 17535 // CHECK26-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 17536 // CHECK26-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 17537 // CHECK26-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 17538 // CHECK26-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 17539 // CHECK26-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 17540 // CHECK26-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 17541 // CHECK26-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 17542 // CHECK26-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 17543 // CHECK26-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 17544 // CHECK26-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 17545 // CHECK26-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 17546 // CHECK26-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 17547 // CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 17548 // CHECK26-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 17549 // CHECK26-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 17550 // CHECK26-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 17551 // CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 17552 // CHECK26-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 17553 // CHECK26-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 17554 // CHECK26-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 17555 // CHECK26-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 17556 // CHECK26-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 17557 // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 17558 // CHECK26: omp.body.continue: 17559 // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 17560 // CHECK26: omp.inner.for.inc: 17561 // CHECK26-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17562 // CHECK26-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 17563 // CHECK26-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 17564 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] 17565 // CHECK26: omp.inner.for.end: 17566 // CHECK26-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 17567 // CHECK26: omp.dispatch.inc: 17568 // CHECK26-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 17569 // CHECK26-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 17570 // CHECK26-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 17571 // CHECK26-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 17572 // CHECK26-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17573 // CHECK26-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 17574 // CHECK26-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 17575 // CHECK26-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 17576 // CHECK26-NEXT: br label [[OMP_DISPATCH_COND]] 17577 // CHECK26: omp.dispatch.end: 17578 // CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 17579 // CHECK26-NEXT: ret void 17580 // 17581 // 17582 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 17583 // CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 17584 // CHECK26-NEXT: entry: 17585 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17586 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17587 // CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 17588 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 17589 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 17590 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 17591 // CHECK26-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 17592 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17593 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17594 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 17595 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 17596 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17597 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17598 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 17599 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 17600 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 17601 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 17602 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 17603 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 17604 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 17605 // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 17606 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 17607 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 17608 // CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 17609 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 17610 // CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 17611 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 17612 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 17613 // CHECK26-NEXT: ret void 17614 // 17615 // 17616 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 17617 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 17618 // CHECK26-NEXT: entry: 17619 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17620 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17621 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17622 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17623 // CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 17624 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 17625 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 17626 // CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 17627 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17628 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17629 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17630 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17631 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 17632 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 17633 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17634 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17635 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 17636 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 17637 // CHECK26-NEXT: ret void 17638 // 17639 // 17640 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 17641 // CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 17642 // CHECK26-NEXT: entry: 17643 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 17644 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 17645 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 17646 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 17647 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 17648 // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 17649 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 17650 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 17651 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 17652 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 17653 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 17654 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 17655 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 17656 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 17657 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 17658 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 17659 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 17660 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 17661 // CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 17662 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 17663 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 17664 // CHECK26-NEXT: ret void 17665 // 17666 // 17667 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 17668 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 17669 // CHECK26-NEXT: entry: 17670 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17671 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17672 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 17673 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 17674 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 17675 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 17676 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 17677 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 17678 // CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8 17679 // CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 17680 // CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 17681 // CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 17682 // CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 17683 // CHECK26-NEXT: [[IT:%.*]] = alloca i64, align 8 17684 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17685 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17686 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 17687 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 17688 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 17689 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 17690 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 17691 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 17692 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 17693 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 17694 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 17695 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 17696 // CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 17697 // CHECK26-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 17698 // CHECK26-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 17699 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 17700 // CHECK26-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 17701 // CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 17702 // CHECK26-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 17703 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17704 // CHECK26-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 17705 // CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 17706 // CHECK26: cond.true: 17707 // CHECK26-NEXT: br label [[COND_END:%.*]] 17708 // CHECK26: cond.false: 17709 // CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17710 // CHECK26-NEXT: br label [[COND_END]] 17711 // CHECK26: cond.end: 17712 // CHECK26-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 17713 // CHECK26-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 17714 // CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 17715 // CHECK26-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 17716 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 17717 // CHECK26: omp.inner.for.cond: 17718 // CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17719 // CHECK26-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17720 // CHECK26-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 17721 // CHECK26-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 17722 // CHECK26: omp.inner.for.body: 17723 // CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17724 // CHECK26-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 17725 // CHECK26-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 17726 // CHECK26-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 17727 // CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 17728 // CHECK26-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 17729 // CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 17730 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 17731 // CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 17732 // CHECK26-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 17733 // CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 17734 // CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 17735 // CHECK26-NEXT: store double [[INC]], double* [[A5]], align 8 17736 // CHECK26-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 17737 // CHECK26-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 17738 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 17739 // CHECK26-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 17740 // CHECK26-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 17741 // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 17742 // CHECK26: omp.body.continue: 17743 // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 17744 // CHECK26: omp.inner.for.inc: 17745 // CHECK26-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17746 // CHECK26-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 17747 // CHECK26-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 17748 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] 17749 // CHECK26: omp.inner.for.end: 17750 // CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 17751 // CHECK26: omp.loop.exit: 17752 // CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 17753 // CHECK26-NEXT: ret void 17754 // 17755 // 17756 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 17757 // CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 17758 // CHECK26-NEXT: entry: 17759 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17760 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17761 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 17762 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 17763 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 17764 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17765 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17766 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 17767 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17768 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17769 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 17770 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 17771 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 17772 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 17773 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 17774 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 17775 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 17776 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 17777 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 17778 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 17779 // CHECK26-NEXT: ret void 17780 // 17781 // 17782 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 17783 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 17784 // CHECK26-NEXT: entry: 17785 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17786 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17787 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17788 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17789 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 17790 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 17791 // CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8 17792 // CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 17793 // CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 17794 // CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 17795 // CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 17796 // CHECK26-NEXT: [[I:%.*]] = alloca i64, align 8 17797 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17798 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17799 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17800 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17801 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 17802 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17803 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17804 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 17805 // CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 17806 // CHECK26-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 17807 // CHECK26-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 17808 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 17809 // CHECK26-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 17810 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 17811 // CHECK26-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 17812 // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17813 // CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 17814 // CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 17815 // CHECK26: cond.true: 17816 // CHECK26-NEXT: br label [[COND_END:%.*]] 17817 // CHECK26: cond.false: 17818 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17819 // CHECK26-NEXT: br label [[COND_END]] 17820 // CHECK26: cond.end: 17821 // CHECK26-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 17822 // CHECK26-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 17823 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 17824 // CHECK26-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 17825 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 17826 // CHECK26: omp.inner.for.cond: 17827 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17828 // CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17829 // CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 17830 // CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 17831 // CHECK26: omp.inner.for.body: 17832 // CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17833 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 17834 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 17835 // CHECK26-NEXT: store i64 [[ADD]], i64* [[I]], align 8 17836 // CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 17837 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 17838 // CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 17839 // CHECK26-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 17840 // CHECK26-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 17841 // CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 17842 // CHECK26-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 17843 // CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 17844 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 17845 // CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 17846 // CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 17847 // CHECK26-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 17848 // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 17849 // CHECK26: omp.body.continue: 17850 // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 17851 // CHECK26: omp.inner.for.inc: 17852 // CHECK26-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17853 // CHECK26-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 17854 // CHECK26-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 17855 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] 17856 // CHECK26: omp.inner.for.end: 17857 // CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 17858 // CHECK26: omp.loop.exit: 17859 // CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 17860 // CHECK26-NEXT: ret void 17861 // 17862 // 17863 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 17864 // CHECK27-SAME: () #[[ATTR0:[0-9]+]] { 17865 // CHECK27-NEXT: entry: 17866 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 17867 // CHECK27-NEXT: ret void 17868 // 17869 // 17870 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. 17871 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 17872 // CHECK27-NEXT: entry: 17873 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 17874 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 17875 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 17876 // CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 17877 // CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 17878 // CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 17879 // CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 17880 // CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 17881 // CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 17882 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 17883 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 17884 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 17885 // CHECK27-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 17886 // CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 17887 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 17888 // CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 17889 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 17890 // CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 17891 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17892 // CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 17893 // CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 17894 // CHECK27: cond.true: 17895 // CHECK27-NEXT: br label [[COND_END:%.*]] 17896 // CHECK27: cond.false: 17897 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17898 // CHECK27-NEXT: br label [[COND_END]] 17899 // CHECK27: cond.end: 17900 // CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 17901 // CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 17902 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 17903 // CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 17904 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 17905 // CHECK27: omp.inner.for.cond: 17906 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17907 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17908 // CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 17909 // CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 17910 // CHECK27: omp.inner.for.body: 17911 // CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17912 // CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 17913 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 17914 // CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 17915 // CHECK27-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 17916 // CHECK27-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 17917 // CHECK27-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 17918 // CHECK27: .cancel.exit: 17919 // CHECK27-NEXT: br label [[CANCEL_EXIT:%.*]] 17920 // CHECK27: .cancel.continue: 17921 // CHECK27-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 17922 // CHECK27-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 17923 // CHECK27-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 17924 // CHECK27: .cancel.exit2: 17925 // CHECK27-NEXT: br label [[CANCEL_EXIT]] 17926 // CHECK27: .cancel.continue3: 17927 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 17928 // CHECK27: omp.body.continue: 17929 // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 17930 // CHECK27: omp.inner.for.inc: 17931 // CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17932 // CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 17933 // CHECK27-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 17934 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] 17935 // CHECK27: omp.inner.for.end: 17936 // CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 17937 // CHECK27: omp.loop.exit: 17938 // CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 17939 // CHECK27-NEXT: br label [[CANCEL_CONT:%.*]] 17940 // CHECK27: cancel.cont: 17941 // CHECK27-NEXT: ret void 17942 // CHECK27: cancel.exit: 17943 // CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 17944 // CHECK27-NEXT: br label [[CANCEL_CONT]] 17945 // 17946 // 17947 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 17948 // CHECK27-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 17949 // CHECK27-NEXT: entry: 17950 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 17951 // CHECK27-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 17952 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 17953 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 17954 // CHECK27-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 17955 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 17956 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 17957 // CHECK27-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 17958 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 17959 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 17960 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 17961 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 17962 // CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 17963 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 17964 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 17965 // CHECK27-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 17966 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 17967 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 17968 // CHECK27-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 17969 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 17970 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 17971 // CHECK27-NEXT: ret void 17972 // 17973 // 17974 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 17975 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 17976 // CHECK27-NEXT: entry: 17977 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 17978 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 17979 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 17980 // CHECK27-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 17981 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 17982 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 17983 // CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4 17984 // CHECK27-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 17985 // CHECK27-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 17986 // CHECK27-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 17987 // CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 17988 // CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 17989 // CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 17990 // CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 17991 // CHECK27-NEXT: [[IT:%.*]] = alloca i64, align 8 17992 // CHECK27-NEXT: [[LIN2:%.*]] = alloca i32, align 4 17993 // CHECK27-NEXT: [[A3:%.*]] = alloca i32, align 4 17994 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 17995 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 17996 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 17997 // CHECK27-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 17998 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 17999 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18000 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 18001 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 18002 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 18003 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 18004 // CHECK27-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 18005 // CHECK27-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 18006 // CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 18007 // CHECK27-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 18008 // CHECK27-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 18009 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 18010 // CHECK27-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 18011 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 18012 // CHECK27-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 18013 // CHECK27-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 18014 // CHECK27-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18015 // CHECK27-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 18016 // CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 18017 // CHECK27: cond.true: 18018 // CHECK27-NEXT: br label [[COND_END:%.*]] 18019 // CHECK27: cond.false: 18020 // CHECK27-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18021 // CHECK27-NEXT: br label [[COND_END]] 18022 // CHECK27: cond.end: 18023 // CHECK27-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 18024 // CHECK27-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 18025 // CHECK27-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 18026 // CHECK27-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 18027 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 18028 // CHECK27: omp.inner.for.cond: 18029 // CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18030 // CHECK27-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18031 // CHECK27-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 18032 // CHECK27-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 18033 // CHECK27: omp.inner.for.body: 18034 // CHECK27-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18035 // CHECK27-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 18036 // CHECK27-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 18037 // CHECK27-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 18038 // CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 18039 // CHECK27-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 18040 // CHECK27-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18041 // CHECK27-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 18042 // CHECK27-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 18043 // CHECK27-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 18044 // CHECK27-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 18045 // CHECK27-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 18046 // CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 18047 // CHECK27-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 18048 // CHECK27-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18049 // CHECK27-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 18050 // CHECK27-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 18051 // CHECK27-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 18052 // CHECK27-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 18053 // CHECK27-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 18054 // CHECK27-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 18055 // CHECK27-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 18056 // CHECK27-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 18057 // CHECK27-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 18058 // CHECK27-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 18059 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 18060 // CHECK27: omp.body.continue: 18061 // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 18062 // CHECK27: omp.inner.for.inc: 18063 // CHECK27-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18064 // CHECK27-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 18065 // CHECK27-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 18066 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] 18067 // CHECK27: omp.inner.for.end: 18068 // CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 18069 // CHECK27: omp.loop.exit: 18070 // CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 18071 // CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 18072 // CHECK27-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 18073 // CHECK27-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 18074 // CHECK27: .omp.linear.pu: 18075 // CHECK27-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 18076 // CHECK27-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 18077 // CHECK27-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 18078 // CHECK27-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 18079 // CHECK27-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 18080 // CHECK27: .omp.linear.pu.done: 18081 // CHECK27-NEXT: ret void 18082 // 18083 // 18084 // CHECK27-LABEL: define {{[^@]+}}@_Z7get_valv 18085 // CHECK27-SAME: () #[[ATTR3:[0-9]+]] { 18086 // CHECK27-NEXT: entry: 18087 // CHECK27-NEXT: ret i64 0 18088 // 18089 // 18090 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 18091 // CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 18092 // CHECK27-NEXT: entry: 18093 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18094 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18095 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 18096 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 18097 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18098 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18099 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18100 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 18101 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 18102 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 18103 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 18104 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 18105 // CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 18106 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 18107 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 18108 // CHECK27-NEXT: ret void 18109 // 18110 // 18111 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 18112 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 18113 // CHECK27-NEXT: entry: 18114 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18115 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18116 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18117 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18118 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 18119 // CHECK27-NEXT: [[TMP:%.*]] = alloca i16, align 2 18120 // CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 18121 // CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 18122 // CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 18123 // CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 18124 // CHECK27-NEXT: [[IT:%.*]] = alloca i16, align 2 18125 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18126 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18127 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18128 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18129 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18130 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 18131 // CHECK27-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 18132 // CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 18133 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 18134 // CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 18135 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 18136 // CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 18137 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18138 // CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 18139 // CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 18140 // CHECK27: cond.true: 18141 // CHECK27-NEXT: br label [[COND_END:%.*]] 18142 // CHECK27: cond.false: 18143 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18144 // CHECK27-NEXT: br label [[COND_END]] 18145 // CHECK27: cond.end: 18146 // CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 18147 // CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 18148 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 18149 // CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 18150 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 18151 // CHECK27: omp.inner.for.cond: 18152 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18153 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18154 // CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 18155 // CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 18156 // CHECK27: omp.inner.for.body: 18157 // CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18158 // CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 18159 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 18160 // CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 18161 // CHECK27-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 18162 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 18163 // CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 18164 // CHECK27-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 18165 // CHECK27-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 18166 // CHECK27-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 18167 // CHECK27-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 18168 // CHECK27-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 18169 // CHECK27-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 18170 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 18171 // CHECK27: omp.body.continue: 18172 // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 18173 // CHECK27: omp.inner.for.inc: 18174 // CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18175 // CHECK27-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 18176 // CHECK27-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 18177 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] 18178 // CHECK27: omp.inner.for.end: 18179 // CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 18180 // CHECK27: omp.loop.exit: 18181 // CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 18182 // CHECK27-NEXT: ret void 18183 // 18184 // 18185 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 18186 // CHECK27-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 18187 // CHECK27-NEXT: entry: 18188 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18189 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 18190 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 18191 // CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 18192 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 18193 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 18194 // CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 18195 // CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 18196 // CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 18197 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 18198 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 18199 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 18200 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18201 // CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 18202 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 18203 // CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 18204 // CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 18205 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 18206 // CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 18207 // CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 18208 // CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 18209 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 18210 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 18211 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 18212 // CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 18213 // CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 18214 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 18215 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 18216 // CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 18217 // CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 18218 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 18219 // CHECK27-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 18220 // CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 18221 // CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 18222 // CHECK27-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 18223 // CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 18224 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 18225 // CHECK27-NEXT: ret void 18226 // 18227 // 18228 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 18229 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 18230 // CHECK27-NEXT: entry: 18231 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18232 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18233 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18234 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 18235 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 18236 // CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 18237 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 18238 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 18239 // CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 18240 // CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 18241 // CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 18242 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 18243 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 18244 // CHECK27-NEXT: [[TMP:%.*]] = alloca i8, align 1 18245 // CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 18246 // CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 18247 // CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 18248 // CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 18249 // CHECK27-NEXT: [[IT:%.*]] = alloca i8, align 1 18250 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18251 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18252 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18253 // CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 18254 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 18255 // CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 18256 // CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 18257 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 18258 // CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 18259 // CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 18260 // CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 18261 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 18262 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 18263 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 18264 // CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 18265 // CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 18266 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 18267 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 18268 // CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 18269 // CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 18270 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 18271 // CHECK27-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 18272 // CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 18273 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 18274 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 18275 // CHECK27-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 18276 // CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 18277 // CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 18278 // CHECK27-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 18279 // CHECK27: omp.dispatch.cond: 18280 // CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18281 // CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 18282 // CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 18283 // CHECK27: cond.true: 18284 // CHECK27-NEXT: br label [[COND_END:%.*]] 18285 // CHECK27: cond.false: 18286 // CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18287 // CHECK27-NEXT: br label [[COND_END]] 18288 // CHECK27: cond.end: 18289 // CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 18290 // CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 18291 // CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 18292 // CHECK27-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 18293 // CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18294 // CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18295 // CHECK27-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 18296 // CHECK27-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 18297 // CHECK27: omp.dispatch.body: 18298 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 18299 // CHECK27: omp.inner.for.cond: 18300 // CHECK27-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18301 // CHECK27-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18302 // CHECK27-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 18303 // CHECK27-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 18304 // CHECK27: omp.inner.for.body: 18305 // CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18306 // CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 18307 // CHECK27-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 18308 // CHECK27-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 18309 // CHECK27-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 18310 // CHECK27-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 18311 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 18312 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 18313 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 18314 // CHECK27-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 18315 // CHECK27-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 18316 // CHECK27-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 18317 // CHECK27-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 18318 // CHECK27-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 18319 // CHECK27-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 18320 // CHECK27-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 18321 // CHECK27-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 18322 // CHECK27-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 18323 // CHECK27-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 18324 // CHECK27-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 18325 // CHECK27-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 18326 // CHECK27-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 18327 // CHECK27-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 18328 // CHECK27-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 18329 // CHECK27-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 18330 // CHECK27-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 18331 // CHECK27-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 18332 // CHECK27-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 18333 // CHECK27-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 18334 // CHECK27-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 18335 // CHECK27-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 18336 // CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 18337 // CHECK27-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 18338 // CHECK27-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 18339 // CHECK27-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 18340 // CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 18341 // CHECK27-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 18342 // CHECK27-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 18343 // CHECK27-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 18344 // CHECK27-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 18345 // CHECK27-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 18346 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 18347 // CHECK27: omp.body.continue: 18348 // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 18349 // CHECK27: omp.inner.for.inc: 18350 // CHECK27-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18351 // CHECK27-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 18352 // CHECK27-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 18353 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] 18354 // CHECK27: omp.inner.for.end: 18355 // CHECK27-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 18356 // CHECK27: omp.dispatch.inc: 18357 // CHECK27-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 18358 // CHECK27-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 18359 // CHECK27-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 18360 // CHECK27-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 18361 // CHECK27-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18362 // CHECK27-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 18363 // CHECK27-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 18364 // CHECK27-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 18365 // CHECK27-NEXT: br label [[OMP_DISPATCH_COND]] 18366 // CHECK27: omp.dispatch.end: 18367 // CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 18368 // CHECK27-NEXT: ret void 18369 // 18370 // 18371 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 18372 // CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 18373 // CHECK27-NEXT: entry: 18374 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18375 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18376 // CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 18377 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 18378 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 18379 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 18380 // CHECK27-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 18381 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18382 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18383 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 18384 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 18385 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18386 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 18387 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 18388 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 18389 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 18390 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 18391 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 18392 // CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 18393 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 18394 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 18395 // CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 18396 // CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 18397 // CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 18398 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 18399 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 18400 // CHECK27-NEXT: ret void 18401 // 18402 // 18403 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 18404 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 18405 // CHECK27-NEXT: entry: 18406 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18407 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18408 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18409 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18410 // CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 18411 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 18412 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 18413 // CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 18414 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18415 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18416 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18417 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18418 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 18419 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 18420 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18421 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 18422 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 18423 // CHECK27-NEXT: ret void 18424 // 18425 // 18426 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 18427 // CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 18428 // CHECK27-NEXT: entry: 18429 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 18430 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 18431 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 18432 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 18433 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 18434 // CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 18435 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 18436 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 18437 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 18438 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 18439 // CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 18440 // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 18441 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 18442 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 18443 // CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 18444 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 18445 // CHECK27-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 18446 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 18447 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 18448 // CHECK27-NEXT: ret void 18449 // 18450 // 18451 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 18452 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 18453 // CHECK27-NEXT: entry: 18454 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18455 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18456 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 18457 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 18458 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 18459 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 18460 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 18461 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 18462 // CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4 18463 // CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 18464 // CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 18465 // CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 18466 // CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 18467 // CHECK27-NEXT: [[IT:%.*]] = alloca i64, align 8 18468 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18469 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18470 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 18471 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 18472 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 18473 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 18474 // CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 18475 // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 18476 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 18477 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 18478 // CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 18479 // CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 18480 // CHECK27-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 18481 // CHECK27-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 18482 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 18483 // CHECK27-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 18484 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 18485 // CHECK27-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 18486 // CHECK27-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18487 // CHECK27-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 18488 // CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 18489 // CHECK27: cond.true: 18490 // CHECK27-NEXT: br label [[COND_END:%.*]] 18491 // CHECK27: cond.false: 18492 // CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18493 // CHECK27-NEXT: br label [[COND_END]] 18494 // CHECK27: cond.end: 18495 // CHECK27-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 18496 // CHECK27-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 18497 // CHECK27-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 18498 // CHECK27-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 18499 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 18500 // CHECK27: omp.inner.for.cond: 18501 // CHECK27-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18502 // CHECK27-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18503 // CHECK27-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 18504 // CHECK27-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 18505 // CHECK27: omp.inner.for.body: 18506 // CHECK27-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18507 // CHECK27-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 18508 // CHECK27-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 18509 // CHECK27-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 18510 // CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 18511 // CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 18512 // CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 18513 // CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 18514 // CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 18515 // CHECK27-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 18516 // CHECK27-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 18517 // CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 18518 // CHECK27-NEXT: store double [[INC]], double* [[A4]], align 4 18519 // CHECK27-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 18520 // CHECK27-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 18521 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 18522 // CHECK27-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 18523 // CHECK27-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 18524 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 18525 // CHECK27: omp.body.continue: 18526 // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 18527 // CHECK27: omp.inner.for.inc: 18528 // CHECK27-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18529 // CHECK27-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 18530 // CHECK27-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 18531 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] 18532 // CHECK27: omp.inner.for.end: 18533 // CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 18534 // CHECK27: omp.loop.exit: 18535 // CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 18536 // CHECK27-NEXT: ret void 18537 // 18538 // 18539 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 18540 // CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 18541 // CHECK27-NEXT: entry: 18542 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18543 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18544 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 18545 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 18546 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 18547 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18548 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18549 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 18550 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18551 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 18552 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 18553 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 18554 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 18555 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 18556 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 18557 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 18558 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 18559 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 18560 // CHECK27-NEXT: ret void 18561 // 18562 // 18563 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 18564 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 18565 // CHECK27-NEXT: entry: 18566 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18567 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18568 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18569 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18570 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 18571 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 18572 // CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4 18573 // CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 18574 // CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 18575 // CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 18576 // CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 18577 // CHECK27-NEXT: [[I:%.*]] = alloca i64, align 8 18578 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18579 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18580 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18581 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18582 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 18583 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18584 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 18585 // CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 18586 // CHECK27-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 18587 // CHECK27-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 18588 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 18589 // CHECK27-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 18590 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 18591 // CHECK27-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 18592 // CHECK27-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18593 // CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 18594 // CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 18595 // CHECK27: cond.true: 18596 // CHECK27-NEXT: br label [[COND_END:%.*]] 18597 // CHECK27: cond.false: 18598 // CHECK27-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18599 // CHECK27-NEXT: br label [[COND_END]] 18600 // CHECK27: cond.end: 18601 // CHECK27-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 18602 // CHECK27-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 18603 // CHECK27-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 18604 // CHECK27-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 18605 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 18606 // CHECK27: omp.inner.for.cond: 18607 // CHECK27-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18608 // CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18609 // CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 18610 // CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 18611 // CHECK27: omp.inner.for.body: 18612 // CHECK27-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18613 // CHECK27-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 18614 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 18615 // CHECK27-NEXT: store i64 [[ADD]], i64* [[I]], align 8 18616 // CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 18617 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 18618 // CHECK27-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 18619 // CHECK27-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 18620 // CHECK27-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 18621 // CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 18622 // CHECK27-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 18623 // CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 18624 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 18625 // CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 18626 // CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 18627 // CHECK27-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 18628 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 18629 // CHECK27: omp.body.continue: 18630 // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 18631 // CHECK27: omp.inner.for.inc: 18632 // CHECK27-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18633 // CHECK27-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 18634 // CHECK27-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 18635 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] 18636 // CHECK27: omp.inner.for.end: 18637 // CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 18638 // CHECK27: omp.loop.exit: 18639 // CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 18640 // CHECK27-NEXT: ret void 18641 // 18642 // 18643 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 18644 // CHECK28-SAME: () #[[ATTR0:[0-9]+]] { 18645 // CHECK28-NEXT: entry: 18646 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 18647 // CHECK28-NEXT: ret void 18648 // 18649 // 18650 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. 18651 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 18652 // CHECK28-NEXT: entry: 18653 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18654 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18655 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 18656 // CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 18657 // CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 18658 // CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 18659 // CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 18660 // CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 18661 // CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 18662 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18663 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18664 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 18665 // CHECK28-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 18666 // CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 18667 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 18668 // CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 18669 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 18670 // CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 18671 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18672 // CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 18673 // CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 18674 // CHECK28: cond.true: 18675 // CHECK28-NEXT: br label [[COND_END:%.*]] 18676 // CHECK28: cond.false: 18677 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18678 // CHECK28-NEXT: br label [[COND_END]] 18679 // CHECK28: cond.end: 18680 // CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 18681 // CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 18682 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 18683 // CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 18684 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 18685 // CHECK28: omp.inner.for.cond: 18686 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18687 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18688 // CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 18689 // CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 18690 // CHECK28: omp.inner.for.body: 18691 // CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18692 // CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 18693 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 18694 // CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 18695 // CHECK28-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 18696 // CHECK28-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 18697 // CHECK28-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 18698 // CHECK28: .cancel.exit: 18699 // CHECK28-NEXT: br label [[CANCEL_EXIT:%.*]] 18700 // CHECK28: .cancel.continue: 18701 // CHECK28-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 18702 // CHECK28-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 18703 // CHECK28-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 18704 // CHECK28: .cancel.exit2: 18705 // CHECK28-NEXT: br label [[CANCEL_EXIT]] 18706 // CHECK28: .cancel.continue3: 18707 // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 18708 // CHECK28: omp.body.continue: 18709 // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 18710 // CHECK28: omp.inner.for.inc: 18711 // CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18712 // CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 18713 // CHECK28-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 18714 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] 18715 // CHECK28: omp.inner.for.end: 18716 // CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 18717 // CHECK28: omp.loop.exit: 18718 // CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 18719 // CHECK28-NEXT: br label [[CANCEL_CONT:%.*]] 18720 // CHECK28: cancel.cont: 18721 // CHECK28-NEXT: ret void 18722 // CHECK28: cancel.exit: 18723 // CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 18724 // CHECK28-NEXT: br label [[CANCEL_CONT]] 18725 // 18726 // 18727 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 18728 // CHECK28-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 18729 // CHECK28-NEXT: entry: 18730 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18731 // CHECK28-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 18732 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18733 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 18734 // CHECK28-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 18735 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 18736 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18737 // CHECK28-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 18738 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18739 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18740 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 18741 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 18742 // CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 18743 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 18744 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 18745 // CHECK28-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 18746 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 18747 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 18748 // CHECK28-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 18749 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 18750 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 18751 // CHECK28-NEXT: ret void 18752 // 18753 // 18754 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 18755 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 18756 // CHECK28-NEXT: entry: 18757 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18758 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18759 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18760 // CHECK28-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 18761 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18762 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 18763 // CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4 18764 // CHECK28-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 18765 // CHECK28-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 18766 // CHECK28-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 18767 // CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 18768 // CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 18769 // CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 18770 // CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 18771 // CHECK28-NEXT: [[IT:%.*]] = alloca i64, align 8 18772 // CHECK28-NEXT: [[LIN2:%.*]] = alloca i32, align 4 18773 // CHECK28-NEXT: [[A3:%.*]] = alloca i32, align 4 18774 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18775 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18776 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18777 // CHECK28-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 18778 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18779 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18780 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 18781 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 18782 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 18783 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 18784 // CHECK28-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 18785 // CHECK28-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 18786 // CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 18787 // CHECK28-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 18788 // CHECK28-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 18789 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 18790 // CHECK28-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 18791 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 18792 // CHECK28-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 18793 // CHECK28-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 18794 // CHECK28-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18795 // CHECK28-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 18796 // CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 18797 // CHECK28: cond.true: 18798 // CHECK28-NEXT: br label [[COND_END:%.*]] 18799 // CHECK28: cond.false: 18800 // CHECK28-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18801 // CHECK28-NEXT: br label [[COND_END]] 18802 // CHECK28: cond.end: 18803 // CHECK28-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 18804 // CHECK28-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 18805 // CHECK28-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 18806 // CHECK28-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 18807 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 18808 // CHECK28: omp.inner.for.cond: 18809 // CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18810 // CHECK28-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18811 // CHECK28-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 18812 // CHECK28-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 18813 // CHECK28: omp.inner.for.body: 18814 // CHECK28-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18815 // CHECK28-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 18816 // CHECK28-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 18817 // CHECK28-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 18818 // CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 18819 // CHECK28-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 18820 // CHECK28-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18821 // CHECK28-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 18822 // CHECK28-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 18823 // CHECK28-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 18824 // CHECK28-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 18825 // CHECK28-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 18826 // CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 18827 // CHECK28-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 18828 // CHECK28-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18829 // CHECK28-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 18830 // CHECK28-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 18831 // CHECK28-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 18832 // CHECK28-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 18833 // CHECK28-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 18834 // CHECK28-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 18835 // CHECK28-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 18836 // CHECK28-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 18837 // CHECK28-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 18838 // CHECK28-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 18839 // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 18840 // CHECK28: omp.body.continue: 18841 // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 18842 // CHECK28: omp.inner.for.inc: 18843 // CHECK28-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18844 // CHECK28-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 18845 // CHECK28-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 18846 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] 18847 // CHECK28: omp.inner.for.end: 18848 // CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 18849 // CHECK28: omp.loop.exit: 18850 // CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 18851 // CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 18852 // CHECK28-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 18853 // CHECK28-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 18854 // CHECK28: .omp.linear.pu: 18855 // CHECK28-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 18856 // CHECK28-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 18857 // CHECK28-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 18858 // CHECK28-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 18859 // CHECK28-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 18860 // CHECK28: .omp.linear.pu.done: 18861 // CHECK28-NEXT: ret void 18862 // 18863 // 18864 // CHECK28-LABEL: define {{[^@]+}}@_Z7get_valv 18865 // CHECK28-SAME: () #[[ATTR3:[0-9]+]] { 18866 // CHECK28-NEXT: entry: 18867 // CHECK28-NEXT: ret i64 0 18868 // 18869 // 18870 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 18871 // CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 18872 // CHECK28-NEXT: entry: 18873 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18874 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18875 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 18876 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 18877 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18878 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18879 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18880 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 18881 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 18882 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 18883 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 18884 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 18885 // CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 18886 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 18887 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 18888 // CHECK28-NEXT: ret void 18889 // 18890 // 18891 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 18892 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 18893 // CHECK28-NEXT: entry: 18894 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18895 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18896 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18897 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18898 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 18899 // CHECK28-NEXT: [[TMP:%.*]] = alloca i16, align 2 18900 // CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 18901 // CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 18902 // CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 18903 // CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 18904 // CHECK28-NEXT: [[IT:%.*]] = alloca i16, align 2 18905 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18906 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18907 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18908 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18909 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18910 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 18911 // CHECK28-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 18912 // CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 18913 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 18914 // CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 18915 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 18916 // CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 18917 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18918 // CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 18919 // CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 18920 // CHECK28: cond.true: 18921 // CHECK28-NEXT: br label [[COND_END:%.*]] 18922 // CHECK28: cond.false: 18923 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18924 // CHECK28-NEXT: br label [[COND_END]] 18925 // CHECK28: cond.end: 18926 // CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 18927 // CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 18928 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 18929 // CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 18930 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 18931 // CHECK28: omp.inner.for.cond: 18932 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18933 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18934 // CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 18935 // CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 18936 // CHECK28: omp.inner.for.body: 18937 // CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18938 // CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 18939 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 18940 // CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 18941 // CHECK28-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 18942 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 18943 // CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 18944 // CHECK28-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 18945 // CHECK28-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 18946 // CHECK28-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 18947 // CHECK28-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 18948 // CHECK28-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 18949 // CHECK28-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 18950 // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 18951 // CHECK28: omp.body.continue: 18952 // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 18953 // CHECK28: omp.inner.for.inc: 18954 // CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18955 // CHECK28-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 18956 // CHECK28-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 18957 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] 18958 // CHECK28: omp.inner.for.end: 18959 // CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 18960 // CHECK28: omp.loop.exit: 18961 // CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 18962 // CHECK28-NEXT: ret void 18963 // 18964 // 18965 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 18966 // CHECK28-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 18967 // CHECK28-NEXT: entry: 18968 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18969 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 18970 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 18971 // CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 18972 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 18973 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 18974 // CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 18975 // CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 18976 // CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 18977 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 18978 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 18979 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 18980 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18981 // CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 18982 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 18983 // CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 18984 // CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 18985 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 18986 // CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 18987 // CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 18988 // CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 18989 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 18990 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 18991 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 18992 // CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 18993 // CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 18994 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 18995 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 18996 // CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 18997 // CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 18998 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 18999 // CHECK28-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 19000 // CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 19001 // CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 19002 // CHECK28-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 19003 // CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 19004 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 19005 // CHECK28-NEXT: ret void 19006 // 19007 // 19008 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 19009 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 19010 // CHECK28-NEXT: entry: 19011 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 19012 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 19013 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 19014 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 19015 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 19016 // CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 19017 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 19018 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 19019 // CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 19020 // CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 19021 // CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 19022 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 19023 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 19024 // CHECK28-NEXT: [[TMP:%.*]] = alloca i8, align 1 19025 // CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 19026 // CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 19027 // CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 19028 // CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 19029 // CHECK28-NEXT: [[IT:%.*]] = alloca i8, align 1 19030 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 19031 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 19032 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 19033 // CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 19034 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 19035 // CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 19036 // CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 19037 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 19038 // CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 19039 // CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 19040 // CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 19041 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 19042 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 19043 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 19044 // CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 19045 // CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 19046 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 19047 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 19048 // CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 19049 // CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 19050 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 19051 // CHECK28-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 19052 // CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 19053 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 19054 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 19055 // CHECK28-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 19056 // CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 19057 // CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 19058 // CHECK28-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 19059 // CHECK28: omp.dispatch.cond: 19060 // CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 19061 // CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 19062 // CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 19063 // CHECK28: cond.true: 19064 // CHECK28-NEXT: br label [[COND_END:%.*]] 19065 // CHECK28: cond.false: 19066 // CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 19067 // CHECK28-NEXT: br label [[COND_END]] 19068 // CHECK28: cond.end: 19069 // CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 19070 // CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 19071 // CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 19072 // CHECK28-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 19073 // CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 19074 // CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 19075 // CHECK28-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 19076 // CHECK28-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 19077 // CHECK28: omp.dispatch.body: 19078 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 19079 // CHECK28: omp.inner.for.cond: 19080 // CHECK28-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 19081 // CHECK28-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 19082 // CHECK28-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 19083 // CHECK28-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 19084 // CHECK28: omp.inner.for.body: 19085 // CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 19086 // CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 19087 // CHECK28-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 19088 // CHECK28-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 19089 // CHECK28-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 19090 // CHECK28-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 19091 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 19092 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 19093 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 19094 // CHECK28-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 19095 // CHECK28-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 19096 // CHECK28-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 19097 // CHECK28-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 19098 // CHECK28-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 19099 // CHECK28-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 19100 // CHECK28-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 19101 // CHECK28-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 19102 // CHECK28-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 19103 // CHECK28-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 19104 // CHECK28-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 19105 // CHECK28-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 19106 // CHECK28-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 19107 // CHECK28-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 19108 // CHECK28-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 19109 // CHECK28-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 19110 // CHECK28-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 19111 // CHECK28-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 19112 // CHECK28-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 19113 // CHECK28-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 19114 // CHECK28-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 19115 // CHECK28-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 19116 // CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 19117 // CHECK28-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 19118 // CHECK28-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 19119 // CHECK28-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 19120 // CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 19121 // CHECK28-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 19122 // CHECK28-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 19123 // CHECK28-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 19124 // CHECK28-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 19125 // CHECK28-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 19126 // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 19127 // CHECK28: omp.body.continue: 19128 // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 19129 // CHECK28: omp.inner.for.inc: 19130 // CHECK28-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 19131 // CHECK28-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 19132 // CHECK28-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 19133 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] 19134 // CHECK28: omp.inner.for.end: 19135 // CHECK28-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 19136 // CHECK28: omp.dispatch.inc: 19137 // CHECK28-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 19138 // CHECK28-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 19139 // CHECK28-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 19140 // CHECK28-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 19141 // CHECK28-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 19142 // CHECK28-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 19143 // CHECK28-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 19144 // CHECK28-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 19145 // CHECK28-NEXT: br label [[OMP_DISPATCH_COND]] 19146 // CHECK28: omp.dispatch.end: 19147 // CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 19148 // CHECK28-NEXT: ret void 19149 // 19150 // 19151 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 19152 // CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 19153 // CHECK28-NEXT: entry: 19154 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 19155 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 19156 // CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 19157 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 19158 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 19159 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 19160 // CHECK28-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 19161 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 19162 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 19163 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 19164 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 19165 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 19166 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 19167 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 19168 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 19169 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 19170 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 19171 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 19172 // CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 19173 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 19174 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 19175 // CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 19176 // CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 19177 // CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 19178 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 19179 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 19180 // CHECK28-NEXT: ret void 19181 // 19182 // 19183 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 19184 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 19185 // CHECK28-NEXT: entry: 19186 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 19187 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 19188 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 19189 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 19190 // CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 19191 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 19192 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 19193 // CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 19194 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 19195 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 19196 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 19197 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 19198 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 19199 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 19200 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 19201 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 19202 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 19203 // CHECK28-NEXT: ret void 19204 // 19205 // 19206 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 19207 // CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 19208 // CHECK28-NEXT: entry: 19209 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 19210 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 19211 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 19212 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 19213 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 19214 // CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 19215 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 19216 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 19217 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 19218 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 19219 // CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 19220 // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 19221 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 19222 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 19223 // CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 19224 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 19225 // CHECK28-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 19226 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 19227 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 19228 // CHECK28-NEXT: ret void 19229 // 19230 // 19231 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 19232 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 19233 // CHECK28-NEXT: entry: 19234 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 19235 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 19236 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 19237 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 19238 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 19239 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 19240 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 19241 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 19242 // CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4 19243 // CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 19244 // CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 19245 // CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 19246 // CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 19247 // CHECK28-NEXT: [[IT:%.*]] = alloca i64, align 8 19248 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 19249 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 19250 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 19251 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 19252 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 19253 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 19254 // CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 19255 // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 19256 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 19257 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 19258 // CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 19259 // CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 19260 // CHECK28-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 19261 // CHECK28-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 19262 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 19263 // CHECK28-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 19264 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 19265 // CHECK28-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 19266 // CHECK28-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 19267 // CHECK28-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 19268 // CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 19269 // CHECK28: cond.true: 19270 // CHECK28-NEXT: br label [[COND_END:%.*]] 19271 // CHECK28: cond.false: 19272 // CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 19273 // CHECK28-NEXT: br label [[COND_END]] 19274 // CHECK28: cond.end: 19275 // CHECK28-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 19276 // CHECK28-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 19277 // CHECK28-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 19278 // CHECK28-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 19279 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 19280 // CHECK28: omp.inner.for.cond: 19281 // CHECK28-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 19282 // CHECK28-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 19283 // CHECK28-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 19284 // CHECK28-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 19285 // CHECK28: omp.inner.for.body: 19286 // CHECK28-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 19287 // CHECK28-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 19288 // CHECK28-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 19289 // CHECK28-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 19290 // CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 19291 // CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 19292 // CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 19293 // CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 19294 // CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 19295 // CHECK28-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 19296 // CHECK28-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 19297 // CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 19298 // CHECK28-NEXT: store double [[INC]], double* [[A4]], align 4 19299 // CHECK28-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 19300 // CHECK28-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 19301 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 19302 // CHECK28-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 19303 // CHECK28-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 19304 // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 19305 // CHECK28: omp.body.continue: 19306 // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 19307 // CHECK28: omp.inner.for.inc: 19308 // CHECK28-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 19309 // CHECK28-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 19310 // CHECK28-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 19311 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] 19312 // CHECK28: omp.inner.for.end: 19313 // CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 19314 // CHECK28: omp.loop.exit: 19315 // CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 19316 // CHECK28-NEXT: ret void 19317 // 19318 // 19319 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 19320 // CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 19321 // CHECK28-NEXT: entry: 19322 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 19323 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 19324 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 19325 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 19326 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 19327 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 19328 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 19329 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 19330 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 19331 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 19332 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 19333 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 19334 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 19335 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 19336 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 19337 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 19338 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 19339 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 19340 // CHECK28-NEXT: ret void 19341 // 19342 // 19343 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 19344 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 19345 // CHECK28-NEXT: entry: 19346 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 19347 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 19348 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 19349 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 19350 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 19351 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 19352 // CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4 19353 // CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 19354 // CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 19355 // CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 19356 // CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 19357 // CHECK28-NEXT: [[I:%.*]] = alloca i64, align 8 19358 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 19359 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 19360 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 19361 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 19362 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 19363 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 19364 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 19365 // CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 19366 // CHECK28-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 19367 // CHECK28-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 19368 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 19369 // CHECK28-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 19370 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 19371 // CHECK28-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 19372 // CHECK28-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 19373 // CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 19374 // CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 19375 // CHECK28: cond.true: 19376 // CHECK28-NEXT: br label [[COND_END:%.*]] 19377 // CHECK28: cond.false: 19378 // CHECK28-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 19379 // CHECK28-NEXT: br label [[COND_END]] 19380 // CHECK28: cond.end: 19381 // CHECK28-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 19382 // CHECK28-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 19383 // CHECK28-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 19384 // CHECK28-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 19385 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 19386 // CHECK28: omp.inner.for.cond: 19387 // CHECK28-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 19388 // CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 19389 // CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 19390 // CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 19391 // CHECK28: omp.inner.for.body: 19392 // CHECK28-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 19393 // CHECK28-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 19394 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 19395 // CHECK28-NEXT: store i64 [[ADD]], i64* [[I]], align 8 19396 // CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 19397 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 19398 // CHECK28-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 19399 // CHECK28-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 19400 // CHECK28-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 19401 // CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 19402 // CHECK28-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 19403 // CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 19404 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 19405 // CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 19406 // CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 19407 // CHECK28-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 19408 // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 19409 // CHECK28: omp.body.continue: 19410 // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 19411 // CHECK28: omp.inner.for.inc: 19412 // CHECK28-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 19413 // CHECK28-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 19414 // CHECK28-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 19415 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] 19416 // CHECK28: omp.inner.for.end: 19417 // CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 19418 // CHECK28: omp.loop.exit: 19419 // CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 19420 // CHECK28-NEXT: ret void 19421 // 19422