1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test host codegen.
3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
9
10 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
12 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
13 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
15 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
16
17 // Test target codegen - host bc file has to be created first.
18 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
19 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
20 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
22 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
23 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
24 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
25 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
26
27 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
28 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
29 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
30 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
31 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
32 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
33 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
34 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
35
36 // Test host codegen.
37 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17
38 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
39 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17
40 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19
41 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
42 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19
43
44 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
45 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
46 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
47 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
48 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
49 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
50
51 // Test target codegen - host bc file has to be created first.
52 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
53 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
54 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
55 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
56 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
57 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
58 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
59 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
60
61 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
62 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
63 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
64 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
65 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
66 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
67 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
68 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
69
70 // expected-no-diagnostics
71 #ifndef HEADER
72 #define HEADER
73
74
75
76
77 // We have 8 target regions, but only 7 that actually will generate offloading
78 // code, only 6 will have mapped arguments, and only 4 have all-constant map
79 // sizes.
80
81
82
83 // Check target registration is registered as a Ctor.
84
85
86 template<typename tx, typename ty>
87 struct TT{
88 tx X;
89 ty Y;
90 };
91
get_val()92 long long get_val() { return 0; }
93
foo(int n)94 int foo(int n) {
95 int a = 0;
96 short aa = 0;
97 float b[10];
98 float bn[n];
99 double c[5][10];
100 double cn[5][n];
101 TT<long long, char> d;
102
103 #pragma omp target parallel for
104 for (int i = 3; i < 32; i += 5) {
105 #pragma omp cancel for
106 #pragma omp cancellation point for
107 }
108
109 long long k = get_val();
110 #pragma omp target parallel for if(target: 0) linear(k : 3) schedule(dynamic)
111 for (int i = 10; i > 1; i--) {
112 a += 1;
113 }
114
115 // CEHCK-32: [[FPSIZEGEP]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 0
116 // CEHCK-32: [[FPSIZEADDR:%.+]] = bitcast [3 x i64]* [[FPSIZEGEP]] to i8*
117 // CEHCK-32: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPSIZEADDR]], i8* align 8 bitcast ([3 x i64]* [[SIZET2]] to i8*), i64 24, i1 false)
118 // CEHCK-32: [[FPBPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 1
119 // CEHCK-32: [[FPBPADDR:%.+]] = bitcast [3 x i8*]* [[FPBPGEP]] to i8*
120 // CEHCK-32: [[BPCAST:%.+]] = bitcast i8** [[BPGEP]] to i8*
121 // CEHCK-32: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPBPADDR]], i8* align 8 [[BPCAST]], i64 24, i1 false)
122 // CEHCK-32: [[FPPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 2
123 // CEHCK-32: [[FPPADDR:%.+]] = bitcast [3 x i8*]* [[FPPGEP]] to i8*
124 // CEHCK-32: [[PCAST:%.+]] = bitcast i8** [[PGEP]] to i8*
125 // CEHCK-32: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPPADDR]], i8* align 8 [[BCAST]], i64 24, i1 false)
126 // CEHCK-64: [[FPBPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 0
127 // CEHCK-64: [[FPBPADDR:%.+]] = bitcast [3 x i8*]* [[FPBPGEP]] to i8*
128 // CEHCK-64: [[BPCAST:%.+]] = bitcast i8** [[BPGEP]] to i8*
129 // CEHCK-64: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPBPADDR]], i8* align 8 [[BPCAST]], i64 24, i1 false)
130 // CEHCK-64: [[FPPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 1
131 // CEHCK-64: [[FPPADDR:%.+]] = bitcast [3 x i8*]* [[FPPGEP]] to i8*
132 // CEHCK-64: [[PCAST:%.+]] = bitcast i8** [[PGEP]] to i8*
133 // CEHCK-64: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPPADDR]], i8* align 8 [[BCAST]], i64 24, i1 false)
134 // CEHCK-64: [[FPSIZEGEP]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 2
135 // CEHCK-64: [[FPSIZEADDR:%.+]] = bitcast [3 x i64]* [[FPSIZEGEP]] to i8*
136 // CEHCK-64: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPSIZEADDR]], i8* align 8 bitcast ([3 x i64]* [[SIZET2]] to i8*), i64 24, i1 false)
137 int lin = 12;
138 #pragma omp target parallel for if(target: 1) linear(lin, a : get_val()) nowait
139 for (unsigned long long it = 2000; it >= 600; it-=400) {
140 aa += 1;
141 }
142
143
144
145
146 #pragma omp target parallel for if(target: n>10)
147 for (short it = 6; it <= 20; it-=-4) {
148 a += 1;
149 aa += 1;
150 }
151
152 // We capture 3 VLA sizes in this target region
153
154
155
156
157
158 // The names below are not necessarily consistent with the names used for the
159 // addresses above as some are repeated.
160
161
162
163
164
165
166
167
168
169
170 #pragma omp target parallel for if(target: n>20) schedule(static, a)
171 for (unsigned char it = 'z'; it >= 'a'; it+=-1) {
172 a += 1;
173 b[2] += 1.0;
174 bn[3] += 1.0;
175 c[1][2] += 1.0;
176 cn[1][3] += 1.0;
177 d.X += 1;
178 d.Y += 1;
179 }
180
181 return a;
182 }
183
184 // Check that the offloading functions are emitted and that the arguments are
185 // correct and loaded correctly for the target regions in foo().
186
187
188 // Create stack storage and store argument in there.
189
190 // Create stack storage and store argument in there.
191
192
193 // Create stack storage and store argument in there.
194
195 // Create local storage for each capture.
196
197
198
199 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
200
201 template<typename tx>
ftemplate(int n)202 tx ftemplate(int n) {
203 tx a = 0;
204 short aa = 0;
205 tx b[10];
206
207 #pragma omp target parallel for if(target: n>40)
208 for (long long i = -10; i < 10; i += 3) {
209 a += 1;
210 aa += 1;
211 b[2] += 1;
212 }
213
214 return a;
215 }
216
217 static
fstatic(int n)218 int fstatic(int n) {
219 int a = 0;
220 short aa = 0;
221 char aaa = 0;
222 int b[10];
223
224 #pragma omp target parallel for if(target: n>50)
225 for (unsigned i=100; i<10; i+=10) {
226 a += 1;
227 aa += 1;
228 aaa += 1;
229 b[2] += 1;
230 }
231
232 return a;
233 }
234
235 struct S1 {
236 double a;
237
r1S1238 int r1(int n){
239 int b = n+1;
240 short int c[2][n];
241
242 #pragma omp target parallel for if(target: n>60)
243 for (unsigned long long it = 2000; it >= 600; it -= 400) {
244 this->a = (double)b + 1.5;
245 c[1][1] = ++a;
246 }
247
248 return c[1][1] + (int)b;
249 }
250 };
251
bar(int n)252 int bar(int n){
253 int a = 0;
254
255 a += foo(n);
256
257 S1 S;
258 a += S.r1(n);
259
260 a += fstatic(n);
261
262 a += ftemplate<int>(n);
263
264 return a;
265 }
266
267
268
269 // We capture 2 VLA sizes in this target region
270
271
272 // The names below are not necessarily consistent with the names used for the
273 // addresses above as some are repeated.
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292 // Check that the offloading functions are emitted and that the arguments are
293 // correct and loaded correctly for the target regions of the callees of bar().
294
295 // Create local storage for each capture.
296 // Store captures in the context.
297
298
299 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
300
301
302 // Create local storage for each capture.
303 // Store captures in the context.
304
305
306
307
308 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
309
310 // Create local storage for each capture.
311 // Store captures in the context.
312
313
314
315 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
316
317
318 #endif
319 // CHECK1-LABEL: define {{[^@]+}}@_Z7get_valv
320 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
321 // CHECK1-NEXT: entry:
322 // CHECK1-NEXT: ret i64 0
323 //
324 //
325 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi
326 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
327 // CHECK1-NEXT: entry:
328 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
329 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
330 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
331 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4
332 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
333 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
334 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
335 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
336 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
337 // CHECK1-NEXT: [[K:%.*]] = alloca i64, align 8
338 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
339 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
340 // CHECK1-NEXT: [[LIN:%.*]] = alloca i32, align 4
341 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
342 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
343 // CHECK1-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8
344 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
345 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
346 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
347 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
348 // CHECK1-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8
349 // CHECK1-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8
350 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
351 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
352 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
353 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
354 // CHECK1-NEXT: [[A_CASTED16:%.*]] = alloca i64, align 8
355 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
356 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [10 x i8*], align 8
357 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [10 x i8*], align 8
358 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [10 x i8*], align 8
359 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
360 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
361 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
362 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4
363 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2
364 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
365 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
366 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
367 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
368 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
369 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
370 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
371 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
372 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
373 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
374 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
375 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
376 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
377 // CHECK1-NEXT: store i32 1, i32* [[TMP7]], align 4
378 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
379 // CHECK1-NEXT: store i32 0, i32* [[TMP8]], align 4
380 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
381 // CHECK1-NEXT: store i8** null, i8*** [[TMP9]], align 8
382 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
383 // CHECK1-NEXT: store i8** null, i8*** [[TMP10]], align 8
384 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
385 // CHECK1-NEXT: store i64* null, i64** [[TMP11]], align 8
386 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
387 // CHECK1-NEXT: store i64* null, i64** [[TMP12]], align 8
388 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
389 // CHECK1-NEXT: store i8** null, i8*** [[TMP13]], align 8
390 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
391 // CHECK1-NEXT: store i8** null, i8*** [[TMP14]], align 8
392 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
393 // CHECK1-NEXT: store i64 0, i64* [[TMP15]], align 8
394 // CHECK1-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
395 // CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
396 // CHECK1-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
397 // CHECK1: omp_offload.failed:
398 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]]
399 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
400 // CHECK1: omp_offload.cont:
401 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
402 // CHECK1-NEXT: store i64 [[CALL]], i64* [[K]], align 8
403 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4
404 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
405 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV]], align 4
406 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[A_CASTED]], align 8
407 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[K]], align 8
408 // CHECK1-NEXT: store i64 [[TMP20]], i64* [[K_CASTED]], align 8
409 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[K_CASTED]], align 8
410 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR4]]
411 // CHECK1-NEXT: store i32 12, i32* [[LIN]], align 4
412 // CHECK1-NEXT: [[TMP22:%.*]] = load i16, i16* [[AA]], align 2
413 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
414 // CHECK1-NEXT: store i16 [[TMP22]], i16* [[CONV2]], align 2
415 // CHECK1-NEXT: [[TMP23:%.*]] = load i64, i64* [[AA_CASTED]], align 8
416 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[LIN]], align 4
417 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
418 // CHECK1-NEXT: store i32 [[TMP24]], i32* [[CONV3]], align 4
419 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
420 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[A]], align 4
421 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32*
422 // CHECK1-NEXT: store i32 [[TMP26]], i32* [[CONV5]], align 4
423 // CHECK1-NEXT: [[TMP27:%.*]] = load i64, i64* [[A_CASTED4]], align 8
424 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
425 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
426 // CHECK1-NEXT: store i64 [[TMP23]], i64* [[TMP29]], align 8
427 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
428 // CHECK1-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
429 // CHECK1-NEXT: store i64 [[TMP23]], i64* [[TMP31]], align 8
430 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
431 // CHECK1-NEXT: store i8* null, i8** [[TMP32]], align 8
432 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
433 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
434 // CHECK1-NEXT: store i64 [[TMP25]], i64* [[TMP34]], align 8
435 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
436 // CHECK1-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64*
437 // CHECK1-NEXT: store i64 [[TMP25]], i64* [[TMP36]], align 8
438 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
439 // CHECK1-NEXT: store i8* null, i8** [[TMP37]], align 8
440 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
441 // CHECK1-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64*
442 // CHECK1-NEXT: store i64 [[TMP27]], i64* [[TMP39]], align 8
443 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
444 // CHECK1-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64*
445 // CHECK1-NEXT: store i64 [[TMP27]], i64* [[TMP41]], align 8
446 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
447 // CHECK1-NEXT: store i8* null, i8** [[TMP42]], align 8
448 // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
449 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
450 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
451 // CHECK1-NEXT: [[TMP46:%.*]] = load i16, i16* [[AA]], align 2
452 // CHECK1-NEXT: store i16 [[TMP46]], i16* [[TMP45]], align 4
453 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
454 // CHECK1-NEXT: [[TMP48:%.*]] = load i32, i32* [[LIN]], align 4
455 // CHECK1-NEXT: store i32 [[TMP48]], i32* [[TMP47]], align 4
456 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
457 // CHECK1-NEXT: [[TMP50:%.*]] = load i32, i32* [[A]], align 4
458 // CHECK1-NEXT: store i32 [[TMP50]], i32* [[TMP49]], align 4
459 // CHECK1-NEXT: [[TMP51:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
460 // CHECK1-NEXT: [[TMP52:%.*]] = bitcast i8* [[TMP51]] to %struct.kmp_task_t_with_privates*
461 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP52]], i32 0, i32 0
462 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP53]], i32 0, i32 0
463 // CHECK1-NEXT: [[TMP55:%.*]] = load i8*, i8** [[TMP54]], align 8
464 // CHECK1-NEXT: [[TMP56:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
465 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP55]], i8* align 4 [[TMP56]], i64 12, i1 false)
466 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP52]], i32 0, i32 1
467 // CHECK1-NEXT: [[TMP58:%.*]] = bitcast i8* [[TMP55]] to %struct.anon*
468 // CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP57]], i32 0, i32 0
469 // CHECK1-NEXT: [[TMP60:%.*]] = bitcast [3 x i8*]* [[TMP59]] to i8*
470 // CHECK1-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP43]] to i8*
471 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP60]], i8* align 8 [[TMP61]], i64 24, i1 false)
472 // CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP57]], i32 0, i32 1
473 // CHECK1-NEXT: [[TMP63:%.*]] = bitcast [3 x i8*]* [[TMP62]] to i8*
474 // CHECK1-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP44]] to i8*
475 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP63]], i8* align 8 [[TMP64]], i64 24, i1 false)
476 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP57]], i32 0, i32 2
477 // CHECK1-NEXT: [[TMP66:%.*]] = bitcast [3 x i64]* [[TMP65]] to i8*
478 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP66]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
479 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP57]], i32 0, i32 3
480 // CHECK1-NEXT: [[TMP68:%.*]] = load i16, i16* [[AA]], align 2
481 // CHECK1-NEXT: store i16 [[TMP68]], i16* [[TMP67]], align 8
482 // CHECK1-NEXT: [[TMP69:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP51]])
483 // CHECK1-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4
484 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32*
485 // CHECK1-NEXT: store i32 [[TMP70]], i32* [[CONV7]], align 4
486 // CHECK1-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED6]], align 8
487 // CHECK1-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2
488 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16*
489 // CHECK1-NEXT: store i16 [[TMP72]], i16* [[CONV9]], align 2
490 // CHECK1-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED8]], align 8
491 // CHECK1-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4
492 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10
493 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
494 // CHECK1: omp_if.then:
495 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
496 // CHECK1-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64*
497 // CHECK1-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8
498 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
499 // CHECK1-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
500 // CHECK1-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8
501 // CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
502 // CHECK1-NEXT: store i8* null, i8** [[TMP79]], align 8
503 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
504 // CHECK1-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
505 // CHECK1-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8
506 // CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
507 // CHECK1-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
508 // CHECK1-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8
509 // CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
510 // CHECK1-NEXT: store i8* null, i8** [[TMP84]], align 8
511 // CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
512 // CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
513 // CHECK1-NEXT: [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
514 // CHECK1-NEXT: [[TMP87:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 0
515 // CHECK1-NEXT: store i32 1, i32* [[TMP87]], align 4
516 // CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 1
517 // CHECK1-NEXT: store i32 2, i32* [[TMP88]], align 4
518 // CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 2
519 // CHECK1-NEXT: store i8** [[TMP85]], i8*** [[TMP89]], align 8
520 // CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 3
521 // CHECK1-NEXT: store i8** [[TMP86]], i8*** [[TMP90]], align 8
522 // CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 4
523 // CHECK1-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64** [[TMP91]], align 8
524 // CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 5
525 // CHECK1-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP92]], align 8
526 // CHECK1-NEXT: [[TMP93:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 6
527 // CHECK1-NEXT: store i8** null, i8*** [[TMP93]], align 8
528 // CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 7
529 // CHECK1-NEXT: store i8** null, i8*** [[TMP94]], align 8
530 // CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 8
531 // CHECK1-NEXT: store i64 0, i64* [[TMP95]], align 8
532 // CHECK1-NEXT: [[TMP96:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]])
533 // CHECK1-NEXT: [[TMP97:%.*]] = icmp ne i32 [[TMP96]], 0
534 // CHECK1-NEXT: br i1 [[TMP97]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]
535 // CHECK1: omp_offload.failed14:
536 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR4]]
537 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT15]]
538 // CHECK1: omp_offload.cont15:
539 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
540 // CHECK1: omp_if.else:
541 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR4]]
542 // CHECK1-NEXT: br label [[OMP_IF_END]]
543 // CHECK1: omp_if.end:
544 // CHECK1-NEXT: [[TMP98:%.*]] = load i32, i32* [[A]], align 4
545 // CHECK1-NEXT: store i32 [[TMP98]], i32* [[DOTCAPTURE_EXPR_]], align 4
546 // CHECK1-NEXT: [[TMP99:%.*]] = load i32, i32* [[A]], align 4
547 // CHECK1-NEXT: [[CONV17:%.*]] = bitcast i64* [[A_CASTED16]] to i32*
548 // CHECK1-NEXT: store i32 [[TMP99]], i32* [[CONV17]], align 4
549 // CHECK1-NEXT: [[TMP100:%.*]] = load i64, i64* [[A_CASTED16]], align 8
550 // CHECK1-NEXT: [[TMP101:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
551 // CHECK1-NEXT: [[CONV18:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
552 // CHECK1-NEXT: store i32 [[TMP101]], i32* [[CONV18]], align 4
553 // CHECK1-NEXT: [[TMP102:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
554 // CHECK1-NEXT: [[TMP103:%.*]] = load i32, i32* [[N_ADDR]], align 4
555 // CHECK1-NEXT: [[CMP19:%.*]] = icmp sgt i32 [[TMP103]], 20
556 // CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN20:%.*]], label [[OMP_IF_ELSE27:%.*]]
557 // CHECK1: omp_if.then20:
558 // CHECK1-NEXT: [[TMP104:%.*]] = mul nuw i64 [[TMP2]], 4
559 // CHECK1-NEXT: [[TMP105:%.*]] = mul nuw i64 5, [[TMP5]]
560 // CHECK1-NEXT: [[TMP106:%.*]] = mul nuw i64 [[TMP105]], 8
561 // CHECK1-NEXT: [[TMP107:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
562 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP107]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i64 80, i1 false)
563 // CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0
564 // CHECK1-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i64*
565 // CHECK1-NEXT: store i64 [[TMP100]], i64* [[TMP109]], align 8
566 // CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0
567 // CHECK1-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i64*
568 // CHECK1-NEXT: store i64 [[TMP100]], i64* [[TMP111]], align 8
569 // CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 0
570 // CHECK1-NEXT: store i8* null, i8** [[TMP112]], align 8
571 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1
572 // CHECK1-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [10 x float]**
573 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP114]], align 8
574 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1
575 // CHECK1-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to [10 x float]**
576 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP116]], align 8
577 // CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 1
578 // CHECK1-NEXT: store i8* null, i8** [[TMP117]], align 8
579 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2
580 // CHECK1-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i64*
581 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP119]], align 8
582 // CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2
583 // CHECK1-NEXT: [[TMP121:%.*]] = bitcast i8** [[TMP120]] to i64*
584 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP121]], align 8
585 // CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 2
586 // CHECK1-NEXT: store i8* null, i8** [[TMP122]], align 8
587 // CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3
588 // CHECK1-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to float**
589 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP124]], align 8
590 // CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3
591 // CHECK1-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to float**
592 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP126]], align 8
593 // CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
594 // CHECK1-NEXT: store i64 [[TMP104]], i64* [[TMP127]], align 8
595 // CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 3
596 // CHECK1-NEXT: store i8* null, i8** [[TMP128]], align 8
597 // CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 4
598 // CHECK1-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to [5 x [10 x double]]**
599 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP130]], align 8
600 // CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 4
601 // CHECK1-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to [5 x [10 x double]]**
602 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP132]], align 8
603 // CHECK1-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 4
604 // CHECK1-NEXT: store i8* null, i8** [[TMP133]], align 8
605 // CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 5
606 // CHECK1-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i64*
607 // CHECK1-NEXT: store i64 5, i64* [[TMP135]], align 8
608 // CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 5
609 // CHECK1-NEXT: [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i64*
610 // CHECK1-NEXT: store i64 5, i64* [[TMP137]], align 8
611 // CHECK1-NEXT: [[TMP138:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 5
612 // CHECK1-NEXT: store i8* null, i8** [[TMP138]], align 8
613 // CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 6
614 // CHECK1-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to i64*
615 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP140]], align 8
616 // CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 6
617 // CHECK1-NEXT: [[TMP142:%.*]] = bitcast i8** [[TMP141]] to i64*
618 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP142]], align 8
619 // CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 6
620 // CHECK1-NEXT: store i8* null, i8** [[TMP143]], align 8
621 // CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 7
622 // CHECK1-NEXT: [[TMP145:%.*]] = bitcast i8** [[TMP144]] to double**
623 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP145]], align 8
624 // CHECK1-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 7
625 // CHECK1-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to double**
626 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP147]], align 8
627 // CHECK1-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
628 // CHECK1-NEXT: store i64 [[TMP106]], i64* [[TMP148]], align 8
629 // CHECK1-NEXT: [[TMP149:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 7
630 // CHECK1-NEXT: store i8* null, i8** [[TMP149]], align 8
631 // CHECK1-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 8
632 // CHECK1-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to %struct.TT**
633 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP151]], align 8
634 // CHECK1-NEXT: [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 8
635 // CHECK1-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to %struct.TT**
636 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP153]], align 8
637 // CHECK1-NEXT: [[TMP154:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 8
638 // CHECK1-NEXT: store i8* null, i8** [[TMP154]], align 8
639 // CHECK1-NEXT: [[TMP155:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 9
640 // CHECK1-NEXT: [[TMP156:%.*]] = bitcast i8** [[TMP155]] to i64*
641 // CHECK1-NEXT: store i64 [[TMP102]], i64* [[TMP156]], align 8
642 // CHECK1-NEXT: [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 9
643 // CHECK1-NEXT: [[TMP158:%.*]] = bitcast i8** [[TMP157]] to i64*
644 // CHECK1-NEXT: store i64 [[TMP102]], i64* [[TMP158]], align 8
645 // CHECK1-NEXT: [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 9
646 // CHECK1-NEXT: store i8* null, i8** [[TMP159]], align 8
647 // CHECK1-NEXT: [[TMP160:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0
648 // CHECK1-NEXT: [[TMP161:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0
649 // CHECK1-NEXT: [[TMP162:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
650 // CHECK1-NEXT: [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
651 // CHECK1-NEXT: [[TMP163:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 0
652 // CHECK1-NEXT: store i32 1, i32* [[TMP163]], align 4
653 // CHECK1-NEXT: [[TMP164:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 1
654 // CHECK1-NEXT: store i32 10, i32* [[TMP164]], align 4
655 // CHECK1-NEXT: [[TMP165:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 2
656 // CHECK1-NEXT: store i8** [[TMP160]], i8*** [[TMP165]], align 8
657 // CHECK1-NEXT: [[TMP166:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 3
658 // CHECK1-NEXT: store i8** [[TMP161]], i8*** [[TMP166]], align 8
659 // CHECK1-NEXT: [[TMP167:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 4
660 // CHECK1-NEXT: store i64* [[TMP162]], i64** [[TMP167]], align 8
661 // CHECK1-NEXT: [[TMP168:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 5
662 // CHECK1-NEXT: store i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i64** [[TMP168]], align 8
663 // CHECK1-NEXT: [[TMP169:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 6
664 // CHECK1-NEXT: store i8** null, i8*** [[TMP169]], align 8
665 // CHECK1-NEXT: [[TMP170:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 7
666 // CHECK1-NEXT: store i8** null, i8*** [[TMP170]], align 8
667 // CHECK1-NEXT: [[TMP171:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 8
668 // CHECK1-NEXT: store i64 0, i64* [[TMP171]], align 8
669 // CHECK1-NEXT: [[TMP172:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]])
670 // CHECK1-NEXT: [[TMP173:%.*]] = icmp ne i32 [[TMP172]], 0
671 // CHECK1-NEXT: br i1 [[TMP173]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]]
672 // CHECK1: omp_offload.failed25:
673 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP100]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP102]]) #[[ATTR4]]
674 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT26]]
675 // CHECK1: omp_offload.cont26:
676 // CHECK1-NEXT: br label [[OMP_IF_END28:%.*]]
677 // CHECK1: omp_if.else27:
678 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP100]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP102]]) #[[ATTR4]]
679 // CHECK1-NEXT: br label [[OMP_IF_END28]]
680 // CHECK1: omp_if.end28:
681 // CHECK1-NEXT: [[TMP174:%.*]] = load i32, i32* [[A]], align 4
682 // CHECK1-NEXT: [[TMP175:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
683 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP175]])
684 // CHECK1-NEXT: ret i32 [[TMP174]]
685 //
686 //
687 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
688 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] {
689 // CHECK1-NEXT: entry:
690 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
691 // CHECK1-NEXT: ret void
692 //
693 //
694 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
695 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
696 // CHECK1-NEXT: entry:
697 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
698 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
699 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
700 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
701 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
702 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
703 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
704 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
705 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
706 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
707 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
708 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
709 // CHECK1-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
710 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
711 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
712 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
713 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
714 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
715 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
716 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
717 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
718 // CHECK1: cond.true:
719 // CHECK1-NEXT: br label [[COND_END:%.*]]
720 // CHECK1: cond.false:
721 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
722 // CHECK1-NEXT: br label [[COND_END]]
723 // CHECK1: cond.end:
724 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
725 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
726 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
727 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
728 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
729 // CHECK1: omp.inner.for.cond:
730 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
731 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
732 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
733 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
734 // CHECK1: omp.inner.for.body:
735 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
736 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
737 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
738 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
739 // CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
740 // CHECK1-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
741 // CHECK1-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
742 // CHECK1: .cancel.exit:
743 // CHECK1-NEXT: br label [[CANCEL_EXIT:%.*]]
744 // CHECK1: .cancel.continue:
745 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
746 // CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
747 // CHECK1-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
748 // CHECK1: .cancel.exit2:
749 // CHECK1-NEXT: br label [[CANCEL_EXIT]]
750 // CHECK1: .cancel.continue3:
751 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
752 // CHECK1: omp.body.continue:
753 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
754 // CHECK1: omp.inner.for.inc:
755 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
756 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
757 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
758 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
759 // CHECK1: omp.inner.for.end:
760 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
761 // CHECK1: omp.loop.exit:
762 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
763 // CHECK1-NEXT: br label [[CANCEL_CONT:%.*]]
764 // CHECK1: cancel.cont:
765 // CHECK1-NEXT: ret void
766 // CHECK1: cancel.exit:
767 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
768 // CHECK1-NEXT: br label [[CANCEL_CONT]]
769 //
770 //
771 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
772 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] {
773 // CHECK1-NEXT: entry:
774 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
775 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
776 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
777 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
778 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
779 // CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
780 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
781 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
782 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
783 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
784 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
785 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
786 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8
787 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
788 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
789 // CHECK1-NEXT: ret void
790 //
791 //
792 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
793 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] {
794 // CHECK1-NEXT: entry:
795 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
796 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
797 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
798 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
799 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
800 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
801 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
802 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
803 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
804 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
805 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
806 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
807 // CHECK1-NEXT: [[K1:%.*]] = alloca i64, align 8
808 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
809 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
810 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
811 // CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
812 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
813 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8
814 // CHECK1-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8
815 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
816 // CHECK1-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
817 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
818 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
819 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
820 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
821 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]])
822 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1)
823 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
824 // CHECK1: omp.dispatch.cond:
825 // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
826 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
827 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
828 // CHECK1: omp.dispatch.body:
829 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
830 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
831 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
832 // CHECK1: omp.inner.for.cond:
833 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
834 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]
835 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
836 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
837 // CHECK1: omp.inner.for.body:
838 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
839 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
840 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
841 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
842 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP12]]
843 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
844 // CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
845 // CHECK1-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
846 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
847 // CHECK1-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group [[ACC_GRP12]]
848 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP12]]
849 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
850 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP12]]
851 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
852 // CHECK1: omp.body.continue:
853 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
854 // CHECK1: omp.inner.for.inc:
855 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
856 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
857 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
858 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
859 // CHECK1: omp.inner.for.end:
860 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
861 // CHECK1: omp.dispatch.inc:
862 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
863 // CHECK1: omp.dispatch.end:
864 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
865 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
866 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
867 // CHECK1: .omp.linear.pu:
868 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[K1]], align 8
869 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[K_ADDR]], align 8
870 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
871 // CHECK1: .omp.linear.pu.done:
872 // CHECK1-NEXT: ret void
873 //
874 //
875 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
876 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {
877 // CHECK1-NEXT: entry:
878 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
879 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
880 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
881 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
882 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
883 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
884 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
885 // CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
886 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
887 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
888 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
889 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
890 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
891 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
892 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
893 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
894 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
895 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
896 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
897 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
898 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
899 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
900 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
901 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
902 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
903 // CHECK1-NEXT: ret void
904 //
905 //
906 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
907 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {
908 // CHECK1-NEXT: entry:
909 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
910 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
911 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
912 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
913 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
914 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
915 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8
916 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
917 // CHECK1-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
918 // CHECK1-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
919 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
920 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
921 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
922 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
923 // CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8
924 // CHECK1-NEXT: [[LIN4:%.*]] = alloca i32, align 4
925 // CHECK1-NEXT: [[A5:%.*]] = alloca i32, align 4
926 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
927 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
928 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
929 // CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
930 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
931 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
932 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
933 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
934 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
935 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
936 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
937 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
938 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
939 // CHECK1-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
940 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
941 // CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
942 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
943 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
944 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
945 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
946 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
947 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
948 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
949 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
950 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
951 // CHECK1: cond.true:
952 // CHECK1-NEXT: br label [[COND_END:%.*]]
953 // CHECK1: cond.false:
954 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
955 // CHECK1-NEXT: br label [[COND_END]]
956 // CHECK1: cond.end:
957 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
958 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
959 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
960 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
961 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
962 // CHECK1: omp.inner.for.cond:
963 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
964 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
965 // CHECK1-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
966 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
967 // CHECK1: omp.inner.for.body:
968 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
969 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
970 // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
971 // CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
972 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
973 // CHECK1-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
974 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
975 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
976 // CHECK1-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
977 // CHECK1-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
978 // CHECK1-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
979 // CHECK1-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4
980 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
981 // CHECK1-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
982 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
983 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
984 // CHECK1-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
985 // CHECK1-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
986 // CHECK1-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
987 // CHECK1-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
988 // CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
989 // CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
990 // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
991 // CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
992 // CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
993 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
994 // CHECK1: omp.body.continue:
995 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
996 // CHECK1: omp.inner.for.inc:
997 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
998 // CHECK1-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
999 // CHECK1-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
1000 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
1001 // CHECK1: omp.inner.for.end:
1002 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1003 // CHECK1: omp.loop.exit:
1004 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
1005 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1006 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
1007 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
1008 // CHECK1: .omp.linear.pu:
1009 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
1010 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
1011 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
1012 // CHECK1-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
1013 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
1014 // CHECK1: .omp.linear.pu.done:
1015 // CHECK1-NEXT: ret void
1016 //
1017 //
1018 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.
1019 // CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
1020 // CHECK1-NEXT: entry:
1021 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
1022 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8
1023 // CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
1024 // CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
1025 // CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
1026 // CHECK1-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
1027 // CHECK1-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
1028 // CHECK1-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
1029 // CHECK1-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
1030 // CHECK1-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
1031 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
1032 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
1033 // CHECK1-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
1034 // CHECK1-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
1035 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
1036 // CHECK1-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
1037 // CHECK1-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
1038 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
1039 // CHECK1-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
1040 // CHECK1-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
1041 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
1042 // CHECK1-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
1043 // CHECK1-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8
1044 // CHECK1-NEXT: ret void
1045 //
1046 //
1047 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.
1048 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
1049 // CHECK1-NEXT: entry:
1050 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
1051 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
1052 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
1053 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
1054 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
1055 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
1056 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
1057 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
1058 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
1059 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
1060 // CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8
1061 // CHECK1-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8
1062 // CHECK1-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8
1063 // CHECK1-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1064 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
1065 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
1066 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
1067 // CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
1068 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
1069 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
1070 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
1071 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
1072 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
1073 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
1074 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
1075 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
1076 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
1077 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
1078 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
1079 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
1080 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
1081 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
1082 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
1083 // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
1084 // CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
1085 // CHECK1-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
1086 // CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
1087 // CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
1088 // CHECK1-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
1089 // CHECK1-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
1090 // CHECK1-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
1091 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
1092 // CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
1093 // CHECK1-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
1094 // CHECK1-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
1095 // CHECK1-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
1096 // CHECK1-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
1097 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
1098 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
1099 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
1100 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
1101 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
1102 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 0
1103 // CHECK1-NEXT: store i32 1, i32* [[TMP25]], align 4, !noalias !24
1104 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 1
1105 // CHECK1-NEXT: store i32 3, i32* [[TMP26]], align 4, !noalias !24
1106 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 2
1107 // CHECK1-NEXT: store i8** [[TMP20]], i8*** [[TMP27]], align 8, !noalias !24
1108 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 3
1109 // CHECK1-NEXT: store i8** [[TMP21]], i8*** [[TMP28]], align 8, !noalias !24
1110 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 4
1111 // CHECK1-NEXT: store i64* [[TMP22]], i64** [[TMP29]], align 8, !noalias !24
1112 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 5
1113 // CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP30]], align 8, !noalias !24
1114 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 6
1115 // CHECK1-NEXT: store i8** null, i8*** [[TMP31]], align 8, !noalias !24
1116 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 7
1117 // CHECK1-NEXT: store i8** null, i8*** [[TMP32]], align 8, !noalias !24
1118 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 8
1119 // CHECK1-NEXT: store i64 0, i64* [[TMP33]], align 8, !noalias !24
1120 // CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel_nowait(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i8* null, i32 0, i8* null)
1121 // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
1122 // CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
1123 // CHECK1: omp_offload.failed.i:
1124 // CHECK1-NEXT: [[TMP36:%.*]] = load i16, i16* [[TMP16]], align 2
1125 // CHECK1-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
1126 // CHECK1-NEXT: store i16 [[TMP36]], i16* [[CONV_I]], align 2, !noalias !24
1127 // CHECK1-NEXT: [[TMP37:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24
1128 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, i32* [[TMP23]], align 4
1129 // CHECK1-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32*
1130 // CHECK1-NEXT: store i32 [[TMP38]], i32* [[CONV4_I]], align 4, !noalias !24
1131 // CHECK1-NEXT: [[TMP39:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !24
1132 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, i32* [[TMP24]], align 4
1133 // CHECK1-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32*
1134 // CHECK1-NEXT: store i32 [[TMP40]], i32* [[CONV5_I]], align 4, !noalias !24
1135 // CHECK1-NEXT: [[TMP41:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !24
1136 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP37]], i64 [[TMP39]], i64 [[TMP41]]) #[[ATTR4]]
1137 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
1138 // CHECK1: .omp_outlined..3.exit:
1139 // CHECK1-NEXT: ret i32 0
1140 //
1141 //
1142 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
1143 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
1144 // CHECK1-NEXT: entry:
1145 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1146 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
1147 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1148 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
1149 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1150 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
1151 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1152 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1153 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
1154 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1155 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
1156 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1157 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
1158 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1159 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
1160 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1161 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
1162 // CHECK1-NEXT: ret void
1163 //
1164 //
1165 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
1166 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
1167 // CHECK1-NEXT: entry:
1168 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1169 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1170 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1171 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
1172 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1173 // CHECK1-NEXT: [[TMP:%.*]] = alloca i16, align 2
1174 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1175 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1176 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1177 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1178 // CHECK1-NEXT: [[IT:%.*]] = alloca i16, align 2
1179 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1180 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1181 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1182 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
1183 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1184 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1185 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1186 // CHECK1-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
1187 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1188 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1189 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1190 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1191 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1192 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1193 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
1194 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1195 // CHECK1: cond.true:
1196 // CHECK1-NEXT: br label [[COND_END:%.*]]
1197 // CHECK1: cond.false:
1198 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1199 // CHECK1-NEXT: br label [[COND_END]]
1200 // CHECK1: cond.end:
1201 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1202 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1203 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1204 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1205 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1206 // CHECK1: omp.inner.for.cond:
1207 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1208 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1209 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1210 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1211 // CHECK1: omp.inner.for.body:
1212 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1213 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
1214 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
1215 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
1216 // CHECK1-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
1217 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
1218 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
1219 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
1220 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
1221 // CHECK1-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
1222 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
1223 // CHECK1-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
1224 // CHECK1-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
1225 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1226 // CHECK1: omp.body.continue:
1227 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1228 // CHECK1: omp.inner.for.inc:
1229 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1230 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
1231 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
1232 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
1233 // CHECK1: omp.inner.for.end:
1234 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1235 // CHECK1: omp.loop.exit:
1236 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
1237 // CHECK1-NEXT: ret void
1238 //
1239 //
1240 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
1241 // CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
1242 // CHECK1-NEXT: entry:
1243 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1244 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
1245 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1246 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
1247 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
1248 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
1249 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
1250 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
1251 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
1252 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1253 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1254 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
1255 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1256 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
1257 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1258 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
1259 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
1260 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1261 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
1262 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
1263 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
1264 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
1265 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1266 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
1267 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1268 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
1269 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
1270 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1271 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
1272 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
1273 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
1274 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
1275 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
1276 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1277 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
1278 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
1279 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
1280 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
1281 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
1282 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
1283 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
1284 // CHECK1-NEXT: ret void
1285 //
1286 //
1287 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
1288 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
1289 // CHECK1-NEXT: entry:
1290 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1291 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1292 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1293 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
1294 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1295 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
1296 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
1297 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
1298 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
1299 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
1300 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
1301 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1302 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1303 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1
1304 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1305 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1306 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1307 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1308 // CHECK1-NEXT: [[IT:%.*]] = alloca i8, align 1
1309 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1310 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1311 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1312 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
1313 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1314 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
1315 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
1316 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1317 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
1318 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
1319 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
1320 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
1321 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1322 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
1323 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1324 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
1325 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
1326 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1327 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
1328 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
1329 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
1330 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
1331 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1332 // CHECK1-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
1333 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1334 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1335 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
1336 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1337 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
1338 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
1339 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
1340 // CHECK1: omp.dispatch.cond:
1341 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1342 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
1343 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1344 // CHECK1: cond.true:
1345 // CHECK1-NEXT: br label [[COND_END:%.*]]
1346 // CHECK1: cond.false:
1347 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1348 // CHECK1-NEXT: br label [[COND_END]]
1349 // CHECK1: cond.end:
1350 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
1351 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1352 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1353 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
1354 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1355 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1356 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
1357 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1358 // CHECK1: omp.dispatch.body:
1359 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1360 // CHECK1: omp.inner.for.cond:
1361 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1362 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1363 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
1364 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1365 // CHECK1: omp.inner.for.body:
1366 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1367 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
1368 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
1369 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
1370 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
1371 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
1372 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
1373 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
1374 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
1375 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
1376 // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
1377 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
1378 // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
1379 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
1380 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
1381 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
1382 // CHECK1-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
1383 // CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
1384 // CHECK1-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
1385 // CHECK1-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4
1386 // CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
1387 // CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
1388 // CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
1389 // CHECK1-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
1390 // CHECK1-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8
1391 // CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
1392 // CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
1393 // CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
1394 // CHECK1-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
1395 // CHECK1-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
1396 // CHECK1-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8
1397 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
1398 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8
1399 // CHECK1-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
1400 // CHECK1-NEXT: store i64 [[ADD22]], i64* [[X]], align 8
1401 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
1402 // CHECK1-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
1403 // CHECK1-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
1404 // CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
1405 // CHECK1-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
1406 // CHECK1-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8
1407 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1408 // CHECK1: omp.body.continue:
1409 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1410 // CHECK1: omp.inner.for.inc:
1411 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1412 // CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
1413 // CHECK1-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
1414 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
1415 // CHECK1: omp.inner.for.end:
1416 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
1417 // CHECK1: omp.dispatch.inc:
1418 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1419 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1420 // CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
1421 // CHECK1-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
1422 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1423 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1424 // CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
1425 // CHECK1-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
1426 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
1427 // CHECK1: omp.dispatch.end:
1428 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
1429 // CHECK1-NEXT: ret void
1430 //
1431 //
1432 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari
1433 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
1434 // CHECK1-NEXT: entry:
1435 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1436 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
1437 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
1438 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
1439 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4
1440 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1441 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
1442 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
1443 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
1444 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4
1445 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
1446 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
1447 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
1448 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
1449 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
1450 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1451 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
1452 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
1453 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
1454 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
1455 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
1456 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
1457 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
1458 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
1459 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
1460 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
1461 // CHECK1-NEXT: ret i32 [[TMP8]]
1462 //
1463 //
1464 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
1465 // CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
1466 // CHECK1-NEXT: entry:
1467 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1468 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1469 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
1470 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
1471 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1472 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
1473 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
1474 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
1475 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
1476 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
1477 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1478 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
1479 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1480 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1481 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1482 // CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4
1483 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
1484 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
1485 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
1486 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
1487 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
1488 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
1489 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
1490 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
1491 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
1492 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4
1493 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
1494 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
1495 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
1496 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1497 // CHECK1: omp_if.then:
1498 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
1499 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
1500 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
1501 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
1502 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false)
1503 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1504 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1**
1505 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8
1506 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1507 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double**
1508 // CHECK1-NEXT: store double* [[A]], double** [[TMP14]], align 8
1509 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1510 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8
1511 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1512 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
1513 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8
1514 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1515 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
1516 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8
1517 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1518 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8
1519 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1520 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
1521 // CHECK1-NEXT: store i64 2, i64* [[TMP22]], align 8
1522 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1523 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
1524 // CHECK1-NEXT: store i64 2, i64* [[TMP24]], align 8
1525 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1526 // CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8
1527 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1528 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
1529 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8
1530 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1531 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
1532 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8
1533 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1534 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8
1535 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1536 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16**
1537 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8
1538 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1539 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16**
1540 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8
1541 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1542 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8
1543 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1544 // CHECK1-NEXT: store i8* null, i8** [[TMP36]], align 8
1545 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1546 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1547 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1548 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1549 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1550 // CHECK1-NEXT: store i32 1, i32* [[TMP40]], align 4
1551 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1552 // CHECK1-NEXT: store i32 5, i32* [[TMP41]], align 4
1553 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1554 // CHECK1-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 8
1555 // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1556 // CHECK1-NEXT: store i8** [[TMP38]], i8*** [[TMP43]], align 8
1557 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1558 // CHECK1-NEXT: store i64* [[TMP39]], i64** [[TMP44]], align 8
1559 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1560 // CHECK1-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i64** [[TMP45]], align 8
1561 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1562 // CHECK1-NEXT: store i8** null, i8*** [[TMP46]], align 8
1563 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1564 // CHECK1-NEXT: store i8** null, i8*** [[TMP47]], align 8
1565 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1566 // CHECK1-NEXT: store i64 0, i64* [[TMP48]], align 8
1567 // CHECK1-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1568 // CHECK1-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
1569 // CHECK1-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1570 // CHECK1: omp_offload.failed:
1571 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
1572 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
1573 // CHECK1: omp_offload.cont:
1574 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
1575 // CHECK1: omp_if.else:
1576 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
1577 // CHECK1-NEXT: br label [[OMP_IF_END]]
1578 // CHECK1: omp_if.end:
1579 // CHECK1-NEXT: [[TMP51:%.*]] = mul nsw i64 1, [[TMP2]]
1580 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP51]]
1581 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
1582 // CHECK1-NEXT: [[TMP52:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
1583 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP52]] to i32
1584 // CHECK1-NEXT: [[TMP53:%.*]] = load i32, i32* [[B]], align 4
1585 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP53]]
1586 // CHECK1-NEXT: [[TMP54:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
1587 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP54]])
1588 // CHECK1-NEXT: ret i32 [[ADD4]]
1589 //
1590 //
1591 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
1592 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
1593 // CHECK1-NEXT: entry:
1594 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1595 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
1596 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
1597 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1
1598 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
1599 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1600 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
1601 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
1602 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
1603 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
1604 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
1605 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
1606 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4
1607 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2
1608 // CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1
1609 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
1610 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1611 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
1612 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1613 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
1614 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1615 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
1616 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1617 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
1618 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
1619 // CHECK1-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1
1620 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
1621 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
1622 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
1623 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1624 // CHECK1: omp_if.then:
1625 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1626 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
1627 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
1628 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1629 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
1630 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8
1631 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1632 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8
1633 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1634 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1635 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
1636 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1637 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
1638 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8
1639 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1640 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8
1641 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1642 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
1643 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8
1644 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1645 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
1646 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8
1647 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1648 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8
1649 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1650 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
1651 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
1652 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1653 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
1654 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
1655 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1656 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8
1657 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1658 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1659 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1660 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1661 // CHECK1-NEXT: store i32 1, i32* [[TMP29]], align 4
1662 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1663 // CHECK1-NEXT: store i32 4, i32* [[TMP30]], align 4
1664 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1665 // CHECK1-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 8
1666 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1667 // CHECK1-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 8
1668 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1669 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64** [[TMP33]], align 8
1670 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1671 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i64** [[TMP34]], align 8
1672 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1673 // CHECK1-NEXT: store i8** null, i8*** [[TMP35]], align 8
1674 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1675 // CHECK1-NEXT: store i8** null, i8*** [[TMP36]], align 8
1676 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1677 // CHECK1-NEXT: store i64 0, i64* [[TMP37]], align 8
1678 // CHECK1-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1679 // CHECK1-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
1680 // CHECK1-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1681 // CHECK1: omp_offload.failed:
1682 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
1683 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
1684 // CHECK1: omp_offload.cont:
1685 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
1686 // CHECK1: omp_if.else:
1687 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
1688 // CHECK1-NEXT: br label [[OMP_IF_END]]
1689 // CHECK1: omp_if.end:
1690 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, i32* [[A]], align 4
1691 // CHECK1-NEXT: ret i32 [[TMP40]]
1692 //
1693 //
1694 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
1695 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
1696 // CHECK1-NEXT: entry:
1697 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1698 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
1699 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
1700 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
1701 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1702 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
1703 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
1704 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
1705 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
1706 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
1707 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4
1708 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2
1709 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
1710 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1711 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
1712 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1713 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
1714 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1715 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
1716 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1717 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1718 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
1719 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1720 // CHECK1: omp_if.then:
1721 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1722 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
1723 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8
1724 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1725 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
1726 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
1727 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1728 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8
1729 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1730 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
1731 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
1732 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1733 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1734 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
1735 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1736 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8
1737 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1738 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
1739 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
1740 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1741 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
1742 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
1743 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1744 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8
1745 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1746 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1747 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1748 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1749 // CHECK1-NEXT: store i32 1, i32* [[TMP22]], align 4
1750 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1751 // CHECK1-NEXT: store i32 3, i32* [[TMP23]], align 4
1752 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1753 // CHECK1-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 8
1754 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1755 // CHECK1-NEXT: store i8** [[TMP21]], i8*** [[TMP25]], align 8
1756 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1757 // CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64** [[TMP26]], align 8
1758 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1759 // CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i64** [[TMP27]], align 8
1760 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1761 // CHECK1-NEXT: store i8** null, i8*** [[TMP28]], align 8
1762 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1763 // CHECK1-NEXT: store i8** null, i8*** [[TMP29]], align 8
1764 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1765 // CHECK1-NEXT: store i64 0, i64* [[TMP30]], align 8
1766 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1767 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
1768 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1769 // CHECK1: omp_offload.failed:
1770 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
1771 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
1772 // CHECK1: omp_offload.cont:
1773 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
1774 // CHECK1: omp_if.else:
1775 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
1776 // CHECK1-NEXT: br label [[OMP_IF_END]]
1777 // CHECK1: omp_if.end:
1778 // CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[A]], align 4
1779 // CHECK1-NEXT: ret i32 [[TMP33]]
1780 //
1781 //
1782 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
1783 // CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1784 // CHECK1-NEXT: entry:
1785 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1786 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
1787 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1788 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
1789 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
1790 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
1791 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1792 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
1793 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1794 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1795 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
1796 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1797 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1798 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1799 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1800 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
1801 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
1802 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
1803 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
1804 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
1805 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
1806 // CHECK1-NEXT: ret void
1807 //
1808 //
1809 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10
1810 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
1811 // CHECK1-NEXT: entry:
1812 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1813 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1814 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1815 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
1816 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1817 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
1818 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
1819 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
1820 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8
1821 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
1822 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
1823 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1824 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1825 // CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8
1826 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1827 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1828 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1829 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
1830 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1831 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1832 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
1833 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1834 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1835 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1836 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1837 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
1838 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
1839 // CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
1840 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
1841 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1842 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1843 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
1844 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
1845 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1846 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
1847 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1848 // CHECK1: cond.true:
1849 // CHECK1-NEXT: br label [[COND_END:%.*]]
1850 // CHECK1: cond.false:
1851 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1852 // CHECK1-NEXT: br label [[COND_END]]
1853 // CHECK1: cond.end:
1854 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1855 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
1856 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
1857 // CHECK1-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
1858 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1859 // CHECK1: omp.inner.for.cond:
1860 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1861 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1862 // CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
1863 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1864 // CHECK1: omp.inner.for.body:
1865 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1866 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
1867 // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
1868 // CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
1869 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
1870 // CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
1871 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
1872 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
1873 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8
1874 // CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
1875 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
1876 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
1877 // CHECK1-NEXT: store double [[INC]], double* [[A5]], align 8
1878 // CHECK1-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
1879 // CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
1880 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
1881 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
1882 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
1883 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1884 // CHECK1: omp.body.continue:
1885 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1886 // CHECK1: omp.inner.for.inc:
1887 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1888 // CHECK1-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1
1889 // CHECK1-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
1890 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
1891 // CHECK1: omp.inner.for.end:
1892 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1893 // CHECK1: omp.loop.exit:
1894 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
1895 // CHECK1-NEXT: ret void
1896 //
1897 //
1898 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
1899 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1900 // CHECK1-NEXT: entry:
1901 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1902 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
1903 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
1904 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1905 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1906 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
1907 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
1908 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1909 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
1910 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
1911 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1912 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1913 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1914 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
1915 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1916 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
1917 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1918 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
1919 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
1920 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
1921 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1922 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
1923 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1924 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
1925 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
1926 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
1927 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
1928 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
1929 // CHECK1-NEXT: ret void
1930 //
1931 //
1932 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13
1933 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
1934 // CHECK1-NEXT: entry:
1935 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1936 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1937 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1938 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
1939 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
1940 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1941 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1942 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1943 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1944 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1945 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1946 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
1947 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
1948 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1949 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1950 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1951 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
1952 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1953 // CHECK1-NEXT: ret void
1954 //
1955 //
1956 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
1957 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1958 // CHECK1-NEXT: entry:
1959 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1960 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
1961 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1962 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1963 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
1964 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1965 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
1966 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1967 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1968 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1969 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1970 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
1971 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1972 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
1973 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
1974 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
1975 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1976 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
1977 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1978 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
1979 // CHECK1-NEXT: ret void
1980 //
1981 //
1982 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16
1983 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
1984 // CHECK1-NEXT: entry:
1985 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1986 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1987 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1988 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
1989 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1990 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
1991 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8
1992 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
1993 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
1994 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1995 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1996 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8
1997 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1998 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1999 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
2000 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
2001 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
2002 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2003 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2004 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
2005 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
2006 // CHECK1-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
2007 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
2008 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2009 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2010 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
2011 // CHECK1-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
2012 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
2013 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
2014 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2015 // CHECK1: cond.true:
2016 // CHECK1-NEXT: br label [[COND_END:%.*]]
2017 // CHECK1: cond.false:
2018 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
2019 // CHECK1-NEXT: br label [[COND_END]]
2020 // CHECK1: cond.end:
2021 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
2022 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
2023 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
2024 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
2025 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2026 // CHECK1: omp.inner.for.cond:
2027 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2028 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
2029 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
2030 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2031 // CHECK1: omp.inner.for.body:
2032 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2033 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
2034 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
2035 // CHECK1-NEXT: store i64 [[ADD]], i64* [[I]], align 8
2036 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
2037 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
2038 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
2039 // CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
2040 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
2041 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
2042 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
2043 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
2044 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
2045 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
2046 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
2047 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
2048 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2049 // CHECK1: omp.body.continue:
2050 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2051 // CHECK1: omp.inner.for.inc:
2052 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2053 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
2054 // CHECK1-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
2055 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
2056 // CHECK1: omp.inner.for.end:
2057 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2058 // CHECK1: omp.loop.exit:
2059 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
2060 // CHECK1-NEXT: ret void
2061 //
2062 //
2063 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2064 // CHECK1-SAME: () #[[ATTR6]] {
2065 // CHECK1-NEXT: entry:
2066 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
2067 // CHECK1-NEXT: ret void
2068 //
2069 //
2070 // CHECK3-LABEL: define {{[^@]+}}@_Z7get_valv
2071 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
2072 // CHECK3-NEXT: entry:
2073 // CHECK3-NEXT: ret i64 0
2074 //
2075 //
2076 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi
2077 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
2078 // CHECK3-NEXT: entry:
2079 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
2080 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
2081 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
2082 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4
2083 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
2084 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
2085 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
2086 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
2087 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
2088 // CHECK3-NEXT: [[K:%.*]] = alloca i64, align 8
2089 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
2090 // CHECK3-NEXT: [[LIN:%.*]] = alloca i32, align 4
2091 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
2092 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
2093 // CHECK3-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4
2094 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
2095 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
2096 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
2097 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
2098 // CHECK3-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4
2099 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4
2100 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4
2101 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4
2102 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4
2103 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2104 // CHECK3-NEXT: [[A_CASTED12:%.*]] = alloca i32, align 4
2105 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
2106 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS15:%.*]] = alloca [10 x i8*], align 4
2107 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS16:%.*]] = alloca [10 x i8*], align 4
2108 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS17:%.*]] = alloca [10 x i8*], align 4
2109 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
2110 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
2111 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
2112 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4
2113 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2
2114 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
2115 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
2116 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
2117 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
2118 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
2119 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
2120 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
2121 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
2122 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
2123 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2124 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
2125 // CHECK3-NEXT: store i32 1, i32* [[TMP5]], align 4
2126 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
2127 // CHECK3-NEXT: store i32 0, i32* [[TMP6]], align 4
2128 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
2129 // CHECK3-NEXT: store i8** null, i8*** [[TMP7]], align 4
2130 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
2131 // CHECK3-NEXT: store i8** null, i8*** [[TMP8]], align 4
2132 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
2133 // CHECK3-NEXT: store i64* null, i64** [[TMP9]], align 4
2134 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
2135 // CHECK3-NEXT: store i64* null, i64** [[TMP10]], align 4
2136 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
2137 // CHECK3-NEXT: store i8** null, i8*** [[TMP11]], align 4
2138 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
2139 // CHECK3-NEXT: store i8** null, i8*** [[TMP12]], align 4
2140 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
2141 // CHECK3-NEXT: store i64 0, i64* [[TMP13]], align 8
2142 // CHECK3-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
2143 // CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
2144 // CHECK3-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2145 // CHECK3: omp_offload.failed:
2146 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]]
2147 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
2148 // CHECK3: omp_offload.cont:
2149 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
2150 // CHECK3-NEXT: store i64 [[CALL]], i64* [[K]], align 8
2151 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4
2152 // CHECK3-NEXT: store i32 [[TMP16]], i32* [[A_CASTED]], align 4
2153 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[A_CASTED]], align 4
2154 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP17]], i64* [[K]]) #[[ATTR4]]
2155 // CHECK3-NEXT: store i32 12, i32* [[LIN]], align 4
2156 // CHECK3-NEXT: [[TMP18:%.*]] = load i16, i16* [[AA]], align 2
2157 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
2158 // CHECK3-NEXT: store i16 [[TMP18]], i16* [[CONV]], align 2
2159 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[AA_CASTED]], align 4
2160 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4
2161 // CHECK3-NEXT: store i32 [[TMP20]], i32* [[LIN_CASTED]], align 4
2162 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
2163 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4
2164 // CHECK3-NEXT: store i32 [[TMP22]], i32* [[A_CASTED2]], align 4
2165 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4
2166 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2167 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
2168 // CHECK3-NEXT: store i32 [[TMP19]], i32* [[TMP25]], align 4
2169 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2170 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
2171 // CHECK3-NEXT: store i32 [[TMP19]], i32* [[TMP27]], align 4
2172 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2173 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4
2174 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2175 // CHECK3-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
2176 // CHECK3-NEXT: store i32 [[TMP21]], i32* [[TMP30]], align 4
2177 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2178 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
2179 // CHECK3-NEXT: store i32 [[TMP21]], i32* [[TMP32]], align 4
2180 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2181 // CHECK3-NEXT: store i8* null, i8** [[TMP33]], align 4
2182 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2183 // CHECK3-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32*
2184 // CHECK3-NEXT: store i32 [[TMP23]], i32* [[TMP35]], align 4
2185 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2186 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32*
2187 // CHECK3-NEXT: store i32 [[TMP23]], i32* [[TMP37]], align 4
2188 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2189 // CHECK3-NEXT: store i8* null, i8** [[TMP38]], align 4
2190 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2191 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2192 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
2193 // CHECK3-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2
2194 // CHECK3-NEXT: store i16 [[TMP42]], i16* [[TMP41]], align 4
2195 // CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
2196 // CHECK3-NEXT: [[TMP44:%.*]] = load i32, i32* [[LIN]], align 4
2197 // CHECK3-NEXT: store i32 [[TMP44]], i32* [[TMP43]], align 4
2198 // CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
2199 // CHECK3-NEXT: [[TMP46:%.*]] = load i32, i32* [[A]], align 4
2200 // CHECK3-NEXT: store i32 [[TMP46]], i32* [[TMP45]], align 4
2201 // CHECK3-NEXT: [[TMP47:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
2202 // CHECK3-NEXT: [[TMP48:%.*]] = bitcast i8* [[TMP47]] to %struct.kmp_task_t_with_privates*
2203 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP48]], i32 0, i32 0
2204 // CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP49]], i32 0, i32 0
2205 // CHECK3-NEXT: [[TMP51:%.*]] = load i8*, i8** [[TMP50]], align 4
2206 // CHECK3-NEXT: [[TMP52:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
2207 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP51]], i8* align 4 [[TMP52]], i32 12, i1 false)
2208 // CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP48]], i32 0, i32 1
2209 // CHECK3-NEXT: [[TMP54:%.*]] = bitcast i8* [[TMP51]] to %struct.anon*
2210 // CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP53]], i32 0, i32 0
2211 // CHECK3-NEXT: [[TMP56:%.*]] = bitcast [3 x i64]* [[TMP55]] to i8*
2212 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP56]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
2213 // CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP53]], i32 0, i32 1
2214 // CHECK3-NEXT: [[TMP58:%.*]] = bitcast [3 x i8*]* [[TMP57]] to i8*
2215 // CHECK3-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP39]] to i8*
2216 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP58]], i8* align 4 [[TMP59]], i32 12, i1 false)
2217 // CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP53]], i32 0, i32 2
2218 // CHECK3-NEXT: [[TMP61:%.*]] = bitcast [3 x i8*]* [[TMP60]] to i8*
2219 // CHECK3-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP40]] to i8*
2220 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP61]], i8* align 4 [[TMP62]], i32 12, i1 false)
2221 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP53]], i32 0, i32 3
2222 // CHECK3-NEXT: [[TMP64:%.*]] = load i16, i16* [[AA]], align 2
2223 // CHECK3-NEXT: store i16 [[TMP64]], i16* [[TMP63]], align 4
2224 // CHECK3-NEXT: [[TMP65:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP47]])
2225 // CHECK3-NEXT: [[TMP66:%.*]] = load i32, i32* [[A]], align 4
2226 // CHECK3-NEXT: store i32 [[TMP66]], i32* [[A_CASTED3]], align 4
2227 // CHECK3-NEXT: [[TMP67:%.*]] = load i32, i32* [[A_CASTED3]], align 4
2228 // CHECK3-NEXT: [[TMP68:%.*]] = load i16, i16* [[AA]], align 2
2229 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
2230 // CHECK3-NEXT: store i16 [[TMP68]], i16* [[CONV5]], align 2
2231 // CHECK3-NEXT: [[TMP69:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
2232 // CHECK3-NEXT: [[TMP70:%.*]] = load i32, i32* [[N_ADDR]], align 4
2233 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP70]], 10
2234 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2235 // CHECK3: omp_if.then:
2236 // CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
2237 // CHECK3-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i32*
2238 // CHECK3-NEXT: store i32 [[TMP67]], i32* [[TMP72]], align 4
2239 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
2240 // CHECK3-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32*
2241 // CHECK3-NEXT: store i32 [[TMP67]], i32* [[TMP74]], align 4
2242 // CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
2243 // CHECK3-NEXT: store i8* null, i8** [[TMP75]], align 4
2244 // CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1
2245 // CHECK3-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32*
2246 // CHECK3-NEXT: store i32 [[TMP69]], i32* [[TMP77]], align 4
2247 // CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1
2248 // CHECK3-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
2249 // CHECK3-NEXT: store i32 [[TMP69]], i32* [[TMP79]], align 4
2250 // CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1
2251 // CHECK3-NEXT: store i8* null, i8** [[TMP80]], align 4
2252 // CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
2253 // CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
2254 // CHECK3-NEXT: [[KERNEL_ARGS9:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
2255 // CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 0
2256 // CHECK3-NEXT: store i32 1, i32* [[TMP83]], align 4
2257 // CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 1
2258 // CHECK3-NEXT: store i32 2, i32* [[TMP84]], align 4
2259 // CHECK3-NEXT: [[TMP85:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 2
2260 // CHECK3-NEXT: store i8** [[TMP81]], i8*** [[TMP85]], align 4
2261 // CHECK3-NEXT: [[TMP86:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 3
2262 // CHECK3-NEXT: store i8** [[TMP82]], i8*** [[TMP86]], align 4
2263 // CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 4
2264 // CHECK3-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64** [[TMP87]], align 4
2265 // CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 5
2266 // CHECK3-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP88]], align 4
2267 // CHECK3-NEXT: [[TMP89:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 6
2268 // CHECK3-NEXT: store i8** null, i8*** [[TMP89]], align 4
2269 // CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 7
2270 // CHECK3-NEXT: store i8** null, i8*** [[TMP90]], align 4
2271 // CHECK3-NEXT: [[TMP91:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 8
2272 // CHECK3-NEXT: store i64 0, i64* [[TMP91]], align 8
2273 // CHECK3-NEXT: [[TMP92:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]])
2274 // CHECK3-NEXT: [[TMP93:%.*]] = icmp ne i32 [[TMP92]], 0
2275 // CHECK3-NEXT: br i1 [[TMP93]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]]
2276 // CHECK3: omp_offload.failed10:
2277 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP67]], i32 [[TMP69]]) #[[ATTR4]]
2278 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT11]]
2279 // CHECK3: omp_offload.cont11:
2280 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
2281 // CHECK3: omp_if.else:
2282 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP67]], i32 [[TMP69]]) #[[ATTR4]]
2283 // CHECK3-NEXT: br label [[OMP_IF_END]]
2284 // CHECK3: omp_if.end:
2285 // CHECK3-NEXT: [[TMP94:%.*]] = load i32, i32* [[A]], align 4
2286 // CHECK3-NEXT: store i32 [[TMP94]], i32* [[DOTCAPTURE_EXPR_]], align 4
2287 // CHECK3-NEXT: [[TMP95:%.*]] = load i32, i32* [[A]], align 4
2288 // CHECK3-NEXT: store i32 [[TMP95]], i32* [[A_CASTED12]], align 4
2289 // CHECK3-NEXT: [[TMP96:%.*]] = load i32, i32* [[A_CASTED12]], align 4
2290 // CHECK3-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2291 // CHECK3-NEXT: store i32 [[TMP97]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
2292 // CHECK3-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
2293 // CHECK3-NEXT: [[TMP99:%.*]] = load i32, i32* [[N_ADDR]], align 4
2294 // CHECK3-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[TMP99]], 20
2295 // CHECK3-NEXT: br i1 [[CMP13]], label [[OMP_IF_THEN14:%.*]], label [[OMP_IF_ELSE21:%.*]]
2296 // CHECK3: omp_if.then14:
2297 // CHECK3-NEXT: [[TMP100:%.*]] = mul nuw i32 [[TMP1]], 4
2298 // CHECK3-NEXT: [[TMP101:%.*]] = sext i32 [[TMP100]] to i64
2299 // CHECK3-NEXT: [[TMP102:%.*]] = mul nuw i32 5, [[TMP3]]
2300 // CHECK3-NEXT: [[TMP103:%.*]] = mul nuw i32 [[TMP102]], 8
2301 // CHECK3-NEXT: [[TMP104:%.*]] = sext i32 [[TMP103]] to i64
2302 // CHECK3-NEXT: [[TMP105:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
2303 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP105]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i32 80, i1 false)
2304 // CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 0
2305 // CHECK3-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i32*
2306 // CHECK3-NEXT: store i32 [[TMP96]], i32* [[TMP107]], align 4
2307 // CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 0
2308 // CHECK3-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32*
2309 // CHECK3-NEXT: store i32 [[TMP96]], i32* [[TMP109]], align 4
2310 // CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 0
2311 // CHECK3-NEXT: store i8* null, i8** [[TMP110]], align 4
2312 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 1
2313 // CHECK3-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [10 x float]**
2314 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP112]], align 4
2315 // CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 1
2316 // CHECK3-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [10 x float]**
2317 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP114]], align 4
2318 // CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 1
2319 // CHECK3-NEXT: store i8* null, i8** [[TMP115]], align 4
2320 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 2
2321 // CHECK3-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32*
2322 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP117]], align 4
2323 // CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 2
2324 // CHECK3-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i32*
2325 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP119]], align 4
2326 // CHECK3-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 2
2327 // CHECK3-NEXT: store i8* null, i8** [[TMP120]], align 4
2328 // CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 3
2329 // CHECK3-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to float**
2330 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP122]], align 4
2331 // CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 3
2332 // CHECK3-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to float**
2333 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP124]], align 4
2334 // CHECK3-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
2335 // CHECK3-NEXT: store i64 [[TMP101]], i64* [[TMP125]], align 4
2336 // CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 3
2337 // CHECK3-NEXT: store i8* null, i8** [[TMP126]], align 4
2338 // CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 4
2339 // CHECK3-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to [5 x [10 x double]]**
2340 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP128]], align 4
2341 // CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 4
2342 // CHECK3-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to [5 x [10 x double]]**
2343 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP130]], align 4
2344 // CHECK3-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 4
2345 // CHECK3-NEXT: store i8* null, i8** [[TMP131]], align 4
2346 // CHECK3-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 5
2347 // CHECK3-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to i32*
2348 // CHECK3-NEXT: store i32 5, i32* [[TMP133]], align 4
2349 // CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 5
2350 // CHECK3-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i32*
2351 // CHECK3-NEXT: store i32 5, i32* [[TMP135]], align 4
2352 // CHECK3-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 5
2353 // CHECK3-NEXT: store i8* null, i8** [[TMP136]], align 4
2354 // CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 6
2355 // CHECK3-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i32*
2356 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP138]], align 4
2357 // CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 6
2358 // CHECK3-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to i32*
2359 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP140]], align 4
2360 // CHECK3-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 6
2361 // CHECK3-NEXT: store i8* null, i8** [[TMP141]], align 4
2362 // CHECK3-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 7
2363 // CHECK3-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to double**
2364 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP143]], align 4
2365 // CHECK3-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 7
2366 // CHECK3-NEXT: [[TMP145:%.*]] = bitcast i8** [[TMP144]] to double**
2367 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP145]], align 4
2368 // CHECK3-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
2369 // CHECK3-NEXT: store i64 [[TMP104]], i64* [[TMP146]], align 4
2370 // CHECK3-NEXT: [[TMP147:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 7
2371 // CHECK3-NEXT: store i8* null, i8** [[TMP147]], align 4
2372 // CHECK3-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 8
2373 // CHECK3-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to %struct.TT**
2374 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP149]], align 4
2375 // CHECK3-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 8
2376 // CHECK3-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to %struct.TT**
2377 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP151]], align 4
2378 // CHECK3-NEXT: [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 8
2379 // CHECK3-NEXT: store i8* null, i8** [[TMP152]], align 4
2380 // CHECK3-NEXT: [[TMP153:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 9
2381 // CHECK3-NEXT: [[TMP154:%.*]] = bitcast i8** [[TMP153]] to i32*
2382 // CHECK3-NEXT: store i32 [[TMP98]], i32* [[TMP154]], align 4
2383 // CHECK3-NEXT: [[TMP155:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 9
2384 // CHECK3-NEXT: [[TMP156:%.*]] = bitcast i8** [[TMP155]] to i32*
2385 // CHECK3-NEXT: store i32 [[TMP98]], i32* [[TMP156]], align 4
2386 // CHECK3-NEXT: [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 9
2387 // CHECK3-NEXT: store i8* null, i8** [[TMP157]], align 4
2388 // CHECK3-NEXT: [[TMP158:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 0
2389 // CHECK3-NEXT: [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 0
2390 // CHECK3-NEXT: [[TMP160:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2391 // CHECK3-NEXT: [[KERNEL_ARGS18:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
2392 // CHECK3-NEXT: [[TMP161:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 0
2393 // CHECK3-NEXT: store i32 1, i32* [[TMP161]], align 4
2394 // CHECK3-NEXT: [[TMP162:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 1
2395 // CHECK3-NEXT: store i32 10, i32* [[TMP162]], align 4
2396 // CHECK3-NEXT: [[TMP163:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 2
2397 // CHECK3-NEXT: store i8** [[TMP158]], i8*** [[TMP163]], align 4
2398 // CHECK3-NEXT: [[TMP164:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 3
2399 // CHECK3-NEXT: store i8** [[TMP159]], i8*** [[TMP164]], align 4
2400 // CHECK3-NEXT: [[TMP165:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 4
2401 // CHECK3-NEXT: store i64* [[TMP160]], i64** [[TMP165]], align 4
2402 // CHECK3-NEXT: [[TMP166:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 5
2403 // CHECK3-NEXT: store i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i64** [[TMP166]], align 4
2404 // CHECK3-NEXT: [[TMP167:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 6
2405 // CHECK3-NEXT: store i8** null, i8*** [[TMP167]], align 4
2406 // CHECK3-NEXT: [[TMP168:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 7
2407 // CHECK3-NEXT: store i8** null, i8*** [[TMP168]], align 4
2408 // CHECK3-NEXT: [[TMP169:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 8
2409 // CHECK3-NEXT: store i64 0, i64* [[TMP169]], align 8
2410 // CHECK3-NEXT: [[TMP170:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]])
2411 // CHECK3-NEXT: [[TMP171:%.*]] = icmp ne i32 [[TMP170]], 0
2412 // CHECK3-NEXT: br i1 [[TMP171]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]]
2413 // CHECK3: omp_offload.failed19:
2414 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP96]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP98]]) #[[ATTR4]]
2415 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT20]]
2416 // CHECK3: omp_offload.cont20:
2417 // CHECK3-NEXT: br label [[OMP_IF_END22:%.*]]
2418 // CHECK3: omp_if.else21:
2419 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP96]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP98]]) #[[ATTR4]]
2420 // CHECK3-NEXT: br label [[OMP_IF_END22]]
2421 // CHECK3: omp_if.end22:
2422 // CHECK3-NEXT: [[TMP172:%.*]] = load i32, i32* [[A]], align 4
2423 // CHECK3-NEXT: [[TMP173:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
2424 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP173]])
2425 // CHECK3-NEXT: ret i32 [[TMP172]]
2426 //
2427 //
2428 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
2429 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] {
2430 // CHECK3-NEXT: entry:
2431 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
2432 // CHECK3-NEXT: ret void
2433 //
2434 //
2435 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
2436 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
2437 // CHECK3-NEXT: entry:
2438 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2439 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2440 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2441 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2442 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2443 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2444 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2445 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2446 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2447 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2448 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2449 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2450 // CHECK3-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
2451 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2452 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2453 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2454 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2455 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2456 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2457 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
2458 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2459 // CHECK3: cond.true:
2460 // CHECK3-NEXT: br label [[COND_END:%.*]]
2461 // CHECK3: cond.false:
2462 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2463 // CHECK3-NEXT: br label [[COND_END]]
2464 // CHECK3: cond.end:
2465 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2466 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2467 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2468 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2469 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2470 // CHECK3: omp.inner.for.cond:
2471 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2472 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2473 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2474 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2475 // CHECK3: omp.inner.for.body:
2476 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2477 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
2478 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
2479 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2480 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
2481 // CHECK3-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
2482 // CHECK3-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
2483 // CHECK3: .cancel.exit:
2484 // CHECK3-NEXT: br label [[CANCEL_EXIT:%.*]]
2485 // CHECK3: .cancel.continue:
2486 // CHECK3-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
2487 // CHECK3-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
2488 // CHECK3-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
2489 // CHECK3: .cancel.exit2:
2490 // CHECK3-NEXT: br label [[CANCEL_EXIT]]
2491 // CHECK3: .cancel.continue3:
2492 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2493 // CHECK3: omp.body.continue:
2494 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2495 // CHECK3: omp.inner.for.inc:
2496 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2497 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
2498 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
2499 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
2500 // CHECK3: omp.inner.for.end:
2501 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2502 // CHECK3: omp.loop.exit:
2503 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2504 // CHECK3-NEXT: br label [[CANCEL_CONT:%.*]]
2505 // CHECK3: cancel.cont:
2506 // CHECK3-NEXT: ret void
2507 // CHECK3: cancel.exit:
2508 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2509 // CHECK3-NEXT: br label [[CANCEL_CONT]]
2510 //
2511 //
2512 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
2513 // CHECK3-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
2514 // CHECK3-NEXT: entry:
2515 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2516 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
2517 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
2518 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2519 // CHECK3-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
2520 // CHECK3-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
2521 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
2522 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
2523 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
2524 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]])
2525 // CHECK3-NEXT: ret void
2526 //
2527 //
2528 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
2529 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
2530 // CHECK3-NEXT: entry:
2531 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2532 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2533 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2534 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
2535 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2536 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2537 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
2538 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2539 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2540 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2541 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2542 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2543 // CHECK3-NEXT: [[K1:%.*]] = alloca i64, align 8
2544 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2545 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2546 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2547 // CHECK3-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
2548 // CHECK3-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
2549 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8
2550 // CHECK3-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8
2551 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2552 // CHECK3-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
2553 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2554 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2555 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2556 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2557 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
2558 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1)
2559 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
2560 // CHECK3: omp.dispatch.cond:
2561 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
2562 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
2563 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2564 // CHECK3: omp.dispatch.body:
2565 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2566 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
2567 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2568 // CHECK3: omp.inner.for.cond:
2569 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]
2570 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]]
2571 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
2572 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2573 // CHECK3: omp.inner.for.body:
2574 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
2575 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
2576 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
2577 // CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP13]]
2578 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP13]]
2579 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
2580 // CHECK3-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
2581 // CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
2582 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
2583 // CHECK3-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group [[ACC_GRP13]]
2584 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]
2585 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
2586 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]
2587 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2588 // CHECK3: omp.body.continue:
2589 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2590 // CHECK3: omp.inner.for.inc:
2591 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
2592 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
2593 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
2594 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
2595 // CHECK3: omp.inner.for.end:
2596 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
2597 // CHECK3: omp.dispatch.inc:
2598 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
2599 // CHECK3: omp.dispatch.end:
2600 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2601 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
2602 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
2603 // CHECK3: .omp.linear.pu:
2604 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[K1]], align 8
2605 // CHECK3-NEXT: store i64 [[TMP15]], i64* [[TMP0]], align 8
2606 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
2607 // CHECK3: .omp.linear.pu.done:
2608 // CHECK3-NEXT: ret void
2609 //
2610 //
2611 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
2612 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {
2613 // CHECK3-NEXT: entry:
2614 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
2615 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
2616 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2617 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
2618 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
2619 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
2620 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
2621 // CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
2622 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2623 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
2624 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
2625 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
2626 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
2627 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
2628 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
2629 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
2630 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
2631 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
2632 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
2633 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
2634 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
2635 // CHECK3-NEXT: ret void
2636 //
2637 //
2638 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2
2639 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {
2640 // CHECK3-NEXT: entry:
2641 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2642 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2643 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
2644 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
2645 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2646 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
2647 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4
2648 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
2649 // CHECK3-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
2650 // CHECK3-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
2651 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
2652 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
2653 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
2654 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2655 // CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8
2656 // CHECK3-NEXT: [[LIN2:%.*]] = alloca i32, align 4
2657 // CHECK3-NEXT: [[A3:%.*]] = alloca i32, align 4
2658 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2659 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2660 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
2661 // CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
2662 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2663 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
2664 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
2665 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
2666 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
2667 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
2668 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
2669 // CHECK3-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
2670 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
2671 // CHECK3-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
2672 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
2673 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2674 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2675 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2676 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
2677 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
2678 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
2679 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
2680 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2681 // CHECK3: cond.true:
2682 // CHECK3-NEXT: br label [[COND_END:%.*]]
2683 // CHECK3: cond.false:
2684 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
2685 // CHECK3-NEXT: br label [[COND_END]]
2686 // CHECK3: cond.end:
2687 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2688 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
2689 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
2690 // CHECK3-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
2691 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2692 // CHECK3: omp.inner.for.cond:
2693 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2694 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
2695 // CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
2696 // CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2697 // CHECK3: omp.inner.for.body:
2698 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2699 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
2700 // CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
2701 // CHECK3-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
2702 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
2703 // CHECK3-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
2704 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2705 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
2706 // CHECK3-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
2707 // CHECK3-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
2708 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
2709 // CHECK3-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4
2710 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
2711 // CHECK3-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
2712 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2713 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
2714 // CHECK3-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
2715 // CHECK3-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
2716 // CHECK3-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
2717 // CHECK3-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
2718 // CHECK3-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
2719 // CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
2720 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
2721 // CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
2722 // CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
2723 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2724 // CHECK3: omp.body.continue:
2725 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2726 // CHECK3: omp.inner.for.inc:
2727 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2728 // CHECK3-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
2729 // CHECK3-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
2730 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
2731 // CHECK3: omp.inner.for.end:
2732 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2733 // CHECK3: omp.loop.exit:
2734 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
2735 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2736 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
2737 // CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
2738 // CHECK3: .omp.linear.pu:
2739 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4
2740 // CHECK3-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4
2741 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4
2742 // CHECK3-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4
2743 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
2744 // CHECK3: .omp.linear.pu.done:
2745 // CHECK3-NEXT: ret void
2746 //
2747 //
2748 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.
2749 // CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
2750 // CHECK3-NEXT: entry:
2751 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
2752 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4
2753 // CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
2754 // CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
2755 // CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
2756 // CHECK3-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
2757 // CHECK3-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
2758 // CHECK3-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
2759 // CHECK3-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
2760 // CHECK3-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
2761 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
2762 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
2763 // CHECK3-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
2764 // CHECK3-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
2765 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
2766 // CHECK3-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
2767 // CHECK3-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
2768 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
2769 // CHECK3-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
2770 // CHECK3-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
2771 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
2772 // CHECK3-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
2773 // CHECK3-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4
2774 // CHECK3-NEXT: ret void
2775 //
2776 //
2777 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.
2778 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
2779 // CHECK3-NEXT: entry:
2780 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
2781 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
2782 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
2783 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
2784 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
2785 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
2786 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
2787 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
2788 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
2789 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
2790 // CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4
2791 // CHECK3-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4
2792 // CHECK3-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4
2793 // CHECK3-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2794 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
2795 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
2796 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
2797 // CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
2798 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
2799 // CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
2800 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
2801 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
2802 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
2803 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
2804 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
2805 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
2806 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
2807 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
2808 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
2809 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
2810 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
2811 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
2812 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
2813 // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
2814 // CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
2815 // CHECK3-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
2816 // CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
2817 // CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
2818 // CHECK3-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
2819 // CHECK3-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
2820 // CHECK3-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
2821 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
2822 // CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
2823 // CHECK3-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
2824 // CHECK3-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
2825 // CHECK3-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
2826 // CHECK3-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
2827 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
2828 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
2829 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
2830 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
2831 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
2832 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 0
2833 // CHECK3-NEXT: store i32 1, i32* [[TMP25]], align 4, !noalias !25
2834 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 1
2835 // CHECK3-NEXT: store i32 3, i32* [[TMP26]], align 4, !noalias !25
2836 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 2
2837 // CHECK3-NEXT: store i8** [[TMP20]], i8*** [[TMP27]], align 4, !noalias !25
2838 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 3
2839 // CHECK3-NEXT: store i8** [[TMP21]], i8*** [[TMP28]], align 4, !noalias !25
2840 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 4
2841 // CHECK3-NEXT: store i64* [[TMP22]], i64** [[TMP29]], align 4, !noalias !25
2842 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 5
2843 // CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP30]], align 4, !noalias !25
2844 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 6
2845 // CHECK3-NEXT: store i8** null, i8*** [[TMP31]], align 4, !noalias !25
2846 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 7
2847 // CHECK3-NEXT: store i8** null, i8*** [[TMP32]], align 4, !noalias !25
2848 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 8
2849 // CHECK3-NEXT: store i64 0, i64* [[TMP33]], align 8, !noalias !25
2850 // CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel_nowait(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i8* null, i32 0, i8* null)
2851 // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
2852 // CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
2853 // CHECK3: omp_offload.failed.i:
2854 // CHECK3-NEXT: [[TMP36:%.*]] = load i16, i16* [[TMP16]], align 2
2855 // CHECK3-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
2856 // CHECK3-NEXT: store i16 [[TMP36]], i16* [[CONV_I]], align 2, !noalias !25
2857 // CHECK3-NEXT: [[TMP37:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25
2858 // CHECK3-NEXT: [[TMP38:%.*]] = load i32, i32* [[TMP23]], align 4
2859 // CHECK3-NEXT: store i32 [[TMP38]], i32* [[LIN_CASTED_I]], align 4, !noalias !25
2860 // CHECK3-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !25
2861 // CHECK3-NEXT: [[TMP40:%.*]] = load i32, i32* [[TMP24]], align 4
2862 // CHECK3-NEXT: store i32 [[TMP40]], i32* [[A_CASTED_I]], align 4, !noalias !25
2863 // CHECK3-NEXT: [[TMP41:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !25
2864 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP37]], i32 [[TMP39]], i32 [[TMP41]]) #[[ATTR4]]
2865 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
2866 // CHECK3: .omp_outlined..3.exit:
2867 // CHECK3-NEXT: ret i32 0
2868 //
2869 //
2870 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
2871 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2872 // CHECK3-NEXT: entry:
2873 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2874 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
2875 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
2876 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
2877 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2878 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
2879 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
2880 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2881 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
2882 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
2883 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
2884 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
2885 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
2886 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
2887 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
2888 // CHECK3-NEXT: ret void
2889 //
2890 //
2891 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
2892 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
2893 // CHECK3-NEXT: entry:
2894 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2895 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2896 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2897 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
2898 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2899 // CHECK3-NEXT: [[TMP:%.*]] = alloca i16, align 2
2900 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2901 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2902 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2903 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2904 // CHECK3-NEXT: [[IT:%.*]] = alloca i16, align 2
2905 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2906 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2907 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2908 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
2909 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
2910 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2911 // CHECK3-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
2912 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2913 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2914 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2915 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2916 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2917 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2918 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
2919 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2920 // CHECK3: cond.true:
2921 // CHECK3-NEXT: br label [[COND_END:%.*]]
2922 // CHECK3: cond.false:
2923 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2924 // CHECK3-NEXT: br label [[COND_END]]
2925 // CHECK3: cond.end:
2926 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2927 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2928 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2929 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2930 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2931 // CHECK3: omp.inner.for.cond:
2932 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2933 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2934 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2935 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2936 // CHECK3: omp.inner.for.body:
2937 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2938 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
2939 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
2940 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
2941 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
2942 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
2943 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
2944 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
2945 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
2946 // CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
2947 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
2948 // CHECK3-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
2949 // CHECK3-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
2950 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2951 // CHECK3: omp.body.continue:
2952 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2953 // CHECK3: omp.inner.for.inc:
2954 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2955 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
2956 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
2957 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
2958 // CHECK3: omp.inner.for.end:
2959 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2960 // CHECK3: omp.loop.exit:
2961 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2962 // CHECK3-NEXT: ret void
2963 //
2964 //
2965 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
2966 // CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
2967 // CHECK3-NEXT: entry:
2968 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2969 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
2970 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
2971 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
2972 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
2973 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
2974 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
2975 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
2976 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
2977 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
2978 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
2979 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
2980 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2981 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
2982 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
2983 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
2984 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
2985 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
2986 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
2987 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
2988 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
2989 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
2990 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
2991 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
2992 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
2993 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
2994 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
2995 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
2996 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
2997 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
2998 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
2999 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
3000 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
3001 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
3002 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
3003 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
3004 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
3005 // CHECK3-NEXT: ret void
3006 //
3007 //
3008 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7
3009 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
3010 // CHECK3-NEXT: entry:
3011 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3012 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3013 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3014 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
3015 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
3016 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
3017 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
3018 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
3019 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
3020 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
3021 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
3022 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
3023 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3024 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1
3025 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3026 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3027 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3028 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3029 // CHECK3-NEXT: [[IT:%.*]] = alloca i8, align 1
3030 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3031 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3032 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3033 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
3034 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3035 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
3036 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
3037 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
3038 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
3039 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
3040 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
3041 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
3042 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
3043 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3044 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
3045 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
3046 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
3047 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
3048 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
3049 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
3050 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3051 // CHECK3-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
3052 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3053 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3054 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
3055 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3056 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
3057 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
3058 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
3059 // CHECK3: omp.dispatch.cond:
3060 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3061 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
3062 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3063 // CHECK3: cond.true:
3064 // CHECK3-NEXT: br label [[COND_END:%.*]]
3065 // CHECK3: cond.false:
3066 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3067 // CHECK3-NEXT: br label [[COND_END]]
3068 // CHECK3: cond.end:
3069 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
3070 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3071 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3072 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
3073 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3074 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3075 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
3076 // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
3077 // CHECK3: omp.dispatch.body:
3078 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3079 // CHECK3: omp.inner.for.cond:
3080 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3081 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3082 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
3083 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3084 // CHECK3: omp.inner.for.body:
3085 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3086 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
3087 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
3088 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
3089 // CHECK3-NEXT: store i8 [[CONV]], i8* [[IT]], align 1
3090 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
3091 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
3092 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
3093 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
3094 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
3095 // CHECK3-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
3096 // CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
3097 // CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
3098 // CHECK3-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4
3099 // CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
3100 // CHECK3-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
3101 // CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
3102 // CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
3103 // CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
3104 // CHECK3-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4
3105 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
3106 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
3107 // CHECK3-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
3108 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
3109 // CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
3110 // CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
3111 // CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
3112 // CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
3113 // CHECK3-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
3114 // CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
3115 // CHECK3-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8
3116 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
3117 // CHECK3-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4
3118 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
3119 // CHECK3-NEXT: store i64 [[ADD20]], i64* [[X]], align 4
3120 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
3121 // CHECK3-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
3122 // CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
3123 // CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
3124 // CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
3125 // CHECK3-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4
3126 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3127 // CHECK3: omp.body.continue:
3128 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3129 // CHECK3: omp.inner.for.inc:
3130 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3131 // CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
3132 // CHECK3-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
3133 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
3134 // CHECK3: omp.inner.for.end:
3135 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
3136 // CHECK3: omp.dispatch.inc:
3137 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3138 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3139 // CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
3140 // CHECK3-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
3141 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3142 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3143 // CHECK3-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
3144 // CHECK3-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
3145 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
3146 // CHECK3: omp.dispatch.end:
3147 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
3148 // CHECK3-NEXT: ret void
3149 //
3150 //
3151 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari
3152 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
3153 // CHECK3-NEXT: entry:
3154 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
3155 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
3156 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
3157 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
3158 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4
3159 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3160 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
3161 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
3162 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
3163 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4
3164 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
3165 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
3166 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
3167 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
3168 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
3169 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
3170 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
3171 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
3172 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
3173 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
3174 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
3175 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
3176 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
3177 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
3178 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
3179 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
3180 // CHECK3-NEXT: ret i32 [[TMP8]]
3181 //
3182 //
3183 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
3184 // CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
3185 // CHECK3-NEXT: entry:
3186 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3187 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
3188 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4
3189 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
3190 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
3191 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
3192 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
3193 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
3194 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
3195 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
3196 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3197 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
3198 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3199 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3200 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3201 // CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4
3202 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
3203 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
3204 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
3205 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
3206 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
3207 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
3208 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
3209 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
3210 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
3211 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
3212 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
3213 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3214 // CHECK3: omp_if.then:
3215 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
3216 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
3217 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
3218 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
3219 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
3220 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false)
3221 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3222 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1**
3223 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4
3224 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3225 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double**
3226 // CHECK3-NEXT: store double* [[A]], double** [[TMP14]], align 4
3227 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3228 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4
3229 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3230 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
3231 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4
3232 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3233 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
3234 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4
3235 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3236 // CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4
3237 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3238 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
3239 // CHECK3-NEXT: store i32 2, i32* [[TMP22]], align 4
3240 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3241 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
3242 // CHECK3-NEXT: store i32 2, i32* [[TMP24]], align 4
3243 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3244 // CHECK3-NEXT: store i8* null, i8** [[TMP25]], align 4
3245 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3246 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
3247 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4
3248 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3249 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
3250 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4
3251 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3252 // CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4
3253 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3254 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16**
3255 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4
3256 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3257 // CHECK3-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16**
3258 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4
3259 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
3260 // CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4
3261 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
3262 // CHECK3-NEXT: store i8* null, i8** [[TMP36]], align 4
3263 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3264 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3265 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3266 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3267 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
3268 // CHECK3-NEXT: store i32 1, i32* [[TMP40]], align 4
3269 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
3270 // CHECK3-NEXT: store i32 5, i32* [[TMP41]], align 4
3271 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
3272 // CHECK3-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 4
3273 // CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
3274 // CHECK3-NEXT: store i8** [[TMP38]], i8*** [[TMP43]], align 4
3275 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
3276 // CHECK3-NEXT: store i64* [[TMP39]], i64** [[TMP44]], align 4
3277 // CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
3278 // CHECK3-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i64** [[TMP45]], align 4
3279 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
3280 // CHECK3-NEXT: store i8** null, i8*** [[TMP46]], align 4
3281 // CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
3282 // CHECK3-NEXT: store i8** null, i8*** [[TMP47]], align 4
3283 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
3284 // CHECK3-NEXT: store i64 0, i64* [[TMP48]], align 8
3285 // CHECK3-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
3286 // CHECK3-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
3287 // CHECK3-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3288 // CHECK3: omp_offload.failed:
3289 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
3290 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
3291 // CHECK3: omp_offload.cont:
3292 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
3293 // CHECK3: omp_if.else:
3294 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
3295 // CHECK3-NEXT: br label [[OMP_IF_END]]
3296 // CHECK3: omp_if.end:
3297 // CHECK3-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP1]]
3298 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP51]]
3299 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
3300 // CHECK3-NEXT: [[TMP52:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
3301 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP52]] to i32
3302 // CHECK3-NEXT: [[TMP53:%.*]] = load i32, i32* [[B]], align 4
3303 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP53]]
3304 // CHECK3-NEXT: [[TMP54:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
3305 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP54]])
3306 // CHECK3-NEXT: ret i32 [[ADD3]]
3307 //
3308 //
3309 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
3310 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
3311 // CHECK3-NEXT: entry:
3312 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
3313 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
3314 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
3315 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1
3316 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
3317 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
3318 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
3319 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
3320 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
3321 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
3322 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
3323 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
3324 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4
3325 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2
3326 // CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1
3327 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
3328 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
3329 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
3330 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
3331 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3332 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
3333 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3334 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
3335 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
3336 // CHECK3-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1
3337 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
3338 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
3339 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
3340 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3341 // CHECK3: omp_if.then:
3342 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3343 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
3344 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
3345 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3346 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
3347 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4
3348 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3349 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4
3350 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3351 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
3352 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
3353 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3354 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
3355 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4
3356 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3357 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4
3358 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3359 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
3360 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
3361 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3362 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
3363 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
3364 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3365 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4
3366 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3367 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
3368 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
3369 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3370 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
3371 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
3372 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3373 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4
3374 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3375 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3376 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3377 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
3378 // CHECK3-NEXT: store i32 1, i32* [[TMP29]], align 4
3379 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
3380 // CHECK3-NEXT: store i32 4, i32* [[TMP30]], align 4
3381 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
3382 // CHECK3-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 4
3383 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
3384 // CHECK3-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 4
3385 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
3386 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64** [[TMP33]], align 4
3387 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
3388 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i64** [[TMP34]], align 4
3389 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
3390 // CHECK3-NEXT: store i8** null, i8*** [[TMP35]], align 4
3391 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
3392 // CHECK3-NEXT: store i8** null, i8*** [[TMP36]], align 4
3393 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
3394 // CHECK3-NEXT: store i64 0, i64* [[TMP37]], align 8
3395 // CHECK3-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
3396 // CHECK3-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
3397 // CHECK3-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3398 // CHECK3: omp_offload.failed:
3399 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
3400 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
3401 // CHECK3: omp_offload.cont:
3402 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
3403 // CHECK3: omp_if.else:
3404 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
3405 // CHECK3-NEXT: br label [[OMP_IF_END]]
3406 // CHECK3: omp_if.end:
3407 // CHECK3-NEXT: [[TMP40:%.*]] = load i32, i32* [[A]], align 4
3408 // CHECK3-NEXT: ret i32 [[TMP40]]
3409 //
3410 //
3411 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
3412 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
3413 // CHECK3-NEXT: entry:
3414 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
3415 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
3416 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
3417 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
3418 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
3419 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
3420 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
3421 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
3422 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
3423 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
3424 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4
3425 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2
3426 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
3427 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
3428 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
3429 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
3430 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3431 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
3432 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3433 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
3434 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
3435 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3436 // CHECK3: omp_if.then:
3437 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3438 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
3439 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4
3440 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3441 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
3442 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
3443 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3444 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4
3445 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3446 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
3447 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
3448 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3449 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
3450 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
3451 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3452 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4
3453 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3454 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
3455 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
3456 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3457 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
3458 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
3459 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3460 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4
3461 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3462 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3463 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3464 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
3465 // CHECK3-NEXT: store i32 1, i32* [[TMP22]], align 4
3466 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
3467 // CHECK3-NEXT: store i32 3, i32* [[TMP23]], align 4
3468 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
3469 // CHECK3-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 4
3470 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
3471 // CHECK3-NEXT: store i8** [[TMP21]], i8*** [[TMP25]], align 4
3472 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
3473 // CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64** [[TMP26]], align 4
3474 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
3475 // CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i64** [[TMP27]], align 4
3476 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
3477 // CHECK3-NEXT: store i8** null, i8*** [[TMP28]], align 4
3478 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
3479 // CHECK3-NEXT: store i8** null, i8*** [[TMP29]], align 4
3480 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
3481 // CHECK3-NEXT: store i64 0, i64* [[TMP30]], align 8
3482 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
3483 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
3484 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3485 // CHECK3: omp_offload.failed:
3486 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
3487 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
3488 // CHECK3: omp_offload.cont:
3489 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
3490 // CHECK3: omp_if.else:
3491 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
3492 // CHECK3-NEXT: br label [[OMP_IF_END]]
3493 // CHECK3: omp_if.end:
3494 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[A]], align 4
3495 // CHECK3-NEXT: ret i32 [[TMP33]]
3496 //
3497 //
3498 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
3499 // CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
3500 // CHECK3-NEXT: entry:
3501 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3502 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
3503 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
3504 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
3505 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
3506 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
3507 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3508 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
3509 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3510 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
3511 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
3512 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3513 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3514 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
3515 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
3516 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
3517 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
3518 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
3519 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
3520 // CHECK3-NEXT: ret void
3521 //
3522 //
3523 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10
3524 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
3525 // CHECK3-NEXT: entry:
3526 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3527 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3528 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3529 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
3530 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
3531 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
3532 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
3533 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
3534 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4
3535 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
3536 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
3537 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
3538 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3539 // CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8
3540 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3541 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3542 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3543 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
3544 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3545 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
3546 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
3547 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3548 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3549 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
3550 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
3551 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
3552 // CHECK3-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
3553 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
3554 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3555 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3556 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
3557 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
3558 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3559 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
3560 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3561 // CHECK3: cond.true:
3562 // CHECK3-NEXT: br label [[COND_END:%.*]]
3563 // CHECK3: cond.false:
3564 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3565 // CHECK3-NEXT: br label [[COND_END]]
3566 // CHECK3: cond.end:
3567 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3568 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
3569 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
3570 // CHECK3-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
3571 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3572 // CHECK3: omp.inner.for.cond:
3573 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3574 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3575 // CHECK3-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
3576 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3577 // CHECK3: omp.inner.for.body:
3578 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3579 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
3580 // CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
3581 // CHECK3-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
3582 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
3583 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
3584 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
3585 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
3586 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4
3587 // CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
3588 // CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4
3589 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
3590 // CHECK3-NEXT: store double [[INC]], double* [[A4]], align 4
3591 // CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
3592 // CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
3593 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
3594 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
3595 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
3596 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3597 // CHECK3: omp.body.continue:
3598 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3599 // CHECK3: omp.inner.for.inc:
3600 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3601 // CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
3602 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
3603 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
3604 // CHECK3: omp.inner.for.end:
3605 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3606 // CHECK3: omp.loop.exit:
3607 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
3608 // CHECK3-NEXT: ret void
3609 //
3610 //
3611 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
3612 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3613 // CHECK3-NEXT: entry:
3614 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3615 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
3616 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
3617 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
3618 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
3619 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
3620 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
3621 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3622 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
3623 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
3624 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
3625 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3626 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
3627 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
3628 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
3629 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
3630 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
3631 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
3632 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3633 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
3634 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3635 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
3636 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
3637 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
3638 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
3639 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
3640 // CHECK3-NEXT: ret void
3641 //
3642 //
3643 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13
3644 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
3645 // CHECK3-NEXT: entry:
3646 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3647 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3648 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3649 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
3650 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
3651 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
3652 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3653 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
3654 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3655 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3656 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3657 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
3658 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
3659 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
3660 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3661 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
3662 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
3663 // CHECK3-NEXT: ret void
3664 //
3665 //
3666 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
3667 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3668 // CHECK3-NEXT: entry:
3669 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3670 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
3671 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
3672 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
3673 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
3674 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3675 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
3676 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
3677 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3678 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
3679 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
3680 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
3681 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
3682 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
3683 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3684 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
3685 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3686 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
3687 // CHECK3-NEXT: ret void
3688 //
3689 //
3690 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16
3691 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
3692 // CHECK3-NEXT: entry:
3693 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3694 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3695 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3696 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
3697 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
3698 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
3699 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4
3700 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
3701 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
3702 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
3703 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3704 // CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8
3705 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3706 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3707 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3708 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
3709 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
3710 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3711 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
3712 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
3713 // CHECK3-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
3714 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
3715 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3716 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3717 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
3718 // CHECK3-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
3719 // CHECK3-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3720 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
3721 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3722 // CHECK3: cond.true:
3723 // CHECK3-NEXT: br label [[COND_END:%.*]]
3724 // CHECK3: cond.false:
3725 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3726 // CHECK3-NEXT: br label [[COND_END]]
3727 // CHECK3: cond.end:
3728 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
3729 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
3730 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
3731 // CHECK3-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
3732 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3733 // CHECK3: omp.inner.for.cond:
3734 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3735 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3736 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
3737 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3738 // CHECK3: omp.inner.for.body:
3739 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3740 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
3741 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
3742 // CHECK3-NEXT: store i64 [[ADD]], i64* [[I]], align 8
3743 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
3744 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
3745 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
3746 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
3747 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
3748 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
3749 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
3750 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
3751 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
3752 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
3753 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
3754 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
3755 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3756 // CHECK3: omp.body.continue:
3757 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3758 // CHECK3: omp.inner.for.inc:
3759 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3760 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
3761 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
3762 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
3763 // CHECK3: omp.inner.for.end:
3764 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3765 // CHECK3: omp.loop.exit:
3766 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
3767 // CHECK3-NEXT: ret void
3768 //
3769 //
3770 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3771 // CHECK3-SAME: () #[[ATTR6]] {
3772 // CHECK3-NEXT: entry:
3773 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
3774 // CHECK3-NEXT: ret void
3775 //
3776 //
3777 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
3778 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
3779 // CHECK9-NEXT: entry:
3780 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
3781 // CHECK9-NEXT: ret void
3782 //
3783 //
3784 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
3785 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
3786 // CHECK9-NEXT: entry:
3787 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3788 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3789 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3790 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
3791 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3792 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3793 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3794 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3795 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
3796 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3797 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3798 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3799 // CHECK9-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
3800 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3801 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3802 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3803 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
3804 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3805 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3806 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
3807 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3808 // CHECK9: cond.true:
3809 // CHECK9-NEXT: br label [[COND_END:%.*]]
3810 // CHECK9: cond.false:
3811 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3812 // CHECK9-NEXT: br label [[COND_END]]
3813 // CHECK9: cond.end:
3814 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
3815 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3816 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3817 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
3818 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3819 // CHECK9: omp.inner.for.cond:
3820 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3821 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3822 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
3823 // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3824 // CHECK9: omp.inner.for.body:
3825 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3826 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
3827 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
3828 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
3829 // CHECK9-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
3830 // CHECK9-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
3831 // CHECK9-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
3832 // CHECK9: .cancel.exit:
3833 // CHECK9-NEXT: br label [[CANCEL_EXIT:%.*]]
3834 // CHECK9: .cancel.continue:
3835 // CHECK9-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
3836 // CHECK9-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
3837 // CHECK9-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
3838 // CHECK9: .cancel.exit2:
3839 // CHECK9-NEXT: br label [[CANCEL_EXIT]]
3840 // CHECK9: .cancel.continue3:
3841 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3842 // CHECK9: omp.body.continue:
3843 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3844 // CHECK9: omp.inner.for.inc:
3845 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3846 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
3847 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
3848 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
3849 // CHECK9: omp.inner.for.end:
3850 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3851 // CHECK9: omp.loop.exit:
3852 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
3853 // CHECK9-NEXT: br label [[CANCEL_CONT:%.*]]
3854 // CHECK9: cancel.cont:
3855 // CHECK9-NEXT: ret void
3856 // CHECK9: cancel.exit:
3857 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
3858 // CHECK9-NEXT: br label [[CANCEL_CONT]]
3859 //
3860 //
3861 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
3862 // CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {
3863 // CHECK9-NEXT: entry:
3864 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
3865 // CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
3866 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
3867 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
3868 // CHECK9-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
3869 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
3870 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
3871 // CHECK9-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
3872 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
3873 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3874 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
3875 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3876 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
3877 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
3878 // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
3879 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
3880 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
3881 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
3882 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
3883 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
3884 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
3885 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3886 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
3887 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
3888 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
3889 // CHECK9-NEXT: ret void
3890 //
3891 //
3892 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
3893 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {
3894 // CHECK9-NEXT: entry:
3895 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3896 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3897 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
3898 // CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
3899 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
3900 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
3901 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8
3902 // CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
3903 // CHECK9-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
3904 // CHECK9-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
3905 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
3906 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
3907 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
3908 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3909 // CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8
3910 // CHECK9-NEXT: [[LIN4:%.*]] = alloca i32, align 4
3911 // CHECK9-NEXT: [[A5:%.*]] = alloca i32, align 4
3912 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3913 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3914 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
3915 // CHECK9-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
3916 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
3917 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3918 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
3919 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3920 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
3921 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
3922 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
3923 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
3924 // CHECK9-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
3925 // CHECK9-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
3926 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
3927 // CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
3928 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
3929 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3930 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3931 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
3932 // CHECK9-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
3933 // CHECK9-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
3934 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3935 // CHECK9-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
3936 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3937 // CHECK9: cond.true:
3938 // CHECK9-NEXT: br label [[COND_END:%.*]]
3939 // CHECK9: cond.false:
3940 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3941 // CHECK9-NEXT: br label [[COND_END]]
3942 // CHECK9: cond.end:
3943 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
3944 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
3945 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
3946 // CHECK9-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
3947 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3948 // CHECK9: omp.inner.for.cond:
3949 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3950 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3951 // CHECK9-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
3952 // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3953 // CHECK9: omp.inner.for.body:
3954 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3955 // CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
3956 // CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
3957 // CHECK9-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
3958 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
3959 // CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
3960 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3961 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
3962 // CHECK9-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
3963 // CHECK9-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
3964 // CHECK9-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
3965 // CHECK9-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4
3966 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
3967 // CHECK9-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
3968 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3969 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
3970 // CHECK9-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
3971 // CHECK9-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
3972 // CHECK9-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
3973 // CHECK9-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
3974 // CHECK9-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
3975 // CHECK9-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
3976 // CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
3977 // CHECK9-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
3978 // CHECK9-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
3979 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3980 // CHECK9: omp.body.continue:
3981 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3982 // CHECK9: omp.inner.for.inc:
3983 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3984 // CHECK9-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
3985 // CHECK9-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
3986 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
3987 // CHECK9: omp.inner.for.end:
3988 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3989 // CHECK9: omp.loop.exit:
3990 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
3991 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3992 // CHECK9-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
3993 // CHECK9-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
3994 // CHECK9: .omp.linear.pu:
3995 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
3996 // CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
3997 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
3998 // CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
3999 // CHECK9-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
4000 // CHECK9: .omp.linear.pu.done:
4001 // CHECK9-NEXT: ret void
4002 //
4003 //
4004 // CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv
4005 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
4006 // CHECK9-NEXT: entry:
4007 // CHECK9-NEXT: ret i64 0
4008 //
4009 //
4010 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
4011 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
4012 // CHECK9-NEXT: entry:
4013 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
4014 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
4015 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
4016 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
4017 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
4018 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
4019 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
4020 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
4021 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
4022 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
4023 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
4024 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
4025 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
4026 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
4027 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
4028 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
4029 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
4030 // CHECK9-NEXT: ret void
4031 //
4032 //
4033 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
4034 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] {
4035 // CHECK9-NEXT: entry:
4036 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4037 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4038 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
4039 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
4040 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4041 // CHECK9-NEXT: [[TMP:%.*]] = alloca i16, align 2
4042 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4043 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4044 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4045 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4046 // CHECK9-NEXT: [[IT:%.*]] = alloca i16, align 2
4047 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4048 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4049 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
4050 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
4051 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
4052 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
4053 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4054 // CHECK9-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
4055 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4056 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4057 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4058 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4059 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4060 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4061 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
4062 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4063 // CHECK9: cond.true:
4064 // CHECK9-NEXT: br label [[COND_END:%.*]]
4065 // CHECK9: cond.false:
4066 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4067 // CHECK9-NEXT: br label [[COND_END]]
4068 // CHECK9: cond.end:
4069 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4070 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4071 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4072 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4073 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4074 // CHECK9: omp.inner.for.cond:
4075 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4076 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4077 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4078 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4079 // CHECK9: omp.inner.for.body:
4080 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4081 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
4082 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
4083 // CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
4084 // CHECK9-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
4085 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
4086 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
4087 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
4088 // CHECK9-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
4089 // CHECK9-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
4090 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
4091 // CHECK9-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
4092 // CHECK9-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
4093 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4094 // CHECK9: omp.body.continue:
4095 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4096 // CHECK9: omp.inner.for.inc:
4097 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4098 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
4099 // CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
4100 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
4101 // CHECK9: omp.inner.for.end:
4102 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4103 // CHECK9: omp.loop.exit:
4104 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4105 // CHECK9-NEXT: ret void
4106 //
4107 //
4108 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
4109 // CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
4110 // CHECK9-NEXT: entry:
4111 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
4112 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
4113 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
4114 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
4115 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
4116 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
4117 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
4118 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
4119 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
4120 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
4121 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
4122 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
4123 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
4124 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
4125 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
4126 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
4127 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
4128 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
4129 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
4130 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
4131 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
4132 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
4133 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
4134 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
4135 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
4136 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
4137 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
4138 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
4139 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
4140 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
4141 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
4142 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
4143 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
4144 // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
4145 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
4146 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
4147 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
4148 // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
4149 // CHECK9-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
4150 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
4151 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
4152 // CHECK9-NEXT: ret void
4153 //
4154 //
4155 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
4156 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
4157 // CHECK9-NEXT: entry:
4158 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4159 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4160 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
4161 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
4162 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
4163 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
4164 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
4165 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
4166 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
4167 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
4168 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
4169 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
4170 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4171 // CHECK9-NEXT: [[TMP:%.*]] = alloca i8, align 1
4172 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4173 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4174 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4175 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4176 // CHECK9-NEXT: [[IT:%.*]] = alloca i8, align 1
4177 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4178 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4179 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
4180 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
4181 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
4182 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
4183 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
4184 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
4185 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
4186 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
4187 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
4188 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
4189 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
4190 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
4191 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
4192 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
4193 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
4194 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
4195 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
4196 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
4197 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
4198 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
4199 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4200 // CHECK9-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
4201 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4202 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4203 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
4204 // CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4205 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
4206 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
4207 // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
4208 // CHECK9: omp.dispatch.cond:
4209 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4210 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
4211 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4212 // CHECK9: cond.true:
4213 // CHECK9-NEXT: br label [[COND_END:%.*]]
4214 // CHECK9: cond.false:
4215 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4216 // CHECK9-NEXT: br label [[COND_END]]
4217 // CHECK9: cond.end:
4218 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
4219 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4220 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4221 // CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
4222 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4223 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4224 // CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
4225 // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
4226 // CHECK9: omp.dispatch.body:
4227 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4228 // CHECK9: omp.inner.for.cond:
4229 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4230 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4231 // CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
4232 // CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4233 // CHECK9: omp.inner.for.body:
4234 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4235 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
4236 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
4237 // CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
4238 // CHECK9-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
4239 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
4240 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
4241 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
4242 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
4243 // CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
4244 // CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
4245 // CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
4246 // CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
4247 // CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
4248 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
4249 // CHECK9-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
4250 // CHECK9-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
4251 // CHECK9-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
4252 // CHECK9-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
4253 // CHECK9-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4
4254 // CHECK9-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
4255 // CHECK9-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
4256 // CHECK9-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
4257 // CHECK9-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
4258 // CHECK9-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8
4259 // CHECK9-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
4260 // CHECK9-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
4261 // CHECK9-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
4262 // CHECK9-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
4263 // CHECK9-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
4264 // CHECK9-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8
4265 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
4266 // CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8
4267 // CHECK9-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
4268 // CHECK9-NEXT: store i64 [[ADD22]], i64* [[X]], align 8
4269 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
4270 // CHECK9-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
4271 // CHECK9-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
4272 // CHECK9-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
4273 // CHECK9-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
4274 // CHECK9-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8
4275 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4276 // CHECK9: omp.body.continue:
4277 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4278 // CHECK9: omp.inner.for.inc:
4279 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4280 // CHECK9-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
4281 // CHECK9-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
4282 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
4283 // CHECK9: omp.inner.for.end:
4284 // CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
4285 // CHECK9: omp.dispatch.inc:
4286 // CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4287 // CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4288 // CHECK9-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
4289 // CHECK9-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
4290 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4291 // CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4292 // CHECK9-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
4293 // CHECK9-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
4294 // CHECK9-NEXT: br label [[OMP_DISPATCH_COND]]
4295 // CHECK9: omp.dispatch.end:
4296 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
4297 // CHECK9-NEXT: ret void
4298 //
4299 //
4300 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
4301 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
4302 // CHECK9-NEXT: entry:
4303 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
4304 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
4305 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
4306 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
4307 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
4308 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
4309 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
4310 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
4311 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
4312 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
4313 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
4314 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
4315 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
4316 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
4317 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
4318 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
4319 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
4320 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
4321 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
4322 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
4323 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
4324 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
4325 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
4326 // CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
4327 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
4328 // CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
4329 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
4330 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
4331 // CHECK9-NEXT: ret void
4332 //
4333 //
4334 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4
4335 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
4336 // CHECK9-NEXT: entry:
4337 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4338 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4339 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
4340 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
4341 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
4342 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
4343 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4344 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
4345 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4346 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4347 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
4348 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
4349 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
4350 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
4351 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
4352 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
4353 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
4354 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
4355 // CHECK9-NEXT: ret void
4356 //
4357 //
4358 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
4359 // CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
4360 // CHECK9-NEXT: entry:
4361 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
4362 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
4363 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
4364 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
4365 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
4366 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
4367 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
4368 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
4369 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
4370 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
4371 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
4372 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
4373 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
4374 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
4375 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
4376 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
4377 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
4378 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
4379 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
4380 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
4381 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
4382 // CHECK9-NEXT: ret void
4383 //
4384 //
4385 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
4386 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
4387 // CHECK9-NEXT: entry:
4388 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4389 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4390 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
4391 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
4392 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
4393 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
4394 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
4395 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
4396 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8
4397 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
4398 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
4399 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
4400 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4401 // CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8
4402 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4403 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4404 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
4405 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
4406 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
4407 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
4408 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
4409 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
4410 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
4411 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
4412 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
4413 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
4414 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
4415 // CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
4416 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
4417 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4418 // CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4419 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
4420 // CHECK9-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
4421 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
4422 // CHECK9-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
4423 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4424 // CHECK9: cond.true:
4425 // CHECK9-NEXT: br label [[COND_END:%.*]]
4426 // CHECK9: cond.false:
4427 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
4428 // CHECK9-NEXT: br label [[COND_END]]
4429 // CHECK9: cond.end:
4430 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
4431 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
4432 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
4433 // CHECK9-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
4434 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4435 // CHECK9: omp.inner.for.cond:
4436 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
4437 // CHECK9-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
4438 // CHECK9-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
4439 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4440 // CHECK9: omp.inner.for.body:
4441 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
4442 // CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
4443 // CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
4444 // CHECK9-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
4445 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
4446 // CHECK9-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
4447 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
4448 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
4449 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8
4450 // CHECK9-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
4451 // CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
4452 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
4453 // CHECK9-NEXT: store double [[INC]], double* [[A5]], align 8
4454 // CHECK9-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
4455 // CHECK9-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
4456 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
4457 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
4458 // CHECK9-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
4459 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4460 // CHECK9: omp.body.continue:
4461 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4462 // CHECK9: omp.inner.for.inc:
4463 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
4464 // CHECK9-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1
4465 // CHECK9-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
4466 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
4467 // CHECK9: omp.inner.for.end:
4468 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4469 // CHECK9: omp.loop.exit:
4470 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
4471 // CHECK9-NEXT: ret void
4472 //
4473 //
4474 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
4475 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
4476 // CHECK9-NEXT: entry:
4477 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
4478 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
4479 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
4480 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
4481 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
4482 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
4483 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
4484 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
4485 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
4486 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
4487 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
4488 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
4489 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
4490 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
4491 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
4492 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
4493 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
4494 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
4495 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
4496 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
4497 // CHECK9-NEXT: ret void
4498 //
4499 //
4500 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6
4501 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
4502 // CHECK9-NEXT: entry:
4503 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4504 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4505 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
4506 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
4507 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
4508 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
4509 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8
4510 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
4511 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
4512 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
4513 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4514 // CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8
4515 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4516 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4517 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
4518 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
4519 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
4520 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
4521 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
4522 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
4523 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
4524 // CHECK9-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
4525 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
4526 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4527 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4528 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
4529 // CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
4530 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
4531 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
4532 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4533 // CHECK9: cond.true:
4534 // CHECK9-NEXT: br label [[COND_END:%.*]]
4535 // CHECK9: cond.false:
4536 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
4537 // CHECK9-NEXT: br label [[COND_END]]
4538 // CHECK9: cond.end:
4539 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
4540 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
4541 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
4542 // CHECK9-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
4543 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4544 // CHECK9: omp.inner.for.cond:
4545 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
4546 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
4547 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
4548 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4549 // CHECK9: omp.inner.for.body:
4550 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
4551 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
4552 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
4553 // CHECK9-NEXT: store i64 [[ADD]], i64* [[I]], align 8
4554 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
4555 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
4556 // CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
4557 // CHECK9-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
4558 // CHECK9-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
4559 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
4560 // CHECK9-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
4561 // CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
4562 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
4563 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
4564 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
4565 // CHECK9-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
4566 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4567 // CHECK9: omp.body.continue:
4568 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4569 // CHECK9: omp.inner.for.inc:
4570 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
4571 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
4572 // CHECK9-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
4573 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
4574 // CHECK9: omp.inner.for.end:
4575 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4576 // CHECK9: omp.loop.exit:
4577 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
4578 // CHECK9-NEXT: ret void
4579 //
4580 //
4581 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
4582 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
4583 // CHECK11-NEXT: entry:
4584 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
4585 // CHECK11-NEXT: ret void
4586 //
4587 //
4588 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
4589 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
4590 // CHECK11-NEXT: entry:
4591 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4592 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4593 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4594 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
4595 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4596 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4597 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4598 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4599 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
4600 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4601 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4602 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4603 // CHECK11-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
4604 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4605 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4606 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4607 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4608 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4609 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4610 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
4611 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4612 // CHECK11: cond.true:
4613 // CHECK11-NEXT: br label [[COND_END:%.*]]
4614 // CHECK11: cond.false:
4615 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4616 // CHECK11-NEXT: br label [[COND_END]]
4617 // CHECK11: cond.end:
4618 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4619 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4620 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4621 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4622 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4623 // CHECK11: omp.inner.for.cond:
4624 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4625 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4626 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4627 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4628 // CHECK11: omp.inner.for.body:
4629 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4630 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
4631 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
4632 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4
4633 // CHECK11-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
4634 // CHECK11-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
4635 // CHECK11-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
4636 // CHECK11: .cancel.exit:
4637 // CHECK11-NEXT: br label [[CANCEL_EXIT:%.*]]
4638 // CHECK11: .cancel.continue:
4639 // CHECK11-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
4640 // CHECK11-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
4641 // CHECK11-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
4642 // CHECK11: .cancel.exit2:
4643 // CHECK11-NEXT: br label [[CANCEL_EXIT]]
4644 // CHECK11: .cancel.continue3:
4645 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4646 // CHECK11: omp.body.continue:
4647 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4648 // CHECK11: omp.inner.for.inc:
4649 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4650 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
4651 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
4652 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
4653 // CHECK11: omp.inner.for.end:
4654 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4655 // CHECK11: omp.loop.exit:
4656 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4657 // CHECK11-NEXT: br label [[CANCEL_CONT:%.*]]
4658 // CHECK11: cancel.cont:
4659 // CHECK11-NEXT: ret void
4660 // CHECK11: cancel.exit:
4661 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4662 // CHECK11-NEXT: br label [[CANCEL_CONT]]
4663 //
4664 //
4665 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
4666 // CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {
4667 // CHECK11-NEXT: entry:
4668 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4669 // CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
4670 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4671 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
4672 // CHECK11-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
4673 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
4674 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
4675 // CHECK11-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
4676 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4677 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4678 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
4679 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4680 // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
4681 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4682 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
4683 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
4684 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
4685 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
4686 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
4687 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
4688 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
4689 // CHECK11-NEXT: ret void
4690 //
4691 //
4692 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1
4693 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] {
4694 // CHECK11-NEXT: entry:
4695 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4696 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4697 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4698 // CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
4699 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4700 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
4701 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4
4702 // CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
4703 // CHECK11-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
4704 // CHECK11-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
4705 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
4706 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
4707 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
4708 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4709 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8
4710 // CHECK11-NEXT: [[LIN2:%.*]] = alloca i32, align 4
4711 // CHECK11-NEXT: [[A3:%.*]] = alloca i32, align 4
4712 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4713 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4714 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
4715 // CHECK11-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
4716 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4717 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4718 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
4719 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
4720 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
4721 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
4722 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
4723 // CHECK11-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
4724 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
4725 // CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
4726 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
4727 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4728 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4729 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
4730 // CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
4731 // CHECK11-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
4732 // CHECK11-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
4733 // CHECK11-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
4734 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4735 // CHECK11: cond.true:
4736 // CHECK11-NEXT: br label [[COND_END:%.*]]
4737 // CHECK11: cond.false:
4738 // CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
4739 // CHECK11-NEXT: br label [[COND_END]]
4740 // CHECK11: cond.end:
4741 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
4742 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
4743 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
4744 // CHECK11-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
4745 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4746 // CHECK11: omp.inner.for.cond:
4747 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
4748 // CHECK11-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
4749 // CHECK11-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
4750 // CHECK11-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4751 // CHECK11: omp.inner.for.body:
4752 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
4753 // CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
4754 // CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
4755 // CHECK11-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
4756 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
4757 // CHECK11-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
4758 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
4759 // CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
4760 // CHECK11-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
4761 // CHECK11-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
4762 // CHECK11-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
4763 // CHECK11-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4
4764 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
4765 // CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
4766 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
4767 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
4768 // CHECK11-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
4769 // CHECK11-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
4770 // CHECK11-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
4771 // CHECK11-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
4772 // CHECK11-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
4773 // CHECK11-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
4774 // CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
4775 // CHECK11-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
4776 // CHECK11-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
4777 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4778 // CHECK11: omp.body.continue:
4779 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4780 // CHECK11: omp.inner.for.inc:
4781 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
4782 // CHECK11-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
4783 // CHECK11-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
4784 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
4785 // CHECK11: omp.inner.for.end:
4786 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4787 // CHECK11: omp.loop.exit:
4788 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
4789 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4790 // CHECK11-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
4791 // CHECK11-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
4792 // CHECK11: .omp.linear.pu:
4793 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4
4794 // CHECK11-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4
4795 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4
4796 // CHECK11-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4
4797 // CHECK11-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
4798 // CHECK11: .omp.linear.pu.done:
4799 // CHECK11-NEXT: ret void
4800 //
4801 //
4802 // CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv
4803 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
4804 // CHECK11-NEXT: entry:
4805 // CHECK11-NEXT: ret i64 0
4806 //
4807 //
4808 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
4809 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
4810 // CHECK11-NEXT: entry:
4811 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4812 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4813 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
4814 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
4815 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4816 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
4817 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4818 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4819 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4820 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4821 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
4822 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4823 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
4824 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4825 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
4826 // CHECK11-NEXT: ret void
4827 //
4828 //
4829 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2
4830 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] {
4831 // CHECK11-NEXT: entry:
4832 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4833 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4834 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4835 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4836 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4837 // CHECK11-NEXT: [[TMP:%.*]] = alloca i16, align 2
4838 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4839 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4840 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4841 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4842 // CHECK11-NEXT: [[IT:%.*]] = alloca i16, align 2
4843 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4844 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4845 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4846 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
4847 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4848 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4849 // CHECK11-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
4850 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4851 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4852 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4853 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4854 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4855 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4856 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
4857 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4858 // CHECK11: cond.true:
4859 // CHECK11-NEXT: br label [[COND_END:%.*]]
4860 // CHECK11: cond.false:
4861 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4862 // CHECK11-NEXT: br label [[COND_END]]
4863 // CHECK11: cond.end:
4864 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4865 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4866 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4867 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4868 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4869 // CHECK11: omp.inner.for.cond:
4870 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4871 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4872 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4873 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4874 // CHECK11: omp.inner.for.body:
4875 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4876 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
4877 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
4878 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
4879 // CHECK11-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
4880 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
4881 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
4882 // CHECK11-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
4883 // CHECK11-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
4884 // CHECK11-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
4885 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
4886 // CHECK11-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
4887 // CHECK11-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
4888 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4889 // CHECK11: omp.body.continue:
4890 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4891 // CHECK11: omp.inner.for.inc:
4892 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4893 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
4894 // CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
4895 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
4896 // CHECK11: omp.inner.for.end:
4897 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4898 // CHECK11: omp.loop.exit:
4899 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4900 // CHECK11-NEXT: ret void
4901 //
4902 //
4903 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
4904 // CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
4905 // CHECK11-NEXT: entry:
4906 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4907 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
4908 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
4909 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
4910 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
4911 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
4912 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
4913 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
4914 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
4915 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
4916 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
4917 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
4918 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4919 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
4920 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
4921 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
4922 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
4923 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
4924 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
4925 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
4926 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
4927 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4928 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
4929 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
4930 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
4931 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
4932 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
4933 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
4934 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
4935 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
4936 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
4937 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
4938 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
4939 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4940 // CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
4941 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
4942 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
4943 // CHECK11-NEXT: ret void
4944 //
4945 //
4946 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3
4947 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
4948 // CHECK11-NEXT: entry:
4949 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4950 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4951 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4952 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
4953 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
4954 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
4955 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
4956 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
4957 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
4958 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
4959 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
4960 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
4961 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4962 // CHECK11-NEXT: [[TMP:%.*]] = alloca i8, align 1
4963 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4964 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4965 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4966 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4967 // CHECK11-NEXT: [[IT:%.*]] = alloca i8, align 1
4968 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4969 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4970 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4971 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
4972 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
4973 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
4974 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
4975 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
4976 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
4977 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
4978 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
4979 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4980 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
4981 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
4982 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
4983 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
4984 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
4985 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
4986 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
4987 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
4988 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4989 // CHECK11-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
4990 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4991 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4992 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4993 // CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4994 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
4995 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
4996 // CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
4997 // CHECK11: omp.dispatch.cond:
4998 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4999 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
5000 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5001 // CHECK11: cond.true:
5002 // CHECK11-NEXT: br label [[COND_END:%.*]]
5003 // CHECK11: cond.false:
5004 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5005 // CHECK11-NEXT: br label [[COND_END]]
5006 // CHECK11: cond.end:
5007 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
5008 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5009 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5010 // CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
5011 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5012 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5013 // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
5014 // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
5015 // CHECK11: omp.dispatch.body:
5016 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5017 // CHECK11: omp.inner.for.cond:
5018 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5019 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5020 // CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
5021 // CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5022 // CHECK11: omp.inner.for.body:
5023 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5024 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
5025 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
5026 // CHECK11-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
5027 // CHECK11-NEXT: store i8 [[CONV]], i8* [[IT]], align 1
5028 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
5029 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
5030 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
5031 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
5032 // CHECK11-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
5033 // CHECK11-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
5034 // CHECK11-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
5035 // CHECK11-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
5036 // CHECK11-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4
5037 // CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
5038 // CHECK11-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
5039 // CHECK11-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
5040 // CHECK11-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
5041 // CHECK11-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
5042 // CHECK11-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4
5043 // CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
5044 // CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
5045 // CHECK11-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
5046 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
5047 // CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
5048 // CHECK11-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
5049 // CHECK11-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
5050 // CHECK11-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
5051 // CHECK11-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
5052 // CHECK11-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
5053 // CHECK11-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8
5054 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
5055 // CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4
5056 // CHECK11-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
5057 // CHECK11-NEXT: store i64 [[ADD20]], i64* [[X]], align 4
5058 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
5059 // CHECK11-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
5060 // CHECK11-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
5061 // CHECK11-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
5062 // CHECK11-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
5063 // CHECK11-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4
5064 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5065 // CHECK11: omp.body.continue:
5066 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5067 // CHECK11: omp.inner.for.inc:
5068 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5069 // CHECK11-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
5070 // CHECK11-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
5071 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
5072 // CHECK11: omp.inner.for.end:
5073 // CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
5074 // CHECK11: omp.dispatch.inc:
5075 // CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5076 // CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
5077 // CHECK11-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
5078 // CHECK11-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
5079 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5080 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
5081 // CHECK11-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
5082 // CHECK11-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
5083 // CHECK11-NEXT: br label [[OMP_DISPATCH_COND]]
5084 // CHECK11: omp.dispatch.end:
5085 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
5086 // CHECK11-NEXT: ret void
5087 //
5088 //
5089 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
5090 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
5091 // CHECK11-NEXT: entry:
5092 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5093 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
5094 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
5095 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5096 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
5097 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
5098 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
5099 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
5100 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
5101 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
5102 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5103 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5104 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
5105 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5106 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5107 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
5108 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
5109 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
5110 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5111 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
5112 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5113 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
5114 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
5115 // CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
5116 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
5117 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
5118 // CHECK11-NEXT: ret void
5119 //
5120 //
5121 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4
5122 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
5123 // CHECK11-NEXT: entry:
5124 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5125 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5126 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5127 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
5128 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
5129 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5130 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5131 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
5132 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5133 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5134 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
5135 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
5136 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
5137 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5138 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5139 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
5140 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5141 // CHECK11-NEXT: ret void
5142 //
5143 //
5144 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
5145 // CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
5146 // CHECK11-NEXT: entry:
5147 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
5148 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
5149 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
5150 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
5151 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
5152 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
5153 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
5154 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
5155 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
5156 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
5157 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
5158 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
5159 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
5160 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
5161 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
5162 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
5163 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
5164 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
5165 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
5166 // CHECK11-NEXT: ret void
5167 //
5168 //
5169 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5
5170 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
5171 // CHECK11-NEXT: entry:
5172 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5173 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5174 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
5175 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
5176 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
5177 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
5178 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
5179 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
5180 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4
5181 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
5182 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
5183 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
5184 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5185 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8
5186 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5187 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5188 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
5189 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
5190 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
5191 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
5192 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
5193 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
5194 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
5195 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
5196 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
5197 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
5198 // CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
5199 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
5200 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5201 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5202 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
5203 // CHECK11-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
5204 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5205 // CHECK11-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
5206 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5207 // CHECK11: cond.true:
5208 // CHECK11-NEXT: br label [[COND_END:%.*]]
5209 // CHECK11: cond.false:
5210 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5211 // CHECK11-NEXT: br label [[COND_END]]
5212 // CHECK11: cond.end:
5213 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
5214 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
5215 // CHECK11-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
5216 // CHECK11-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
5217 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5218 // CHECK11: omp.inner.for.cond:
5219 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
5220 // CHECK11-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5221 // CHECK11-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
5222 // CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5223 // CHECK11: omp.inner.for.body:
5224 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
5225 // CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
5226 // CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
5227 // CHECK11-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
5228 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
5229 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
5230 // CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
5231 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
5232 // CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4
5233 // CHECK11-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
5234 // CHECK11-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4
5235 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
5236 // CHECK11-NEXT: store double [[INC]], double* [[A4]], align 4
5237 // CHECK11-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
5238 // CHECK11-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
5239 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
5240 // CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
5241 // CHECK11-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
5242 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5243 // CHECK11: omp.body.continue:
5244 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5245 // CHECK11: omp.inner.for.inc:
5246 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
5247 // CHECK11-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
5248 // CHECK11-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
5249 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
5250 // CHECK11: omp.inner.for.end:
5251 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5252 // CHECK11: omp.loop.exit:
5253 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
5254 // CHECK11-NEXT: ret void
5255 //
5256 //
5257 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
5258 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
5259 // CHECK11-NEXT: entry:
5260 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5261 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
5262 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5263 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
5264 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
5265 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
5266 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
5267 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5268 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5269 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5270 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5271 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
5272 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
5273 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
5274 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5275 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
5276 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5277 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
5278 // CHECK11-NEXT: ret void
5279 //
5280 //
5281 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6
5282 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
5283 // CHECK11-NEXT: entry:
5284 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5285 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5286 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5287 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
5288 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5289 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
5290 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4
5291 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
5292 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
5293 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
5294 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5295 // CHECK11-NEXT: [[I:%.*]] = alloca i64, align 8
5296 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5297 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5298 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
5299 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
5300 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5301 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5302 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5303 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
5304 // CHECK11-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
5305 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
5306 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5307 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5308 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
5309 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
5310 // CHECK11-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5311 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
5312 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5313 // CHECK11: cond.true:
5314 // CHECK11-NEXT: br label [[COND_END:%.*]]
5315 // CHECK11: cond.false:
5316 // CHECK11-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5317 // CHECK11-NEXT: br label [[COND_END]]
5318 // CHECK11: cond.end:
5319 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
5320 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
5321 // CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
5322 // CHECK11-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
5323 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5324 // CHECK11: omp.inner.for.cond:
5325 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
5326 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5327 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
5328 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5329 // CHECK11: omp.inner.for.body:
5330 // CHECK11-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
5331 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
5332 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
5333 // CHECK11-NEXT: store i64 [[ADD]], i64* [[I]], align 8
5334 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
5335 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
5336 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
5337 // CHECK11-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
5338 // CHECK11-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
5339 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
5340 // CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
5341 // CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
5342 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
5343 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
5344 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
5345 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
5346 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5347 // CHECK11: omp.body.continue:
5348 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5349 // CHECK11: omp.inner.for.inc:
5350 // CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
5351 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
5352 // CHECK11-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
5353 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
5354 // CHECK11: omp.inner.for.end:
5355 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5356 // CHECK11: omp.loop.exit:
5357 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
5358 // CHECK11-NEXT: ret void
5359 //
5360 //
5361 // CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv
5362 // CHECK17-SAME: () #[[ATTR0:[0-9]+]] {
5363 // CHECK17-NEXT: entry:
5364 // CHECK17-NEXT: ret i64 0
5365 //
5366 //
5367 // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi
5368 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
5369 // CHECK17-NEXT: entry:
5370 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
5371 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
5372 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2
5373 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 4
5374 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
5375 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
5376 // CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
5377 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
5378 // CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
5379 // CHECK17-NEXT: [[K:%.*]] = alloca i64, align 8
5380 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
5381 // CHECK17-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
5382 // CHECK17-NEXT: [[LIN:%.*]] = alloca i32, align 4
5383 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
5384 // CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
5385 // CHECK17-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8
5386 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
5387 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
5388 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
5389 // CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
5390 // CHECK17-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8
5391 // CHECK17-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8
5392 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
5393 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
5394 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
5395 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
5396 // CHECK17-NEXT: [[A_CASTED16:%.*]] = alloca i64, align 8
5397 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
5398 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [10 x i8*], align 8
5399 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [10 x i8*], align 8
5400 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [10 x i8*], align 8
5401 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
5402 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
5403 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
5404 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4
5405 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2
5406 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
5407 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
5408 // CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
5409 // CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
5410 // CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
5411 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
5412 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
5413 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
5414 // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
5415 // CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
5416 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
5417 // CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
5418 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
5419 // CHECK17-NEXT: store i32 1, i32* [[TMP7]], align 4
5420 // CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
5421 // CHECK17-NEXT: store i32 0, i32* [[TMP8]], align 4
5422 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
5423 // CHECK17-NEXT: store i8** null, i8*** [[TMP9]], align 8
5424 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
5425 // CHECK17-NEXT: store i8** null, i8*** [[TMP10]], align 8
5426 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
5427 // CHECK17-NEXT: store i64* null, i64** [[TMP11]], align 8
5428 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
5429 // CHECK17-NEXT: store i64* null, i64** [[TMP12]], align 8
5430 // CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
5431 // CHECK17-NEXT: store i8** null, i8*** [[TMP13]], align 8
5432 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
5433 // CHECK17-NEXT: store i8** null, i8*** [[TMP14]], align 8
5434 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
5435 // CHECK17-NEXT: store i64 0, i64* [[TMP15]], align 8
5436 // CHECK17-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
5437 // CHECK17-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
5438 // CHECK17-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5439 // CHECK17: omp_offload.failed:
5440 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]]
5441 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
5442 // CHECK17: omp_offload.cont:
5443 // CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
5444 // CHECK17-NEXT: store i64 [[CALL]], i64* [[K]], align 8
5445 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4
5446 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
5447 // CHECK17-NEXT: store i32 [[TMP18]], i32* [[CONV]], align 4
5448 // CHECK17-NEXT: [[TMP19:%.*]] = load i64, i64* [[A_CASTED]], align 8
5449 // CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[K]], align 8
5450 // CHECK17-NEXT: store i64 [[TMP20]], i64* [[K_CASTED]], align 8
5451 // CHECK17-NEXT: [[TMP21:%.*]] = load i64, i64* [[K_CASTED]], align 8
5452 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR4]]
5453 // CHECK17-NEXT: store i32 12, i32* [[LIN]], align 4
5454 // CHECK17-NEXT: [[TMP22:%.*]] = load i16, i16* [[AA]], align 2
5455 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
5456 // CHECK17-NEXT: store i16 [[TMP22]], i16* [[CONV2]], align 2
5457 // CHECK17-NEXT: [[TMP23:%.*]] = load i64, i64* [[AA_CASTED]], align 8
5458 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[LIN]], align 4
5459 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
5460 // CHECK17-NEXT: store i32 [[TMP24]], i32* [[CONV3]], align 4
5461 // CHECK17-NEXT: [[TMP25:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
5462 // CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[A]], align 4
5463 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32*
5464 // CHECK17-NEXT: store i32 [[TMP26]], i32* [[CONV5]], align 4
5465 // CHECK17-NEXT: [[TMP27:%.*]] = load i64, i64* [[A_CASTED4]], align 8
5466 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5467 // CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
5468 // CHECK17-NEXT: store i64 [[TMP23]], i64* [[TMP29]], align 8
5469 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5470 // CHECK17-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
5471 // CHECK17-NEXT: store i64 [[TMP23]], i64* [[TMP31]], align 8
5472 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
5473 // CHECK17-NEXT: store i8* null, i8** [[TMP32]], align 8
5474 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5475 // CHECK17-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
5476 // CHECK17-NEXT: store i64 [[TMP25]], i64* [[TMP34]], align 8
5477 // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5478 // CHECK17-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64*
5479 // CHECK17-NEXT: store i64 [[TMP25]], i64* [[TMP36]], align 8
5480 // CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
5481 // CHECK17-NEXT: store i8* null, i8** [[TMP37]], align 8
5482 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5483 // CHECK17-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64*
5484 // CHECK17-NEXT: store i64 [[TMP27]], i64* [[TMP39]], align 8
5485 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5486 // CHECK17-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64*
5487 // CHECK17-NEXT: store i64 [[TMP27]], i64* [[TMP41]], align 8
5488 // CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
5489 // CHECK17-NEXT: store i8* null, i8** [[TMP42]], align 8
5490 // CHECK17-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5491 // CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5492 // CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
5493 // CHECK17-NEXT: [[TMP46:%.*]] = load i16, i16* [[AA]], align 2
5494 // CHECK17-NEXT: store i16 [[TMP46]], i16* [[TMP45]], align 4
5495 // CHECK17-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
5496 // CHECK17-NEXT: [[TMP48:%.*]] = load i32, i32* [[LIN]], align 4
5497 // CHECK17-NEXT: store i32 [[TMP48]], i32* [[TMP47]], align 4
5498 // CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
5499 // CHECK17-NEXT: [[TMP50:%.*]] = load i32, i32* [[A]], align 4
5500 // CHECK17-NEXT: store i32 [[TMP50]], i32* [[TMP49]], align 4
5501 // CHECK17-NEXT: [[TMP51:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
5502 // CHECK17-NEXT: [[TMP52:%.*]] = bitcast i8* [[TMP51]] to %struct.kmp_task_t_with_privates*
5503 // CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP52]], i32 0, i32 0
5504 // CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP53]], i32 0, i32 0
5505 // CHECK17-NEXT: [[TMP55:%.*]] = load i8*, i8** [[TMP54]], align 8
5506 // CHECK17-NEXT: [[TMP56:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
5507 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP55]], i8* align 4 [[TMP56]], i64 12, i1 false)
5508 // CHECK17-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP52]], i32 0, i32 1
5509 // CHECK17-NEXT: [[TMP58:%.*]] = bitcast i8* [[TMP55]] to %struct.anon*
5510 // CHECK17-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP57]], i32 0, i32 0
5511 // CHECK17-NEXT: [[TMP60:%.*]] = bitcast [3 x i8*]* [[TMP59]] to i8*
5512 // CHECK17-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP43]] to i8*
5513 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP60]], i8* align 8 [[TMP61]], i64 24, i1 false)
5514 // CHECK17-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP57]], i32 0, i32 1
5515 // CHECK17-NEXT: [[TMP63:%.*]] = bitcast [3 x i8*]* [[TMP62]] to i8*
5516 // CHECK17-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP44]] to i8*
5517 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP63]], i8* align 8 [[TMP64]], i64 24, i1 false)
5518 // CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP57]], i32 0, i32 2
5519 // CHECK17-NEXT: [[TMP66:%.*]] = bitcast [3 x i64]* [[TMP65]] to i8*
5520 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP66]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
5521 // CHECK17-NEXT: [[TMP67:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP57]], i32 0, i32 3
5522 // CHECK17-NEXT: [[TMP68:%.*]] = load i16, i16* [[AA]], align 2
5523 // CHECK17-NEXT: store i16 [[TMP68]], i16* [[TMP67]], align 8
5524 // CHECK17-NEXT: [[TMP69:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP51]])
5525 // CHECK17-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4
5526 // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32*
5527 // CHECK17-NEXT: store i32 [[TMP70]], i32* [[CONV7]], align 4
5528 // CHECK17-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED6]], align 8
5529 // CHECK17-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2
5530 // CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16*
5531 // CHECK17-NEXT: store i16 [[TMP72]], i16* [[CONV9]], align 2
5532 // CHECK17-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED8]], align 8
5533 // CHECK17-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4
5534 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10
5535 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5536 // CHECK17: omp_if.then:
5537 // CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
5538 // CHECK17-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64*
5539 // CHECK17-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8
5540 // CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
5541 // CHECK17-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
5542 // CHECK17-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8
5543 // CHECK17-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
5544 // CHECK17-NEXT: store i8* null, i8** [[TMP79]], align 8
5545 // CHECK17-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
5546 // CHECK17-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
5547 // CHECK17-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8
5548 // CHECK17-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
5549 // CHECK17-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
5550 // CHECK17-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8
5551 // CHECK17-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
5552 // CHECK17-NEXT: store i8* null, i8** [[TMP84]], align 8
5553 // CHECK17-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
5554 // CHECK17-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
5555 // CHECK17-NEXT: [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
5556 // CHECK17-NEXT: [[TMP87:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 0
5557 // CHECK17-NEXT: store i32 1, i32* [[TMP87]], align 4
5558 // CHECK17-NEXT: [[TMP88:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 1
5559 // CHECK17-NEXT: store i32 2, i32* [[TMP88]], align 4
5560 // CHECK17-NEXT: [[TMP89:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 2
5561 // CHECK17-NEXT: store i8** [[TMP85]], i8*** [[TMP89]], align 8
5562 // CHECK17-NEXT: [[TMP90:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 3
5563 // CHECK17-NEXT: store i8** [[TMP86]], i8*** [[TMP90]], align 8
5564 // CHECK17-NEXT: [[TMP91:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 4
5565 // CHECK17-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64** [[TMP91]], align 8
5566 // CHECK17-NEXT: [[TMP92:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 5
5567 // CHECK17-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP92]], align 8
5568 // CHECK17-NEXT: [[TMP93:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 6
5569 // CHECK17-NEXT: store i8** null, i8*** [[TMP93]], align 8
5570 // CHECK17-NEXT: [[TMP94:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 7
5571 // CHECK17-NEXT: store i8** null, i8*** [[TMP94]], align 8
5572 // CHECK17-NEXT: [[TMP95:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 8
5573 // CHECK17-NEXT: store i64 0, i64* [[TMP95]], align 8
5574 // CHECK17-NEXT: [[TMP96:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]])
5575 // CHECK17-NEXT: [[TMP97:%.*]] = icmp ne i32 [[TMP96]], 0
5576 // CHECK17-NEXT: br i1 [[TMP97]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]
5577 // CHECK17: omp_offload.failed14:
5578 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR4]]
5579 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT15]]
5580 // CHECK17: omp_offload.cont15:
5581 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
5582 // CHECK17: omp_if.else:
5583 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR4]]
5584 // CHECK17-NEXT: br label [[OMP_IF_END]]
5585 // CHECK17: omp_if.end:
5586 // CHECK17-NEXT: [[TMP98:%.*]] = load i32, i32* [[A]], align 4
5587 // CHECK17-NEXT: store i32 [[TMP98]], i32* [[DOTCAPTURE_EXPR_]], align 4
5588 // CHECK17-NEXT: [[TMP99:%.*]] = load i32, i32* [[A]], align 4
5589 // CHECK17-NEXT: [[CONV17:%.*]] = bitcast i64* [[A_CASTED16]] to i32*
5590 // CHECK17-NEXT: store i32 [[TMP99]], i32* [[CONV17]], align 4
5591 // CHECK17-NEXT: [[TMP100:%.*]] = load i64, i64* [[A_CASTED16]], align 8
5592 // CHECK17-NEXT: [[TMP101:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5593 // CHECK17-NEXT: [[CONV18:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
5594 // CHECK17-NEXT: store i32 [[TMP101]], i32* [[CONV18]], align 4
5595 // CHECK17-NEXT: [[TMP102:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
5596 // CHECK17-NEXT: [[TMP103:%.*]] = load i32, i32* [[N_ADDR]], align 4
5597 // CHECK17-NEXT: [[CMP19:%.*]] = icmp sgt i32 [[TMP103]], 20
5598 // CHECK17-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN20:%.*]], label [[OMP_IF_ELSE27:%.*]]
5599 // CHECK17: omp_if.then20:
5600 // CHECK17-NEXT: [[TMP104:%.*]] = mul nuw i64 [[TMP2]], 4
5601 // CHECK17-NEXT: [[TMP105:%.*]] = mul nuw i64 5, [[TMP5]]
5602 // CHECK17-NEXT: [[TMP106:%.*]] = mul nuw i64 [[TMP105]], 8
5603 // CHECK17-NEXT: [[TMP107:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
5604 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP107]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i64 80, i1 false)
5605 // CHECK17-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0
5606 // CHECK17-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i64*
5607 // CHECK17-NEXT: store i64 [[TMP100]], i64* [[TMP109]], align 8
5608 // CHECK17-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0
5609 // CHECK17-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i64*
5610 // CHECK17-NEXT: store i64 [[TMP100]], i64* [[TMP111]], align 8
5611 // CHECK17-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 0
5612 // CHECK17-NEXT: store i8* null, i8** [[TMP112]], align 8
5613 // CHECK17-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1
5614 // CHECK17-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [10 x float]**
5615 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP114]], align 8
5616 // CHECK17-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1
5617 // CHECK17-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to [10 x float]**
5618 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP116]], align 8
5619 // CHECK17-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 1
5620 // CHECK17-NEXT: store i8* null, i8** [[TMP117]], align 8
5621 // CHECK17-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2
5622 // CHECK17-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i64*
5623 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP119]], align 8
5624 // CHECK17-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2
5625 // CHECK17-NEXT: [[TMP121:%.*]] = bitcast i8** [[TMP120]] to i64*
5626 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP121]], align 8
5627 // CHECK17-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 2
5628 // CHECK17-NEXT: store i8* null, i8** [[TMP122]], align 8
5629 // CHECK17-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3
5630 // CHECK17-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to float**
5631 // CHECK17-NEXT: store float* [[VLA]], float** [[TMP124]], align 8
5632 // CHECK17-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3
5633 // CHECK17-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to float**
5634 // CHECK17-NEXT: store float* [[VLA]], float** [[TMP126]], align 8
5635 // CHECK17-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
5636 // CHECK17-NEXT: store i64 [[TMP104]], i64* [[TMP127]], align 8
5637 // CHECK17-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 3
5638 // CHECK17-NEXT: store i8* null, i8** [[TMP128]], align 8
5639 // CHECK17-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 4
5640 // CHECK17-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to [5 x [10 x double]]**
5641 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP130]], align 8
5642 // CHECK17-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 4
5643 // CHECK17-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to [5 x [10 x double]]**
5644 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP132]], align 8
5645 // CHECK17-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 4
5646 // CHECK17-NEXT: store i8* null, i8** [[TMP133]], align 8
5647 // CHECK17-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 5
5648 // CHECK17-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i64*
5649 // CHECK17-NEXT: store i64 5, i64* [[TMP135]], align 8
5650 // CHECK17-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 5
5651 // CHECK17-NEXT: [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i64*
5652 // CHECK17-NEXT: store i64 5, i64* [[TMP137]], align 8
5653 // CHECK17-NEXT: [[TMP138:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 5
5654 // CHECK17-NEXT: store i8* null, i8** [[TMP138]], align 8
5655 // CHECK17-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 6
5656 // CHECK17-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to i64*
5657 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP140]], align 8
5658 // CHECK17-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 6
5659 // CHECK17-NEXT: [[TMP142:%.*]] = bitcast i8** [[TMP141]] to i64*
5660 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP142]], align 8
5661 // CHECK17-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 6
5662 // CHECK17-NEXT: store i8* null, i8** [[TMP143]], align 8
5663 // CHECK17-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 7
5664 // CHECK17-NEXT: [[TMP145:%.*]] = bitcast i8** [[TMP144]] to double**
5665 // CHECK17-NEXT: store double* [[VLA1]], double** [[TMP145]], align 8
5666 // CHECK17-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 7
5667 // CHECK17-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to double**
5668 // CHECK17-NEXT: store double* [[VLA1]], double** [[TMP147]], align 8
5669 // CHECK17-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
5670 // CHECK17-NEXT: store i64 [[TMP106]], i64* [[TMP148]], align 8
5671 // CHECK17-NEXT: [[TMP149:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 7
5672 // CHECK17-NEXT: store i8* null, i8** [[TMP149]], align 8
5673 // CHECK17-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 8
5674 // CHECK17-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to %struct.TT**
5675 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP151]], align 8
5676 // CHECK17-NEXT: [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 8
5677 // CHECK17-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to %struct.TT**
5678 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP153]], align 8
5679 // CHECK17-NEXT: [[TMP154:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 8
5680 // CHECK17-NEXT: store i8* null, i8** [[TMP154]], align 8
5681 // CHECK17-NEXT: [[TMP155:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 9
5682 // CHECK17-NEXT: [[TMP156:%.*]] = bitcast i8** [[TMP155]] to i64*
5683 // CHECK17-NEXT: store i64 [[TMP102]], i64* [[TMP156]], align 8
5684 // CHECK17-NEXT: [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 9
5685 // CHECK17-NEXT: [[TMP158:%.*]] = bitcast i8** [[TMP157]] to i64*
5686 // CHECK17-NEXT: store i64 [[TMP102]], i64* [[TMP158]], align 8
5687 // CHECK17-NEXT: [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 9
5688 // CHECK17-NEXT: store i8* null, i8** [[TMP159]], align 8
5689 // CHECK17-NEXT: [[TMP160:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0
5690 // CHECK17-NEXT: [[TMP161:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0
5691 // CHECK17-NEXT: [[TMP162:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
5692 // CHECK17-NEXT: [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
5693 // CHECK17-NEXT: [[TMP163:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 0
5694 // CHECK17-NEXT: store i32 1, i32* [[TMP163]], align 4
5695 // CHECK17-NEXT: [[TMP164:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 1
5696 // CHECK17-NEXT: store i32 10, i32* [[TMP164]], align 4
5697 // CHECK17-NEXT: [[TMP165:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 2
5698 // CHECK17-NEXT: store i8** [[TMP160]], i8*** [[TMP165]], align 8
5699 // CHECK17-NEXT: [[TMP166:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 3
5700 // CHECK17-NEXT: store i8** [[TMP161]], i8*** [[TMP166]], align 8
5701 // CHECK17-NEXT: [[TMP167:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 4
5702 // CHECK17-NEXT: store i64* [[TMP162]], i64** [[TMP167]], align 8
5703 // CHECK17-NEXT: [[TMP168:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 5
5704 // CHECK17-NEXT: store i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i64** [[TMP168]], align 8
5705 // CHECK17-NEXT: [[TMP169:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 6
5706 // CHECK17-NEXT: store i8** null, i8*** [[TMP169]], align 8
5707 // CHECK17-NEXT: [[TMP170:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 7
5708 // CHECK17-NEXT: store i8** null, i8*** [[TMP170]], align 8
5709 // CHECK17-NEXT: [[TMP171:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 8
5710 // CHECK17-NEXT: store i64 0, i64* [[TMP171]], align 8
5711 // CHECK17-NEXT: [[TMP172:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]])
5712 // CHECK17-NEXT: [[TMP173:%.*]] = icmp ne i32 [[TMP172]], 0
5713 // CHECK17-NEXT: br i1 [[TMP173]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]]
5714 // CHECK17: omp_offload.failed25:
5715 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP100]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP102]]) #[[ATTR4]]
5716 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT26]]
5717 // CHECK17: omp_offload.cont26:
5718 // CHECK17-NEXT: br label [[OMP_IF_END28:%.*]]
5719 // CHECK17: omp_if.else27:
5720 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP100]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP102]]) #[[ATTR4]]
5721 // CHECK17-NEXT: br label [[OMP_IF_END28]]
5722 // CHECK17: omp_if.end28:
5723 // CHECK17-NEXT: [[TMP174:%.*]] = load i32, i32* [[A]], align 4
5724 // CHECK17-NEXT: [[TMP175:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
5725 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP175]])
5726 // CHECK17-NEXT: ret i32 [[TMP174]]
5727 //
5728 //
5729 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
5730 // CHECK17-SAME: () #[[ATTR2:[0-9]+]] {
5731 // CHECK17-NEXT: entry:
5732 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
5733 // CHECK17-NEXT: ret void
5734 //
5735 //
5736 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
5737 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
5738 // CHECK17-NEXT: entry:
5739 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5740 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5741 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5742 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
5743 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5744 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5745 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5746 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5747 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4
5748 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5749 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5750 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5751 // CHECK17-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
5752 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5753 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5754 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5755 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
5756 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5757 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5758 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
5759 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5760 // CHECK17: cond.true:
5761 // CHECK17-NEXT: br label [[COND_END:%.*]]
5762 // CHECK17: cond.false:
5763 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5764 // CHECK17-NEXT: br label [[COND_END]]
5765 // CHECK17: cond.end:
5766 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
5767 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5768 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5769 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
5770 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5771 // CHECK17: omp.inner.for.cond:
5772 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5773 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5774 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
5775 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5776 // CHECK17: omp.inner.for.body:
5777 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5778 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
5779 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
5780 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4
5781 // CHECK17-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
5782 // CHECK17-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
5783 // CHECK17-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
5784 // CHECK17: .cancel.exit:
5785 // CHECK17-NEXT: br label [[CANCEL_EXIT:%.*]]
5786 // CHECK17: .cancel.continue:
5787 // CHECK17-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
5788 // CHECK17-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
5789 // CHECK17-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
5790 // CHECK17: .cancel.exit2:
5791 // CHECK17-NEXT: br label [[CANCEL_EXIT]]
5792 // CHECK17: .cancel.continue3:
5793 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5794 // CHECK17: omp.body.continue:
5795 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5796 // CHECK17: omp.inner.for.inc:
5797 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5798 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
5799 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
5800 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
5801 // CHECK17: omp.inner.for.end:
5802 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5803 // CHECK17: omp.loop.exit:
5804 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
5805 // CHECK17-NEXT: br label [[CANCEL_CONT:%.*]]
5806 // CHECK17: cancel.cont:
5807 // CHECK17-NEXT: ret void
5808 // CHECK17: cancel.exit:
5809 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
5810 // CHECK17-NEXT: br label [[CANCEL_CONT]]
5811 //
5812 //
5813 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
5814 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] {
5815 // CHECK17-NEXT: entry:
5816 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
5817 // CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
5818 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
5819 // CHECK17-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
5820 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
5821 // CHECK17-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
5822 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5823 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
5824 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
5825 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
5826 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
5827 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
5828 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8
5829 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
5830 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
5831 // CHECK17-NEXT: ret void
5832 //
5833 //
5834 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1
5835 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] {
5836 // CHECK17-NEXT: entry:
5837 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5838 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5839 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
5840 // CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
5841 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5842 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
5843 // CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
5844 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5845 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5846 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5847 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5848 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4
5849 // CHECK17-NEXT: [[K1:%.*]] = alloca i64, align 8
5850 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5851 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5852 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
5853 // CHECK17-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
5854 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5855 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8
5856 // CHECK17-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8
5857 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5858 // CHECK17-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
5859 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5860 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5861 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5862 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
5863 // CHECK17-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]])
5864 // CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
5865 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
5866 // CHECK17: omp.dispatch.cond:
5867 // CHECK17-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
5868 // CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
5869 // CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
5870 // CHECK17: omp.dispatch.body:
5871 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5872 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
5873 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5874 // CHECK17: omp.inner.for.cond:
5875 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
5876 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]
5877 // CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
5878 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5879 // CHECK17: omp.inner.for.body:
5880 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
5881 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
5882 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
5883 // CHECK17-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
5884 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP12]]
5885 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
5886 // CHECK17-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
5887 // CHECK17-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
5888 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
5889 // CHECK17-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group [[ACC_GRP12]]
5890 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP12]]
5891 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
5892 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP12]]
5893 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5894 // CHECK17: omp.body.continue:
5895 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5896 // CHECK17: omp.inner.for.inc:
5897 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
5898 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
5899 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
5900 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
5901 // CHECK17: omp.inner.for.end:
5902 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
5903 // CHECK17: omp.dispatch.inc:
5904 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
5905 // CHECK17: omp.dispatch.end:
5906 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5907 // CHECK17-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
5908 // CHECK17-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
5909 // CHECK17: .omp.linear.pu:
5910 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[K1]], align 8
5911 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[K_ADDR]], align 8
5912 // CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
5913 // CHECK17: .omp.linear.pu.done:
5914 // CHECK17-NEXT: ret void
5915 //
5916 //
5917 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
5918 // CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {
5919 // CHECK17-NEXT: entry:
5920 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
5921 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
5922 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
5923 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
5924 // CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
5925 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
5926 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
5927 // CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
5928 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
5929 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5930 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
5931 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5932 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
5933 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
5934 // CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
5935 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
5936 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
5937 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
5938 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
5939 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
5940 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
5941 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
5942 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
5943 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
5944 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
5945 // CHECK17-NEXT: ret void
5946 //
5947 //
5948 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
5949 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {
5950 // CHECK17-NEXT: entry:
5951 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5952 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5953 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
5954 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
5955 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
5956 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
5957 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8
5958 // CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
5959 // CHECK17-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
5960 // CHECK17-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
5961 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
5962 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
5963 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
5964 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5965 // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8
5966 // CHECK17-NEXT: [[LIN4:%.*]] = alloca i32, align 4
5967 // CHECK17-NEXT: [[A5:%.*]] = alloca i32, align 4
5968 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5969 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5970 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
5971 // CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
5972 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
5973 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5974 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
5975 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5976 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
5977 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
5978 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
5979 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
5980 // CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
5981 // CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
5982 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
5983 // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
5984 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
5985 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5986 // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5987 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
5988 // CHECK17-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
5989 // CHECK17-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
5990 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5991 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
5992 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5993 // CHECK17: cond.true:
5994 // CHECK17-NEXT: br label [[COND_END:%.*]]
5995 // CHECK17: cond.false:
5996 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5997 // CHECK17-NEXT: br label [[COND_END]]
5998 // CHECK17: cond.end:
5999 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
6000 // CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
6001 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
6002 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
6003 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6004 // CHECK17: omp.inner.for.cond:
6005 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
6006 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
6007 // CHECK17-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
6008 // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6009 // CHECK17: omp.inner.for.body:
6010 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
6011 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
6012 // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
6013 // CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
6014 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
6015 // CHECK17-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
6016 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
6017 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
6018 // CHECK17-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
6019 // CHECK17-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
6020 // CHECK17-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
6021 // CHECK17-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4
6022 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
6023 // CHECK17-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
6024 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
6025 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
6026 // CHECK17-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
6027 // CHECK17-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
6028 // CHECK17-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
6029 // CHECK17-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
6030 // CHECK17-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
6031 // CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
6032 // CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
6033 // CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
6034 // CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
6035 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6036 // CHECK17: omp.body.continue:
6037 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6038 // CHECK17: omp.inner.for.inc:
6039 // CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
6040 // CHECK17-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
6041 // CHECK17-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
6042 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
6043 // CHECK17: omp.inner.for.end:
6044 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6045 // CHECK17: omp.loop.exit:
6046 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
6047 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6048 // CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
6049 // CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
6050 // CHECK17: .omp.linear.pu:
6051 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
6052 // CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
6053 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
6054 // CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
6055 // CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
6056 // CHECK17: .omp.linear.pu.done:
6057 // CHECK17-NEXT: ret void
6058 //
6059 //
6060 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map.
6061 // CHECK17-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
6062 // CHECK17-NEXT: entry:
6063 // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
6064 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8
6065 // CHECK17-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
6066 // CHECK17-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
6067 // CHECK17-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
6068 // CHECK17-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
6069 // CHECK17-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
6070 // CHECK17-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
6071 // CHECK17-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
6072 // CHECK17-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
6073 // CHECK17-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
6074 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
6075 // CHECK17-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
6076 // CHECK17-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
6077 // CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
6078 // CHECK17-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
6079 // CHECK17-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
6080 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
6081 // CHECK17-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
6082 // CHECK17-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
6083 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
6084 // CHECK17-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
6085 // CHECK17-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8
6086 // CHECK17-NEXT: ret void
6087 //
6088 //
6089 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry.
6090 // CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
6091 // CHECK17-NEXT: entry:
6092 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
6093 // CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
6094 // CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
6095 // CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
6096 // CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
6097 // CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
6098 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
6099 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
6100 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
6101 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
6102 // CHECK17-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8
6103 // CHECK17-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8
6104 // CHECK17-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8
6105 // CHECK17-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
6106 // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
6107 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
6108 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
6109 // CHECK17-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
6110 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
6111 // CHECK17-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
6112 // CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
6113 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
6114 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
6115 // CHECK17-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
6116 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
6117 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
6118 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
6119 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
6120 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
6121 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
6122 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
6123 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
6124 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
6125 // CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
6126 // CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
6127 // CHECK17-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
6128 // CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
6129 // CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
6130 // CHECK17-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
6131 // CHECK17-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
6132 // CHECK17-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
6133 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
6134 // CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
6135 // CHECK17-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
6136 // CHECK17-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
6137 // CHECK17-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
6138 // CHECK17-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
6139 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
6140 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
6141 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
6142 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
6143 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
6144 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 0
6145 // CHECK17-NEXT: store i32 1, i32* [[TMP25]], align 4, !noalias !24
6146 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 1
6147 // CHECK17-NEXT: store i32 3, i32* [[TMP26]], align 4, !noalias !24
6148 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 2
6149 // CHECK17-NEXT: store i8** [[TMP20]], i8*** [[TMP27]], align 8, !noalias !24
6150 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 3
6151 // CHECK17-NEXT: store i8** [[TMP21]], i8*** [[TMP28]], align 8, !noalias !24
6152 // CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 4
6153 // CHECK17-NEXT: store i64* [[TMP22]], i64** [[TMP29]], align 8, !noalias !24
6154 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 5
6155 // CHECK17-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP30]], align 8, !noalias !24
6156 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 6
6157 // CHECK17-NEXT: store i8** null, i8*** [[TMP31]], align 8, !noalias !24
6158 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 7
6159 // CHECK17-NEXT: store i8** null, i8*** [[TMP32]], align 8, !noalias !24
6160 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 8
6161 // CHECK17-NEXT: store i64 0, i64* [[TMP33]], align 8, !noalias !24
6162 // CHECK17-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel_nowait(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i8* null, i32 0, i8* null)
6163 // CHECK17-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
6164 // CHECK17-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
6165 // CHECK17: omp_offload.failed.i:
6166 // CHECK17-NEXT: [[TMP36:%.*]] = load i16, i16* [[TMP16]], align 2
6167 // CHECK17-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
6168 // CHECK17-NEXT: store i16 [[TMP36]], i16* [[CONV_I]], align 2, !noalias !24
6169 // CHECK17-NEXT: [[TMP37:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24
6170 // CHECK17-NEXT: [[TMP38:%.*]] = load i32, i32* [[TMP23]], align 4
6171 // CHECK17-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32*
6172 // CHECK17-NEXT: store i32 [[TMP38]], i32* [[CONV4_I]], align 4, !noalias !24
6173 // CHECK17-NEXT: [[TMP39:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !24
6174 // CHECK17-NEXT: [[TMP40:%.*]] = load i32, i32* [[TMP24]], align 4
6175 // CHECK17-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32*
6176 // CHECK17-NEXT: store i32 [[TMP40]], i32* [[CONV5_I]], align 4, !noalias !24
6177 // CHECK17-NEXT: [[TMP41:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !24
6178 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP37]], i64 [[TMP39]], i64 [[TMP41]]) #[[ATTR4]]
6179 // CHECK17-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
6180 // CHECK17: .omp_outlined..3.exit:
6181 // CHECK17-NEXT: ret i32 0
6182 //
6183 //
6184 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
6185 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
6186 // CHECK17-NEXT: entry:
6187 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6188 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
6189 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
6190 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
6191 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
6192 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
6193 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6194 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6195 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
6196 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
6197 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
6198 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
6199 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
6200 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
6201 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
6202 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
6203 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
6204 // CHECK17-NEXT: ret void
6205 //
6206 //
6207 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
6208 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
6209 // CHECK17-NEXT: entry:
6210 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6211 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6212 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6213 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
6214 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6215 // CHECK17-NEXT: [[TMP:%.*]] = alloca i16, align 2
6216 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6217 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6218 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6219 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6220 // CHECK17-NEXT: [[IT:%.*]] = alloca i16, align 2
6221 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6222 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6223 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
6224 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
6225 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6226 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6227 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6228 // CHECK17-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
6229 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6230 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6231 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
6232 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
6233 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6234 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6235 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
6236 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6237 // CHECK17: cond.true:
6238 // CHECK17-NEXT: br label [[COND_END:%.*]]
6239 // CHECK17: cond.false:
6240 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6241 // CHECK17-NEXT: br label [[COND_END]]
6242 // CHECK17: cond.end:
6243 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
6244 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6245 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6246 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
6247 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6248 // CHECK17: omp.inner.for.cond:
6249 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6250 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6251 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
6252 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6253 // CHECK17: omp.inner.for.body:
6254 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6255 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
6256 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
6257 // CHECK17-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
6258 // CHECK17-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
6259 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
6260 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
6261 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
6262 // CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
6263 // CHECK17-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
6264 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
6265 // CHECK17-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
6266 // CHECK17-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
6267 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6268 // CHECK17: omp.body.continue:
6269 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6270 // CHECK17: omp.inner.for.inc:
6271 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6272 // CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
6273 // CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
6274 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
6275 // CHECK17: omp.inner.for.end:
6276 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6277 // CHECK17: omp.loop.exit:
6278 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
6279 // CHECK17-NEXT: ret void
6280 //
6281 //
6282 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
6283 // CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
6284 // CHECK17-NEXT: entry:
6285 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6286 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
6287 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
6288 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
6289 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
6290 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
6291 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
6292 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
6293 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
6294 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
6295 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
6296 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
6297 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
6298 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
6299 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
6300 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
6301 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
6302 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
6303 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
6304 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
6305 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
6306 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
6307 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6308 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
6309 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
6310 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
6311 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
6312 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
6313 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
6314 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
6315 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
6316 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
6317 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
6318 // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
6319 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
6320 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
6321 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
6322 // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
6323 // CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
6324 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
6325 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
6326 // CHECK17-NEXT: ret void
6327 //
6328 //
6329 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7
6330 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
6331 // CHECK17-NEXT: entry:
6332 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6333 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6334 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6335 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
6336 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
6337 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
6338 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
6339 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
6340 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
6341 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
6342 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
6343 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
6344 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6345 // CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1
6346 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6347 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6348 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6349 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6350 // CHECK17-NEXT: [[IT:%.*]] = alloca i8, align 1
6351 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6352 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6353 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
6354 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
6355 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
6356 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
6357 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
6358 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
6359 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
6360 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
6361 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
6362 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
6363 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6364 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
6365 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
6366 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
6367 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
6368 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
6369 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
6370 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
6371 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
6372 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
6373 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6374 // CHECK17-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
6375 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6376 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6377 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
6378 // CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
6379 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
6380 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
6381 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
6382 // CHECK17: omp.dispatch.cond:
6383 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6384 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
6385 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6386 // CHECK17: cond.true:
6387 // CHECK17-NEXT: br label [[COND_END:%.*]]
6388 // CHECK17: cond.false:
6389 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6390 // CHECK17-NEXT: br label [[COND_END]]
6391 // CHECK17: cond.end:
6392 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
6393 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6394 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6395 // CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
6396 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6397 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6398 // CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
6399 // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
6400 // CHECK17: omp.dispatch.body:
6401 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6402 // CHECK17: omp.inner.for.cond:
6403 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6404 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6405 // CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
6406 // CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6407 // CHECK17: omp.inner.for.body:
6408 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6409 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
6410 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
6411 // CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
6412 // CHECK17-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
6413 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
6414 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
6415 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
6416 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
6417 // CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
6418 // CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
6419 // CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
6420 // CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
6421 // CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
6422 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
6423 // CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
6424 // CHECK17-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
6425 // CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
6426 // CHECK17-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
6427 // CHECK17-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4
6428 // CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
6429 // CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
6430 // CHECK17-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
6431 // CHECK17-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
6432 // CHECK17-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8
6433 // CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
6434 // CHECK17-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
6435 // CHECK17-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
6436 // CHECK17-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
6437 // CHECK17-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
6438 // CHECK17-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8
6439 // CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
6440 // CHECK17-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8
6441 // CHECK17-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
6442 // CHECK17-NEXT: store i64 [[ADD22]], i64* [[X]], align 8
6443 // CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
6444 // CHECK17-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
6445 // CHECK17-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
6446 // CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
6447 // CHECK17-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
6448 // CHECK17-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8
6449 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6450 // CHECK17: omp.body.continue:
6451 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6452 // CHECK17: omp.inner.for.inc:
6453 // CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6454 // CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
6455 // CHECK17-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
6456 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
6457 // CHECK17: omp.inner.for.end:
6458 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
6459 // CHECK17: omp.dispatch.inc:
6460 // CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6461 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6462 // CHECK17-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
6463 // CHECK17-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
6464 // CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6465 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6466 // CHECK17-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
6467 // CHECK17-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
6468 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
6469 // CHECK17: omp.dispatch.end:
6470 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
6471 // CHECK17-NEXT: ret void
6472 //
6473 //
6474 // CHECK17-LABEL: define {{[^@]+}}@_Z3bari
6475 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
6476 // CHECK17-NEXT: entry:
6477 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
6478 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
6479 // CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
6480 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
6481 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4
6482 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6483 // CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
6484 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
6485 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
6486 // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4
6487 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
6488 // CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
6489 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
6490 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
6491 // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
6492 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
6493 // CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
6494 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
6495 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
6496 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
6497 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
6498 // CHECK17-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
6499 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
6500 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
6501 // CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
6502 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
6503 // CHECK17-NEXT: ret i32 [[TMP8]]
6504 //
6505 //
6506 // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
6507 // CHECK17-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
6508 // CHECK17-NEXT: entry:
6509 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
6510 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
6511 // CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4
6512 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
6513 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
6514 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
6515 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
6516 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
6517 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
6518 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
6519 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
6520 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
6521 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
6522 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6523 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6524 // CHECK17-NEXT: store i32 [[ADD]], i32* [[B]], align 4
6525 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
6526 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
6527 // CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
6528 // CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
6529 // CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
6530 // CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
6531 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
6532 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
6533 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
6534 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4
6535 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
6536 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
6537 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
6538 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6539 // CHECK17: omp_if.then:
6540 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
6541 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
6542 // CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
6543 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
6544 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false)
6545 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6546 // CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1**
6547 // CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8
6548 // CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6549 // CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double**
6550 // CHECK17-NEXT: store double* [[A]], double** [[TMP14]], align 8
6551 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
6552 // CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8
6553 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6554 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
6555 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8
6556 // CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6557 // CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
6558 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8
6559 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
6560 // CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8
6561 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6562 // CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
6563 // CHECK17-NEXT: store i64 2, i64* [[TMP22]], align 8
6564 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6565 // CHECK17-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
6566 // CHECK17-NEXT: store i64 2, i64* [[TMP24]], align 8
6567 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
6568 // CHECK17-NEXT: store i8* null, i8** [[TMP25]], align 8
6569 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
6570 // CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
6571 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8
6572 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
6573 // CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
6574 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8
6575 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
6576 // CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8
6577 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
6578 // CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16**
6579 // CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8
6580 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
6581 // CHECK17-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16**
6582 // CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8
6583 // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
6584 // CHECK17-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8
6585 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
6586 // CHECK17-NEXT: store i8* null, i8** [[TMP36]], align 8
6587 // CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6588 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6589 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
6590 // CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
6591 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
6592 // CHECK17-NEXT: store i32 1, i32* [[TMP40]], align 4
6593 // CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
6594 // CHECK17-NEXT: store i32 5, i32* [[TMP41]], align 4
6595 // CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
6596 // CHECK17-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 8
6597 // CHECK17-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
6598 // CHECK17-NEXT: store i8** [[TMP38]], i8*** [[TMP43]], align 8
6599 // CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
6600 // CHECK17-NEXT: store i64* [[TMP39]], i64** [[TMP44]], align 8
6601 // CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
6602 // CHECK17-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i64** [[TMP45]], align 8
6603 // CHECK17-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
6604 // CHECK17-NEXT: store i8** null, i8*** [[TMP46]], align 8
6605 // CHECK17-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
6606 // CHECK17-NEXT: store i8** null, i8*** [[TMP47]], align 8
6607 // CHECK17-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
6608 // CHECK17-NEXT: store i64 0, i64* [[TMP48]], align 8
6609 // CHECK17-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
6610 // CHECK17-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
6611 // CHECK17-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6612 // CHECK17: omp_offload.failed:
6613 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
6614 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
6615 // CHECK17: omp_offload.cont:
6616 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
6617 // CHECK17: omp_if.else:
6618 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
6619 // CHECK17-NEXT: br label [[OMP_IF_END]]
6620 // CHECK17: omp_if.end:
6621 // CHECK17-NEXT: [[TMP51:%.*]] = mul nsw i64 1, [[TMP2]]
6622 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP51]]
6623 // CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
6624 // CHECK17-NEXT: [[TMP52:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
6625 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP52]] to i32
6626 // CHECK17-NEXT: [[TMP53:%.*]] = load i32, i32* [[B]], align 4
6627 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP53]]
6628 // CHECK17-NEXT: [[TMP54:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
6629 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP54]])
6630 // CHECK17-NEXT: ret i32 [[ADD4]]
6631 //
6632 //
6633 // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici
6634 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
6635 // CHECK17-NEXT: entry:
6636 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
6637 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
6638 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2
6639 // CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1
6640 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
6641 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
6642 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
6643 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
6644 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
6645 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
6646 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
6647 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
6648 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4
6649 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2
6650 // CHECK17-NEXT: store i8 0, i8* [[AAA]], align 1
6651 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
6652 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
6653 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
6654 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
6655 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
6656 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
6657 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
6658 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
6659 // CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
6660 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
6661 // CHECK17-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1
6662 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
6663 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
6664 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
6665 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6666 // CHECK17: omp_if.then:
6667 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6668 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
6669 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
6670 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6671 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
6672 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8
6673 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
6674 // CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8
6675 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6676 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
6677 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
6678 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6679 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
6680 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8
6681 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
6682 // CHECK17-NEXT: store i8* null, i8** [[TMP16]], align 8
6683 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6684 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
6685 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8
6686 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6687 // CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
6688 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8
6689 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
6690 // CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8
6691 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
6692 // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
6693 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
6694 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
6695 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
6696 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
6697 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
6698 // CHECK17-NEXT: store i8* null, i8** [[TMP26]], align 8
6699 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6700 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6701 // CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
6702 // CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
6703 // CHECK17-NEXT: store i32 1, i32* [[TMP29]], align 4
6704 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
6705 // CHECK17-NEXT: store i32 4, i32* [[TMP30]], align 4
6706 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
6707 // CHECK17-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 8
6708 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
6709 // CHECK17-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 8
6710 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
6711 // CHECK17-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64** [[TMP33]], align 8
6712 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
6713 // CHECK17-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i64** [[TMP34]], align 8
6714 // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
6715 // CHECK17-NEXT: store i8** null, i8*** [[TMP35]], align 8
6716 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
6717 // CHECK17-NEXT: store i8** null, i8*** [[TMP36]], align 8
6718 // CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
6719 // CHECK17-NEXT: store i64 0, i64* [[TMP37]], align 8
6720 // CHECK17-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
6721 // CHECK17-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
6722 // CHECK17-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6723 // CHECK17: omp_offload.failed:
6724 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
6725 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
6726 // CHECK17: omp_offload.cont:
6727 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
6728 // CHECK17: omp_if.else:
6729 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
6730 // CHECK17-NEXT: br label [[OMP_IF_END]]
6731 // CHECK17: omp_if.end:
6732 // CHECK17-NEXT: [[TMP40:%.*]] = load i32, i32* [[A]], align 4
6733 // CHECK17-NEXT: ret i32 [[TMP40]]
6734 //
6735 //
6736 // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
6737 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
6738 // CHECK17-NEXT: entry:
6739 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
6740 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
6741 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2
6742 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
6743 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
6744 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
6745 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
6746 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
6747 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
6748 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
6749 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4
6750 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2
6751 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
6752 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
6753 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
6754 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
6755 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
6756 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
6757 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
6758 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
6759 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
6760 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
6761 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6762 // CHECK17: omp_if.then:
6763 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6764 // CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
6765 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8
6766 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6767 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
6768 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
6769 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
6770 // CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8
6771 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6772 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
6773 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
6774 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6775 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
6776 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
6777 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
6778 // CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8
6779 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6780 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
6781 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
6782 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6783 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
6784 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
6785 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
6786 // CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8
6787 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6788 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6789 // CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
6790 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
6791 // CHECK17-NEXT: store i32 1, i32* [[TMP22]], align 4
6792 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
6793 // CHECK17-NEXT: store i32 3, i32* [[TMP23]], align 4
6794 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
6795 // CHECK17-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 8
6796 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
6797 // CHECK17-NEXT: store i8** [[TMP21]], i8*** [[TMP25]], align 8
6798 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
6799 // CHECK17-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64** [[TMP26]], align 8
6800 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
6801 // CHECK17-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i64** [[TMP27]], align 8
6802 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
6803 // CHECK17-NEXT: store i8** null, i8*** [[TMP28]], align 8
6804 // CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
6805 // CHECK17-NEXT: store i8** null, i8*** [[TMP29]], align 8
6806 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
6807 // CHECK17-NEXT: store i64 0, i64* [[TMP30]], align 8
6808 // CHECK17-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
6809 // CHECK17-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
6810 // CHECK17-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6811 // CHECK17: omp_offload.failed:
6812 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
6813 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
6814 // CHECK17: omp_offload.cont:
6815 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
6816 // CHECK17: omp_if.else:
6817 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
6818 // CHECK17-NEXT: br label [[OMP_IF_END]]
6819 // CHECK17: omp_if.end:
6820 // CHECK17-NEXT: [[TMP33:%.*]] = load i32, i32* [[A]], align 4
6821 // CHECK17-NEXT: ret i32 [[TMP33]]
6822 //
6823 //
6824 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
6825 // CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
6826 // CHECK17-NEXT: entry:
6827 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
6828 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
6829 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
6830 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
6831 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
6832 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
6833 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
6834 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
6835 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
6836 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
6837 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
6838 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
6839 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
6840 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
6841 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
6842 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
6843 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
6844 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
6845 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
6846 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
6847 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
6848 // CHECK17-NEXT: ret void
6849 //
6850 //
6851 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10
6852 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
6853 // CHECK17-NEXT: entry:
6854 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6855 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6856 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
6857 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
6858 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
6859 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
6860 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
6861 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
6862 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8
6863 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
6864 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
6865 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
6866 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6867 // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8
6868 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6869 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6870 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
6871 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
6872 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
6873 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
6874 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
6875 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
6876 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
6877 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
6878 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
6879 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
6880 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
6881 // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
6882 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
6883 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6884 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
6885 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
6886 // CHECK17-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
6887 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
6888 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
6889 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6890 // CHECK17: cond.true:
6891 // CHECK17-NEXT: br label [[COND_END:%.*]]
6892 // CHECK17: cond.false:
6893 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
6894 // CHECK17-NEXT: br label [[COND_END]]
6895 // CHECK17: cond.end:
6896 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
6897 // CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
6898 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
6899 // CHECK17-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
6900 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6901 // CHECK17: omp.inner.for.cond:
6902 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
6903 // CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
6904 // CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
6905 // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6906 // CHECK17: omp.inner.for.body:
6907 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
6908 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
6909 // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
6910 // CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
6911 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
6912 // CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
6913 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
6914 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
6915 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8
6916 // CHECK17-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
6917 // CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
6918 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
6919 // CHECK17-NEXT: store double [[INC]], double* [[A5]], align 8
6920 // CHECK17-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
6921 // CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
6922 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
6923 // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
6924 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
6925 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6926 // CHECK17: omp.body.continue:
6927 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6928 // CHECK17: omp.inner.for.inc:
6929 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
6930 // CHECK17-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1
6931 // CHECK17-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
6932 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
6933 // CHECK17: omp.inner.for.end:
6934 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6935 // CHECK17: omp.loop.exit:
6936 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
6937 // CHECK17-NEXT: ret void
6938 //
6939 //
6940 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
6941 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
6942 // CHECK17-NEXT: entry:
6943 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6944 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
6945 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
6946 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
6947 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
6948 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
6949 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
6950 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
6951 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
6952 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
6953 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
6954 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6955 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6956 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
6957 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
6958 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
6959 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
6960 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
6961 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
6962 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
6963 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
6964 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
6965 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
6966 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
6967 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
6968 // CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
6969 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
6970 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
6971 // CHECK17-NEXT: ret void
6972 //
6973 //
6974 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..13
6975 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
6976 // CHECK17-NEXT: entry:
6977 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6978 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6979 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6980 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
6981 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
6982 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
6983 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6984 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
6985 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6986 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6987 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
6988 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
6989 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
6990 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
6991 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6992 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6993 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
6994 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
6995 // CHECK17-NEXT: ret void
6996 //
6997 //
6998 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
6999 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
7000 // CHECK17-NEXT: entry:
7001 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
7002 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
7003 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
7004 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
7005 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
7006 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
7007 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
7008 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
7009 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
7010 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
7011 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
7012 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
7013 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
7014 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
7015 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
7016 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
7017 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
7018 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
7019 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
7020 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
7021 // CHECK17-NEXT: ret void
7022 //
7023 //
7024 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..16
7025 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
7026 // CHECK17-NEXT: entry:
7027 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
7028 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
7029 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
7030 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
7031 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
7032 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
7033 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8
7034 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
7035 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
7036 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
7037 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7038 // CHECK17-NEXT: [[I:%.*]] = alloca i64, align 8
7039 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
7040 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
7041 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
7042 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
7043 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
7044 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
7045 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
7046 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
7047 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
7048 // CHECK17-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
7049 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
7050 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7051 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
7052 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
7053 // CHECK17-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
7054 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
7055 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
7056 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7057 // CHECK17: cond.true:
7058 // CHECK17-NEXT: br label [[COND_END:%.*]]
7059 // CHECK17: cond.false:
7060 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
7061 // CHECK17-NEXT: br label [[COND_END]]
7062 // CHECK17: cond.end:
7063 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
7064 // CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
7065 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
7066 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
7067 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7068 // CHECK17: omp.inner.for.cond:
7069 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
7070 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
7071 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
7072 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7073 // CHECK17: omp.inner.for.body:
7074 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
7075 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
7076 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
7077 // CHECK17-NEXT: store i64 [[ADD]], i64* [[I]], align 8
7078 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
7079 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
7080 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
7081 // CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
7082 // CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
7083 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
7084 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
7085 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
7086 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
7087 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7088 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
7089 // CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
7090 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7091 // CHECK17: omp.body.continue:
7092 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7093 // CHECK17: omp.inner.for.inc:
7094 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
7095 // CHECK17-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
7096 // CHECK17-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
7097 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
7098 // CHECK17: omp.inner.for.end:
7099 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
7100 // CHECK17: omp.loop.exit:
7101 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
7102 // CHECK17-NEXT: ret void
7103 //
7104 //
7105 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
7106 // CHECK17-SAME: () #[[ATTR6]] {
7107 // CHECK17-NEXT: entry:
7108 // CHECK17-NEXT: call void @__tgt_register_requires(i64 1)
7109 // CHECK17-NEXT: ret void
7110 //
7111 //
7112 // CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv
7113 // CHECK19-SAME: () #[[ATTR0:[0-9]+]] {
7114 // CHECK19-NEXT: entry:
7115 // CHECK19-NEXT: ret i64 0
7116 //
7117 //
7118 // CHECK19-LABEL: define {{[^@]+}}@_Z3fooi
7119 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
7120 // CHECK19-NEXT: entry:
7121 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
7122 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
7123 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2
7124 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 4
7125 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
7126 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
7127 // CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
7128 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
7129 // CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
7130 // CHECK19-NEXT: [[K:%.*]] = alloca i64, align 8
7131 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
7132 // CHECK19-NEXT: [[LIN:%.*]] = alloca i32, align 4
7133 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
7134 // CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
7135 // CHECK19-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4
7136 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
7137 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
7138 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
7139 // CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
7140 // CHECK19-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4
7141 // CHECK19-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4
7142 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4
7143 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4
7144 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4
7145 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
7146 // CHECK19-NEXT: [[A_CASTED12:%.*]] = alloca i32, align 4
7147 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
7148 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS15:%.*]] = alloca [10 x i8*], align 4
7149 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS16:%.*]] = alloca [10 x i8*], align 4
7150 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS17:%.*]] = alloca [10 x i8*], align 4
7151 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
7152 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
7153 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
7154 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4
7155 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2
7156 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
7157 // CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
7158 // CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
7159 // CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
7160 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
7161 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
7162 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
7163 // CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
7164 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
7165 // CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
7166 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
7167 // CHECK19-NEXT: store i32 1, i32* [[TMP5]], align 4
7168 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
7169 // CHECK19-NEXT: store i32 0, i32* [[TMP6]], align 4
7170 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
7171 // CHECK19-NEXT: store i8** null, i8*** [[TMP7]], align 4
7172 // CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
7173 // CHECK19-NEXT: store i8** null, i8*** [[TMP8]], align 4
7174 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
7175 // CHECK19-NEXT: store i64* null, i64** [[TMP9]], align 4
7176 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
7177 // CHECK19-NEXT: store i64* null, i64** [[TMP10]], align 4
7178 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
7179 // CHECK19-NEXT: store i8** null, i8*** [[TMP11]], align 4
7180 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
7181 // CHECK19-NEXT: store i8** null, i8*** [[TMP12]], align 4
7182 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
7183 // CHECK19-NEXT: store i64 0, i64* [[TMP13]], align 8
7184 // CHECK19-NEXT: [[TMP14:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
7185 // CHECK19-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
7186 // CHECK19-NEXT: br i1 [[TMP15]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
7187 // CHECK19: omp_offload.failed:
7188 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]]
7189 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
7190 // CHECK19: omp_offload.cont:
7191 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
7192 // CHECK19-NEXT: store i64 [[CALL]], i64* [[K]], align 8
7193 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4
7194 // CHECK19-NEXT: store i32 [[TMP16]], i32* [[A_CASTED]], align 4
7195 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[A_CASTED]], align 4
7196 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP17]], i64* [[K]]) #[[ATTR4]]
7197 // CHECK19-NEXT: store i32 12, i32* [[LIN]], align 4
7198 // CHECK19-NEXT: [[TMP18:%.*]] = load i16, i16* [[AA]], align 2
7199 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
7200 // CHECK19-NEXT: store i16 [[TMP18]], i16* [[CONV]], align 2
7201 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[AA_CASTED]], align 4
7202 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4
7203 // CHECK19-NEXT: store i32 [[TMP20]], i32* [[LIN_CASTED]], align 4
7204 // CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
7205 // CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4
7206 // CHECK19-NEXT: store i32 [[TMP22]], i32* [[A_CASTED2]], align 4
7207 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4
7208 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7209 // CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
7210 // CHECK19-NEXT: store i32 [[TMP19]], i32* [[TMP25]], align 4
7211 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7212 // CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
7213 // CHECK19-NEXT: store i32 [[TMP19]], i32* [[TMP27]], align 4
7214 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
7215 // CHECK19-NEXT: store i8* null, i8** [[TMP28]], align 4
7216 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
7217 // CHECK19-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
7218 // CHECK19-NEXT: store i32 [[TMP21]], i32* [[TMP30]], align 4
7219 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
7220 // CHECK19-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
7221 // CHECK19-NEXT: store i32 [[TMP21]], i32* [[TMP32]], align 4
7222 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
7223 // CHECK19-NEXT: store i8* null, i8** [[TMP33]], align 4
7224 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
7225 // CHECK19-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32*
7226 // CHECK19-NEXT: store i32 [[TMP23]], i32* [[TMP35]], align 4
7227 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
7228 // CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32*
7229 // CHECK19-NEXT: store i32 [[TMP23]], i32* [[TMP37]], align 4
7230 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
7231 // CHECK19-NEXT: store i8* null, i8** [[TMP38]], align 4
7232 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7233 // CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7234 // CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
7235 // CHECK19-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2
7236 // CHECK19-NEXT: store i16 [[TMP42]], i16* [[TMP41]], align 4
7237 // CHECK19-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
7238 // CHECK19-NEXT: [[TMP44:%.*]] = load i32, i32* [[LIN]], align 4
7239 // CHECK19-NEXT: store i32 [[TMP44]], i32* [[TMP43]], align 4
7240 // CHECK19-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
7241 // CHECK19-NEXT: [[TMP46:%.*]] = load i32, i32* [[A]], align 4
7242 // CHECK19-NEXT: store i32 [[TMP46]], i32* [[TMP45]], align 4
7243 // CHECK19-NEXT: [[TMP47:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
7244 // CHECK19-NEXT: [[TMP48:%.*]] = bitcast i8* [[TMP47]] to %struct.kmp_task_t_with_privates*
7245 // CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP48]], i32 0, i32 0
7246 // CHECK19-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP49]], i32 0, i32 0
7247 // CHECK19-NEXT: [[TMP51:%.*]] = load i8*, i8** [[TMP50]], align 4
7248 // CHECK19-NEXT: [[TMP52:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
7249 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP51]], i8* align 4 [[TMP52]], i32 12, i1 false)
7250 // CHECK19-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP48]], i32 0, i32 1
7251 // CHECK19-NEXT: [[TMP54:%.*]] = bitcast i8* [[TMP51]] to %struct.anon*
7252 // CHECK19-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP53]], i32 0, i32 0
7253 // CHECK19-NEXT: [[TMP56:%.*]] = bitcast [3 x i64]* [[TMP55]] to i8*
7254 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP56]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
7255 // CHECK19-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP53]], i32 0, i32 1
7256 // CHECK19-NEXT: [[TMP58:%.*]] = bitcast [3 x i8*]* [[TMP57]] to i8*
7257 // CHECK19-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP39]] to i8*
7258 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP58]], i8* align 4 [[TMP59]], i32 12, i1 false)
7259 // CHECK19-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP53]], i32 0, i32 2
7260 // CHECK19-NEXT: [[TMP61:%.*]] = bitcast [3 x i8*]* [[TMP60]] to i8*
7261 // CHECK19-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP40]] to i8*
7262 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP61]], i8* align 4 [[TMP62]], i32 12, i1 false)
7263 // CHECK19-NEXT: [[TMP63:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP53]], i32 0, i32 3
7264 // CHECK19-NEXT: [[TMP64:%.*]] = load i16, i16* [[AA]], align 2
7265 // CHECK19-NEXT: store i16 [[TMP64]], i16* [[TMP63]], align 4
7266 // CHECK19-NEXT: [[TMP65:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP47]])
7267 // CHECK19-NEXT: [[TMP66:%.*]] = load i32, i32* [[A]], align 4
7268 // CHECK19-NEXT: store i32 [[TMP66]], i32* [[A_CASTED3]], align 4
7269 // CHECK19-NEXT: [[TMP67:%.*]] = load i32, i32* [[A_CASTED3]], align 4
7270 // CHECK19-NEXT: [[TMP68:%.*]] = load i16, i16* [[AA]], align 2
7271 // CHECK19-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
7272 // CHECK19-NEXT: store i16 [[TMP68]], i16* [[CONV5]], align 2
7273 // CHECK19-NEXT: [[TMP69:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
7274 // CHECK19-NEXT: [[TMP70:%.*]] = load i32, i32* [[N_ADDR]], align 4
7275 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP70]], 10
7276 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7277 // CHECK19: omp_if.then:
7278 // CHECK19-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
7279 // CHECK19-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i32*
7280 // CHECK19-NEXT: store i32 [[TMP67]], i32* [[TMP72]], align 4
7281 // CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
7282 // CHECK19-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32*
7283 // CHECK19-NEXT: store i32 [[TMP67]], i32* [[TMP74]], align 4
7284 // CHECK19-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
7285 // CHECK19-NEXT: store i8* null, i8** [[TMP75]], align 4
7286 // CHECK19-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1
7287 // CHECK19-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32*
7288 // CHECK19-NEXT: store i32 [[TMP69]], i32* [[TMP77]], align 4
7289 // CHECK19-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1
7290 // CHECK19-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
7291 // CHECK19-NEXT: store i32 [[TMP69]], i32* [[TMP79]], align 4
7292 // CHECK19-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1
7293 // CHECK19-NEXT: store i8* null, i8** [[TMP80]], align 4
7294 // CHECK19-NEXT: [[TMP81:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
7295 // CHECK19-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
7296 // CHECK19-NEXT: [[KERNEL_ARGS9:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
7297 // CHECK19-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 0
7298 // CHECK19-NEXT: store i32 1, i32* [[TMP83]], align 4
7299 // CHECK19-NEXT: [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 1
7300 // CHECK19-NEXT: store i32 2, i32* [[TMP84]], align 4
7301 // CHECK19-NEXT: [[TMP85:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 2
7302 // CHECK19-NEXT: store i8** [[TMP81]], i8*** [[TMP85]], align 4
7303 // CHECK19-NEXT: [[TMP86:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 3
7304 // CHECK19-NEXT: store i8** [[TMP82]], i8*** [[TMP86]], align 4
7305 // CHECK19-NEXT: [[TMP87:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 4
7306 // CHECK19-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64** [[TMP87]], align 4
7307 // CHECK19-NEXT: [[TMP88:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 5
7308 // CHECK19-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP88]], align 4
7309 // CHECK19-NEXT: [[TMP89:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 6
7310 // CHECK19-NEXT: store i8** null, i8*** [[TMP89]], align 4
7311 // CHECK19-NEXT: [[TMP90:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 7
7312 // CHECK19-NEXT: store i8** null, i8*** [[TMP90]], align 4
7313 // CHECK19-NEXT: [[TMP91:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 8
7314 // CHECK19-NEXT: store i64 0, i64* [[TMP91]], align 8
7315 // CHECK19-NEXT: [[TMP92:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]])
7316 // CHECK19-NEXT: [[TMP93:%.*]] = icmp ne i32 [[TMP92]], 0
7317 // CHECK19-NEXT: br i1 [[TMP93]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]]
7318 // CHECK19: omp_offload.failed10:
7319 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP67]], i32 [[TMP69]]) #[[ATTR4]]
7320 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT11]]
7321 // CHECK19: omp_offload.cont11:
7322 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
7323 // CHECK19: omp_if.else:
7324 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP67]], i32 [[TMP69]]) #[[ATTR4]]
7325 // CHECK19-NEXT: br label [[OMP_IF_END]]
7326 // CHECK19: omp_if.end:
7327 // CHECK19-NEXT: [[TMP94:%.*]] = load i32, i32* [[A]], align 4
7328 // CHECK19-NEXT: store i32 [[TMP94]], i32* [[DOTCAPTURE_EXPR_]], align 4
7329 // CHECK19-NEXT: [[TMP95:%.*]] = load i32, i32* [[A]], align 4
7330 // CHECK19-NEXT: store i32 [[TMP95]], i32* [[A_CASTED12]], align 4
7331 // CHECK19-NEXT: [[TMP96:%.*]] = load i32, i32* [[A_CASTED12]], align 4
7332 // CHECK19-NEXT: [[TMP97:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
7333 // CHECK19-NEXT: store i32 [[TMP97]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
7334 // CHECK19-NEXT: [[TMP98:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
7335 // CHECK19-NEXT: [[TMP99:%.*]] = load i32, i32* [[N_ADDR]], align 4
7336 // CHECK19-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[TMP99]], 20
7337 // CHECK19-NEXT: br i1 [[CMP13]], label [[OMP_IF_THEN14:%.*]], label [[OMP_IF_ELSE21:%.*]]
7338 // CHECK19: omp_if.then14:
7339 // CHECK19-NEXT: [[TMP100:%.*]] = mul nuw i32 [[TMP1]], 4
7340 // CHECK19-NEXT: [[TMP101:%.*]] = sext i32 [[TMP100]] to i64
7341 // CHECK19-NEXT: [[TMP102:%.*]] = mul nuw i32 5, [[TMP3]]
7342 // CHECK19-NEXT: [[TMP103:%.*]] = mul nuw i32 [[TMP102]], 8
7343 // CHECK19-NEXT: [[TMP104:%.*]] = sext i32 [[TMP103]] to i64
7344 // CHECK19-NEXT: [[TMP105:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
7345 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP105]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i32 80, i1 false)
7346 // CHECK19-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 0
7347 // CHECK19-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i32*
7348 // CHECK19-NEXT: store i32 [[TMP96]], i32* [[TMP107]], align 4
7349 // CHECK19-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 0
7350 // CHECK19-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32*
7351 // CHECK19-NEXT: store i32 [[TMP96]], i32* [[TMP109]], align 4
7352 // CHECK19-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 0
7353 // CHECK19-NEXT: store i8* null, i8** [[TMP110]], align 4
7354 // CHECK19-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 1
7355 // CHECK19-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [10 x float]**
7356 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP112]], align 4
7357 // CHECK19-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 1
7358 // CHECK19-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [10 x float]**
7359 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP114]], align 4
7360 // CHECK19-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 1
7361 // CHECK19-NEXT: store i8* null, i8** [[TMP115]], align 4
7362 // CHECK19-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 2
7363 // CHECK19-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32*
7364 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP117]], align 4
7365 // CHECK19-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 2
7366 // CHECK19-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i32*
7367 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP119]], align 4
7368 // CHECK19-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 2
7369 // CHECK19-NEXT: store i8* null, i8** [[TMP120]], align 4
7370 // CHECK19-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 3
7371 // CHECK19-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to float**
7372 // CHECK19-NEXT: store float* [[VLA]], float** [[TMP122]], align 4
7373 // CHECK19-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 3
7374 // CHECK19-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to float**
7375 // CHECK19-NEXT: store float* [[VLA]], float** [[TMP124]], align 4
7376 // CHECK19-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
7377 // CHECK19-NEXT: store i64 [[TMP101]], i64* [[TMP125]], align 4
7378 // CHECK19-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 3
7379 // CHECK19-NEXT: store i8* null, i8** [[TMP126]], align 4
7380 // CHECK19-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 4
7381 // CHECK19-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to [5 x [10 x double]]**
7382 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP128]], align 4
7383 // CHECK19-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 4
7384 // CHECK19-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to [5 x [10 x double]]**
7385 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP130]], align 4
7386 // CHECK19-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 4
7387 // CHECK19-NEXT: store i8* null, i8** [[TMP131]], align 4
7388 // CHECK19-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 5
7389 // CHECK19-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to i32*
7390 // CHECK19-NEXT: store i32 5, i32* [[TMP133]], align 4
7391 // CHECK19-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 5
7392 // CHECK19-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i32*
7393 // CHECK19-NEXT: store i32 5, i32* [[TMP135]], align 4
7394 // CHECK19-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 5
7395 // CHECK19-NEXT: store i8* null, i8** [[TMP136]], align 4
7396 // CHECK19-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 6
7397 // CHECK19-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i32*
7398 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP138]], align 4
7399 // CHECK19-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 6
7400 // CHECK19-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to i32*
7401 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP140]], align 4
7402 // CHECK19-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 6
7403 // CHECK19-NEXT: store i8* null, i8** [[TMP141]], align 4
7404 // CHECK19-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 7
7405 // CHECK19-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to double**
7406 // CHECK19-NEXT: store double* [[VLA1]], double** [[TMP143]], align 4
7407 // CHECK19-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 7
7408 // CHECK19-NEXT: [[TMP145:%.*]] = bitcast i8** [[TMP144]] to double**
7409 // CHECK19-NEXT: store double* [[VLA1]], double** [[TMP145]], align 4
7410 // CHECK19-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
7411 // CHECK19-NEXT: store i64 [[TMP104]], i64* [[TMP146]], align 4
7412 // CHECK19-NEXT: [[TMP147:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 7
7413 // CHECK19-NEXT: store i8* null, i8** [[TMP147]], align 4
7414 // CHECK19-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 8
7415 // CHECK19-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to %struct.TT**
7416 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP149]], align 4
7417 // CHECK19-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 8
7418 // CHECK19-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to %struct.TT**
7419 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP151]], align 4
7420 // CHECK19-NEXT: [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 8
7421 // CHECK19-NEXT: store i8* null, i8** [[TMP152]], align 4
7422 // CHECK19-NEXT: [[TMP153:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 9
7423 // CHECK19-NEXT: [[TMP154:%.*]] = bitcast i8** [[TMP153]] to i32*
7424 // CHECK19-NEXT: store i32 [[TMP98]], i32* [[TMP154]], align 4
7425 // CHECK19-NEXT: [[TMP155:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 9
7426 // CHECK19-NEXT: [[TMP156:%.*]] = bitcast i8** [[TMP155]] to i32*
7427 // CHECK19-NEXT: store i32 [[TMP98]], i32* [[TMP156]], align 4
7428 // CHECK19-NEXT: [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 9
7429 // CHECK19-NEXT: store i8* null, i8** [[TMP157]], align 4
7430 // CHECK19-NEXT: [[TMP158:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 0
7431 // CHECK19-NEXT: [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 0
7432 // CHECK19-NEXT: [[TMP160:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
7433 // CHECK19-NEXT: [[KERNEL_ARGS18:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
7434 // CHECK19-NEXT: [[TMP161:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 0
7435 // CHECK19-NEXT: store i32 1, i32* [[TMP161]], align 4
7436 // CHECK19-NEXT: [[TMP162:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 1
7437 // CHECK19-NEXT: store i32 10, i32* [[TMP162]], align 4
7438 // CHECK19-NEXT: [[TMP163:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 2
7439 // CHECK19-NEXT: store i8** [[TMP158]], i8*** [[TMP163]], align 4
7440 // CHECK19-NEXT: [[TMP164:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 3
7441 // CHECK19-NEXT: store i8** [[TMP159]], i8*** [[TMP164]], align 4
7442 // CHECK19-NEXT: [[TMP165:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 4
7443 // CHECK19-NEXT: store i64* [[TMP160]], i64** [[TMP165]], align 4
7444 // CHECK19-NEXT: [[TMP166:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 5
7445 // CHECK19-NEXT: store i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i64** [[TMP166]], align 4
7446 // CHECK19-NEXT: [[TMP167:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 6
7447 // CHECK19-NEXT: store i8** null, i8*** [[TMP167]], align 4
7448 // CHECK19-NEXT: [[TMP168:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 7
7449 // CHECK19-NEXT: store i8** null, i8*** [[TMP168]], align 4
7450 // CHECK19-NEXT: [[TMP169:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 8
7451 // CHECK19-NEXT: store i64 0, i64* [[TMP169]], align 8
7452 // CHECK19-NEXT: [[TMP170:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]])
7453 // CHECK19-NEXT: [[TMP171:%.*]] = icmp ne i32 [[TMP170]], 0
7454 // CHECK19-NEXT: br i1 [[TMP171]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]]
7455 // CHECK19: omp_offload.failed19:
7456 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP96]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP98]]) #[[ATTR4]]
7457 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT20]]
7458 // CHECK19: omp_offload.cont20:
7459 // CHECK19-NEXT: br label [[OMP_IF_END22:%.*]]
7460 // CHECK19: omp_if.else21:
7461 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP96]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP98]]) #[[ATTR4]]
7462 // CHECK19-NEXT: br label [[OMP_IF_END22]]
7463 // CHECK19: omp_if.end22:
7464 // CHECK19-NEXT: [[TMP172:%.*]] = load i32, i32* [[A]], align 4
7465 // CHECK19-NEXT: [[TMP173:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
7466 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP173]])
7467 // CHECK19-NEXT: ret i32 [[TMP172]]
7468 //
7469 //
7470 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
7471 // CHECK19-SAME: () #[[ATTR2:[0-9]+]] {
7472 // CHECK19-NEXT: entry:
7473 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
7474 // CHECK19-NEXT: ret void
7475 //
7476 //
7477 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
7478 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
7479 // CHECK19-NEXT: entry:
7480 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7481 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7482 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7483 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
7484 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7485 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7486 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7487 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7488 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4
7489 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7490 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7491 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7492 // CHECK19-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
7493 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7494 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7495 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7496 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
7497 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7498 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7499 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
7500 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7501 // CHECK19: cond.true:
7502 // CHECK19-NEXT: br label [[COND_END:%.*]]
7503 // CHECK19: cond.false:
7504 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7505 // CHECK19-NEXT: br label [[COND_END]]
7506 // CHECK19: cond.end:
7507 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
7508 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7509 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7510 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
7511 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7512 // CHECK19: omp.inner.for.cond:
7513 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7514 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7515 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
7516 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7517 // CHECK19: omp.inner.for.body:
7518 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7519 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
7520 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
7521 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4
7522 // CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
7523 // CHECK19-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
7524 // CHECK19-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
7525 // CHECK19: .cancel.exit:
7526 // CHECK19-NEXT: br label [[CANCEL_EXIT:%.*]]
7527 // CHECK19: .cancel.continue:
7528 // CHECK19-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
7529 // CHECK19-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
7530 // CHECK19-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
7531 // CHECK19: .cancel.exit2:
7532 // CHECK19-NEXT: br label [[CANCEL_EXIT]]
7533 // CHECK19: .cancel.continue3:
7534 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7535 // CHECK19: omp.body.continue:
7536 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7537 // CHECK19: omp.inner.for.inc:
7538 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7539 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
7540 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
7541 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
7542 // CHECK19: omp.inner.for.end:
7543 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
7544 // CHECK19: omp.loop.exit:
7545 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
7546 // CHECK19-NEXT: br label [[CANCEL_CONT:%.*]]
7547 // CHECK19: cancel.cont:
7548 // CHECK19-NEXT: ret void
7549 // CHECK19: cancel.exit:
7550 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
7551 // CHECK19-NEXT: br label [[CANCEL_CONT]]
7552 //
7553 //
7554 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
7555 // CHECK19-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
7556 // CHECK19-NEXT: entry:
7557 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7558 // CHECK19-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
7559 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
7560 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7561 // CHECK19-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
7562 // CHECK19-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
7563 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7564 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
7565 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
7566 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]])
7567 // CHECK19-NEXT: ret void
7568 //
7569 //
7570 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1
7571 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
7572 // CHECK19-NEXT: entry:
7573 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7574 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7575 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7576 // CHECK19-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
7577 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7578 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
7579 // CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
7580 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7581 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7582 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7583 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7584 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4
7585 // CHECK19-NEXT: [[K1:%.*]] = alloca i64, align 8
7586 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7587 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7588 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7589 // CHECK19-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
7590 // CHECK19-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
7591 // CHECK19-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8
7592 // CHECK19-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8
7593 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7594 // CHECK19-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
7595 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7596 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7597 // CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7598 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
7599 // CHECK19-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
7600 // CHECK19-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
7601 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
7602 // CHECK19: omp.dispatch.cond:
7603 // CHECK19-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
7604 // CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
7605 // CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
7606 // CHECK19: omp.dispatch.body:
7607 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7608 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
7609 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7610 // CHECK19: omp.inner.for.cond:
7611 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]
7612 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]]
7613 // CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
7614 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7615 // CHECK19: omp.inner.for.body:
7616 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
7617 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
7618 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
7619 // CHECK19-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP13]]
7620 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP13]]
7621 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
7622 // CHECK19-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
7623 // CHECK19-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
7624 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
7625 // CHECK19-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group [[ACC_GRP13]]
7626 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]
7627 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
7628 // CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]
7629 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7630 // CHECK19: omp.body.continue:
7631 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7632 // CHECK19: omp.inner.for.inc:
7633 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
7634 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
7635 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
7636 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
7637 // CHECK19: omp.inner.for.end:
7638 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
7639 // CHECK19: omp.dispatch.inc:
7640 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
7641 // CHECK19: omp.dispatch.end:
7642 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7643 // CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
7644 // CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
7645 // CHECK19: .omp.linear.pu:
7646 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[K1]], align 8
7647 // CHECK19-NEXT: store i64 [[TMP15]], i64* [[TMP0]], align 8
7648 // CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
7649 // CHECK19: .omp.linear.pu.done:
7650 // CHECK19-NEXT: ret void
7651 //
7652 //
7653 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
7654 // CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {
7655 // CHECK19-NEXT: entry:
7656 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7657 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
7658 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7659 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
7660 // CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
7661 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
7662 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7663 // CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
7664 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7665 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7666 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
7667 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
7668 // CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
7669 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
7670 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
7671 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
7672 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
7673 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
7674 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
7675 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
7676 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
7677 // CHECK19-NEXT: ret void
7678 //
7679 //
7680 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2
7681 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {
7682 // CHECK19-NEXT: entry:
7683 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7684 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7685 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7686 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
7687 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7688 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
7689 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4
7690 // CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
7691 // CHECK19-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
7692 // CHECK19-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
7693 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
7694 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
7695 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
7696 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7697 // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8
7698 // CHECK19-NEXT: [[LIN2:%.*]] = alloca i32, align 4
7699 // CHECK19-NEXT: [[A3:%.*]] = alloca i32, align 4
7700 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7701 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7702 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7703 // CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
7704 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7705 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7706 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
7707 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
7708 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7709 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
7710 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
7711 // CHECK19-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
7712 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
7713 // CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
7714 // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
7715 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7716 // CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7717 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
7718 // CHECK19-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
7719 // CHECK19-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
7720 // CHECK19-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
7721 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
7722 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7723 // CHECK19: cond.true:
7724 // CHECK19-NEXT: br label [[COND_END:%.*]]
7725 // CHECK19: cond.false:
7726 // CHECK19-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
7727 // CHECK19-NEXT: br label [[COND_END]]
7728 // CHECK19: cond.end:
7729 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
7730 // CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
7731 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
7732 // CHECK19-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
7733 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7734 // CHECK19: omp.inner.for.cond:
7735 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
7736 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
7737 // CHECK19-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
7738 // CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7739 // CHECK19: omp.inner.for.body:
7740 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
7741 // CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
7742 // CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
7743 // CHECK19-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
7744 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
7745 // CHECK19-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
7746 // CHECK19-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
7747 // CHECK19-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
7748 // CHECK19-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
7749 // CHECK19-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
7750 // CHECK19-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
7751 // CHECK19-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4
7752 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
7753 // CHECK19-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
7754 // CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
7755 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
7756 // CHECK19-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
7757 // CHECK19-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
7758 // CHECK19-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
7759 // CHECK19-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
7760 // CHECK19-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
7761 // CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
7762 // CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
7763 // CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
7764 // CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
7765 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7766 // CHECK19: omp.body.continue:
7767 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7768 // CHECK19: omp.inner.for.inc:
7769 // CHECK19-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
7770 // CHECK19-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
7771 // CHECK19-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
7772 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
7773 // CHECK19: omp.inner.for.end:
7774 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
7775 // CHECK19: omp.loop.exit:
7776 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
7777 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7778 // CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
7779 // CHECK19-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
7780 // CHECK19: .omp.linear.pu:
7781 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4
7782 // CHECK19-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4
7783 // CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4
7784 // CHECK19-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4
7785 // CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
7786 // CHECK19: .omp.linear.pu.done:
7787 // CHECK19-NEXT: ret void
7788 //
7789 //
7790 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map.
7791 // CHECK19-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
7792 // CHECK19-NEXT: entry:
7793 // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
7794 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4
7795 // CHECK19-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
7796 // CHECK19-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
7797 // CHECK19-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
7798 // CHECK19-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
7799 // CHECK19-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
7800 // CHECK19-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
7801 // CHECK19-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
7802 // CHECK19-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
7803 // CHECK19-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
7804 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
7805 // CHECK19-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
7806 // CHECK19-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
7807 // CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
7808 // CHECK19-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
7809 // CHECK19-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
7810 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
7811 // CHECK19-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
7812 // CHECK19-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
7813 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
7814 // CHECK19-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
7815 // CHECK19-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4
7816 // CHECK19-NEXT: ret void
7817 //
7818 //
7819 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry.
7820 // CHECK19-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
7821 // CHECK19-NEXT: entry:
7822 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
7823 // CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
7824 // CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
7825 // CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
7826 // CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
7827 // CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
7828 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
7829 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
7830 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
7831 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
7832 // CHECK19-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4
7833 // CHECK19-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4
7834 // CHECK19-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4
7835 // CHECK19-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
7836 // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
7837 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
7838 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
7839 // CHECK19-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
7840 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
7841 // CHECK19-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
7842 // CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
7843 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
7844 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
7845 // CHECK19-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
7846 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
7847 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
7848 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
7849 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
7850 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
7851 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
7852 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
7853 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
7854 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
7855 // CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
7856 // CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
7857 // CHECK19-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
7858 // CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
7859 // CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
7860 // CHECK19-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
7861 // CHECK19-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
7862 // CHECK19-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
7863 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
7864 // CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
7865 // CHECK19-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
7866 // CHECK19-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
7867 // CHECK19-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
7868 // CHECK19-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
7869 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
7870 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
7871 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
7872 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
7873 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
7874 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 0
7875 // CHECK19-NEXT: store i32 1, i32* [[TMP25]], align 4, !noalias !25
7876 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 1
7877 // CHECK19-NEXT: store i32 3, i32* [[TMP26]], align 4, !noalias !25
7878 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 2
7879 // CHECK19-NEXT: store i8** [[TMP20]], i8*** [[TMP27]], align 4, !noalias !25
7880 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 3
7881 // CHECK19-NEXT: store i8** [[TMP21]], i8*** [[TMP28]], align 4, !noalias !25
7882 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 4
7883 // CHECK19-NEXT: store i64* [[TMP22]], i64** [[TMP29]], align 4, !noalias !25
7884 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 5
7885 // CHECK19-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP30]], align 4, !noalias !25
7886 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 6
7887 // CHECK19-NEXT: store i8** null, i8*** [[TMP31]], align 4, !noalias !25
7888 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 7
7889 // CHECK19-NEXT: store i8** null, i8*** [[TMP32]], align 4, !noalias !25
7890 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 8
7891 // CHECK19-NEXT: store i64 0, i64* [[TMP33]], align 8, !noalias !25
7892 // CHECK19-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel_nowait(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i8* null, i32 0, i8* null)
7893 // CHECK19-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
7894 // CHECK19-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
7895 // CHECK19: omp_offload.failed.i:
7896 // CHECK19-NEXT: [[TMP36:%.*]] = load i16, i16* [[TMP16]], align 2
7897 // CHECK19-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
7898 // CHECK19-NEXT: store i16 [[TMP36]], i16* [[CONV_I]], align 2, !noalias !25
7899 // CHECK19-NEXT: [[TMP37:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25
7900 // CHECK19-NEXT: [[TMP38:%.*]] = load i32, i32* [[TMP23]], align 4
7901 // CHECK19-NEXT: store i32 [[TMP38]], i32* [[LIN_CASTED_I]], align 4, !noalias !25
7902 // CHECK19-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !25
7903 // CHECK19-NEXT: [[TMP40:%.*]] = load i32, i32* [[TMP24]], align 4
7904 // CHECK19-NEXT: store i32 [[TMP40]], i32* [[A_CASTED_I]], align 4, !noalias !25
7905 // CHECK19-NEXT: [[TMP41:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !25
7906 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP37]], i32 [[TMP39]], i32 [[TMP41]]) #[[ATTR4]]
7907 // CHECK19-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
7908 // CHECK19: .omp_outlined..3.exit:
7909 // CHECK19-NEXT: ret i32 0
7910 //
7911 //
7912 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
7913 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
7914 // CHECK19-NEXT: entry:
7915 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7916 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7917 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
7918 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
7919 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7920 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7921 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7922 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
7923 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
7924 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
7925 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
7926 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
7927 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
7928 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
7929 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
7930 // CHECK19-NEXT: ret void
7931 //
7932 //
7933 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4
7934 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
7935 // CHECK19-NEXT: entry:
7936 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7937 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7938 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7939 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7940 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7941 // CHECK19-NEXT: [[TMP:%.*]] = alloca i16, align 2
7942 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7943 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7944 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7945 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7946 // CHECK19-NEXT: [[IT:%.*]] = alloca i16, align 2
7947 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7948 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7949 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7950 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7951 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7952 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7953 // CHECK19-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
7954 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7955 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7956 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7957 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
7958 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7959 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7960 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
7961 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7962 // CHECK19: cond.true:
7963 // CHECK19-NEXT: br label [[COND_END:%.*]]
7964 // CHECK19: cond.false:
7965 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7966 // CHECK19-NEXT: br label [[COND_END]]
7967 // CHECK19: cond.end:
7968 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
7969 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7970 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7971 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
7972 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7973 // CHECK19: omp.inner.for.cond:
7974 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7975 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7976 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
7977 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7978 // CHECK19: omp.inner.for.body:
7979 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7980 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
7981 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
7982 // CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
7983 // CHECK19-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
7984 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
7985 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
7986 // CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
7987 // CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
7988 // CHECK19-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
7989 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
7990 // CHECK19-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
7991 // CHECK19-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
7992 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7993 // CHECK19: omp.body.continue:
7994 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7995 // CHECK19: omp.inner.for.inc:
7996 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7997 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
7998 // CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
7999 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
8000 // CHECK19: omp.inner.for.end:
8001 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
8002 // CHECK19: omp.loop.exit:
8003 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
8004 // CHECK19-NEXT: ret void
8005 //
8006 //
8007 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
8008 // CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
8009 // CHECK19-NEXT: entry:
8010 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
8011 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
8012 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
8013 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
8014 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
8015 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
8016 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
8017 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
8018 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
8019 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
8020 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
8021 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
8022 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
8023 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
8024 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
8025 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
8026 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
8027 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
8028 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
8029 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
8030 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
8031 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
8032 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
8033 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
8034 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
8035 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
8036 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
8037 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
8038 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
8039 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
8040 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
8041 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
8042 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
8043 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
8044 // CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
8045 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
8046 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
8047 // CHECK19-NEXT: ret void
8048 //
8049 //
8050 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7
8051 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
8052 // CHECK19-NEXT: entry:
8053 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
8054 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
8055 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
8056 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
8057 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
8058 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
8059 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
8060 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
8061 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
8062 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
8063 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
8064 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
8065 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8066 // CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1
8067 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
8068 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
8069 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
8070 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8071 // CHECK19-NEXT: [[IT:%.*]] = alloca i8, align 1
8072 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
8073 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
8074 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
8075 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
8076 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
8077 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
8078 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
8079 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
8080 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
8081 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
8082 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
8083 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
8084 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
8085 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
8086 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
8087 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
8088 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
8089 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
8090 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
8091 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
8092 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
8093 // CHECK19-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
8094 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
8095 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8096 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
8097 // CHECK19-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
8098 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
8099 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
8100 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
8101 // CHECK19: omp.dispatch.cond:
8102 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8103 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
8104 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8105 // CHECK19: cond.true:
8106 // CHECK19-NEXT: br label [[COND_END:%.*]]
8107 // CHECK19: cond.false:
8108 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8109 // CHECK19-NEXT: br label [[COND_END]]
8110 // CHECK19: cond.end:
8111 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
8112 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
8113 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8114 // CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
8115 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8116 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8117 // CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
8118 // CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
8119 // CHECK19: omp.dispatch.body:
8120 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8121 // CHECK19: omp.inner.for.cond:
8122 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8123 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8124 // CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
8125 // CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8126 // CHECK19: omp.inner.for.body:
8127 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8128 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
8129 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
8130 // CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
8131 // CHECK19-NEXT: store i8 [[CONV]], i8* [[IT]], align 1
8132 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
8133 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
8134 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
8135 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
8136 // CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
8137 // CHECK19-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
8138 // CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
8139 // CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
8140 // CHECK19-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4
8141 // CHECK19-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
8142 // CHECK19-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
8143 // CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
8144 // CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
8145 // CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
8146 // CHECK19-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4
8147 // CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
8148 // CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
8149 // CHECK19-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
8150 // CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
8151 // CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
8152 // CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
8153 // CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
8154 // CHECK19-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
8155 // CHECK19-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
8156 // CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
8157 // CHECK19-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8
8158 // CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
8159 // CHECK19-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4
8160 // CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
8161 // CHECK19-NEXT: store i64 [[ADD20]], i64* [[X]], align 4
8162 // CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
8163 // CHECK19-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
8164 // CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
8165 // CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
8166 // CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
8167 // CHECK19-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4
8168 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8169 // CHECK19: omp.body.continue:
8170 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8171 // CHECK19: omp.inner.for.inc:
8172 // CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8173 // CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
8174 // CHECK19-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
8175 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
8176 // CHECK19: omp.inner.for.end:
8177 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
8178 // CHECK19: omp.dispatch.inc:
8179 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8180 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
8181 // CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
8182 // CHECK19-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
8183 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8184 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
8185 // CHECK19-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
8186 // CHECK19-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
8187 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
8188 // CHECK19: omp.dispatch.end:
8189 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
8190 // CHECK19-NEXT: ret void
8191 //
8192 //
8193 // CHECK19-LABEL: define {{[^@]+}}@_Z3bari
8194 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
8195 // CHECK19-NEXT: entry:
8196 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
8197 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
8198 // CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
8199 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
8200 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4
8201 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8202 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
8203 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
8204 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
8205 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4
8206 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
8207 // CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
8208 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
8209 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
8210 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
8211 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
8212 // CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
8213 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
8214 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
8215 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
8216 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
8217 // CHECK19-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
8218 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
8219 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
8220 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
8221 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
8222 // CHECK19-NEXT: ret i32 [[TMP8]]
8223 //
8224 //
8225 // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
8226 // CHECK19-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
8227 // CHECK19-NEXT: entry:
8228 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
8229 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
8230 // CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4
8231 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
8232 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
8233 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
8234 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
8235 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
8236 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
8237 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
8238 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
8239 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
8240 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
8241 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8242 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
8243 // CHECK19-NEXT: store i32 [[ADD]], i32* [[B]], align 4
8244 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
8245 // CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
8246 // CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
8247 // CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
8248 // CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
8249 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
8250 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
8251 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
8252 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
8253 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
8254 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
8255 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8256 // CHECK19: omp_if.then:
8257 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
8258 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
8259 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
8260 // CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
8261 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
8262 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false)
8263 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8264 // CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1**
8265 // CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4
8266 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8267 // CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double**
8268 // CHECK19-NEXT: store double* [[A]], double** [[TMP14]], align 4
8269 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
8270 // CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4
8271 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
8272 // CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
8273 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4
8274 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
8275 // CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
8276 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4
8277 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
8278 // CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4
8279 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
8280 // CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
8281 // CHECK19-NEXT: store i32 2, i32* [[TMP22]], align 4
8282 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
8283 // CHECK19-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
8284 // CHECK19-NEXT: store i32 2, i32* [[TMP24]], align 4
8285 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
8286 // CHECK19-NEXT: store i8* null, i8** [[TMP25]], align 4
8287 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
8288 // CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
8289 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4
8290 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
8291 // CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
8292 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4
8293 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
8294 // CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4
8295 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
8296 // CHECK19-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16**
8297 // CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4
8298 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
8299 // CHECK19-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16**
8300 // CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4
8301 // CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
8302 // CHECK19-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4
8303 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
8304 // CHECK19-NEXT: store i8* null, i8** [[TMP36]], align 4
8305 // CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8306 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8307 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
8308 // CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
8309 // CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
8310 // CHECK19-NEXT: store i32 1, i32* [[TMP40]], align 4
8311 // CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
8312 // CHECK19-NEXT: store i32 5, i32* [[TMP41]], align 4
8313 // CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
8314 // CHECK19-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 4
8315 // CHECK19-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
8316 // CHECK19-NEXT: store i8** [[TMP38]], i8*** [[TMP43]], align 4
8317 // CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
8318 // CHECK19-NEXT: store i64* [[TMP39]], i64** [[TMP44]], align 4
8319 // CHECK19-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
8320 // CHECK19-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i64** [[TMP45]], align 4
8321 // CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
8322 // CHECK19-NEXT: store i8** null, i8*** [[TMP46]], align 4
8323 // CHECK19-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
8324 // CHECK19-NEXT: store i8** null, i8*** [[TMP47]], align 4
8325 // CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
8326 // CHECK19-NEXT: store i64 0, i64* [[TMP48]], align 8
8327 // CHECK19-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
8328 // CHECK19-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
8329 // CHECK19-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
8330 // CHECK19: omp_offload.failed:
8331 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
8332 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
8333 // CHECK19: omp_offload.cont:
8334 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
8335 // CHECK19: omp_if.else:
8336 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
8337 // CHECK19-NEXT: br label [[OMP_IF_END]]
8338 // CHECK19: omp_if.end:
8339 // CHECK19-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP1]]
8340 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP51]]
8341 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
8342 // CHECK19-NEXT: [[TMP52:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
8343 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP52]] to i32
8344 // CHECK19-NEXT: [[TMP53:%.*]] = load i32, i32* [[B]], align 4
8345 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP53]]
8346 // CHECK19-NEXT: [[TMP54:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
8347 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP54]])
8348 // CHECK19-NEXT: ret i32 [[ADD3]]
8349 //
8350 //
8351 // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici
8352 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
8353 // CHECK19-NEXT: entry:
8354 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
8355 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
8356 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2
8357 // CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1
8358 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
8359 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
8360 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
8361 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
8362 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
8363 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
8364 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
8365 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
8366 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4
8367 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2
8368 // CHECK19-NEXT: store i8 0, i8* [[AAA]], align 1
8369 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
8370 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
8371 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
8372 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
8373 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
8374 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
8375 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
8376 // CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
8377 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
8378 // CHECK19-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1
8379 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
8380 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
8381 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
8382 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8383 // CHECK19: omp_if.then:
8384 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8385 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
8386 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
8387 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8388 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
8389 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4
8390 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
8391 // CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4
8392 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
8393 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
8394 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
8395 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
8396 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
8397 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4
8398 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
8399 // CHECK19-NEXT: store i8* null, i8** [[TMP16]], align 4
8400 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
8401 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
8402 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
8403 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
8404 // CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
8405 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
8406 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
8407 // CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4
8408 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
8409 // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
8410 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
8411 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
8412 // CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
8413 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
8414 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
8415 // CHECK19-NEXT: store i8* null, i8** [[TMP26]], align 4
8416 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8417 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8418 // CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
8419 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
8420 // CHECK19-NEXT: store i32 1, i32* [[TMP29]], align 4
8421 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
8422 // CHECK19-NEXT: store i32 4, i32* [[TMP30]], align 4
8423 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
8424 // CHECK19-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 4
8425 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
8426 // CHECK19-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 4
8427 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
8428 // CHECK19-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64** [[TMP33]], align 4
8429 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
8430 // CHECK19-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i64** [[TMP34]], align 4
8431 // CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
8432 // CHECK19-NEXT: store i8** null, i8*** [[TMP35]], align 4
8433 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
8434 // CHECK19-NEXT: store i8** null, i8*** [[TMP36]], align 4
8435 // CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
8436 // CHECK19-NEXT: store i64 0, i64* [[TMP37]], align 8
8437 // CHECK19-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
8438 // CHECK19-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
8439 // CHECK19-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
8440 // CHECK19: omp_offload.failed:
8441 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
8442 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
8443 // CHECK19: omp_offload.cont:
8444 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
8445 // CHECK19: omp_if.else:
8446 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
8447 // CHECK19-NEXT: br label [[OMP_IF_END]]
8448 // CHECK19: omp_if.end:
8449 // CHECK19-NEXT: [[TMP40:%.*]] = load i32, i32* [[A]], align 4
8450 // CHECK19-NEXT: ret i32 [[TMP40]]
8451 //
8452 //
8453 // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
8454 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
8455 // CHECK19-NEXT: entry:
8456 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
8457 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
8458 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2
8459 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
8460 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
8461 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
8462 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
8463 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
8464 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
8465 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
8466 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4
8467 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2
8468 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
8469 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
8470 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
8471 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
8472 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
8473 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
8474 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
8475 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
8476 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
8477 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8478 // CHECK19: omp_if.then:
8479 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8480 // CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
8481 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4
8482 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8483 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
8484 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
8485 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
8486 // CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4
8487 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
8488 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
8489 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
8490 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
8491 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
8492 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
8493 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
8494 // CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4
8495 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
8496 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
8497 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
8498 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
8499 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
8500 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
8501 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
8502 // CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4
8503 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8504 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8505 // CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
8506 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
8507 // CHECK19-NEXT: store i32 1, i32* [[TMP22]], align 4
8508 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
8509 // CHECK19-NEXT: store i32 3, i32* [[TMP23]], align 4
8510 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
8511 // CHECK19-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 4
8512 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
8513 // CHECK19-NEXT: store i8** [[TMP21]], i8*** [[TMP25]], align 4
8514 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
8515 // CHECK19-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64** [[TMP26]], align 4
8516 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
8517 // CHECK19-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i64** [[TMP27]], align 4
8518 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
8519 // CHECK19-NEXT: store i8** null, i8*** [[TMP28]], align 4
8520 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
8521 // CHECK19-NEXT: store i8** null, i8*** [[TMP29]], align 4
8522 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
8523 // CHECK19-NEXT: store i64 0, i64* [[TMP30]], align 8
8524 // CHECK19-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
8525 // CHECK19-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
8526 // CHECK19-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
8527 // CHECK19: omp_offload.failed:
8528 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
8529 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
8530 // CHECK19: omp_offload.cont:
8531 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
8532 // CHECK19: omp_if.else:
8533 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
8534 // CHECK19-NEXT: br label [[OMP_IF_END]]
8535 // CHECK19: omp_if.end:
8536 // CHECK19-NEXT: [[TMP33:%.*]] = load i32, i32* [[A]], align 4
8537 // CHECK19-NEXT: ret i32 [[TMP33]]
8538 //
8539 //
8540 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
8541 // CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
8542 // CHECK19-NEXT: entry:
8543 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
8544 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
8545 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
8546 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
8547 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
8548 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
8549 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
8550 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
8551 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
8552 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
8553 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
8554 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
8555 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
8556 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
8557 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
8558 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
8559 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
8560 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
8561 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
8562 // CHECK19-NEXT: ret void
8563 //
8564 //
8565 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10
8566 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
8567 // CHECK19-NEXT: entry:
8568 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
8569 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
8570 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
8571 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
8572 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
8573 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
8574 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
8575 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
8576 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4
8577 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
8578 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
8579 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
8580 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8581 // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8
8582 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
8583 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
8584 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
8585 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
8586 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
8587 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
8588 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
8589 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
8590 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
8591 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
8592 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
8593 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
8594 // CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
8595 // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
8596 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8597 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
8598 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
8599 // CHECK19-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
8600 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8601 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
8602 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8603 // CHECK19: cond.true:
8604 // CHECK19-NEXT: br label [[COND_END:%.*]]
8605 // CHECK19: cond.false:
8606 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8607 // CHECK19-NEXT: br label [[COND_END]]
8608 // CHECK19: cond.end:
8609 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
8610 // CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
8611 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
8612 // CHECK19-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
8613 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8614 // CHECK19: omp.inner.for.cond:
8615 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
8616 // CHECK19-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8617 // CHECK19-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
8618 // CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8619 // CHECK19: omp.inner.for.body:
8620 // CHECK19-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
8621 // CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
8622 // CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
8623 // CHECK19-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
8624 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
8625 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
8626 // CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
8627 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
8628 // CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4
8629 // CHECK19-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
8630 // CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4
8631 // CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
8632 // CHECK19-NEXT: store double [[INC]], double* [[A4]], align 4
8633 // CHECK19-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
8634 // CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
8635 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
8636 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
8637 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
8638 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8639 // CHECK19: omp.body.continue:
8640 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8641 // CHECK19: omp.inner.for.inc:
8642 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
8643 // CHECK19-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
8644 // CHECK19-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
8645 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
8646 // CHECK19: omp.inner.for.end:
8647 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
8648 // CHECK19: omp.loop.exit:
8649 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
8650 // CHECK19-NEXT: ret void
8651 //
8652 //
8653 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
8654 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
8655 // CHECK19-NEXT: entry:
8656 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
8657 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
8658 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
8659 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
8660 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
8661 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
8662 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
8663 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
8664 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
8665 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
8666 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
8667 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
8668 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
8669 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
8670 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
8671 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
8672 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
8673 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
8674 // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
8675 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
8676 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
8677 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
8678 // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
8679 // CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
8680 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
8681 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
8682 // CHECK19-NEXT: ret void
8683 //
8684 //
8685 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..13
8686 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
8687 // CHECK19-NEXT: entry:
8688 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
8689 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
8690 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
8691 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
8692 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
8693 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
8694 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8695 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
8696 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
8697 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
8698 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
8699 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
8700 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
8701 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
8702 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
8703 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
8704 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
8705 // CHECK19-NEXT: ret void
8706 //
8707 //
8708 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
8709 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
8710 // CHECK19-NEXT: entry:
8711 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
8712 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
8713 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
8714 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
8715 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
8716 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
8717 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
8718 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
8719 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
8720 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
8721 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
8722 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
8723 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
8724 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
8725 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
8726 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
8727 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
8728 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
8729 // CHECK19-NEXT: ret void
8730 //
8731 //
8732 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..16
8733 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
8734 // CHECK19-NEXT: entry:
8735 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
8736 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
8737 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
8738 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
8739 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
8740 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
8741 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4
8742 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
8743 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
8744 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
8745 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8746 // CHECK19-NEXT: [[I:%.*]] = alloca i64, align 8
8747 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
8748 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
8749 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
8750 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
8751 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
8752 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
8753 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
8754 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
8755 // CHECK19-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
8756 // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
8757 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8758 // CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
8759 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
8760 // CHECK19-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
8761 // CHECK19-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8762 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
8763 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8764 // CHECK19: cond.true:
8765 // CHECK19-NEXT: br label [[COND_END:%.*]]
8766 // CHECK19: cond.false:
8767 // CHECK19-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8768 // CHECK19-NEXT: br label [[COND_END]]
8769 // CHECK19: cond.end:
8770 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
8771 // CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
8772 // CHECK19-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
8773 // CHECK19-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
8774 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8775 // CHECK19: omp.inner.for.cond:
8776 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
8777 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8778 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
8779 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8780 // CHECK19: omp.inner.for.body:
8781 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
8782 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
8783 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
8784 // CHECK19-NEXT: store i64 [[ADD]], i64* [[I]], align 8
8785 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
8786 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
8787 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
8788 // CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
8789 // CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
8790 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
8791 // CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
8792 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
8793 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
8794 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
8795 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
8796 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
8797 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8798 // CHECK19: omp.body.continue:
8799 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8800 // CHECK19: omp.inner.for.inc:
8801 // CHECK19-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
8802 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
8803 // CHECK19-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
8804 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
8805 // CHECK19: omp.inner.for.end:
8806 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
8807 // CHECK19: omp.loop.exit:
8808 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
8809 // CHECK19-NEXT: ret void
8810 //
8811 //
8812 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
8813 // CHECK19-SAME: () #[[ATTR6]] {
8814 // CHECK19-NEXT: entry:
8815 // CHECK19-NEXT: call void @__tgt_register_requires(i64 1)
8816 // CHECK19-NEXT: ret void
8817 //
8818