1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2 6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 9 10 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 17 // Test target codegen - host bc file has to be created first. 18 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 19 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 21 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 22 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 23 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 24 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 25 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 26 27 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 28 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 29 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 30 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 31 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 32 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 33 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 34 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 35 36 // Test host codegen. 37 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 38 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 39 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK18 40 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 41 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 42 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK20 43 44 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 45 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 46 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 47 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 48 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 49 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 50 51 // Test target codegen - host bc file has to be created first. 52 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 53 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK25 54 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 55 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK26 56 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 57 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK27 58 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 59 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK28 60 61 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 62 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 63 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 64 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 65 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 66 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 67 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 68 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 69 70 // expected-no-diagnostics 71 #ifndef HEADER 72 #define HEADER 73 74 75 76 77 // We have 8 target regions, but only 7 that actually will generate offloading 78 // code, only 6 will have mapped arguments, and only 4 have all-constant map 79 // sizes. 80 81 82 83 // Check target registration is registered as a Ctor. 84 85 86 template<typename tx, typename ty> 87 struct TT{ 88 tx X; 89 ty Y; 90 }; 91 92 long long get_val() { return 0; } 93 94 int foo(int n) { 95 int a = 0; 96 short aa = 0; 97 float b[10]; 98 float bn[n]; 99 double c[5][10]; 100 double cn[5][n]; 101 TT<long long, char> d; 102 103 #pragma omp target parallel for 104 for (int i = 3; i < 32; i += 5) { 105 #pragma omp cancel for 106 #pragma omp cancellation point for 107 } 108 109 long long k = get_val(); 110 #pragma omp target parallel for if(target: 0) linear(k : 3) schedule(dynamic) 111 for (int i = 10; i > 1; i--) { 112 a += 1; 113 } 114 115 // CEHCK-32: [[FPSIZEGEP]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 0 116 // CEHCK-32: [[FPSIZEADDR:%.+]] = bitcast [3 x i64]* [[FPSIZEGEP]] to i8* 117 // CEHCK-32: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPSIZEADDR]], i8* align 8 bitcast ([3 x i64]* [[SIZET2]] to i8*), i64 24, i1 false) 118 // CEHCK-32: [[FPBPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 1 119 // CEHCK-32: [[FPBPADDR:%.+]] = bitcast [3 x i8*]* [[FPBPGEP]] to i8* 120 // CEHCK-32: [[BPCAST:%.+]] = bitcast i8** [[BPGEP]] to i8* 121 // CEHCK-32: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPBPADDR]], i8* align 8 [[BPCAST]], i64 24, i1 false) 122 // CEHCK-32: [[FPPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 2 123 // CEHCK-32: [[FPPADDR:%.+]] = bitcast [3 x i8*]* [[FPPGEP]] to i8* 124 // CEHCK-32: [[PCAST:%.+]] = bitcast i8** [[PGEP]] to i8* 125 // CEHCK-32: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPPADDR]], i8* align 8 [[BCAST]], i64 24, i1 false) 126 // CEHCK-64: [[FPBPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 0 127 // CEHCK-64: [[FPBPADDR:%.+]] = bitcast [3 x i8*]* [[FPBPGEP]] to i8* 128 // CEHCK-64: [[BPCAST:%.+]] = bitcast i8** [[BPGEP]] to i8* 129 // CEHCK-64: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPBPADDR]], i8* align 8 [[BPCAST]], i64 24, i1 false) 130 // CEHCK-64: [[FPPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 1 131 // CEHCK-64: [[FPPADDR:%.+]] = bitcast [3 x i8*]* [[FPPGEP]] to i8* 132 // CEHCK-64: [[PCAST:%.+]] = bitcast i8** [[PGEP]] to i8* 133 // CEHCK-64: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPPADDR]], i8* align 8 [[BCAST]], i64 24, i1 false) 134 // CEHCK-64: [[FPSIZEGEP]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 2 135 // CEHCK-64: [[FPSIZEADDR:%.+]] = bitcast [3 x i64]* [[FPSIZEGEP]] to i8* 136 // CEHCK-64: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPSIZEADDR]], i8* align 8 bitcast ([3 x i64]* [[SIZET2]] to i8*), i64 24, i1 false) 137 int lin = 12; 138 #pragma omp target parallel for if(target: 1) linear(lin, a : get_val()) nowait 139 for (unsigned long long it = 2000; it >= 600; it-=400) { 140 aa += 1; 141 } 142 143 144 145 146 #pragma omp target parallel for if(target: n>10) 147 for (short it = 6; it <= 20; it-=-4) { 148 a += 1; 149 aa += 1; 150 } 151 152 // We capture 3 VLA sizes in this target region 153 154 155 156 157 158 // The names below are not necessarily consistent with the names used for the 159 // addresses above as some are repeated. 160 161 162 163 164 165 166 167 168 169 170 #pragma omp target parallel for if(target: n>20) schedule(static, a) 171 for (unsigned char it = 'z'; it >= 'a'; it+=-1) { 172 a += 1; 173 b[2] += 1.0; 174 bn[3] += 1.0; 175 c[1][2] += 1.0; 176 cn[1][3] += 1.0; 177 d.X += 1; 178 d.Y += 1; 179 } 180 181 return a; 182 } 183 184 // Check that the offloading functions are emitted and that the arguments are 185 // correct and loaded correctly for the target regions in foo(). 186 187 188 // Create stack storage and store argument in there. 189 190 // Create stack storage and store argument in there. 191 192 193 // Create stack storage and store argument in there. 194 195 // Create local storage for each capture. 196 197 198 199 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 200 201 template<typename tx> 202 tx ftemplate(int n) { 203 tx a = 0; 204 short aa = 0; 205 tx b[10]; 206 207 #pragma omp target parallel for if(target: n>40) 208 for (long long i = -10; i < 10; i += 3) { 209 a += 1; 210 aa += 1; 211 b[2] += 1; 212 } 213 214 return a; 215 } 216 217 static 218 int fstatic(int n) { 219 int a = 0; 220 short aa = 0; 221 char aaa = 0; 222 int b[10]; 223 224 #pragma omp target parallel for if(target: n>50) 225 for (unsigned i=100; i<10; i+=10) { 226 a += 1; 227 aa += 1; 228 aaa += 1; 229 b[2] += 1; 230 } 231 232 return a; 233 } 234 235 struct S1 { 236 double a; 237 238 int r1(int n){ 239 int b = n+1; 240 short int c[2][n]; 241 242 #pragma omp target parallel for if(target: n>60) 243 for (unsigned long long it = 2000; it >= 600; it -= 400) { 244 this->a = (double)b + 1.5; 245 c[1][1] = ++a; 246 } 247 248 return c[1][1] + (int)b; 249 } 250 }; 251 252 int bar(int n){ 253 int a = 0; 254 255 a += foo(n); 256 257 S1 S; 258 a += S.r1(n); 259 260 a += fstatic(n); 261 262 a += ftemplate<int>(n); 263 264 return a; 265 } 266 267 268 269 // We capture 2 VLA sizes in this target region 270 271 272 // The names below are not necessarily consistent with the names used for the 273 // addresses above as some are repeated. 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 // Check that the offloading functions are emitted and that the arguments are 293 // correct and loaded correctly for the target regions of the callees of bar(). 294 295 // Create local storage for each capture. 296 // Store captures in the context. 297 298 299 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 300 301 302 // Create local storage for each capture. 303 // Store captures in the context. 304 305 306 307 308 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 309 310 // Create local storage for each capture. 311 // Store captures in the context. 312 313 314 315 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 316 317 318 #endif 319 // CHECK1-LABEL: define {{[^@]+}}@_Z7get_valv 320 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 321 // CHECK1-NEXT: entry: 322 // CHECK1-NEXT: ret i64 0 323 // 324 // 325 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 326 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 327 // CHECK1-NEXT: entry: 328 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 329 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 330 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 331 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 332 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 333 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 334 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 335 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 336 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 337 // CHECK1-NEXT: [[K:%.*]] = alloca i64, align 8 338 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 339 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 340 // CHECK1-NEXT: [[LIN:%.*]] = alloca i32, align 4 341 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 342 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 343 // CHECK1-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8 344 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 345 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 346 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 347 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 348 // CHECK1-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8 349 // CHECK1-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8 350 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 351 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 352 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 353 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 354 // CHECK1-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8 355 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 356 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8 357 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8 358 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8 359 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 360 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 361 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 362 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 363 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 364 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 365 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 366 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 367 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 368 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 369 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 370 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 371 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 372 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 373 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 374 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 375 // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 376 // CHECK1-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 377 // CHECK1-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 378 // CHECK1: omp_offload.failed: 379 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 380 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 381 // CHECK1: omp_offload.cont: 382 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 383 // CHECK1-NEXT: store i64 [[CALL]], i64* [[K]], align 8 384 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 385 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 386 // CHECK1-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4 387 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8 388 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[K]], align 8 389 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[K_CASTED]], align 8 390 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8 391 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR4]] 392 // CHECK1-NEXT: store i32 12, i32* [[LIN]], align 4 393 // CHECK1-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 394 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 395 // CHECK1-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 396 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 397 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4 398 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 399 // CHECK1-NEXT: store i32 [[TMP15]], i32* [[CONV3]], align 4 400 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 401 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 402 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32* 403 // CHECK1-NEXT: store i32 [[TMP17]], i32* [[CONV5]], align 4 404 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8 405 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 406 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 407 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP20]], align 8 408 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 409 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 410 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP22]], align 8 411 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 412 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 413 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 414 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 415 // CHECK1-NEXT: store i64 [[TMP16]], i64* [[TMP25]], align 8 416 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 417 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 418 // CHECK1-NEXT: store i64 [[TMP16]], i64* [[TMP27]], align 8 419 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 420 // CHECK1-NEXT: store i8* null, i8** [[TMP28]], align 8 421 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 422 // CHECK1-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 423 // CHECK1-NEXT: store i64 [[TMP18]], i64* [[TMP30]], align 8 424 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 425 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 426 // CHECK1-NEXT: store i64 [[TMP18]], i64* [[TMP32]], align 8 427 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 428 // CHECK1-NEXT: store i8* null, i8** [[TMP33]], align 8 429 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 430 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 431 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 432 // CHECK1-NEXT: [[TMP37:%.*]] = load i16, i16* [[AA]], align 2 433 // CHECK1-NEXT: store i16 [[TMP37]], i16* [[TMP36]], align 4 434 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 435 // CHECK1-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4 436 // CHECK1-NEXT: store i32 [[TMP39]], i32* [[TMP38]], align 4 437 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 438 // CHECK1-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 439 // CHECK1-NEXT: store i32 [[TMP41]], i32* [[TMP40]], align 4 440 // CHECK1-NEXT: [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 441 // CHECK1-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates* 442 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0 443 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0 444 // CHECK1-NEXT: [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8 445 // CHECK1-NEXT: [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 446 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false) 447 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1 448 // CHECK1-NEXT: [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon* 449 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0 450 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8* 451 // CHECK1-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8* 452 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false) 453 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1 454 // CHECK1-NEXT: [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8* 455 // CHECK1-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8* 456 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false) 457 // CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2 458 // CHECK1-NEXT: [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8* 459 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 460 // CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3 461 // CHECK1-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 462 // CHECK1-NEXT: store i16 [[TMP59]], i16* [[TMP58]], align 8 463 // CHECK1-NEXT: [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]]) 464 // CHECK1-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4 465 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32* 466 // CHECK1-NEXT: store i32 [[TMP61]], i32* [[CONV7]], align 4 467 // CHECK1-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8 468 // CHECK1-NEXT: [[TMP63:%.*]] = load i16, i16* [[AA]], align 2 469 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16* 470 // CHECK1-NEXT: store i16 [[TMP63]], i16* [[CONV9]], align 2 471 // CHECK1-NEXT: [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8 472 // CHECK1-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4 473 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10 474 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 475 // CHECK1: omp_if.then: 476 // CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 477 // CHECK1-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64* 478 // CHECK1-NEXT: store i64 [[TMP62]], i64* [[TMP67]], align 8 479 // CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 480 // CHECK1-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* 481 // CHECK1-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8 482 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 483 // CHECK1-NEXT: store i8* null, i8** [[TMP70]], align 8 484 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 485 // CHECK1-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* 486 // CHECK1-NEXT: store i64 [[TMP64]], i64* [[TMP72]], align 8 487 // CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 488 // CHECK1-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* 489 // CHECK1-NEXT: store i64 [[TMP64]], i64* [[TMP74]], align 8 490 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 491 // CHECK1-NEXT: store i8* null, i8** [[TMP75]], align 8 492 // CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 493 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 494 // CHECK1-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 495 // CHECK1-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0 496 // CHECK1-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]] 497 // CHECK1: omp_offload.failed13: 498 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 499 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT14]] 500 // CHECK1: omp_offload.cont14: 501 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 502 // CHECK1: omp_if.else: 503 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 504 // CHECK1-NEXT: br label [[OMP_IF_END]] 505 // CHECK1: omp_if.end: 506 // CHECK1-NEXT: [[TMP80:%.*]] = load i32, i32* [[A]], align 4 507 // CHECK1-NEXT: store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4 508 // CHECK1-NEXT: [[TMP81:%.*]] = load i32, i32* [[A]], align 4 509 // CHECK1-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32* 510 // CHECK1-NEXT: store i32 [[TMP81]], i32* [[CONV16]], align 4 511 // CHECK1-NEXT: [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8 512 // CHECK1-NEXT: [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 513 // CHECK1-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 514 // CHECK1-NEXT: store i32 [[TMP83]], i32* [[CONV17]], align 4 515 // CHECK1-NEXT: [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 516 // CHECK1-NEXT: [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4 517 // CHECK1-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20 518 // CHECK1-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 519 // CHECK1: omp_if.then19: 520 // CHECK1-NEXT: [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4 521 // CHECK1-NEXT: [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]] 522 // CHECK1-NEXT: [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8 523 // CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 524 // CHECK1-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* 525 // CHECK1-NEXT: store i64 [[TMP82]], i64* [[TMP90]], align 8 526 // CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 527 // CHECK1-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i64* 528 // CHECK1-NEXT: store i64 [[TMP82]], i64* [[TMP92]], align 8 529 // CHECK1-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 530 // CHECK1-NEXT: store i64 4, i64* [[TMP93]], align 8 531 // CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 532 // CHECK1-NEXT: store i8* null, i8** [[TMP94]], align 8 533 // CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 534 // CHECK1-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 535 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8 536 // CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 537 // CHECK1-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]** 538 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8 539 // CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 540 // CHECK1-NEXT: store i64 40, i64* [[TMP99]], align 8 541 // CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 542 // CHECK1-NEXT: store i8* null, i8** [[TMP100]], align 8 543 // CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 544 // CHECK1-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i64* 545 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP102]], align 8 546 // CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 547 // CHECK1-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to i64* 548 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP104]], align 8 549 // CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 550 // CHECK1-NEXT: store i64 8, i64* [[TMP105]], align 8 551 // CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 552 // CHECK1-NEXT: store i8* null, i8** [[TMP106]], align 8 553 // CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 554 // CHECK1-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** 555 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP108]], align 8 556 // CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 557 // CHECK1-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to float** 558 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP110]], align 8 559 // CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 560 // CHECK1-NEXT: store i64 [[TMP86]], i64* [[TMP111]], align 8 561 // CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 562 // CHECK1-NEXT: store i8* null, i8** [[TMP112]], align 8 563 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 564 // CHECK1-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** 565 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8 566 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 567 // CHECK1-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to [5 x [10 x double]]** 568 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP116]], align 8 569 // CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 570 // CHECK1-NEXT: store i64 400, i64* [[TMP117]], align 8 571 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 572 // CHECK1-NEXT: store i8* null, i8** [[TMP118]], align 8 573 // CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 574 // CHECK1-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i64* 575 // CHECK1-NEXT: store i64 5, i64* [[TMP120]], align 8 576 // CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 577 // CHECK1-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64* 578 // CHECK1-NEXT: store i64 5, i64* [[TMP122]], align 8 579 // CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 580 // CHECK1-NEXT: store i64 8, i64* [[TMP123]], align 8 581 // CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5 582 // CHECK1-NEXT: store i8* null, i8** [[TMP124]], align 8 583 // CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 584 // CHECK1-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* 585 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP126]], align 8 586 // CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 587 // CHECK1-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* 588 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP128]], align 8 589 // CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 590 // CHECK1-NEXT: store i64 8, i64* [[TMP129]], align 8 591 // CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6 592 // CHECK1-NEXT: store i8* null, i8** [[TMP130]], align 8 593 // CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 594 // CHECK1-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double** 595 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP132]], align 8 596 // CHECK1-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 597 // CHECK1-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to double** 598 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP134]], align 8 599 // CHECK1-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 600 // CHECK1-NEXT: store i64 [[TMP88]], i64* [[TMP135]], align 8 601 // CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7 602 // CHECK1-NEXT: store i8* null, i8** [[TMP136]], align 8 603 // CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 604 // CHECK1-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT** 605 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 8 606 // CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 607 // CHECK1-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to %struct.TT** 608 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP140]], align 8 609 // CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 610 // CHECK1-NEXT: store i64 16, i64* [[TMP141]], align 8 611 // CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8 612 // CHECK1-NEXT: store i8* null, i8** [[TMP142]], align 8 613 // CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9 614 // CHECK1-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i64* 615 // CHECK1-NEXT: store i64 [[TMP84]], i64* [[TMP144]], align 8 616 // CHECK1-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9 617 // CHECK1-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to i64* 618 // CHECK1-NEXT: store i64 [[TMP84]], i64* [[TMP146]], align 8 619 // CHECK1-NEXT: [[TMP147:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 620 // CHECK1-NEXT: store i64 4, i64* [[TMP147]], align 8 621 // CHECK1-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9 622 // CHECK1-NEXT: store i8* null, i8** [[TMP148]], align 8 623 // CHECK1-NEXT: [[TMP149:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 624 // CHECK1-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 625 // CHECK1-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 626 // CHECK1-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 627 // CHECK1-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 628 // CHECK1-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 629 // CHECK1: omp_offload.failed23: 630 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 631 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT24]] 632 // CHECK1: omp_offload.cont24: 633 // CHECK1-NEXT: br label [[OMP_IF_END26:%.*]] 634 // CHECK1: omp_if.else25: 635 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 636 // CHECK1-NEXT: br label [[OMP_IF_END26]] 637 // CHECK1: omp_if.end26: 638 // CHECK1-NEXT: [[TMP154:%.*]] = load i32, i32* [[A]], align 4 639 // CHECK1-NEXT: [[TMP155:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 640 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP155]]) 641 // CHECK1-NEXT: ret i32 [[TMP154]] 642 // 643 // 644 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 645 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] { 646 // CHECK1-NEXT: entry: 647 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 648 // CHECK1-NEXT: ret void 649 // 650 // 651 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 652 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 653 // CHECK1-NEXT: entry: 654 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 655 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 656 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 657 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 658 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 659 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 660 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 661 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 662 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 663 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 664 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 665 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 666 // CHECK1-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 667 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 668 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 669 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 670 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 671 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 672 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 673 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 674 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 675 // CHECK1: cond.true: 676 // CHECK1-NEXT: br label [[COND_END:%.*]] 677 // CHECK1: cond.false: 678 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 679 // CHECK1-NEXT: br label [[COND_END]] 680 // CHECK1: cond.end: 681 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 682 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 683 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 684 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 685 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 686 // CHECK1: omp.inner.for.cond: 687 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 688 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 689 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 690 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 691 // CHECK1: omp.inner.for.body: 692 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 693 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 694 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 695 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 696 // CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 697 // CHECK1-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 698 // CHECK1-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 699 // CHECK1: .cancel.exit: 700 // CHECK1-NEXT: br label [[CANCEL_EXIT:%.*]] 701 // CHECK1: .cancel.continue: 702 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 703 // CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 704 // CHECK1-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 705 // CHECK1: .cancel.exit2: 706 // CHECK1-NEXT: br label [[CANCEL_EXIT]] 707 // CHECK1: .cancel.continue3: 708 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 709 // CHECK1: omp.body.continue: 710 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 711 // CHECK1: omp.inner.for.inc: 712 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 713 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 714 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 715 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 716 // CHECK1: omp.inner.for.end: 717 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 718 // CHECK1: omp.loop.exit: 719 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 720 // CHECK1-NEXT: br label [[CANCEL_CONT:%.*]] 721 // CHECK1: cancel.cont: 722 // CHECK1-NEXT: ret void 723 // CHECK1: cancel.exit: 724 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 725 // CHECK1-NEXT: br label [[CANCEL_CONT]] 726 // 727 // 728 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 729 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 730 // CHECK1-NEXT: entry: 731 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 732 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 733 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 734 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 735 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 736 // CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 737 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 738 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 739 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 740 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 741 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 742 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 743 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 744 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 745 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 746 // CHECK1-NEXT: ret void 747 // 748 // 749 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 750 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 751 // CHECK1-NEXT: entry: 752 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 753 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 754 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 755 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 756 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 757 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 758 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 759 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 760 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 761 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 762 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 763 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 764 // CHECK1-NEXT: [[K1:%.*]] = alloca i64, align 8 765 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 766 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 767 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 768 // CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 769 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 770 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8 771 // CHECK1-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8 772 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 773 // CHECK1-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 774 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 775 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 776 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 777 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 778 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 779 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1) 780 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 781 // CHECK1: omp.dispatch.cond: 782 // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 783 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 784 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 785 // CHECK1: omp.dispatch.body: 786 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 787 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 788 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 789 // CHECK1: omp.inner.for.cond: 790 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 791 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 792 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 793 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 794 // CHECK1: omp.inner.for.body: 795 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 796 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 797 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 798 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12 799 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12 800 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 801 // CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 802 // CHECK1-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 803 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] 804 // CHECK1-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12 805 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12 806 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 807 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12 808 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 809 // CHECK1: omp.body.continue: 810 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 811 // CHECK1: omp.inner.for.inc: 812 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 813 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 814 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 815 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 816 // CHECK1: omp.inner.for.end: 817 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 818 // CHECK1: omp.dispatch.inc: 819 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 820 // CHECK1: omp.dispatch.end: 821 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 822 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 823 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 824 // CHECK1: .omp.linear.pu: 825 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[K1]], align 8 826 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[K_ADDR]], align 8 827 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 828 // CHECK1: .omp.linear.pu.done: 829 // CHECK1-NEXT: ret void 830 // 831 // 832 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 833 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 834 // CHECK1-NEXT: entry: 835 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 836 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 837 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 838 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 839 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 840 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 841 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 842 // CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 843 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 844 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 845 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 846 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 847 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 848 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 849 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 850 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 851 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 852 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 853 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 854 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 855 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 856 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 857 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 858 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 859 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 860 // CHECK1-NEXT: ret void 861 // 862 // 863 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 864 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 865 // CHECK1-NEXT: entry: 866 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 867 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 868 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 869 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 870 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 871 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 872 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 873 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 874 // CHECK1-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 875 // CHECK1-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 876 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 877 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 878 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 879 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 880 // CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8 881 // CHECK1-NEXT: [[LIN4:%.*]] = alloca i32, align 4 882 // CHECK1-NEXT: [[A5:%.*]] = alloca i32, align 4 883 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 884 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 885 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 886 // CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 887 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 888 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 889 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 890 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 891 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 892 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 893 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 894 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 895 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 896 // CHECK1-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 897 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 898 // CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 899 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 900 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 901 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 902 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 903 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 904 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 905 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 906 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 907 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 908 // CHECK1: cond.true: 909 // CHECK1-NEXT: br label [[COND_END:%.*]] 910 // CHECK1: cond.false: 911 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 912 // CHECK1-NEXT: br label [[COND_END]] 913 // CHECK1: cond.end: 914 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 915 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 916 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 917 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 918 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 919 // CHECK1: omp.inner.for.cond: 920 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 921 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 922 // CHECK1-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 923 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 924 // CHECK1: omp.inner.for.body: 925 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 926 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 927 // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 928 // CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 929 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 930 // CHECK1-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 931 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 932 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 933 // CHECK1-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 934 // CHECK1-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 935 // CHECK1-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 936 // CHECK1-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 937 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 938 // CHECK1-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 939 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 940 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 941 // CHECK1-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 942 // CHECK1-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 943 // CHECK1-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 944 // CHECK1-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 945 // CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 946 // CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 947 // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 948 // CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 949 // CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 950 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 951 // CHECK1: omp.body.continue: 952 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 953 // CHECK1: omp.inner.for.inc: 954 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 955 // CHECK1-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 956 // CHECK1-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 957 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 958 // CHECK1: omp.inner.for.end: 959 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 960 // CHECK1: omp.loop.exit: 961 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 962 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 963 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 964 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 965 // CHECK1: .omp.linear.pu: 966 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 967 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 968 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 969 // CHECK1-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 970 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 971 // CHECK1: .omp.linear.pu.done: 972 // CHECK1-NEXT: ret void 973 // 974 // 975 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. 976 // CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 977 // CHECK1-NEXT: entry: 978 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 979 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 980 // CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 981 // CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 982 // CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 983 // CHECK1-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 984 // CHECK1-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 985 // CHECK1-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 986 // CHECK1-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 987 // CHECK1-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 988 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 989 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 990 // CHECK1-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 991 // CHECK1-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 992 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 993 // CHECK1-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 994 // CHECK1-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 995 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 996 // CHECK1-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 997 // CHECK1-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 998 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 999 // CHECK1-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 1000 // CHECK1-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 1001 // CHECK1-NEXT: ret void 1002 // 1003 // 1004 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 1005 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 1006 // CHECK1-NEXT: entry: 1007 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 1008 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 1009 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 1010 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 1011 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 1012 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 1013 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 1014 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 1015 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 1016 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 1017 // CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 1018 // CHECK1-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8 1019 // CHECK1-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8 1020 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 1021 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 1022 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 1023 // CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 1024 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 1025 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 1026 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 1027 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 1028 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 1029 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 1030 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 1031 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 1032 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 1033 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 1034 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 1035 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 1036 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 1037 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 1038 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 1039 // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24 1040 // CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 1041 // CHECK1-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 1042 // CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24 1043 // CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 1044 // CHECK1-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 1045 // CHECK1-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 1046 // CHECK1-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 1047 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 1048 // CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 1049 // CHECK1-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 1050 // CHECK1-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 1051 // CHECK1-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 1052 // CHECK1-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24 1053 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 1054 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 1055 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 1056 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 1057 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 1058 // CHECK1-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 1059 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 1060 // CHECK1-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 1061 // CHECK1: omp_offload.failed.i: 1062 // CHECK1-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 1063 // CHECK1-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 1064 // CHECK1-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24 1065 // CHECK1-NEXT: [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24 1066 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 1067 // CHECK1-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32* 1068 // CHECK1-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !24 1069 // CHECK1-NEXT: [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !24 1070 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 1071 // CHECK1-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32* 1072 // CHECK1-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !24 1073 // CHECK1-NEXT: [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !24 1074 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR4]] 1075 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 1076 // CHECK1: .omp_outlined..3.exit: 1077 // CHECK1-NEXT: ret i32 0 1078 // 1079 // 1080 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 1081 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1082 // CHECK1-NEXT: entry: 1083 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1084 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1085 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1086 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1087 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1088 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1089 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1090 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1091 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1092 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1093 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 1094 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1095 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1096 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1097 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 1098 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1099 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 1100 // CHECK1-NEXT: ret void 1101 // 1102 // 1103 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 1104 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 1105 // CHECK1-NEXT: entry: 1106 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1107 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1108 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1109 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1110 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1111 // CHECK1-NEXT: [[TMP:%.*]] = alloca i16, align 2 1112 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1113 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1114 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1115 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1116 // CHECK1-NEXT: [[IT:%.*]] = alloca i16, align 2 1117 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1118 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1119 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1120 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1121 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1122 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1123 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1124 // CHECK1-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 1125 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1126 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1127 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1128 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1129 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1130 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1131 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 1132 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1133 // CHECK1: cond.true: 1134 // CHECK1-NEXT: br label [[COND_END:%.*]] 1135 // CHECK1: cond.false: 1136 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1137 // CHECK1-NEXT: br label [[COND_END]] 1138 // CHECK1: cond.end: 1139 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1140 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1141 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1142 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1143 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1144 // CHECK1: omp.inner.for.cond: 1145 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1146 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1147 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1148 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1149 // CHECK1: omp.inner.for.body: 1150 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1151 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 1152 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 1153 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 1154 // CHECK1-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 1155 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 1156 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 1157 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 1158 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 1159 // CHECK1-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 1160 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 1161 // CHECK1-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 1162 // CHECK1-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 1163 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1164 // CHECK1: omp.body.continue: 1165 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1166 // CHECK1: omp.inner.for.inc: 1167 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1168 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 1169 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 1170 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1171 // CHECK1: omp.inner.for.end: 1172 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1173 // CHECK1: omp.loop.exit: 1174 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 1175 // CHECK1-NEXT: ret void 1176 // 1177 // 1178 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 1179 // CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 1180 // CHECK1-NEXT: entry: 1181 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1182 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1183 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1184 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1185 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1186 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1187 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1188 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1189 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1190 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1191 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1192 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1193 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1194 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1195 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1196 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1197 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1198 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1199 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1200 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1201 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1202 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 1203 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1204 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1205 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1206 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1207 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1208 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1209 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1210 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1211 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1212 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 1213 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 1214 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1215 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 1216 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 1217 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 1218 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 1219 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 1220 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 1221 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 1222 // CHECK1-NEXT: ret void 1223 // 1224 // 1225 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 1226 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 1227 // CHECK1-NEXT: entry: 1228 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1229 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1230 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1231 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1232 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1233 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1234 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1235 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1236 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1237 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1238 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1239 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1240 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1241 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 1242 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1243 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1244 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1245 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1246 // CHECK1-NEXT: [[IT:%.*]] = alloca i8, align 1 1247 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1248 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1249 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1250 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1251 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1252 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1253 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1254 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1255 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1256 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1257 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1258 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 1259 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1260 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1261 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1262 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1263 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1264 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1265 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1266 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1267 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1268 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 1269 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1270 // CHECK1-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 1271 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1272 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1273 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 1274 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1275 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 1276 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 1277 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1278 // CHECK1: omp.dispatch.cond: 1279 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1280 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 1281 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1282 // CHECK1: cond.true: 1283 // CHECK1-NEXT: br label [[COND_END:%.*]] 1284 // CHECK1: cond.false: 1285 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1286 // CHECK1-NEXT: br label [[COND_END]] 1287 // CHECK1: cond.end: 1288 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 1289 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1290 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1291 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 1292 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1293 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1294 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 1295 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1296 // CHECK1: omp.dispatch.body: 1297 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1298 // CHECK1: omp.inner.for.cond: 1299 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1300 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1301 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 1302 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1303 // CHECK1: omp.inner.for.body: 1304 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1305 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 1306 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 1307 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 1308 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 1309 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 1310 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 1311 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1312 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 1313 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 1314 // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 1315 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 1316 // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 1317 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 1318 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 1319 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 1320 // CHECK1-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 1321 // CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 1322 // CHECK1-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 1323 // CHECK1-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 1324 // CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 1325 // CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 1326 // CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 1327 // CHECK1-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 1328 // CHECK1-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 1329 // CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 1330 // CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 1331 // CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 1332 // CHECK1-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 1333 // CHECK1-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 1334 // CHECK1-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 1335 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 1336 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 1337 // CHECK1-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 1338 // CHECK1-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 1339 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 1340 // CHECK1-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 1341 // CHECK1-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 1342 // CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 1343 // CHECK1-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 1344 // CHECK1-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 1345 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1346 // CHECK1: omp.body.continue: 1347 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1348 // CHECK1: omp.inner.for.inc: 1349 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1350 // CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 1351 // CHECK1-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 1352 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1353 // CHECK1: omp.inner.for.end: 1354 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1355 // CHECK1: omp.dispatch.inc: 1356 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1357 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1358 // CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 1359 // CHECK1-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 1360 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1361 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1362 // CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 1363 // CHECK1-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 1364 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1365 // CHECK1: omp.dispatch.end: 1366 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 1367 // CHECK1-NEXT: ret void 1368 // 1369 // 1370 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 1371 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1372 // CHECK1-NEXT: entry: 1373 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1374 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1375 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1376 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1377 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1378 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1379 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 1380 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1381 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1382 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1383 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1384 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 1385 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1386 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1387 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1388 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1389 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 1390 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1391 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1392 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 1393 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1394 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 1395 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 1396 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1397 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 1398 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 1399 // CHECK1-NEXT: ret i32 [[TMP8]] 1400 // 1401 // 1402 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1403 // CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1404 // CHECK1-NEXT: entry: 1405 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1406 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1407 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 1408 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1409 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1410 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1411 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1412 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1413 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1414 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1415 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1416 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1417 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1418 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1419 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1420 // CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4 1421 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1422 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1423 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 1424 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 1425 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 1426 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 1427 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1428 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 1429 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1430 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 1431 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 1432 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 1433 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 1434 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1435 // CHECK1: omp_if.then: 1436 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 1437 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 1438 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 1439 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1440 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 1441 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 1442 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1443 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 1444 // CHECK1-NEXT: store double* [[A]], double** [[TMP13]], align 8 1445 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1446 // CHECK1-NEXT: store i64 8, i64* [[TMP14]], align 8 1447 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1448 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8 1449 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1450 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 1451 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 1452 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1453 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1454 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 1455 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 1456 // CHECK1-NEXT: store i64 4, i64* [[TMP20]], align 8 1457 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1458 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 1459 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1460 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 1461 // CHECK1-NEXT: store i64 2, i64* [[TMP23]], align 8 1462 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1463 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 1464 // CHECK1-NEXT: store i64 2, i64* [[TMP25]], align 8 1465 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 1466 // CHECK1-NEXT: store i64 8, i64* [[TMP26]], align 8 1467 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1468 // CHECK1-NEXT: store i8* null, i8** [[TMP27]], align 8 1469 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1470 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1471 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 1472 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1473 // CHECK1-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 1474 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 1475 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 1476 // CHECK1-NEXT: store i64 8, i64* [[TMP32]], align 8 1477 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1478 // CHECK1-NEXT: store i8* null, i8** [[TMP33]], align 8 1479 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1480 // CHECK1-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 1481 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 1482 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1483 // CHECK1-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 1484 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 1485 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1486 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 1487 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1488 // CHECK1-NEXT: store i8* null, i8** [[TMP39]], align 8 1489 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1490 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1491 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1492 // CHECK1-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1493 // CHECK1-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 1494 // CHECK1-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1495 // CHECK1: omp_offload.failed: 1496 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 1497 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1498 // CHECK1: omp_offload.cont: 1499 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1500 // CHECK1: omp_if.else: 1501 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 1502 // CHECK1-NEXT: br label [[OMP_IF_END]] 1503 // CHECK1: omp_if.end: 1504 // CHECK1-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] 1505 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] 1506 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1507 // CHECK1-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 1508 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 1509 // CHECK1-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 1510 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] 1511 // CHECK1-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1512 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 1513 // CHECK1-NEXT: ret i32 [[ADD4]] 1514 // 1515 // 1516 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 1517 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1518 // CHECK1-NEXT: entry: 1519 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1520 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1521 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1522 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 1523 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1524 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1525 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1526 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1527 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1528 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1529 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1530 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1531 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1532 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1533 // CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1 1534 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1535 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1536 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1537 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1538 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1539 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1540 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1541 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1542 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 1543 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1544 // CHECK1-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 1545 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1546 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1547 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 1548 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1549 // CHECK1: omp_if.then: 1550 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1551 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1552 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1553 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1554 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 1555 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 1556 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1557 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8 1558 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1559 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1560 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1561 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1562 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 1563 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 1564 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1565 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8 1566 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1567 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 1568 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 1569 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1570 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 1571 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 1572 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1573 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 1574 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1575 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 1576 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 1577 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1578 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 1579 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 1580 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1581 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8 1582 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1583 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1584 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1585 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1586 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1587 // CHECK1: omp_offload.failed: 1588 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 1589 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1590 // CHECK1: omp_offload.cont: 1591 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1592 // CHECK1: omp_if.else: 1593 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 1594 // CHECK1-NEXT: br label [[OMP_IF_END]] 1595 // CHECK1: omp_if.end: 1596 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 1597 // CHECK1-NEXT: ret i32 [[TMP31]] 1598 // 1599 // 1600 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1601 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1602 // CHECK1-NEXT: entry: 1603 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1604 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1605 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1606 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1607 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1608 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1609 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1610 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1611 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1612 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1613 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1614 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1615 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1616 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1617 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1618 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1619 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1620 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1621 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1622 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1623 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1624 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1625 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1626 // CHECK1: omp_if.then: 1627 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1628 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 1629 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 1630 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1631 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1632 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1633 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1634 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 1635 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1636 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 1637 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 1638 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1639 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1640 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1641 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1642 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 1643 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1644 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 1645 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 1646 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1647 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 1648 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 1649 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1650 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 1651 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1652 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1653 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1654 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 1655 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1656 // CHECK1: omp_offload.failed: 1657 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1658 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1659 // CHECK1: omp_offload.cont: 1660 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1661 // CHECK1: omp_if.else: 1662 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1663 // CHECK1-NEXT: br label [[OMP_IF_END]] 1664 // CHECK1: omp_if.end: 1665 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 1666 // CHECK1-NEXT: ret i32 [[TMP24]] 1667 // 1668 // 1669 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 1670 // CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1671 // CHECK1-NEXT: entry: 1672 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1673 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1674 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1675 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1676 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1677 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1678 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1679 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1680 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1681 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1682 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1683 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1684 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1685 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1686 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1687 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1688 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1689 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1690 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 1691 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 1692 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 1693 // CHECK1-NEXT: ret void 1694 // 1695 // 1696 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 1697 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 1698 // CHECK1-NEXT: entry: 1699 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1700 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1701 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1702 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1703 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1704 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1705 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1706 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1707 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 1708 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1709 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1710 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1711 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1712 // CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8 1713 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1714 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1715 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1716 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1717 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1718 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1719 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1720 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1721 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1722 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1723 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1724 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1725 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1726 // CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 1727 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1728 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1729 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1730 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1731 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1732 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1733 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 1734 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1735 // CHECK1: cond.true: 1736 // CHECK1-NEXT: br label [[COND_END:%.*]] 1737 // CHECK1: cond.false: 1738 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1739 // CHECK1-NEXT: br label [[COND_END]] 1740 // CHECK1: cond.end: 1741 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1742 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1743 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1744 // CHECK1-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 1745 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1746 // CHECK1: omp.inner.for.cond: 1747 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1748 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1749 // CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 1750 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1751 // CHECK1: omp.inner.for.body: 1752 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1753 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 1754 // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 1755 // CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 1756 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 1757 // CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 1758 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 1759 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1760 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 1761 // CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1762 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 1763 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 1764 // CHECK1-NEXT: store double [[INC]], double* [[A5]], align 8 1765 // CHECK1-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 1766 // CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 1767 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 1768 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1769 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 1770 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1771 // CHECK1: omp.body.continue: 1772 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1773 // CHECK1: omp.inner.for.inc: 1774 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1775 // CHECK1-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 1776 // CHECK1-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 1777 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1778 // CHECK1: omp.inner.for.end: 1779 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1780 // CHECK1: omp.loop.exit: 1781 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1782 // CHECK1-NEXT: ret void 1783 // 1784 // 1785 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 1786 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1787 // CHECK1-NEXT: entry: 1788 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1789 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1790 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1791 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1792 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1793 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1794 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1795 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1796 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1797 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1798 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1799 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1800 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1801 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1802 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1803 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1804 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1805 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 1806 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1807 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1808 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1809 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 1810 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1811 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 1812 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1813 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 1814 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1815 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 1816 // CHECK1-NEXT: ret void 1817 // 1818 // 1819 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 1820 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1821 // CHECK1-NEXT: entry: 1822 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1823 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1824 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1825 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1826 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1827 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1828 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1829 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1830 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1831 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1832 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1833 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1834 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1835 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1836 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1837 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1838 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1839 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1840 // CHECK1-NEXT: ret void 1841 // 1842 // 1843 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 1844 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1845 // CHECK1-NEXT: entry: 1846 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1847 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1848 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1849 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1850 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1851 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1852 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1853 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1854 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1855 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1856 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1857 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1858 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1859 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 1860 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1861 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1862 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1863 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 1864 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1865 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 1866 // CHECK1-NEXT: ret void 1867 // 1868 // 1869 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 1870 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1871 // CHECK1-NEXT: entry: 1872 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1873 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1874 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1875 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1876 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1877 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1878 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 1879 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1880 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1881 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1882 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1883 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 1884 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1885 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1886 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1887 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1888 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1889 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1890 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1891 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1892 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1893 // CHECK1-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 1894 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1895 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1896 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1897 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1898 // CHECK1-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1899 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1900 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 1901 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1902 // CHECK1: cond.true: 1903 // CHECK1-NEXT: br label [[COND_END:%.*]] 1904 // CHECK1: cond.false: 1905 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1906 // CHECK1-NEXT: br label [[COND_END]] 1907 // CHECK1: cond.end: 1908 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1909 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1910 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1911 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 1912 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1913 // CHECK1: omp.inner.for.cond: 1914 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1915 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1916 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 1917 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1918 // CHECK1: omp.inner.for.body: 1919 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1920 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 1921 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 1922 // CHECK1-NEXT: store i64 [[ADD]], i64* [[I]], align 8 1923 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 1924 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 1925 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 1926 // CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 1927 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 1928 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 1929 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 1930 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 1931 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1932 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1933 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 1934 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 1935 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1936 // CHECK1: omp.body.continue: 1937 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1938 // CHECK1: omp.inner.for.inc: 1939 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1940 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 1941 // CHECK1-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 1942 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1943 // CHECK1: omp.inner.for.end: 1944 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1945 // CHECK1: omp.loop.exit: 1946 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1947 // CHECK1-NEXT: ret void 1948 // 1949 // 1950 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1951 // CHECK1-SAME: () #[[ATTR6]] { 1952 // CHECK1-NEXT: entry: 1953 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1954 // CHECK1-NEXT: ret void 1955 // 1956 // 1957 // CHECK2-LABEL: define {{[^@]+}}@_Z7get_valv 1958 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 1959 // CHECK2-NEXT: entry: 1960 // CHECK2-NEXT: ret i64 0 1961 // 1962 // 1963 // CHECK2-LABEL: define {{[^@]+}}@_Z3fooi 1964 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1965 // CHECK2-NEXT: entry: 1966 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1967 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 1968 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 1969 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x float], align 4 1970 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1971 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1972 // CHECK2-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 1973 // CHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 1974 // CHECK2-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 1975 // CHECK2-NEXT: [[K:%.*]] = alloca i64, align 8 1976 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1977 // CHECK2-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 1978 // CHECK2-NEXT: [[LIN:%.*]] = alloca i32, align 4 1979 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1980 // CHECK2-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 1981 // CHECK2-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8 1982 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1983 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1984 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1985 // CHECK2-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 1986 // CHECK2-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8 1987 // CHECK2-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8 1988 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 1989 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 1990 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 1991 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1992 // CHECK2-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8 1993 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1994 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8 1995 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8 1996 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8 1997 // CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 1998 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 1999 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2000 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 2001 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 2002 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2003 // CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 2004 // CHECK2-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 2005 // CHECK2-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 2006 // CHECK2-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 2007 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 2008 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2009 // CHECK2-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 2010 // CHECK2-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 2011 // CHECK2-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 2012 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 2013 // CHECK2-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 2014 // CHECK2-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 2015 // CHECK2-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2016 // CHECK2: omp_offload.failed: 2017 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 2018 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 2019 // CHECK2: omp_offload.cont: 2020 // CHECK2-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 2021 // CHECK2-NEXT: store i64 [[CALL]], i64* [[K]], align 8 2022 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 2023 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2024 // CHECK2-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4 2025 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8 2026 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[K]], align 8 2027 // CHECK2-NEXT: store i64 [[TMP11]], i64* [[K_CASTED]], align 8 2028 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8 2029 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR4]] 2030 // CHECK2-NEXT: store i32 12, i32* [[LIN]], align 4 2031 // CHECK2-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 2032 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2033 // CHECK2-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 2034 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2035 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4 2036 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 2037 // CHECK2-NEXT: store i32 [[TMP15]], i32* [[CONV3]], align 4 2038 // CHECK2-NEXT: [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 2039 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 2040 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32* 2041 // CHECK2-NEXT: store i32 [[TMP17]], i32* [[CONV5]], align 4 2042 // CHECK2-NEXT: [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8 2043 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2044 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 2045 // CHECK2-NEXT: store i64 [[TMP14]], i64* [[TMP20]], align 8 2046 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2047 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 2048 // CHECK2-NEXT: store i64 [[TMP14]], i64* [[TMP22]], align 8 2049 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2050 // CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8 2051 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2052 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 2053 // CHECK2-NEXT: store i64 [[TMP16]], i64* [[TMP25]], align 8 2054 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2055 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 2056 // CHECK2-NEXT: store i64 [[TMP16]], i64* [[TMP27]], align 8 2057 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2058 // CHECK2-NEXT: store i8* null, i8** [[TMP28]], align 8 2059 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2060 // CHECK2-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 2061 // CHECK2-NEXT: store i64 [[TMP18]], i64* [[TMP30]], align 8 2062 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2063 // CHECK2-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 2064 // CHECK2-NEXT: store i64 [[TMP18]], i64* [[TMP32]], align 8 2065 // CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2066 // CHECK2-NEXT: store i8* null, i8** [[TMP33]], align 8 2067 // CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2068 // CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2069 // CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 2070 // CHECK2-NEXT: [[TMP37:%.*]] = load i16, i16* [[AA]], align 2 2071 // CHECK2-NEXT: store i16 [[TMP37]], i16* [[TMP36]], align 4 2072 // CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 2073 // CHECK2-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4 2074 // CHECK2-NEXT: store i32 [[TMP39]], i32* [[TMP38]], align 4 2075 // CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 2076 // CHECK2-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 2077 // CHECK2-NEXT: store i32 [[TMP41]], i32* [[TMP40]], align 4 2078 // CHECK2-NEXT: [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 2079 // CHECK2-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates* 2080 // CHECK2-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0 2081 // CHECK2-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0 2082 // CHECK2-NEXT: [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8 2083 // CHECK2-NEXT: [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 2084 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false) 2085 // CHECK2-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1 2086 // CHECK2-NEXT: [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon* 2087 // CHECK2-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0 2088 // CHECK2-NEXT: [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8* 2089 // CHECK2-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8* 2090 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false) 2091 // CHECK2-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1 2092 // CHECK2-NEXT: [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8* 2093 // CHECK2-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8* 2094 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false) 2095 // CHECK2-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2 2096 // CHECK2-NEXT: [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8* 2097 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 2098 // CHECK2-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3 2099 // CHECK2-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 2100 // CHECK2-NEXT: store i16 [[TMP59]], i16* [[TMP58]], align 8 2101 // CHECK2-NEXT: [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]]) 2102 // CHECK2-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4 2103 // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32* 2104 // CHECK2-NEXT: store i32 [[TMP61]], i32* [[CONV7]], align 4 2105 // CHECK2-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8 2106 // CHECK2-NEXT: [[TMP63:%.*]] = load i16, i16* [[AA]], align 2 2107 // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16* 2108 // CHECK2-NEXT: store i16 [[TMP63]], i16* [[CONV9]], align 2 2109 // CHECK2-NEXT: [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8 2110 // CHECK2-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4 2111 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10 2112 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2113 // CHECK2: omp_if.then: 2114 // CHECK2-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 2115 // CHECK2-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64* 2116 // CHECK2-NEXT: store i64 [[TMP62]], i64* [[TMP67]], align 8 2117 // CHECK2-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 2118 // CHECK2-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* 2119 // CHECK2-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8 2120 // CHECK2-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 2121 // CHECK2-NEXT: store i8* null, i8** [[TMP70]], align 8 2122 // CHECK2-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 2123 // CHECK2-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* 2124 // CHECK2-NEXT: store i64 [[TMP64]], i64* [[TMP72]], align 8 2125 // CHECK2-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 2126 // CHECK2-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* 2127 // CHECK2-NEXT: store i64 [[TMP64]], i64* [[TMP74]], align 8 2128 // CHECK2-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 2129 // CHECK2-NEXT: store i8* null, i8** [[TMP75]], align 8 2130 // CHECK2-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 2131 // CHECK2-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 2132 // CHECK2-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2133 // CHECK2-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0 2134 // CHECK2-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]] 2135 // CHECK2: omp_offload.failed13: 2136 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 2137 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT14]] 2138 // CHECK2: omp_offload.cont14: 2139 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 2140 // CHECK2: omp_if.else: 2141 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 2142 // CHECK2-NEXT: br label [[OMP_IF_END]] 2143 // CHECK2: omp_if.end: 2144 // CHECK2-NEXT: [[TMP80:%.*]] = load i32, i32* [[A]], align 4 2145 // CHECK2-NEXT: store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4 2146 // CHECK2-NEXT: [[TMP81:%.*]] = load i32, i32* [[A]], align 4 2147 // CHECK2-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32* 2148 // CHECK2-NEXT: store i32 [[TMP81]], i32* [[CONV16]], align 4 2149 // CHECK2-NEXT: [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8 2150 // CHECK2-NEXT: [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2151 // CHECK2-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 2152 // CHECK2-NEXT: store i32 [[TMP83]], i32* [[CONV17]], align 4 2153 // CHECK2-NEXT: [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 2154 // CHECK2-NEXT: [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4 2155 // CHECK2-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20 2156 // CHECK2-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 2157 // CHECK2: omp_if.then19: 2158 // CHECK2-NEXT: [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4 2159 // CHECK2-NEXT: [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]] 2160 // CHECK2-NEXT: [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8 2161 // CHECK2-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 2162 // CHECK2-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* 2163 // CHECK2-NEXT: store i64 [[TMP82]], i64* [[TMP90]], align 8 2164 // CHECK2-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 2165 // CHECK2-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i64* 2166 // CHECK2-NEXT: store i64 [[TMP82]], i64* [[TMP92]], align 8 2167 // CHECK2-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2168 // CHECK2-NEXT: store i64 4, i64* [[TMP93]], align 8 2169 // CHECK2-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 2170 // CHECK2-NEXT: store i8* null, i8** [[TMP94]], align 8 2171 // CHECK2-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 2172 // CHECK2-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 2173 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8 2174 // CHECK2-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 2175 // CHECK2-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]** 2176 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8 2177 // CHECK2-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 2178 // CHECK2-NEXT: store i64 40, i64* [[TMP99]], align 8 2179 // CHECK2-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 2180 // CHECK2-NEXT: store i8* null, i8** [[TMP100]], align 8 2181 // CHECK2-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 2182 // CHECK2-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i64* 2183 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP102]], align 8 2184 // CHECK2-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 2185 // CHECK2-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to i64* 2186 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP104]], align 8 2187 // CHECK2-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 2188 // CHECK2-NEXT: store i64 8, i64* [[TMP105]], align 8 2189 // CHECK2-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 2190 // CHECK2-NEXT: store i8* null, i8** [[TMP106]], align 8 2191 // CHECK2-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 2192 // CHECK2-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** 2193 // CHECK2-NEXT: store float* [[VLA]], float** [[TMP108]], align 8 2194 // CHECK2-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 2195 // CHECK2-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to float** 2196 // CHECK2-NEXT: store float* [[VLA]], float** [[TMP110]], align 8 2197 // CHECK2-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 2198 // CHECK2-NEXT: store i64 [[TMP86]], i64* [[TMP111]], align 8 2199 // CHECK2-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 2200 // CHECK2-NEXT: store i8* null, i8** [[TMP112]], align 8 2201 // CHECK2-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 2202 // CHECK2-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** 2203 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8 2204 // CHECK2-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 2205 // CHECK2-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to [5 x [10 x double]]** 2206 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP116]], align 8 2207 // CHECK2-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 2208 // CHECK2-NEXT: store i64 400, i64* [[TMP117]], align 8 2209 // CHECK2-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 2210 // CHECK2-NEXT: store i8* null, i8** [[TMP118]], align 8 2211 // CHECK2-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 2212 // CHECK2-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i64* 2213 // CHECK2-NEXT: store i64 5, i64* [[TMP120]], align 8 2214 // CHECK2-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 2215 // CHECK2-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64* 2216 // CHECK2-NEXT: store i64 5, i64* [[TMP122]], align 8 2217 // CHECK2-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 2218 // CHECK2-NEXT: store i64 8, i64* [[TMP123]], align 8 2219 // CHECK2-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5 2220 // CHECK2-NEXT: store i8* null, i8** [[TMP124]], align 8 2221 // CHECK2-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 2222 // CHECK2-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* 2223 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP126]], align 8 2224 // CHECK2-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 2225 // CHECK2-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* 2226 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP128]], align 8 2227 // CHECK2-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 2228 // CHECK2-NEXT: store i64 8, i64* [[TMP129]], align 8 2229 // CHECK2-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6 2230 // CHECK2-NEXT: store i8* null, i8** [[TMP130]], align 8 2231 // CHECK2-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 2232 // CHECK2-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double** 2233 // CHECK2-NEXT: store double* [[VLA1]], double** [[TMP132]], align 8 2234 // CHECK2-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 2235 // CHECK2-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to double** 2236 // CHECK2-NEXT: store double* [[VLA1]], double** [[TMP134]], align 8 2237 // CHECK2-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 2238 // CHECK2-NEXT: store i64 [[TMP88]], i64* [[TMP135]], align 8 2239 // CHECK2-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7 2240 // CHECK2-NEXT: store i8* null, i8** [[TMP136]], align 8 2241 // CHECK2-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 2242 // CHECK2-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT** 2243 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 8 2244 // CHECK2-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 2245 // CHECK2-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to %struct.TT** 2246 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP140]], align 8 2247 // CHECK2-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 2248 // CHECK2-NEXT: store i64 16, i64* [[TMP141]], align 8 2249 // CHECK2-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8 2250 // CHECK2-NEXT: store i8* null, i8** [[TMP142]], align 8 2251 // CHECK2-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9 2252 // CHECK2-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i64* 2253 // CHECK2-NEXT: store i64 [[TMP84]], i64* [[TMP144]], align 8 2254 // CHECK2-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9 2255 // CHECK2-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to i64* 2256 // CHECK2-NEXT: store i64 [[TMP84]], i64* [[TMP146]], align 8 2257 // CHECK2-NEXT: [[TMP147:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 2258 // CHECK2-NEXT: store i64 4, i64* [[TMP147]], align 8 2259 // CHECK2-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9 2260 // CHECK2-NEXT: store i8* null, i8** [[TMP148]], align 8 2261 // CHECK2-NEXT: [[TMP149:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 2262 // CHECK2-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 2263 // CHECK2-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2264 // CHECK2-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2265 // CHECK2-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 2266 // CHECK2-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 2267 // CHECK2: omp_offload.failed23: 2268 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 2269 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT24]] 2270 // CHECK2: omp_offload.cont24: 2271 // CHECK2-NEXT: br label [[OMP_IF_END26:%.*]] 2272 // CHECK2: omp_if.else25: 2273 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 2274 // CHECK2-NEXT: br label [[OMP_IF_END26]] 2275 // CHECK2: omp_if.end26: 2276 // CHECK2-NEXT: [[TMP154:%.*]] = load i32, i32* [[A]], align 4 2277 // CHECK2-NEXT: [[TMP155:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 2278 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP155]]) 2279 // CHECK2-NEXT: ret i32 [[TMP154]] 2280 // 2281 // 2282 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 2283 // CHECK2-SAME: () #[[ATTR2:[0-9]+]] { 2284 // CHECK2-NEXT: entry: 2285 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2286 // CHECK2-NEXT: ret void 2287 // 2288 // 2289 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 2290 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 2291 // CHECK2-NEXT: entry: 2292 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2293 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2294 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2295 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 2296 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2297 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2298 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2299 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2300 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 2301 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2302 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2303 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2304 // CHECK2-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 2305 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2306 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2307 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2308 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2309 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2310 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2311 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 2312 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2313 // CHECK2: cond.true: 2314 // CHECK2-NEXT: br label [[COND_END:%.*]] 2315 // CHECK2: cond.false: 2316 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2317 // CHECK2-NEXT: br label [[COND_END]] 2318 // CHECK2: cond.end: 2319 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2320 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2321 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2322 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2323 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2324 // CHECK2: omp.inner.for.cond: 2325 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2326 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2327 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2328 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2329 // CHECK2: omp.inner.for.body: 2330 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2331 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 2332 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 2333 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2334 // CHECK2-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 2335 // CHECK2-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 2336 // CHECK2-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 2337 // CHECK2: .cancel.exit: 2338 // CHECK2-NEXT: br label [[CANCEL_EXIT:%.*]] 2339 // CHECK2: .cancel.continue: 2340 // CHECK2-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 2341 // CHECK2-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 2342 // CHECK2-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 2343 // CHECK2: .cancel.exit2: 2344 // CHECK2-NEXT: br label [[CANCEL_EXIT]] 2345 // CHECK2: .cancel.continue3: 2346 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2347 // CHECK2: omp.body.continue: 2348 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2349 // CHECK2: omp.inner.for.inc: 2350 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2351 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 2352 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 2353 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 2354 // CHECK2: omp.inner.for.end: 2355 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2356 // CHECK2: omp.loop.exit: 2357 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2358 // CHECK2-NEXT: br label [[CANCEL_CONT:%.*]] 2359 // CHECK2: cancel.cont: 2360 // CHECK2-NEXT: ret void 2361 // CHECK2: cancel.exit: 2362 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2363 // CHECK2-NEXT: br label [[CANCEL_CONT]] 2364 // 2365 // 2366 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 2367 // CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 2368 // CHECK2-NEXT: entry: 2369 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2370 // CHECK2-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 2371 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2372 // CHECK2-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 2373 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2374 // CHECK2-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 2375 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2376 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 2377 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2378 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 2379 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 2380 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 2381 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 2382 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 2383 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 2384 // CHECK2-NEXT: ret void 2385 // 2386 // 2387 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 2388 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 2389 // CHECK2-NEXT: entry: 2390 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2391 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2392 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2393 // CHECK2-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 2394 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2395 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 2396 // CHECK2-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 2397 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2398 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2399 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2400 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2401 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 2402 // CHECK2-NEXT: [[K1:%.*]] = alloca i64, align 8 2403 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2404 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2405 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2406 // CHECK2-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 2407 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2408 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8 2409 // CHECK2-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8 2410 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2411 // CHECK2-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 2412 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2413 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2414 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2415 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2416 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 2417 // CHECK2-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1) 2418 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2419 // CHECK2: omp.dispatch.cond: 2420 // CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 2421 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 2422 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2423 // CHECK2: omp.dispatch.body: 2424 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2425 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2426 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2427 // CHECK2: omp.inner.for.cond: 2428 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2429 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 2430 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2431 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2432 // CHECK2: omp.inner.for.body: 2433 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2434 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2435 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 2436 // CHECK2-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12 2437 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12 2438 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2439 // CHECK2-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 2440 // CHECK2-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 2441 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] 2442 // CHECK2-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12 2443 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12 2444 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 2445 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12 2446 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2447 // CHECK2: omp.body.continue: 2448 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2449 // CHECK2: omp.inner.for.inc: 2450 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2451 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 2452 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2453 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 2454 // CHECK2: omp.inner.for.end: 2455 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2456 // CHECK2: omp.dispatch.inc: 2457 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 2458 // CHECK2: omp.dispatch.end: 2459 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2460 // CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 2461 // CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 2462 // CHECK2: .omp.linear.pu: 2463 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[K1]], align 8 2464 // CHECK2-NEXT: store i64 [[TMP14]], i64* [[K_ADDR]], align 8 2465 // CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 2466 // CHECK2: .omp.linear.pu.done: 2467 // CHECK2-NEXT: ret void 2468 // 2469 // 2470 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 2471 // CHECK2-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 2472 // CHECK2-NEXT: entry: 2473 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2474 // CHECK2-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 2475 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2476 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2477 // CHECK2-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 2478 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2479 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2480 // CHECK2-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 2481 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2482 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2483 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 2484 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2485 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2486 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2487 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 2488 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2489 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 2490 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 2491 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 2492 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 2493 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 2494 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2495 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 2496 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 2497 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 2498 // CHECK2-NEXT: ret void 2499 // 2500 // 2501 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 2502 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 2503 // CHECK2-NEXT: entry: 2504 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2505 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2506 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2507 // CHECK2-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 2508 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2509 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2510 // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 2511 // CHECK2-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 2512 // CHECK2-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 2513 // CHECK2-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 2514 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2515 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2516 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2517 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2518 // CHECK2-NEXT: [[IT:%.*]] = alloca i64, align 8 2519 // CHECK2-NEXT: [[LIN4:%.*]] = alloca i32, align 4 2520 // CHECK2-NEXT: [[A5:%.*]] = alloca i32, align 4 2521 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2522 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2523 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2524 // CHECK2-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 2525 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2526 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2527 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 2528 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2529 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 2530 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 2531 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 2532 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 2533 // CHECK2-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 2534 // CHECK2-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 2535 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2536 // CHECK2-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 2537 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2538 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2539 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2540 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2541 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 2542 // CHECK2-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 2543 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2544 // CHECK2-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 2545 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2546 // CHECK2: cond.true: 2547 // CHECK2-NEXT: br label [[COND_END:%.*]] 2548 // CHECK2: cond.false: 2549 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2550 // CHECK2-NEXT: br label [[COND_END]] 2551 // CHECK2: cond.end: 2552 // CHECK2-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2553 // CHECK2-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 2554 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2555 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 2556 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2557 // CHECK2: omp.inner.for.cond: 2558 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2559 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2560 // CHECK2-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 2561 // CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2562 // CHECK2: omp.inner.for.body: 2563 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2564 // CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 2565 // CHECK2-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 2566 // CHECK2-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 2567 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 2568 // CHECK2-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 2569 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2570 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 2571 // CHECK2-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 2572 // CHECK2-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 2573 // CHECK2-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 2574 // CHECK2-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 2575 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 2576 // CHECK2-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 2577 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2578 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 2579 // CHECK2-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 2580 // CHECK2-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 2581 // CHECK2-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 2582 // CHECK2-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 2583 // CHECK2-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 2584 // CHECK2-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 2585 // CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 2586 // CHECK2-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 2587 // CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 2588 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2589 // CHECK2: omp.body.continue: 2590 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2591 // CHECK2: omp.inner.for.inc: 2592 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2593 // CHECK2-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 2594 // CHECK2-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 2595 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 2596 // CHECK2: omp.inner.for.end: 2597 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2598 // CHECK2: omp.loop.exit: 2599 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 2600 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2601 // CHECK2-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 2602 // CHECK2-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 2603 // CHECK2: .omp.linear.pu: 2604 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 2605 // CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 2606 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 2607 // CHECK2-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 2608 // CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 2609 // CHECK2: .omp.linear.pu.done: 2610 // CHECK2-NEXT: ret void 2611 // 2612 // 2613 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. 2614 // CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 2615 // CHECK2-NEXT: entry: 2616 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 2617 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 2618 // CHECK2-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 2619 // CHECK2-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 2620 // CHECK2-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 2621 // CHECK2-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 2622 // CHECK2-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 2623 // CHECK2-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 2624 // CHECK2-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 2625 // CHECK2-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 2626 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 2627 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 2628 // CHECK2-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 2629 // CHECK2-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 2630 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 2631 // CHECK2-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 2632 // CHECK2-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 2633 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 2634 // CHECK2-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 2635 // CHECK2-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 2636 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 2637 // CHECK2-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 2638 // CHECK2-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 2639 // CHECK2-NEXT: ret void 2640 // 2641 // 2642 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. 2643 // CHECK2-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 2644 // CHECK2-NEXT: entry: 2645 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 2646 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 2647 // CHECK2-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 2648 // CHECK2-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 2649 // CHECK2-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 2650 // CHECK2-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 2651 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 2652 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 2653 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 2654 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 2655 // CHECK2-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 2656 // CHECK2-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8 2657 // CHECK2-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8 2658 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 2659 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 2660 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 2661 // CHECK2-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 2662 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 2663 // CHECK2-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 2664 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 2665 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 2666 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 2667 // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 2668 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 2669 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 2670 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 2671 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 2672 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 2673 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 2674 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 2675 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 2676 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 2677 // CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24 2678 // CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 2679 // CHECK2-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 2680 // CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24 2681 // CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 2682 // CHECK2-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 2683 // CHECK2-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 2684 // CHECK2-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 2685 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 2686 // CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 2687 // CHECK2-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 2688 // CHECK2-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 2689 // CHECK2-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 2690 // CHECK2-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24 2691 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 2692 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 2693 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 2694 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 2695 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 2696 // CHECK2-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 2697 // CHECK2-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 2698 // CHECK2-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 2699 // CHECK2: omp_offload.failed.i: 2700 // CHECK2-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 2701 // CHECK2-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 2702 // CHECK2-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24 2703 // CHECK2-NEXT: [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24 2704 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 2705 // CHECK2-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32* 2706 // CHECK2-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !24 2707 // CHECK2-NEXT: [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !24 2708 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 2709 // CHECK2-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32* 2710 // CHECK2-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !24 2711 // CHECK2-NEXT: [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !24 2712 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR4]] 2713 // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 2714 // CHECK2: .omp_outlined..3.exit: 2715 // CHECK2-NEXT: ret i32 0 2716 // 2717 // 2718 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 2719 // CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 2720 // CHECK2-NEXT: entry: 2721 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2722 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2723 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2724 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2725 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2726 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2727 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2728 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2729 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 2730 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2731 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 2732 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 2733 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 2734 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2735 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 2736 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2737 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 2738 // CHECK2-NEXT: ret void 2739 // 2740 // 2741 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 2742 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 2743 // CHECK2-NEXT: entry: 2744 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2745 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2746 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2747 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2748 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2749 // CHECK2-NEXT: [[TMP:%.*]] = alloca i16, align 2 2750 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2751 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2752 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2753 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2754 // CHECK2-NEXT: [[IT:%.*]] = alloca i16, align 2 2755 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2756 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2757 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2758 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2759 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2760 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2761 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2762 // CHECK2-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 2763 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2764 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2765 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2766 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2767 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2768 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2769 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 2770 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2771 // CHECK2: cond.true: 2772 // CHECK2-NEXT: br label [[COND_END:%.*]] 2773 // CHECK2: cond.false: 2774 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2775 // CHECK2-NEXT: br label [[COND_END]] 2776 // CHECK2: cond.end: 2777 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2778 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2779 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2780 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2781 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2782 // CHECK2: omp.inner.for.cond: 2783 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2784 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2785 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2786 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2787 // CHECK2: omp.inner.for.body: 2788 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2789 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 2790 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 2791 // CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 2792 // CHECK2-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 2793 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 2794 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 2795 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 2796 // CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 2797 // CHECK2-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 2798 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 2799 // CHECK2-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 2800 // CHECK2-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 2801 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2802 // CHECK2: omp.body.continue: 2803 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2804 // CHECK2: omp.inner.for.inc: 2805 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2806 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 2807 // CHECK2-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 2808 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 2809 // CHECK2: omp.inner.for.end: 2810 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2811 // CHECK2: omp.loop.exit: 2812 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2813 // CHECK2-NEXT: ret void 2814 // 2815 // 2816 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 2817 // CHECK2-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 2818 // CHECK2-NEXT: entry: 2819 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2820 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 2821 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2822 // CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 2823 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 2824 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2825 // CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 2826 // CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 2827 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 2828 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2829 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2830 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 2831 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2832 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 2833 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2834 // CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 2835 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 2836 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2837 // CHECK2-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 2838 // CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 2839 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 2840 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2841 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2842 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 2843 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2844 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 2845 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 2846 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2847 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 2848 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 2849 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 2850 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 2851 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 2852 // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2853 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 2854 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 2855 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 2856 // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 2857 // CHECK2-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 2858 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 2859 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 2860 // CHECK2-NEXT: ret void 2861 // 2862 // 2863 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 2864 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 2865 // CHECK2-NEXT: entry: 2866 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2867 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2868 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2869 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 2870 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2871 // CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 2872 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 2873 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2874 // CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 2875 // CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 2876 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 2877 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2878 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2879 // CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1 2880 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2881 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2882 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2883 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2884 // CHECK2-NEXT: [[IT:%.*]] = alloca i8, align 1 2885 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2886 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2887 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2888 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 2889 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2890 // CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 2891 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 2892 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2893 // CHECK2-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 2894 // CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 2895 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 2896 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2897 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2898 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 2899 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2900 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 2901 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 2902 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2903 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 2904 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 2905 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 2906 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 2907 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2908 // CHECK2-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 2909 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2910 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2911 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 2912 // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2913 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 2914 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 2915 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2916 // CHECK2: omp.dispatch.cond: 2917 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2918 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 2919 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2920 // CHECK2: cond.true: 2921 // CHECK2-NEXT: br label [[COND_END:%.*]] 2922 // CHECK2: cond.false: 2923 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2924 // CHECK2-NEXT: br label [[COND_END]] 2925 // CHECK2: cond.end: 2926 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 2927 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2928 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2929 // CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 2930 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2931 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2932 // CHECK2-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 2933 // CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2934 // CHECK2: omp.dispatch.body: 2935 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2936 // CHECK2: omp.inner.for.cond: 2937 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2938 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2939 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 2940 // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2941 // CHECK2: omp.inner.for.body: 2942 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2943 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 2944 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 2945 // CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 2946 // CHECK2-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 2947 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 2948 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 2949 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 2950 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 2951 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 2952 // CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 2953 // CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 2954 // CHECK2-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 2955 // CHECK2-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 2956 // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 2957 // CHECK2-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 2958 // CHECK2-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 2959 // CHECK2-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 2960 // CHECK2-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 2961 // CHECK2-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 2962 // CHECK2-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 2963 // CHECK2-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 2964 // CHECK2-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 2965 // CHECK2-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 2966 // CHECK2-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 2967 // CHECK2-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 2968 // CHECK2-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 2969 // CHECK2-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 2970 // CHECK2-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 2971 // CHECK2-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 2972 // CHECK2-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 2973 // CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 2974 // CHECK2-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 2975 // CHECK2-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 2976 // CHECK2-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 2977 // CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 2978 // CHECK2-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 2979 // CHECK2-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 2980 // CHECK2-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 2981 // CHECK2-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 2982 // CHECK2-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 2983 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2984 // CHECK2: omp.body.continue: 2985 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2986 // CHECK2: omp.inner.for.inc: 2987 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2988 // CHECK2-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 2989 // CHECK2-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 2990 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 2991 // CHECK2: omp.inner.for.end: 2992 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2993 // CHECK2: omp.dispatch.inc: 2994 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2995 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2996 // CHECK2-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 2997 // CHECK2-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 2998 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2999 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3000 // CHECK2-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 3001 // CHECK2-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 3002 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 3003 // CHECK2: omp.dispatch.end: 3004 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 3005 // CHECK2-NEXT: ret void 3006 // 3007 // 3008 // CHECK2-LABEL: define {{[^@]+}}@_Z3bari 3009 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 3010 // CHECK2-NEXT: entry: 3011 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3012 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 3013 // CHECK2-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 3014 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3015 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 3016 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3017 // CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 3018 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 3019 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3020 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3021 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3022 // CHECK2-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 3023 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3024 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3025 // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 3026 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3027 // CHECK2-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 3028 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3029 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3030 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 3031 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3032 // CHECK2-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 3033 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 3034 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 3035 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 3036 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 3037 // CHECK2-NEXT: ret i32 [[TMP8]] 3038 // 3039 // 3040 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3041 // CHECK2-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3042 // CHECK2-NEXT: entry: 3043 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3044 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3045 // CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4 3046 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3047 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3048 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3049 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 3050 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 3051 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 3052 // CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 3053 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3054 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3055 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3056 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3057 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3058 // CHECK2-NEXT: store i32 [[ADD]], i32* [[B]], align 4 3059 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3060 // CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 3061 // CHECK2-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 3062 // CHECK2-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 3063 // CHECK2-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 3064 // CHECK2-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 3065 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 3066 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 3067 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 3068 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 3069 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 3070 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 3071 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 3072 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3073 // CHECK2: omp_if.then: 3074 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3075 // CHECK2-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 3076 // CHECK2-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 3077 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3078 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 3079 // CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 3080 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3081 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 3082 // CHECK2-NEXT: store double* [[A]], double** [[TMP13]], align 8 3083 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3084 // CHECK2-NEXT: store i64 8, i64* [[TMP14]], align 8 3085 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3086 // CHECK2-NEXT: store i8* null, i8** [[TMP15]], align 8 3087 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3088 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 3089 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 3090 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3091 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 3092 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 3093 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 3094 // CHECK2-NEXT: store i64 4, i64* [[TMP20]], align 8 3095 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3096 // CHECK2-NEXT: store i8* null, i8** [[TMP21]], align 8 3097 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3098 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 3099 // CHECK2-NEXT: store i64 2, i64* [[TMP23]], align 8 3100 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3101 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 3102 // CHECK2-NEXT: store i64 2, i64* [[TMP25]], align 8 3103 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 3104 // CHECK2-NEXT: store i64 8, i64* [[TMP26]], align 8 3105 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3106 // CHECK2-NEXT: store i8* null, i8** [[TMP27]], align 8 3107 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3108 // CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 3109 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 3110 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3111 // CHECK2-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 3112 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 3113 // CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 3114 // CHECK2-NEXT: store i64 8, i64* [[TMP32]], align 8 3115 // CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 3116 // CHECK2-NEXT: store i8* null, i8** [[TMP33]], align 8 3117 // CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3118 // CHECK2-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 3119 // CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 3120 // CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3121 // CHECK2-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 3122 // CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 3123 // CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3124 // CHECK2-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 3125 // CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 3126 // CHECK2-NEXT: store i8* null, i8** [[TMP39]], align 8 3127 // CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3128 // CHECK2-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3129 // CHECK2-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3130 // CHECK2-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3131 // CHECK2-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 3132 // CHECK2-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3133 // CHECK2: omp_offload.failed: 3134 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 3135 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 3136 // CHECK2: omp_offload.cont: 3137 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 3138 // CHECK2: omp_if.else: 3139 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 3140 // CHECK2-NEXT: br label [[OMP_IF_END]] 3141 // CHECK2: omp_if.end: 3142 // CHECK2-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] 3143 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] 3144 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 3145 // CHECK2-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 3146 // CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 3147 // CHECK2-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 3148 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] 3149 // CHECK2-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 3150 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 3151 // CHECK2-NEXT: ret i32 [[ADD4]] 3152 // 3153 // 3154 // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici 3155 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 3156 // CHECK2-NEXT: entry: 3157 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3158 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 3159 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 3160 // CHECK2-NEXT: [[AAA:%.*]] = alloca i8, align 1 3161 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3162 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3163 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3164 // CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 3165 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 3166 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 3167 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 3168 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3169 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 3170 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 3171 // CHECK2-NEXT: store i8 0, i8* [[AAA]], align 1 3172 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 3173 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3174 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 3175 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 3176 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 3177 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3178 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 3179 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3180 // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 3181 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 3182 // CHECK2-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 3183 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 3184 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3185 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 3186 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3187 // CHECK2: omp_if.then: 3188 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3189 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 3190 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 3191 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3192 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 3193 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 3194 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3195 // CHECK2-NEXT: store i8* null, i8** [[TMP11]], align 8 3196 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3197 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 3198 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 3199 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3200 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 3201 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 3202 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3203 // CHECK2-NEXT: store i8* null, i8** [[TMP16]], align 8 3204 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3205 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 3206 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 3207 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3208 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 3209 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 3210 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3211 // CHECK2-NEXT: store i8* null, i8** [[TMP21]], align 8 3212 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3213 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 3214 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 3215 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3216 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 3217 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 3218 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 3219 // CHECK2-NEXT: store i8* null, i8** [[TMP26]], align 8 3220 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3221 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3222 // CHECK2-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3223 // CHECK2-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 3224 // CHECK2-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3225 // CHECK2: omp_offload.failed: 3226 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 3227 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 3228 // CHECK2: omp_offload.cont: 3229 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 3230 // CHECK2: omp_if.else: 3231 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 3232 // CHECK2-NEXT: br label [[OMP_IF_END]] 3233 // CHECK2: omp_if.end: 3234 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 3235 // CHECK2-NEXT: ret i32 [[TMP31]] 3236 // 3237 // 3238 // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3239 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 3240 // CHECK2-NEXT: entry: 3241 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3242 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 3243 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 3244 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3245 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3246 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3247 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 3248 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 3249 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 3250 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3251 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 3252 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 3253 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 3254 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3255 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 3256 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 3257 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 3258 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3259 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 3260 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3261 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3262 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 3263 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3264 // CHECK2: omp_if.then: 3265 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3266 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 3267 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 3268 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3269 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 3270 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 3271 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3272 // CHECK2-NEXT: store i8* null, i8** [[TMP9]], align 8 3273 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3274 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 3275 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 3276 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3277 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 3278 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 3279 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3280 // CHECK2-NEXT: store i8* null, i8** [[TMP14]], align 8 3281 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3282 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 3283 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 3284 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3285 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 3286 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 3287 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3288 // CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8 3289 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3290 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3291 // CHECK2-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3292 // CHECK2-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 3293 // CHECK2-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3294 // CHECK2: omp_offload.failed: 3295 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 3296 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 3297 // CHECK2: omp_offload.cont: 3298 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 3299 // CHECK2: omp_if.else: 3300 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 3301 // CHECK2-NEXT: br label [[OMP_IF_END]] 3302 // CHECK2: omp_if.end: 3303 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 3304 // CHECK2-NEXT: ret i32 [[TMP24]] 3305 // 3306 // 3307 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 3308 // CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3309 // CHECK2-NEXT: entry: 3310 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3311 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3312 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3313 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 3314 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 3315 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3316 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3317 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3318 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3319 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 3320 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 3321 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3322 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 3323 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3324 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 3325 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 3326 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 3327 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 3328 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 3329 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 3330 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 3331 // CHECK2-NEXT: ret void 3332 // 3333 // 3334 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 3335 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 3336 // CHECK2-NEXT: entry: 3337 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3338 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3339 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3340 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3341 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3342 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 3343 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 3344 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3345 // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 3346 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3347 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3348 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3349 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3350 // CHECK2-NEXT: [[IT:%.*]] = alloca i64, align 8 3351 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3352 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3353 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3354 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3355 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3356 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 3357 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 3358 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3359 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 3360 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3361 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 3362 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 3363 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3364 // CHECK2-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 3365 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3366 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3367 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3368 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3369 // CHECK2-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 3370 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3371 // CHECK2-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 3372 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3373 // CHECK2: cond.true: 3374 // CHECK2-NEXT: br label [[COND_END:%.*]] 3375 // CHECK2: cond.false: 3376 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3377 // CHECK2-NEXT: br label [[COND_END]] 3378 // CHECK2: cond.end: 3379 // CHECK2-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3380 // CHECK2-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 3381 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3382 // CHECK2-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 3383 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3384 // CHECK2: omp.inner.for.cond: 3385 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3386 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3387 // CHECK2-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 3388 // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3389 // CHECK2: omp.inner.for.body: 3390 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3391 // CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 3392 // CHECK2-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 3393 // CHECK2-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 3394 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 3395 // CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 3396 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 3397 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3398 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8 3399 // CHECK2-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 3400 // CHECK2-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 3401 // CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 3402 // CHECK2-NEXT: store double [[INC]], double* [[A5]], align 8 3403 // CHECK2-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 3404 // CHECK2-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 3405 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 3406 // CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 3407 // CHECK2-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 3408 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3409 // CHECK2: omp.body.continue: 3410 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3411 // CHECK2: omp.inner.for.inc: 3412 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3413 // CHECK2-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 3414 // CHECK2-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 3415 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 3416 // CHECK2: omp.inner.for.end: 3417 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3418 // CHECK2: omp.loop.exit: 3419 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 3420 // CHECK2-NEXT: ret void 3421 // 3422 // 3423 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 3424 // CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3425 // CHECK2-NEXT: entry: 3426 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3427 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3428 // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 3429 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3430 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3431 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3432 // CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 3433 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3434 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3435 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 3436 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3437 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3438 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3439 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 3440 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3441 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 3442 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3443 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 3444 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 3445 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 3446 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3447 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 3448 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3449 // CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 3450 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 3451 // CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 3452 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 3453 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 3454 // CHECK2-NEXT: ret void 3455 // 3456 // 3457 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 3458 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3459 // CHECK2-NEXT: entry: 3460 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3461 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3462 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3463 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3464 // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 3465 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3466 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3467 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 3468 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3469 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3470 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3471 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3472 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 3473 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3474 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3475 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3476 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 3477 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3478 // CHECK2-NEXT: ret void 3479 // 3480 // 3481 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 3482 // CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3483 // CHECK2-NEXT: entry: 3484 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3485 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3486 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3487 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3488 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3489 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3490 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3491 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3492 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3493 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3494 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3495 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 3496 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3497 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 3498 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 3499 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 3500 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3501 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 3502 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3503 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 3504 // CHECK2-NEXT: ret void 3505 // 3506 // 3507 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 3508 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3509 // CHECK2-NEXT: entry: 3510 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3511 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3512 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3513 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3514 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3515 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3516 // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 3517 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3518 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3519 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3520 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3521 // CHECK2-NEXT: [[I:%.*]] = alloca i64, align 8 3522 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3523 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3524 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3525 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3526 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3527 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3528 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3529 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3530 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3531 // CHECK2-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 3532 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3533 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3534 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3535 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 3536 // CHECK2-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 3537 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3538 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 3539 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3540 // CHECK2: cond.true: 3541 // CHECK2-NEXT: br label [[COND_END:%.*]] 3542 // CHECK2: cond.false: 3543 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3544 // CHECK2-NEXT: br label [[COND_END]] 3545 // CHECK2: cond.end: 3546 // CHECK2-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 3547 // CHECK2-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 3548 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3549 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 3550 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3551 // CHECK2: omp.inner.for.cond: 3552 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3553 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3554 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 3555 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3556 // CHECK2: omp.inner.for.body: 3557 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3558 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 3559 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 3560 // CHECK2-NEXT: store i64 [[ADD]], i64* [[I]], align 8 3561 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 3562 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 3563 // CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 3564 // CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 3565 // CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 3566 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 3567 // CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 3568 // CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 3569 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 3570 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3571 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 3572 // CHECK2-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 3573 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3574 // CHECK2: omp.body.continue: 3575 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3576 // CHECK2: omp.inner.for.inc: 3577 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3578 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 3579 // CHECK2-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 3580 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 3581 // CHECK2: omp.inner.for.end: 3582 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3583 // CHECK2: omp.loop.exit: 3584 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 3585 // CHECK2-NEXT: ret void 3586 // 3587 // 3588 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3589 // CHECK2-SAME: () #[[ATTR6]] { 3590 // CHECK2-NEXT: entry: 3591 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 3592 // CHECK2-NEXT: ret void 3593 // 3594 // 3595 // CHECK3-LABEL: define {{[^@]+}}@_Z7get_valv 3596 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 3597 // CHECK3-NEXT: entry: 3598 // CHECK3-NEXT: ret i64 0 3599 // 3600 // 3601 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 3602 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 3603 // CHECK3-NEXT: entry: 3604 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3605 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3606 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3607 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 3608 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 3609 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 3610 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 3611 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 3612 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 3613 // CHECK3-NEXT: [[K:%.*]] = alloca i64, align 8 3614 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3615 // CHECK3-NEXT: [[LIN:%.*]] = alloca i32, align 4 3616 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3617 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 3618 // CHECK3-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 3619 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 3620 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 3621 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 3622 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 3623 // CHECK3-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 3624 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 3625 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 3626 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 3627 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 3628 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3629 // CHECK3-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 3630 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 3631 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4 3632 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4 3633 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4 3634 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 3635 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 3636 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3637 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3638 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 3639 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3640 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3641 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 3642 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 3643 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 3644 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 3645 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 3646 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 3647 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 3648 // CHECK3-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 3649 // CHECK3-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 3650 // CHECK3-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3651 // CHECK3: omp_offload.failed: 3652 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 3653 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3654 // CHECK3: omp_offload.cont: 3655 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 3656 // CHECK3-NEXT: store i64 [[CALL]], i64* [[K]], align 8 3657 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 3658 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 3659 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4 3660 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR4]] 3661 // CHECK3-NEXT: store i32 12, i32* [[LIN]], align 4 3662 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 3663 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3664 // CHECK3-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 3665 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3666 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4 3667 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4 3668 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 3669 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 3670 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4 3671 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4 3672 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3673 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 3674 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4 3675 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3676 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 3677 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4 3678 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3679 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 3680 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3681 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 3682 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4 3683 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3684 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 3685 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4 3686 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3687 // CHECK3-NEXT: store i8* null, i8** [[TMP24]], align 4 3688 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3689 // CHECK3-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 3690 // CHECK3-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4 3691 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3692 // CHECK3-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 3693 // CHECK3-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4 3694 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3695 // CHECK3-NEXT: store i8* null, i8** [[TMP29]], align 4 3696 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3697 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3698 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 3699 // CHECK3-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 3700 // CHECK3-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 3701 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 3702 // CHECK3-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4 3703 // CHECK3-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 3704 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 3705 // CHECK3-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4 3706 // CHECK3-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 3707 // CHECK3-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 3708 // CHECK3-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 3709 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 3710 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 3711 // CHECK3-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4 3712 // CHECK3-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 3713 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false) 3714 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 3715 // CHECK3-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 3716 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 3717 // CHECK3-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8* 3718 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 3719 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 3720 // CHECK3-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8* 3721 // CHECK3-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8* 3722 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false) 3723 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 3724 // CHECK3-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8* 3725 // CHECK3-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8* 3726 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false) 3727 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 3728 // CHECK3-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 3729 // CHECK3-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4 3730 // CHECK3-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) 3731 // CHECK3-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 3732 // CHECK3-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4 3733 // CHECK3-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4 3734 // CHECK3-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 3735 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 3736 // CHECK3-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2 3737 // CHECK3-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 3738 // CHECK3-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4 3739 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10 3740 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3741 // CHECK3: omp_if.then: 3742 // CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 3743 // CHECK3-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* 3744 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4 3745 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 3746 // CHECK3-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32* 3747 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4 3748 // CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 3749 // CHECK3-NEXT: store i8* null, i8** [[TMP66]], align 4 3750 // CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 3751 // CHECK3-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32* 3752 // CHECK3-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4 3753 // CHECK3-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 3754 // CHECK3-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32* 3755 // CHECK3-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4 3756 // CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 3757 // CHECK3-NEXT: store i8* null, i8** [[TMP71]], align 4 3758 // CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 3759 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 3760 // CHECK3-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3761 // CHECK3-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0 3762 // CHECK3-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 3763 // CHECK3: omp_offload.failed9: 3764 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 3765 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT10]] 3766 // CHECK3: omp_offload.cont10: 3767 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3768 // CHECK3: omp_if.else: 3769 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 3770 // CHECK3-NEXT: br label [[OMP_IF_END]] 3771 // CHECK3: omp_if.end: 3772 // CHECK3-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4 3773 // CHECK3-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4 3774 // CHECK3-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4 3775 // CHECK3-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4 3776 // CHECK3-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4 3777 // CHECK3-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3778 // CHECK3-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 3779 // CHECK3-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 3780 // CHECK3-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4 3781 // CHECK3-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20 3782 // CHECK3-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]] 3783 // CHECK3: omp_if.then13: 3784 // CHECK3-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4 3785 // CHECK3-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64 3786 // CHECK3-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]] 3787 // CHECK3-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8 3788 // CHECK3-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64 3789 // CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 3790 // CHECK3-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* 3791 // CHECK3-NEXT: store i32 [[TMP78]], i32* [[TMP88]], align 4 3792 // CHECK3-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 3793 // CHECK3-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* 3794 // CHECK3-NEXT: store i32 [[TMP78]], i32* [[TMP90]], align 4 3795 // CHECK3-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3796 // CHECK3-NEXT: store i64 4, i64* [[TMP91]], align 4 3797 // CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 3798 // CHECK3-NEXT: store i8* null, i8** [[TMP92]], align 4 3799 // CHECK3-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 3800 // CHECK3-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]** 3801 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4 3802 // CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 3803 // CHECK3-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 3804 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4 3805 // CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 3806 // CHECK3-NEXT: store i64 40, i64* [[TMP97]], align 4 3807 // CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 3808 // CHECK3-NEXT: store i8* null, i8** [[TMP98]], align 4 3809 // CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 3810 // CHECK3-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i32* 3811 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP100]], align 4 3812 // CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 3813 // CHECK3-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i32* 3814 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP102]], align 4 3815 // CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 3816 // CHECK3-NEXT: store i64 4, i64* [[TMP103]], align 4 3817 // CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 3818 // CHECK3-NEXT: store i8* null, i8** [[TMP104]], align 4 3819 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 3820 // CHECK3-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** 3821 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP106]], align 4 3822 // CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 3823 // CHECK3-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** 3824 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP108]], align 4 3825 // CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 3826 // CHECK3-NEXT: store i64 [[TMP83]], i64* [[TMP109]], align 4 3827 // CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 3828 // CHECK3-NEXT: store i8* null, i8** [[TMP110]], align 4 3829 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 3830 // CHECK3-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** 3831 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4 3832 // CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 3833 // CHECK3-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** 3834 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 4 3835 // CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3836 // CHECK3-NEXT: store i64 400, i64* [[TMP115]], align 4 3837 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 3838 // CHECK3-NEXT: store i8* null, i8** [[TMP116]], align 4 3839 // CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 3840 // CHECK3-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to i32* 3841 // CHECK3-NEXT: store i32 5, i32* [[TMP118]], align 4 3842 // CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 3843 // CHECK3-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32* 3844 // CHECK3-NEXT: store i32 5, i32* [[TMP120]], align 4 3845 // CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 3846 // CHECK3-NEXT: store i64 4, i64* [[TMP121]], align 4 3847 // CHECK3-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 3848 // CHECK3-NEXT: store i8* null, i8** [[TMP122]], align 4 3849 // CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 3850 // CHECK3-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32* 3851 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP124]], align 4 3852 // CHECK3-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 3853 // CHECK3-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* 3854 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP126]], align 4 3855 // CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 3856 // CHECK3-NEXT: store i64 4, i64* [[TMP127]], align 4 3857 // CHECK3-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 3858 // CHECK3-NEXT: store i8* null, i8** [[TMP128]], align 4 3859 // CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 3860 // CHECK3-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to double** 3861 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP130]], align 4 3862 // CHECK3-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 3863 // CHECK3-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double** 3864 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP132]], align 4 3865 // CHECK3-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 3866 // CHECK3-NEXT: store i64 [[TMP86]], i64* [[TMP133]], align 4 3867 // CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 3868 // CHECK3-NEXT: store i8* null, i8** [[TMP134]], align 4 3869 // CHECK3-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 3870 // CHECK3-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to %struct.TT** 3871 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP136]], align 4 3872 // CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 3873 // CHECK3-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT** 3874 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 4 3875 // CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 3876 // CHECK3-NEXT: store i64 12, i64* [[TMP139]], align 4 3877 // CHECK3-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 3878 // CHECK3-NEXT: store i8* null, i8** [[TMP140]], align 4 3879 // CHECK3-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 3880 // CHECK3-NEXT: [[TMP142:%.*]] = bitcast i8** [[TMP141]] to i32* 3881 // CHECK3-NEXT: store i32 [[TMP80]], i32* [[TMP142]], align 4 3882 // CHECK3-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 3883 // CHECK3-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i32* 3884 // CHECK3-NEXT: store i32 [[TMP80]], i32* [[TMP144]], align 4 3885 // CHECK3-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 3886 // CHECK3-NEXT: store i64 4, i64* [[TMP145]], align 4 3887 // CHECK3-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 3888 // CHECK3-NEXT: store i8* null, i8** [[TMP146]], align 4 3889 // CHECK3-NEXT: [[TMP147:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 3890 // CHECK3-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 3891 // CHECK3-NEXT: [[TMP149:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3892 // CHECK3-NEXT: [[TMP150:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP147]], i8** [[TMP148]], i64* [[TMP149]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3893 // CHECK3-NEXT: [[TMP151:%.*]] = icmp ne i32 [[TMP150]], 0 3894 // CHECK3-NEXT: br i1 [[TMP151]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] 3895 // CHECK3: omp_offload.failed17: 3896 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 3897 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT18]] 3898 // CHECK3: omp_offload.cont18: 3899 // CHECK3-NEXT: br label [[OMP_IF_END20:%.*]] 3900 // CHECK3: omp_if.else19: 3901 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 3902 // CHECK3-NEXT: br label [[OMP_IF_END20]] 3903 // CHECK3: omp_if.end20: 3904 // CHECK3-NEXT: [[TMP152:%.*]] = load i32, i32* [[A]], align 4 3905 // CHECK3-NEXT: [[TMP153:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 3906 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP153]]) 3907 // CHECK3-NEXT: ret i32 [[TMP152]] 3908 // 3909 // 3910 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 3911 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] { 3912 // CHECK3-NEXT: entry: 3913 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 3914 // CHECK3-NEXT: ret void 3915 // 3916 // 3917 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 3918 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 3919 // CHECK3-NEXT: entry: 3920 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3921 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3922 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3923 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3924 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3925 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3926 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3927 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3928 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 3929 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3930 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3931 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3932 // CHECK3-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 3933 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3934 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3935 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3936 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3937 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3938 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3939 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 3940 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3941 // CHECK3: cond.true: 3942 // CHECK3-NEXT: br label [[COND_END:%.*]] 3943 // CHECK3: cond.false: 3944 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3945 // CHECK3-NEXT: br label [[COND_END]] 3946 // CHECK3: cond.end: 3947 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3948 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3949 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3950 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 3951 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3952 // CHECK3: omp.inner.for.cond: 3953 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3954 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3955 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3956 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3957 // CHECK3: omp.inner.for.body: 3958 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3959 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 3960 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 3961 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3962 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 3963 // CHECK3-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 3964 // CHECK3-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 3965 // CHECK3: .cancel.exit: 3966 // CHECK3-NEXT: br label [[CANCEL_EXIT:%.*]] 3967 // CHECK3: .cancel.continue: 3968 // CHECK3-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 3969 // CHECK3-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 3970 // CHECK3-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 3971 // CHECK3: .cancel.exit2: 3972 // CHECK3-NEXT: br label [[CANCEL_EXIT]] 3973 // CHECK3: .cancel.continue3: 3974 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3975 // CHECK3: omp.body.continue: 3976 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3977 // CHECK3: omp.inner.for.inc: 3978 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3979 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 3980 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 3981 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 3982 // CHECK3: omp.inner.for.end: 3983 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3984 // CHECK3: omp.loop.exit: 3985 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 3986 // CHECK3-NEXT: br label [[CANCEL_CONT:%.*]] 3987 // CHECK3: cancel.cont: 3988 // CHECK3-NEXT: ret void 3989 // CHECK3: cancel.exit: 3990 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 3991 // CHECK3-NEXT: br label [[CANCEL_CONT]] 3992 // 3993 // 3994 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 3995 // CHECK3-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 3996 // CHECK3-NEXT: entry: 3997 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3998 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 3999 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4000 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4001 // CHECK3-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 4002 // CHECK3-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 4003 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4004 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 4005 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 4006 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) 4007 // CHECK3-NEXT: ret void 4008 // 4009 // 4010 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 4011 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 4012 // CHECK3-NEXT: entry: 4013 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4014 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4015 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4016 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 4017 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4018 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 4019 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 4020 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4021 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4022 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4023 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4024 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 4025 // CHECK3-NEXT: [[K1:%.*]] = alloca i64, align 8 4026 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4027 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4028 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4029 // CHECK3-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 4030 // CHECK3-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 4031 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 4032 // CHECK3-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 4033 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4034 // CHECK3-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 4035 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4036 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4037 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4038 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 4039 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 4040 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1) 4041 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4042 // CHECK3: omp.dispatch.cond: 4043 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 4044 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 4045 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4046 // CHECK3: omp.dispatch.body: 4047 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4048 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 4049 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4050 // CHECK3: omp.inner.for.cond: 4051 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4052 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 4053 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 4054 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4055 // CHECK3: omp.inner.for.body: 4056 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4057 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 4058 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 4059 // CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13 4060 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !13 4061 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4062 // CHECK3-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 4063 // CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 4064 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 4065 // CHECK3-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13 4066 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !13 4067 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 4068 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13 4069 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4070 // CHECK3: omp.body.continue: 4071 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4072 // CHECK3: omp.inner.for.inc: 4073 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4074 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 4075 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4076 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 4077 // CHECK3: omp.inner.for.end: 4078 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4079 // CHECK3: omp.dispatch.inc: 4080 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 4081 // CHECK3: omp.dispatch.end: 4082 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4083 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 4084 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 4085 // CHECK3: .omp.linear.pu: 4086 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[K1]], align 8 4087 // CHECK3-NEXT: store i64 [[TMP15]], i64* [[TMP0]], align 8 4088 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 4089 // CHECK3: .omp.linear.pu.done: 4090 // CHECK3-NEXT: ret void 4091 // 4092 // 4093 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 4094 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 4095 // CHECK3-NEXT: entry: 4096 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4097 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 4098 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4099 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4100 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 4101 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4102 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4103 // CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 4104 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4105 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4106 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 4107 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4108 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 4109 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4110 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 4111 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 4112 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 4113 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 4114 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 4115 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 4116 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 4117 // CHECK3-NEXT: ret void 4118 // 4119 // 4120 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 4121 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 4122 // CHECK3-NEXT: entry: 4123 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4124 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4125 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4126 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 4127 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4128 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4129 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 4130 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 4131 // CHECK3-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 4132 // CHECK3-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 4133 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4134 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4135 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4136 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4137 // CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8 4138 // CHECK3-NEXT: [[LIN2:%.*]] = alloca i32, align 4 4139 // CHECK3-NEXT: [[A3:%.*]] = alloca i32, align 4 4140 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4141 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4142 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4143 // CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 4144 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4145 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4146 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 4147 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 4148 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4149 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 4150 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 4151 // CHECK3-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 4152 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4153 // CHECK3-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 4154 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4155 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4156 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4157 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 4158 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 4159 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 4160 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4161 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 4162 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4163 // CHECK3: cond.true: 4164 // CHECK3-NEXT: br label [[COND_END:%.*]] 4165 // CHECK3: cond.false: 4166 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4167 // CHECK3-NEXT: br label [[COND_END]] 4168 // CHECK3: cond.end: 4169 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 4170 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 4171 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4172 // CHECK3-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 4173 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4174 // CHECK3: omp.inner.for.cond: 4175 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4176 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4177 // CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 4178 // CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4179 // CHECK3: omp.inner.for.body: 4180 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4181 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 4182 // CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 4183 // CHECK3-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 4184 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 4185 // CHECK3-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 4186 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4187 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 4188 // CHECK3-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 4189 // CHECK3-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 4190 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 4191 // CHECK3-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 4192 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 4193 // CHECK3-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 4194 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4195 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 4196 // CHECK3-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 4197 // CHECK3-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 4198 // CHECK3-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 4199 // CHECK3-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 4200 // CHECK3-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 4201 // CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 4202 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 4203 // CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 4204 // CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 4205 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4206 // CHECK3: omp.body.continue: 4207 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4208 // CHECK3: omp.inner.for.inc: 4209 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4210 // CHECK3-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 4211 // CHECK3-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 4212 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 4213 // CHECK3: omp.inner.for.end: 4214 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4215 // CHECK3: omp.loop.exit: 4216 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 4217 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4218 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 4219 // CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 4220 // CHECK3: .omp.linear.pu: 4221 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 4222 // CHECK3-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 4223 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 4224 // CHECK3-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 4225 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 4226 // CHECK3: .omp.linear.pu.done: 4227 // CHECK3-NEXT: ret void 4228 // 4229 // 4230 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. 4231 // CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 4232 // CHECK3-NEXT: entry: 4233 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 4234 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 4235 // CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 4236 // CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 4237 // CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 4238 // CHECK3-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 4239 // CHECK3-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 4240 // CHECK3-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 4241 // CHECK3-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 4242 // CHECK3-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 4243 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 4244 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 4245 // CHECK3-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 4246 // CHECK3-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 4247 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 4248 // CHECK3-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 4249 // CHECK3-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 4250 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 4251 // CHECK3-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 4252 // CHECK3-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 4253 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 4254 // CHECK3-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 4255 // CHECK3-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 4256 // CHECK3-NEXT: ret void 4257 // 4258 // 4259 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 4260 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 4261 // CHECK3-NEXT: entry: 4262 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 4263 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 4264 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 4265 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 4266 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 4267 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 4268 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 4269 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 4270 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 4271 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 4272 // CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 4273 // CHECK3-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4 4274 // CHECK3-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4 4275 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 4276 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 4277 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 4278 // CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 4279 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 4280 // CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 4281 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 4282 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 4283 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 4284 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 4285 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 4286 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 4287 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 4288 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 4289 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 4290 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 4291 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 4292 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 4293 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 4294 // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 4295 // CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 4296 // CHECK3-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 4297 // CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 4298 // CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 4299 // CHECK3-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 4300 // CHECK3-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 4301 // CHECK3-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 4302 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 4303 // CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 4304 // CHECK3-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 4305 // CHECK3-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 4306 // CHECK3-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 4307 // CHECK3-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 4308 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 4309 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 4310 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 4311 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 4312 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 4313 // CHECK3-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 4314 // CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 4315 // CHECK3-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 4316 // CHECK3: omp_offload.failed.i: 4317 // CHECK3-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 4318 // CHECK3-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 4319 // CHECK3-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25 4320 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 4321 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 4322 // CHECK3-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25 4323 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !25 4324 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 4325 // CHECK3-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25 4326 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !25 4327 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR4]] 4328 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 4329 // CHECK3: .omp_outlined..3.exit: 4330 // CHECK3-NEXT: ret i32 0 4331 // 4332 // 4333 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 4334 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 4335 // CHECK3-NEXT: entry: 4336 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4337 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4338 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4339 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4340 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4341 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4342 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4343 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4344 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4345 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4346 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 4347 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4348 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 4349 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4350 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 4351 // CHECK3-NEXT: ret void 4352 // 4353 // 4354 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 4355 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 4356 // CHECK3-NEXT: entry: 4357 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4358 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4359 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4360 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4361 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4362 // CHECK3-NEXT: [[TMP:%.*]] = alloca i16, align 2 4363 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4364 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4365 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4366 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4367 // CHECK3-NEXT: [[IT:%.*]] = alloca i16, align 2 4368 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4369 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4370 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4371 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4372 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4373 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4374 // CHECK3-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 4375 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4376 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4377 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4378 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4379 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4380 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4381 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 4382 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4383 // CHECK3: cond.true: 4384 // CHECK3-NEXT: br label [[COND_END:%.*]] 4385 // CHECK3: cond.false: 4386 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4387 // CHECK3-NEXT: br label [[COND_END]] 4388 // CHECK3: cond.end: 4389 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4390 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4391 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4392 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4393 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4394 // CHECK3: omp.inner.for.cond: 4395 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4396 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4397 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4398 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4399 // CHECK3: omp.inner.for.body: 4400 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4401 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 4402 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 4403 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 4404 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 4405 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 4406 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 4407 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 4408 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 4409 // CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 4410 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 4411 // CHECK3-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 4412 // CHECK3-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 4413 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4414 // CHECK3: omp.body.continue: 4415 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4416 // CHECK3: omp.inner.for.inc: 4417 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4418 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 4419 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 4420 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 4421 // CHECK3: omp.inner.for.end: 4422 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4423 // CHECK3: omp.loop.exit: 4424 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4425 // CHECK3-NEXT: ret void 4426 // 4427 // 4428 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 4429 // CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 4430 // CHECK3-NEXT: entry: 4431 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4432 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 4433 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4434 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 4435 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 4436 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4437 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 4438 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 4439 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 4440 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4441 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4442 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 4443 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4444 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 4445 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4446 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 4447 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 4448 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4449 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 4450 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 4451 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 4452 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4453 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 4454 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4455 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 4456 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 4457 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4458 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 4459 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 4460 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 4461 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 4462 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 4463 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 4464 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4465 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4466 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4467 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 4468 // CHECK3-NEXT: ret void 4469 // 4470 // 4471 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 4472 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 4473 // CHECK3-NEXT: entry: 4474 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4475 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4476 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4477 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 4478 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4479 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 4480 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 4481 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4482 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 4483 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 4484 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 4485 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4486 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4487 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 4488 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4489 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4490 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4491 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4492 // CHECK3-NEXT: [[IT:%.*]] = alloca i8, align 1 4493 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4494 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4495 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4496 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 4497 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4498 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 4499 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 4500 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4501 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 4502 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 4503 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 4504 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4505 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 4506 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4507 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 4508 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 4509 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4510 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 4511 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 4512 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 4513 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4514 // CHECK3-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 4515 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4516 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4517 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4518 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4519 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 4520 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 4521 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4522 // CHECK3: omp.dispatch.cond: 4523 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4524 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 4525 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4526 // CHECK3: cond.true: 4527 // CHECK3-NEXT: br label [[COND_END:%.*]] 4528 // CHECK3: cond.false: 4529 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4530 // CHECK3-NEXT: br label [[COND_END]] 4531 // CHECK3: cond.end: 4532 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 4533 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4534 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4535 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 4536 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4537 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4538 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 4539 // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4540 // CHECK3: omp.dispatch.body: 4541 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4542 // CHECK3: omp.inner.for.cond: 4543 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4544 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4545 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 4546 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4547 // CHECK3: omp.inner.for.body: 4548 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4549 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 4550 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 4551 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 4552 // CHECK3-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 4553 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 4554 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 4555 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4556 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 4557 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 4558 // CHECK3-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 4559 // CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 4560 // CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 4561 // CHECK3-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 4562 // CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 4563 // CHECK3-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 4564 // CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 4565 // CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 4566 // CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 4567 // CHECK3-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 4568 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 4569 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 4570 // CHECK3-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 4571 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 4572 // CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 4573 // CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 4574 // CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 4575 // CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 4576 // CHECK3-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 4577 // CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 4578 // CHECK3-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 4579 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 4580 // CHECK3-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 4581 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 4582 // CHECK3-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 4583 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 4584 // CHECK3-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 4585 // CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 4586 // CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 4587 // CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 4588 // CHECK3-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 4589 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4590 // CHECK3: omp.body.continue: 4591 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4592 // CHECK3: omp.inner.for.inc: 4593 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4594 // CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 4595 // CHECK3-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 4596 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 4597 // CHECK3: omp.inner.for.end: 4598 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4599 // CHECK3: omp.dispatch.inc: 4600 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4601 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4602 // CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 4603 // CHECK3-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 4604 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4605 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4606 // CHECK3-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 4607 // CHECK3-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 4608 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 4609 // CHECK3: omp.dispatch.end: 4610 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 4611 // CHECK3-NEXT: ret void 4612 // 4613 // 4614 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 4615 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 4616 // CHECK3-NEXT: entry: 4617 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4618 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 4619 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 4620 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4621 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 4622 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4623 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 4624 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 4625 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 4626 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 4627 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4628 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 4629 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 4630 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 4631 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 4632 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4633 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 4634 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 4635 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 4636 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 4637 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 4638 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 4639 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 4640 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 4641 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 4642 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 4643 // CHECK3-NEXT: ret i32 [[TMP8]] 4644 // 4645 // 4646 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 4647 // CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 4648 // CHECK3-NEXT: entry: 4649 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4650 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4651 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 4652 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 4653 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 4654 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4655 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 4656 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 4657 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 4658 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 4659 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4660 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4661 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4662 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4663 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4664 // CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4 4665 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 4666 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 4667 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 4668 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 4669 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 4670 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 4671 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 4672 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 4673 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 4674 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 4675 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 4676 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4677 // CHECK3: omp_if.then: 4678 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 4679 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 4680 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 4681 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 4682 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4683 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 4684 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 4685 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4686 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 4687 // CHECK3-NEXT: store double* [[A]], double** [[TMP13]], align 4 4688 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4689 // CHECK3-NEXT: store i64 8, i64* [[TMP14]], align 4 4690 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4691 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4 4692 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4693 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 4694 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 4695 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4696 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 4697 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 4698 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 4699 // CHECK3-NEXT: store i64 4, i64* [[TMP20]], align 4 4700 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4701 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 4702 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4703 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 4704 // CHECK3-NEXT: store i32 2, i32* [[TMP23]], align 4 4705 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4706 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 4707 // CHECK3-NEXT: store i32 2, i32* [[TMP25]], align 4 4708 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 4709 // CHECK3-NEXT: store i64 4, i64* [[TMP26]], align 4 4710 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4711 // CHECK3-NEXT: store i8* null, i8** [[TMP27]], align 4 4712 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4713 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 4714 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 4715 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4716 // CHECK3-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* 4717 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 4718 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 4719 // CHECK3-NEXT: store i64 4, i64* [[TMP32]], align 4 4720 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 4721 // CHECK3-NEXT: store i8* null, i8** [[TMP33]], align 4 4722 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 4723 // CHECK3-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 4724 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 4725 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 4726 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 4727 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 4728 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 4729 // CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 4730 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 4731 // CHECK3-NEXT: store i8* null, i8** [[TMP39]], align 4 4732 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4733 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4734 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4735 // CHECK3-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 4736 // CHECK3-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 4737 // CHECK3-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4738 // CHECK3: omp_offload.failed: 4739 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 4740 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 4741 // CHECK3: omp_offload.cont: 4742 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 4743 // CHECK3: omp_if.else: 4744 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 4745 // CHECK3-NEXT: br label [[OMP_IF_END]] 4746 // CHECK3: omp_if.end: 4747 // CHECK3-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] 4748 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] 4749 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 4750 // CHECK3-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 4751 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 4752 // CHECK3-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 4753 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] 4754 // CHECK3-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 4755 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 4756 // CHECK3-NEXT: ret i32 [[ADD3]] 4757 // 4758 // 4759 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 4760 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 4761 // CHECK3-NEXT: entry: 4762 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4763 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 4764 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 4765 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 4766 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4767 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4768 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4769 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 4770 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 4771 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 4772 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 4773 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4774 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 4775 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 4776 // CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1 4777 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 4778 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4779 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4780 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 4781 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4782 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 4783 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4784 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 4785 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 4786 // CHECK3-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 4787 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 4788 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 4789 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 4790 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4791 // CHECK3: omp_if.then: 4792 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4793 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 4794 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 4795 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4796 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 4797 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 4798 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4799 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4 4800 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4801 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 4802 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 4803 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4804 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 4805 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 4806 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4807 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4 4808 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4809 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 4810 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 4811 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4812 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 4813 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 4814 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4815 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 4816 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4817 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 4818 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 4819 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4820 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 4821 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 4822 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 4823 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4 4824 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4825 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4826 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 4827 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 4828 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4829 // CHECK3: omp_offload.failed: 4830 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 4831 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 4832 // CHECK3: omp_offload.cont: 4833 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 4834 // CHECK3: omp_if.else: 4835 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 4836 // CHECK3-NEXT: br label [[OMP_IF_END]] 4837 // CHECK3: omp_if.end: 4838 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 4839 // CHECK3-NEXT: ret i32 [[TMP31]] 4840 // 4841 // 4842 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 4843 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 4844 // CHECK3-NEXT: entry: 4845 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4846 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 4847 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 4848 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4849 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4850 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4851 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 4852 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 4853 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 4854 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4855 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 4856 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 4857 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 4858 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4859 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4860 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 4861 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4862 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 4863 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4864 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4865 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 4866 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4867 // CHECK3: omp_if.then: 4868 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4869 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 4870 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 4871 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4872 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 4873 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 4874 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4875 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 4876 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4877 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 4878 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 4879 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4880 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 4881 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 4882 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4883 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 4884 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4885 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 4886 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 4887 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4888 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 4889 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 4890 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4891 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 4892 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4893 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4894 // CHECK3-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 4895 // CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 4896 // CHECK3-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4897 // CHECK3: omp_offload.failed: 4898 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 4899 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 4900 // CHECK3: omp_offload.cont: 4901 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 4902 // CHECK3: omp_if.else: 4903 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 4904 // CHECK3-NEXT: br label [[OMP_IF_END]] 4905 // CHECK3: omp_if.end: 4906 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 4907 // CHECK3-NEXT: ret i32 [[TMP24]] 4908 // 4909 // 4910 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 4911 // CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 4912 // CHECK3-NEXT: entry: 4913 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4914 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4915 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4916 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4917 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 4918 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4919 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4920 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4921 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4922 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4923 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 4924 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4925 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4926 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4927 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 4928 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 4929 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 4930 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 4931 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 4932 // CHECK3-NEXT: ret void 4933 // 4934 // 4935 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 4936 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 4937 // CHECK3-NEXT: entry: 4938 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4939 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4940 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4941 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4942 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4943 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4944 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 4945 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4946 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 4947 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4948 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4949 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4950 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4951 // CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8 4952 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4953 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4954 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4955 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4956 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4957 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4958 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 4959 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4960 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4961 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4962 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 4963 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4964 // CHECK3-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 4965 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4966 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4967 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4968 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 4969 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 4970 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4971 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 4972 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4973 // CHECK3: cond.true: 4974 // CHECK3-NEXT: br label [[COND_END:%.*]] 4975 // CHECK3: cond.false: 4976 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4977 // CHECK3-NEXT: br label [[COND_END]] 4978 // CHECK3: cond.end: 4979 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 4980 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 4981 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4982 // CHECK3-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 4983 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4984 // CHECK3: omp.inner.for.cond: 4985 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4986 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4987 // CHECK3-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 4988 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4989 // CHECK3: omp.inner.for.body: 4990 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4991 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 4992 // CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 4993 // CHECK3-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 4994 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 4995 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 4996 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 4997 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4998 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4 4999 // CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 5000 // CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 5001 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 5002 // CHECK3-NEXT: store double [[INC]], double* [[A4]], align 4 5003 // CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 5004 // CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 5005 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 5006 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 5007 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 5008 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5009 // CHECK3: omp.body.continue: 5010 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5011 // CHECK3: omp.inner.for.inc: 5012 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5013 // CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 5014 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 5015 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 5016 // CHECK3: omp.inner.for.end: 5017 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5018 // CHECK3: omp.loop.exit: 5019 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 5020 // CHECK3-NEXT: ret void 5021 // 5022 // 5023 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 5024 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5025 // CHECK3-NEXT: entry: 5026 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5027 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5028 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 5029 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5030 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5031 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5032 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 5033 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5034 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5035 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 5036 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5037 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5038 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 5039 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5040 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5041 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5042 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5043 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 5044 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5045 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 5046 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5047 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 5048 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 5049 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 5050 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 5051 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 5052 // CHECK3-NEXT: ret void 5053 // 5054 // 5055 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 5056 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 5057 // CHECK3-NEXT: entry: 5058 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5059 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5060 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5061 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5062 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 5063 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5064 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5065 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 5066 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5067 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5068 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5069 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5070 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 5071 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5072 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5073 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 5074 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5075 // CHECK3-NEXT: ret void 5076 // 5077 // 5078 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 5079 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5080 // CHECK3-NEXT: entry: 5081 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5082 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5083 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5084 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5085 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5086 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5087 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5088 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5089 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5090 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5091 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5092 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5093 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5094 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 5095 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5096 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 5097 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5098 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 5099 // CHECK3-NEXT: ret void 5100 // 5101 // 5102 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 5103 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 5104 // CHECK3-NEXT: entry: 5105 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5106 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5107 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5108 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5109 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5110 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5111 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 5112 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5113 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5114 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5115 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5116 // CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 5117 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5118 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5119 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5120 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5121 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5122 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5123 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5124 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 5125 // CHECK3-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 5126 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 5127 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5128 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5129 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 5130 // CHECK3-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 5131 // CHECK3-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5132 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 5133 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5134 // CHECK3: cond.true: 5135 // CHECK3-NEXT: br label [[COND_END:%.*]] 5136 // CHECK3: cond.false: 5137 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5138 // CHECK3-NEXT: br label [[COND_END]] 5139 // CHECK3: cond.end: 5140 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 5141 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 5142 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 5143 // CHECK3-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 5144 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5145 // CHECK3: omp.inner.for.cond: 5146 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5147 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5148 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 5149 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5150 // CHECK3: omp.inner.for.body: 5151 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5152 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 5153 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 5154 // CHECK3-NEXT: store i64 [[ADD]], i64* [[I]], align 8 5155 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 5156 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 5157 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 5158 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 5159 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 5160 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 5161 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 5162 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 5163 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 5164 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5165 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 5166 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 5167 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5168 // CHECK3: omp.body.continue: 5169 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5170 // CHECK3: omp.inner.for.inc: 5171 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5172 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 5173 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 5174 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 5175 // CHECK3: omp.inner.for.end: 5176 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5177 // CHECK3: omp.loop.exit: 5178 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 5179 // CHECK3-NEXT: ret void 5180 // 5181 // 5182 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 5183 // CHECK3-SAME: () #[[ATTR6]] { 5184 // CHECK3-NEXT: entry: 5185 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 5186 // CHECK3-NEXT: ret void 5187 // 5188 // 5189 // CHECK4-LABEL: define {{[^@]+}}@_Z7get_valv 5190 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 5191 // CHECK4-NEXT: entry: 5192 // CHECK4-NEXT: ret i64 0 5193 // 5194 // 5195 // CHECK4-LABEL: define {{[^@]+}}@_Z3fooi 5196 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 5197 // CHECK4-NEXT: entry: 5198 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5199 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 5200 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 5201 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x float], align 4 5202 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 5203 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5204 // CHECK4-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 5205 // CHECK4-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 5206 // CHECK4-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 5207 // CHECK4-NEXT: [[K:%.*]] = alloca i64, align 8 5208 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5209 // CHECK4-NEXT: [[LIN:%.*]] = alloca i32, align 4 5210 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5211 // CHECK4-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 5212 // CHECK4-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 5213 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 5214 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 5215 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 5216 // CHECK4-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 5217 // CHECK4-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 5218 // CHECK4-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 5219 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 5220 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 5221 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 5222 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5223 // CHECK4-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 5224 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 5225 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4 5226 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4 5227 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4 5228 // CHECK4-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 5229 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 5230 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5231 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 5232 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 5233 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5234 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 5235 // CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 5236 // CHECK4-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 5237 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 5238 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 5239 // CHECK4-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 5240 // CHECK4-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 5241 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 5242 // CHECK4-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 5243 // CHECK4-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 5244 // CHECK4-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5245 // CHECK4: omp_offload.failed: 5246 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 5247 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 5248 // CHECK4: omp_offload.cont: 5249 // CHECK4-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 5250 // CHECK4-NEXT: store i64 [[CALL]], i64* [[K]], align 8 5251 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 5252 // CHECK4-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 5253 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4 5254 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR4]] 5255 // CHECK4-NEXT: store i32 12, i32* [[LIN]], align 4 5256 // CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 5257 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5258 // CHECK4-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 5259 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5260 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4 5261 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4 5262 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 5263 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 5264 // CHECK4-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4 5265 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4 5266 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5267 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 5268 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4 5269 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5270 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 5271 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4 5272 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5273 // CHECK4-NEXT: store i8* null, i8** [[TMP19]], align 4 5274 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5275 // CHECK4-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 5276 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4 5277 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5278 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 5279 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4 5280 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5281 // CHECK4-NEXT: store i8* null, i8** [[TMP24]], align 4 5282 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5283 // CHECK4-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 5284 // CHECK4-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4 5285 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5286 // CHECK4-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 5287 // CHECK4-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4 5288 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5289 // CHECK4-NEXT: store i8* null, i8** [[TMP29]], align 4 5290 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5291 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5292 // CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 5293 // CHECK4-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 5294 // CHECK4-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 5295 // CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 5296 // CHECK4-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4 5297 // CHECK4-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 5298 // CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 5299 // CHECK4-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4 5300 // CHECK4-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 5301 // CHECK4-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 5302 // CHECK4-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 5303 // CHECK4-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 5304 // CHECK4-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 5305 // CHECK4-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4 5306 // CHECK4-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 5307 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false) 5308 // CHECK4-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 5309 // CHECK4-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 5310 // CHECK4-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 5311 // CHECK4-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8* 5312 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 5313 // CHECK4-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 5314 // CHECK4-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8* 5315 // CHECK4-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8* 5316 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false) 5317 // CHECK4-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 5318 // CHECK4-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8* 5319 // CHECK4-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8* 5320 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false) 5321 // CHECK4-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 5322 // CHECK4-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 5323 // CHECK4-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4 5324 // CHECK4-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) 5325 // CHECK4-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 5326 // CHECK4-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4 5327 // CHECK4-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4 5328 // CHECK4-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 5329 // CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 5330 // CHECK4-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2 5331 // CHECK4-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 5332 // CHECK4-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4 5333 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10 5334 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5335 // CHECK4: omp_if.then: 5336 // CHECK4-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 5337 // CHECK4-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* 5338 // CHECK4-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4 5339 // CHECK4-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 5340 // CHECK4-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32* 5341 // CHECK4-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4 5342 // CHECK4-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 5343 // CHECK4-NEXT: store i8* null, i8** [[TMP66]], align 4 5344 // CHECK4-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 5345 // CHECK4-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32* 5346 // CHECK4-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4 5347 // CHECK4-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 5348 // CHECK4-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32* 5349 // CHECK4-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4 5350 // CHECK4-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 5351 // CHECK4-NEXT: store i8* null, i8** [[TMP71]], align 4 5352 // CHECK4-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 5353 // CHECK4-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 5354 // CHECK4-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 5355 // CHECK4-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0 5356 // CHECK4-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 5357 // CHECK4: omp_offload.failed9: 5358 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 5359 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT10]] 5360 // CHECK4: omp_offload.cont10: 5361 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 5362 // CHECK4: omp_if.else: 5363 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 5364 // CHECK4-NEXT: br label [[OMP_IF_END]] 5365 // CHECK4: omp_if.end: 5366 // CHECK4-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4 5367 // CHECK4-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4 5368 // CHECK4-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4 5369 // CHECK4-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4 5370 // CHECK4-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4 5371 // CHECK4-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5372 // CHECK4-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 5373 // CHECK4-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 5374 // CHECK4-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4 5375 // CHECK4-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20 5376 // CHECK4-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]] 5377 // CHECK4: omp_if.then13: 5378 // CHECK4-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4 5379 // CHECK4-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64 5380 // CHECK4-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]] 5381 // CHECK4-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8 5382 // CHECK4-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64 5383 // CHECK4-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 5384 // CHECK4-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* 5385 // CHECK4-NEXT: store i32 [[TMP78]], i32* [[TMP88]], align 4 5386 // CHECK4-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 5387 // CHECK4-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* 5388 // CHECK4-NEXT: store i32 [[TMP78]], i32* [[TMP90]], align 4 5389 // CHECK4-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5390 // CHECK4-NEXT: store i64 4, i64* [[TMP91]], align 4 5391 // CHECK4-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 5392 // CHECK4-NEXT: store i8* null, i8** [[TMP92]], align 4 5393 // CHECK4-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 5394 // CHECK4-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]** 5395 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4 5396 // CHECK4-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 5397 // CHECK4-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 5398 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4 5399 // CHECK4-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 5400 // CHECK4-NEXT: store i64 40, i64* [[TMP97]], align 4 5401 // CHECK4-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 5402 // CHECK4-NEXT: store i8* null, i8** [[TMP98]], align 4 5403 // CHECK4-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 5404 // CHECK4-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i32* 5405 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP100]], align 4 5406 // CHECK4-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 5407 // CHECK4-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i32* 5408 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP102]], align 4 5409 // CHECK4-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 5410 // CHECK4-NEXT: store i64 4, i64* [[TMP103]], align 4 5411 // CHECK4-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 5412 // CHECK4-NEXT: store i8* null, i8** [[TMP104]], align 4 5413 // CHECK4-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 5414 // CHECK4-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** 5415 // CHECK4-NEXT: store float* [[VLA]], float** [[TMP106]], align 4 5416 // CHECK4-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 5417 // CHECK4-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** 5418 // CHECK4-NEXT: store float* [[VLA]], float** [[TMP108]], align 4 5419 // CHECK4-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 5420 // CHECK4-NEXT: store i64 [[TMP83]], i64* [[TMP109]], align 4 5421 // CHECK4-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 5422 // CHECK4-NEXT: store i8* null, i8** [[TMP110]], align 4 5423 // CHECK4-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 5424 // CHECK4-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** 5425 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4 5426 // CHECK4-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 5427 // CHECK4-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** 5428 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 4 5429 // CHECK4-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 5430 // CHECK4-NEXT: store i64 400, i64* [[TMP115]], align 4 5431 // CHECK4-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 5432 // CHECK4-NEXT: store i8* null, i8** [[TMP116]], align 4 5433 // CHECK4-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 5434 // CHECK4-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to i32* 5435 // CHECK4-NEXT: store i32 5, i32* [[TMP118]], align 4 5436 // CHECK4-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 5437 // CHECK4-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32* 5438 // CHECK4-NEXT: store i32 5, i32* [[TMP120]], align 4 5439 // CHECK4-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 5440 // CHECK4-NEXT: store i64 4, i64* [[TMP121]], align 4 5441 // CHECK4-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 5442 // CHECK4-NEXT: store i8* null, i8** [[TMP122]], align 4 5443 // CHECK4-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 5444 // CHECK4-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32* 5445 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP124]], align 4 5446 // CHECK4-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 5447 // CHECK4-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* 5448 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP126]], align 4 5449 // CHECK4-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 5450 // CHECK4-NEXT: store i64 4, i64* [[TMP127]], align 4 5451 // CHECK4-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 5452 // CHECK4-NEXT: store i8* null, i8** [[TMP128]], align 4 5453 // CHECK4-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 5454 // CHECK4-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to double** 5455 // CHECK4-NEXT: store double* [[VLA1]], double** [[TMP130]], align 4 5456 // CHECK4-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 5457 // CHECK4-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double** 5458 // CHECK4-NEXT: store double* [[VLA1]], double** [[TMP132]], align 4 5459 // CHECK4-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 5460 // CHECK4-NEXT: store i64 [[TMP86]], i64* [[TMP133]], align 4 5461 // CHECK4-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 5462 // CHECK4-NEXT: store i8* null, i8** [[TMP134]], align 4 5463 // CHECK4-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 5464 // CHECK4-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to %struct.TT** 5465 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP136]], align 4 5466 // CHECK4-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 5467 // CHECK4-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT** 5468 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 4 5469 // CHECK4-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 5470 // CHECK4-NEXT: store i64 12, i64* [[TMP139]], align 4 5471 // CHECK4-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 5472 // CHECK4-NEXT: store i8* null, i8** [[TMP140]], align 4 5473 // CHECK4-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 5474 // CHECK4-NEXT: [[TMP142:%.*]] = bitcast i8** [[TMP141]] to i32* 5475 // CHECK4-NEXT: store i32 [[TMP80]], i32* [[TMP142]], align 4 5476 // CHECK4-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 5477 // CHECK4-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i32* 5478 // CHECK4-NEXT: store i32 [[TMP80]], i32* [[TMP144]], align 4 5479 // CHECK4-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 5480 // CHECK4-NEXT: store i64 4, i64* [[TMP145]], align 4 5481 // CHECK4-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 5482 // CHECK4-NEXT: store i8* null, i8** [[TMP146]], align 4 5483 // CHECK4-NEXT: [[TMP147:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 5484 // CHECK4-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 5485 // CHECK4-NEXT: [[TMP149:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5486 // CHECK4-NEXT: [[TMP150:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP147]], i8** [[TMP148]], i64* [[TMP149]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 5487 // CHECK4-NEXT: [[TMP151:%.*]] = icmp ne i32 [[TMP150]], 0 5488 // CHECK4-NEXT: br i1 [[TMP151]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] 5489 // CHECK4: omp_offload.failed17: 5490 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 5491 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT18]] 5492 // CHECK4: omp_offload.cont18: 5493 // CHECK4-NEXT: br label [[OMP_IF_END20:%.*]] 5494 // CHECK4: omp_if.else19: 5495 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 5496 // CHECK4-NEXT: br label [[OMP_IF_END20]] 5497 // CHECK4: omp_if.end20: 5498 // CHECK4-NEXT: [[TMP152:%.*]] = load i32, i32* [[A]], align 4 5499 // CHECK4-NEXT: [[TMP153:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 5500 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP153]]) 5501 // CHECK4-NEXT: ret i32 [[TMP152]] 5502 // 5503 // 5504 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 5505 // CHECK4-SAME: () #[[ATTR2:[0-9]+]] { 5506 // CHECK4-NEXT: entry: 5507 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 5508 // CHECK4-NEXT: ret void 5509 // 5510 // 5511 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 5512 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 5513 // CHECK4-NEXT: entry: 5514 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5515 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5516 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5517 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 5518 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5519 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5520 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5521 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5522 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 5523 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5524 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5525 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5526 // CHECK4-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 5527 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5528 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5529 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5530 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 5531 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5532 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5533 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 5534 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5535 // CHECK4: cond.true: 5536 // CHECK4-NEXT: br label [[COND_END:%.*]] 5537 // CHECK4: cond.false: 5538 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5539 // CHECK4-NEXT: br label [[COND_END]] 5540 // CHECK4: cond.end: 5541 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 5542 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5543 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5544 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 5545 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5546 // CHECK4: omp.inner.for.cond: 5547 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5548 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5549 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 5550 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5551 // CHECK4: omp.inner.for.body: 5552 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5553 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 5554 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 5555 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 5556 // CHECK4-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 5557 // CHECK4-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 5558 // CHECK4-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 5559 // CHECK4: .cancel.exit: 5560 // CHECK4-NEXT: br label [[CANCEL_EXIT:%.*]] 5561 // CHECK4: .cancel.continue: 5562 // CHECK4-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 5563 // CHECK4-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 5564 // CHECK4-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 5565 // CHECK4: .cancel.exit2: 5566 // CHECK4-NEXT: br label [[CANCEL_EXIT]] 5567 // CHECK4: .cancel.continue3: 5568 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5569 // CHECK4: omp.body.continue: 5570 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5571 // CHECK4: omp.inner.for.inc: 5572 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5573 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 5574 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 5575 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 5576 // CHECK4: omp.inner.for.end: 5577 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5578 // CHECK4: omp.loop.exit: 5579 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 5580 // CHECK4-NEXT: br label [[CANCEL_CONT:%.*]] 5581 // CHECK4: cancel.cont: 5582 // CHECK4-NEXT: ret void 5583 // CHECK4: cancel.exit: 5584 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 5585 // CHECK4-NEXT: br label [[CANCEL_CONT]] 5586 // 5587 // 5588 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 5589 // CHECK4-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 5590 // CHECK4-NEXT: entry: 5591 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5592 // CHECK4-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 5593 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5594 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5595 // CHECK4-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 5596 // CHECK4-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 5597 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5598 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5599 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5600 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) 5601 // CHECK4-NEXT: ret void 5602 // 5603 // 5604 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 5605 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 5606 // CHECK4-NEXT: entry: 5607 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5608 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5609 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5610 // CHECK4-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 5611 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5612 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 5613 // CHECK4-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 5614 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5615 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5616 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5617 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5618 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 5619 // CHECK4-NEXT: [[K1:%.*]] = alloca i64, align 8 5620 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5621 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5622 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5623 // CHECK4-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 5624 // CHECK4-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 5625 // CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 5626 // CHECK4-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 5627 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5628 // CHECK4-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 5629 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5630 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5631 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5632 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 5633 // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 5634 // CHECK4-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1) 5635 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 5636 // CHECK4: omp.dispatch.cond: 5637 // CHECK4-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 5638 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 5639 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 5640 // CHECK4: omp.dispatch.body: 5641 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5642 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 5643 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5644 // CHECK4: omp.inner.for.cond: 5645 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 5646 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 5647 // CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 5648 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5649 // CHECK4: omp.inner.for.body: 5650 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 5651 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 5652 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 5653 // CHECK4-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13 5654 // CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !13 5655 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 5656 // CHECK4-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 5657 // CHECK4-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 5658 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 5659 // CHECK4-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13 5660 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !13 5661 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 5662 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13 5663 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5664 // CHECK4: omp.body.continue: 5665 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5666 // CHECK4: omp.inner.for.inc: 5667 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 5668 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 5669 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 5670 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 5671 // CHECK4: omp.inner.for.end: 5672 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 5673 // CHECK4: omp.dispatch.inc: 5674 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 5675 // CHECK4: omp.dispatch.end: 5676 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5677 // CHECK4-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 5678 // CHECK4-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 5679 // CHECK4: .omp.linear.pu: 5680 // CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[K1]], align 8 5681 // CHECK4-NEXT: store i64 [[TMP15]], i64* [[TMP0]], align 8 5682 // CHECK4-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 5683 // CHECK4: .omp.linear.pu.done: 5684 // CHECK4-NEXT: ret void 5685 // 5686 // 5687 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 5688 // CHECK4-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 5689 // CHECK4-NEXT: entry: 5690 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5691 // CHECK4-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 5692 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5693 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5694 // CHECK4-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 5695 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5696 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5697 // CHECK4-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 5698 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5699 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5700 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 5701 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5702 // CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 5703 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5704 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 5705 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 5706 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 5707 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 5708 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 5709 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 5710 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 5711 // CHECK4-NEXT: ret void 5712 // 5713 // 5714 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 5715 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 5716 // CHECK4-NEXT: entry: 5717 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5718 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5719 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5720 // CHECK4-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 5721 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5722 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5723 // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 4 5724 // CHECK4-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 5725 // CHECK4-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 5726 // CHECK4-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 5727 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5728 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5729 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5730 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5731 // CHECK4-NEXT: [[IT:%.*]] = alloca i64, align 8 5732 // CHECK4-NEXT: [[LIN2:%.*]] = alloca i32, align 4 5733 // CHECK4-NEXT: [[A3:%.*]] = alloca i32, align 4 5734 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5735 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5736 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5737 // CHECK4-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 5738 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5739 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5740 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 5741 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 5742 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5743 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 5744 // CHECK4-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 5745 // CHECK4-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 5746 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 5747 // CHECK4-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 5748 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 5749 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5750 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5751 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 5752 // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 5753 // CHECK4-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 5754 // CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5755 // CHECK4-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 5756 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5757 // CHECK4: cond.true: 5758 // CHECK4-NEXT: br label [[COND_END:%.*]] 5759 // CHECK4: cond.false: 5760 // CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5761 // CHECK4-NEXT: br label [[COND_END]] 5762 // CHECK4: cond.end: 5763 // CHECK4-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 5764 // CHECK4-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 5765 // CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 5766 // CHECK4-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 5767 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5768 // CHECK4: omp.inner.for.cond: 5769 // CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5770 // CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5771 // CHECK4-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 5772 // CHECK4-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5773 // CHECK4: omp.inner.for.body: 5774 // CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5775 // CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 5776 // CHECK4-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 5777 // CHECK4-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 5778 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 5779 // CHECK4-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 5780 // CHECK4-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5781 // CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 5782 // CHECK4-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 5783 // CHECK4-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 5784 // CHECK4-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 5785 // CHECK4-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 5786 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 5787 // CHECK4-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 5788 // CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5789 // CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 5790 // CHECK4-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 5791 // CHECK4-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 5792 // CHECK4-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 5793 // CHECK4-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 5794 // CHECK4-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 5795 // CHECK4-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 5796 // CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 5797 // CHECK4-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 5798 // CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 5799 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5800 // CHECK4: omp.body.continue: 5801 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5802 // CHECK4: omp.inner.for.inc: 5803 // CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5804 // CHECK4-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 5805 // CHECK4-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 5806 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 5807 // CHECK4: omp.inner.for.end: 5808 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5809 // CHECK4: omp.loop.exit: 5810 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 5811 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5812 // CHECK4-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 5813 // CHECK4-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 5814 // CHECK4: .omp.linear.pu: 5815 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 5816 // CHECK4-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 5817 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 5818 // CHECK4-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 5819 // CHECK4-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 5820 // CHECK4: .omp.linear.pu.done: 5821 // CHECK4-NEXT: ret void 5822 // 5823 // 5824 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map. 5825 // CHECK4-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 5826 // CHECK4-NEXT: entry: 5827 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 5828 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 5829 // CHECK4-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 5830 // CHECK4-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 5831 // CHECK4-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 5832 // CHECK4-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 5833 // CHECK4-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 5834 // CHECK4-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 5835 // CHECK4-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 5836 // CHECK4-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 5837 // CHECK4-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 5838 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 5839 // CHECK4-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 5840 // CHECK4-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 5841 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 5842 // CHECK4-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 5843 // CHECK4-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 5844 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 5845 // CHECK4-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 5846 // CHECK4-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 5847 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 5848 // CHECK4-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 5849 // CHECK4-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 5850 // CHECK4-NEXT: ret void 5851 // 5852 // 5853 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry. 5854 // CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 5855 // CHECK4-NEXT: entry: 5856 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 5857 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 5858 // CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 5859 // CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 5860 // CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 5861 // CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 5862 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 5863 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 5864 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 5865 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 5866 // CHECK4-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 5867 // CHECK4-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4 5868 // CHECK4-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4 5869 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 5870 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 5871 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 5872 // CHECK4-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 5873 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 5874 // CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 5875 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 5876 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 5877 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 5878 // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 5879 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 5880 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 5881 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 5882 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 5883 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 5884 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 5885 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 5886 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 5887 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 5888 // CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 5889 // CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 5890 // CHECK4-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 5891 // CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 5892 // CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 5893 // CHECK4-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 5894 // CHECK4-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 5895 // CHECK4-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 5896 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 5897 // CHECK4-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 5898 // CHECK4-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 5899 // CHECK4-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 5900 // CHECK4-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 5901 // CHECK4-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 5902 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 5903 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 5904 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 5905 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 5906 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 5907 // CHECK4-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 5908 // CHECK4-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 5909 // CHECK4-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 5910 // CHECK4: omp_offload.failed.i: 5911 // CHECK4-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 5912 // CHECK4-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 5913 // CHECK4-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25 5914 // CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 5915 // CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 5916 // CHECK4-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25 5917 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !25 5918 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 5919 // CHECK4-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25 5920 // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !25 5921 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR4]] 5922 // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 5923 // CHECK4: .omp_outlined..3.exit: 5924 // CHECK4-NEXT: ret i32 0 5925 // 5926 // 5927 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 5928 // CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 5929 // CHECK4-NEXT: entry: 5930 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5931 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5932 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5933 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5934 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5935 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5936 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5937 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 5938 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 5939 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 5940 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 5941 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5942 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 5943 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5944 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 5945 // CHECK4-NEXT: ret void 5946 // 5947 // 5948 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 5949 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 5950 // CHECK4-NEXT: entry: 5951 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5952 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5953 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5954 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5955 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5956 // CHECK4-NEXT: [[TMP:%.*]] = alloca i16, align 2 5957 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5958 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5959 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5960 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5961 // CHECK4-NEXT: [[IT:%.*]] = alloca i16, align 2 5962 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5963 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5964 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5965 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5966 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5967 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5968 // CHECK4-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 5969 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5970 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5971 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5972 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 5973 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5974 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5975 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 5976 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5977 // CHECK4: cond.true: 5978 // CHECK4-NEXT: br label [[COND_END:%.*]] 5979 // CHECK4: cond.false: 5980 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5981 // CHECK4-NEXT: br label [[COND_END]] 5982 // CHECK4: cond.end: 5983 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 5984 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5985 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5986 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 5987 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5988 // CHECK4: omp.inner.for.cond: 5989 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5990 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5991 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 5992 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5993 // CHECK4: omp.inner.for.body: 5994 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5995 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 5996 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 5997 // CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 5998 // CHECK4-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 5999 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 6000 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 6001 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 6002 // CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 6003 // CHECK4-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 6004 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 6005 // CHECK4-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 6006 // CHECK4-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 6007 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6008 // CHECK4: omp.body.continue: 6009 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6010 // CHECK4: omp.inner.for.inc: 6011 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6012 // CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 6013 // CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 6014 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 6015 // CHECK4: omp.inner.for.end: 6016 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6017 // CHECK4: omp.loop.exit: 6018 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 6019 // CHECK4-NEXT: ret void 6020 // 6021 // 6022 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 6023 // CHECK4-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 6024 // CHECK4-NEXT: entry: 6025 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6026 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 6027 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6028 // CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 6029 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 6030 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6031 // CHECK4-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 6032 // CHECK4-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 6033 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 6034 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6035 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6036 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 6037 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6038 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 6039 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6040 // CHECK4-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 6041 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 6042 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6043 // CHECK4-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 6044 // CHECK4-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 6045 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 6046 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6047 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 6048 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6049 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 6050 // CHECK4-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 6051 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6052 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 6053 // CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 6054 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 6055 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 6056 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 6057 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 6058 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6059 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 6060 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 6061 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 6062 // CHECK4-NEXT: ret void 6063 // 6064 // 6065 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 6066 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 6067 // CHECK4-NEXT: entry: 6068 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6069 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6070 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6071 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 6072 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6073 // CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 6074 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 6075 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6076 // CHECK4-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 6077 // CHECK4-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 6078 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 6079 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6080 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6081 // CHECK4-NEXT: [[TMP:%.*]] = alloca i8, align 1 6082 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6083 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6084 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6085 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6086 // CHECK4-NEXT: [[IT:%.*]] = alloca i8, align 1 6087 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6088 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6089 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6090 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 6091 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6092 // CHECK4-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 6093 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 6094 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6095 // CHECK4-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 6096 // CHECK4-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 6097 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 6098 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6099 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 6100 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6101 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 6102 // CHECK4-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 6103 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6104 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 6105 // CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 6106 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 6107 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6108 // CHECK4-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 6109 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6110 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6111 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6112 // CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6113 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 6114 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 6115 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6116 // CHECK4: omp.dispatch.cond: 6117 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6118 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 6119 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6120 // CHECK4: cond.true: 6121 // CHECK4-NEXT: br label [[COND_END:%.*]] 6122 // CHECK4: cond.false: 6123 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6124 // CHECK4-NEXT: br label [[COND_END]] 6125 // CHECK4: cond.end: 6126 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 6127 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6128 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6129 // CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 6130 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6131 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6132 // CHECK4-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 6133 // CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6134 // CHECK4: omp.dispatch.body: 6135 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6136 // CHECK4: omp.inner.for.cond: 6137 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6138 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6139 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 6140 // CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6141 // CHECK4: omp.inner.for.body: 6142 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6143 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 6144 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 6145 // CHECK4-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 6146 // CHECK4-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 6147 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 6148 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 6149 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 6150 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 6151 // CHECK4-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 6152 // CHECK4-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 6153 // CHECK4-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 6154 // CHECK4-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 6155 // CHECK4-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 6156 // CHECK4-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 6157 // CHECK4-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 6158 // CHECK4-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 6159 // CHECK4-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 6160 // CHECK4-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 6161 // CHECK4-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 6162 // CHECK4-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 6163 // CHECK4-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 6164 // CHECK4-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 6165 // CHECK4-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 6166 // CHECK4-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 6167 // CHECK4-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 6168 // CHECK4-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 6169 // CHECK4-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 6170 // CHECK4-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 6171 // CHECK4-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 6172 // CHECK4-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 6173 // CHECK4-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 6174 // CHECK4-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 6175 // CHECK4-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 6176 // CHECK4-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 6177 // CHECK4-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 6178 // CHECK4-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 6179 // CHECK4-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 6180 // CHECK4-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 6181 // CHECK4-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 6182 // CHECK4-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 6183 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6184 // CHECK4: omp.body.continue: 6185 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6186 // CHECK4: omp.inner.for.inc: 6187 // CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6188 // CHECK4-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 6189 // CHECK4-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 6190 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 6191 // CHECK4: omp.inner.for.end: 6192 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6193 // CHECK4: omp.dispatch.inc: 6194 // CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6195 // CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6196 // CHECK4-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 6197 // CHECK4-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 6198 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6199 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6200 // CHECK4-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 6201 // CHECK4-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 6202 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 6203 // CHECK4: omp.dispatch.end: 6204 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 6205 // CHECK4-NEXT: ret void 6206 // 6207 // 6208 // CHECK4-LABEL: define {{[^@]+}}@_Z3bari 6209 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 6210 // CHECK4-NEXT: entry: 6211 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6212 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 6213 // CHECK4-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 6214 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6215 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 6216 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6217 // CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 6218 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6219 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6220 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6221 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6222 // CHECK4-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 6223 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6224 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6225 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6226 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6227 // CHECK4-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 6228 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6229 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6230 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6231 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6232 // CHECK4-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 6233 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 6234 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 6235 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 6236 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 6237 // CHECK4-NEXT: ret i32 [[TMP8]] 6238 // 6239 // 6240 // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6241 // CHECK4-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6242 // CHECK4-NEXT: entry: 6243 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6244 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6245 // CHECK4-NEXT: [[B:%.*]] = alloca i32, align 4 6246 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 6247 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 6248 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6249 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 6250 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 6251 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 6252 // CHECK4-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 6253 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6254 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6255 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6256 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6257 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6258 // CHECK4-NEXT: store i32 [[ADD]], i32* [[B]], align 4 6259 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6260 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 6261 // CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 6262 // CHECK4-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 6263 // CHECK4-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 6264 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 6265 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 6266 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 6267 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 6268 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6269 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 6270 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6271 // CHECK4: omp_if.then: 6272 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6273 // CHECK4-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 6274 // CHECK4-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 6275 // CHECK4-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 6276 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6277 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 6278 // CHECK4-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 6279 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6280 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 6281 // CHECK4-NEXT: store double* [[A]], double** [[TMP13]], align 4 6282 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6283 // CHECK4-NEXT: store i64 8, i64* [[TMP14]], align 4 6284 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6285 // CHECK4-NEXT: store i8* null, i8** [[TMP15]], align 4 6286 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6287 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 6288 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 6289 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6290 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 6291 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 6292 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 6293 // CHECK4-NEXT: store i64 4, i64* [[TMP20]], align 4 6294 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6295 // CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4 6296 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6297 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 6298 // CHECK4-NEXT: store i32 2, i32* [[TMP23]], align 4 6299 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6300 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 6301 // CHECK4-NEXT: store i32 2, i32* [[TMP25]], align 4 6302 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 6303 // CHECK4-NEXT: store i64 4, i64* [[TMP26]], align 4 6304 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6305 // CHECK4-NEXT: store i8* null, i8** [[TMP27]], align 4 6306 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6307 // CHECK4-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 6308 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 6309 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6310 // CHECK4-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* 6311 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 6312 // CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 6313 // CHECK4-NEXT: store i64 4, i64* [[TMP32]], align 4 6314 // CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6315 // CHECK4-NEXT: store i8* null, i8** [[TMP33]], align 4 6316 // CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 6317 // CHECK4-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 6318 // CHECK4-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 6319 // CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 6320 // CHECK4-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 6321 // CHECK4-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 6322 // CHECK4-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 6323 // CHECK4-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 6324 // CHECK4-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 6325 // CHECK4-NEXT: store i8* null, i8** [[TMP39]], align 4 6326 // CHECK4-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6327 // CHECK4-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6328 // CHECK4-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6329 // CHECK4-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6330 // CHECK4-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 6331 // CHECK4-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6332 // CHECK4: omp_offload.failed: 6333 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 6334 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 6335 // CHECK4: omp_offload.cont: 6336 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 6337 // CHECK4: omp_if.else: 6338 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 6339 // CHECK4-NEXT: br label [[OMP_IF_END]] 6340 // CHECK4: omp_if.end: 6341 // CHECK4-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] 6342 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] 6343 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 6344 // CHECK4-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 6345 // CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 6346 // CHECK4-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 6347 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] 6348 // CHECK4-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 6349 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 6350 // CHECK4-NEXT: ret i32 [[ADD3]] 6351 // 6352 // 6353 // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici 6354 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 6355 // CHECK4-NEXT: entry: 6356 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6357 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 6358 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 6359 // CHECK4-NEXT: [[AAA:%.*]] = alloca i8, align 1 6360 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6361 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6362 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6363 // CHECK4-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 6364 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 6365 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 6366 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 6367 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6368 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 6369 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 6370 // CHECK4-NEXT: store i8 0, i8* [[AAA]], align 1 6371 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6372 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 6373 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 6374 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 6375 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6376 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 6377 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6378 // CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 6379 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 6380 // CHECK4-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 6381 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 6382 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6383 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 6384 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6385 // CHECK4: omp_if.then: 6386 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6387 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 6388 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 6389 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6390 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 6391 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 6392 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6393 // CHECK4-NEXT: store i8* null, i8** [[TMP11]], align 4 6394 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6395 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 6396 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 6397 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6398 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 6399 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 6400 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6401 // CHECK4-NEXT: store i8* null, i8** [[TMP16]], align 4 6402 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6403 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 6404 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 6405 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6406 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 6407 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 6408 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6409 // CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4 6410 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6411 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 6412 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 6413 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6414 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 6415 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 6416 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6417 // CHECK4-NEXT: store i8* null, i8** [[TMP26]], align 4 6418 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6419 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6420 // CHECK4-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6421 // CHECK4-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 6422 // CHECK4-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6423 // CHECK4: omp_offload.failed: 6424 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 6425 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 6426 // CHECK4: omp_offload.cont: 6427 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 6428 // CHECK4: omp_if.else: 6429 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 6430 // CHECK4-NEXT: br label [[OMP_IF_END]] 6431 // CHECK4: omp_if.end: 6432 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 6433 // CHECK4-NEXT: ret i32 [[TMP31]] 6434 // 6435 // 6436 // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6437 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 6438 // CHECK4-NEXT: entry: 6439 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6440 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 6441 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 6442 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6443 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6444 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6445 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 6446 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 6447 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 6448 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6449 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 6450 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 6451 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6452 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 6453 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 6454 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 6455 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6456 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 6457 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6458 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6459 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 6460 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6461 // CHECK4: omp_if.then: 6462 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6463 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 6464 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 6465 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6466 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 6467 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 6468 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6469 // CHECK4-NEXT: store i8* null, i8** [[TMP9]], align 4 6470 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6471 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 6472 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 6473 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6474 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 6475 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 6476 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6477 // CHECK4-NEXT: store i8* null, i8** [[TMP14]], align 4 6478 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6479 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 6480 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 6481 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6482 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 6483 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 6484 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6485 // CHECK4-NEXT: store i8* null, i8** [[TMP19]], align 4 6486 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6487 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6488 // CHECK4-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6489 // CHECK4-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 6490 // CHECK4-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6491 // CHECK4: omp_offload.failed: 6492 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 6493 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 6494 // CHECK4: omp_offload.cont: 6495 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 6496 // CHECK4: omp_if.else: 6497 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 6498 // CHECK4-NEXT: br label [[OMP_IF_END]] 6499 // CHECK4: omp_if.end: 6500 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 6501 // CHECK4-NEXT: ret i32 [[TMP24]] 6502 // 6503 // 6504 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 6505 // CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 6506 // CHECK4-NEXT: entry: 6507 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6508 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6509 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6510 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6511 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 6512 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6513 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6514 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6515 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6516 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6517 // CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 6518 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6519 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6520 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6521 // CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 6522 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 6523 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 6524 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 6525 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 6526 // CHECK4-NEXT: ret void 6527 // 6528 // 6529 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 6530 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 6531 // CHECK4-NEXT: entry: 6532 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6533 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6534 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6535 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6536 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6537 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6538 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 6539 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6540 // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 4 6541 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6542 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6543 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6544 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6545 // CHECK4-NEXT: [[IT:%.*]] = alloca i64, align 8 6546 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6547 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6548 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6549 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6550 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6551 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6552 // CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 6553 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6554 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6555 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6556 // CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 6557 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 6558 // CHECK4-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 6559 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 6560 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6561 // CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6562 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 6563 // CHECK4-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 6564 // CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6565 // CHECK4-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 6566 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6567 // CHECK4: cond.true: 6568 // CHECK4-NEXT: br label [[COND_END:%.*]] 6569 // CHECK4: cond.false: 6570 // CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6571 // CHECK4-NEXT: br label [[COND_END]] 6572 // CHECK4: cond.end: 6573 // CHECK4-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 6574 // CHECK4-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 6575 // CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6576 // CHECK4-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 6577 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6578 // CHECK4: omp.inner.for.cond: 6579 // CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6580 // CHECK4-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6581 // CHECK4-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 6582 // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6583 // CHECK4: omp.inner.for.body: 6584 // CHECK4-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6585 // CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 6586 // CHECK4-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 6587 // CHECK4-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 6588 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 6589 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 6590 // CHECK4-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 6591 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 6592 // CHECK4-NEXT: store double [[ADD]], double* [[A]], align 4 6593 // CHECK4-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 6594 // CHECK4-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 6595 // CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 6596 // CHECK4-NEXT: store double [[INC]], double* [[A4]], align 4 6597 // CHECK4-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 6598 // CHECK4-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 6599 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 6600 // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 6601 // CHECK4-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 6602 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6603 // CHECK4: omp.body.continue: 6604 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6605 // CHECK4: omp.inner.for.inc: 6606 // CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6607 // CHECK4-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 6608 // CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 6609 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 6610 // CHECK4: omp.inner.for.end: 6611 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6612 // CHECK4: omp.loop.exit: 6613 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 6614 // CHECK4-NEXT: ret void 6615 // 6616 // 6617 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 6618 // CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6619 // CHECK4-NEXT: entry: 6620 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6621 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6622 // CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 6623 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 6624 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6625 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6626 // CHECK4-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 6627 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6628 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6629 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 6630 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 6631 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6632 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 6633 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 6634 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 6635 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 6636 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 6637 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 6638 // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6639 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 6640 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6641 // CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 6642 // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 6643 // CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 6644 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 6645 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 6646 // CHECK4-NEXT: ret void 6647 // 6648 // 6649 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 6650 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 6651 // CHECK4-NEXT: entry: 6652 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6653 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6654 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6655 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6656 // CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 6657 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 6658 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6659 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 6660 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6661 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6662 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6663 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6664 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 6665 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 6666 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6667 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 6668 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 6669 // CHECK4-NEXT: ret void 6670 // 6671 // 6672 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 6673 // CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6674 // CHECK4-NEXT: entry: 6675 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6676 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6677 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 6678 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6679 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6680 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6681 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6682 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 6683 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6684 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 6685 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 6686 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 6687 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 6688 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 6689 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6690 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 6691 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6692 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 6693 // CHECK4-NEXT: ret void 6694 // 6695 // 6696 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 6697 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 6698 // CHECK4-NEXT: entry: 6699 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6700 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6701 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6702 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6703 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 6704 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6705 // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 4 6706 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6707 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6708 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6709 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6710 // CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 6711 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6712 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6713 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6714 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6715 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 6716 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6717 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 6718 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 6719 // CHECK4-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 6720 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 6721 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6722 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6723 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 6724 // CHECK4-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 6725 // CHECK4-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6726 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 6727 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6728 // CHECK4: cond.true: 6729 // CHECK4-NEXT: br label [[COND_END:%.*]] 6730 // CHECK4: cond.false: 6731 // CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6732 // CHECK4-NEXT: br label [[COND_END]] 6733 // CHECK4: cond.end: 6734 // CHECK4-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 6735 // CHECK4-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 6736 // CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6737 // CHECK4-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 6738 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6739 // CHECK4: omp.inner.for.cond: 6740 // CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6741 // CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6742 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 6743 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6744 // CHECK4: omp.inner.for.body: 6745 // CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6746 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 6747 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 6748 // CHECK4-NEXT: store i64 [[ADD]], i64* [[I]], align 8 6749 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 6750 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 6751 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 6752 // CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 6753 // CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 6754 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 6755 // CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 6756 // CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 6757 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 6758 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 6759 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 6760 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 6761 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6762 // CHECK4: omp.body.continue: 6763 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6764 // CHECK4: omp.inner.for.inc: 6765 // CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6766 // CHECK4-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 6767 // CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 6768 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 6769 // CHECK4: omp.inner.for.end: 6770 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6771 // CHECK4: omp.loop.exit: 6772 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 6773 // CHECK4-NEXT: ret void 6774 // 6775 // 6776 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 6777 // CHECK4-SAME: () #[[ATTR6]] { 6778 // CHECK4-NEXT: entry: 6779 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 6780 // CHECK4-NEXT: ret void 6781 // 6782 // 6783 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 6784 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 6785 // CHECK9-NEXT: entry: 6786 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 6787 // CHECK9-NEXT: ret void 6788 // 6789 // 6790 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 6791 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 6792 // CHECK9-NEXT: entry: 6793 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6794 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6795 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6796 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 6797 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6798 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6799 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6800 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6801 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 6802 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6803 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6804 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6805 // CHECK9-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 6806 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6807 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6808 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6809 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 6810 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6811 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6812 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 6813 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6814 // CHECK9: cond.true: 6815 // CHECK9-NEXT: br label [[COND_END:%.*]] 6816 // CHECK9: cond.false: 6817 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6818 // CHECK9-NEXT: br label [[COND_END]] 6819 // CHECK9: cond.end: 6820 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 6821 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6822 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6823 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 6824 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6825 // CHECK9: omp.inner.for.cond: 6826 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6827 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6828 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 6829 // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6830 // CHECK9: omp.inner.for.body: 6831 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6832 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 6833 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 6834 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 6835 // CHECK9-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 6836 // CHECK9-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 6837 // CHECK9-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 6838 // CHECK9: .cancel.exit: 6839 // CHECK9-NEXT: br label [[CANCEL_EXIT:%.*]] 6840 // CHECK9: .cancel.continue: 6841 // CHECK9-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 6842 // CHECK9-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 6843 // CHECK9-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 6844 // CHECK9: .cancel.exit2: 6845 // CHECK9-NEXT: br label [[CANCEL_EXIT]] 6846 // CHECK9: .cancel.continue3: 6847 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6848 // CHECK9: omp.body.continue: 6849 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6850 // CHECK9: omp.inner.for.inc: 6851 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6852 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 6853 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 6854 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 6855 // CHECK9: omp.inner.for.end: 6856 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6857 // CHECK9: omp.loop.exit: 6858 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 6859 // CHECK9-NEXT: br label [[CANCEL_CONT:%.*]] 6860 // CHECK9: cancel.cont: 6861 // CHECK9-NEXT: ret void 6862 // CHECK9: cancel.exit: 6863 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 6864 // CHECK9-NEXT: br label [[CANCEL_CONT]] 6865 // 6866 // 6867 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 6868 // CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 6869 // CHECK9-NEXT: entry: 6870 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6871 // CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 6872 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6873 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6874 // CHECK9-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 6875 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6876 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6877 // CHECK9-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 6878 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6879 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6880 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 6881 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6882 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 6883 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6884 // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 6885 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6886 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 6887 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 6888 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 6889 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 6890 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 6891 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6892 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 6893 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 6894 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 6895 // CHECK9-NEXT: ret void 6896 // 6897 // 6898 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 6899 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 6900 // CHECK9-NEXT: entry: 6901 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6902 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6903 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6904 // CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 6905 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6906 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6907 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 6908 // CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 6909 // CHECK9-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 6910 // CHECK9-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 6911 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6912 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6913 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6914 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6915 // CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8 6916 // CHECK9-NEXT: [[LIN4:%.*]] = alloca i32, align 4 6917 // CHECK9-NEXT: [[A5:%.*]] = alloca i32, align 4 6918 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6919 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6920 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6921 // CHECK9-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 6922 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6923 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6924 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 6925 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6926 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 6927 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 6928 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 6929 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 6930 // CHECK9-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 6931 // CHECK9-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 6932 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 6933 // CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 6934 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 6935 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6936 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6937 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 6938 // CHECK9-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 6939 // CHECK9-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 6940 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6941 // CHECK9-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 6942 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6943 // CHECK9: cond.true: 6944 // CHECK9-NEXT: br label [[COND_END:%.*]] 6945 // CHECK9: cond.false: 6946 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6947 // CHECK9-NEXT: br label [[COND_END]] 6948 // CHECK9: cond.end: 6949 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 6950 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 6951 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6952 // CHECK9-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 6953 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6954 // CHECK9: omp.inner.for.cond: 6955 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6956 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6957 // CHECK9-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 6958 // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6959 // CHECK9: omp.inner.for.body: 6960 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6961 // CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 6962 // CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 6963 // CHECK9-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 6964 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 6965 // CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 6966 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6967 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 6968 // CHECK9-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 6969 // CHECK9-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 6970 // CHECK9-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 6971 // CHECK9-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 6972 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 6973 // CHECK9-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 6974 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6975 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 6976 // CHECK9-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 6977 // CHECK9-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 6978 // CHECK9-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 6979 // CHECK9-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 6980 // CHECK9-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 6981 // CHECK9-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 6982 // CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 6983 // CHECK9-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 6984 // CHECK9-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 6985 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6986 // CHECK9: omp.body.continue: 6987 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6988 // CHECK9: omp.inner.for.inc: 6989 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6990 // CHECK9-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 6991 // CHECK9-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 6992 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 6993 // CHECK9: omp.inner.for.end: 6994 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6995 // CHECK9: omp.loop.exit: 6996 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 6997 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6998 // CHECK9-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 6999 // CHECK9-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 7000 // CHECK9: .omp.linear.pu: 7001 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 7002 // CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 7003 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 7004 // CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 7005 // CHECK9-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 7006 // CHECK9: .omp.linear.pu.done: 7007 // CHECK9-NEXT: ret void 7008 // 7009 // 7010 // CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv 7011 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 7012 // CHECK9-NEXT: entry: 7013 // CHECK9-NEXT: ret i64 0 7014 // 7015 // 7016 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 7017 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 7018 // CHECK9-NEXT: entry: 7019 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7020 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7021 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7022 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7023 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7024 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7025 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7026 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7027 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 7028 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7029 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 7030 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 7031 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 7032 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7033 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 7034 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7035 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 7036 // CHECK9-NEXT: ret void 7037 // 7038 // 7039 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 7040 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 7041 // CHECK9-NEXT: entry: 7042 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7043 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7044 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7045 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7046 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7047 // CHECK9-NEXT: [[TMP:%.*]] = alloca i16, align 2 7048 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7049 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7050 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7051 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7052 // CHECK9-NEXT: [[IT:%.*]] = alloca i16, align 2 7053 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7054 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7055 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7056 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7057 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7058 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7059 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7060 // CHECK9-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 7061 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7062 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7063 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7064 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 7065 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 7066 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7067 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 7068 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7069 // CHECK9: cond.true: 7070 // CHECK9-NEXT: br label [[COND_END:%.*]] 7071 // CHECK9: cond.false: 7072 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7073 // CHECK9-NEXT: br label [[COND_END]] 7074 // CHECK9: cond.end: 7075 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 7076 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7077 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7078 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 7079 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7080 // CHECK9: omp.inner.for.cond: 7081 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7082 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7083 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 7084 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7085 // CHECK9: omp.inner.for.body: 7086 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7087 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 7088 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 7089 // CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 7090 // CHECK9-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 7091 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 7092 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 7093 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 7094 // CHECK9-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 7095 // CHECK9-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 7096 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 7097 // CHECK9-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 7098 // CHECK9-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 7099 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7100 // CHECK9: omp.body.continue: 7101 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7102 // CHECK9: omp.inner.for.inc: 7103 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7104 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 7105 // CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 7106 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 7107 // CHECK9: omp.inner.for.end: 7108 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7109 // CHECK9: omp.loop.exit: 7110 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 7111 // CHECK9-NEXT: ret void 7112 // 7113 // 7114 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 7115 // CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 7116 // CHECK9-NEXT: entry: 7117 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7118 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 7119 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7120 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 7121 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 7122 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7123 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 7124 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 7125 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 7126 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 7127 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7128 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 7129 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7130 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 7131 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7132 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 7133 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 7134 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7135 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 7136 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 7137 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 7138 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 7139 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7140 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 7141 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7142 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 7143 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 7144 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7145 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 7146 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 7147 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 7148 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 7149 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 7150 // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7151 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 7152 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 7153 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 7154 // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 7155 // CHECK9-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 7156 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 7157 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 7158 // CHECK9-NEXT: ret void 7159 // 7160 // 7161 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 7162 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 7163 // CHECK9-NEXT: entry: 7164 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7165 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7166 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7167 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 7168 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7169 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 7170 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 7171 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7172 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 7173 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 7174 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 7175 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 7176 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7177 // CHECK9-NEXT: [[TMP:%.*]] = alloca i8, align 1 7178 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7179 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7180 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7181 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7182 // CHECK9-NEXT: [[IT:%.*]] = alloca i8, align 1 7183 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7184 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7185 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7186 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 7187 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7188 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 7189 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 7190 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7191 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 7192 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 7193 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 7194 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 7195 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7196 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 7197 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7198 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 7199 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 7200 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7201 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 7202 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 7203 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 7204 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 7205 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7206 // CHECK9-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 7207 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7208 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7209 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 7210 // CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7211 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 7212 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 7213 // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 7214 // CHECK9: omp.dispatch.cond: 7215 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7216 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 7217 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7218 // CHECK9: cond.true: 7219 // CHECK9-NEXT: br label [[COND_END:%.*]] 7220 // CHECK9: cond.false: 7221 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7222 // CHECK9-NEXT: br label [[COND_END]] 7223 // CHECK9: cond.end: 7224 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 7225 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7226 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7227 // CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 7228 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7229 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7230 // CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 7231 // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 7232 // CHECK9: omp.dispatch.body: 7233 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7234 // CHECK9: omp.inner.for.cond: 7235 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7236 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7237 // CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 7238 // CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7239 // CHECK9: omp.inner.for.body: 7240 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7241 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 7242 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 7243 // CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 7244 // CHECK9-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 7245 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 7246 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 7247 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 7248 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 7249 // CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 7250 // CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 7251 // CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 7252 // CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 7253 // CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 7254 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 7255 // CHECK9-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 7256 // CHECK9-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 7257 // CHECK9-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 7258 // CHECK9-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 7259 // CHECK9-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 7260 // CHECK9-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 7261 // CHECK9-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 7262 // CHECK9-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 7263 // CHECK9-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 7264 // CHECK9-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 7265 // CHECK9-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 7266 // CHECK9-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 7267 // CHECK9-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 7268 // CHECK9-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 7269 // CHECK9-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 7270 // CHECK9-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 7271 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 7272 // CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 7273 // CHECK9-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 7274 // CHECK9-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 7275 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 7276 // CHECK9-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 7277 // CHECK9-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 7278 // CHECK9-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 7279 // CHECK9-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 7280 // CHECK9-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 7281 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7282 // CHECK9: omp.body.continue: 7283 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7284 // CHECK9: omp.inner.for.inc: 7285 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7286 // CHECK9-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 7287 // CHECK9-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 7288 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 7289 // CHECK9: omp.inner.for.end: 7290 // CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 7291 // CHECK9: omp.dispatch.inc: 7292 // CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7293 // CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 7294 // CHECK9-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 7295 // CHECK9-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 7296 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7297 // CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 7298 // CHECK9-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 7299 // CHECK9-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 7300 // CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] 7301 // CHECK9: omp.dispatch.end: 7302 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 7303 // CHECK9-NEXT: ret void 7304 // 7305 // 7306 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 7307 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7308 // CHECK9-NEXT: entry: 7309 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7310 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7311 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 7312 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7313 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7314 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7315 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 7316 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7317 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7318 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 7319 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7320 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7321 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7322 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 7323 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7324 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 7325 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7326 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 7327 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 7328 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 7329 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7330 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 7331 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7332 // CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 7333 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 7334 // CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 7335 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 7336 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 7337 // CHECK9-NEXT: ret void 7338 // 7339 // 7340 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 7341 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 7342 // CHECK9-NEXT: entry: 7343 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7344 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7345 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7346 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7347 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 7348 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7349 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7350 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 7351 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7352 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7353 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7354 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7355 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 7356 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7357 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7358 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7359 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 7360 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7361 // CHECK9-NEXT: ret void 7362 // 7363 // 7364 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 7365 // CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 7366 // CHECK9-NEXT: entry: 7367 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 7368 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 7369 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7370 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7371 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 7372 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 7373 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 7374 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 7375 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7376 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7377 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 7378 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 7379 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 7380 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7381 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7382 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 7383 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 7384 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 7385 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 7386 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 7387 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 7388 // CHECK9-NEXT: ret void 7389 // 7390 // 7391 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 7392 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 7393 // CHECK9-NEXT: entry: 7394 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7395 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7396 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 7397 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 7398 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7399 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7400 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 7401 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7402 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 7403 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7404 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7405 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 7406 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7407 // CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8 7408 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7409 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7410 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 7411 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 7412 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7413 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7414 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 7415 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 7416 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 7417 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7418 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7419 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 7420 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 7421 // CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 7422 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 7423 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7424 // CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7425 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 7426 // CHECK9-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 7427 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7428 // CHECK9-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 7429 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7430 // CHECK9: cond.true: 7431 // CHECK9-NEXT: br label [[COND_END:%.*]] 7432 // CHECK9: cond.false: 7433 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7434 // CHECK9-NEXT: br label [[COND_END]] 7435 // CHECK9: cond.end: 7436 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 7437 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 7438 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 7439 // CHECK9-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 7440 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7441 // CHECK9: omp.inner.for.cond: 7442 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7443 // CHECK9-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7444 // CHECK9-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 7445 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7446 // CHECK9: omp.inner.for.body: 7447 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7448 // CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 7449 // CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 7450 // CHECK9-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 7451 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 7452 // CHECK9-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 7453 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 7454 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 7455 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 7456 // CHECK9-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 7457 // CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 7458 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 7459 // CHECK9-NEXT: store double [[INC]], double* [[A5]], align 8 7460 // CHECK9-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 7461 // CHECK9-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 7462 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 7463 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 7464 // CHECK9-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 7465 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7466 // CHECK9: omp.body.continue: 7467 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7468 // CHECK9: omp.inner.for.inc: 7469 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7470 // CHECK9-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 7471 // CHECK9-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 7472 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 7473 // CHECK9: omp.inner.for.end: 7474 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7475 // CHECK9: omp.loop.exit: 7476 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 7477 // CHECK9-NEXT: ret void 7478 // 7479 // 7480 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 7481 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7482 // CHECK9-NEXT: entry: 7483 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7484 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7485 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7486 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7487 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7488 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7489 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7490 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7491 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7492 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7493 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7494 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 7495 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7496 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 7497 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 7498 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 7499 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7500 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 7501 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7502 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 7503 // CHECK9-NEXT: ret void 7504 // 7505 // 7506 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 7507 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 7508 // CHECK9-NEXT: entry: 7509 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7510 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7511 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7512 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7513 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7514 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7515 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 7516 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7517 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7518 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 7519 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7520 // CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8 7521 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7522 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7523 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7524 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7525 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7526 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7527 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7528 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7529 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 7530 // CHECK9-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 7531 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 7532 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7533 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7534 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 7535 // CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 7536 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7537 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 7538 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7539 // CHECK9: cond.true: 7540 // CHECK9-NEXT: br label [[COND_END:%.*]] 7541 // CHECK9: cond.false: 7542 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7543 // CHECK9-NEXT: br label [[COND_END]] 7544 // CHECK9: cond.end: 7545 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 7546 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 7547 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 7548 // CHECK9-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 7549 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7550 // CHECK9: omp.inner.for.cond: 7551 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7552 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7553 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 7554 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7555 // CHECK9: omp.inner.for.body: 7556 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7557 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 7558 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 7559 // CHECK9-NEXT: store i64 [[ADD]], i64* [[I]], align 8 7560 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 7561 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 7562 // CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 7563 // CHECK9-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 7564 // CHECK9-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 7565 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 7566 // CHECK9-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 7567 // CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 7568 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 7569 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 7570 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 7571 // CHECK9-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 7572 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7573 // CHECK9: omp.body.continue: 7574 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7575 // CHECK9: omp.inner.for.inc: 7576 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7577 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 7578 // CHECK9-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 7579 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 7580 // CHECK9: omp.inner.for.end: 7581 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7582 // CHECK9: omp.loop.exit: 7583 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 7584 // CHECK9-NEXT: ret void 7585 // 7586 // 7587 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 7588 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 7589 // CHECK10-NEXT: entry: 7590 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 7591 // CHECK10-NEXT: ret void 7592 // 7593 // 7594 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 7595 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 7596 // CHECK10-NEXT: entry: 7597 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7598 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7599 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7600 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 7601 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7602 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7603 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7604 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7605 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 7606 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7607 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7608 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7609 // CHECK10-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 7610 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7611 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7612 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7613 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 7614 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 7615 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7616 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 7617 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7618 // CHECK10: cond.true: 7619 // CHECK10-NEXT: br label [[COND_END:%.*]] 7620 // CHECK10: cond.false: 7621 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7622 // CHECK10-NEXT: br label [[COND_END]] 7623 // CHECK10: cond.end: 7624 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 7625 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7626 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7627 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 7628 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7629 // CHECK10: omp.inner.for.cond: 7630 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7631 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7632 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 7633 // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7634 // CHECK10: omp.inner.for.body: 7635 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7636 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 7637 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 7638 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7639 // CHECK10-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 7640 // CHECK10-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 7641 // CHECK10-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 7642 // CHECK10: .cancel.exit: 7643 // CHECK10-NEXT: br label [[CANCEL_EXIT:%.*]] 7644 // CHECK10: .cancel.continue: 7645 // CHECK10-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 7646 // CHECK10-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 7647 // CHECK10-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 7648 // CHECK10: .cancel.exit2: 7649 // CHECK10-NEXT: br label [[CANCEL_EXIT]] 7650 // CHECK10: .cancel.continue3: 7651 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7652 // CHECK10: omp.body.continue: 7653 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7654 // CHECK10: omp.inner.for.inc: 7655 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7656 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 7657 // CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 7658 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 7659 // CHECK10: omp.inner.for.end: 7660 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7661 // CHECK10: omp.loop.exit: 7662 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 7663 // CHECK10-NEXT: br label [[CANCEL_CONT:%.*]] 7664 // CHECK10: cancel.cont: 7665 // CHECK10-NEXT: ret void 7666 // CHECK10: cancel.exit: 7667 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 7668 // CHECK10-NEXT: br label [[CANCEL_CONT]] 7669 // 7670 // 7671 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 7672 // CHECK10-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 7673 // CHECK10-NEXT: entry: 7674 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7675 // CHECK10-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 7676 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7677 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7678 // CHECK10-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 7679 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7680 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7681 // CHECK10-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 7682 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7683 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7684 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 7685 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7686 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 7687 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7688 // CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 7689 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7690 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 7691 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 7692 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 7693 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 7694 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 7695 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7696 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 7697 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 7698 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 7699 // CHECK10-NEXT: ret void 7700 // 7701 // 7702 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 7703 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 7704 // CHECK10-NEXT: entry: 7705 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7706 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7707 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7708 // CHECK10-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 7709 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7710 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7711 // CHECK10-NEXT: [[TMP:%.*]] = alloca i64, align 8 7712 // CHECK10-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 7713 // CHECK10-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 7714 // CHECK10-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 7715 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7716 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7717 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 7718 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7719 // CHECK10-NEXT: [[IT:%.*]] = alloca i64, align 8 7720 // CHECK10-NEXT: [[LIN4:%.*]] = alloca i32, align 4 7721 // CHECK10-NEXT: [[A5:%.*]] = alloca i32, align 4 7722 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7723 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7724 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7725 // CHECK10-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 7726 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7727 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7728 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 7729 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7730 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 7731 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 7732 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 7733 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 7734 // CHECK10-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 7735 // CHECK10-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 7736 // CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 7737 // CHECK10-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 7738 // CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 7739 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7740 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7741 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 7742 // CHECK10-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 7743 // CHECK10-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 7744 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7745 // CHECK10-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 7746 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7747 // CHECK10: cond.true: 7748 // CHECK10-NEXT: br label [[COND_END:%.*]] 7749 // CHECK10: cond.false: 7750 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7751 // CHECK10-NEXT: br label [[COND_END]] 7752 // CHECK10: cond.end: 7753 // CHECK10-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 7754 // CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 7755 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 7756 // CHECK10-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 7757 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7758 // CHECK10: omp.inner.for.cond: 7759 // CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7760 // CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7761 // CHECK10-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 7762 // CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7763 // CHECK10: omp.inner.for.body: 7764 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7765 // CHECK10-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 7766 // CHECK10-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 7767 // CHECK10-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 7768 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 7769 // CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 7770 // CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7771 // CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 7772 // CHECK10-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 7773 // CHECK10-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 7774 // CHECK10-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 7775 // CHECK10-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 7776 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 7777 // CHECK10-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 7778 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7779 // CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 7780 // CHECK10-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 7781 // CHECK10-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 7782 // CHECK10-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 7783 // CHECK10-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 7784 // CHECK10-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 7785 // CHECK10-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 7786 // CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 7787 // CHECK10-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 7788 // CHECK10-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 7789 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7790 // CHECK10: omp.body.continue: 7791 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7792 // CHECK10: omp.inner.for.inc: 7793 // CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7794 // CHECK10-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 7795 // CHECK10-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 7796 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 7797 // CHECK10: omp.inner.for.end: 7798 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7799 // CHECK10: omp.loop.exit: 7800 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 7801 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 7802 // CHECK10-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 7803 // CHECK10-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 7804 // CHECK10: .omp.linear.pu: 7805 // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 7806 // CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 7807 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 7808 // CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 7809 // CHECK10-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 7810 // CHECK10: .omp.linear.pu.done: 7811 // CHECK10-NEXT: ret void 7812 // 7813 // 7814 // CHECK10-LABEL: define {{[^@]+}}@_Z7get_valv 7815 // CHECK10-SAME: () #[[ATTR3:[0-9]+]] { 7816 // CHECK10-NEXT: entry: 7817 // CHECK10-NEXT: ret i64 0 7818 // 7819 // 7820 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 7821 // CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 7822 // CHECK10-NEXT: entry: 7823 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7824 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7825 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7826 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7827 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7828 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7829 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7830 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7831 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 7832 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7833 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 7834 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 7835 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 7836 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7837 // CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 7838 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7839 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 7840 // CHECK10-NEXT: ret void 7841 // 7842 // 7843 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 7844 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 7845 // CHECK10-NEXT: entry: 7846 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7847 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7848 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7849 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7850 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7851 // CHECK10-NEXT: [[TMP:%.*]] = alloca i16, align 2 7852 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7853 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7854 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7855 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7856 // CHECK10-NEXT: [[IT:%.*]] = alloca i16, align 2 7857 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7858 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7859 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7860 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7861 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7862 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7863 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7864 // CHECK10-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 7865 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7866 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7867 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7868 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 7869 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 7870 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7871 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 7872 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7873 // CHECK10: cond.true: 7874 // CHECK10-NEXT: br label [[COND_END:%.*]] 7875 // CHECK10: cond.false: 7876 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7877 // CHECK10-NEXT: br label [[COND_END]] 7878 // CHECK10: cond.end: 7879 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 7880 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7881 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7882 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 7883 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7884 // CHECK10: omp.inner.for.cond: 7885 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7886 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7887 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 7888 // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7889 // CHECK10: omp.inner.for.body: 7890 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7891 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 7892 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 7893 // CHECK10-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 7894 // CHECK10-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 7895 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 7896 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 7897 // CHECK10-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 7898 // CHECK10-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 7899 // CHECK10-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 7900 // CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 7901 // CHECK10-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 7902 // CHECK10-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 7903 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7904 // CHECK10: omp.body.continue: 7905 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7906 // CHECK10: omp.inner.for.inc: 7907 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7908 // CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 7909 // CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 7910 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 7911 // CHECK10: omp.inner.for.end: 7912 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7913 // CHECK10: omp.loop.exit: 7914 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 7915 // CHECK10-NEXT: ret void 7916 // 7917 // 7918 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 7919 // CHECK10-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 7920 // CHECK10-NEXT: entry: 7921 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7922 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 7923 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7924 // CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 7925 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 7926 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7927 // CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 7928 // CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 7929 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 7930 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 7931 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7932 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 7933 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7934 // CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 7935 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7936 // CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 7937 // CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 7938 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7939 // CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 7940 // CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 7941 // CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 7942 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 7943 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7944 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 7945 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7946 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 7947 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 7948 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7949 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 7950 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 7951 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 7952 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 7953 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 7954 // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7955 // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 7956 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 7957 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 7958 // CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 7959 // CHECK10-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 7960 // CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 7961 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 7962 // CHECK10-NEXT: ret void 7963 // 7964 // 7965 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 7966 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 7967 // CHECK10-NEXT: entry: 7968 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7969 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7970 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7971 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 7972 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7973 // CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 7974 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 7975 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7976 // CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 7977 // CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 7978 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 7979 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 7980 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7981 // CHECK10-NEXT: [[TMP:%.*]] = alloca i8, align 1 7982 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7983 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7984 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7985 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7986 // CHECK10-NEXT: [[IT:%.*]] = alloca i8, align 1 7987 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7988 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7989 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7990 // CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 7991 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7992 // CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 7993 // CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 7994 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7995 // CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 7996 // CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 7997 // CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 7998 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 7999 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8000 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 8001 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 8002 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 8003 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 8004 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 8005 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 8006 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 8007 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 8008 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 8009 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8010 // CHECK10-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 8011 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8012 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8013 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 8014 // CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8015 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 8016 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 8017 // CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 8018 // CHECK10: omp.dispatch.cond: 8019 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8020 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 8021 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8022 // CHECK10: cond.true: 8023 // CHECK10-NEXT: br label [[COND_END:%.*]] 8024 // CHECK10: cond.false: 8025 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8026 // CHECK10-NEXT: br label [[COND_END]] 8027 // CHECK10: cond.end: 8028 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 8029 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8030 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8031 // CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 8032 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8033 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8034 // CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 8035 // CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 8036 // CHECK10: omp.dispatch.body: 8037 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8038 // CHECK10: omp.inner.for.cond: 8039 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8040 // CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8041 // CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 8042 // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8043 // CHECK10: omp.inner.for.body: 8044 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8045 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 8046 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 8047 // CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 8048 // CHECK10-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 8049 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 8050 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 8051 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 8052 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 8053 // CHECK10-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 8054 // CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 8055 // CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 8056 // CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 8057 // CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 8058 // CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 8059 // CHECK10-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 8060 // CHECK10-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 8061 // CHECK10-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 8062 // CHECK10-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 8063 // CHECK10-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 8064 // CHECK10-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 8065 // CHECK10-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 8066 // CHECK10-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 8067 // CHECK10-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 8068 // CHECK10-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 8069 // CHECK10-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 8070 // CHECK10-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 8071 // CHECK10-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 8072 // CHECK10-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 8073 // CHECK10-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 8074 // CHECK10-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 8075 // CHECK10-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 8076 // CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 8077 // CHECK10-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 8078 // CHECK10-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 8079 // CHECK10-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 8080 // CHECK10-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 8081 // CHECK10-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 8082 // CHECK10-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 8083 // CHECK10-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 8084 // CHECK10-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 8085 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8086 // CHECK10: omp.body.continue: 8087 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8088 // CHECK10: omp.inner.for.inc: 8089 // CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8090 // CHECK10-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 8091 // CHECK10-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 8092 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 8093 // CHECK10: omp.inner.for.end: 8094 // CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 8095 // CHECK10: omp.dispatch.inc: 8096 // CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8097 // CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 8098 // CHECK10-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 8099 // CHECK10-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 8100 // CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8101 // CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 8102 // CHECK10-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 8103 // CHECK10-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 8104 // CHECK10-NEXT: br label [[OMP_DISPATCH_COND]] 8105 // CHECK10: omp.dispatch.end: 8106 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 8107 // CHECK10-NEXT: ret void 8108 // 8109 // 8110 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 8111 // CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 8112 // CHECK10-NEXT: entry: 8113 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8114 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8115 // CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 8116 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 8117 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 8118 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 8119 // CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 8120 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8121 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8122 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 8123 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 8124 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8125 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8126 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 8127 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 8128 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 8129 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 8130 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 8131 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 8132 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 8133 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 8134 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 8135 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 8136 // CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 8137 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 8138 // CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 8139 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 8140 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 8141 // CHECK10-NEXT: ret void 8142 // 8143 // 8144 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 8145 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 8146 // CHECK10-NEXT: entry: 8147 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8148 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8149 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8150 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8151 // CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 8152 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 8153 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8154 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 8155 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8156 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8157 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8158 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8159 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 8160 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 8161 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8162 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8163 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 8164 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 8165 // CHECK10-NEXT: ret void 8166 // 8167 // 8168 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 8169 // CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 8170 // CHECK10-NEXT: entry: 8171 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 8172 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 8173 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 8174 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 8175 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 8176 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 8177 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 8178 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 8179 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 8180 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 8181 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 8182 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 8183 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 8184 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 8185 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 8186 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 8187 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 8188 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 8189 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 8190 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 8191 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 8192 // CHECK10-NEXT: ret void 8193 // 8194 // 8195 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 8196 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 8197 // CHECK10-NEXT: entry: 8198 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8199 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8200 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 8201 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 8202 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 8203 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 8204 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 8205 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8206 // CHECK10-NEXT: [[TMP:%.*]] = alloca i64, align 8 8207 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8208 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8209 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 8210 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8211 // CHECK10-NEXT: [[IT:%.*]] = alloca i64, align 8 8212 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8213 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8214 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 8215 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 8216 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 8217 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 8218 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 8219 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 8220 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 8221 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 8222 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 8223 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 8224 // CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8225 // CHECK10-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 8226 // CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 8227 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8228 // CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8229 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 8230 // CHECK10-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 8231 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8232 // CHECK10-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 8233 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8234 // CHECK10: cond.true: 8235 // CHECK10-NEXT: br label [[COND_END:%.*]] 8236 // CHECK10: cond.false: 8237 // CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8238 // CHECK10-NEXT: br label [[COND_END]] 8239 // CHECK10: cond.end: 8240 // CHECK10-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 8241 // CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 8242 // CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8243 // CHECK10-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 8244 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8245 // CHECK10: omp.inner.for.cond: 8246 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8247 // CHECK10-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8248 // CHECK10-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 8249 // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8250 // CHECK10: omp.inner.for.body: 8251 // CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8252 // CHECK10-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 8253 // CHECK10-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 8254 // CHECK10-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 8255 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 8256 // CHECK10-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 8257 // CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 8258 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 8259 // CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 8260 // CHECK10-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 8261 // CHECK10-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 8262 // CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 8263 // CHECK10-NEXT: store double [[INC]], double* [[A5]], align 8 8264 // CHECK10-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 8265 // CHECK10-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 8266 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 8267 // CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 8268 // CHECK10-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 8269 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8270 // CHECK10: omp.body.continue: 8271 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8272 // CHECK10: omp.inner.for.inc: 8273 // CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8274 // CHECK10-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 8275 // CHECK10-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 8276 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 8277 // CHECK10: omp.inner.for.end: 8278 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8279 // CHECK10: omp.loop.exit: 8280 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 8281 // CHECK10-NEXT: ret void 8282 // 8283 // 8284 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 8285 // CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 8286 // CHECK10-NEXT: entry: 8287 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8288 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8289 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 8290 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 8291 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 8292 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8293 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8294 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 8295 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8296 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8297 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 8298 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 8299 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 8300 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 8301 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 8302 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 8303 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 8304 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 8305 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 8306 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 8307 // CHECK10-NEXT: ret void 8308 // 8309 // 8310 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 8311 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 8312 // CHECK10-NEXT: entry: 8313 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8314 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8315 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8316 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8317 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 8318 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8319 // CHECK10-NEXT: [[TMP:%.*]] = alloca i64, align 8 8320 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8321 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8322 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 8323 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8324 // CHECK10-NEXT: [[I:%.*]] = alloca i64, align 8 8325 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8326 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8327 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8328 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8329 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 8330 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8331 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8332 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 8333 // CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8334 // CHECK10-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 8335 // CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 8336 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8337 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8338 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 8339 // CHECK10-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 8340 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8341 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 8342 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8343 // CHECK10: cond.true: 8344 // CHECK10-NEXT: br label [[COND_END:%.*]] 8345 // CHECK10: cond.false: 8346 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8347 // CHECK10-NEXT: br label [[COND_END]] 8348 // CHECK10: cond.end: 8349 // CHECK10-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 8350 // CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 8351 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8352 // CHECK10-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 8353 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8354 // CHECK10: omp.inner.for.cond: 8355 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8356 // CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8357 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 8358 // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8359 // CHECK10: omp.inner.for.body: 8360 // CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8361 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 8362 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 8363 // CHECK10-NEXT: store i64 [[ADD]], i64* [[I]], align 8 8364 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 8365 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 8366 // CHECK10-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 8367 // CHECK10-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 8368 // CHECK10-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 8369 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 8370 // CHECK10-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 8371 // CHECK10-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 8372 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 8373 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 8374 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 8375 // CHECK10-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 8376 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8377 // CHECK10: omp.body.continue: 8378 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8379 // CHECK10: omp.inner.for.inc: 8380 // CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8381 // CHECK10-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 8382 // CHECK10-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 8383 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 8384 // CHECK10: omp.inner.for.end: 8385 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8386 // CHECK10: omp.loop.exit: 8387 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 8388 // CHECK10-NEXT: ret void 8389 // 8390 // 8391 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 8392 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 8393 // CHECK11-NEXT: entry: 8394 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 8395 // CHECK11-NEXT: ret void 8396 // 8397 // 8398 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 8399 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 8400 // CHECK11-NEXT: entry: 8401 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8402 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8403 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8404 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 8405 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8406 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8407 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8408 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8409 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 8410 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8411 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8412 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8413 // CHECK11-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 8414 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8415 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8416 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 8417 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 8418 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 8419 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8420 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 8421 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8422 // CHECK11: cond.true: 8423 // CHECK11-NEXT: br label [[COND_END:%.*]] 8424 // CHECK11: cond.false: 8425 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8426 // CHECK11-NEXT: br label [[COND_END]] 8427 // CHECK11: cond.end: 8428 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 8429 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8430 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8431 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 8432 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8433 // CHECK11: omp.inner.for.cond: 8434 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8435 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8436 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 8437 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8438 // CHECK11: omp.inner.for.body: 8439 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8440 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 8441 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 8442 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 8443 // CHECK11-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 8444 // CHECK11-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 8445 // CHECK11-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 8446 // CHECK11: .cancel.exit: 8447 // CHECK11-NEXT: br label [[CANCEL_EXIT:%.*]] 8448 // CHECK11: .cancel.continue: 8449 // CHECK11-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 8450 // CHECK11-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 8451 // CHECK11-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 8452 // CHECK11: .cancel.exit2: 8453 // CHECK11-NEXT: br label [[CANCEL_EXIT]] 8454 // CHECK11: .cancel.continue3: 8455 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8456 // CHECK11: omp.body.continue: 8457 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8458 // CHECK11: omp.inner.for.inc: 8459 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8460 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 8461 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 8462 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 8463 // CHECK11: omp.inner.for.end: 8464 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8465 // CHECK11: omp.loop.exit: 8466 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 8467 // CHECK11-NEXT: br label [[CANCEL_CONT:%.*]] 8468 // CHECK11: cancel.cont: 8469 // CHECK11-NEXT: ret void 8470 // CHECK11: cancel.exit: 8471 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 8472 // CHECK11-NEXT: br label [[CANCEL_CONT]] 8473 // 8474 // 8475 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 8476 // CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 8477 // CHECK11-NEXT: entry: 8478 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8479 // CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 8480 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8481 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8482 // CHECK11-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 8483 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8484 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8485 // CHECK11-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 8486 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8487 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8488 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 8489 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8490 // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 8491 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8492 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 8493 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 8494 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 8495 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 8496 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 8497 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 8498 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 8499 // CHECK11-NEXT: ret void 8500 // 8501 // 8502 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 8503 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 8504 // CHECK11-NEXT: entry: 8505 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8506 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8507 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8508 // CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 8509 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8510 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8511 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 8512 // CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 8513 // CHECK11-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 8514 // CHECK11-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 8515 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8516 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8517 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 8518 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8519 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8 8520 // CHECK11-NEXT: [[LIN2:%.*]] = alloca i32, align 4 8521 // CHECK11-NEXT: [[A3:%.*]] = alloca i32, align 4 8522 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8523 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8524 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8525 // CHECK11-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 8526 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8527 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8528 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 8529 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 8530 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8531 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 8532 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 8533 // CHECK11-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 8534 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8535 // CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 8536 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 8537 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8538 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 8539 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 8540 // CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 8541 // CHECK11-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 8542 // CHECK11-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8543 // CHECK11-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 8544 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8545 // CHECK11: cond.true: 8546 // CHECK11-NEXT: br label [[COND_END:%.*]] 8547 // CHECK11: cond.false: 8548 // CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8549 // CHECK11-NEXT: br label [[COND_END]] 8550 // CHECK11: cond.end: 8551 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 8552 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 8553 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8554 // CHECK11-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 8555 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8556 // CHECK11: omp.inner.for.cond: 8557 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8558 // CHECK11-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8559 // CHECK11-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 8560 // CHECK11-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8561 // CHECK11: omp.inner.for.body: 8562 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8563 // CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 8564 // CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 8565 // CHECK11-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 8566 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 8567 // CHECK11-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 8568 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8569 // CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 8570 // CHECK11-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 8571 // CHECK11-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 8572 // CHECK11-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 8573 // CHECK11-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 8574 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 8575 // CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 8576 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8577 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 8578 // CHECK11-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 8579 // CHECK11-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 8580 // CHECK11-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 8581 // CHECK11-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 8582 // CHECK11-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 8583 // CHECK11-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 8584 // CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 8585 // CHECK11-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 8586 // CHECK11-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 8587 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8588 // CHECK11: omp.body.continue: 8589 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8590 // CHECK11: omp.inner.for.inc: 8591 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8592 // CHECK11-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 8593 // CHECK11-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 8594 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 8595 // CHECK11: omp.inner.for.end: 8596 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8597 // CHECK11: omp.loop.exit: 8598 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 8599 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 8600 // CHECK11-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 8601 // CHECK11-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 8602 // CHECK11: .omp.linear.pu: 8603 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 8604 // CHECK11-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 8605 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 8606 // CHECK11-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 8607 // CHECK11-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 8608 // CHECK11: .omp.linear.pu.done: 8609 // CHECK11-NEXT: ret void 8610 // 8611 // 8612 // CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv 8613 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 8614 // CHECK11-NEXT: entry: 8615 // CHECK11-NEXT: ret i64 0 8616 // 8617 // 8618 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 8619 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 8620 // CHECK11-NEXT: entry: 8621 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8622 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8623 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8624 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8625 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8626 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8627 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8628 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 8629 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 8630 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 8631 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 8632 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8633 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 8634 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8635 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 8636 // CHECK11-NEXT: ret void 8637 // 8638 // 8639 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 8640 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 8641 // CHECK11-NEXT: entry: 8642 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8643 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8644 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8645 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8646 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8647 // CHECK11-NEXT: [[TMP:%.*]] = alloca i16, align 2 8648 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8649 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8650 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8651 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8652 // CHECK11-NEXT: [[IT:%.*]] = alloca i16, align 2 8653 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8654 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8655 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8656 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8657 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8658 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8659 // CHECK11-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 8660 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8661 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8662 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 8663 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 8664 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 8665 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8666 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 8667 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8668 // CHECK11: cond.true: 8669 // CHECK11-NEXT: br label [[COND_END:%.*]] 8670 // CHECK11: cond.false: 8671 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8672 // CHECK11-NEXT: br label [[COND_END]] 8673 // CHECK11: cond.end: 8674 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 8675 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8676 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8677 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 8678 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8679 // CHECK11: omp.inner.for.cond: 8680 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8681 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8682 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 8683 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8684 // CHECK11: omp.inner.for.body: 8685 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8686 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 8687 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 8688 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 8689 // CHECK11-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 8690 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 8691 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 8692 // CHECK11-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 8693 // CHECK11-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 8694 // CHECK11-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 8695 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 8696 // CHECK11-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 8697 // CHECK11-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 8698 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8699 // CHECK11: omp.body.continue: 8700 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8701 // CHECK11: omp.inner.for.inc: 8702 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8703 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 8704 // CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 8705 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 8706 // CHECK11: omp.inner.for.end: 8707 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8708 // CHECK11: omp.loop.exit: 8709 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 8710 // CHECK11-NEXT: ret void 8711 // 8712 // 8713 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 8714 // CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 8715 // CHECK11-NEXT: entry: 8716 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8717 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 8718 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8719 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 8720 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 8721 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8722 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 8723 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 8724 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 8725 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 8726 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8727 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 8728 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8729 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 8730 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8731 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 8732 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 8733 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8734 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 8735 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 8736 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 8737 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 8738 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 8739 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8740 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 8741 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 8742 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8743 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 8744 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 8745 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 8746 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 8747 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 8748 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 8749 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 8750 // CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 8751 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 8752 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 8753 // CHECK11-NEXT: ret void 8754 // 8755 // 8756 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 8757 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 8758 // CHECK11-NEXT: entry: 8759 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8760 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8761 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8762 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 8763 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8764 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 8765 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 8766 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8767 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 8768 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 8769 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 8770 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 8771 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8772 // CHECK11-NEXT: [[TMP:%.*]] = alloca i8, align 1 8773 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8774 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8775 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8776 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8777 // CHECK11-NEXT: [[IT:%.*]] = alloca i8, align 1 8778 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8779 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8780 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8781 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 8782 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8783 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 8784 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 8785 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8786 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 8787 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 8788 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 8789 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 8790 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 8791 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8792 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 8793 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 8794 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8795 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 8796 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 8797 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 8798 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8799 // CHECK11-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 8800 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8801 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8802 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 8803 // CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 8804 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 8805 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 8806 // CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 8807 // CHECK11: omp.dispatch.cond: 8808 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8809 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 8810 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8811 // CHECK11: cond.true: 8812 // CHECK11-NEXT: br label [[COND_END:%.*]] 8813 // CHECK11: cond.false: 8814 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8815 // CHECK11-NEXT: br label [[COND_END]] 8816 // CHECK11: cond.end: 8817 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 8818 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8819 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8820 // CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 8821 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8822 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8823 // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 8824 // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 8825 // CHECK11: omp.dispatch.body: 8826 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8827 // CHECK11: omp.inner.for.cond: 8828 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8829 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8830 // CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 8831 // CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8832 // CHECK11: omp.inner.for.body: 8833 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8834 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 8835 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 8836 // CHECK11-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 8837 // CHECK11-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 8838 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 8839 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 8840 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 8841 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 8842 // CHECK11-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 8843 // CHECK11-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 8844 // CHECK11-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 8845 // CHECK11-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 8846 // CHECK11-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 8847 // CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 8848 // CHECK11-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 8849 // CHECK11-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 8850 // CHECK11-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 8851 // CHECK11-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 8852 // CHECK11-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 8853 // CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 8854 // CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 8855 // CHECK11-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 8856 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 8857 // CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 8858 // CHECK11-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 8859 // CHECK11-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 8860 // CHECK11-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 8861 // CHECK11-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 8862 // CHECK11-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 8863 // CHECK11-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 8864 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 8865 // CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 8866 // CHECK11-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 8867 // CHECK11-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 8868 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 8869 // CHECK11-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 8870 // CHECK11-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 8871 // CHECK11-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 8872 // CHECK11-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 8873 // CHECK11-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 8874 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8875 // CHECK11: omp.body.continue: 8876 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8877 // CHECK11: omp.inner.for.inc: 8878 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8879 // CHECK11-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 8880 // CHECK11-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 8881 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 8882 // CHECK11: omp.inner.for.end: 8883 // CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 8884 // CHECK11: omp.dispatch.inc: 8885 // CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8886 // CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 8887 // CHECK11-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 8888 // CHECK11-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 8889 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8890 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 8891 // CHECK11-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 8892 // CHECK11-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 8893 // CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] 8894 // CHECK11: omp.dispatch.end: 8895 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 8896 // CHECK11-NEXT: ret void 8897 // 8898 // 8899 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 8900 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 8901 // CHECK11-NEXT: entry: 8902 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8903 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8904 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 8905 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8906 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8907 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8908 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 8909 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8910 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8911 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 8912 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8913 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8914 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 8915 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8916 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8917 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 8918 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 8919 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 8920 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8921 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 8922 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8923 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 8924 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 8925 // CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 8926 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 8927 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 8928 // CHECK11-NEXT: ret void 8929 // 8930 // 8931 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 8932 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 8933 // CHECK11-NEXT: entry: 8934 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8935 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8936 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8937 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8938 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 8939 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8940 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8941 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 8942 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8943 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8944 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8945 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8946 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 8947 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8948 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8949 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 8950 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8951 // CHECK11-NEXT: ret void 8952 // 8953 // 8954 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 8955 // CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 8956 // CHECK11-NEXT: entry: 8957 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8958 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 8959 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8960 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8961 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 8962 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 8963 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8964 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 8965 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8966 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8967 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 8968 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 8969 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8970 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8971 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 8972 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 8973 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 8974 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 8975 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 8976 // CHECK11-NEXT: ret void 8977 // 8978 // 8979 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 8980 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 8981 // CHECK11-NEXT: entry: 8982 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8983 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8984 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8985 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 8986 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8987 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8988 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 8989 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8990 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 8991 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8992 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8993 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 8994 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8995 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8 8996 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8997 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8998 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8999 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 9000 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9001 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9002 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 9003 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 9004 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9005 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9006 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 9007 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 9008 // CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 9009 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 9010 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9011 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9012 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 9013 // CHECK11-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 9014 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9015 // CHECK11-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 9016 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9017 // CHECK11: cond.true: 9018 // CHECK11-NEXT: br label [[COND_END:%.*]] 9019 // CHECK11: cond.false: 9020 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9021 // CHECK11-NEXT: br label [[COND_END]] 9022 // CHECK11: cond.end: 9023 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 9024 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 9025 // CHECK11-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 9026 // CHECK11-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 9027 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9028 // CHECK11: omp.inner.for.cond: 9029 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9030 // CHECK11-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9031 // CHECK11-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 9032 // CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9033 // CHECK11: omp.inner.for.body: 9034 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9035 // CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 9036 // CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 9037 // CHECK11-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 9038 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 9039 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 9040 // CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 9041 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 9042 // CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4 9043 // CHECK11-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 9044 // CHECK11-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 9045 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 9046 // CHECK11-NEXT: store double [[INC]], double* [[A4]], align 4 9047 // CHECK11-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 9048 // CHECK11-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 9049 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 9050 // CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 9051 // CHECK11-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 9052 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9053 // CHECK11: omp.body.continue: 9054 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9055 // CHECK11: omp.inner.for.inc: 9056 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9057 // CHECK11-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 9058 // CHECK11-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 9059 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 9060 // CHECK11: omp.inner.for.end: 9061 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9062 // CHECK11: omp.loop.exit: 9063 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 9064 // CHECK11-NEXT: ret void 9065 // 9066 // 9067 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 9068 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 9069 // CHECK11-NEXT: entry: 9070 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9071 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9072 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9073 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9074 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9075 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9076 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9077 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9078 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9079 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9080 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 9081 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 9082 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 9083 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 9084 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9085 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 9086 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9087 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 9088 // CHECK11-NEXT: ret void 9089 // 9090 // 9091 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 9092 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 9093 // CHECK11-NEXT: entry: 9094 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9095 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9096 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9097 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9098 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9099 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9100 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 9101 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9102 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9103 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9104 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9105 // CHECK11-NEXT: [[I:%.*]] = alloca i64, align 8 9106 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9107 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9108 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9109 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9110 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9111 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9112 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9113 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 9114 // CHECK11-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 9115 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 9116 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9117 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9118 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 9119 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 9120 // CHECK11-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9121 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 9122 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9123 // CHECK11: cond.true: 9124 // CHECK11-NEXT: br label [[COND_END:%.*]] 9125 // CHECK11: cond.false: 9126 // CHECK11-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9127 // CHECK11-NEXT: br label [[COND_END]] 9128 // CHECK11: cond.end: 9129 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 9130 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 9131 // CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 9132 // CHECK11-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 9133 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9134 // CHECK11: omp.inner.for.cond: 9135 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9136 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9137 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 9138 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9139 // CHECK11: omp.inner.for.body: 9140 // CHECK11-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9141 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 9142 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 9143 // CHECK11-NEXT: store i64 [[ADD]], i64* [[I]], align 8 9144 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 9145 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 9146 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 9147 // CHECK11-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 9148 // CHECK11-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 9149 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 9150 // CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 9151 // CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 9152 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 9153 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 9154 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 9155 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 9156 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9157 // CHECK11: omp.body.continue: 9158 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9159 // CHECK11: omp.inner.for.inc: 9160 // CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9161 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 9162 // CHECK11-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 9163 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 9164 // CHECK11: omp.inner.for.end: 9165 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9166 // CHECK11: omp.loop.exit: 9167 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 9168 // CHECK11-NEXT: ret void 9169 // 9170 // 9171 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 9172 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 9173 // CHECK12-NEXT: entry: 9174 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 9175 // CHECK12-NEXT: ret void 9176 // 9177 // 9178 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 9179 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 9180 // CHECK12-NEXT: entry: 9181 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9182 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9183 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9184 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 9185 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9186 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9187 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9188 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9189 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 9190 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9191 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9192 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9193 // CHECK12-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 9194 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9195 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9196 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9197 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 9198 // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9199 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9200 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 9201 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9202 // CHECK12: cond.true: 9203 // CHECK12-NEXT: br label [[COND_END:%.*]] 9204 // CHECK12: cond.false: 9205 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9206 // CHECK12-NEXT: br label [[COND_END]] 9207 // CHECK12: cond.end: 9208 // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9209 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9210 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9211 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 9212 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9213 // CHECK12: omp.inner.for.cond: 9214 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9215 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9216 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9217 // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9218 // CHECK12: omp.inner.for.body: 9219 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9220 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 9221 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 9222 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 9223 // CHECK12-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 9224 // CHECK12-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 9225 // CHECK12-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 9226 // CHECK12: .cancel.exit: 9227 // CHECK12-NEXT: br label [[CANCEL_EXIT:%.*]] 9228 // CHECK12: .cancel.continue: 9229 // CHECK12-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 9230 // CHECK12-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 9231 // CHECK12-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 9232 // CHECK12: .cancel.exit2: 9233 // CHECK12-NEXT: br label [[CANCEL_EXIT]] 9234 // CHECK12: .cancel.continue3: 9235 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9236 // CHECK12: omp.body.continue: 9237 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9238 // CHECK12: omp.inner.for.inc: 9239 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9240 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 9241 // CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 9242 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 9243 // CHECK12: omp.inner.for.end: 9244 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9245 // CHECK12: omp.loop.exit: 9246 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 9247 // CHECK12-NEXT: br label [[CANCEL_CONT:%.*]] 9248 // CHECK12: cancel.cont: 9249 // CHECK12-NEXT: ret void 9250 // CHECK12: cancel.exit: 9251 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 9252 // CHECK12-NEXT: br label [[CANCEL_CONT]] 9253 // 9254 // 9255 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 9256 // CHECK12-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 9257 // CHECK12-NEXT: entry: 9258 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9259 // CHECK12-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 9260 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9261 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9262 // CHECK12-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 9263 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9264 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9265 // CHECK12-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 9266 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9267 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9268 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 9269 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9270 // CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 9271 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9272 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 9273 // CHECK12-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 9274 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 9275 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 9276 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 9277 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 9278 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 9279 // CHECK12-NEXT: ret void 9280 // 9281 // 9282 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 9283 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 9284 // CHECK12-NEXT: entry: 9285 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9286 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9287 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9288 // CHECK12-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 9289 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9290 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9291 // CHECK12-NEXT: [[TMP:%.*]] = alloca i64, align 4 9292 // CHECK12-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 9293 // CHECK12-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 9294 // CHECK12-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 9295 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9296 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9297 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9298 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9299 // CHECK12-NEXT: [[IT:%.*]] = alloca i64, align 8 9300 // CHECK12-NEXT: [[LIN2:%.*]] = alloca i32, align 4 9301 // CHECK12-NEXT: [[A3:%.*]] = alloca i32, align 4 9302 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9303 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9304 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9305 // CHECK12-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 9306 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9307 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9308 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 9309 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 9310 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 9311 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 9312 // CHECK12-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 9313 // CHECK12-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 9314 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 9315 // CHECK12-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 9316 // CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 9317 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9318 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9319 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 9320 // CHECK12-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 9321 // CHECK12-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 9322 // CHECK12-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9323 // CHECK12-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 9324 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9325 // CHECK12: cond.true: 9326 // CHECK12-NEXT: br label [[COND_END:%.*]] 9327 // CHECK12: cond.false: 9328 // CHECK12-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9329 // CHECK12-NEXT: br label [[COND_END]] 9330 // CHECK12: cond.end: 9331 // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 9332 // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 9333 // CHECK12-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 9334 // CHECK12-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 9335 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9336 // CHECK12: omp.inner.for.cond: 9337 // CHECK12-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9338 // CHECK12-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9339 // CHECK12-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 9340 // CHECK12-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9341 // CHECK12: omp.inner.for.body: 9342 // CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9343 // CHECK12-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 9344 // CHECK12-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 9345 // CHECK12-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 9346 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 9347 // CHECK12-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 9348 // CHECK12-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9349 // CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 9350 // CHECK12-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 9351 // CHECK12-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 9352 // CHECK12-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 9353 // CHECK12-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 9354 // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 9355 // CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 9356 // CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9357 // CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 9358 // CHECK12-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 9359 // CHECK12-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 9360 // CHECK12-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 9361 // CHECK12-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 9362 // CHECK12-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 9363 // CHECK12-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 9364 // CHECK12-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 9365 // CHECK12-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 9366 // CHECK12-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 9367 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9368 // CHECK12: omp.body.continue: 9369 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9370 // CHECK12: omp.inner.for.inc: 9371 // CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9372 // CHECK12-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 9373 // CHECK12-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 9374 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 9375 // CHECK12: omp.inner.for.end: 9376 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9377 // CHECK12: omp.loop.exit: 9378 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 9379 // CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9380 // CHECK12-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 9381 // CHECK12-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 9382 // CHECK12: .omp.linear.pu: 9383 // CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 9384 // CHECK12-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 9385 // CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 9386 // CHECK12-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 9387 // CHECK12-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 9388 // CHECK12: .omp.linear.pu.done: 9389 // CHECK12-NEXT: ret void 9390 // 9391 // 9392 // CHECK12-LABEL: define {{[^@]+}}@_Z7get_valv 9393 // CHECK12-SAME: () #[[ATTR3:[0-9]+]] { 9394 // CHECK12-NEXT: entry: 9395 // CHECK12-NEXT: ret i64 0 9396 // 9397 // 9398 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 9399 // CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 9400 // CHECK12-NEXT: entry: 9401 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9402 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9403 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9404 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9405 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9406 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9407 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9408 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 9409 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 9410 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 9411 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 9412 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9413 // CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 9414 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9415 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 9416 // CHECK12-NEXT: ret void 9417 // 9418 // 9419 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 9420 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 9421 // CHECK12-NEXT: entry: 9422 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9423 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9424 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9425 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9426 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9427 // CHECK12-NEXT: [[TMP:%.*]] = alloca i16, align 2 9428 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9429 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9430 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9431 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9432 // CHECK12-NEXT: [[IT:%.*]] = alloca i16, align 2 9433 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9434 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9435 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9436 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9437 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9438 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9439 // CHECK12-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 9440 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9441 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9442 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9443 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 9444 // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9445 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9446 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 9447 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9448 // CHECK12: cond.true: 9449 // CHECK12-NEXT: br label [[COND_END:%.*]] 9450 // CHECK12: cond.false: 9451 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9452 // CHECK12-NEXT: br label [[COND_END]] 9453 // CHECK12: cond.end: 9454 // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9455 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9456 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9457 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 9458 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9459 // CHECK12: omp.inner.for.cond: 9460 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9461 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9462 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9463 // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9464 // CHECK12: omp.inner.for.body: 9465 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9466 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 9467 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 9468 // CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 9469 // CHECK12-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 9470 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 9471 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 9472 // CHECK12-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 9473 // CHECK12-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 9474 // CHECK12-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 9475 // CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 9476 // CHECK12-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 9477 // CHECK12-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 9478 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9479 // CHECK12: omp.body.continue: 9480 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9481 // CHECK12: omp.inner.for.inc: 9482 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9483 // CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 9484 // CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 9485 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 9486 // CHECK12: omp.inner.for.end: 9487 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9488 // CHECK12: omp.loop.exit: 9489 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 9490 // CHECK12-NEXT: ret void 9491 // 9492 // 9493 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 9494 // CHECK12-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 9495 // CHECK12-NEXT: entry: 9496 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9497 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 9498 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9499 // CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 9500 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 9501 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9502 // CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 9503 // CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 9504 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 9505 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 9506 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9507 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 9508 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9509 // CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 9510 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9511 // CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 9512 // CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 9513 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9514 // CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 9515 // CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 9516 // CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 9517 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 9518 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 9519 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9520 // CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 9521 // CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 9522 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9523 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 9524 // CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 9525 // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 9526 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 9527 // CHECK12-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 9528 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 9529 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 9530 // CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 9531 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 9532 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 9533 // CHECK12-NEXT: ret void 9534 // 9535 // 9536 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 9537 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 9538 // CHECK12-NEXT: entry: 9539 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9540 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9541 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9542 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 9543 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9544 // CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 9545 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 9546 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9547 // CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 9548 // CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 9549 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 9550 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 9551 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9552 // CHECK12-NEXT: [[TMP:%.*]] = alloca i8, align 1 9553 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9554 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9555 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9556 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9557 // CHECK12-NEXT: [[IT:%.*]] = alloca i8, align 1 9558 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9559 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9560 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9561 // CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 9562 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9563 // CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 9564 // CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 9565 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9566 // CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 9567 // CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 9568 // CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 9569 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 9570 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 9571 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9572 // CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 9573 // CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 9574 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9575 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 9576 // CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 9577 // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 9578 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9579 // CHECK12-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 9580 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9581 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9582 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 9583 // CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9584 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 9585 // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 9586 // CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 9587 // CHECK12: omp.dispatch.cond: 9588 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9589 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 9590 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9591 // CHECK12: cond.true: 9592 // CHECK12-NEXT: br label [[COND_END:%.*]] 9593 // CHECK12: cond.false: 9594 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9595 // CHECK12-NEXT: br label [[COND_END]] 9596 // CHECK12: cond.end: 9597 // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 9598 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9599 // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9600 // CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 9601 // CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9602 // CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9603 // CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 9604 // CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 9605 // CHECK12: omp.dispatch.body: 9606 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9607 // CHECK12: omp.inner.for.cond: 9608 // CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9609 // CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9610 // CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 9611 // CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9612 // CHECK12: omp.inner.for.body: 9613 // CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9614 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 9615 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 9616 // CHECK12-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 9617 // CHECK12-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 9618 // CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 9619 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 9620 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 9621 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 9622 // CHECK12-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 9623 // CHECK12-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 9624 // CHECK12-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 9625 // CHECK12-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 9626 // CHECK12-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 9627 // CHECK12-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 9628 // CHECK12-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 9629 // CHECK12-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 9630 // CHECK12-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 9631 // CHECK12-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 9632 // CHECK12-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 9633 // CHECK12-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 9634 // CHECK12-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 9635 // CHECK12-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 9636 // CHECK12-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 9637 // CHECK12-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 9638 // CHECK12-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 9639 // CHECK12-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 9640 // CHECK12-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 9641 // CHECK12-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 9642 // CHECK12-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 9643 // CHECK12-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 9644 // CHECK12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 9645 // CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 9646 // CHECK12-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 9647 // CHECK12-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 9648 // CHECK12-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 9649 // CHECK12-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 9650 // CHECK12-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 9651 // CHECK12-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 9652 // CHECK12-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 9653 // CHECK12-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 9654 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9655 // CHECK12: omp.body.continue: 9656 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9657 // CHECK12: omp.inner.for.inc: 9658 // CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9659 // CHECK12-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 9660 // CHECK12-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 9661 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 9662 // CHECK12: omp.inner.for.end: 9663 // CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 9664 // CHECK12: omp.dispatch.inc: 9665 // CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9666 // CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 9667 // CHECK12-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 9668 // CHECK12-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 9669 // CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9670 // CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 9671 // CHECK12-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 9672 // CHECK12-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 9673 // CHECK12-NEXT: br label [[OMP_DISPATCH_COND]] 9674 // CHECK12: omp.dispatch.end: 9675 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 9676 // CHECK12-NEXT: ret void 9677 // 9678 // 9679 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 9680 // CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 9681 // CHECK12-NEXT: entry: 9682 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9683 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9684 // CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 9685 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9686 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9687 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9688 // CHECK12-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 9689 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9690 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9691 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 9692 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9693 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9694 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 9695 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9696 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 9697 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 9698 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 9699 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 9700 // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9701 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 9702 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9703 // CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 9704 // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 9705 // CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 9706 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 9707 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 9708 // CHECK12-NEXT: ret void 9709 // 9710 // 9711 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 9712 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 9713 // CHECK12-NEXT: entry: 9714 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9715 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9716 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9717 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9718 // CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 9719 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9720 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9721 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 9722 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9723 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9724 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9725 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9726 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 9727 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9728 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9729 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 9730 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9731 // CHECK12-NEXT: ret void 9732 // 9733 // 9734 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 9735 // CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 9736 // CHECK12-NEXT: entry: 9737 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 9738 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 9739 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9740 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9741 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 9742 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 9743 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 9744 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 9745 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9746 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9747 // CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 9748 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 9749 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9750 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9751 // CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 9752 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 9753 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 9754 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 9755 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 9756 // CHECK12-NEXT: ret void 9757 // 9758 // 9759 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 9760 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 9761 // CHECK12-NEXT: entry: 9762 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9763 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9764 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 9765 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 9766 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9767 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9768 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 9769 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9770 // CHECK12-NEXT: [[TMP:%.*]] = alloca i64, align 4 9771 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9772 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9773 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9774 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9775 // CHECK12-NEXT: [[IT:%.*]] = alloca i64, align 8 9776 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9777 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9778 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 9779 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 9780 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9781 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9782 // CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 9783 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 9784 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9785 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9786 // CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 9787 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 9788 // CHECK12-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 9789 // CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 9790 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9791 // CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9792 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 9793 // CHECK12-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 9794 // CHECK12-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9795 // CHECK12-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 9796 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9797 // CHECK12: cond.true: 9798 // CHECK12-NEXT: br label [[COND_END:%.*]] 9799 // CHECK12: cond.false: 9800 // CHECK12-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9801 // CHECK12-NEXT: br label [[COND_END]] 9802 // CHECK12: cond.end: 9803 // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 9804 // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 9805 // CHECK12-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 9806 // CHECK12-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 9807 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9808 // CHECK12: omp.inner.for.cond: 9809 // CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9810 // CHECK12-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9811 // CHECK12-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 9812 // CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9813 // CHECK12: omp.inner.for.body: 9814 // CHECK12-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9815 // CHECK12-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 9816 // CHECK12-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 9817 // CHECK12-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 9818 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 9819 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 9820 // CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 9821 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 9822 // CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4 9823 // CHECK12-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 9824 // CHECK12-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 9825 // CHECK12-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 9826 // CHECK12-NEXT: store double [[INC]], double* [[A4]], align 4 9827 // CHECK12-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 9828 // CHECK12-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 9829 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 9830 // CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 9831 // CHECK12-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 9832 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9833 // CHECK12: omp.body.continue: 9834 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9835 // CHECK12: omp.inner.for.inc: 9836 // CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9837 // CHECK12-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 9838 // CHECK12-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 9839 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 9840 // CHECK12: omp.inner.for.end: 9841 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9842 // CHECK12: omp.loop.exit: 9843 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 9844 // CHECK12-NEXT: ret void 9845 // 9846 // 9847 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 9848 // CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 9849 // CHECK12-NEXT: entry: 9850 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9851 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9852 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9853 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9854 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9855 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9856 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9857 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9858 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9859 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9860 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 9861 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 9862 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 9863 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 9864 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9865 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 9866 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9867 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 9868 // CHECK12-NEXT: ret void 9869 // 9870 // 9871 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 9872 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 9873 // CHECK12-NEXT: entry: 9874 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9875 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9876 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9877 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9878 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9879 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9880 // CHECK12-NEXT: [[TMP:%.*]] = alloca i64, align 4 9881 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9882 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9883 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9884 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9885 // CHECK12-NEXT: [[I:%.*]] = alloca i64, align 8 9886 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9887 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9888 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9889 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9890 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9891 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9892 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9893 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 9894 // CHECK12-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 9895 // CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 9896 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9897 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9898 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 9899 // CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 9900 // CHECK12-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9901 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 9902 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9903 // CHECK12: cond.true: 9904 // CHECK12-NEXT: br label [[COND_END:%.*]] 9905 // CHECK12: cond.false: 9906 // CHECK12-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9907 // CHECK12-NEXT: br label [[COND_END]] 9908 // CHECK12: cond.end: 9909 // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 9910 // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 9911 // CHECK12-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 9912 // CHECK12-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 9913 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9914 // CHECK12: omp.inner.for.cond: 9915 // CHECK12-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9916 // CHECK12-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9917 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 9918 // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9919 // CHECK12: omp.inner.for.body: 9920 // CHECK12-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9921 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 9922 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 9923 // CHECK12-NEXT: store i64 [[ADD]], i64* [[I]], align 8 9924 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 9925 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 9926 // CHECK12-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 9927 // CHECK12-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 9928 // CHECK12-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 9929 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 9930 // CHECK12-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 9931 // CHECK12-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 9932 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 9933 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 9934 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 9935 // CHECK12-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 9936 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9937 // CHECK12: omp.body.continue: 9938 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9939 // CHECK12: omp.inner.for.inc: 9940 // CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9941 // CHECK12-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 9942 // CHECK12-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 9943 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 9944 // CHECK12: omp.inner.for.end: 9945 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9946 // CHECK12: omp.loop.exit: 9947 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 9948 // CHECK12-NEXT: ret void 9949 // 9950 // 9951 // CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv 9952 // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { 9953 // CHECK17-NEXT: entry: 9954 // CHECK17-NEXT: ret i64 0 9955 // 9956 // 9957 // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi 9958 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 9959 // CHECK17-NEXT: entry: 9960 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9961 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 9962 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 9963 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 4 9964 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 9965 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 9966 // CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 9967 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 9968 // CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 9969 // CHECK17-NEXT: [[K:%.*]] = alloca i64, align 8 9970 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9971 // CHECK17-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 9972 // CHECK17-NEXT: [[LIN:%.*]] = alloca i32, align 4 9973 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9974 // CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 9975 // CHECK17-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8 9976 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 9977 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 9978 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 9979 // CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 9980 // CHECK17-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8 9981 // CHECK17-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8 9982 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 9983 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 9984 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 9985 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 9986 // CHECK17-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8 9987 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 9988 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8 9989 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8 9990 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8 9991 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 9992 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 9993 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9994 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 9995 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 9996 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 9997 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 9998 // CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 9999 // CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 10000 // CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 10001 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 10002 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 10003 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 10004 // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 10005 // CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 10006 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 10007 // CHECK17-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 10008 // CHECK17-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 10009 // CHECK17-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 10010 // CHECK17: omp_offload.failed: 10011 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 10012 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 10013 // CHECK17: omp_offload.cont: 10014 // CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 10015 // CHECK17-NEXT: store i64 [[CALL]], i64* [[K]], align 8 10016 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 10017 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10018 // CHECK17-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4 10019 // CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8 10020 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[K]], align 8 10021 // CHECK17-NEXT: store i64 [[TMP11]], i64* [[K_CASTED]], align 8 10022 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8 10023 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR4]] 10024 // CHECK17-NEXT: store i32 12, i32* [[LIN]], align 4 10025 // CHECK17-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 10026 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10027 // CHECK17-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 10028 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10029 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4 10030 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 10031 // CHECK17-NEXT: store i32 [[TMP15]], i32* [[CONV3]], align 4 10032 // CHECK17-NEXT: [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 10033 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 10034 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32* 10035 // CHECK17-NEXT: store i32 [[TMP17]], i32* [[CONV5]], align 4 10036 // CHECK17-NEXT: [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8 10037 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10038 // CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 10039 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP20]], align 8 10040 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10041 // CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 10042 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP22]], align 8 10043 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 10044 // CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8 10045 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 10046 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 10047 // CHECK17-NEXT: store i64 [[TMP16]], i64* [[TMP25]], align 8 10048 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 10049 // CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 10050 // CHECK17-NEXT: store i64 [[TMP16]], i64* [[TMP27]], align 8 10051 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 10052 // CHECK17-NEXT: store i8* null, i8** [[TMP28]], align 8 10053 // CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 10054 // CHECK17-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 10055 // CHECK17-NEXT: store i64 [[TMP18]], i64* [[TMP30]], align 8 10056 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 10057 // CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 10058 // CHECK17-NEXT: store i64 [[TMP18]], i64* [[TMP32]], align 8 10059 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 10060 // CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 10061 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10062 // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10063 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 10064 // CHECK17-NEXT: [[TMP37:%.*]] = load i16, i16* [[AA]], align 2 10065 // CHECK17-NEXT: store i16 [[TMP37]], i16* [[TMP36]], align 4 10066 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 10067 // CHECK17-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4 10068 // CHECK17-NEXT: store i32 [[TMP39]], i32* [[TMP38]], align 4 10069 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 10070 // CHECK17-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 10071 // CHECK17-NEXT: store i32 [[TMP41]], i32* [[TMP40]], align 4 10072 // CHECK17-NEXT: [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 10073 // CHECK17-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates* 10074 // CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0 10075 // CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0 10076 // CHECK17-NEXT: [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8 10077 // CHECK17-NEXT: [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 10078 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false) 10079 // CHECK17-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1 10080 // CHECK17-NEXT: [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon* 10081 // CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0 10082 // CHECK17-NEXT: [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8* 10083 // CHECK17-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8* 10084 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false) 10085 // CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1 10086 // CHECK17-NEXT: [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8* 10087 // CHECK17-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8* 10088 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false) 10089 // CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2 10090 // CHECK17-NEXT: [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8* 10091 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 10092 // CHECK17-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3 10093 // CHECK17-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 10094 // CHECK17-NEXT: store i16 [[TMP59]], i16* [[TMP58]], align 8 10095 // CHECK17-NEXT: [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]]) 10096 // CHECK17-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4 10097 // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32* 10098 // CHECK17-NEXT: store i32 [[TMP61]], i32* [[CONV7]], align 4 10099 // CHECK17-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8 10100 // CHECK17-NEXT: [[TMP63:%.*]] = load i16, i16* [[AA]], align 2 10101 // CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16* 10102 // CHECK17-NEXT: store i16 [[TMP63]], i16* [[CONV9]], align 2 10103 // CHECK17-NEXT: [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8 10104 // CHECK17-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4 10105 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10 10106 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 10107 // CHECK17: omp_if.then: 10108 // CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 10109 // CHECK17-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64* 10110 // CHECK17-NEXT: store i64 [[TMP62]], i64* [[TMP67]], align 8 10111 // CHECK17-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 10112 // CHECK17-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* 10113 // CHECK17-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8 10114 // CHECK17-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 10115 // CHECK17-NEXT: store i8* null, i8** [[TMP70]], align 8 10116 // CHECK17-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 10117 // CHECK17-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* 10118 // CHECK17-NEXT: store i64 [[TMP64]], i64* [[TMP72]], align 8 10119 // CHECK17-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 10120 // CHECK17-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* 10121 // CHECK17-NEXT: store i64 [[TMP64]], i64* [[TMP74]], align 8 10122 // CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 10123 // CHECK17-NEXT: store i8* null, i8** [[TMP75]], align 8 10124 // CHECK17-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 10125 // CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 10126 // CHECK17-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 10127 // CHECK17-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0 10128 // CHECK17-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]] 10129 // CHECK17: omp_offload.failed13: 10130 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 10131 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT14]] 10132 // CHECK17: omp_offload.cont14: 10133 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 10134 // CHECK17: omp_if.else: 10135 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 10136 // CHECK17-NEXT: br label [[OMP_IF_END]] 10137 // CHECK17: omp_if.end: 10138 // CHECK17-NEXT: [[TMP80:%.*]] = load i32, i32* [[A]], align 4 10139 // CHECK17-NEXT: store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4 10140 // CHECK17-NEXT: [[TMP81:%.*]] = load i32, i32* [[A]], align 4 10141 // CHECK17-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32* 10142 // CHECK17-NEXT: store i32 [[TMP81]], i32* [[CONV16]], align 4 10143 // CHECK17-NEXT: [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8 10144 // CHECK17-NEXT: [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 10145 // CHECK17-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 10146 // CHECK17-NEXT: store i32 [[TMP83]], i32* [[CONV17]], align 4 10147 // CHECK17-NEXT: [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 10148 // CHECK17-NEXT: [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4 10149 // CHECK17-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20 10150 // CHECK17-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 10151 // CHECK17: omp_if.then19: 10152 // CHECK17-NEXT: [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4 10153 // CHECK17-NEXT: [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]] 10154 // CHECK17-NEXT: [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8 10155 // CHECK17-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 10156 // CHECK17-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* 10157 // CHECK17-NEXT: store i64 [[TMP82]], i64* [[TMP90]], align 8 10158 // CHECK17-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 10159 // CHECK17-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i64* 10160 // CHECK17-NEXT: store i64 [[TMP82]], i64* [[TMP92]], align 8 10161 // CHECK17-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 10162 // CHECK17-NEXT: store i64 4, i64* [[TMP93]], align 8 10163 // CHECK17-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 10164 // CHECK17-NEXT: store i8* null, i8** [[TMP94]], align 8 10165 // CHECK17-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 10166 // CHECK17-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 10167 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8 10168 // CHECK17-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 10169 // CHECK17-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]** 10170 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8 10171 // CHECK17-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 10172 // CHECK17-NEXT: store i64 40, i64* [[TMP99]], align 8 10173 // CHECK17-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 10174 // CHECK17-NEXT: store i8* null, i8** [[TMP100]], align 8 10175 // CHECK17-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 10176 // CHECK17-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i64* 10177 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP102]], align 8 10178 // CHECK17-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 10179 // CHECK17-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to i64* 10180 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP104]], align 8 10181 // CHECK17-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 10182 // CHECK17-NEXT: store i64 8, i64* [[TMP105]], align 8 10183 // CHECK17-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 10184 // CHECK17-NEXT: store i8* null, i8** [[TMP106]], align 8 10185 // CHECK17-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 10186 // CHECK17-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** 10187 // CHECK17-NEXT: store float* [[VLA]], float** [[TMP108]], align 8 10188 // CHECK17-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 10189 // CHECK17-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to float** 10190 // CHECK17-NEXT: store float* [[VLA]], float** [[TMP110]], align 8 10191 // CHECK17-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 10192 // CHECK17-NEXT: store i64 [[TMP86]], i64* [[TMP111]], align 8 10193 // CHECK17-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 10194 // CHECK17-NEXT: store i8* null, i8** [[TMP112]], align 8 10195 // CHECK17-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 10196 // CHECK17-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** 10197 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8 10198 // CHECK17-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 10199 // CHECK17-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to [5 x [10 x double]]** 10200 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP116]], align 8 10201 // CHECK17-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 10202 // CHECK17-NEXT: store i64 400, i64* [[TMP117]], align 8 10203 // CHECK17-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 10204 // CHECK17-NEXT: store i8* null, i8** [[TMP118]], align 8 10205 // CHECK17-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 10206 // CHECK17-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i64* 10207 // CHECK17-NEXT: store i64 5, i64* [[TMP120]], align 8 10208 // CHECK17-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 10209 // CHECK17-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64* 10210 // CHECK17-NEXT: store i64 5, i64* [[TMP122]], align 8 10211 // CHECK17-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 10212 // CHECK17-NEXT: store i64 8, i64* [[TMP123]], align 8 10213 // CHECK17-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5 10214 // CHECK17-NEXT: store i8* null, i8** [[TMP124]], align 8 10215 // CHECK17-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 10216 // CHECK17-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* 10217 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP126]], align 8 10218 // CHECK17-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 10219 // CHECK17-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* 10220 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP128]], align 8 10221 // CHECK17-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 10222 // CHECK17-NEXT: store i64 8, i64* [[TMP129]], align 8 10223 // CHECK17-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6 10224 // CHECK17-NEXT: store i8* null, i8** [[TMP130]], align 8 10225 // CHECK17-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 10226 // CHECK17-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double** 10227 // CHECK17-NEXT: store double* [[VLA1]], double** [[TMP132]], align 8 10228 // CHECK17-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 10229 // CHECK17-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to double** 10230 // CHECK17-NEXT: store double* [[VLA1]], double** [[TMP134]], align 8 10231 // CHECK17-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 10232 // CHECK17-NEXT: store i64 [[TMP88]], i64* [[TMP135]], align 8 10233 // CHECK17-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7 10234 // CHECK17-NEXT: store i8* null, i8** [[TMP136]], align 8 10235 // CHECK17-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 10236 // CHECK17-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT** 10237 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 8 10238 // CHECK17-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 10239 // CHECK17-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to %struct.TT** 10240 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP140]], align 8 10241 // CHECK17-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 10242 // CHECK17-NEXT: store i64 16, i64* [[TMP141]], align 8 10243 // CHECK17-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8 10244 // CHECK17-NEXT: store i8* null, i8** [[TMP142]], align 8 10245 // CHECK17-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9 10246 // CHECK17-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i64* 10247 // CHECK17-NEXT: store i64 [[TMP84]], i64* [[TMP144]], align 8 10248 // CHECK17-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9 10249 // CHECK17-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to i64* 10250 // CHECK17-NEXT: store i64 [[TMP84]], i64* [[TMP146]], align 8 10251 // CHECK17-NEXT: [[TMP147:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 10252 // CHECK17-NEXT: store i64 4, i64* [[TMP147]], align 8 10253 // CHECK17-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9 10254 // CHECK17-NEXT: store i8* null, i8** [[TMP148]], align 8 10255 // CHECK17-NEXT: [[TMP149:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 10256 // CHECK17-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 10257 // CHECK17-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 10258 // CHECK17-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 10259 // CHECK17-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 10260 // CHECK17-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 10261 // CHECK17: omp_offload.failed23: 10262 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 10263 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT24]] 10264 // CHECK17: omp_offload.cont24: 10265 // CHECK17-NEXT: br label [[OMP_IF_END26:%.*]] 10266 // CHECK17: omp_if.else25: 10267 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 10268 // CHECK17-NEXT: br label [[OMP_IF_END26]] 10269 // CHECK17: omp_if.end26: 10270 // CHECK17-NEXT: [[TMP154:%.*]] = load i32, i32* [[A]], align 4 10271 // CHECK17-NEXT: [[TMP155:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 10272 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP155]]) 10273 // CHECK17-NEXT: ret i32 [[TMP154]] 10274 // 10275 // 10276 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 10277 // CHECK17-SAME: () #[[ATTR2:[0-9]+]] { 10278 // CHECK17-NEXT: entry: 10279 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 10280 // CHECK17-NEXT: ret void 10281 // 10282 // 10283 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 10284 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 10285 // CHECK17-NEXT: entry: 10286 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10287 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10288 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10289 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 10290 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10291 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10292 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10293 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10294 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 10295 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10296 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10297 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10298 // CHECK17-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 10299 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10300 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10301 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10302 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 10303 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10304 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10305 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 10306 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10307 // CHECK17: cond.true: 10308 // CHECK17-NEXT: br label [[COND_END:%.*]] 10309 // CHECK17: cond.false: 10310 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10311 // CHECK17-NEXT: br label [[COND_END]] 10312 // CHECK17: cond.end: 10313 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10314 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10315 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10316 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 10317 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10318 // CHECK17: omp.inner.for.cond: 10319 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10320 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10321 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10322 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10323 // CHECK17: omp.inner.for.body: 10324 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10325 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 10326 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 10327 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 10328 // CHECK17-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 10329 // CHECK17-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 10330 // CHECK17-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 10331 // CHECK17: .cancel.exit: 10332 // CHECK17-NEXT: br label [[CANCEL_EXIT:%.*]] 10333 // CHECK17: .cancel.continue: 10334 // CHECK17-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 10335 // CHECK17-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 10336 // CHECK17-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 10337 // CHECK17: .cancel.exit2: 10338 // CHECK17-NEXT: br label [[CANCEL_EXIT]] 10339 // CHECK17: .cancel.continue3: 10340 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10341 // CHECK17: omp.body.continue: 10342 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10343 // CHECK17: omp.inner.for.inc: 10344 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10345 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 10346 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 10347 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 10348 // CHECK17: omp.inner.for.end: 10349 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10350 // CHECK17: omp.loop.exit: 10351 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 10352 // CHECK17-NEXT: br label [[CANCEL_CONT:%.*]] 10353 // CHECK17: cancel.cont: 10354 // CHECK17-NEXT: ret void 10355 // CHECK17: cancel.exit: 10356 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 10357 // CHECK17-NEXT: br label [[CANCEL_CONT]] 10358 // 10359 // 10360 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 10361 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 10362 // CHECK17-NEXT: entry: 10363 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10364 // CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 10365 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10366 // CHECK17-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 10367 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10368 // CHECK17-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 10369 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10370 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 10371 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10372 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 10373 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 10374 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 10375 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 10376 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 10377 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 10378 // CHECK17-NEXT: ret void 10379 // 10380 // 10381 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 10382 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 10383 // CHECK17-NEXT: entry: 10384 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10385 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10386 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10387 // CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 10388 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10389 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 10390 // CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 10391 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10392 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10393 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10394 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10395 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 10396 // CHECK17-NEXT: [[K1:%.*]] = alloca i64, align 8 10397 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10398 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10399 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10400 // CHECK17-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 10401 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10402 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8 10403 // CHECK17-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8 10404 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10405 // CHECK17-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 10406 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10407 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10408 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10409 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 10410 // CHECK17-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 10411 // CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 10412 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 10413 // CHECK17: omp.dispatch.cond: 10414 // CHECK17-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 10415 // CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 10416 // CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 10417 // CHECK17: omp.dispatch.body: 10418 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10419 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 10420 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10421 // CHECK17: omp.inner.for.cond: 10422 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 10423 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 10424 // CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10425 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10426 // CHECK17: omp.inner.for.body: 10427 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 10428 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 10429 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 10430 // CHECK17-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12 10431 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12 10432 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 10433 // CHECK17-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 10434 // CHECK17-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 10435 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] 10436 // CHECK17-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12 10437 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12 10438 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 10439 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12 10440 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10441 // CHECK17: omp.body.continue: 10442 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10443 // CHECK17: omp.inner.for.inc: 10444 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 10445 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 10446 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 10447 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 10448 // CHECK17: omp.inner.for.end: 10449 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 10450 // CHECK17: omp.dispatch.inc: 10451 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 10452 // CHECK17: omp.dispatch.end: 10453 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10454 // CHECK17-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 10455 // CHECK17-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 10456 // CHECK17: .omp.linear.pu: 10457 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[K1]], align 8 10458 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[K_ADDR]], align 8 10459 // CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 10460 // CHECK17: .omp.linear.pu.done: 10461 // CHECK17-NEXT: ret void 10462 // 10463 // 10464 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 10465 // CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 10466 // CHECK17-NEXT: entry: 10467 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10468 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 10469 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10470 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10471 // CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 10472 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10473 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10474 // CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 10475 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10476 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10477 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 10478 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10479 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 10480 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10481 // CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 10482 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10483 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 10484 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 10485 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 10486 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 10487 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 10488 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10489 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 10490 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 10491 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 10492 // CHECK17-NEXT: ret void 10493 // 10494 // 10495 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 10496 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 10497 // CHECK17-NEXT: entry: 10498 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10499 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10500 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10501 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 10502 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10503 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10504 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 10505 // CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 10506 // CHECK17-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 10507 // CHECK17-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 10508 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10509 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10510 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10511 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10512 // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 10513 // CHECK17-NEXT: [[LIN4:%.*]] = alloca i32, align 4 10514 // CHECK17-NEXT: [[A5:%.*]] = alloca i32, align 4 10515 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10516 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10517 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10518 // CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 10519 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10520 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10521 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 10522 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10523 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 10524 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 10525 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 10526 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 10527 // CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 10528 // CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 10529 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 10530 // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 10531 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 10532 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10533 // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10534 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 10535 // CHECK17-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 10536 // CHECK17-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 10537 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10538 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 10539 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10540 // CHECK17: cond.true: 10541 // CHECK17-NEXT: br label [[COND_END:%.*]] 10542 // CHECK17: cond.false: 10543 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10544 // CHECK17-NEXT: br label [[COND_END]] 10545 // CHECK17: cond.end: 10546 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 10547 // CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 10548 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 10549 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 10550 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10551 // CHECK17: omp.inner.for.cond: 10552 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 10553 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10554 // CHECK17-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 10555 // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10556 // CHECK17: omp.inner.for.body: 10557 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 10558 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 10559 // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 10560 // CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 10561 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 10562 // CHECK17-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 10563 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 10564 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 10565 // CHECK17-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 10566 // CHECK17-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 10567 // CHECK17-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 10568 // CHECK17-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 10569 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 10570 // CHECK17-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 10571 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 10572 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 10573 // CHECK17-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 10574 // CHECK17-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 10575 // CHECK17-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 10576 // CHECK17-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 10577 // CHECK17-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 10578 // CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 10579 // CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 10580 // CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 10581 // CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 10582 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10583 // CHECK17: omp.body.continue: 10584 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10585 // CHECK17: omp.inner.for.inc: 10586 // CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 10587 // CHECK17-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 10588 // CHECK17-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 10589 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 10590 // CHECK17: omp.inner.for.end: 10591 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10592 // CHECK17: omp.loop.exit: 10593 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 10594 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10595 // CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 10596 // CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 10597 // CHECK17: .omp.linear.pu: 10598 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 10599 // CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 10600 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 10601 // CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 10602 // CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 10603 // CHECK17: .omp.linear.pu.done: 10604 // CHECK17-NEXT: ret void 10605 // 10606 // 10607 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map. 10608 // CHECK17-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 10609 // CHECK17-NEXT: entry: 10610 // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 10611 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 10612 // CHECK17-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 10613 // CHECK17-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 10614 // CHECK17-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 10615 // CHECK17-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 10616 // CHECK17-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 10617 // CHECK17-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 10618 // CHECK17-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 10619 // CHECK17-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 10620 // CHECK17-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 10621 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 10622 // CHECK17-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 10623 // CHECK17-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 10624 // CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 10625 // CHECK17-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 10626 // CHECK17-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 10627 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 10628 // CHECK17-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 10629 // CHECK17-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 10630 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 10631 // CHECK17-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 10632 // CHECK17-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 10633 // CHECK17-NEXT: ret void 10634 // 10635 // 10636 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. 10637 // CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 10638 // CHECK17-NEXT: entry: 10639 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 10640 // CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 10641 // CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 10642 // CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 10643 // CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 10644 // CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 10645 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 10646 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 10647 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 10648 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 10649 // CHECK17-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 10650 // CHECK17-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8 10651 // CHECK17-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8 10652 // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 10653 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 10654 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 10655 // CHECK17-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 10656 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 10657 // CHECK17-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 10658 // CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 10659 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 10660 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 10661 // CHECK17-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 10662 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 10663 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 10664 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 10665 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 10666 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 10667 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 10668 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 10669 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 10670 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 10671 // CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24 10672 // CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 10673 // CHECK17-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 10674 // CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24 10675 // CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 10676 // CHECK17-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 10677 // CHECK17-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 10678 // CHECK17-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 10679 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 10680 // CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 10681 // CHECK17-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 10682 // CHECK17-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 10683 // CHECK17-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 10684 // CHECK17-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24 10685 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 10686 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 10687 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 10688 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 10689 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 10690 // CHECK17-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 10691 // CHECK17-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 10692 // CHECK17-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 10693 // CHECK17: omp_offload.failed.i: 10694 // CHECK17-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 10695 // CHECK17-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 10696 // CHECK17-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24 10697 // CHECK17-NEXT: [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24 10698 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 10699 // CHECK17-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32* 10700 // CHECK17-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !24 10701 // CHECK17-NEXT: [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !24 10702 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 10703 // CHECK17-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32* 10704 // CHECK17-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !24 10705 // CHECK17-NEXT: [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !24 10706 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR4]] 10707 // CHECK17-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 10708 // CHECK17: .omp_outlined..3.exit: 10709 // CHECK17-NEXT: ret i32 0 10710 // 10711 // 10712 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 10713 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 10714 // CHECK17-NEXT: entry: 10715 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10716 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10717 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10718 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10719 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10720 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10721 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10722 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10723 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 10724 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10725 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 10726 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 10727 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 10728 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10729 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 10730 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10731 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 10732 // CHECK17-NEXT: ret void 10733 // 10734 // 10735 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 10736 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 10737 // CHECK17-NEXT: entry: 10738 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10739 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10740 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10741 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10742 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10743 // CHECK17-NEXT: [[TMP:%.*]] = alloca i16, align 2 10744 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10745 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10746 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10747 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10748 // CHECK17-NEXT: [[IT:%.*]] = alloca i16, align 2 10749 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10750 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10751 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10752 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10753 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10754 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10755 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10756 // CHECK17-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 10757 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10758 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10759 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10760 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 10761 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10762 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10763 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 10764 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10765 // CHECK17: cond.true: 10766 // CHECK17-NEXT: br label [[COND_END:%.*]] 10767 // CHECK17: cond.false: 10768 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10769 // CHECK17-NEXT: br label [[COND_END]] 10770 // CHECK17: cond.end: 10771 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10772 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10773 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10774 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 10775 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10776 // CHECK17: omp.inner.for.cond: 10777 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10778 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10779 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10780 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10781 // CHECK17: omp.inner.for.body: 10782 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10783 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 10784 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 10785 // CHECK17-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 10786 // CHECK17-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 10787 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 10788 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 10789 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 10790 // CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 10791 // CHECK17-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 10792 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 10793 // CHECK17-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 10794 // CHECK17-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 10795 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10796 // CHECK17: omp.body.continue: 10797 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10798 // CHECK17: omp.inner.for.inc: 10799 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10800 // CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 10801 // CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 10802 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 10803 // CHECK17: omp.inner.for.end: 10804 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10805 // CHECK17: omp.loop.exit: 10806 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 10807 // CHECK17-NEXT: ret void 10808 // 10809 // 10810 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 10811 // CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 10812 // CHECK17-NEXT: entry: 10813 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10814 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 10815 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10816 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 10817 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 10818 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10819 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10820 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 10821 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 10822 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 10823 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10824 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 10825 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10826 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 10827 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10828 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 10829 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 10830 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10831 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 10832 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 10833 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 10834 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 10835 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10836 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 10837 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10838 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 10839 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 10840 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10841 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 10842 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 10843 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 10844 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 10845 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 10846 // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10847 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 10848 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 10849 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 10850 // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 10851 // CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 10852 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 10853 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 10854 // CHECK17-NEXT: ret void 10855 // 10856 // 10857 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 10858 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 10859 // CHECK17-NEXT: entry: 10860 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10861 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10862 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10863 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 10864 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10865 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 10866 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 10867 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10868 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10869 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 10870 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 10871 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 10872 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10873 // CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1 10874 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10875 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10876 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10877 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10878 // CHECK17-NEXT: [[IT:%.*]] = alloca i8, align 1 10879 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10880 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10881 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10882 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 10883 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10884 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 10885 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 10886 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10887 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 10888 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 10889 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 10890 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 10891 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10892 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 10893 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10894 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 10895 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 10896 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10897 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 10898 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 10899 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 10900 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 10901 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10902 // CHECK17-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 10903 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10904 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10905 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 10906 // CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10907 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 10908 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 10909 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 10910 // CHECK17: omp.dispatch.cond: 10911 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10912 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 10913 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10914 // CHECK17: cond.true: 10915 // CHECK17-NEXT: br label [[COND_END:%.*]] 10916 // CHECK17: cond.false: 10917 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10918 // CHECK17-NEXT: br label [[COND_END]] 10919 // CHECK17: cond.end: 10920 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 10921 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10922 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10923 // CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 10924 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10925 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10926 // CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 10927 // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 10928 // CHECK17: omp.dispatch.body: 10929 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10930 // CHECK17: omp.inner.for.cond: 10931 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10932 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10933 // CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 10934 // CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10935 // CHECK17: omp.inner.for.body: 10936 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10937 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 10938 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 10939 // CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 10940 // CHECK17-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 10941 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 10942 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 10943 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10944 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 10945 // CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 10946 // CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 10947 // CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 10948 // CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 10949 // CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 10950 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 10951 // CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 10952 // CHECK17-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 10953 // CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 10954 // CHECK17-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 10955 // CHECK17-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 10956 // CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 10957 // CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 10958 // CHECK17-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 10959 // CHECK17-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 10960 // CHECK17-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 10961 // CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 10962 // CHECK17-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 10963 // CHECK17-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 10964 // CHECK17-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 10965 // CHECK17-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 10966 // CHECK17-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 10967 // CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 10968 // CHECK17-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 10969 // CHECK17-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 10970 // CHECK17-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 10971 // CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 10972 // CHECK17-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 10973 // CHECK17-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 10974 // CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 10975 // CHECK17-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 10976 // CHECK17-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 10977 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10978 // CHECK17: omp.body.continue: 10979 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10980 // CHECK17: omp.inner.for.inc: 10981 // CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10982 // CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 10983 // CHECK17-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 10984 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 10985 // CHECK17: omp.inner.for.end: 10986 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 10987 // CHECK17: omp.dispatch.inc: 10988 // CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10989 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 10990 // CHECK17-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 10991 // CHECK17-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 10992 // CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10993 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 10994 // CHECK17-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 10995 // CHECK17-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 10996 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 10997 // CHECK17: omp.dispatch.end: 10998 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 10999 // CHECK17-NEXT: ret void 11000 // 11001 // 11002 // CHECK17-LABEL: define {{[^@]+}}@_Z3bari 11003 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 11004 // CHECK17-NEXT: entry: 11005 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 11006 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 11007 // CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 11008 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 11009 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 11010 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 11011 // CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 11012 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 11013 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 11014 // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 11015 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 11016 // CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 11017 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 11018 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 11019 // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 11020 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 11021 // CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 11022 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 11023 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 11024 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 11025 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 11026 // CHECK17-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 11027 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 11028 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 11029 // CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 11030 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 11031 // CHECK17-NEXT: ret i32 [[TMP8]] 11032 // 11033 // 11034 // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 11035 // CHECK17-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 11036 // CHECK17-NEXT: entry: 11037 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 11038 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 11039 // CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 11040 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 11041 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 11042 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 11043 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 11044 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 11045 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 11046 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 11047 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 11048 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 11049 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 11050 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 11051 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 11052 // CHECK17-NEXT: store i32 [[ADD]], i32* [[B]], align 4 11053 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 11054 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 11055 // CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 11056 // CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 11057 // CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 11058 // CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 11059 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 11060 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 11061 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 11062 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 11063 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 11064 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 11065 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 11066 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11067 // CHECK17: omp_if.then: 11068 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 11069 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 11070 // CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 11071 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11072 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 11073 // CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 11074 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11075 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 11076 // CHECK17-NEXT: store double* [[A]], double** [[TMP13]], align 8 11077 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 11078 // CHECK17-NEXT: store i64 8, i64* [[TMP14]], align 8 11079 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 11080 // CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 11081 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 11082 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 11083 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 11084 // CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 11085 // CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 11086 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 11087 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 11088 // CHECK17-NEXT: store i64 4, i64* [[TMP20]], align 8 11089 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 11090 // CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 11091 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 11092 // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 11093 // CHECK17-NEXT: store i64 2, i64* [[TMP23]], align 8 11094 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 11095 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 11096 // CHECK17-NEXT: store i64 2, i64* [[TMP25]], align 8 11097 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 11098 // CHECK17-NEXT: store i64 8, i64* [[TMP26]], align 8 11099 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 11100 // CHECK17-NEXT: store i8* null, i8** [[TMP27]], align 8 11101 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 11102 // CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 11103 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 11104 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 11105 // CHECK17-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 11106 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 11107 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 11108 // CHECK17-NEXT: store i64 8, i64* [[TMP32]], align 8 11109 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 11110 // CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 11111 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 11112 // CHECK17-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 11113 // CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 11114 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 11115 // CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 11116 // CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 11117 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 11118 // CHECK17-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 11119 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 11120 // CHECK17-NEXT: store i8* null, i8** [[TMP39]], align 8 11121 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11122 // CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11123 // CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 11124 // CHECK17-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 11125 // CHECK17-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 11126 // CHECK17-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 11127 // CHECK17: omp_offload.failed: 11128 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 11129 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 11130 // CHECK17: omp_offload.cont: 11131 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 11132 // CHECK17: omp_if.else: 11133 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 11134 // CHECK17-NEXT: br label [[OMP_IF_END]] 11135 // CHECK17: omp_if.end: 11136 // CHECK17-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] 11137 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] 11138 // CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 11139 // CHECK17-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 11140 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 11141 // CHECK17-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 11142 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] 11143 // CHECK17-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 11144 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 11145 // CHECK17-NEXT: ret i32 [[ADD4]] 11146 // 11147 // 11148 // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici 11149 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 11150 // CHECK17-NEXT: entry: 11151 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 11152 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 11153 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 11154 // CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1 11155 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 11156 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11157 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11158 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 11159 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 11160 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 11161 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 11162 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 11163 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 11164 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 11165 // CHECK17-NEXT: store i8 0, i8* [[AAA]], align 1 11166 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 11167 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11168 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 11169 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 11170 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 11171 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11172 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 11173 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11174 // CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 11175 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 11176 // CHECK17-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 11177 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 11178 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 11179 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 11180 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11181 // CHECK17: omp_if.then: 11182 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11183 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 11184 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 11185 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11186 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 11187 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 11188 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 11189 // CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8 11190 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 11191 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 11192 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 11193 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 11194 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 11195 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 11196 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 11197 // CHECK17-NEXT: store i8* null, i8** [[TMP16]], align 8 11198 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 11199 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 11200 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 11201 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 11202 // CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 11203 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 11204 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 11205 // CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 11206 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 11207 // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 11208 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 11209 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 11210 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 11211 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 11212 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 11213 // CHECK17-NEXT: store i8* null, i8** [[TMP26]], align 8 11214 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11215 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11216 // CHECK17-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 11217 // CHECK17-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 11218 // CHECK17-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 11219 // CHECK17: omp_offload.failed: 11220 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 11221 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 11222 // CHECK17: omp_offload.cont: 11223 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 11224 // CHECK17: omp_if.else: 11225 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 11226 // CHECK17-NEXT: br label [[OMP_IF_END]] 11227 // CHECK17: omp_if.end: 11228 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 11229 // CHECK17-NEXT: ret i32 [[TMP31]] 11230 // 11231 // 11232 // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 11233 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 11234 // CHECK17-NEXT: entry: 11235 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 11236 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 11237 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 11238 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 11239 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11240 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11241 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 11242 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 11243 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 11244 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 11245 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 11246 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 11247 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 11248 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11249 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 11250 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 11251 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 11252 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11253 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 11254 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11255 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 11256 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 11257 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11258 // CHECK17: omp_if.then: 11259 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11260 // CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 11261 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 11262 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11263 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 11264 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 11265 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 11266 // CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8 11267 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 11268 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 11269 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 11270 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 11271 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 11272 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 11273 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 11274 // CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8 11275 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 11276 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 11277 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 11278 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 11279 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 11280 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 11281 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 11282 // CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 11283 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11284 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11285 // CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 11286 // CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 11287 // CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 11288 // CHECK17: omp_offload.failed: 11289 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 11290 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 11291 // CHECK17: omp_offload.cont: 11292 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 11293 // CHECK17: omp_if.else: 11294 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 11295 // CHECK17-NEXT: br label [[OMP_IF_END]] 11296 // CHECK17: omp_if.end: 11297 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 11298 // CHECK17-NEXT: ret i32 [[TMP24]] 11299 // 11300 // 11301 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 11302 // CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 11303 // CHECK17-NEXT: entry: 11304 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 11305 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 11306 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11307 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11308 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 11309 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 11310 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 11311 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 11312 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 11313 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 11314 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 11315 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 11316 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 11317 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 11318 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 11319 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 11320 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 11321 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 11322 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 11323 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 11324 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 11325 // CHECK17-NEXT: ret void 11326 // 11327 // 11328 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 11329 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 11330 // CHECK17-NEXT: entry: 11331 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11332 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11333 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 11334 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 11335 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11336 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11337 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 11338 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11339 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 11340 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11341 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11342 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11343 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11344 // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 11345 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11346 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11347 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 11348 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 11349 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 11350 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 11351 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 11352 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 11353 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 11354 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 11355 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 11356 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 11357 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 11358 // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 11359 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 11360 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11361 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11362 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 11363 // CHECK17-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 11364 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11365 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 11366 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11367 // CHECK17: cond.true: 11368 // CHECK17-NEXT: br label [[COND_END:%.*]] 11369 // CHECK17: cond.false: 11370 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11371 // CHECK17-NEXT: br label [[COND_END]] 11372 // CHECK17: cond.end: 11373 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 11374 // CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 11375 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 11376 // CHECK17-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 11377 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11378 // CHECK17: omp.inner.for.cond: 11379 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11380 // CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11381 // CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 11382 // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11383 // CHECK17: omp.inner.for.body: 11384 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11385 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 11386 // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 11387 // CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 11388 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 11389 // CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 11390 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 11391 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 11392 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 11393 // CHECK17-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11394 // CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 11395 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 11396 // CHECK17-NEXT: store double [[INC]], double* [[A5]], align 8 11397 // CHECK17-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 11398 // CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 11399 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 11400 // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 11401 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 11402 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11403 // CHECK17: omp.body.continue: 11404 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11405 // CHECK17: omp.inner.for.inc: 11406 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11407 // CHECK17-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 11408 // CHECK17-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 11409 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 11410 // CHECK17: omp.inner.for.end: 11411 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11412 // CHECK17: omp.loop.exit: 11413 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 11414 // CHECK17-NEXT: ret void 11415 // 11416 // 11417 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 11418 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 11419 // CHECK17-NEXT: entry: 11420 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11421 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11422 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 11423 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11424 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11425 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11426 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 11427 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11428 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11429 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 11430 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11431 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11432 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11433 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 11434 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11435 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 11436 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11437 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 11438 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 11439 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 11440 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11441 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 11442 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11443 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 11444 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 11445 // CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 11446 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 11447 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 11448 // CHECK17-NEXT: ret void 11449 // 11450 // 11451 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 11452 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 11453 // CHECK17-NEXT: entry: 11454 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11455 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11456 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11457 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11458 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 11459 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11460 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11461 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 11462 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11463 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11464 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11465 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11466 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 11467 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11468 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11469 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11470 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 11471 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11472 // CHECK17-NEXT: ret void 11473 // 11474 // 11475 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 11476 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 11477 // CHECK17-NEXT: entry: 11478 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11479 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11480 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11481 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11482 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11483 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11484 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11485 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11486 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11487 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11488 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11489 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 11490 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11491 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 11492 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 11493 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 11494 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11495 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 11496 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11497 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 11498 // CHECK17-NEXT: ret void 11499 // 11500 // 11501 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..14 11502 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 11503 // CHECK17-NEXT: entry: 11504 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11505 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11506 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11507 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11508 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11509 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11510 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 11511 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11512 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11513 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11514 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11515 // CHECK17-NEXT: [[I:%.*]] = alloca i64, align 8 11516 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11517 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11518 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11519 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11520 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11521 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11522 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11523 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11524 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 11525 // CHECK17-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 11526 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 11527 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11528 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11529 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 11530 // CHECK17-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 11531 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11532 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 11533 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11534 // CHECK17: cond.true: 11535 // CHECK17-NEXT: br label [[COND_END:%.*]] 11536 // CHECK17: cond.false: 11537 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11538 // CHECK17-NEXT: br label [[COND_END]] 11539 // CHECK17: cond.end: 11540 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 11541 // CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 11542 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 11543 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 11544 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11545 // CHECK17: omp.inner.for.cond: 11546 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11547 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11548 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 11549 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11550 // CHECK17: omp.inner.for.body: 11551 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11552 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 11553 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 11554 // CHECK17-NEXT: store i64 [[ADD]], i64* [[I]], align 8 11555 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 11556 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 11557 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 11558 // CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 11559 // CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 11560 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 11561 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 11562 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 11563 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 11564 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 11565 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 11566 // CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 11567 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11568 // CHECK17: omp.body.continue: 11569 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11570 // CHECK17: omp.inner.for.inc: 11571 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11572 // CHECK17-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 11573 // CHECK17-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 11574 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 11575 // CHECK17: omp.inner.for.end: 11576 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11577 // CHECK17: omp.loop.exit: 11578 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 11579 // CHECK17-NEXT: ret void 11580 // 11581 // 11582 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 11583 // CHECK17-SAME: () #[[ATTR6]] { 11584 // CHECK17-NEXT: entry: 11585 // CHECK17-NEXT: call void @__tgt_register_requires(i64 1) 11586 // CHECK17-NEXT: ret void 11587 // 11588 // 11589 // CHECK18-LABEL: define {{[^@]+}}@_Z7get_valv 11590 // CHECK18-SAME: () #[[ATTR0:[0-9]+]] { 11591 // CHECK18-NEXT: entry: 11592 // CHECK18-NEXT: ret i64 0 11593 // 11594 // 11595 // CHECK18-LABEL: define {{[^@]+}}@_Z3fooi 11596 // CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 11597 // CHECK18-NEXT: entry: 11598 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 11599 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 11600 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 11601 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x float], align 4 11602 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 11603 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 11604 // CHECK18-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 11605 // CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 11606 // CHECK18-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 11607 // CHECK18-NEXT: [[K:%.*]] = alloca i64, align 8 11608 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11609 // CHECK18-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 11610 // CHECK18-NEXT: [[LIN:%.*]] = alloca i32, align 4 11611 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11612 // CHECK18-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 11613 // CHECK18-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8 11614 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 11615 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 11616 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 11617 // CHECK18-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 11618 // CHECK18-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8 11619 // CHECK18-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8 11620 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 11621 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 11622 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 11623 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 11624 // CHECK18-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8 11625 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 11626 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8 11627 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8 11628 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8 11629 // CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 11630 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 11631 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 11632 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 11633 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 11634 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 11635 // CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 11636 // CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 11637 // CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 11638 // CHECK18-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 11639 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 11640 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 11641 // CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 11642 // CHECK18-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 11643 // CHECK18-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 11644 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 11645 // CHECK18-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 11646 // CHECK18-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 11647 // CHECK18-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 11648 // CHECK18: omp_offload.failed: 11649 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 11650 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 11651 // CHECK18: omp_offload.cont: 11652 // CHECK18-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 11653 // CHECK18-NEXT: store i64 [[CALL]], i64* [[K]], align 8 11654 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 11655 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11656 // CHECK18-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4 11657 // CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8 11658 // CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[K]], align 8 11659 // CHECK18-NEXT: store i64 [[TMP11]], i64* [[K_CASTED]], align 8 11660 // CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8 11661 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR4]] 11662 // CHECK18-NEXT: store i32 12, i32* [[LIN]], align 4 11663 // CHECK18-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 11664 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11665 // CHECK18-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 11666 // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11667 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4 11668 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 11669 // CHECK18-NEXT: store i32 [[TMP15]], i32* [[CONV3]], align 4 11670 // CHECK18-NEXT: [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 11671 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 11672 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32* 11673 // CHECK18-NEXT: store i32 [[TMP17]], i32* [[CONV5]], align 4 11674 // CHECK18-NEXT: [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8 11675 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11676 // CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 11677 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP20]], align 8 11678 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11679 // CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 11680 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP22]], align 8 11681 // CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 11682 // CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8 11683 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 11684 // CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 11685 // CHECK18-NEXT: store i64 [[TMP16]], i64* [[TMP25]], align 8 11686 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 11687 // CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 11688 // CHECK18-NEXT: store i64 [[TMP16]], i64* [[TMP27]], align 8 11689 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 11690 // CHECK18-NEXT: store i8* null, i8** [[TMP28]], align 8 11691 // CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 11692 // CHECK18-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 11693 // CHECK18-NEXT: store i64 [[TMP18]], i64* [[TMP30]], align 8 11694 // CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 11695 // CHECK18-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 11696 // CHECK18-NEXT: store i64 [[TMP18]], i64* [[TMP32]], align 8 11697 // CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 11698 // CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 11699 // CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11700 // CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11701 // CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 11702 // CHECK18-NEXT: [[TMP37:%.*]] = load i16, i16* [[AA]], align 2 11703 // CHECK18-NEXT: store i16 [[TMP37]], i16* [[TMP36]], align 4 11704 // CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 11705 // CHECK18-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4 11706 // CHECK18-NEXT: store i32 [[TMP39]], i32* [[TMP38]], align 4 11707 // CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 11708 // CHECK18-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 11709 // CHECK18-NEXT: store i32 [[TMP41]], i32* [[TMP40]], align 4 11710 // CHECK18-NEXT: [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 11711 // CHECK18-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates* 11712 // CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0 11713 // CHECK18-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0 11714 // CHECK18-NEXT: [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8 11715 // CHECK18-NEXT: [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 11716 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false) 11717 // CHECK18-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1 11718 // CHECK18-NEXT: [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon* 11719 // CHECK18-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0 11720 // CHECK18-NEXT: [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8* 11721 // CHECK18-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8* 11722 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false) 11723 // CHECK18-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1 11724 // CHECK18-NEXT: [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8* 11725 // CHECK18-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8* 11726 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false) 11727 // CHECK18-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2 11728 // CHECK18-NEXT: [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8* 11729 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 11730 // CHECK18-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3 11731 // CHECK18-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 11732 // CHECK18-NEXT: store i16 [[TMP59]], i16* [[TMP58]], align 8 11733 // CHECK18-NEXT: [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]]) 11734 // CHECK18-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4 11735 // CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32* 11736 // CHECK18-NEXT: store i32 [[TMP61]], i32* [[CONV7]], align 4 11737 // CHECK18-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8 11738 // CHECK18-NEXT: [[TMP63:%.*]] = load i16, i16* [[AA]], align 2 11739 // CHECK18-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16* 11740 // CHECK18-NEXT: store i16 [[TMP63]], i16* [[CONV9]], align 2 11741 // CHECK18-NEXT: [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8 11742 // CHECK18-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4 11743 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10 11744 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11745 // CHECK18: omp_if.then: 11746 // CHECK18-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 11747 // CHECK18-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64* 11748 // CHECK18-NEXT: store i64 [[TMP62]], i64* [[TMP67]], align 8 11749 // CHECK18-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 11750 // CHECK18-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* 11751 // CHECK18-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8 11752 // CHECK18-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 11753 // CHECK18-NEXT: store i8* null, i8** [[TMP70]], align 8 11754 // CHECK18-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 11755 // CHECK18-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* 11756 // CHECK18-NEXT: store i64 [[TMP64]], i64* [[TMP72]], align 8 11757 // CHECK18-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 11758 // CHECK18-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* 11759 // CHECK18-NEXT: store i64 [[TMP64]], i64* [[TMP74]], align 8 11760 // CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 11761 // CHECK18-NEXT: store i8* null, i8** [[TMP75]], align 8 11762 // CHECK18-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 11763 // CHECK18-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 11764 // CHECK18-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 11765 // CHECK18-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0 11766 // CHECK18-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]] 11767 // CHECK18: omp_offload.failed13: 11768 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 11769 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT14]] 11770 // CHECK18: omp_offload.cont14: 11771 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 11772 // CHECK18: omp_if.else: 11773 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 11774 // CHECK18-NEXT: br label [[OMP_IF_END]] 11775 // CHECK18: omp_if.end: 11776 // CHECK18-NEXT: [[TMP80:%.*]] = load i32, i32* [[A]], align 4 11777 // CHECK18-NEXT: store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4 11778 // CHECK18-NEXT: [[TMP81:%.*]] = load i32, i32* [[A]], align 4 11779 // CHECK18-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32* 11780 // CHECK18-NEXT: store i32 [[TMP81]], i32* [[CONV16]], align 4 11781 // CHECK18-NEXT: [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8 11782 // CHECK18-NEXT: [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 11783 // CHECK18-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 11784 // CHECK18-NEXT: store i32 [[TMP83]], i32* [[CONV17]], align 4 11785 // CHECK18-NEXT: [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 11786 // CHECK18-NEXT: [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4 11787 // CHECK18-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20 11788 // CHECK18-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 11789 // CHECK18: omp_if.then19: 11790 // CHECK18-NEXT: [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4 11791 // CHECK18-NEXT: [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]] 11792 // CHECK18-NEXT: [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8 11793 // CHECK18-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 11794 // CHECK18-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* 11795 // CHECK18-NEXT: store i64 [[TMP82]], i64* [[TMP90]], align 8 11796 // CHECK18-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 11797 // CHECK18-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i64* 11798 // CHECK18-NEXT: store i64 [[TMP82]], i64* [[TMP92]], align 8 11799 // CHECK18-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 11800 // CHECK18-NEXT: store i64 4, i64* [[TMP93]], align 8 11801 // CHECK18-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 11802 // CHECK18-NEXT: store i8* null, i8** [[TMP94]], align 8 11803 // CHECK18-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 11804 // CHECK18-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 11805 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8 11806 // CHECK18-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 11807 // CHECK18-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]** 11808 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8 11809 // CHECK18-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 11810 // CHECK18-NEXT: store i64 40, i64* [[TMP99]], align 8 11811 // CHECK18-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 11812 // CHECK18-NEXT: store i8* null, i8** [[TMP100]], align 8 11813 // CHECK18-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 11814 // CHECK18-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i64* 11815 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP102]], align 8 11816 // CHECK18-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 11817 // CHECK18-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to i64* 11818 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP104]], align 8 11819 // CHECK18-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 11820 // CHECK18-NEXT: store i64 8, i64* [[TMP105]], align 8 11821 // CHECK18-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 11822 // CHECK18-NEXT: store i8* null, i8** [[TMP106]], align 8 11823 // CHECK18-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 11824 // CHECK18-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** 11825 // CHECK18-NEXT: store float* [[VLA]], float** [[TMP108]], align 8 11826 // CHECK18-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 11827 // CHECK18-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to float** 11828 // CHECK18-NEXT: store float* [[VLA]], float** [[TMP110]], align 8 11829 // CHECK18-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 11830 // CHECK18-NEXT: store i64 [[TMP86]], i64* [[TMP111]], align 8 11831 // CHECK18-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 11832 // CHECK18-NEXT: store i8* null, i8** [[TMP112]], align 8 11833 // CHECK18-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 11834 // CHECK18-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** 11835 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8 11836 // CHECK18-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 11837 // CHECK18-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to [5 x [10 x double]]** 11838 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP116]], align 8 11839 // CHECK18-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 11840 // CHECK18-NEXT: store i64 400, i64* [[TMP117]], align 8 11841 // CHECK18-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 11842 // CHECK18-NEXT: store i8* null, i8** [[TMP118]], align 8 11843 // CHECK18-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 11844 // CHECK18-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i64* 11845 // CHECK18-NEXT: store i64 5, i64* [[TMP120]], align 8 11846 // CHECK18-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 11847 // CHECK18-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64* 11848 // CHECK18-NEXT: store i64 5, i64* [[TMP122]], align 8 11849 // CHECK18-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 11850 // CHECK18-NEXT: store i64 8, i64* [[TMP123]], align 8 11851 // CHECK18-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5 11852 // CHECK18-NEXT: store i8* null, i8** [[TMP124]], align 8 11853 // CHECK18-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 11854 // CHECK18-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* 11855 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP126]], align 8 11856 // CHECK18-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 11857 // CHECK18-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* 11858 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP128]], align 8 11859 // CHECK18-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 11860 // CHECK18-NEXT: store i64 8, i64* [[TMP129]], align 8 11861 // CHECK18-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6 11862 // CHECK18-NEXT: store i8* null, i8** [[TMP130]], align 8 11863 // CHECK18-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 11864 // CHECK18-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double** 11865 // CHECK18-NEXT: store double* [[VLA1]], double** [[TMP132]], align 8 11866 // CHECK18-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 11867 // CHECK18-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to double** 11868 // CHECK18-NEXT: store double* [[VLA1]], double** [[TMP134]], align 8 11869 // CHECK18-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 11870 // CHECK18-NEXT: store i64 [[TMP88]], i64* [[TMP135]], align 8 11871 // CHECK18-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7 11872 // CHECK18-NEXT: store i8* null, i8** [[TMP136]], align 8 11873 // CHECK18-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 11874 // CHECK18-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT** 11875 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 8 11876 // CHECK18-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 11877 // CHECK18-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to %struct.TT** 11878 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP140]], align 8 11879 // CHECK18-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 11880 // CHECK18-NEXT: store i64 16, i64* [[TMP141]], align 8 11881 // CHECK18-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8 11882 // CHECK18-NEXT: store i8* null, i8** [[TMP142]], align 8 11883 // CHECK18-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9 11884 // CHECK18-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i64* 11885 // CHECK18-NEXT: store i64 [[TMP84]], i64* [[TMP144]], align 8 11886 // CHECK18-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9 11887 // CHECK18-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to i64* 11888 // CHECK18-NEXT: store i64 [[TMP84]], i64* [[TMP146]], align 8 11889 // CHECK18-NEXT: [[TMP147:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 11890 // CHECK18-NEXT: store i64 4, i64* [[TMP147]], align 8 11891 // CHECK18-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9 11892 // CHECK18-NEXT: store i8* null, i8** [[TMP148]], align 8 11893 // CHECK18-NEXT: [[TMP149:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 11894 // CHECK18-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 11895 // CHECK18-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 11896 // CHECK18-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 11897 // CHECK18-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 11898 // CHECK18-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 11899 // CHECK18: omp_offload.failed23: 11900 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 11901 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT24]] 11902 // CHECK18: omp_offload.cont24: 11903 // CHECK18-NEXT: br label [[OMP_IF_END26:%.*]] 11904 // CHECK18: omp_if.else25: 11905 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 11906 // CHECK18-NEXT: br label [[OMP_IF_END26]] 11907 // CHECK18: omp_if.end26: 11908 // CHECK18-NEXT: [[TMP154:%.*]] = load i32, i32* [[A]], align 4 11909 // CHECK18-NEXT: [[TMP155:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 11910 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP155]]) 11911 // CHECK18-NEXT: ret i32 [[TMP154]] 11912 // 11913 // 11914 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 11915 // CHECK18-SAME: () #[[ATTR2:[0-9]+]] { 11916 // CHECK18-NEXT: entry: 11917 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 11918 // CHECK18-NEXT: ret void 11919 // 11920 // 11921 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. 11922 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 11923 // CHECK18-NEXT: entry: 11924 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11925 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11926 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11927 // CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 11928 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11929 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11930 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11931 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11932 // CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 11933 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11934 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11935 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 11936 // CHECK18-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 11937 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 11938 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11939 // CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11940 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 11941 // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 11942 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11943 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 11944 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11945 // CHECK18: cond.true: 11946 // CHECK18-NEXT: br label [[COND_END:%.*]] 11947 // CHECK18: cond.false: 11948 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11949 // CHECK18-NEXT: br label [[COND_END]] 11950 // CHECK18: cond.end: 11951 // CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 11952 // CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 11953 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 11954 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 11955 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11956 // CHECK18: omp.inner.for.cond: 11957 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 11958 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11959 // CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 11960 // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11961 // CHECK18: omp.inner.for.body: 11962 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 11963 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 11964 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 11965 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 11966 // CHECK18-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 11967 // CHECK18-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 11968 // CHECK18-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 11969 // CHECK18: .cancel.exit: 11970 // CHECK18-NEXT: br label [[CANCEL_EXIT:%.*]] 11971 // CHECK18: .cancel.continue: 11972 // CHECK18-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 11973 // CHECK18-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 11974 // CHECK18-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 11975 // CHECK18: .cancel.exit2: 11976 // CHECK18-NEXT: br label [[CANCEL_EXIT]] 11977 // CHECK18: .cancel.continue3: 11978 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11979 // CHECK18: omp.body.continue: 11980 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11981 // CHECK18: omp.inner.for.inc: 11982 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 11983 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 11984 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 11985 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] 11986 // CHECK18: omp.inner.for.end: 11987 // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11988 // CHECK18: omp.loop.exit: 11989 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 11990 // CHECK18-NEXT: br label [[CANCEL_CONT:%.*]] 11991 // CHECK18: cancel.cont: 11992 // CHECK18-NEXT: ret void 11993 // CHECK18: cancel.exit: 11994 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 11995 // CHECK18-NEXT: br label [[CANCEL_CONT]] 11996 // 11997 // 11998 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 11999 // CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 12000 // CHECK18-NEXT: entry: 12001 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12002 // CHECK18-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 12003 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 12004 // CHECK18-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 12005 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12006 // CHECK18-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 12007 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12008 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 12009 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 12010 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 12011 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 12012 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 12013 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 12014 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 12015 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 12016 // CHECK18-NEXT: ret void 12017 // 12018 // 12019 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 12020 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 12021 // CHECK18-NEXT: entry: 12022 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 12023 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 12024 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12025 // CHECK18-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 12026 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 12027 // CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 12028 // CHECK18-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 12029 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 12030 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 12031 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 12032 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12033 // CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 12034 // CHECK18-NEXT: [[K1:%.*]] = alloca i64, align 8 12035 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 12036 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 12037 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12038 // CHECK18-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 12039 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12040 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8 12041 // CHECK18-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8 12042 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 12043 // CHECK18-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 12044 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 12045 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12046 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 12047 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 12048 // CHECK18-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 12049 // CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 12050 // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 12051 // CHECK18: omp.dispatch.cond: 12052 // CHECK18-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 12053 // CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 12054 // CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 12055 // CHECK18: omp.dispatch.body: 12056 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 12057 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 12058 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12059 // CHECK18: omp.inner.for.cond: 12060 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 12061 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 12062 // CHECK18-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 12063 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12064 // CHECK18: omp.inner.for.body: 12065 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 12066 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 12067 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 12068 // CHECK18-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12 12069 // CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12 12070 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 12071 // CHECK18-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 12072 // CHECK18-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 12073 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] 12074 // CHECK18-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12 12075 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12 12076 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 12077 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12 12078 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12079 // CHECK18: omp.body.continue: 12080 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12081 // CHECK18: omp.inner.for.inc: 12082 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 12083 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 12084 // CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 12085 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 12086 // CHECK18: omp.inner.for.end: 12087 // CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 12088 // CHECK18: omp.dispatch.inc: 12089 // CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] 12090 // CHECK18: omp.dispatch.end: 12091 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 12092 // CHECK18-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 12093 // CHECK18-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 12094 // CHECK18: .omp.linear.pu: 12095 // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[K1]], align 8 12096 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[K_ADDR]], align 8 12097 // CHECK18-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 12098 // CHECK18: .omp.linear.pu.done: 12099 // CHECK18-NEXT: ret void 12100 // 12101 // 12102 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 12103 // CHECK18-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 12104 // CHECK18-NEXT: entry: 12105 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 12106 // CHECK18-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 12107 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12108 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 12109 // CHECK18-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 12110 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 12111 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 12112 // CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 12113 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12114 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 12115 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 12116 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12117 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 12118 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 12119 // CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 12120 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 12121 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 12122 // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 12123 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 12124 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 12125 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 12126 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 12127 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 12128 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 12129 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 12130 // CHECK18-NEXT: ret void 12131 // 12132 // 12133 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 12134 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 12135 // CHECK18-NEXT: entry: 12136 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 12137 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 12138 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 12139 // CHECK18-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 12140 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12141 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 12142 // CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8 12143 // CHECK18-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 12144 // CHECK18-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 12145 // CHECK18-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 12146 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 12147 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 12148 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 12149 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12150 // CHECK18-NEXT: [[IT:%.*]] = alloca i64, align 8 12151 // CHECK18-NEXT: [[LIN4:%.*]] = alloca i32, align 4 12152 // CHECK18-NEXT: [[A5:%.*]] = alloca i32, align 4 12153 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 12154 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 12155 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 12156 // CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 12157 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12158 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 12159 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 12160 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12161 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 12162 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 12163 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 12164 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 12165 // CHECK18-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 12166 // CHECK18-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 12167 // CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 12168 // CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 12169 // CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 12170 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12171 // CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 12172 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 12173 // CHECK18-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 12174 // CHECK18-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 12175 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 12176 // CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 12177 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12178 // CHECK18: cond.true: 12179 // CHECK18-NEXT: br label [[COND_END:%.*]] 12180 // CHECK18: cond.false: 12181 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 12182 // CHECK18-NEXT: br label [[COND_END]] 12183 // CHECK18: cond.end: 12184 // CHECK18-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 12185 // CHECK18-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 12186 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 12187 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 12188 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12189 // CHECK18: omp.inner.for.cond: 12190 // CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 12191 // CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 12192 // CHECK18-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 12193 // CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12194 // CHECK18: omp.inner.for.body: 12195 // CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 12196 // CHECK18-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 12197 // CHECK18-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 12198 // CHECK18-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 12199 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 12200 // CHECK18-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 12201 // CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 12202 // CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 12203 // CHECK18-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 12204 // CHECK18-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 12205 // CHECK18-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 12206 // CHECK18-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 12207 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 12208 // CHECK18-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 12209 // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 12210 // CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 12211 // CHECK18-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 12212 // CHECK18-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 12213 // CHECK18-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 12214 // CHECK18-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 12215 // CHECK18-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 12216 // CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 12217 // CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 12218 // CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 12219 // CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 12220 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12221 // CHECK18: omp.body.continue: 12222 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12223 // CHECK18: omp.inner.for.inc: 12224 // CHECK18-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 12225 // CHECK18-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 12226 // CHECK18-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 12227 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] 12228 // CHECK18: omp.inner.for.end: 12229 // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12230 // CHECK18: omp.loop.exit: 12231 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 12232 // CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 12233 // CHECK18-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 12234 // CHECK18-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 12235 // CHECK18: .omp.linear.pu: 12236 // CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 12237 // CHECK18-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 12238 // CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 12239 // CHECK18-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 12240 // CHECK18-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 12241 // CHECK18: .omp.linear.pu.done: 12242 // CHECK18-NEXT: ret void 12243 // 12244 // 12245 // CHECK18-LABEL: define {{[^@]+}}@.omp_task_privates_map. 12246 // CHECK18-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 12247 // CHECK18-NEXT: entry: 12248 // CHECK18-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 12249 // CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 12250 // CHECK18-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 12251 // CHECK18-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 12252 // CHECK18-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 12253 // CHECK18-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 12254 // CHECK18-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 12255 // CHECK18-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 12256 // CHECK18-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 12257 // CHECK18-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 12258 // CHECK18-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 12259 // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 12260 // CHECK18-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 12261 // CHECK18-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 12262 // CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 12263 // CHECK18-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 12264 // CHECK18-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 12265 // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 12266 // CHECK18-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 12267 // CHECK18-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 12268 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 12269 // CHECK18-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 12270 // CHECK18-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 12271 // CHECK18-NEXT: ret void 12272 // 12273 // 12274 // CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry. 12275 // CHECK18-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 12276 // CHECK18-NEXT: entry: 12277 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 12278 // CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 12279 // CHECK18-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 12280 // CHECK18-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 12281 // CHECK18-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 12282 // CHECK18-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 12283 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 12284 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 12285 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 12286 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 12287 // CHECK18-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 12288 // CHECK18-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8 12289 // CHECK18-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8 12290 // CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 12291 // CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 12292 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 12293 // CHECK18-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 12294 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 12295 // CHECK18-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 12296 // CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 12297 // CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 12298 // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 12299 // CHECK18-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 12300 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 12301 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 12302 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 12303 // CHECK18-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 12304 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 12305 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 12306 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 12307 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 12308 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 12309 // CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24 12310 // CHECK18-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 12311 // CHECK18-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 12312 // CHECK18-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24 12313 // CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 12314 // CHECK18-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 12315 // CHECK18-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 12316 // CHECK18-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 12317 // CHECK18-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 12318 // CHECK18-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 12319 // CHECK18-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 12320 // CHECK18-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 12321 // CHECK18-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 12322 // CHECK18-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24 12323 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 12324 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 12325 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 12326 // CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 12327 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 12328 // CHECK18-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 12329 // CHECK18-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 12330 // CHECK18-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 12331 // CHECK18: omp_offload.failed.i: 12332 // CHECK18-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 12333 // CHECK18-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 12334 // CHECK18-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24 12335 // CHECK18-NEXT: [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24 12336 // CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 12337 // CHECK18-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32* 12338 // CHECK18-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !24 12339 // CHECK18-NEXT: [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !24 12340 // CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 12341 // CHECK18-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32* 12342 // CHECK18-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !24 12343 // CHECK18-NEXT: [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !24 12344 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR4]] 12345 // CHECK18-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 12346 // CHECK18: .omp_outlined..3.exit: 12347 // CHECK18-NEXT: ret i32 0 12348 // 12349 // 12350 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 12351 // CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 12352 // CHECK18-NEXT: entry: 12353 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12354 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 12355 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 12356 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 12357 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12358 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 12359 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12360 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 12361 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 12362 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 12363 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 12364 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 12365 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 12366 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 12367 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 12368 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 12369 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 12370 // CHECK18-NEXT: ret void 12371 // 12372 // 12373 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 12374 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 12375 // CHECK18-NEXT: entry: 12376 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 12377 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 12378 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12379 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 12380 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 12381 // CHECK18-NEXT: [[TMP:%.*]] = alloca i16, align 2 12382 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 12383 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 12384 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 12385 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12386 // CHECK18-NEXT: [[IT:%.*]] = alloca i16, align 2 12387 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 12388 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 12389 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12390 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 12391 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12392 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 12393 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 12394 // CHECK18-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 12395 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 12396 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12397 // CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 12398 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 12399 // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 12400 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12401 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 12402 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12403 // CHECK18: cond.true: 12404 // CHECK18-NEXT: br label [[COND_END:%.*]] 12405 // CHECK18: cond.false: 12406 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12407 // CHECK18-NEXT: br label [[COND_END]] 12408 // CHECK18: cond.end: 12409 // CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 12410 // CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 12411 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 12412 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 12413 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12414 // CHECK18: omp.inner.for.cond: 12415 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 12416 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12417 // CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 12418 // CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12419 // CHECK18: omp.inner.for.body: 12420 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 12421 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 12422 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 12423 // CHECK18-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 12424 // CHECK18-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 12425 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 12426 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 12427 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 12428 // CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 12429 // CHECK18-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 12430 // CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 12431 // CHECK18-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 12432 // CHECK18-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 12433 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12434 // CHECK18: omp.body.continue: 12435 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12436 // CHECK18: omp.inner.for.inc: 12437 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 12438 // CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 12439 // CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 12440 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] 12441 // CHECK18: omp.inner.for.end: 12442 // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12443 // CHECK18: omp.loop.exit: 12444 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 12445 // CHECK18-NEXT: ret void 12446 // 12447 // 12448 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 12449 // CHECK18-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 12450 // CHECK18-NEXT: entry: 12451 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12452 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 12453 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 12454 // CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 12455 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 12456 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 12457 // CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 12458 // CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 12459 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 12460 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 12461 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 12462 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 12463 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12464 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 12465 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 12466 // CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 12467 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 12468 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 12469 // CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 12470 // CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 12471 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 12472 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 12473 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12474 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 12475 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 12476 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 12477 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 12478 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 12479 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 12480 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 12481 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 12482 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 12483 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 12484 // CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 12485 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 12486 // CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 12487 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 12488 // CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 12489 // CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 12490 // CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 12491 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 12492 // CHECK18-NEXT: ret void 12493 // 12494 // 12495 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 12496 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 12497 // CHECK18-NEXT: entry: 12498 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 12499 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 12500 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12501 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 12502 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 12503 // CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 12504 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 12505 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 12506 // CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 12507 // CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 12508 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 12509 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 12510 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 12511 // CHECK18-NEXT: [[TMP:%.*]] = alloca i8, align 1 12512 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 12513 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 12514 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 12515 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12516 // CHECK18-NEXT: [[IT:%.*]] = alloca i8, align 1 12517 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 12518 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 12519 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12520 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 12521 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 12522 // CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 12523 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 12524 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 12525 // CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 12526 // CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 12527 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 12528 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 12529 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12530 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 12531 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 12532 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 12533 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 12534 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 12535 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 12536 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 12537 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 12538 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 12539 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 12540 // CHECK18-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 12541 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 12542 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12543 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 12544 // CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 12545 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 12546 // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 12547 // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 12548 // CHECK18: omp.dispatch.cond: 12549 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12550 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 12551 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12552 // CHECK18: cond.true: 12553 // CHECK18-NEXT: br label [[COND_END:%.*]] 12554 // CHECK18: cond.false: 12555 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12556 // CHECK18-NEXT: br label [[COND_END]] 12557 // CHECK18: cond.end: 12558 // CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 12559 // CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 12560 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 12561 // CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 12562 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 12563 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12564 // CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 12565 // CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 12566 // CHECK18: omp.dispatch.body: 12567 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12568 // CHECK18: omp.inner.for.cond: 12569 // CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 12570 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12571 // CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 12572 // CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12573 // CHECK18: omp.inner.for.body: 12574 // CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 12575 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 12576 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 12577 // CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 12578 // CHECK18-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 12579 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 12580 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 12581 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 12582 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 12583 // CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 12584 // CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 12585 // CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 12586 // CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 12587 // CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 12588 // CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 12589 // CHECK18-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 12590 // CHECK18-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 12591 // CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 12592 // CHECK18-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 12593 // CHECK18-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 12594 // CHECK18-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 12595 // CHECK18-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 12596 // CHECK18-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 12597 // CHECK18-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 12598 // CHECK18-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 12599 // CHECK18-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 12600 // CHECK18-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 12601 // CHECK18-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 12602 // CHECK18-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 12603 // CHECK18-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 12604 // CHECK18-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 12605 // CHECK18-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 12606 // CHECK18-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 12607 // CHECK18-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 12608 // CHECK18-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 12609 // CHECK18-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 12610 // CHECK18-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 12611 // CHECK18-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 12612 // CHECK18-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 12613 // CHECK18-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 12614 // CHECK18-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 12615 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12616 // CHECK18: omp.body.continue: 12617 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12618 // CHECK18: omp.inner.for.inc: 12619 // CHECK18-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 12620 // CHECK18-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 12621 // CHECK18-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 12622 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] 12623 // CHECK18: omp.inner.for.end: 12624 // CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 12625 // CHECK18: omp.dispatch.inc: 12626 // CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 12627 // CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 12628 // CHECK18-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 12629 // CHECK18-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 12630 // CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12631 // CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 12632 // CHECK18-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 12633 // CHECK18-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 12634 // CHECK18-NEXT: br label [[OMP_DISPATCH_COND]] 12635 // CHECK18: omp.dispatch.end: 12636 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 12637 // CHECK18-NEXT: ret void 12638 // 12639 // 12640 // CHECK18-LABEL: define {{[^@]+}}@_Z3bari 12641 // CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 12642 // CHECK18-NEXT: entry: 12643 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12644 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 12645 // CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 12646 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12647 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 12648 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 12649 // CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 12650 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 12651 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 12652 // CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 12653 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 12654 // CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 12655 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 12656 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 12657 // CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 12658 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 12659 // CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 12660 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 12661 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 12662 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 12663 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 12664 // CHECK18-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 12665 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 12666 // CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 12667 // CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 12668 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 12669 // CHECK18-NEXT: ret i32 [[TMP8]] 12670 // 12671 // 12672 // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 12673 // CHECK18-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 12674 // CHECK18-NEXT: entry: 12675 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 12676 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12677 // CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 12678 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 12679 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 12680 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 12681 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 12682 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 12683 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 12684 // CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 12685 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 12686 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12687 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 12688 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 12689 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 12690 // CHECK18-NEXT: store i32 [[ADD]], i32* [[B]], align 4 12691 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 12692 // CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 12693 // CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 12694 // CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 12695 // CHECK18-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 12696 // CHECK18-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 12697 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 12698 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 12699 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 12700 // CHECK18-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 12701 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 12702 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 12703 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 12704 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12705 // CHECK18: omp_if.then: 12706 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 12707 // CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 12708 // CHECK18-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 12709 // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12710 // CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 12711 // CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 12712 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12713 // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 12714 // CHECK18-NEXT: store double* [[A]], double** [[TMP13]], align 8 12715 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 12716 // CHECK18-NEXT: store i64 8, i64* [[TMP14]], align 8 12717 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 12718 // CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 12719 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 12720 // CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 12721 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 12722 // CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 12723 // CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 12724 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 12725 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 12726 // CHECK18-NEXT: store i64 4, i64* [[TMP20]], align 8 12727 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 12728 // CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8 12729 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 12730 // CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 12731 // CHECK18-NEXT: store i64 2, i64* [[TMP23]], align 8 12732 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 12733 // CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 12734 // CHECK18-NEXT: store i64 2, i64* [[TMP25]], align 8 12735 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 12736 // CHECK18-NEXT: store i64 8, i64* [[TMP26]], align 8 12737 // CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 12738 // CHECK18-NEXT: store i8* null, i8** [[TMP27]], align 8 12739 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 12740 // CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 12741 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 12742 // CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 12743 // CHECK18-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 12744 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 12745 // CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 12746 // CHECK18-NEXT: store i64 8, i64* [[TMP32]], align 8 12747 // CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 12748 // CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 12749 // CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 12750 // CHECK18-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 12751 // CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 12752 // CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 12753 // CHECK18-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 12754 // CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 12755 // CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 12756 // CHECK18-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 12757 // CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 12758 // CHECK18-NEXT: store i8* null, i8** [[TMP39]], align 8 12759 // CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12760 // CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12761 // CHECK18-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 12762 // CHECK18-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 12763 // CHECK18-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 12764 // CHECK18-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 12765 // CHECK18: omp_offload.failed: 12766 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 12767 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 12768 // CHECK18: omp_offload.cont: 12769 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 12770 // CHECK18: omp_if.else: 12771 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 12772 // CHECK18-NEXT: br label [[OMP_IF_END]] 12773 // CHECK18: omp_if.end: 12774 // CHECK18-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] 12775 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] 12776 // CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 12777 // CHECK18-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 12778 // CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 12779 // CHECK18-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 12780 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] 12781 // CHECK18-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 12782 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 12783 // CHECK18-NEXT: ret i32 [[ADD4]] 12784 // 12785 // 12786 // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici 12787 // CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 12788 // CHECK18-NEXT: entry: 12789 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12790 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 12791 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 12792 // CHECK18-NEXT: [[AAA:%.*]] = alloca i8, align 1 12793 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 12794 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 12795 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 12796 // CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 12797 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 12798 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 12799 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 12800 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12801 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 12802 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 12803 // CHECK18-NEXT: store i8 0, i8* [[AAA]], align 1 12804 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 12805 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 12806 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 12807 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 12808 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 12809 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 12810 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 12811 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 12812 // CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 12813 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 12814 // CHECK18-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 12815 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 12816 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 12817 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 12818 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12819 // CHECK18: omp_if.then: 12820 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12821 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 12822 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 12823 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12824 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 12825 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 12826 // CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 12827 // CHECK18-NEXT: store i8* null, i8** [[TMP11]], align 8 12828 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 12829 // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 12830 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 12831 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 12832 // CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 12833 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 12834 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 12835 // CHECK18-NEXT: store i8* null, i8** [[TMP16]], align 8 12836 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 12837 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 12838 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 12839 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 12840 // CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 12841 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 12842 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 12843 // CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8 12844 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 12845 // CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 12846 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 12847 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 12848 // CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 12849 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 12850 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 12851 // CHECK18-NEXT: store i8* null, i8** [[TMP26]], align 8 12852 // CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12853 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12854 // CHECK18-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 12855 // CHECK18-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 12856 // CHECK18-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 12857 // CHECK18: omp_offload.failed: 12858 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 12859 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 12860 // CHECK18: omp_offload.cont: 12861 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 12862 // CHECK18: omp_if.else: 12863 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 12864 // CHECK18-NEXT: br label [[OMP_IF_END]] 12865 // CHECK18: omp_if.end: 12866 // CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 12867 // CHECK18-NEXT: ret i32 [[TMP31]] 12868 // 12869 // 12870 // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 12871 // CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 12872 // CHECK18-NEXT: entry: 12873 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12874 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 12875 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 12876 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 12877 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 12878 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 12879 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 12880 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 12881 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 12882 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12883 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 12884 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 12885 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 12886 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 12887 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 12888 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 12889 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 12890 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 12891 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 12892 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 12893 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 12894 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 12895 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12896 // CHECK18: omp_if.then: 12897 // CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12898 // CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 12899 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 12900 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12901 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 12902 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 12903 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 12904 // CHECK18-NEXT: store i8* null, i8** [[TMP9]], align 8 12905 // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 12906 // CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 12907 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 12908 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 12909 // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 12910 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 12911 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 12912 // CHECK18-NEXT: store i8* null, i8** [[TMP14]], align 8 12913 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 12914 // CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 12915 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 12916 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 12917 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 12918 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 12919 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 12920 // CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 12921 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12922 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12923 // CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 12924 // CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 12925 // CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 12926 // CHECK18: omp_offload.failed: 12927 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 12928 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 12929 // CHECK18: omp_offload.cont: 12930 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 12931 // CHECK18: omp_if.else: 12932 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 12933 // CHECK18-NEXT: br label [[OMP_IF_END]] 12934 // CHECK18: omp_if.end: 12935 // CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 12936 // CHECK18-NEXT: ret i32 [[TMP24]] 12937 // 12938 // 12939 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 12940 // CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 12941 // CHECK18-NEXT: entry: 12942 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 12943 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 12944 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 12945 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 12946 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 12947 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 12948 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 12949 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 12950 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 12951 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 12952 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 12953 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 12954 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 12955 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 12956 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 12957 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 12958 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 12959 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 12960 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 12961 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 12962 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 12963 // CHECK18-NEXT: ret void 12964 // 12965 // 12966 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 12967 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 12968 // CHECK18-NEXT: entry: 12969 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 12970 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 12971 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 12972 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 12973 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 12974 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 12975 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 12976 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 12977 // CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8 12978 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 12979 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 12980 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 12981 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12982 // CHECK18-NEXT: [[IT:%.*]] = alloca i64, align 8 12983 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 12984 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 12985 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 12986 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 12987 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 12988 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 12989 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 12990 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 12991 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 12992 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 12993 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 12994 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 12995 // CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 12996 // CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 12997 // CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 12998 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12999 // CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 13000 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 13001 // CHECK18-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 13002 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 13003 // CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 13004 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 13005 // CHECK18: cond.true: 13006 // CHECK18-NEXT: br label [[COND_END:%.*]] 13007 // CHECK18: cond.false: 13008 // CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 13009 // CHECK18-NEXT: br label [[COND_END]] 13010 // CHECK18: cond.end: 13011 // CHECK18-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 13012 // CHECK18-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 13013 // CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 13014 // CHECK18-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 13015 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 13016 // CHECK18: omp.inner.for.cond: 13017 // CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13018 // CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 13019 // CHECK18-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 13020 // CHECK18-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 13021 // CHECK18: omp.inner.for.body: 13022 // CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13023 // CHECK18-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 13024 // CHECK18-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 13025 // CHECK18-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 13026 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 13027 // CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 13028 // CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 13029 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 13030 // CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 13031 // CHECK18-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 13032 // CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 13033 // CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 13034 // CHECK18-NEXT: store double [[INC]], double* [[A5]], align 8 13035 // CHECK18-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 13036 // CHECK18-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 13037 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 13038 // CHECK18-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 13039 // CHECK18-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 13040 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 13041 // CHECK18: omp.body.continue: 13042 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 13043 // CHECK18: omp.inner.for.inc: 13044 // CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13045 // CHECK18-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 13046 // CHECK18-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 13047 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] 13048 // CHECK18: omp.inner.for.end: 13049 // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 13050 // CHECK18: omp.loop.exit: 13051 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 13052 // CHECK18-NEXT: ret void 13053 // 13054 // 13055 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 13056 // CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 13057 // CHECK18-NEXT: entry: 13058 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 13059 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13060 // CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 13061 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 13062 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 13063 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 13064 // CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 13065 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 13066 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13067 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 13068 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 13069 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 13070 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13071 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 13072 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 13073 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 13074 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 13075 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 13076 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 13077 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 13078 // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 13079 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 13080 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 13081 // CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 13082 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 13083 // CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 13084 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 13085 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 13086 // CHECK18-NEXT: ret void 13087 // 13088 // 13089 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 13090 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 13091 // CHECK18-NEXT: entry: 13092 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13093 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13094 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 13095 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13096 // CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 13097 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 13098 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 13099 // CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 13100 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13101 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13102 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 13103 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13104 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 13105 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 13106 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 13107 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13108 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 13109 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 13110 // CHECK18-NEXT: ret void 13111 // 13112 // 13113 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 13114 // CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 13115 // CHECK18-NEXT: entry: 13116 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 13117 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13118 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 13119 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 13120 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 13121 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 13122 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13123 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 13124 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 13125 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13126 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 13127 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 13128 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 13129 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 13130 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 13131 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 13132 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 13133 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 13134 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 13135 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 13136 // CHECK18-NEXT: ret void 13137 // 13138 // 13139 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..14 13140 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 13141 // CHECK18-NEXT: entry: 13142 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13143 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13144 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 13145 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13146 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 13147 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 13148 // CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8 13149 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 13150 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 13151 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 13152 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 13153 // CHECK18-NEXT: [[I:%.*]] = alloca i64, align 8 13154 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13155 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13156 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 13157 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13158 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 13159 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 13160 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13161 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 13162 // CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 13163 // CHECK18-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 13164 // CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 13165 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 13166 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 13167 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 13168 // CHECK18-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 13169 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 13170 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 13171 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 13172 // CHECK18: cond.true: 13173 // CHECK18-NEXT: br label [[COND_END:%.*]] 13174 // CHECK18: cond.false: 13175 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 13176 // CHECK18-NEXT: br label [[COND_END]] 13177 // CHECK18: cond.end: 13178 // CHECK18-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 13179 // CHECK18-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 13180 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 13181 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 13182 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 13183 // CHECK18: omp.inner.for.cond: 13184 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13185 // CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 13186 // CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 13187 // CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 13188 // CHECK18: omp.inner.for.body: 13189 // CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13190 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 13191 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 13192 // CHECK18-NEXT: store i64 [[ADD]], i64* [[I]], align 8 13193 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 13194 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 13195 // CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 13196 // CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 13197 // CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 13198 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 13199 // CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 13200 // CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 13201 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 13202 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 13203 // CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 13204 // CHECK18-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 13205 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 13206 // CHECK18: omp.body.continue: 13207 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 13208 // CHECK18: omp.inner.for.inc: 13209 // CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13210 // CHECK18-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 13211 // CHECK18-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 13212 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] 13213 // CHECK18: omp.inner.for.end: 13214 // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 13215 // CHECK18: omp.loop.exit: 13216 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 13217 // CHECK18-NEXT: ret void 13218 // 13219 // 13220 // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 13221 // CHECK18-SAME: () #[[ATTR6]] { 13222 // CHECK18-NEXT: entry: 13223 // CHECK18-NEXT: call void @__tgt_register_requires(i64 1) 13224 // CHECK18-NEXT: ret void 13225 // 13226 // 13227 // CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv 13228 // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { 13229 // CHECK19-NEXT: entry: 13230 // CHECK19-NEXT: ret i64 0 13231 // 13232 // 13233 // CHECK19-LABEL: define {{[^@]+}}@_Z3fooi 13234 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 13235 // CHECK19-NEXT: entry: 13236 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 13237 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 13238 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 13239 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 4 13240 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 13241 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 13242 // CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 13243 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 13244 // CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 13245 // CHECK19-NEXT: [[K:%.*]] = alloca i64, align 8 13246 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13247 // CHECK19-NEXT: [[LIN:%.*]] = alloca i32, align 4 13248 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 13249 // CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 13250 // CHECK19-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 13251 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 13252 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 13253 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 13254 // CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 13255 // CHECK19-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 13256 // CHECK19-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 13257 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 13258 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 13259 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 13260 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 13261 // CHECK19-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 13262 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 13263 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4 13264 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4 13265 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4 13266 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 13267 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 13268 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 13269 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 13270 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 13271 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 13272 // CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 13273 // CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 13274 // CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 13275 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 13276 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 13277 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 13278 // CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 13279 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 13280 // CHECK19-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 13281 // CHECK19-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 13282 // CHECK19-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 13283 // CHECK19: omp_offload.failed: 13284 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 13285 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 13286 // CHECK19: omp_offload.cont: 13287 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 13288 // CHECK19-NEXT: store i64 [[CALL]], i64* [[K]], align 8 13289 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 13290 // CHECK19-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 13291 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4 13292 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR4]] 13293 // CHECK19-NEXT: store i32 12, i32* [[LIN]], align 4 13294 // CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 13295 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 13296 // CHECK19-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 13297 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4 13298 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4 13299 // CHECK19-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4 13300 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 13301 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 13302 // CHECK19-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4 13303 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4 13304 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 13305 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 13306 // CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4 13307 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 13308 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 13309 // CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4 13310 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 13311 // CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 13312 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 13313 // CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 13314 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4 13315 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 13316 // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 13317 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4 13318 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 13319 // CHECK19-NEXT: store i8* null, i8** [[TMP24]], align 4 13320 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 13321 // CHECK19-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 13322 // CHECK19-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4 13323 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 13324 // CHECK19-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 13325 // CHECK19-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4 13326 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 13327 // CHECK19-NEXT: store i8* null, i8** [[TMP29]], align 4 13328 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 13329 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 13330 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 13331 // CHECK19-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 13332 // CHECK19-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 13333 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 13334 // CHECK19-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4 13335 // CHECK19-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 13336 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 13337 // CHECK19-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4 13338 // CHECK19-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 13339 // CHECK19-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 13340 // CHECK19-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 13341 // CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 13342 // CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 13343 // CHECK19-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4 13344 // CHECK19-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 13345 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false) 13346 // CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 13347 // CHECK19-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 13348 // CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 13349 // CHECK19-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8* 13350 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 13351 // CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 13352 // CHECK19-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8* 13353 // CHECK19-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8* 13354 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false) 13355 // CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 13356 // CHECK19-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8* 13357 // CHECK19-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8* 13358 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false) 13359 // CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 13360 // CHECK19-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 13361 // CHECK19-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4 13362 // CHECK19-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) 13363 // CHECK19-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 13364 // CHECK19-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4 13365 // CHECK19-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4 13366 // CHECK19-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 13367 // CHECK19-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 13368 // CHECK19-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2 13369 // CHECK19-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 13370 // CHECK19-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4 13371 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10 13372 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 13373 // CHECK19: omp_if.then: 13374 // CHECK19-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 13375 // CHECK19-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* 13376 // CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4 13377 // CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 13378 // CHECK19-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32* 13379 // CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4 13380 // CHECK19-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 13381 // CHECK19-NEXT: store i8* null, i8** [[TMP66]], align 4 13382 // CHECK19-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 13383 // CHECK19-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32* 13384 // CHECK19-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4 13385 // CHECK19-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 13386 // CHECK19-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32* 13387 // CHECK19-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4 13388 // CHECK19-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 13389 // CHECK19-NEXT: store i8* null, i8** [[TMP71]], align 4 13390 // CHECK19-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 13391 // CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 13392 // CHECK19-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 13393 // CHECK19-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0 13394 // CHECK19-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 13395 // CHECK19: omp_offload.failed9: 13396 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 13397 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT10]] 13398 // CHECK19: omp_offload.cont10: 13399 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 13400 // CHECK19: omp_if.else: 13401 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 13402 // CHECK19-NEXT: br label [[OMP_IF_END]] 13403 // CHECK19: omp_if.end: 13404 // CHECK19-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4 13405 // CHECK19-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4 13406 // CHECK19-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4 13407 // CHECK19-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4 13408 // CHECK19-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4 13409 // CHECK19-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 13410 // CHECK19-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 13411 // CHECK19-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 13412 // CHECK19-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4 13413 // CHECK19-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20 13414 // CHECK19-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]] 13415 // CHECK19: omp_if.then13: 13416 // CHECK19-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4 13417 // CHECK19-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64 13418 // CHECK19-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]] 13419 // CHECK19-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8 13420 // CHECK19-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64 13421 // CHECK19-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 13422 // CHECK19-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* 13423 // CHECK19-NEXT: store i32 [[TMP78]], i32* [[TMP88]], align 4 13424 // CHECK19-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 13425 // CHECK19-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* 13426 // CHECK19-NEXT: store i32 [[TMP78]], i32* [[TMP90]], align 4 13427 // CHECK19-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 13428 // CHECK19-NEXT: store i64 4, i64* [[TMP91]], align 4 13429 // CHECK19-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 13430 // CHECK19-NEXT: store i8* null, i8** [[TMP92]], align 4 13431 // CHECK19-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 13432 // CHECK19-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]** 13433 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4 13434 // CHECK19-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 13435 // CHECK19-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 13436 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4 13437 // CHECK19-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 13438 // CHECK19-NEXT: store i64 40, i64* [[TMP97]], align 4 13439 // CHECK19-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 13440 // CHECK19-NEXT: store i8* null, i8** [[TMP98]], align 4 13441 // CHECK19-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 13442 // CHECK19-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i32* 13443 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP100]], align 4 13444 // CHECK19-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 13445 // CHECK19-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i32* 13446 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP102]], align 4 13447 // CHECK19-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 13448 // CHECK19-NEXT: store i64 4, i64* [[TMP103]], align 4 13449 // CHECK19-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 13450 // CHECK19-NEXT: store i8* null, i8** [[TMP104]], align 4 13451 // CHECK19-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 13452 // CHECK19-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** 13453 // CHECK19-NEXT: store float* [[VLA]], float** [[TMP106]], align 4 13454 // CHECK19-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 13455 // CHECK19-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** 13456 // CHECK19-NEXT: store float* [[VLA]], float** [[TMP108]], align 4 13457 // CHECK19-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 13458 // CHECK19-NEXT: store i64 [[TMP83]], i64* [[TMP109]], align 4 13459 // CHECK19-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 13460 // CHECK19-NEXT: store i8* null, i8** [[TMP110]], align 4 13461 // CHECK19-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 13462 // CHECK19-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** 13463 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4 13464 // CHECK19-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 13465 // CHECK19-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** 13466 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 4 13467 // CHECK19-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 13468 // CHECK19-NEXT: store i64 400, i64* [[TMP115]], align 4 13469 // CHECK19-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 13470 // CHECK19-NEXT: store i8* null, i8** [[TMP116]], align 4 13471 // CHECK19-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 13472 // CHECK19-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to i32* 13473 // CHECK19-NEXT: store i32 5, i32* [[TMP118]], align 4 13474 // CHECK19-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 13475 // CHECK19-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32* 13476 // CHECK19-NEXT: store i32 5, i32* [[TMP120]], align 4 13477 // CHECK19-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 13478 // CHECK19-NEXT: store i64 4, i64* [[TMP121]], align 4 13479 // CHECK19-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 13480 // CHECK19-NEXT: store i8* null, i8** [[TMP122]], align 4 13481 // CHECK19-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 13482 // CHECK19-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32* 13483 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP124]], align 4 13484 // CHECK19-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 13485 // CHECK19-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* 13486 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP126]], align 4 13487 // CHECK19-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 13488 // CHECK19-NEXT: store i64 4, i64* [[TMP127]], align 4 13489 // CHECK19-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 13490 // CHECK19-NEXT: store i8* null, i8** [[TMP128]], align 4 13491 // CHECK19-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 13492 // CHECK19-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to double** 13493 // CHECK19-NEXT: store double* [[VLA1]], double** [[TMP130]], align 4 13494 // CHECK19-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 13495 // CHECK19-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double** 13496 // CHECK19-NEXT: store double* [[VLA1]], double** [[TMP132]], align 4 13497 // CHECK19-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 13498 // CHECK19-NEXT: store i64 [[TMP86]], i64* [[TMP133]], align 4 13499 // CHECK19-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 13500 // CHECK19-NEXT: store i8* null, i8** [[TMP134]], align 4 13501 // CHECK19-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 13502 // CHECK19-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to %struct.TT** 13503 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP136]], align 4 13504 // CHECK19-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 13505 // CHECK19-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT** 13506 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 4 13507 // CHECK19-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 13508 // CHECK19-NEXT: store i64 12, i64* [[TMP139]], align 4 13509 // CHECK19-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 13510 // CHECK19-NEXT: store i8* null, i8** [[TMP140]], align 4 13511 // CHECK19-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 13512 // CHECK19-NEXT: [[TMP142:%.*]] = bitcast i8** [[TMP141]] to i32* 13513 // CHECK19-NEXT: store i32 [[TMP80]], i32* [[TMP142]], align 4 13514 // CHECK19-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 13515 // CHECK19-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i32* 13516 // CHECK19-NEXT: store i32 [[TMP80]], i32* [[TMP144]], align 4 13517 // CHECK19-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 13518 // CHECK19-NEXT: store i64 4, i64* [[TMP145]], align 4 13519 // CHECK19-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 13520 // CHECK19-NEXT: store i8* null, i8** [[TMP146]], align 4 13521 // CHECK19-NEXT: [[TMP147:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 13522 // CHECK19-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 13523 // CHECK19-NEXT: [[TMP149:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 13524 // CHECK19-NEXT: [[TMP150:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP147]], i8** [[TMP148]], i64* [[TMP149]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 13525 // CHECK19-NEXT: [[TMP151:%.*]] = icmp ne i32 [[TMP150]], 0 13526 // CHECK19-NEXT: br i1 [[TMP151]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] 13527 // CHECK19: omp_offload.failed17: 13528 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 13529 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT18]] 13530 // CHECK19: omp_offload.cont18: 13531 // CHECK19-NEXT: br label [[OMP_IF_END20:%.*]] 13532 // CHECK19: omp_if.else19: 13533 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 13534 // CHECK19-NEXT: br label [[OMP_IF_END20]] 13535 // CHECK19: omp_if.end20: 13536 // CHECK19-NEXT: [[TMP152:%.*]] = load i32, i32* [[A]], align 4 13537 // CHECK19-NEXT: [[TMP153:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 13538 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP153]]) 13539 // CHECK19-NEXT: ret i32 [[TMP152]] 13540 // 13541 // 13542 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 13543 // CHECK19-SAME: () #[[ATTR2:[0-9]+]] { 13544 // CHECK19-NEXT: entry: 13545 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 13546 // CHECK19-NEXT: ret void 13547 // 13548 // 13549 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 13550 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 13551 // CHECK19-NEXT: entry: 13552 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13553 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13554 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 13555 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 13556 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 13557 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 13558 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 13559 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 13560 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 13561 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13562 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13563 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 13564 // CHECK19-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 13565 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 13566 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 13567 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 13568 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 13569 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 13570 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 13571 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 13572 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 13573 // CHECK19: cond.true: 13574 // CHECK19-NEXT: br label [[COND_END:%.*]] 13575 // CHECK19: cond.false: 13576 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 13577 // CHECK19-NEXT: br label [[COND_END]] 13578 // CHECK19: cond.end: 13579 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 13580 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 13581 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 13582 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 13583 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 13584 // CHECK19: omp.inner.for.cond: 13585 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 13586 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 13587 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 13588 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 13589 // CHECK19: omp.inner.for.body: 13590 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 13591 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 13592 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 13593 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 13594 // CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 13595 // CHECK19-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 13596 // CHECK19-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 13597 // CHECK19: .cancel.exit: 13598 // CHECK19-NEXT: br label [[CANCEL_EXIT:%.*]] 13599 // CHECK19: .cancel.continue: 13600 // CHECK19-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 13601 // CHECK19-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 13602 // CHECK19-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 13603 // CHECK19: .cancel.exit2: 13604 // CHECK19-NEXT: br label [[CANCEL_EXIT]] 13605 // CHECK19: .cancel.continue3: 13606 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 13607 // CHECK19: omp.body.continue: 13608 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 13609 // CHECK19: omp.inner.for.inc: 13610 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 13611 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 13612 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 13613 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 13614 // CHECK19: omp.inner.for.end: 13615 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 13616 // CHECK19: omp.loop.exit: 13617 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 13618 // CHECK19-NEXT: br label [[CANCEL_CONT:%.*]] 13619 // CHECK19: cancel.cont: 13620 // CHECK19-NEXT: ret void 13621 // CHECK19: cancel.exit: 13622 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 13623 // CHECK19-NEXT: br label [[CANCEL_CONT]] 13624 // 13625 // 13626 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 13627 // CHECK19-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 13628 // CHECK19-NEXT: entry: 13629 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13630 // CHECK19-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 13631 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13632 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13633 // CHECK19-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 13634 // CHECK19-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 13635 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 13636 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 13637 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 13638 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) 13639 // CHECK19-NEXT: ret void 13640 // 13641 // 13642 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 13643 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 13644 // CHECK19-NEXT: entry: 13645 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13646 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13647 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13648 // CHECK19-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 13649 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 13650 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 13651 // CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 13652 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 13653 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 13654 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 13655 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 13656 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 13657 // CHECK19-NEXT: [[K1:%.*]] = alloca i64, align 8 13658 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13659 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13660 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13661 // CHECK19-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 13662 // CHECK19-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 13663 // CHECK19-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 13664 // CHECK19-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 13665 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 13666 // CHECK19-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 13667 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 13668 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 13669 // CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 13670 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 13671 // CHECK19-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 13672 // CHECK19-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 13673 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 13674 // CHECK19: omp.dispatch.cond: 13675 // CHECK19-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 13676 // CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 13677 // CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 13678 // CHECK19: omp.dispatch.body: 13679 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 13680 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 13681 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 13682 // CHECK19: omp.inner.for.cond: 13683 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 13684 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 13685 // CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 13686 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 13687 // CHECK19: omp.inner.for.body: 13688 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 13689 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 13690 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 13691 // CHECK19-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13 13692 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !13 13693 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 13694 // CHECK19-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 13695 // CHECK19-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 13696 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 13697 // CHECK19-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13 13698 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !13 13699 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 13700 // CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13 13701 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 13702 // CHECK19: omp.body.continue: 13703 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 13704 // CHECK19: omp.inner.for.inc: 13705 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 13706 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 13707 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 13708 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 13709 // CHECK19: omp.inner.for.end: 13710 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 13711 // CHECK19: omp.dispatch.inc: 13712 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 13713 // CHECK19: omp.dispatch.end: 13714 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 13715 // CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 13716 // CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 13717 // CHECK19: .omp.linear.pu: 13718 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[K1]], align 8 13719 // CHECK19-NEXT: store i64 [[TMP15]], i64* [[TMP0]], align 8 13720 // CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 13721 // CHECK19: .omp.linear.pu.done: 13722 // CHECK19-NEXT: ret void 13723 // 13724 // 13725 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 13726 // CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 13727 // CHECK19-NEXT: entry: 13728 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13729 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 13730 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13731 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 13732 // CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 13733 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13734 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13735 // CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 13736 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13737 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13738 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 13739 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 13740 // CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 13741 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 13742 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 13743 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 13744 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 13745 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 13746 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 13747 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 13748 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 13749 // CHECK19-NEXT: ret void 13750 // 13751 // 13752 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 13753 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 13754 // CHECK19-NEXT: entry: 13755 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13756 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13757 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13758 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 13759 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13760 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 13761 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 13762 // CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 13763 // CHECK19-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 13764 // CHECK19-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 13765 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 13766 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 13767 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 13768 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 13769 // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 13770 // CHECK19-NEXT: [[LIN2:%.*]] = alloca i32, align 4 13771 // CHECK19-NEXT: [[A3:%.*]] = alloca i32, align 4 13772 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13773 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13774 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13775 // CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 13776 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13777 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13778 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 13779 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 13780 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 13781 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 13782 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 13783 // CHECK19-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 13784 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 13785 // CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 13786 // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 13787 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 13788 // CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 13789 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 13790 // CHECK19-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 13791 // CHECK19-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 13792 // CHECK19-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 13793 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 13794 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 13795 // CHECK19: cond.true: 13796 // CHECK19-NEXT: br label [[COND_END:%.*]] 13797 // CHECK19: cond.false: 13798 // CHECK19-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 13799 // CHECK19-NEXT: br label [[COND_END]] 13800 // CHECK19: cond.end: 13801 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 13802 // CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 13803 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 13804 // CHECK19-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 13805 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 13806 // CHECK19: omp.inner.for.cond: 13807 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13808 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 13809 // CHECK19-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 13810 // CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 13811 // CHECK19: omp.inner.for.body: 13812 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13813 // CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 13814 // CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 13815 // CHECK19-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 13816 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 13817 // CHECK19-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 13818 // CHECK19-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13819 // CHECK19-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 13820 // CHECK19-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 13821 // CHECK19-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 13822 // CHECK19-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 13823 // CHECK19-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 13824 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 13825 // CHECK19-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 13826 // CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13827 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 13828 // CHECK19-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 13829 // CHECK19-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 13830 // CHECK19-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 13831 // CHECK19-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 13832 // CHECK19-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 13833 // CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 13834 // CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 13835 // CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 13836 // CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 13837 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 13838 // CHECK19: omp.body.continue: 13839 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 13840 // CHECK19: omp.inner.for.inc: 13841 // CHECK19-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 13842 // CHECK19-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 13843 // CHECK19-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 13844 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 13845 // CHECK19: omp.inner.for.end: 13846 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 13847 // CHECK19: omp.loop.exit: 13848 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 13849 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 13850 // CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 13851 // CHECK19-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 13852 // CHECK19: .omp.linear.pu: 13853 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 13854 // CHECK19-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 13855 // CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 13856 // CHECK19-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 13857 // CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 13858 // CHECK19: .omp.linear.pu.done: 13859 // CHECK19-NEXT: ret void 13860 // 13861 // 13862 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map. 13863 // CHECK19-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 13864 // CHECK19-NEXT: entry: 13865 // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 13866 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 13867 // CHECK19-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 13868 // CHECK19-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 13869 // CHECK19-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 13870 // CHECK19-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 13871 // CHECK19-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 13872 // CHECK19-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 13873 // CHECK19-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 13874 // CHECK19-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 13875 // CHECK19-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 13876 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 13877 // CHECK19-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 13878 // CHECK19-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 13879 // CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 13880 // CHECK19-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 13881 // CHECK19-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 13882 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 13883 // CHECK19-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 13884 // CHECK19-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 13885 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 13886 // CHECK19-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 13887 // CHECK19-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 13888 // CHECK19-NEXT: ret void 13889 // 13890 // 13891 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. 13892 // CHECK19-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 13893 // CHECK19-NEXT: entry: 13894 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 13895 // CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 13896 // CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 13897 // CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 13898 // CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 13899 // CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 13900 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 13901 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 13902 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 13903 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 13904 // CHECK19-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 13905 // CHECK19-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4 13906 // CHECK19-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4 13907 // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 13908 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 13909 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 13910 // CHECK19-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 13911 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 13912 // CHECK19-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 13913 // CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 13914 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 13915 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 13916 // CHECK19-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 13917 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 13918 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 13919 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 13920 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 13921 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 13922 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 13923 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 13924 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 13925 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 13926 // CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 13927 // CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 13928 // CHECK19-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 13929 // CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 13930 // CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 13931 // CHECK19-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 13932 // CHECK19-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 13933 // CHECK19-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 13934 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 13935 // CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 13936 // CHECK19-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 13937 // CHECK19-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 13938 // CHECK19-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 13939 // CHECK19-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 13940 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 13941 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 13942 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 13943 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 13944 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 13945 // CHECK19-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 13946 // CHECK19-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 13947 // CHECK19-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 13948 // CHECK19: omp_offload.failed.i: 13949 // CHECK19-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 13950 // CHECK19-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 13951 // CHECK19-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25 13952 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 13953 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 13954 // CHECK19-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25 13955 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !25 13956 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 13957 // CHECK19-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25 13958 // CHECK19-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !25 13959 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR4]] 13960 // CHECK19-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 13961 // CHECK19: .omp_outlined..3.exit: 13962 // CHECK19-NEXT: ret i32 0 13963 // 13964 // 13965 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 13966 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 13967 // CHECK19-NEXT: entry: 13968 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13969 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13970 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13971 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 13972 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13973 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13974 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13975 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 13976 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 13977 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 13978 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 13979 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 13980 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 13981 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 13982 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 13983 // CHECK19-NEXT: ret void 13984 // 13985 // 13986 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 13987 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 13988 // CHECK19-NEXT: entry: 13989 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13990 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13991 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13992 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13993 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 13994 // CHECK19-NEXT: [[TMP:%.*]] = alloca i16, align 2 13995 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 13996 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 13997 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 13998 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 13999 // CHECK19-NEXT: [[IT:%.*]] = alloca i16, align 2 14000 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14001 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14002 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14003 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14004 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14005 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 14006 // CHECK19-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 14007 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 14008 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 14009 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 14010 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 14011 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 14012 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 14013 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 14014 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 14015 // CHECK19: cond.true: 14016 // CHECK19-NEXT: br label [[COND_END:%.*]] 14017 // CHECK19: cond.false: 14018 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 14019 // CHECK19-NEXT: br label [[COND_END]] 14020 // CHECK19: cond.end: 14021 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 14022 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 14023 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 14024 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 14025 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 14026 // CHECK19: omp.inner.for.cond: 14027 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 14028 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 14029 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 14030 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 14031 // CHECK19: omp.inner.for.body: 14032 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 14033 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 14034 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 14035 // CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 14036 // CHECK19-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 14037 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 14038 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 14039 // CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 14040 // CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 14041 // CHECK19-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 14042 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 14043 // CHECK19-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 14044 // CHECK19-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 14045 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 14046 // CHECK19: omp.body.continue: 14047 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 14048 // CHECK19: omp.inner.for.inc: 14049 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 14050 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 14051 // CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 14052 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 14053 // CHECK19: omp.inner.for.end: 14054 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 14055 // CHECK19: omp.loop.exit: 14056 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 14057 // CHECK19-NEXT: ret void 14058 // 14059 // 14060 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 14061 // CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 14062 // CHECK19-NEXT: entry: 14063 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14064 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 14065 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 14066 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 14067 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 14068 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 14069 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 14070 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 14071 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 14072 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 14073 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14074 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 14075 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14076 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 14077 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 14078 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 14079 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 14080 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 14081 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 14082 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 14083 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 14084 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 14085 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 14086 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14087 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 14088 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 14089 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 14090 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 14091 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 14092 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 14093 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 14094 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 14095 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 14096 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 14097 // CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 14098 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 14099 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 14100 // CHECK19-NEXT: ret void 14101 // 14102 // 14103 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 14104 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 14105 // CHECK19-NEXT: entry: 14106 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14107 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14108 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14109 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 14110 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 14111 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 14112 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 14113 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 14114 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 14115 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 14116 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 14117 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 14118 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 14119 // CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1 14120 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 14121 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 14122 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 14123 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 14124 // CHECK19-NEXT: [[IT:%.*]] = alloca i8, align 1 14125 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14126 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14127 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14128 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 14129 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 14130 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 14131 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 14132 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 14133 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 14134 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 14135 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 14136 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 14137 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 14138 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14139 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 14140 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 14141 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 14142 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 14143 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 14144 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 14145 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 14146 // CHECK19-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 14147 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 14148 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 14149 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 14150 // CHECK19-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 14151 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 14152 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 14153 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 14154 // CHECK19: omp.dispatch.cond: 14155 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 14156 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 14157 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 14158 // CHECK19: cond.true: 14159 // CHECK19-NEXT: br label [[COND_END:%.*]] 14160 // CHECK19: cond.false: 14161 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 14162 // CHECK19-NEXT: br label [[COND_END]] 14163 // CHECK19: cond.end: 14164 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 14165 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 14166 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 14167 // CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 14168 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 14169 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 14170 // CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 14171 // CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 14172 // CHECK19: omp.dispatch.body: 14173 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 14174 // CHECK19: omp.inner.for.cond: 14175 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 14176 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 14177 // CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 14178 // CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 14179 // CHECK19: omp.inner.for.body: 14180 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 14181 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 14182 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 14183 // CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 14184 // CHECK19-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 14185 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 14186 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 14187 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 14188 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 14189 // CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 14190 // CHECK19-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 14191 // CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 14192 // CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 14193 // CHECK19-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 14194 // CHECK19-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 14195 // CHECK19-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 14196 // CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 14197 // CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 14198 // CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 14199 // CHECK19-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 14200 // CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 14201 // CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 14202 // CHECK19-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 14203 // CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 14204 // CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 14205 // CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 14206 // CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 14207 // CHECK19-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 14208 // CHECK19-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 14209 // CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 14210 // CHECK19-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 14211 // CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 14212 // CHECK19-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 14213 // CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 14214 // CHECK19-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 14215 // CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 14216 // CHECK19-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 14217 // CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 14218 // CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 14219 // CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 14220 // CHECK19-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 14221 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 14222 // CHECK19: omp.body.continue: 14223 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 14224 // CHECK19: omp.inner.for.inc: 14225 // CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 14226 // CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 14227 // CHECK19-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 14228 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 14229 // CHECK19: omp.inner.for.end: 14230 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 14231 // CHECK19: omp.dispatch.inc: 14232 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 14233 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 14234 // CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 14235 // CHECK19-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 14236 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 14237 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 14238 // CHECK19-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 14239 // CHECK19-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 14240 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 14241 // CHECK19: omp.dispatch.end: 14242 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 14243 // CHECK19-NEXT: ret void 14244 // 14245 // 14246 // CHECK19-LABEL: define {{[^@]+}}@_Z3bari 14247 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 14248 // CHECK19-NEXT: entry: 14249 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 14250 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 14251 // CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 14252 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 14253 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 14254 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 14255 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 14256 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 14257 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 14258 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 14259 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 14260 // CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 14261 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 14262 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 14263 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 14264 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 14265 // CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 14266 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 14267 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 14268 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 14269 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 14270 // CHECK19-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 14271 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 14272 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 14273 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 14274 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 14275 // CHECK19-NEXT: ret i32 [[TMP8]] 14276 // 14277 // 14278 // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 14279 // CHECK19-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 14280 // CHECK19-NEXT: entry: 14281 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 14282 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 14283 // CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 14284 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 14285 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 14286 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 14287 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 14288 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 14289 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 14290 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 14291 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 14292 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 14293 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 14294 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 14295 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 14296 // CHECK19-NEXT: store i32 [[ADD]], i32* [[B]], align 4 14297 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 14298 // CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 14299 // CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 14300 // CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 14301 // CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 14302 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 14303 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 14304 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 14305 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 14306 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 14307 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 14308 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 14309 // CHECK19: omp_if.then: 14310 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 14311 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 14312 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 14313 // CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 14314 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14315 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 14316 // CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 14317 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14318 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 14319 // CHECK19-NEXT: store double* [[A]], double** [[TMP13]], align 4 14320 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 14321 // CHECK19-NEXT: store i64 8, i64* [[TMP14]], align 4 14322 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 14323 // CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 14324 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 14325 // CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 14326 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 14327 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 14328 // CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 14329 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 14330 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 14331 // CHECK19-NEXT: store i64 4, i64* [[TMP20]], align 4 14332 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 14333 // CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 14334 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 14335 // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 14336 // CHECK19-NEXT: store i32 2, i32* [[TMP23]], align 4 14337 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 14338 // CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 14339 // CHECK19-NEXT: store i32 2, i32* [[TMP25]], align 4 14340 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 14341 // CHECK19-NEXT: store i64 4, i64* [[TMP26]], align 4 14342 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 14343 // CHECK19-NEXT: store i8* null, i8** [[TMP27]], align 4 14344 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 14345 // CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 14346 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 14347 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 14348 // CHECK19-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* 14349 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 14350 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 14351 // CHECK19-NEXT: store i64 4, i64* [[TMP32]], align 4 14352 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 14353 // CHECK19-NEXT: store i8* null, i8** [[TMP33]], align 4 14354 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 14355 // CHECK19-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 14356 // CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 14357 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 14358 // CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 14359 // CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 14360 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 14361 // CHECK19-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 14362 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 14363 // CHECK19-NEXT: store i8* null, i8** [[TMP39]], align 4 14364 // CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14365 // CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14366 // CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 14367 // CHECK19-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 14368 // CHECK19-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 14369 // CHECK19-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 14370 // CHECK19: omp_offload.failed: 14371 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 14372 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 14373 // CHECK19: omp_offload.cont: 14374 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 14375 // CHECK19: omp_if.else: 14376 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 14377 // CHECK19-NEXT: br label [[OMP_IF_END]] 14378 // CHECK19: omp_if.end: 14379 // CHECK19-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] 14380 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] 14381 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 14382 // CHECK19-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 14383 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 14384 // CHECK19-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 14385 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] 14386 // CHECK19-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 14387 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 14388 // CHECK19-NEXT: ret i32 [[ADD3]] 14389 // 14390 // 14391 // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici 14392 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 14393 // CHECK19-NEXT: entry: 14394 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 14395 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 14396 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 14397 // CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1 14398 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 14399 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14400 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14401 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 14402 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 14403 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 14404 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 14405 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 14406 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 14407 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 14408 // CHECK19-NEXT: store i8 0, i8* [[AAA]], align 1 14409 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 14410 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 14411 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 14412 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 14413 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14414 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 14415 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14416 // CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 14417 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 14418 // CHECK19-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 14419 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 14420 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 14421 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 14422 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 14423 // CHECK19: omp_if.then: 14424 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14425 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 14426 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 14427 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14428 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 14429 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 14430 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 14431 // CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4 14432 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 14433 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 14434 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 14435 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 14436 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 14437 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 14438 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 14439 // CHECK19-NEXT: store i8* null, i8** [[TMP16]], align 4 14440 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 14441 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 14442 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 14443 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 14444 // CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 14445 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 14446 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 14447 // CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 14448 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 14449 // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 14450 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 14451 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 14452 // CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 14453 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 14454 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 14455 // CHECK19-NEXT: store i8* null, i8** [[TMP26]], align 4 14456 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14457 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14458 // CHECK19-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 14459 // CHECK19-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 14460 // CHECK19-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 14461 // CHECK19: omp_offload.failed: 14462 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 14463 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 14464 // CHECK19: omp_offload.cont: 14465 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 14466 // CHECK19: omp_if.else: 14467 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 14468 // CHECK19-NEXT: br label [[OMP_IF_END]] 14469 // CHECK19: omp_if.end: 14470 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 14471 // CHECK19-NEXT: ret i32 [[TMP31]] 14472 // 14473 // 14474 // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 14475 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 14476 // CHECK19-NEXT: entry: 14477 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 14478 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 14479 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 14480 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 14481 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14482 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14483 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 14484 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 14485 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 14486 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 14487 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 14488 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 14489 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 14490 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 14491 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 14492 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 14493 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14494 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 14495 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14496 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 14497 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 14498 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 14499 // CHECK19: omp_if.then: 14500 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14501 // CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 14502 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 14503 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14504 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 14505 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 14506 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 14507 // CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4 14508 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 14509 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 14510 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 14511 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 14512 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 14513 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 14514 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 14515 // CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4 14516 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 14517 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 14518 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 14519 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 14520 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 14521 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 14522 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 14523 // CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 14524 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14525 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14526 // CHECK19-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 14527 // CHECK19-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 14528 // CHECK19-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 14529 // CHECK19: omp_offload.failed: 14530 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 14531 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 14532 // CHECK19: omp_offload.cont: 14533 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 14534 // CHECK19: omp_if.else: 14535 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 14536 // CHECK19-NEXT: br label [[OMP_IF_END]] 14537 // CHECK19: omp_if.end: 14538 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 14539 // CHECK19-NEXT: ret i32 [[TMP24]] 14540 // 14541 // 14542 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 14543 // CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 14544 // CHECK19-NEXT: entry: 14545 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 14546 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 14547 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 14548 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 14549 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 14550 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 14551 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 14552 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 14553 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 14554 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 14555 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 14556 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 14557 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14558 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 14559 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 14560 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 14561 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 14562 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 14563 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 14564 // CHECK19-NEXT: ret void 14565 // 14566 // 14567 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 14568 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 14569 // CHECK19-NEXT: entry: 14570 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14571 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14572 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 14573 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 14574 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 14575 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 14576 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 14577 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 14578 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 14579 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 14580 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 14581 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 14582 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 14583 // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 14584 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14585 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14586 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 14587 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 14588 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 14589 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 14590 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 14591 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 14592 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14593 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 14594 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 14595 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 14596 // CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 14597 // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 14598 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 14599 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 14600 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 14601 // CHECK19-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 14602 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 14603 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 14604 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 14605 // CHECK19: cond.true: 14606 // CHECK19-NEXT: br label [[COND_END:%.*]] 14607 // CHECK19: cond.false: 14608 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 14609 // CHECK19-NEXT: br label [[COND_END]] 14610 // CHECK19: cond.end: 14611 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 14612 // CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 14613 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 14614 // CHECK19-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 14615 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 14616 // CHECK19: omp.inner.for.cond: 14617 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 14618 // CHECK19-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 14619 // CHECK19-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 14620 // CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 14621 // CHECK19: omp.inner.for.body: 14622 // CHECK19-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 14623 // CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 14624 // CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 14625 // CHECK19-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 14626 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 14627 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 14628 // CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 14629 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 14630 // CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 14631 // CHECK19-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 14632 // CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 14633 // CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 14634 // CHECK19-NEXT: store double [[INC]], double* [[A4]], align 4 14635 // CHECK19-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 14636 // CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 14637 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 14638 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 14639 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 14640 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 14641 // CHECK19: omp.body.continue: 14642 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 14643 // CHECK19: omp.inner.for.inc: 14644 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 14645 // CHECK19-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 14646 // CHECK19-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 14647 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 14648 // CHECK19: omp.inner.for.end: 14649 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 14650 // CHECK19: omp.loop.exit: 14651 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 14652 // CHECK19-NEXT: ret void 14653 // 14654 // 14655 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 14656 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 14657 // CHECK19-NEXT: entry: 14658 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14659 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14660 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 14661 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 14662 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14663 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14664 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 14665 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14666 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14667 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 14668 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 14669 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14670 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 14671 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 14672 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 14673 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 14674 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 14675 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 14676 // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14677 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 14678 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14679 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 14680 // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 14681 // CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 14682 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 14683 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 14684 // CHECK19-NEXT: ret void 14685 // 14686 // 14687 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 14688 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 14689 // CHECK19-NEXT: entry: 14690 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14691 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14692 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14693 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14694 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 14695 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 14696 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 14697 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 14698 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14699 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14700 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14701 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14702 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 14703 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 14704 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14705 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 14706 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 14707 // CHECK19-NEXT: ret void 14708 // 14709 // 14710 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 14711 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 14712 // CHECK19-NEXT: entry: 14713 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14714 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14715 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 14716 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14717 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14718 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14719 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14720 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 14721 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14722 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 14723 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 14724 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 14725 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 14726 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 14727 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14728 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 14729 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14730 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 14731 // CHECK19-NEXT: ret void 14732 // 14733 // 14734 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..14 14735 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 14736 // CHECK19-NEXT: entry: 14737 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14738 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14739 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14740 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14741 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 14742 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 14743 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 14744 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 14745 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 14746 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 14747 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 14748 // CHECK19-NEXT: [[I:%.*]] = alloca i64, align 8 14749 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14750 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14751 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14752 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14753 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 14754 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14755 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 14756 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 14757 // CHECK19-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 14758 // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 14759 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 14760 // CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 14761 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 14762 // CHECK19-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 14763 // CHECK19-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 14764 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 14765 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 14766 // CHECK19: cond.true: 14767 // CHECK19-NEXT: br label [[COND_END:%.*]] 14768 // CHECK19: cond.false: 14769 // CHECK19-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 14770 // CHECK19-NEXT: br label [[COND_END]] 14771 // CHECK19: cond.end: 14772 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 14773 // CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 14774 // CHECK19-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 14775 // CHECK19-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 14776 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 14777 // CHECK19: omp.inner.for.cond: 14778 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 14779 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 14780 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 14781 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 14782 // CHECK19: omp.inner.for.body: 14783 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 14784 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 14785 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 14786 // CHECK19-NEXT: store i64 [[ADD]], i64* [[I]], align 8 14787 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 14788 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 14789 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 14790 // CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 14791 // CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 14792 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 14793 // CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 14794 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 14795 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 14796 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 14797 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 14798 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 14799 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 14800 // CHECK19: omp.body.continue: 14801 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 14802 // CHECK19: omp.inner.for.inc: 14803 // CHECK19-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 14804 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 14805 // CHECK19-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 14806 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 14807 // CHECK19: omp.inner.for.end: 14808 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 14809 // CHECK19: omp.loop.exit: 14810 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 14811 // CHECK19-NEXT: ret void 14812 // 14813 // 14814 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 14815 // CHECK19-SAME: () #[[ATTR6]] { 14816 // CHECK19-NEXT: entry: 14817 // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) 14818 // CHECK19-NEXT: ret void 14819 // 14820 // 14821 // CHECK20-LABEL: define {{[^@]+}}@_Z7get_valv 14822 // CHECK20-SAME: () #[[ATTR0:[0-9]+]] { 14823 // CHECK20-NEXT: entry: 14824 // CHECK20-NEXT: ret i64 0 14825 // 14826 // 14827 // CHECK20-LABEL: define {{[^@]+}}@_Z3fooi 14828 // CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 14829 // CHECK20-NEXT: entry: 14830 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 14831 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 14832 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 14833 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x float], align 4 14834 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 14835 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 14836 // CHECK20-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 14837 // CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 14838 // CHECK20-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 14839 // CHECK20-NEXT: [[K:%.*]] = alloca i64, align 8 14840 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14841 // CHECK20-NEXT: [[LIN:%.*]] = alloca i32, align 4 14842 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14843 // CHECK20-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 14844 // CHECK20-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 14845 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 14846 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 14847 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 14848 // CHECK20-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 14849 // CHECK20-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 14850 // CHECK20-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 14851 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 14852 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 14853 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 14854 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 14855 // CHECK20-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 14856 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 14857 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4 14858 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4 14859 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4 14860 // CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 14861 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 14862 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 14863 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 14864 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 14865 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 14866 // CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 14867 // CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 14868 // CHECK20-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 14869 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 14870 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 14871 // CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 14872 // CHECK20-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 14873 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 14874 // CHECK20-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 14875 // CHECK20-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 14876 // CHECK20-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 14877 // CHECK20: omp_offload.failed: 14878 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 14879 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 14880 // CHECK20: omp_offload.cont: 14881 // CHECK20-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 14882 // CHECK20-NEXT: store i64 [[CALL]], i64* [[K]], align 8 14883 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 14884 // CHECK20-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 14885 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4 14886 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR4]] 14887 // CHECK20-NEXT: store i32 12, i32* [[LIN]], align 4 14888 // CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 14889 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14890 // CHECK20-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 14891 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14892 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4 14893 // CHECK20-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4 14894 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 14895 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 14896 // CHECK20-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4 14897 // CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4 14898 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14899 // CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 14900 // CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4 14901 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14902 // CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 14903 // CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4 14904 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 14905 // CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 14906 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 14907 // CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 14908 // CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4 14909 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 14910 // CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 14911 // CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4 14912 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 14913 // CHECK20-NEXT: store i8* null, i8** [[TMP24]], align 4 14914 // CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 14915 // CHECK20-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 14916 // CHECK20-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4 14917 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 14918 // CHECK20-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 14919 // CHECK20-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4 14920 // CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 14921 // CHECK20-NEXT: store i8* null, i8** [[TMP29]], align 4 14922 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14923 // CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14924 // CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 14925 // CHECK20-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 14926 // CHECK20-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 14927 // CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 14928 // CHECK20-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4 14929 // CHECK20-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 14930 // CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 14931 // CHECK20-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4 14932 // CHECK20-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 14933 // CHECK20-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 14934 // CHECK20-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 14935 // CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 14936 // CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 14937 // CHECK20-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4 14938 // CHECK20-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 14939 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false) 14940 // CHECK20-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 14941 // CHECK20-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 14942 // CHECK20-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 14943 // CHECK20-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8* 14944 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 14945 // CHECK20-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 14946 // CHECK20-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8* 14947 // CHECK20-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8* 14948 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false) 14949 // CHECK20-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 14950 // CHECK20-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8* 14951 // CHECK20-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8* 14952 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false) 14953 // CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 14954 // CHECK20-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 14955 // CHECK20-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4 14956 // CHECK20-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) 14957 // CHECK20-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 14958 // CHECK20-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4 14959 // CHECK20-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4 14960 // CHECK20-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 14961 // CHECK20-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 14962 // CHECK20-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2 14963 // CHECK20-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 14964 // CHECK20-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4 14965 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10 14966 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 14967 // CHECK20: omp_if.then: 14968 // CHECK20-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 14969 // CHECK20-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* 14970 // CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4 14971 // CHECK20-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 14972 // CHECK20-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32* 14973 // CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4 14974 // CHECK20-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 14975 // CHECK20-NEXT: store i8* null, i8** [[TMP66]], align 4 14976 // CHECK20-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 14977 // CHECK20-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32* 14978 // CHECK20-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4 14979 // CHECK20-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 14980 // CHECK20-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32* 14981 // CHECK20-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4 14982 // CHECK20-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 14983 // CHECK20-NEXT: store i8* null, i8** [[TMP71]], align 4 14984 // CHECK20-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 14985 // CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 14986 // CHECK20-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 14987 // CHECK20-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0 14988 // CHECK20-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 14989 // CHECK20: omp_offload.failed9: 14990 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 14991 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT10]] 14992 // CHECK20: omp_offload.cont10: 14993 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 14994 // CHECK20: omp_if.else: 14995 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 14996 // CHECK20-NEXT: br label [[OMP_IF_END]] 14997 // CHECK20: omp_if.end: 14998 // CHECK20-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4 14999 // CHECK20-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4 15000 // CHECK20-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4 15001 // CHECK20-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4 15002 // CHECK20-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4 15003 // CHECK20-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 15004 // CHECK20-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 15005 // CHECK20-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 15006 // CHECK20-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4 15007 // CHECK20-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20 15008 // CHECK20-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]] 15009 // CHECK20: omp_if.then13: 15010 // CHECK20-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4 15011 // CHECK20-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64 15012 // CHECK20-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]] 15013 // CHECK20-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8 15014 // CHECK20-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64 15015 // CHECK20-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 15016 // CHECK20-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* 15017 // CHECK20-NEXT: store i32 [[TMP78]], i32* [[TMP88]], align 4 15018 // CHECK20-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 15019 // CHECK20-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* 15020 // CHECK20-NEXT: store i32 [[TMP78]], i32* [[TMP90]], align 4 15021 // CHECK20-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 15022 // CHECK20-NEXT: store i64 4, i64* [[TMP91]], align 4 15023 // CHECK20-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 15024 // CHECK20-NEXT: store i8* null, i8** [[TMP92]], align 4 15025 // CHECK20-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 15026 // CHECK20-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]** 15027 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4 15028 // CHECK20-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 15029 // CHECK20-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 15030 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4 15031 // CHECK20-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 15032 // CHECK20-NEXT: store i64 40, i64* [[TMP97]], align 4 15033 // CHECK20-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 15034 // CHECK20-NEXT: store i8* null, i8** [[TMP98]], align 4 15035 // CHECK20-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 15036 // CHECK20-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i32* 15037 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP100]], align 4 15038 // CHECK20-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 15039 // CHECK20-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i32* 15040 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP102]], align 4 15041 // CHECK20-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 15042 // CHECK20-NEXT: store i64 4, i64* [[TMP103]], align 4 15043 // CHECK20-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 15044 // CHECK20-NEXT: store i8* null, i8** [[TMP104]], align 4 15045 // CHECK20-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 15046 // CHECK20-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** 15047 // CHECK20-NEXT: store float* [[VLA]], float** [[TMP106]], align 4 15048 // CHECK20-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 15049 // CHECK20-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** 15050 // CHECK20-NEXT: store float* [[VLA]], float** [[TMP108]], align 4 15051 // CHECK20-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 15052 // CHECK20-NEXT: store i64 [[TMP83]], i64* [[TMP109]], align 4 15053 // CHECK20-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 15054 // CHECK20-NEXT: store i8* null, i8** [[TMP110]], align 4 15055 // CHECK20-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 15056 // CHECK20-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** 15057 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4 15058 // CHECK20-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 15059 // CHECK20-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** 15060 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 4 15061 // CHECK20-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 15062 // CHECK20-NEXT: store i64 400, i64* [[TMP115]], align 4 15063 // CHECK20-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 15064 // CHECK20-NEXT: store i8* null, i8** [[TMP116]], align 4 15065 // CHECK20-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 15066 // CHECK20-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to i32* 15067 // CHECK20-NEXT: store i32 5, i32* [[TMP118]], align 4 15068 // CHECK20-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 15069 // CHECK20-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32* 15070 // CHECK20-NEXT: store i32 5, i32* [[TMP120]], align 4 15071 // CHECK20-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 15072 // CHECK20-NEXT: store i64 4, i64* [[TMP121]], align 4 15073 // CHECK20-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 15074 // CHECK20-NEXT: store i8* null, i8** [[TMP122]], align 4 15075 // CHECK20-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 15076 // CHECK20-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32* 15077 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP124]], align 4 15078 // CHECK20-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 15079 // CHECK20-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* 15080 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP126]], align 4 15081 // CHECK20-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 15082 // CHECK20-NEXT: store i64 4, i64* [[TMP127]], align 4 15083 // CHECK20-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 15084 // CHECK20-NEXT: store i8* null, i8** [[TMP128]], align 4 15085 // CHECK20-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 15086 // CHECK20-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to double** 15087 // CHECK20-NEXT: store double* [[VLA1]], double** [[TMP130]], align 4 15088 // CHECK20-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 15089 // CHECK20-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double** 15090 // CHECK20-NEXT: store double* [[VLA1]], double** [[TMP132]], align 4 15091 // CHECK20-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 15092 // CHECK20-NEXT: store i64 [[TMP86]], i64* [[TMP133]], align 4 15093 // CHECK20-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 15094 // CHECK20-NEXT: store i8* null, i8** [[TMP134]], align 4 15095 // CHECK20-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 15096 // CHECK20-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to %struct.TT** 15097 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP136]], align 4 15098 // CHECK20-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 15099 // CHECK20-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT** 15100 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 4 15101 // CHECK20-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 15102 // CHECK20-NEXT: store i64 12, i64* [[TMP139]], align 4 15103 // CHECK20-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 15104 // CHECK20-NEXT: store i8* null, i8** [[TMP140]], align 4 15105 // CHECK20-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 15106 // CHECK20-NEXT: [[TMP142:%.*]] = bitcast i8** [[TMP141]] to i32* 15107 // CHECK20-NEXT: store i32 [[TMP80]], i32* [[TMP142]], align 4 15108 // CHECK20-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 15109 // CHECK20-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i32* 15110 // CHECK20-NEXT: store i32 [[TMP80]], i32* [[TMP144]], align 4 15111 // CHECK20-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 15112 // CHECK20-NEXT: store i64 4, i64* [[TMP145]], align 4 15113 // CHECK20-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 15114 // CHECK20-NEXT: store i8* null, i8** [[TMP146]], align 4 15115 // CHECK20-NEXT: [[TMP147:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 15116 // CHECK20-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 15117 // CHECK20-NEXT: [[TMP149:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 15118 // CHECK20-NEXT: [[TMP150:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP147]], i8** [[TMP148]], i64* [[TMP149]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 15119 // CHECK20-NEXT: [[TMP151:%.*]] = icmp ne i32 [[TMP150]], 0 15120 // CHECK20-NEXT: br i1 [[TMP151]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] 15121 // CHECK20: omp_offload.failed17: 15122 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 15123 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT18]] 15124 // CHECK20: omp_offload.cont18: 15125 // CHECK20-NEXT: br label [[OMP_IF_END20:%.*]] 15126 // CHECK20: omp_if.else19: 15127 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 15128 // CHECK20-NEXT: br label [[OMP_IF_END20]] 15129 // CHECK20: omp_if.end20: 15130 // CHECK20-NEXT: [[TMP152:%.*]] = load i32, i32* [[A]], align 4 15131 // CHECK20-NEXT: [[TMP153:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 15132 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP153]]) 15133 // CHECK20-NEXT: ret i32 [[TMP152]] 15134 // 15135 // 15136 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 15137 // CHECK20-SAME: () #[[ATTR2:[0-9]+]] { 15138 // CHECK20-NEXT: entry: 15139 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 15140 // CHECK20-NEXT: ret void 15141 // 15142 // 15143 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. 15144 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 15145 // CHECK20-NEXT: entry: 15146 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15147 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15148 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 15149 // CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 15150 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 15151 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 15152 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 15153 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 15154 // CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 15155 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15156 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15157 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 15158 // CHECK20-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 15159 // CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 15160 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 15161 // CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 15162 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 15163 // CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 15164 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15165 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 15166 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 15167 // CHECK20: cond.true: 15168 // CHECK20-NEXT: br label [[COND_END:%.*]] 15169 // CHECK20: cond.false: 15170 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15171 // CHECK20-NEXT: br label [[COND_END]] 15172 // CHECK20: cond.end: 15173 // CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 15174 // CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 15175 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 15176 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 15177 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 15178 // CHECK20: omp.inner.for.cond: 15179 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15180 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15181 // CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 15182 // CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 15183 // CHECK20: omp.inner.for.body: 15184 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15185 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 15186 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 15187 // CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 15188 // CHECK20-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 15189 // CHECK20-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 15190 // CHECK20-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 15191 // CHECK20: .cancel.exit: 15192 // CHECK20-NEXT: br label [[CANCEL_EXIT:%.*]] 15193 // CHECK20: .cancel.continue: 15194 // CHECK20-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 15195 // CHECK20-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 15196 // CHECK20-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 15197 // CHECK20: .cancel.exit2: 15198 // CHECK20-NEXT: br label [[CANCEL_EXIT]] 15199 // CHECK20: .cancel.continue3: 15200 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 15201 // CHECK20: omp.body.continue: 15202 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 15203 // CHECK20: omp.inner.for.inc: 15204 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15205 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 15206 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 15207 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] 15208 // CHECK20: omp.inner.for.end: 15209 // CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 15210 // CHECK20: omp.loop.exit: 15211 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 15212 // CHECK20-NEXT: br label [[CANCEL_CONT:%.*]] 15213 // CHECK20: cancel.cont: 15214 // CHECK20-NEXT: ret void 15215 // CHECK20: cancel.exit: 15216 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 15217 // CHECK20-NEXT: br label [[CANCEL_CONT]] 15218 // 15219 // 15220 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 15221 // CHECK20-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 15222 // CHECK20-NEXT: entry: 15223 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15224 // CHECK20-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 15225 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 15226 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15227 // CHECK20-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 15228 // CHECK20-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 15229 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 15230 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 15231 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 15232 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) 15233 // CHECK20-NEXT: ret void 15234 // 15235 // 15236 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 15237 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 15238 // CHECK20-NEXT: entry: 15239 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15240 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15241 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15242 // CHECK20-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 15243 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 15244 // CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 15245 // CHECK20-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 15246 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 15247 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 15248 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 15249 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 15250 // CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 15251 // CHECK20-NEXT: [[K1:%.*]] = alloca i64, align 8 15252 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15253 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15254 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15255 // CHECK20-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 15256 // CHECK20-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 15257 // CHECK20-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 15258 // CHECK20-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 15259 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 15260 // CHECK20-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 15261 // CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 15262 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 15263 // CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 15264 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 15265 // CHECK20-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 15266 // CHECK20-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 15267 // CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 15268 // CHECK20: omp.dispatch.cond: 15269 // CHECK20-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 15270 // CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 15271 // CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 15272 // CHECK20: omp.dispatch.body: 15273 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 15274 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 15275 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 15276 // CHECK20: omp.inner.for.cond: 15277 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 15278 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 15279 // CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 15280 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 15281 // CHECK20: omp.inner.for.body: 15282 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 15283 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 15284 // CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 15285 // CHECK20-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13 15286 // CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !13 15287 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 15288 // CHECK20-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 15289 // CHECK20-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 15290 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 15291 // CHECK20-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13 15292 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !13 15293 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 15294 // CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13 15295 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 15296 // CHECK20: omp.body.continue: 15297 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 15298 // CHECK20: omp.inner.for.inc: 15299 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 15300 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 15301 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 15302 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 15303 // CHECK20: omp.inner.for.end: 15304 // CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 15305 // CHECK20: omp.dispatch.inc: 15306 // CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] 15307 // CHECK20: omp.dispatch.end: 15308 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 15309 // CHECK20-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 15310 // CHECK20-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 15311 // CHECK20: .omp.linear.pu: 15312 // CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[K1]], align 8 15313 // CHECK20-NEXT: store i64 [[TMP15]], i64* [[TMP0]], align 8 15314 // CHECK20-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 15315 // CHECK20: .omp.linear.pu.done: 15316 // CHECK20-NEXT: ret void 15317 // 15318 // 15319 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 15320 // CHECK20-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 15321 // CHECK20-NEXT: entry: 15322 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 15323 // CHECK20-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 15324 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15325 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 15326 // CHECK20-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 15327 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 15328 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 15329 // CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 15330 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15331 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 15332 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 15333 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 15334 // CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 15335 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 15336 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 15337 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 15338 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 15339 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 15340 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 15341 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 15342 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 15343 // CHECK20-NEXT: ret void 15344 // 15345 // 15346 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 15347 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 15348 // CHECK20-NEXT: entry: 15349 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15350 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15351 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 15352 // CHECK20-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 15353 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15354 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 15355 // CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 15356 // CHECK20-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 15357 // CHECK20-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 15358 // CHECK20-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 15359 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 15360 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 15361 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 15362 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 15363 // CHECK20-NEXT: [[IT:%.*]] = alloca i64, align 8 15364 // CHECK20-NEXT: [[LIN2:%.*]] = alloca i32, align 4 15365 // CHECK20-NEXT: [[A3:%.*]] = alloca i32, align 4 15366 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15367 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15368 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 15369 // CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 15370 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15371 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 15372 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 15373 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 15374 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 15375 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 15376 // CHECK20-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 15377 // CHECK20-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 15378 // CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 15379 // CHECK20-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 15380 // CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 15381 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 15382 // CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 15383 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 15384 // CHECK20-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 15385 // CHECK20-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 15386 // CHECK20-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 15387 // CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 15388 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 15389 // CHECK20: cond.true: 15390 // CHECK20-NEXT: br label [[COND_END:%.*]] 15391 // CHECK20: cond.false: 15392 // CHECK20-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 15393 // CHECK20-NEXT: br label [[COND_END]] 15394 // CHECK20: cond.end: 15395 // CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 15396 // CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 15397 // CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 15398 // CHECK20-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 15399 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 15400 // CHECK20: omp.inner.for.cond: 15401 // CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 15402 // CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 15403 // CHECK20-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 15404 // CHECK20-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 15405 // CHECK20: omp.inner.for.body: 15406 // CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 15407 // CHECK20-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 15408 // CHECK20-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 15409 // CHECK20-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 15410 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 15411 // CHECK20-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 15412 // CHECK20-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 15413 // CHECK20-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 15414 // CHECK20-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 15415 // CHECK20-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 15416 // CHECK20-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 15417 // CHECK20-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 15418 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 15419 // CHECK20-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 15420 // CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 15421 // CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 15422 // CHECK20-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 15423 // CHECK20-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 15424 // CHECK20-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 15425 // CHECK20-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 15426 // CHECK20-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 15427 // CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 15428 // CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 15429 // CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 15430 // CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 15431 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 15432 // CHECK20: omp.body.continue: 15433 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 15434 // CHECK20: omp.inner.for.inc: 15435 // CHECK20-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 15436 // CHECK20-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 15437 // CHECK20-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 15438 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] 15439 // CHECK20: omp.inner.for.end: 15440 // CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 15441 // CHECK20: omp.loop.exit: 15442 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 15443 // CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 15444 // CHECK20-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 15445 // CHECK20-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 15446 // CHECK20: .omp.linear.pu: 15447 // CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 15448 // CHECK20-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 15449 // CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 15450 // CHECK20-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 15451 // CHECK20-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 15452 // CHECK20: .omp.linear.pu.done: 15453 // CHECK20-NEXT: ret void 15454 // 15455 // 15456 // CHECK20-LABEL: define {{[^@]+}}@.omp_task_privates_map. 15457 // CHECK20-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 15458 // CHECK20-NEXT: entry: 15459 // CHECK20-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 15460 // CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 15461 // CHECK20-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 15462 // CHECK20-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 15463 // CHECK20-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 15464 // CHECK20-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 15465 // CHECK20-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 15466 // CHECK20-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 15467 // CHECK20-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 15468 // CHECK20-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 15469 // CHECK20-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 15470 // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 15471 // CHECK20-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 15472 // CHECK20-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 15473 // CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 15474 // CHECK20-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 15475 // CHECK20-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 15476 // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 15477 // CHECK20-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 15478 // CHECK20-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 15479 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 15480 // CHECK20-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 15481 // CHECK20-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 15482 // CHECK20-NEXT: ret void 15483 // 15484 // 15485 // CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry. 15486 // CHECK20-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 15487 // CHECK20-NEXT: entry: 15488 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 15489 // CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 15490 // CHECK20-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 15491 // CHECK20-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 15492 // CHECK20-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 15493 // CHECK20-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 15494 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 15495 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 15496 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 15497 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 15498 // CHECK20-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 15499 // CHECK20-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4 15500 // CHECK20-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4 15501 // CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 15502 // CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 15503 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 15504 // CHECK20-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 15505 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 15506 // CHECK20-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 15507 // CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 15508 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 15509 // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 15510 // CHECK20-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 15511 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 15512 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 15513 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 15514 // CHECK20-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 15515 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 15516 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 15517 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 15518 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 15519 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 15520 // CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 15521 // CHECK20-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 15522 // CHECK20-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 15523 // CHECK20-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 15524 // CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 15525 // CHECK20-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 15526 // CHECK20-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 15527 // CHECK20-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 15528 // CHECK20-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 15529 // CHECK20-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 15530 // CHECK20-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 15531 // CHECK20-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 15532 // CHECK20-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 15533 // CHECK20-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 15534 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 15535 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 15536 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 15537 // CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 15538 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 15539 // CHECK20-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 15540 // CHECK20-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 15541 // CHECK20-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 15542 // CHECK20: omp_offload.failed.i: 15543 // CHECK20-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 15544 // CHECK20-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 15545 // CHECK20-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25 15546 // CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 15547 // CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 15548 // CHECK20-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25 15549 // CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !25 15550 // CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 15551 // CHECK20-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25 15552 // CHECK20-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !25 15553 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR4]] 15554 // CHECK20-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 15555 // CHECK20: .omp_outlined..3.exit: 15556 // CHECK20-NEXT: ret i32 0 15557 // 15558 // 15559 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 15560 // CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 15561 // CHECK20-NEXT: entry: 15562 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15563 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 15564 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 15565 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 15566 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15567 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 15568 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 15569 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 15570 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 15571 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 15572 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 15573 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 15574 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 15575 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 15576 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 15577 // CHECK20-NEXT: ret void 15578 // 15579 // 15580 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 15581 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 15582 // CHECK20-NEXT: entry: 15583 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15584 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15585 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15586 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 15587 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 15588 // CHECK20-NEXT: [[TMP:%.*]] = alloca i16, align 2 15589 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 15590 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 15591 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 15592 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 15593 // CHECK20-NEXT: [[IT:%.*]] = alloca i16, align 2 15594 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15595 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15596 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15597 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 15598 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 15599 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 15600 // CHECK20-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 15601 // CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 15602 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 15603 // CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 15604 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 15605 // CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 15606 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15607 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 15608 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 15609 // CHECK20: cond.true: 15610 // CHECK20-NEXT: br label [[COND_END:%.*]] 15611 // CHECK20: cond.false: 15612 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15613 // CHECK20-NEXT: br label [[COND_END]] 15614 // CHECK20: cond.end: 15615 // CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 15616 // CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 15617 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 15618 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 15619 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 15620 // CHECK20: omp.inner.for.cond: 15621 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15622 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15623 // CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 15624 // CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 15625 // CHECK20: omp.inner.for.body: 15626 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15627 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 15628 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 15629 // CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 15630 // CHECK20-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 15631 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 15632 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 15633 // CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 15634 // CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 15635 // CHECK20-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 15636 // CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 15637 // CHECK20-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 15638 // CHECK20-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 15639 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 15640 // CHECK20: omp.body.continue: 15641 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 15642 // CHECK20: omp.inner.for.inc: 15643 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15644 // CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 15645 // CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 15646 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] 15647 // CHECK20: omp.inner.for.end: 15648 // CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 15649 // CHECK20: omp.loop.exit: 15650 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 15651 // CHECK20-NEXT: ret void 15652 // 15653 // 15654 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 15655 // CHECK20-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 15656 // CHECK20-NEXT: entry: 15657 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15658 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 15659 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 15660 // CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 15661 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 15662 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 15663 // CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 15664 // CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 15665 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 15666 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 15667 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 15668 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 15669 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15670 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 15671 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 15672 // CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 15673 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 15674 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 15675 // CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 15676 // CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 15677 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 15678 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 15679 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 15680 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 15681 // CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 15682 // CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 15683 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 15684 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 15685 // CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 15686 // CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 15687 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 15688 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 15689 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 15690 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 15691 // CHECK20-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 15692 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 15693 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 15694 // CHECK20-NEXT: ret void 15695 // 15696 // 15697 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 15698 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 15699 // CHECK20-NEXT: entry: 15700 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15701 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15702 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15703 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 15704 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 15705 // CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 15706 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 15707 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 15708 // CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 15709 // CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 15710 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 15711 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 15712 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 15713 // CHECK20-NEXT: [[TMP:%.*]] = alloca i8, align 1 15714 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 15715 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 15716 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 15717 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 15718 // CHECK20-NEXT: [[IT:%.*]] = alloca i8, align 1 15719 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15720 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15721 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15722 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 15723 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 15724 // CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 15725 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 15726 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 15727 // CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 15728 // CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 15729 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 15730 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 15731 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 15732 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 15733 // CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 15734 // CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 15735 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 15736 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 15737 // CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 15738 // CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 15739 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 15740 // CHECK20-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 15741 // CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 15742 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 15743 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 15744 // CHECK20-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 15745 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 15746 // CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 15747 // CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 15748 // CHECK20: omp.dispatch.cond: 15749 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15750 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 15751 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 15752 // CHECK20: cond.true: 15753 // CHECK20-NEXT: br label [[COND_END:%.*]] 15754 // CHECK20: cond.false: 15755 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15756 // CHECK20-NEXT: br label [[COND_END]] 15757 // CHECK20: cond.end: 15758 // CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 15759 // CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 15760 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 15761 // CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 15762 // CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15763 // CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15764 // CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 15765 // CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 15766 // CHECK20: omp.dispatch.body: 15767 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 15768 // CHECK20: omp.inner.for.cond: 15769 // CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15770 // CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15771 // CHECK20-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 15772 // CHECK20-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 15773 // CHECK20: omp.inner.for.body: 15774 // CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15775 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 15776 // CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 15777 // CHECK20-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 15778 // CHECK20-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 15779 // CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 15780 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 15781 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 15782 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 15783 // CHECK20-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 15784 // CHECK20-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 15785 // CHECK20-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 15786 // CHECK20-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 15787 // CHECK20-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 15788 // CHECK20-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 15789 // CHECK20-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 15790 // CHECK20-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 15791 // CHECK20-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 15792 // CHECK20-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 15793 // CHECK20-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 15794 // CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 15795 // CHECK20-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 15796 // CHECK20-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 15797 // CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 15798 // CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 15799 // CHECK20-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 15800 // CHECK20-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 15801 // CHECK20-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 15802 // CHECK20-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 15803 // CHECK20-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 15804 // CHECK20-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 15805 // CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 15806 // CHECK20-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 15807 // CHECK20-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 15808 // CHECK20-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 15809 // CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 15810 // CHECK20-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 15811 // CHECK20-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 15812 // CHECK20-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 15813 // CHECK20-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 15814 // CHECK20-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 15815 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 15816 // CHECK20: omp.body.continue: 15817 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 15818 // CHECK20: omp.inner.for.inc: 15819 // CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 15820 // CHECK20-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 15821 // CHECK20-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 15822 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] 15823 // CHECK20: omp.inner.for.end: 15824 // CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 15825 // CHECK20: omp.dispatch.inc: 15826 // CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 15827 // CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 15828 // CHECK20-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 15829 // CHECK20-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 15830 // CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 15831 // CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 15832 // CHECK20-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 15833 // CHECK20-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 15834 // CHECK20-NEXT: br label [[OMP_DISPATCH_COND]] 15835 // CHECK20: omp.dispatch.end: 15836 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 15837 // CHECK20-NEXT: ret void 15838 // 15839 // 15840 // CHECK20-LABEL: define {{[^@]+}}@_Z3bari 15841 // CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 15842 // CHECK20-NEXT: entry: 15843 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15844 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 15845 // CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 15846 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15847 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 15848 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 15849 // CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 15850 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 15851 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 15852 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 15853 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 15854 // CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 15855 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 15856 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 15857 // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 15858 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 15859 // CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 15860 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 15861 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 15862 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 15863 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 15864 // CHECK20-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 15865 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 15866 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 15867 // CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 15868 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 15869 // CHECK20-NEXT: ret i32 [[TMP8]] 15870 // 15871 // 15872 // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 15873 // CHECK20-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 15874 // CHECK20-NEXT: entry: 15875 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 15876 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15877 // CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 15878 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 15879 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 15880 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 15881 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 15882 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 15883 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 15884 // CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 15885 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 15886 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15887 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 15888 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 15889 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 15890 // CHECK20-NEXT: store i32 [[ADD]], i32* [[B]], align 4 15891 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 15892 // CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 15893 // CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 15894 // CHECK20-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 15895 // CHECK20-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 15896 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 15897 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 15898 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 15899 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 15900 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 15901 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 15902 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 15903 // CHECK20: omp_if.then: 15904 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 15905 // CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 15906 // CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 15907 // CHECK20-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 15908 // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 15909 // CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 15910 // CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 15911 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 15912 // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 15913 // CHECK20-NEXT: store double* [[A]], double** [[TMP13]], align 4 15914 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 15915 // CHECK20-NEXT: store i64 8, i64* [[TMP14]], align 4 15916 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 15917 // CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 15918 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 15919 // CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 15920 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 15921 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 15922 // CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 15923 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 15924 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 15925 // CHECK20-NEXT: store i64 4, i64* [[TMP20]], align 4 15926 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 15927 // CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 15928 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 15929 // CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 15930 // CHECK20-NEXT: store i32 2, i32* [[TMP23]], align 4 15931 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 15932 // CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 15933 // CHECK20-NEXT: store i32 2, i32* [[TMP25]], align 4 15934 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 15935 // CHECK20-NEXT: store i64 4, i64* [[TMP26]], align 4 15936 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 15937 // CHECK20-NEXT: store i8* null, i8** [[TMP27]], align 4 15938 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 15939 // CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 15940 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 15941 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 15942 // CHECK20-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* 15943 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 15944 // CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 15945 // CHECK20-NEXT: store i64 4, i64* [[TMP32]], align 4 15946 // CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 15947 // CHECK20-NEXT: store i8* null, i8** [[TMP33]], align 4 15948 // CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 15949 // CHECK20-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 15950 // CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 15951 // CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 15952 // CHECK20-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 15953 // CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 15954 // CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 15955 // CHECK20-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 15956 // CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 15957 // CHECK20-NEXT: store i8* null, i8** [[TMP39]], align 4 15958 // CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 15959 // CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 15960 // CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 15961 // CHECK20-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 15962 // CHECK20-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 15963 // CHECK20-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 15964 // CHECK20: omp_offload.failed: 15965 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 15966 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 15967 // CHECK20: omp_offload.cont: 15968 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 15969 // CHECK20: omp_if.else: 15970 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 15971 // CHECK20-NEXT: br label [[OMP_IF_END]] 15972 // CHECK20: omp_if.end: 15973 // CHECK20-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] 15974 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] 15975 // CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 15976 // CHECK20-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 15977 // CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 15978 // CHECK20-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 15979 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] 15980 // CHECK20-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 15981 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 15982 // CHECK20-NEXT: ret i32 [[ADD3]] 15983 // 15984 // 15985 // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici 15986 // CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 15987 // CHECK20-NEXT: entry: 15988 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15989 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 15990 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 15991 // CHECK20-NEXT: [[AAA:%.*]] = alloca i8, align 1 15992 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 15993 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 15994 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 15995 // CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 15996 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 15997 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 15998 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 15999 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 16000 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 16001 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 16002 // CHECK20-NEXT: store i8 0, i8* [[AAA]], align 1 16003 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 16004 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 16005 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 16006 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 16007 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 16008 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 16009 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 16010 // CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 16011 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 16012 // CHECK20-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 16013 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 16014 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 16015 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 16016 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 16017 // CHECK20: omp_if.then: 16018 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 16019 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 16020 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 16021 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 16022 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 16023 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 16024 // CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 16025 // CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4 16026 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 16027 // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 16028 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 16029 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 16030 // CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 16031 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 16032 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 16033 // CHECK20-NEXT: store i8* null, i8** [[TMP16]], align 4 16034 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 16035 // CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 16036 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 16037 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 16038 // CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 16039 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 16040 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 16041 // CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 16042 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 16043 // CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 16044 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 16045 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 16046 // CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 16047 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 16048 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 16049 // CHECK20-NEXT: store i8* null, i8** [[TMP26]], align 4 16050 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 16051 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 16052 // CHECK20-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 16053 // CHECK20-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 16054 // CHECK20-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 16055 // CHECK20: omp_offload.failed: 16056 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 16057 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 16058 // CHECK20: omp_offload.cont: 16059 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 16060 // CHECK20: omp_if.else: 16061 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 16062 // CHECK20-NEXT: br label [[OMP_IF_END]] 16063 // CHECK20: omp_if.end: 16064 // CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 16065 // CHECK20-NEXT: ret i32 [[TMP31]] 16066 // 16067 // 16068 // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 16069 // CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 16070 // CHECK20-NEXT: entry: 16071 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 16072 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 16073 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 16074 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 16075 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 16076 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 16077 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 16078 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 16079 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 16080 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 16081 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 16082 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 16083 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 16084 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 16085 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 16086 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 16087 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 16088 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 16089 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 16090 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 16091 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 16092 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 16093 // CHECK20: omp_if.then: 16094 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 16095 // CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 16096 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 16097 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 16098 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 16099 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 16100 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 16101 // CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4 16102 // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 16103 // CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 16104 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 16105 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 16106 // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 16107 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 16108 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 16109 // CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4 16110 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 16111 // CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 16112 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 16113 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 16114 // CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 16115 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 16116 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 16117 // CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 16118 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 16119 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 16120 // CHECK20-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 16121 // CHECK20-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 16122 // CHECK20-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 16123 // CHECK20: omp_offload.failed: 16124 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 16125 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 16126 // CHECK20: omp_offload.cont: 16127 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 16128 // CHECK20: omp_if.else: 16129 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 16130 // CHECK20-NEXT: br label [[OMP_IF_END]] 16131 // CHECK20: omp_if.end: 16132 // CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 16133 // CHECK20-NEXT: ret i32 [[TMP24]] 16134 // 16135 // 16136 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 16137 // CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 16138 // CHECK20-NEXT: entry: 16139 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 16140 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 16141 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 16142 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 16143 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 16144 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 16145 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 16146 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 16147 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 16148 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 16149 // CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 16150 // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 16151 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 16152 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 16153 // CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 16154 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 16155 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 16156 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 16157 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 16158 // CHECK20-NEXT: ret void 16159 // 16160 // 16161 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 16162 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 16163 // CHECK20-NEXT: entry: 16164 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 16165 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 16166 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 16167 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 16168 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 16169 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 16170 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 16171 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 16172 // CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 16173 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 16174 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 16175 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 16176 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 16177 // CHECK20-NEXT: [[IT:%.*]] = alloca i64, align 8 16178 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 16179 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 16180 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 16181 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 16182 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 16183 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 16184 // CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 16185 // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 16186 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 16187 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 16188 // CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 16189 // CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 16190 // CHECK20-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 16191 // CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 16192 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 16193 // CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 16194 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 16195 // CHECK20-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 16196 // CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16197 // CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 16198 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 16199 // CHECK20: cond.true: 16200 // CHECK20-NEXT: br label [[COND_END:%.*]] 16201 // CHECK20: cond.false: 16202 // CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16203 // CHECK20-NEXT: br label [[COND_END]] 16204 // CHECK20: cond.end: 16205 // CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 16206 // CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 16207 // CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 16208 // CHECK20-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 16209 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 16210 // CHECK20: omp.inner.for.cond: 16211 // CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16212 // CHECK20-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16213 // CHECK20-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 16214 // CHECK20-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 16215 // CHECK20: omp.inner.for.body: 16216 // CHECK20-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16217 // CHECK20-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 16218 // CHECK20-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 16219 // CHECK20-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 16220 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 16221 // CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 16222 // CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 16223 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 16224 // CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 16225 // CHECK20-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 16226 // CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 16227 // CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 16228 // CHECK20-NEXT: store double [[INC]], double* [[A4]], align 4 16229 // CHECK20-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 16230 // CHECK20-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 16231 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 16232 // CHECK20-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 16233 // CHECK20-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 16234 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 16235 // CHECK20: omp.body.continue: 16236 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 16237 // CHECK20: omp.inner.for.inc: 16238 // CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16239 // CHECK20-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 16240 // CHECK20-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 16241 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] 16242 // CHECK20: omp.inner.for.end: 16243 // CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 16244 // CHECK20: omp.loop.exit: 16245 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 16246 // CHECK20-NEXT: ret void 16247 // 16248 // 16249 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 16250 // CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 16251 // CHECK20-NEXT: entry: 16252 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 16253 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 16254 // CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 16255 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 16256 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 16257 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 16258 // CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 16259 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 16260 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 16261 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 16262 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 16263 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 16264 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 16265 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 16266 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 16267 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 16268 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 16269 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 16270 // CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 16271 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 16272 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 16273 // CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 16274 // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 16275 // CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 16276 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 16277 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 16278 // CHECK20-NEXT: ret void 16279 // 16280 // 16281 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 16282 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 16283 // CHECK20-NEXT: entry: 16284 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 16285 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 16286 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 16287 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 16288 // CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 16289 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 16290 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 16291 // CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 16292 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 16293 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 16294 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 16295 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 16296 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 16297 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 16298 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 16299 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 16300 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 16301 // CHECK20-NEXT: ret void 16302 // 16303 // 16304 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 16305 // CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 16306 // CHECK20-NEXT: entry: 16307 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 16308 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 16309 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 16310 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 16311 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 16312 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 16313 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 16314 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 16315 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 16316 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 16317 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 16318 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 16319 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 16320 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 16321 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 16322 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 16323 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 16324 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 16325 // CHECK20-NEXT: ret void 16326 // 16327 // 16328 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..14 16329 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 16330 // CHECK20-NEXT: entry: 16331 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 16332 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 16333 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 16334 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 16335 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 16336 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 16337 // CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 16338 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 16339 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 16340 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 16341 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 16342 // CHECK20-NEXT: [[I:%.*]] = alloca i64, align 8 16343 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 16344 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 16345 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 16346 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 16347 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 16348 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 16349 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 16350 // CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 16351 // CHECK20-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 16352 // CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 16353 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 16354 // CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 16355 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 16356 // CHECK20-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 16357 // CHECK20-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16358 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 16359 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 16360 // CHECK20: cond.true: 16361 // CHECK20-NEXT: br label [[COND_END:%.*]] 16362 // CHECK20: cond.false: 16363 // CHECK20-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16364 // CHECK20-NEXT: br label [[COND_END]] 16365 // CHECK20: cond.end: 16366 // CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 16367 // CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 16368 // CHECK20-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 16369 // CHECK20-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 16370 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 16371 // CHECK20: omp.inner.for.cond: 16372 // CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16373 // CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16374 // CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 16375 // CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 16376 // CHECK20: omp.inner.for.body: 16377 // CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16378 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 16379 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 16380 // CHECK20-NEXT: store i64 [[ADD]], i64* [[I]], align 8 16381 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 16382 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 16383 // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 16384 // CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 16385 // CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 16386 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 16387 // CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 16388 // CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 16389 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 16390 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 16391 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 16392 // CHECK20-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 16393 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 16394 // CHECK20: omp.body.continue: 16395 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 16396 // CHECK20: omp.inner.for.inc: 16397 // CHECK20-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16398 // CHECK20-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 16399 // CHECK20-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 16400 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] 16401 // CHECK20: omp.inner.for.end: 16402 // CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 16403 // CHECK20: omp.loop.exit: 16404 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 16405 // CHECK20-NEXT: ret void 16406 // 16407 // 16408 // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 16409 // CHECK20-SAME: () #[[ATTR6]] { 16410 // CHECK20-NEXT: entry: 16411 // CHECK20-NEXT: call void @__tgt_register_requires(i64 1) 16412 // CHECK20-NEXT: ret void 16413 // 16414 // 16415 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 16416 // CHECK25-SAME: () #[[ATTR0:[0-9]+]] { 16417 // CHECK25-NEXT: entry: 16418 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 16419 // CHECK25-NEXT: ret void 16420 // 16421 // 16422 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. 16423 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 16424 // CHECK25-NEXT: entry: 16425 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16426 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16427 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 16428 // CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 16429 // CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 16430 // CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 16431 // CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 16432 // CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 16433 // CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 16434 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16435 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16436 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 16437 // CHECK25-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 16438 // CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 16439 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 16440 // CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 16441 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 16442 // CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 16443 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16444 // CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 16445 // CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 16446 // CHECK25: cond.true: 16447 // CHECK25-NEXT: br label [[COND_END:%.*]] 16448 // CHECK25: cond.false: 16449 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16450 // CHECK25-NEXT: br label [[COND_END]] 16451 // CHECK25: cond.end: 16452 // CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 16453 // CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 16454 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 16455 // CHECK25-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 16456 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 16457 // CHECK25: omp.inner.for.cond: 16458 // CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16459 // CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16460 // CHECK25-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 16461 // CHECK25-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 16462 // CHECK25: omp.inner.for.body: 16463 // CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16464 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 16465 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 16466 // CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 16467 // CHECK25-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 16468 // CHECK25-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 16469 // CHECK25-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 16470 // CHECK25: .cancel.exit: 16471 // CHECK25-NEXT: br label [[CANCEL_EXIT:%.*]] 16472 // CHECK25: .cancel.continue: 16473 // CHECK25-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 16474 // CHECK25-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 16475 // CHECK25-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 16476 // CHECK25: .cancel.exit2: 16477 // CHECK25-NEXT: br label [[CANCEL_EXIT]] 16478 // CHECK25: .cancel.continue3: 16479 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 16480 // CHECK25: omp.body.continue: 16481 // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 16482 // CHECK25: omp.inner.for.inc: 16483 // CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16484 // CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 16485 // CHECK25-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 16486 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] 16487 // CHECK25: omp.inner.for.end: 16488 // CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 16489 // CHECK25: omp.loop.exit: 16490 // CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 16491 // CHECK25-NEXT: br label [[CANCEL_CONT:%.*]] 16492 // CHECK25: cancel.cont: 16493 // CHECK25-NEXT: ret void 16494 // CHECK25: cancel.exit: 16495 // CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 16496 // CHECK25-NEXT: br label [[CANCEL_CONT]] 16497 // 16498 // 16499 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 16500 // CHECK25-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 16501 // CHECK25-NEXT: entry: 16502 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16503 // CHECK25-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 16504 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16505 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 16506 // CHECK25-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 16507 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 16508 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16509 // CHECK25-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 16510 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16511 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16512 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 16513 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16514 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 16515 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 16516 // CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 16517 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 16518 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 16519 // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 16520 // CHECK25-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 16521 // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 16522 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 16523 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 16524 // CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 16525 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 16526 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 16527 // CHECK25-NEXT: ret void 16528 // 16529 // 16530 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 16531 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 16532 // CHECK25-NEXT: entry: 16533 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16534 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16535 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16536 // CHECK25-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 16537 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16538 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 16539 // CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8 16540 // CHECK25-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 16541 // CHECK25-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 16542 // CHECK25-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 16543 // CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 16544 // CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 16545 // CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 16546 // CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 16547 // CHECK25-NEXT: [[IT:%.*]] = alloca i64, align 8 16548 // CHECK25-NEXT: [[LIN4:%.*]] = alloca i32, align 4 16549 // CHECK25-NEXT: [[A5:%.*]] = alloca i32, align 4 16550 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16551 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16552 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16553 // CHECK25-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 16554 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16555 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16556 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 16557 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16558 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 16559 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 16560 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 16561 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 16562 // CHECK25-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 16563 // CHECK25-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 16564 // CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 16565 // CHECK25-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 16566 // CHECK25-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 16567 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 16568 // CHECK25-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 16569 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 16570 // CHECK25-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 16571 // CHECK25-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 16572 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16573 // CHECK25-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 16574 // CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 16575 // CHECK25: cond.true: 16576 // CHECK25-NEXT: br label [[COND_END:%.*]] 16577 // CHECK25: cond.false: 16578 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16579 // CHECK25-NEXT: br label [[COND_END]] 16580 // CHECK25: cond.end: 16581 // CHECK25-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 16582 // CHECK25-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 16583 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 16584 // CHECK25-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 16585 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 16586 // CHECK25: omp.inner.for.cond: 16587 // CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16588 // CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 16589 // CHECK25-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 16590 // CHECK25-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 16591 // CHECK25: omp.inner.for.body: 16592 // CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16593 // CHECK25-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 16594 // CHECK25-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 16595 // CHECK25-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 16596 // CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 16597 // CHECK25-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 16598 // CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16599 // CHECK25-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 16600 // CHECK25-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 16601 // CHECK25-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 16602 // CHECK25-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 16603 // CHECK25-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 16604 // CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 16605 // CHECK25-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 16606 // CHECK25-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16607 // CHECK25-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 16608 // CHECK25-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 16609 // CHECK25-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 16610 // CHECK25-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 16611 // CHECK25-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 16612 // CHECK25-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 16613 // CHECK25-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 16614 // CHECK25-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 16615 // CHECK25-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 16616 // CHECK25-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 16617 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 16618 // CHECK25: omp.body.continue: 16619 // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 16620 // CHECK25: omp.inner.for.inc: 16621 // CHECK25-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 16622 // CHECK25-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 16623 // CHECK25-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 16624 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] 16625 // CHECK25: omp.inner.for.end: 16626 // CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 16627 // CHECK25: omp.loop.exit: 16628 // CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 16629 // CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 16630 // CHECK25-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 16631 // CHECK25-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 16632 // CHECK25: .omp.linear.pu: 16633 // CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 16634 // CHECK25-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 16635 // CHECK25-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 16636 // CHECK25-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 16637 // CHECK25-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 16638 // CHECK25: .omp.linear.pu.done: 16639 // CHECK25-NEXT: ret void 16640 // 16641 // 16642 // CHECK25-LABEL: define {{[^@]+}}@_Z7get_valv 16643 // CHECK25-SAME: () #[[ATTR3:[0-9]+]] { 16644 // CHECK25-NEXT: entry: 16645 // CHECK25-NEXT: ret i64 0 16646 // 16647 // 16648 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 16649 // CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 16650 // CHECK25-NEXT: entry: 16651 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16652 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16653 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 16654 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 16655 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16656 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16657 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16658 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16659 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 16660 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 16661 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 16662 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 16663 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 16664 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 16665 // CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 16666 // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 16667 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 16668 // CHECK25-NEXT: ret void 16669 // 16670 // 16671 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 16672 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 16673 // CHECK25-NEXT: entry: 16674 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16675 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16676 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16677 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16678 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 16679 // CHECK25-NEXT: [[TMP:%.*]] = alloca i16, align 2 16680 // CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 16681 // CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 16682 // CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 16683 // CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 16684 // CHECK25-NEXT: [[IT:%.*]] = alloca i16, align 2 16685 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16686 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16687 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16688 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16689 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16690 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16691 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 16692 // CHECK25-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 16693 // CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 16694 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 16695 // CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 16696 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 16697 // CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 16698 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16699 // CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 16700 // CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 16701 // CHECK25: cond.true: 16702 // CHECK25-NEXT: br label [[COND_END:%.*]] 16703 // CHECK25: cond.false: 16704 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16705 // CHECK25-NEXT: br label [[COND_END]] 16706 // CHECK25: cond.end: 16707 // CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 16708 // CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 16709 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 16710 // CHECK25-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 16711 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 16712 // CHECK25: omp.inner.for.cond: 16713 // CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16714 // CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16715 // CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 16716 // CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 16717 // CHECK25: omp.inner.for.body: 16718 // CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16719 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 16720 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 16721 // CHECK25-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 16722 // CHECK25-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 16723 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 16724 // CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 16725 // CHECK25-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 16726 // CHECK25-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 16727 // CHECK25-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 16728 // CHECK25-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 16729 // CHECK25-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 16730 // CHECK25-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 16731 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 16732 // CHECK25: omp.body.continue: 16733 // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 16734 // CHECK25: omp.inner.for.inc: 16735 // CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16736 // CHECK25-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 16737 // CHECK25-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 16738 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] 16739 // CHECK25: omp.inner.for.end: 16740 // CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 16741 // CHECK25: omp.loop.exit: 16742 // CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 16743 // CHECK25-NEXT: ret void 16744 // 16745 // 16746 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 16747 // CHECK25-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 16748 // CHECK25-NEXT: entry: 16749 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16750 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 16751 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 16752 // CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 16753 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 16754 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 16755 // CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 16756 // CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 16757 // CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 16758 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 16759 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 16760 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 16761 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16762 // CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 16763 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 16764 // CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 16765 // CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 16766 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 16767 // CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 16768 // CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 16769 // CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 16770 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 16771 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16772 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 16773 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 16774 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 16775 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 16776 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 16777 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 16778 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 16779 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 16780 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 16781 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 16782 // CHECK25-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 16783 // CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 16784 // CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 16785 // CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 16786 // CHECK25-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 16787 // CHECK25-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 16788 // CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 16789 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 16790 // CHECK25-NEXT: ret void 16791 // 16792 // 16793 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 16794 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 16795 // CHECK25-NEXT: entry: 16796 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16797 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16798 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16799 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 16800 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 16801 // CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 16802 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 16803 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 16804 // CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 16805 // CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 16806 // CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 16807 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 16808 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 16809 // CHECK25-NEXT: [[TMP:%.*]] = alloca i8, align 1 16810 // CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 16811 // CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 16812 // CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 16813 // CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 16814 // CHECK25-NEXT: [[IT:%.*]] = alloca i8, align 1 16815 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16816 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16817 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16818 // CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 16819 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 16820 // CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 16821 // CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 16822 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 16823 // CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 16824 // CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 16825 // CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 16826 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 16827 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16828 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 16829 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 16830 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 16831 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 16832 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 16833 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 16834 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 16835 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 16836 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 16837 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 16838 // CHECK25-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 16839 // CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 16840 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 16841 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 16842 // CHECK25-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 16843 // CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 16844 // CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 16845 // CHECK25-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 16846 // CHECK25: omp.dispatch.cond: 16847 // CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16848 // CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 16849 // CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 16850 // CHECK25: cond.true: 16851 // CHECK25-NEXT: br label [[COND_END:%.*]] 16852 // CHECK25: cond.false: 16853 // CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16854 // CHECK25-NEXT: br label [[COND_END]] 16855 // CHECK25: cond.end: 16856 // CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 16857 // CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 16858 // CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 16859 // CHECK25-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 16860 // CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16861 // CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16862 // CHECK25-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 16863 // CHECK25-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 16864 // CHECK25: omp.dispatch.body: 16865 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 16866 // CHECK25: omp.inner.for.cond: 16867 // CHECK25-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16868 // CHECK25-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16869 // CHECK25-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 16870 // CHECK25-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 16871 // CHECK25: omp.inner.for.body: 16872 // CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16873 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 16874 // CHECK25-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 16875 // CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 16876 // CHECK25-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 16877 // CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 16878 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 16879 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 16880 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 16881 // CHECK25-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 16882 // CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 16883 // CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 16884 // CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 16885 // CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 16886 // CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 16887 // CHECK25-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 16888 // CHECK25-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 16889 // CHECK25-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 16890 // CHECK25-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 16891 // CHECK25-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 16892 // CHECK25-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 16893 // CHECK25-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 16894 // CHECK25-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 16895 // CHECK25-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 16896 // CHECK25-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 16897 // CHECK25-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 16898 // CHECK25-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 16899 // CHECK25-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 16900 // CHECK25-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 16901 // CHECK25-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 16902 // CHECK25-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 16903 // CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 16904 // CHECK25-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 16905 // CHECK25-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 16906 // CHECK25-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 16907 // CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 16908 // CHECK25-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 16909 // CHECK25-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 16910 // CHECK25-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 16911 // CHECK25-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 16912 // CHECK25-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 16913 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 16914 // CHECK25: omp.body.continue: 16915 // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 16916 // CHECK25: omp.inner.for.inc: 16917 // CHECK25-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 16918 // CHECK25-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 16919 // CHECK25-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 16920 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] 16921 // CHECK25: omp.inner.for.end: 16922 // CHECK25-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 16923 // CHECK25: omp.dispatch.inc: 16924 // CHECK25-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 16925 // CHECK25-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 16926 // CHECK25-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 16927 // CHECK25-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 16928 // CHECK25-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 16929 // CHECK25-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 16930 // CHECK25-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 16931 // CHECK25-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 16932 // CHECK25-NEXT: br label [[OMP_DISPATCH_COND]] 16933 // CHECK25: omp.dispatch.end: 16934 // CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 16935 // CHECK25-NEXT: ret void 16936 // 16937 // 16938 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 16939 // CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 16940 // CHECK25-NEXT: entry: 16941 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16942 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16943 // CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 16944 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 16945 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 16946 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 16947 // CHECK25-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 16948 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16949 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16950 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 16951 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 16952 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16953 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16954 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 16955 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 16956 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 16957 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 16958 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 16959 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 16960 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 16961 // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 16962 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 16963 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 16964 // CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 16965 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 16966 // CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 16967 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 16968 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 16969 // CHECK25-NEXT: ret void 16970 // 16971 // 16972 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 16973 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 16974 // CHECK25-NEXT: entry: 16975 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16976 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16977 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16978 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16979 // CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 16980 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 16981 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 16982 // CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 16983 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16984 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16985 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16986 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16987 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 16988 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 16989 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16990 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16991 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 16992 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 16993 // CHECK25-NEXT: ret void 16994 // 16995 // 16996 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 16997 // CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 16998 // CHECK25-NEXT: entry: 16999 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 17000 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 17001 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 17002 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 17003 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 17004 // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 17005 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 17006 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 17007 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 17008 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 17009 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 17010 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 17011 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 17012 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 17013 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 17014 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 17015 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 17016 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 17017 // CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 17018 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 17019 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 17020 // CHECK25-NEXT: ret void 17021 // 17022 // 17023 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 17024 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 17025 // CHECK25-NEXT: entry: 17026 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17027 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17028 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 17029 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 17030 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 17031 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 17032 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 17033 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 17034 // CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8 17035 // CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 17036 // CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 17037 // CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 17038 // CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 17039 // CHECK25-NEXT: [[IT:%.*]] = alloca i64, align 8 17040 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17041 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17042 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 17043 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 17044 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 17045 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 17046 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 17047 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 17048 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 17049 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 17050 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 17051 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 17052 // CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 17053 // CHECK25-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 17054 // CHECK25-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 17055 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 17056 // CHECK25-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 17057 // CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 17058 // CHECK25-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 17059 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17060 // CHECK25-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 17061 // CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 17062 // CHECK25: cond.true: 17063 // CHECK25-NEXT: br label [[COND_END:%.*]] 17064 // CHECK25: cond.false: 17065 // CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17066 // CHECK25-NEXT: br label [[COND_END]] 17067 // CHECK25: cond.end: 17068 // CHECK25-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 17069 // CHECK25-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 17070 // CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 17071 // CHECK25-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 17072 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 17073 // CHECK25: omp.inner.for.cond: 17074 // CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17075 // CHECK25-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17076 // CHECK25-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 17077 // CHECK25-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 17078 // CHECK25: omp.inner.for.body: 17079 // CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17080 // CHECK25-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 17081 // CHECK25-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 17082 // CHECK25-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 17083 // CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 17084 // CHECK25-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 17085 // CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 17086 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 17087 // CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 17088 // CHECK25-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 17089 // CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 17090 // CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 17091 // CHECK25-NEXT: store double [[INC]], double* [[A5]], align 8 17092 // CHECK25-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 17093 // CHECK25-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 17094 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 17095 // CHECK25-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 17096 // CHECK25-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 17097 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 17098 // CHECK25: omp.body.continue: 17099 // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 17100 // CHECK25: omp.inner.for.inc: 17101 // CHECK25-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17102 // CHECK25-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 17103 // CHECK25-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 17104 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] 17105 // CHECK25: omp.inner.for.end: 17106 // CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 17107 // CHECK25: omp.loop.exit: 17108 // CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 17109 // CHECK25-NEXT: ret void 17110 // 17111 // 17112 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 17113 // CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 17114 // CHECK25-NEXT: entry: 17115 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17116 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17117 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 17118 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 17119 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 17120 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17121 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17122 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 17123 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17124 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17125 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 17126 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 17127 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 17128 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 17129 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 17130 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 17131 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 17132 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 17133 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 17134 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 17135 // CHECK25-NEXT: ret void 17136 // 17137 // 17138 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 17139 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 17140 // CHECK25-NEXT: entry: 17141 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17142 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17143 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17144 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17145 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 17146 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 17147 // CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8 17148 // CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 17149 // CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 17150 // CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 17151 // CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 17152 // CHECK25-NEXT: [[I:%.*]] = alloca i64, align 8 17153 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17154 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17155 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17156 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17157 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 17158 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17159 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17160 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 17161 // CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 17162 // CHECK25-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 17163 // CHECK25-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 17164 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 17165 // CHECK25-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 17166 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 17167 // CHECK25-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 17168 // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17169 // CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 17170 // CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 17171 // CHECK25: cond.true: 17172 // CHECK25-NEXT: br label [[COND_END:%.*]] 17173 // CHECK25: cond.false: 17174 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17175 // CHECK25-NEXT: br label [[COND_END]] 17176 // CHECK25: cond.end: 17177 // CHECK25-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 17178 // CHECK25-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 17179 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 17180 // CHECK25-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 17181 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 17182 // CHECK25: omp.inner.for.cond: 17183 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17184 // CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17185 // CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 17186 // CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 17187 // CHECK25: omp.inner.for.body: 17188 // CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17189 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 17190 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 17191 // CHECK25-NEXT: store i64 [[ADD]], i64* [[I]], align 8 17192 // CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 17193 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 17194 // CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 17195 // CHECK25-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 17196 // CHECK25-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 17197 // CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 17198 // CHECK25-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 17199 // CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 17200 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 17201 // CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 17202 // CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 17203 // CHECK25-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 17204 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 17205 // CHECK25: omp.body.continue: 17206 // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 17207 // CHECK25: omp.inner.for.inc: 17208 // CHECK25-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17209 // CHECK25-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 17210 // CHECK25-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 17211 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] 17212 // CHECK25: omp.inner.for.end: 17213 // CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 17214 // CHECK25: omp.loop.exit: 17215 // CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 17216 // CHECK25-NEXT: ret void 17217 // 17218 // 17219 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 17220 // CHECK26-SAME: () #[[ATTR0:[0-9]+]] { 17221 // CHECK26-NEXT: entry: 17222 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 17223 // CHECK26-NEXT: ret void 17224 // 17225 // 17226 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. 17227 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 17228 // CHECK26-NEXT: entry: 17229 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17230 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17231 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 17232 // CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 17233 // CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 17234 // CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 17235 // CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 17236 // CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 17237 // CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4 17238 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17239 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17240 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 17241 // CHECK26-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 17242 // CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 17243 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 17244 // CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 17245 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 17246 // CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 17247 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17248 // CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 17249 // CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 17250 // CHECK26: cond.true: 17251 // CHECK26-NEXT: br label [[COND_END:%.*]] 17252 // CHECK26: cond.false: 17253 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17254 // CHECK26-NEXT: br label [[COND_END]] 17255 // CHECK26: cond.end: 17256 // CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 17257 // CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 17258 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 17259 // CHECK26-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 17260 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 17261 // CHECK26: omp.inner.for.cond: 17262 // CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17263 // CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17264 // CHECK26-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 17265 // CHECK26-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 17266 // CHECK26: omp.inner.for.body: 17267 // CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17268 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 17269 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 17270 // CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 17271 // CHECK26-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 17272 // CHECK26-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 17273 // CHECK26-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 17274 // CHECK26: .cancel.exit: 17275 // CHECK26-NEXT: br label [[CANCEL_EXIT:%.*]] 17276 // CHECK26: .cancel.continue: 17277 // CHECK26-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 17278 // CHECK26-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 17279 // CHECK26-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 17280 // CHECK26: .cancel.exit2: 17281 // CHECK26-NEXT: br label [[CANCEL_EXIT]] 17282 // CHECK26: .cancel.continue3: 17283 // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 17284 // CHECK26: omp.body.continue: 17285 // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 17286 // CHECK26: omp.inner.for.inc: 17287 // CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17288 // CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 17289 // CHECK26-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 17290 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] 17291 // CHECK26: omp.inner.for.end: 17292 // CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 17293 // CHECK26: omp.loop.exit: 17294 // CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 17295 // CHECK26-NEXT: br label [[CANCEL_CONT:%.*]] 17296 // CHECK26: cancel.cont: 17297 // CHECK26-NEXT: ret void 17298 // CHECK26: cancel.exit: 17299 // CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 17300 // CHECK26-NEXT: br label [[CANCEL_CONT]] 17301 // 17302 // 17303 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 17304 // CHECK26-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 17305 // CHECK26-NEXT: entry: 17306 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17307 // CHECK26-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 17308 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17309 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 17310 // CHECK26-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 17311 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 17312 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17313 // CHECK26-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 17314 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17315 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17316 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 17317 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17318 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 17319 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 17320 // CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 17321 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 17322 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 17323 // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 17324 // CHECK26-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 17325 // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 17326 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 17327 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 17328 // CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 17329 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 17330 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 17331 // CHECK26-NEXT: ret void 17332 // 17333 // 17334 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 17335 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 17336 // CHECK26-NEXT: entry: 17337 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17338 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17339 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17340 // CHECK26-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 17341 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17342 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 17343 // CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8 17344 // CHECK26-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 17345 // CHECK26-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 17346 // CHECK26-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 17347 // CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 17348 // CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 17349 // CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 17350 // CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 17351 // CHECK26-NEXT: [[IT:%.*]] = alloca i64, align 8 17352 // CHECK26-NEXT: [[LIN4:%.*]] = alloca i32, align 4 17353 // CHECK26-NEXT: [[A5:%.*]] = alloca i32, align 4 17354 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17355 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17356 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17357 // CHECK26-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 17358 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17359 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17360 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 17361 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17362 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 17363 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 17364 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 17365 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 17366 // CHECK26-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 17367 // CHECK26-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 17368 // CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 17369 // CHECK26-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 17370 // CHECK26-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 17371 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 17372 // CHECK26-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 17373 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 17374 // CHECK26-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 17375 // CHECK26-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 17376 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17377 // CHECK26-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 17378 // CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 17379 // CHECK26: cond.true: 17380 // CHECK26-NEXT: br label [[COND_END:%.*]] 17381 // CHECK26: cond.false: 17382 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17383 // CHECK26-NEXT: br label [[COND_END]] 17384 // CHECK26: cond.end: 17385 // CHECK26-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 17386 // CHECK26-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 17387 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 17388 // CHECK26-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 17389 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 17390 // CHECK26: omp.inner.for.cond: 17391 // CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17392 // CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17393 // CHECK26-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 17394 // CHECK26-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 17395 // CHECK26: omp.inner.for.body: 17396 // CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17397 // CHECK26-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 17398 // CHECK26-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 17399 // CHECK26-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 17400 // CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 17401 // CHECK26-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 17402 // CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17403 // CHECK26-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 17404 // CHECK26-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 17405 // CHECK26-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 17406 // CHECK26-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 17407 // CHECK26-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 17408 // CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 17409 // CHECK26-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 17410 // CHECK26-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17411 // CHECK26-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 17412 // CHECK26-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 17413 // CHECK26-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 17414 // CHECK26-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 17415 // CHECK26-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 17416 // CHECK26-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 17417 // CHECK26-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 17418 // CHECK26-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 17419 // CHECK26-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 17420 // CHECK26-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 17421 // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 17422 // CHECK26: omp.body.continue: 17423 // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 17424 // CHECK26: omp.inner.for.inc: 17425 // CHECK26-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17426 // CHECK26-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 17427 // CHECK26-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 17428 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] 17429 // CHECK26: omp.inner.for.end: 17430 // CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 17431 // CHECK26: omp.loop.exit: 17432 // CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 17433 // CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 17434 // CHECK26-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 17435 // CHECK26-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 17436 // CHECK26: .omp.linear.pu: 17437 // CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 17438 // CHECK26-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 17439 // CHECK26-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 17440 // CHECK26-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 17441 // CHECK26-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 17442 // CHECK26: .omp.linear.pu.done: 17443 // CHECK26-NEXT: ret void 17444 // 17445 // 17446 // CHECK26-LABEL: define {{[^@]+}}@_Z7get_valv 17447 // CHECK26-SAME: () #[[ATTR3:[0-9]+]] { 17448 // CHECK26-NEXT: entry: 17449 // CHECK26-NEXT: ret i64 0 17450 // 17451 // 17452 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 17453 // CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 17454 // CHECK26-NEXT: entry: 17455 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17456 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17457 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 17458 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 17459 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17460 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17461 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17462 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17463 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 17464 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 17465 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 17466 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 17467 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 17468 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 17469 // CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 17470 // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 17471 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 17472 // CHECK26-NEXT: ret void 17473 // 17474 // 17475 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 17476 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 17477 // CHECK26-NEXT: entry: 17478 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17479 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17480 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17481 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17482 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 17483 // CHECK26-NEXT: [[TMP:%.*]] = alloca i16, align 2 17484 // CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 17485 // CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 17486 // CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 17487 // CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 17488 // CHECK26-NEXT: [[IT:%.*]] = alloca i16, align 2 17489 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17490 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17491 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17492 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17493 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17494 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17495 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 17496 // CHECK26-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 17497 // CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 17498 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 17499 // CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 17500 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 17501 // CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 17502 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17503 // CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 17504 // CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 17505 // CHECK26: cond.true: 17506 // CHECK26-NEXT: br label [[COND_END:%.*]] 17507 // CHECK26: cond.false: 17508 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17509 // CHECK26-NEXT: br label [[COND_END]] 17510 // CHECK26: cond.end: 17511 // CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 17512 // CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 17513 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 17514 // CHECK26-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 17515 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 17516 // CHECK26: omp.inner.for.cond: 17517 // CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17518 // CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17519 // CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 17520 // CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 17521 // CHECK26: omp.inner.for.body: 17522 // CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17523 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 17524 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 17525 // CHECK26-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 17526 // CHECK26-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 17527 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 17528 // CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 17529 // CHECK26-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 17530 // CHECK26-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 17531 // CHECK26-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 17532 // CHECK26-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 17533 // CHECK26-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 17534 // CHECK26-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 17535 // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 17536 // CHECK26: omp.body.continue: 17537 // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 17538 // CHECK26: omp.inner.for.inc: 17539 // CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17540 // CHECK26-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 17541 // CHECK26-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 17542 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] 17543 // CHECK26: omp.inner.for.end: 17544 // CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 17545 // CHECK26: omp.loop.exit: 17546 // CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 17547 // CHECK26-NEXT: ret void 17548 // 17549 // 17550 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 17551 // CHECK26-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 17552 // CHECK26-NEXT: entry: 17553 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17554 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 17555 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 17556 // CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 17557 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 17558 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 17559 // CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 17560 // CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 17561 // CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 17562 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 17563 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 17564 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 17565 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17566 // CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 17567 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 17568 // CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 17569 // CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 17570 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 17571 // CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 17572 // CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 17573 // CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 17574 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 17575 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17576 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 17577 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 17578 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 17579 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 17580 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 17581 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 17582 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 17583 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 17584 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 17585 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 17586 // CHECK26-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 17587 // CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 17588 // CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 17589 // CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 17590 // CHECK26-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 17591 // CHECK26-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 17592 // CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 17593 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 17594 // CHECK26-NEXT: ret void 17595 // 17596 // 17597 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 17598 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 17599 // CHECK26-NEXT: entry: 17600 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17601 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17602 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17603 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 17604 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 17605 // CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 17606 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 17607 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 17608 // CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 17609 // CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 17610 // CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 17611 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 17612 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 17613 // CHECK26-NEXT: [[TMP:%.*]] = alloca i8, align 1 17614 // CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 17615 // CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 17616 // CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 17617 // CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 17618 // CHECK26-NEXT: [[IT:%.*]] = alloca i8, align 1 17619 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17620 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17621 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17622 // CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 17623 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 17624 // CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 17625 // CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 17626 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 17627 // CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 17628 // CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 17629 // CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 17630 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 17631 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17632 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 17633 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 17634 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 17635 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 17636 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 17637 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 17638 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 17639 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 17640 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 17641 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 17642 // CHECK26-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 17643 // CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 17644 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 17645 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 17646 // CHECK26-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 17647 // CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 17648 // CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 17649 // CHECK26-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 17650 // CHECK26: omp.dispatch.cond: 17651 // CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17652 // CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 17653 // CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 17654 // CHECK26: cond.true: 17655 // CHECK26-NEXT: br label [[COND_END:%.*]] 17656 // CHECK26: cond.false: 17657 // CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17658 // CHECK26-NEXT: br label [[COND_END]] 17659 // CHECK26: cond.end: 17660 // CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 17661 // CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 17662 // CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 17663 // CHECK26-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 17664 // CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17665 // CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17666 // CHECK26-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 17667 // CHECK26-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 17668 // CHECK26: omp.dispatch.body: 17669 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 17670 // CHECK26: omp.inner.for.cond: 17671 // CHECK26-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17672 // CHECK26-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17673 // CHECK26-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 17674 // CHECK26-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 17675 // CHECK26: omp.inner.for.body: 17676 // CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17677 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 17678 // CHECK26-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 17679 // CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 17680 // CHECK26-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 17681 // CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 17682 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 17683 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 17684 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 17685 // CHECK26-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 17686 // CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 17687 // CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 17688 // CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 17689 // CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 17690 // CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 17691 // CHECK26-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 17692 // CHECK26-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 17693 // CHECK26-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 17694 // CHECK26-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 17695 // CHECK26-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 17696 // CHECK26-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 17697 // CHECK26-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 17698 // CHECK26-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 17699 // CHECK26-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 17700 // CHECK26-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 17701 // CHECK26-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 17702 // CHECK26-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 17703 // CHECK26-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 17704 // CHECK26-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 17705 // CHECK26-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 17706 // CHECK26-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 17707 // CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 17708 // CHECK26-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 17709 // CHECK26-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 17710 // CHECK26-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 17711 // CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 17712 // CHECK26-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 17713 // CHECK26-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 17714 // CHECK26-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 17715 // CHECK26-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 17716 // CHECK26-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 17717 // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 17718 // CHECK26: omp.body.continue: 17719 // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 17720 // CHECK26: omp.inner.for.inc: 17721 // CHECK26-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 17722 // CHECK26-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 17723 // CHECK26-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 17724 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] 17725 // CHECK26: omp.inner.for.end: 17726 // CHECK26-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 17727 // CHECK26: omp.dispatch.inc: 17728 // CHECK26-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 17729 // CHECK26-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 17730 // CHECK26-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 17731 // CHECK26-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 17732 // CHECK26-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 17733 // CHECK26-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 17734 // CHECK26-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 17735 // CHECK26-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 17736 // CHECK26-NEXT: br label [[OMP_DISPATCH_COND]] 17737 // CHECK26: omp.dispatch.end: 17738 // CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 17739 // CHECK26-NEXT: ret void 17740 // 17741 // 17742 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 17743 // CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 17744 // CHECK26-NEXT: entry: 17745 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17746 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17747 // CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 17748 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 17749 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 17750 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 17751 // CHECK26-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 17752 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17753 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17754 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 17755 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 17756 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17757 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17758 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 17759 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 17760 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 17761 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 17762 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 17763 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 17764 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 17765 // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 17766 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 17767 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 17768 // CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 17769 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 17770 // CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 17771 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 17772 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 17773 // CHECK26-NEXT: ret void 17774 // 17775 // 17776 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 17777 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 17778 // CHECK26-NEXT: entry: 17779 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17780 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17781 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17782 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17783 // CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 17784 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 17785 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 17786 // CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 17787 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17788 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17789 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17790 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17791 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 17792 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 17793 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17794 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17795 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 17796 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 17797 // CHECK26-NEXT: ret void 17798 // 17799 // 17800 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 17801 // CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 17802 // CHECK26-NEXT: entry: 17803 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 17804 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 17805 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 17806 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 17807 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 17808 // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 17809 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 17810 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 17811 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 17812 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 17813 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 17814 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 17815 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 17816 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 17817 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 17818 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 17819 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 17820 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 17821 // CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 17822 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 17823 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 17824 // CHECK26-NEXT: ret void 17825 // 17826 // 17827 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 17828 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 17829 // CHECK26-NEXT: entry: 17830 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17831 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17832 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 17833 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 17834 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 17835 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 17836 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 17837 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 17838 // CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8 17839 // CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 17840 // CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 17841 // CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 17842 // CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 17843 // CHECK26-NEXT: [[IT:%.*]] = alloca i64, align 8 17844 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17845 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17846 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 17847 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 17848 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 17849 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 17850 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 17851 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 17852 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 17853 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 17854 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 17855 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 17856 // CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 17857 // CHECK26-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 17858 // CHECK26-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 17859 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 17860 // CHECK26-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 17861 // CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 17862 // CHECK26-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 17863 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17864 // CHECK26-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 17865 // CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 17866 // CHECK26: cond.true: 17867 // CHECK26-NEXT: br label [[COND_END:%.*]] 17868 // CHECK26: cond.false: 17869 // CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17870 // CHECK26-NEXT: br label [[COND_END]] 17871 // CHECK26: cond.end: 17872 // CHECK26-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 17873 // CHECK26-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 17874 // CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 17875 // CHECK26-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 17876 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 17877 // CHECK26: omp.inner.for.cond: 17878 // CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17879 // CHECK26-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17880 // CHECK26-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 17881 // CHECK26-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 17882 // CHECK26: omp.inner.for.body: 17883 // CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17884 // CHECK26-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 17885 // CHECK26-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 17886 // CHECK26-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 17887 // CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 17888 // CHECK26-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 17889 // CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 17890 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 17891 // CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 17892 // CHECK26-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 17893 // CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 17894 // CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 17895 // CHECK26-NEXT: store double [[INC]], double* [[A5]], align 8 17896 // CHECK26-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 17897 // CHECK26-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 17898 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 17899 // CHECK26-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 17900 // CHECK26-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 17901 // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 17902 // CHECK26: omp.body.continue: 17903 // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 17904 // CHECK26: omp.inner.for.inc: 17905 // CHECK26-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17906 // CHECK26-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 17907 // CHECK26-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 17908 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] 17909 // CHECK26: omp.inner.for.end: 17910 // CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 17911 // CHECK26: omp.loop.exit: 17912 // CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 17913 // CHECK26-NEXT: ret void 17914 // 17915 // 17916 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 17917 // CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 17918 // CHECK26-NEXT: entry: 17919 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17920 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17921 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 17922 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 17923 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 17924 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17925 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17926 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 17927 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17928 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17929 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 17930 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 17931 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 17932 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 17933 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 17934 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 17935 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 17936 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 17937 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 17938 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 17939 // CHECK26-NEXT: ret void 17940 // 17941 // 17942 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 17943 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 17944 // CHECK26-NEXT: entry: 17945 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17946 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17947 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17948 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17949 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 17950 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 17951 // CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8 17952 // CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 17953 // CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 17954 // CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 17955 // CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 17956 // CHECK26-NEXT: [[I:%.*]] = alloca i64, align 8 17957 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17958 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17959 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17960 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17961 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 17962 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17963 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17964 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 17965 // CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 17966 // CHECK26-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 17967 // CHECK26-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 17968 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 17969 // CHECK26-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 17970 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 17971 // CHECK26-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 17972 // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17973 // CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 17974 // CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 17975 // CHECK26: cond.true: 17976 // CHECK26-NEXT: br label [[COND_END:%.*]] 17977 // CHECK26: cond.false: 17978 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17979 // CHECK26-NEXT: br label [[COND_END]] 17980 // CHECK26: cond.end: 17981 // CHECK26-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 17982 // CHECK26-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 17983 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 17984 // CHECK26-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 17985 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 17986 // CHECK26: omp.inner.for.cond: 17987 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17988 // CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 17989 // CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 17990 // CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 17991 // CHECK26: omp.inner.for.body: 17992 // CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 17993 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 17994 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 17995 // CHECK26-NEXT: store i64 [[ADD]], i64* [[I]], align 8 17996 // CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 17997 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 17998 // CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 17999 // CHECK26-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 18000 // CHECK26-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 18001 // CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 18002 // CHECK26-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 18003 // CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 18004 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 18005 // CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 18006 // CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 18007 // CHECK26-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 18008 // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 18009 // CHECK26: omp.body.continue: 18010 // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 18011 // CHECK26: omp.inner.for.inc: 18012 // CHECK26-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18013 // CHECK26-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 18014 // CHECK26-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 18015 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] 18016 // CHECK26: omp.inner.for.end: 18017 // CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 18018 // CHECK26: omp.loop.exit: 18019 // CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 18020 // CHECK26-NEXT: ret void 18021 // 18022 // 18023 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 18024 // CHECK27-SAME: () #[[ATTR0:[0-9]+]] { 18025 // CHECK27-NEXT: entry: 18026 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 18027 // CHECK27-NEXT: ret void 18028 // 18029 // 18030 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. 18031 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 18032 // CHECK27-NEXT: entry: 18033 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18034 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18035 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 18036 // CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 18037 // CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 18038 // CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 18039 // CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 18040 // CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 18041 // CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 18042 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18043 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18044 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 18045 // CHECK27-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 18046 // CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 18047 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 18048 // CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 18049 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 18050 // CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 18051 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18052 // CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 18053 // CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 18054 // CHECK27: cond.true: 18055 // CHECK27-NEXT: br label [[COND_END:%.*]] 18056 // CHECK27: cond.false: 18057 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18058 // CHECK27-NEXT: br label [[COND_END]] 18059 // CHECK27: cond.end: 18060 // CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 18061 // CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 18062 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 18063 // CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 18064 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 18065 // CHECK27: omp.inner.for.cond: 18066 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18067 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18068 // CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 18069 // CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 18070 // CHECK27: omp.inner.for.body: 18071 // CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18072 // CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 18073 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 18074 // CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 18075 // CHECK27-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 18076 // CHECK27-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 18077 // CHECK27-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 18078 // CHECK27: .cancel.exit: 18079 // CHECK27-NEXT: br label [[CANCEL_EXIT:%.*]] 18080 // CHECK27: .cancel.continue: 18081 // CHECK27-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 18082 // CHECK27-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 18083 // CHECK27-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 18084 // CHECK27: .cancel.exit2: 18085 // CHECK27-NEXT: br label [[CANCEL_EXIT]] 18086 // CHECK27: .cancel.continue3: 18087 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 18088 // CHECK27: omp.body.continue: 18089 // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 18090 // CHECK27: omp.inner.for.inc: 18091 // CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18092 // CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 18093 // CHECK27-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 18094 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] 18095 // CHECK27: omp.inner.for.end: 18096 // CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 18097 // CHECK27: omp.loop.exit: 18098 // CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 18099 // CHECK27-NEXT: br label [[CANCEL_CONT:%.*]] 18100 // CHECK27: cancel.cont: 18101 // CHECK27-NEXT: ret void 18102 // CHECK27: cancel.exit: 18103 // CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 18104 // CHECK27-NEXT: br label [[CANCEL_CONT]] 18105 // 18106 // 18107 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 18108 // CHECK27-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 18109 // CHECK27-NEXT: entry: 18110 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18111 // CHECK27-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 18112 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18113 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 18114 // CHECK27-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 18115 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 18116 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18117 // CHECK27-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 18118 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18119 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18120 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 18121 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 18122 // CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 18123 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 18124 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 18125 // CHECK27-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 18126 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 18127 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 18128 // CHECK27-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 18129 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 18130 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 18131 // CHECK27-NEXT: ret void 18132 // 18133 // 18134 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 18135 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 18136 // CHECK27-NEXT: entry: 18137 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18138 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18139 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18140 // CHECK27-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 18141 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18142 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 18143 // CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4 18144 // CHECK27-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 18145 // CHECK27-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 18146 // CHECK27-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 18147 // CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 18148 // CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 18149 // CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 18150 // CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 18151 // CHECK27-NEXT: [[IT:%.*]] = alloca i64, align 8 18152 // CHECK27-NEXT: [[LIN2:%.*]] = alloca i32, align 4 18153 // CHECK27-NEXT: [[A3:%.*]] = alloca i32, align 4 18154 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18155 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18156 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18157 // CHECK27-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 18158 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18159 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18160 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 18161 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 18162 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 18163 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 18164 // CHECK27-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 18165 // CHECK27-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 18166 // CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 18167 // CHECK27-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 18168 // CHECK27-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 18169 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 18170 // CHECK27-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 18171 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 18172 // CHECK27-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 18173 // CHECK27-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 18174 // CHECK27-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18175 // CHECK27-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 18176 // CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 18177 // CHECK27: cond.true: 18178 // CHECK27-NEXT: br label [[COND_END:%.*]] 18179 // CHECK27: cond.false: 18180 // CHECK27-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18181 // CHECK27-NEXT: br label [[COND_END]] 18182 // CHECK27: cond.end: 18183 // CHECK27-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 18184 // CHECK27-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 18185 // CHECK27-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 18186 // CHECK27-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 18187 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 18188 // CHECK27: omp.inner.for.cond: 18189 // CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18190 // CHECK27-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18191 // CHECK27-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 18192 // CHECK27-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 18193 // CHECK27: omp.inner.for.body: 18194 // CHECK27-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18195 // CHECK27-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 18196 // CHECK27-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 18197 // CHECK27-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 18198 // CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 18199 // CHECK27-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 18200 // CHECK27-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18201 // CHECK27-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 18202 // CHECK27-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 18203 // CHECK27-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 18204 // CHECK27-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 18205 // CHECK27-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 18206 // CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 18207 // CHECK27-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 18208 // CHECK27-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18209 // CHECK27-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 18210 // CHECK27-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 18211 // CHECK27-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 18212 // CHECK27-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 18213 // CHECK27-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 18214 // CHECK27-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 18215 // CHECK27-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 18216 // CHECK27-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 18217 // CHECK27-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 18218 // CHECK27-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 18219 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 18220 // CHECK27: omp.body.continue: 18221 // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 18222 // CHECK27: omp.inner.for.inc: 18223 // CHECK27-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18224 // CHECK27-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 18225 // CHECK27-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 18226 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] 18227 // CHECK27: omp.inner.for.end: 18228 // CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 18229 // CHECK27: omp.loop.exit: 18230 // CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 18231 // CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 18232 // CHECK27-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 18233 // CHECK27-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 18234 // CHECK27: .omp.linear.pu: 18235 // CHECK27-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 18236 // CHECK27-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 18237 // CHECK27-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 18238 // CHECK27-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 18239 // CHECK27-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 18240 // CHECK27: .omp.linear.pu.done: 18241 // CHECK27-NEXT: ret void 18242 // 18243 // 18244 // CHECK27-LABEL: define {{[^@]+}}@_Z7get_valv 18245 // CHECK27-SAME: () #[[ATTR3:[0-9]+]] { 18246 // CHECK27-NEXT: entry: 18247 // CHECK27-NEXT: ret i64 0 18248 // 18249 // 18250 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 18251 // CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 18252 // CHECK27-NEXT: entry: 18253 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18254 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18255 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 18256 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 18257 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18258 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18259 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18260 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 18261 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 18262 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 18263 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 18264 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 18265 // CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 18266 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 18267 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 18268 // CHECK27-NEXT: ret void 18269 // 18270 // 18271 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 18272 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 18273 // CHECK27-NEXT: entry: 18274 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18275 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18276 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18277 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18278 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 18279 // CHECK27-NEXT: [[TMP:%.*]] = alloca i16, align 2 18280 // CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 18281 // CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 18282 // CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 18283 // CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 18284 // CHECK27-NEXT: [[IT:%.*]] = alloca i16, align 2 18285 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18286 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18287 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18288 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18289 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18290 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 18291 // CHECK27-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 18292 // CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 18293 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 18294 // CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 18295 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 18296 // CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 18297 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18298 // CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 18299 // CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 18300 // CHECK27: cond.true: 18301 // CHECK27-NEXT: br label [[COND_END:%.*]] 18302 // CHECK27: cond.false: 18303 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18304 // CHECK27-NEXT: br label [[COND_END]] 18305 // CHECK27: cond.end: 18306 // CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 18307 // CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 18308 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 18309 // CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 18310 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 18311 // CHECK27: omp.inner.for.cond: 18312 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18313 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18314 // CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 18315 // CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 18316 // CHECK27: omp.inner.for.body: 18317 // CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18318 // CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 18319 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 18320 // CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 18321 // CHECK27-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 18322 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 18323 // CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 18324 // CHECK27-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 18325 // CHECK27-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 18326 // CHECK27-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 18327 // CHECK27-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 18328 // CHECK27-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 18329 // CHECK27-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 18330 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 18331 // CHECK27: omp.body.continue: 18332 // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 18333 // CHECK27: omp.inner.for.inc: 18334 // CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18335 // CHECK27-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 18336 // CHECK27-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 18337 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] 18338 // CHECK27: omp.inner.for.end: 18339 // CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 18340 // CHECK27: omp.loop.exit: 18341 // CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 18342 // CHECK27-NEXT: ret void 18343 // 18344 // 18345 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 18346 // CHECK27-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 18347 // CHECK27-NEXT: entry: 18348 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18349 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 18350 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 18351 // CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 18352 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 18353 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 18354 // CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 18355 // CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 18356 // CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 18357 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 18358 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 18359 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 18360 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18361 // CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 18362 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 18363 // CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 18364 // CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 18365 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 18366 // CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 18367 // CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 18368 // CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 18369 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 18370 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 18371 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 18372 // CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 18373 // CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 18374 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 18375 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 18376 // CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 18377 // CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 18378 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 18379 // CHECK27-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 18380 // CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 18381 // CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 18382 // CHECK27-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 18383 // CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 18384 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 18385 // CHECK27-NEXT: ret void 18386 // 18387 // 18388 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 18389 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 18390 // CHECK27-NEXT: entry: 18391 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18392 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18393 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18394 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 18395 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 18396 // CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 18397 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 18398 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 18399 // CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 18400 // CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 18401 // CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 18402 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 18403 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 18404 // CHECK27-NEXT: [[TMP:%.*]] = alloca i8, align 1 18405 // CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 18406 // CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 18407 // CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 18408 // CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 18409 // CHECK27-NEXT: [[IT:%.*]] = alloca i8, align 1 18410 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18411 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18412 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18413 // CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 18414 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 18415 // CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 18416 // CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 18417 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 18418 // CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 18419 // CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 18420 // CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 18421 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 18422 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 18423 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 18424 // CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 18425 // CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 18426 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 18427 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 18428 // CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 18429 // CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 18430 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 18431 // CHECK27-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 18432 // CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 18433 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 18434 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 18435 // CHECK27-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 18436 // CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 18437 // CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 18438 // CHECK27-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 18439 // CHECK27: omp.dispatch.cond: 18440 // CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18441 // CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 18442 // CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 18443 // CHECK27: cond.true: 18444 // CHECK27-NEXT: br label [[COND_END:%.*]] 18445 // CHECK27: cond.false: 18446 // CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18447 // CHECK27-NEXT: br label [[COND_END]] 18448 // CHECK27: cond.end: 18449 // CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 18450 // CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 18451 // CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 18452 // CHECK27-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 18453 // CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18454 // CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18455 // CHECK27-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 18456 // CHECK27-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 18457 // CHECK27: omp.dispatch.body: 18458 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 18459 // CHECK27: omp.inner.for.cond: 18460 // CHECK27-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18461 // CHECK27-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18462 // CHECK27-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 18463 // CHECK27-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 18464 // CHECK27: omp.inner.for.body: 18465 // CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18466 // CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 18467 // CHECK27-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 18468 // CHECK27-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 18469 // CHECK27-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 18470 // CHECK27-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 18471 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 18472 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 18473 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 18474 // CHECK27-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 18475 // CHECK27-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 18476 // CHECK27-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 18477 // CHECK27-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 18478 // CHECK27-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 18479 // CHECK27-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 18480 // CHECK27-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 18481 // CHECK27-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 18482 // CHECK27-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 18483 // CHECK27-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 18484 // CHECK27-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 18485 // CHECK27-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 18486 // CHECK27-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 18487 // CHECK27-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 18488 // CHECK27-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 18489 // CHECK27-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 18490 // CHECK27-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 18491 // CHECK27-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 18492 // CHECK27-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 18493 // CHECK27-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 18494 // CHECK27-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 18495 // CHECK27-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 18496 // CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 18497 // CHECK27-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 18498 // CHECK27-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 18499 // CHECK27-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 18500 // CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 18501 // CHECK27-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 18502 // CHECK27-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 18503 // CHECK27-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 18504 // CHECK27-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 18505 // CHECK27-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 18506 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 18507 // CHECK27: omp.body.continue: 18508 // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 18509 // CHECK27: omp.inner.for.inc: 18510 // CHECK27-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18511 // CHECK27-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 18512 // CHECK27-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 18513 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] 18514 // CHECK27: omp.inner.for.end: 18515 // CHECK27-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 18516 // CHECK27: omp.dispatch.inc: 18517 // CHECK27-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 18518 // CHECK27-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 18519 // CHECK27-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 18520 // CHECK27-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 18521 // CHECK27-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18522 // CHECK27-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 18523 // CHECK27-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 18524 // CHECK27-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 18525 // CHECK27-NEXT: br label [[OMP_DISPATCH_COND]] 18526 // CHECK27: omp.dispatch.end: 18527 // CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 18528 // CHECK27-NEXT: ret void 18529 // 18530 // 18531 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 18532 // CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 18533 // CHECK27-NEXT: entry: 18534 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18535 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18536 // CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 18537 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 18538 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 18539 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 18540 // CHECK27-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 18541 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18542 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18543 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 18544 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 18545 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18546 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 18547 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 18548 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 18549 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 18550 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 18551 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 18552 // CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 18553 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 18554 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 18555 // CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 18556 // CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 18557 // CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 18558 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 18559 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 18560 // CHECK27-NEXT: ret void 18561 // 18562 // 18563 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 18564 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 18565 // CHECK27-NEXT: entry: 18566 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18567 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18568 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18569 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18570 // CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 18571 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 18572 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 18573 // CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 18574 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18575 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18576 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18577 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18578 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 18579 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 18580 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18581 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 18582 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 18583 // CHECK27-NEXT: ret void 18584 // 18585 // 18586 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 18587 // CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 18588 // CHECK27-NEXT: entry: 18589 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 18590 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 18591 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 18592 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 18593 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 18594 // CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 18595 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 18596 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 18597 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 18598 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 18599 // CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 18600 // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 18601 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 18602 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 18603 // CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 18604 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 18605 // CHECK27-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 18606 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 18607 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 18608 // CHECK27-NEXT: ret void 18609 // 18610 // 18611 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 18612 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 18613 // CHECK27-NEXT: entry: 18614 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18615 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18616 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 18617 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 18618 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 18619 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 18620 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 18621 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 18622 // CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4 18623 // CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 18624 // CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 18625 // CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 18626 // CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 18627 // CHECK27-NEXT: [[IT:%.*]] = alloca i64, align 8 18628 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18629 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18630 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 18631 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 18632 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 18633 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 18634 // CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 18635 // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 18636 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 18637 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 18638 // CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 18639 // CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 18640 // CHECK27-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 18641 // CHECK27-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 18642 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 18643 // CHECK27-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 18644 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 18645 // CHECK27-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 18646 // CHECK27-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18647 // CHECK27-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 18648 // CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 18649 // CHECK27: cond.true: 18650 // CHECK27-NEXT: br label [[COND_END:%.*]] 18651 // CHECK27: cond.false: 18652 // CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18653 // CHECK27-NEXT: br label [[COND_END]] 18654 // CHECK27: cond.end: 18655 // CHECK27-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 18656 // CHECK27-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 18657 // CHECK27-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 18658 // CHECK27-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 18659 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 18660 // CHECK27: omp.inner.for.cond: 18661 // CHECK27-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18662 // CHECK27-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18663 // CHECK27-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 18664 // CHECK27-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 18665 // CHECK27: omp.inner.for.body: 18666 // CHECK27-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18667 // CHECK27-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 18668 // CHECK27-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 18669 // CHECK27-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 18670 // CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 18671 // CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 18672 // CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 18673 // CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 18674 // CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 18675 // CHECK27-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 18676 // CHECK27-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 18677 // CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 18678 // CHECK27-NEXT: store double [[INC]], double* [[A4]], align 4 18679 // CHECK27-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 18680 // CHECK27-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 18681 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 18682 // CHECK27-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 18683 // CHECK27-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 18684 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 18685 // CHECK27: omp.body.continue: 18686 // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 18687 // CHECK27: omp.inner.for.inc: 18688 // CHECK27-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18689 // CHECK27-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 18690 // CHECK27-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 18691 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] 18692 // CHECK27: omp.inner.for.end: 18693 // CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 18694 // CHECK27: omp.loop.exit: 18695 // CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 18696 // CHECK27-NEXT: ret void 18697 // 18698 // 18699 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 18700 // CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 18701 // CHECK27-NEXT: entry: 18702 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18703 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18704 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 18705 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 18706 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 18707 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18708 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18709 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 18710 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18711 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 18712 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 18713 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 18714 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 18715 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 18716 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 18717 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 18718 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 18719 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 18720 // CHECK27-NEXT: ret void 18721 // 18722 // 18723 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 18724 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 18725 // CHECK27-NEXT: entry: 18726 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18727 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18728 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18729 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18730 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 18731 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 18732 // CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4 18733 // CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 18734 // CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 18735 // CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 18736 // CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 18737 // CHECK27-NEXT: [[I:%.*]] = alloca i64, align 8 18738 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18739 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18740 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18741 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18742 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 18743 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18744 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 18745 // CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 18746 // CHECK27-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 18747 // CHECK27-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 18748 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 18749 // CHECK27-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 18750 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 18751 // CHECK27-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 18752 // CHECK27-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18753 // CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 18754 // CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 18755 // CHECK27: cond.true: 18756 // CHECK27-NEXT: br label [[COND_END:%.*]] 18757 // CHECK27: cond.false: 18758 // CHECK27-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18759 // CHECK27-NEXT: br label [[COND_END]] 18760 // CHECK27: cond.end: 18761 // CHECK27-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 18762 // CHECK27-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 18763 // CHECK27-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 18764 // CHECK27-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 18765 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 18766 // CHECK27: omp.inner.for.cond: 18767 // CHECK27-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18768 // CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18769 // CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 18770 // CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 18771 // CHECK27: omp.inner.for.body: 18772 // CHECK27-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18773 // CHECK27-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 18774 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 18775 // CHECK27-NEXT: store i64 [[ADD]], i64* [[I]], align 8 18776 // CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 18777 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 18778 // CHECK27-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 18779 // CHECK27-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 18780 // CHECK27-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 18781 // CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 18782 // CHECK27-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 18783 // CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 18784 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 18785 // CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 18786 // CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 18787 // CHECK27-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 18788 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 18789 // CHECK27: omp.body.continue: 18790 // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 18791 // CHECK27: omp.inner.for.inc: 18792 // CHECK27-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18793 // CHECK27-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 18794 // CHECK27-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 18795 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] 18796 // CHECK27: omp.inner.for.end: 18797 // CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 18798 // CHECK27: omp.loop.exit: 18799 // CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 18800 // CHECK27-NEXT: ret void 18801 // 18802 // 18803 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 18804 // CHECK28-SAME: () #[[ATTR0:[0-9]+]] { 18805 // CHECK28-NEXT: entry: 18806 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 18807 // CHECK28-NEXT: ret void 18808 // 18809 // 18810 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. 18811 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 18812 // CHECK28-NEXT: entry: 18813 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18814 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18815 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 18816 // CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 18817 // CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 18818 // CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 18819 // CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 18820 // CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 18821 // CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4 18822 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18823 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18824 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 18825 // CHECK28-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 18826 // CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 18827 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 18828 // CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 18829 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 18830 // CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 18831 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18832 // CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 18833 // CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 18834 // CHECK28: cond.true: 18835 // CHECK28-NEXT: br label [[COND_END:%.*]] 18836 // CHECK28: cond.false: 18837 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18838 // CHECK28-NEXT: br label [[COND_END]] 18839 // CHECK28: cond.end: 18840 // CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 18841 // CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 18842 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 18843 // CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 18844 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 18845 // CHECK28: omp.inner.for.cond: 18846 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18847 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 18848 // CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 18849 // CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 18850 // CHECK28: omp.inner.for.body: 18851 // CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18852 // CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 18853 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 18854 // CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 18855 // CHECK28-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 18856 // CHECK28-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 18857 // CHECK28-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 18858 // CHECK28: .cancel.exit: 18859 // CHECK28-NEXT: br label [[CANCEL_EXIT:%.*]] 18860 // CHECK28: .cancel.continue: 18861 // CHECK28-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 18862 // CHECK28-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 18863 // CHECK28-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 18864 // CHECK28: .cancel.exit2: 18865 // CHECK28-NEXT: br label [[CANCEL_EXIT]] 18866 // CHECK28: .cancel.continue3: 18867 // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 18868 // CHECK28: omp.body.continue: 18869 // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 18870 // CHECK28: omp.inner.for.inc: 18871 // CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 18872 // CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 18873 // CHECK28-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 18874 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] 18875 // CHECK28: omp.inner.for.end: 18876 // CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 18877 // CHECK28: omp.loop.exit: 18878 // CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 18879 // CHECK28-NEXT: br label [[CANCEL_CONT:%.*]] 18880 // CHECK28: cancel.cont: 18881 // CHECK28-NEXT: ret void 18882 // CHECK28: cancel.exit: 18883 // CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 18884 // CHECK28-NEXT: br label [[CANCEL_CONT]] 18885 // 18886 // 18887 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 18888 // CHECK28-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 18889 // CHECK28-NEXT: entry: 18890 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18891 // CHECK28-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 18892 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18893 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 18894 // CHECK28-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 18895 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 18896 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18897 // CHECK28-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 18898 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18899 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18900 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 18901 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 18902 // CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 18903 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 18904 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 18905 // CHECK28-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 18906 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 18907 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 18908 // CHECK28-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 18909 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 18910 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 18911 // CHECK28-NEXT: ret void 18912 // 18913 // 18914 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 18915 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 18916 // CHECK28-NEXT: entry: 18917 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18918 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18919 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18920 // CHECK28-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 18921 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18922 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 18923 // CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4 18924 // CHECK28-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 18925 // CHECK28-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 18926 // CHECK28-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 18927 // CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 18928 // CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 18929 // CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 18930 // CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 18931 // CHECK28-NEXT: [[IT:%.*]] = alloca i64, align 8 18932 // CHECK28-NEXT: [[LIN2:%.*]] = alloca i32, align 4 18933 // CHECK28-NEXT: [[A3:%.*]] = alloca i32, align 4 18934 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18935 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18936 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18937 // CHECK28-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 18938 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18939 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18940 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 18941 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 18942 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 18943 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 18944 // CHECK28-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 18945 // CHECK28-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 18946 // CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 18947 // CHECK28-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 18948 // CHECK28-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 18949 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 18950 // CHECK28-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 18951 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 18952 // CHECK28-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 18953 // CHECK28-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 18954 // CHECK28-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18955 // CHECK28-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 18956 // CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 18957 // CHECK28: cond.true: 18958 // CHECK28-NEXT: br label [[COND_END:%.*]] 18959 // CHECK28: cond.false: 18960 // CHECK28-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18961 // CHECK28-NEXT: br label [[COND_END]] 18962 // CHECK28: cond.end: 18963 // CHECK28-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 18964 // CHECK28-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 18965 // CHECK28-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 18966 // CHECK28-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 18967 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 18968 // CHECK28: omp.inner.for.cond: 18969 // CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18970 // CHECK28-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 18971 // CHECK28-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 18972 // CHECK28-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 18973 // CHECK28: omp.inner.for.body: 18974 // CHECK28-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18975 // CHECK28-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 18976 // CHECK28-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 18977 // CHECK28-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 18978 // CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 18979 // CHECK28-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 18980 // CHECK28-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18981 // CHECK28-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 18982 // CHECK28-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 18983 // CHECK28-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 18984 // CHECK28-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 18985 // CHECK28-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 18986 // CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 18987 // CHECK28-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 18988 // CHECK28-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 18989 // CHECK28-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 18990 // CHECK28-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 18991 // CHECK28-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 18992 // CHECK28-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 18993 // CHECK28-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 18994 // CHECK28-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 18995 // CHECK28-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 18996 // CHECK28-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 18997 // CHECK28-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 18998 // CHECK28-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 18999 // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 19000 // CHECK28: omp.body.continue: 19001 // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 19002 // CHECK28: omp.inner.for.inc: 19003 // CHECK28-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 19004 // CHECK28-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 19005 // CHECK28-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 19006 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] 19007 // CHECK28: omp.inner.for.end: 19008 // CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 19009 // CHECK28: omp.loop.exit: 19010 // CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 19011 // CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 19012 // CHECK28-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 19013 // CHECK28-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 19014 // CHECK28: .omp.linear.pu: 19015 // CHECK28-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 19016 // CHECK28-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 19017 // CHECK28-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 19018 // CHECK28-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 19019 // CHECK28-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 19020 // CHECK28: .omp.linear.pu.done: 19021 // CHECK28-NEXT: ret void 19022 // 19023 // 19024 // CHECK28-LABEL: define {{[^@]+}}@_Z7get_valv 19025 // CHECK28-SAME: () #[[ATTR3:[0-9]+]] { 19026 // CHECK28-NEXT: entry: 19027 // CHECK28-NEXT: ret i64 0 19028 // 19029 // 19030 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 19031 // CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 19032 // CHECK28-NEXT: entry: 19033 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 19034 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 19035 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 19036 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 19037 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 19038 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 19039 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 19040 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 19041 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 19042 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 19043 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 19044 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 19045 // CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 19046 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 19047 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 19048 // CHECK28-NEXT: ret void 19049 // 19050 // 19051 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 19052 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 19053 // CHECK28-NEXT: entry: 19054 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 19055 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 19056 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 19057 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 19058 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 19059 // CHECK28-NEXT: [[TMP:%.*]] = alloca i16, align 2 19060 // CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 19061 // CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 19062 // CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 19063 // CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 19064 // CHECK28-NEXT: [[IT:%.*]] = alloca i16, align 2 19065 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 19066 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 19067 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 19068 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 19069 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 19070 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 19071 // CHECK28-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 19072 // CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 19073 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 19074 // CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 19075 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 19076 // CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 19077 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 19078 // CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 19079 // CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 19080 // CHECK28: cond.true: 19081 // CHECK28-NEXT: br label [[COND_END:%.*]] 19082 // CHECK28: cond.false: 19083 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 19084 // CHECK28-NEXT: br label [[COND_END]] 19085 // CHECK28: cond.end: 19086 // CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 19087 // CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 19088 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 19089 // CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 19090 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 19091 // CHECK28: omp.inner.for.cond: 19092 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 19093 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 19094 // CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 19095 // CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 19096 // CHECK28: omp.inner.for.body: 19097 // CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 19098 // CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 19099 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 19100 // CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 19101 // CHECK28-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 19102 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 19103 // CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 19104 // CHECK28-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 19105 // CHECK28-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 19106 // CHECK28-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 19107 // CHECK28-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 19108 // CHECK28-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 19109 // CHECK28-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 19110 // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 19111 // CHECK28: omp.body.continue: 19112 // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 19113 // CHECK28: omp.inner.for.inc: 19114 // CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 19115 // CHECK28-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 19116 // CHECK28-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 19117 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] 19118 // CHECK28: omp.inner.for.end: 19119 // CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 19120 // CHECK28: omp.loop.exit: 19121 // CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 19122 // CHECK28-NEXT: ret void 19123 // 19124 // 19125 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 19126 // CHECK28-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 19127 // CHECK28-NEXT: entry: 19128 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 19129 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 19130 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 19131 // CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 19132 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 19133 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 19134 // CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 19135 // CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 19136 // CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 19137 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 19138 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 19139 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 19140 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 19141 // CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 19142 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 19143 // CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 19144 // CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 19145 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 19146 // CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 19147 // CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 19148 // CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 19149 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 19150 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 19151 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 19152 // CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 19153 // CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 19154 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 19155 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 19156 // CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 19157 // CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 19158 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 19159 // CHECK28-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 19160 // CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 19161 // CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 19162 // CHECK28-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 19163 // CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 19164 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 19165 // CHECK28-NEXT: ret void 19166 // 19167 // 19168 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 19169 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 19170 // CHECK28-NEXT: entry: 19171 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 19172 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 19173 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 19174 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 19175 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 19176 // CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 19177 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 19178 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 19179 // CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 19180 // CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 19181 // CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 19182 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 19183 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 19184 // CHECK28-NEXT: [[TMP:%.*]] = alloca i8, align 1 19185 // CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 19186 // CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 19187 // CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 19188 // CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 19189 // CHECK28-NEXT: [[IT:%.*]] = alloca i8, align 1 19190 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 19191 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 19192 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 19193 // CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 19194 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 19195 // CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 19196 // CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 19197 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 19198 // CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 19199 // CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 19200 // CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 19201 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 19202 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 19203 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 19204 // CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 19205 // CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 19206 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 19207 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 19208 // CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 19209 // CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 19210 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 19211 // CHECK28-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 19212 // CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 19213 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 19214 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 19215 // CHECK28-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 19216 // CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 19217 // CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 19218 // CHECK28-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 19219 // CHECK28: omp.dispatch.cond: 19220 // CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 19221 // CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 19222 // CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 19223 // CHECK28: cond.true: 19224 // CHECK28-NEXT: br label [[COND_END:%.*]] 19225 // CHECK28: cond.false: 19226 // CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 19227 // CHECK28-NEXT: br label [[COND_END]] 19228 // CHECK28: cond.end: 19229 // CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 19230 // CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 19231 // CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 19232 // CHECK28-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 19233 // CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 19234 // CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 19235 // CHECK28-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 19236 // CHECK28-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 19237 // CHECK28: omp.dispatch.body: 19238 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 19239 // CHECK28: omp.inner.for.cond: 19240 // CHECK28-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 19241 // CHECK28-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 19242 // CHECK28-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 19243 // CHECK28-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 19244 // CHECK28: omp.inner.for.body: 19245 // CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 19246 // CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 19247 // CHECK28-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 19248 // CHECK28-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 19249 // CHECK28-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 19250 // CHECK28-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 19251 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 19252 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 19253 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 19254 // CHECK28-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 19255 // CHECK28-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 19256 // CHECK28-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 19257 // CHECK28-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 19258 // CHECK28-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 19259 // CHECK28-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 19260 // CHECK28-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 19261 // CHECK28-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 19262 // CHECK28-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 19263 // CHECK28-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 19264 // CHECK28-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 19265 // CHECK28-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 19266 // CHECK28-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 19267 // CHECK28-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 19268 // CHECK28-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 19269 // CHECK28-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 19270 // CHECK28-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 19271 // CHECK28-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 19272 // CHECK28-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 19273 // CHECK28-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 19274 // CHECK28-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 19275 // CHECK28-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 19276 // CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 19277 // CHECK28-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 19278 // CHECK28-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 19279 // CHECK28-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 19280 // CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 19281 // CHECK28-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 19282 // CHECK28-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 19283 // CHECK28-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 19284 // CHECK28-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 19285 // CHECK28-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 19286 // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 19287 // CHECK28: omp.body.continue: 19288 // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 19289 // CHECK28: omp.inner.for.inc: 19290 // CHECK28-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 19291 // CHECK28-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 19292 // CHECK28-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 19293 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] 19294 // CHECK28: omp.inner.for.end: 19295 // CHECK28-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 19296 // CHECK28: omp.dispatch.inc: 19297 // CHECK28-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 19298 // CHECK28-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 19299 // CHECK28-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 19300 // CHECK28-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 19301 // CHECK28-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 19302 // CHECK28-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 19303 // CHECK28-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 19304 // CHECK28-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 19305 // CHECK28-NEXT: br label [[OMP_DISPATCH_COND]] 19306 // CHECK28: omp.dispatch.end: 19307 // CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 19308 // CHECK28-NEXT: ret void 19309 // 19310 // 19311 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 19312 // CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 19313 // CHECK28-NEXT: entry: 19314 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 19315 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 19316 // CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 19317 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 19318 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 19319 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 19320 // CHECK28-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 19321 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 19322 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 19323 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 19324 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 19325 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 19326 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 19327 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 19328 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 19329 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 19330 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 19331 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 19332 // CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 19333 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 19334 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 19335 // CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 19336 // CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 19337 // CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 19338 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 19339 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 19340 // CHECK28-NEXT: ret void 19341 // 19342 // 19343 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 19344 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 19345 // CHECK28-NEXT: entry: 19346 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 19347 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 19348 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 19349 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 19350 // CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 19351 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 19352 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 19353 // CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 19354 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 19355 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 19356 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 19357 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 19358 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 19359 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 19360 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 19361 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 19362 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 19363 // CHECK28-NEXT: ret void 19364 // 19365 // 19366 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 19367 // CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 19368 // CHECK28-NEXT: entry: 19369 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 19370 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 19371 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 19372 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 19373 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 19374 // CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 19375 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 19376 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 19377 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 19378 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 19379 // CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 19380 // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 19381 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 19382 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 19383 // CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 19384 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 19385 // CHECK28-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 19386 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 19387 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 19388 // CHECK28-NEXT: ret void 19389 // 19390 // 19391 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 19392 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 19393 // CHECK28-NEXT: entry: 19394 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 19395 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 19396 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 19397 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 19398 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 19399 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 19400 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 19401 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 19402 // CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4 19403 // CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 19404 // CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 19405 // CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 19406 // CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 19407 // CHECK28-NEXT: [[IT:%.*]] = alloca i64, align 8 19408 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 19409 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 19410 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 19411 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 19412 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 19413 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 19414 // CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 19415 // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 19416 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 19417 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 19418 // CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 19419 // CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 19420 // CHECK28-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 19421 // CHECK28-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 19422 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 19423 // CHECK28-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 19424 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 19425 // CHECK28-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 19426 // CHECK28-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 19427 // CHECK28-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 19428 // CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 19429 // CHECK28: cond.true: 19430 // CHECK28-NEXT: br label [[COND_END:%.*]] 19431 // CHECK28: cond.false: 19432 // CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 19433 // CHECK28-NEXT: br label [[COND_END]] 19434 // CHECK28: cond.end: 19435 // CHECK28-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 19436 // CHECK28-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 19437 // CHECK28-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 19438 // CHECK28-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 19439 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 19440 // CHECK28: omp.inner.for.cond: 19441 // CHECK28-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 19442 // CHECK28-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 19443 // CHECK28-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 19444 // CHECK28-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 19445 // CHECK28: omp.inner.for.body: 19446 // CHECK28-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 19447 // CHECK28-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 19448 // CHECK28-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 19449 // CHECK28-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 19450 // CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 19451 // CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 19452 // CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 19453 // CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 19454 // CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 19455 // CHECK28-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 19456 // CHECK28-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 19457 // CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 19458 // CHECK28-NEXT: store double [[INC]], double* [[A4]], align 4 19459 // CHECK28-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 19460 // CHECK28-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 19461 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 19462 // CHECK28-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 19463 // CHECK28-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 19464 // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 19465 // CHECK28: omp.body.continue: 19466 // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 19467 // CHECK28: omp.inner.for.inc: 19468 // CHECK28-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 19469 // CHECK28-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 19470 // CHECK28-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 19471 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] 19472 // CHECK28: omp.inner.for.end: 19473 // CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 19474 // CHECK28: omp.loop.exit: 19475 // CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 19476 // CHECK28-NEXT: ret void 19477 // 19478 // 19479 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 19480 // CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 19481 // CHECK28-NEXT: entry: 19482 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 19483 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 19484 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 19485 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 19486 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 19487 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 19488 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 19489 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 19490 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 19491 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 19492 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 19493 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 19494 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 19495 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 19496 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 19497 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 19498 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 19499 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 19500 // CHECK28-NEXT: ret void 19501 // 19502 // 19503 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 19504 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 19505 // CHECK28-NEXT: entry: 19506 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 19507 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 19508 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 19509 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 19510 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 19511 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 19512 // CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4 19513 // CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 19514 // CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 19515 // CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 19516 // CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 19517 // CHECK28-NEXT: [[I:%.*]] = alloca i64, align 8 19518 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 19519 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 19520 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 19521 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 19522 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 19523 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 19524 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 19525 // CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 19526 // CHECK28-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 19527 // CHECK28-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 19528 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 19529 // CHECK28-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 19530 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 19531 // CHECK28-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 19532 // CHECK28-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 19533 // CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 19534 // CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 19535 // CHECK28: cond.true: 19536 // CHECK28-NEXT: br label [[COND_END:%.*]] 19537 // CHECK28: cond.false: 19538 // CHECK28-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 19539 // CHECK28-NEXT: br label [[COND_END]] 19540 // CHECK28: cond.end: 19541 // CHECK28-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 19542 // CHECK28-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 19543 // CHECK28-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 19544 // CHECK28-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 19545 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 19546 // CHECK28: omp.inner.for.cond: 19547 // CHECK28-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 19548 // CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 19549 // CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 19550 // CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 19551 // CHECK28: omp.inner.for.body: 19552 // CHECK28-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 19553 // CHECK28-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 19554 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 19555 // CHECK28-NEXT: store i64 [[ADD]], i64* [[I]], align 8 19556 // CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 19557 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 19558 // CHECK28-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 19559 // CHECK28-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 19560 // CHECK28-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 19561 // CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 19562 // CHECK28-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 19563 // CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 19564 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 19565 // CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 19566 // CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 19567 // CHECK28-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 19568 // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 19569 // CHECK28: omp.body.continue: 19570 // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 19571 // CHECK28: omp.inner.for.inc: 19572 // CHECK28-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 19573 // CHECK28-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 19574 // CHECK28-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 19575 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] 19576 // CHECK28: omp.inner.for.end: 19577 // CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 19578 // CHECK28: omp.loop.exit: 19579 // CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 19580 // CHECK28-NEXT: ret void 19581 // 19582