1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 9 10 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 17 // Test target codegen - host bc file has to be created first. 18 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 19 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 22 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 23 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 24 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 25 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 26 27 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 28 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 29 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 30 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 31 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 32 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 33 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 34 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 35 36 // Test host codegen. 37 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 38 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 39 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 40 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 41 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 42 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 43 44 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 45 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 46 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 47 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 48 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 49 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 50 51 // Test target codegen - host bc file has to be created first. 52 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 53 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 54 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 55 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 56 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 57 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 58 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 59 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 60 61 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 62 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 63 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 64 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 65 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 66 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 67 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 68 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 69 70 // expected-no-diagnostics 71 #ifndef HEADER 72 #define HEADER 73 74 75 76 77 // We have 8 target regions, but only 7 that actually will generate offloading 78 // code, only 6 will have mapped arguments, and only 4 have all-constant map 79 // sizes. 80 81 82 83 // Check target registration is registered as a Ctor. 84 85 86 template<typename tx, typename ty> 87 struct TT{ 88 tx X; 89 ty Y; 90 }; 91 92 long long get_val() { return 0; } 93 94 int foo(int n) { 95 int a = 0; 96 short aa = 0; 97 float b[10]; 98 float bn[n]; 99 double c[5][10]; 100 double cn[5][n]; 101 TT<long long, char> d; 102 103 #pragma omp target parallel for 104 for (int i = 3; i < 32; i += 5) { 105 #pragma omp cancel for 106 #pragma omp cancellation point for 107 } 108 109 long long k = get_val(); 110 #pragma omp target parallel for if(target: 0) linear(k : 3) schedule(dynamic) 111 for (int i = 10; i > 1; i--) { 112 a += 1; 113 } 114 115 // CEHCK-32: [[FPSIZEGEP]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 0 116 // CEHCK-32: [[FPSIZEADDR:%.+]] = bitcast [3 x i64]* [[FPSIZEGEP]] to i8* 117 // CEHCK-32: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPSIZEADDR]], i8* align 8 bitcast ([3 x i64]* [[SIZET2]] to i8*), i64 24, i1 false) 118 // CEHCK-32: [[FPBPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 1 119 // CEHCK-32: [[FPBPADDR:%.+]] = bitcast [3 x i8*]* [[FPBPGEP]] to i8* 120 // CEHCK-32: [[BPCAST:%.+]] = bitcast i8** [[BPGEP]] to i8* 121 // CEHCK-32: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPBPADDR]], i8* align 8 [[BPCAST]], i64 24, i1 false) 122 // CEHCK-32: [[FPPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 2 123 // CEHCK-32: [[FPPADDR:%.+]] = bitcast [3 x i8*]* [[FPPGEP]] to i8* 124 // CEHCK-32: [[PCAST:%.+]] = bitcast i8** [[PGEP]] to i8* 125 // CEHCK-32: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPPADDR]], i8* align 8 [[BCAST]], i64 24, i1 false) 126 // CEHCK-64: [[FPBPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 0 127 // CEHCK-64: [[FPBPADDR:%.+]] = bitcast [3 x i8*]* [[FPBPGEP]] to i8* 128 // CEHCK-64: [[BPCAST:%.+]] = bitcast i8** [[BPGEP]] to i8* 129 // CEHCK-64: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPBPADDR]], i8* align 8 [[BPCAST]], i64 24, i1 false) 130 // CEHCK-64: [[FPPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 1 131 // CEHCK-64: [[FPPADDR:%.+]] = bitcast [3 x i8*]* [[FPPGEP]] to i8* 132 // CEHCK-64: [[PCAST:%.+]] = bitcast i8** [[PGEP]] to i8* 133 // CEHCK-64: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPPADDR]], i8* align 8 [[BCAST]], i64 24, i1 false) 134 // CEHCK-64: [[FPSIZEGEP]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 2 135 // CEHCK-64: [[FPSIZEADDR:%.+]] = bitcast [3 x i64]* [[FPSIZEGEP]] to i8* 136 // CEHCK-64: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPSIZEADDR]], i8* align 8 bitcast ([3 x i64]* [[SIZET2]] to i8*), i64 24, i1 false) 137 int lin = 12; 138 #pragma omp target parallel for if(target: 1) linear(lin, a : get_val()) nowait 139 for (unsigned long long it = 2000; it >= 600; it-=400) { 140 aa += 1; 141 } 142 143 144 145 146 #pragma omp target parallel for if(target: n>10) 147 for (short it = 6; it <= 20; it-=-4) { 148 a += 1; 149 aa += 1; 150 } 151 152 // We capture 3 VLA sizes in this target region 153 154 155 156 157 158 // The names below are not necessarily consistent with the names used for the 159 // addresses above as some are repeated. 160 161 162 163 164 165 166 167 168 169 170 #pragma omp target parallel for if(target: n>20) schedule(static, a) 171 for (unsigned char it = 'z'; it >= 'a'; it+=-1) { 172 a += 1; 173 b[2] += 1.0; 174 bn[3] += 1.0; 175 c[1][2] += 1.0; 176 cn[1][3] += 1.0; 177 d.X += 1; 178 d.Y += 1; 179 } 180 181 return a; 182 } 183 184 // Check that the offloading functions are emitted and that the arguments are 185 // correct and loaded correctly for the target regions in foo(). 186 187 188 // Create stack storage and store argument in there. 189 190 // Create stack storage and store argument in there. 191 192 193 // Create stack storage and store argument in there. 194 195 // Create local storage for each capture. 196 197 198 199 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 200 201 template<typename tx> 202 tx ftemplate(int n) { 203 tx a = 0; 204 short aa = 0; 205 tx b[10]; 206 207 #pragma omp target parallel for if(target: n>40) 208 for (long long i = -10; i < 10; i += 3) { 209 a += 1; 210 aa += 1; 211 b[2] += 1; 212 } 213 214 return a; 215 } 216 217 static 218 int fstatic(int n) { 219 int a = 0; 220 short aa = 0; 221 char aaa = 0; 222 int b[10]; 223 224 #pragma omp target parallel for if(target: n>50) 225 for (unsigned i=100; i<10; i+=10) { 226 a += 1; 227 aa += 1; 228 aaa += 1; 229 b[2] += 1; 230 } 231 232 return a; 233 } 234 235 struct S1 { 236 double a; 237 238 int r1(int n){ 239 int b = n+1; 240 short int c[2][n]; 241 242 #pragma omp target parallel for if(target: n>60) 243 for (unsigned long long it = 2000; it >= 600; it -= 400) { 244 this->a = (double)b + 1.5; 245 c[1][1] = ++a; 246 } 247 248 return c[1][1] + (int)b; 249 } 250 }; 251 252 int bar(int n){ 253 int a = 0; 254 255 a += foo(n); 256 257 S1 S; 258 a += S.r1(n); 259 260 a += fstatic(n); 261 262 a += ftemplate<int>(n); 263 264 return a; 265 } 266 267 268 269 // We capture 2 VLA sizes in this target region 270 271 272 // The names below are not necessarily consistent with the names used for the 273 // addresses above as some are repeated. 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 // Check that the offloading functions are emitted and that the arguments are 293 // correct and loaded correctly for the target regions of the callees of bar(). 294 295 // Create local storage for each capture. 296 // Store captures in the context. 297 298 299 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 300 301 302 // Create local storage for each capture. 303 // Store captures in the context. 304 305 306 307 308 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 309 310 // Create local storage for each capture. 311 // Store captures in the context. 312 313 314 315 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 316 317 318 #endif 319 // CHECK1-LABEL: define {{[^@]+}}@_Z7get_valv 320 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 321 // CHECK1-NEXT: entry: 322 // CHECK1-NEXT: ret i64 0 323 // 324 // 325 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 326 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 327 // CHECK1-NEXT: entry: 328 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 329 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 330 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 331 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 332 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 333 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 334 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 335 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 336 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 337 // CHECK1-NEXT: [[K:%.*]] = alloca i64, align 8 338 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 339 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 340 // CHECK1-NEXT: [[LIN:%.*]] = alloca i32, align 4 341 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 342 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 343 // CHECK1-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8 344 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 345 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 346 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 347 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 348 // CHECK1-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8 349 // CHECK1-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8 350 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 351 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 352 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 353 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 354 // CHECK1-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8 355 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 356 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8 357 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8 358 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8 359 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 360 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 361 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 362 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 363 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 364 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 365 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 366 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 367 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 368 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 369 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 370 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 371 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 372 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 373 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 374 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 375 // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 376 // CHECK1-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 377 // CHECK1-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 378 // CHECK1: omp_offload.failed: 379 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 380 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 381 // CHECK1: omp_offload.cont: 382 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 383 // CHECK1-NEXT: store i64 [[CALL]], i64* [[K]], align 8 384 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 385 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 386 // CHECK1-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4 387 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8 388 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[K]], align 8 389 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[K_CASTED]], align 8 390 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8 391 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR4]] 392 // CHECK1-NEXT: store i32 12, i32* [[LIN]], align 4 393 // CHECK1-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 394 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 395 // CHECK1-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 396 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 397 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4 398 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 399 // CHECK1-NEXT: store i32 [[TMP15]], i32* [[CONV3]], align 4 400 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 401 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 402 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32* 403 // CHECK1-NEXT: store i32 [[TMP17]], i32* [[CONV5]], align 4 404 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8 405 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 406 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 407 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP20]], align 8 408 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 409 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 410 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP22]], align 8 411 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 412 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 413 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 414 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 415 // CHECK1-NEXT: store i64 [[TMP16]], i64* [[TMP25]], align 8 416 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 417 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 418 // CHECK1-NEXT: store i64 [[TMP16]], i64* [[TMP27]], align 8 419 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 420 // CHECK1-NEXT: store i8* null, i8** [[TMP28]], align 8 421 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 422 // CHECK1-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 423 // CHECK1-NEXT: store i64 [[TMP18]], i64* [[TMP30]], align 8 424 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 425 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 426 // CHECK1-NEXT: store i64 [[TMP18]], i64* [[TMP32]], align 8 427 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 428 // CHECK1-NEXT: store i8* null, i8** [[TMP33]], align 8 429 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 430 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 431 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 432 // CHECK1-NEXT: [[TMP37:%.*]] = load i16, i16* [[AA]], align 2 433 // CHECK1-NEXT: store i16 [[TMP37]], i16* [[TMP36]], align 4 434 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 435 // CHECK1-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4 436 // CHECK1-NEXT: store i32 [[TMP39]], i32* [[TMP38]], align 4 437 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 438 // CHECK1-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 439 // CHECK1-NEXT: store i32 [[TMP41]], i32* [[TMP40]], align 4 440 // CHECK1-NEXT: [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 441 // CHECK1-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates* 442 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0 443 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0 444 // CHECK1-NEXT: [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8 445 // CHECK1-NEXT: [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 446 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false) 447 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1 448 // CHECK1-NEXT: [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon* 449 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0 450 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8* 451 // CHECK1-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8* 452 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false) 453 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1 454 // CHECK1-NEXT: [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8* 455 // CHECK1-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8* 456 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false) 457 // CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2 458 // CHECK1-NEXT: [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8* 459 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 460 // CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3 461 // CHECK1-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 462 // CHECK1-NEXT: store i16 [[TMP59]], i16* [[TMP58]], align 8 463 // CHECK1-NEXT: [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]]) 464 // CHECK1-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4 465 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32* 466 // CHECK1-NEXT: store i32 [[TMP61]], i32* [[CONV7]], align 4 467 // CHECK1-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8 468 // CHECK1-NEXT: [[TMP63:%.*]] = load i16, i16* [[AA]], align 2 469 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16* 470 // CHECK1-NEXT: store i16 [[TMP63]], i16* [[CONV9]], align 2 471 // CHECK1-NEXT: [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8 472 // CHECK1-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4 473 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10 474 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 475 // CHECK1: omp_if.then: 476 // CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 477 // CHECK1-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64* 478 // CHECK1-NEXT: store i64 [[TMP62]], i64* [[TMP67]], align 8 479 // CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 480 // CHECK1-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* 481 // CHECK1-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8 482 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 483 // CHECK1-NEXT: store i8* null, i8** [[TMP70]], align 8 484 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 485 // CHECK1-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* 486 // CHECK1-NEXT: store i64 [[TMP64]], i64* [[TMP72]], align 8 487 // CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 488 // CHECK1-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* 489 // CHECK1-NEXT: store i64 [[TMP64]], i64* [[TMP74]], align 8 490 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 491 // CHECK1-NEXT: store i8* null, i8** [[TMP75]], align 8 492 // CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 493 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 494 // CHECK1-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 495 // CHECK1-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0 496 // CHECK1-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]] 497 // CHECK1: omp_offload.failed13: 498 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 499 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT14]] 500 // CHECK1: omp_offload.cont14: 501 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 502 // CHECK1: omp_if.else: 503 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 504 // CHECK1-NEXT: br label [[OMP_IF_END]] 505 // CHECK1: omp_if.end: 506 // CHECK1-NEXT: [[TMP80:%.*]] = load i32, i32* [[A]], align 4 507 // CHECK1-NEXT: store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4 508 // CHECK1-NEXT: [[TMP81:%.*]] = load i32, i32* [[A]], align 4 509 // CHECK1-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32* 510 // CHECK1-NEXT: store i32 [[TMP81]], i32* [[CONV16]], align 4 511 // CHECK1-NEXT: [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8 512 // CHECK1-NEXT: [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 513 // CHECK1-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 514 // CHECK1-NEXT: store i32 [[TMP83]], i32* [[CONV17]], align 4 515 // CHECK1-NEXT: [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 516 // CHECK1-NEXT: [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4 517 // CHECK1-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20 518 // CHECK1-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 519 // CHECK1: omp_if.then19: 520 // CHECK1-NEXT: [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4 521 // CHECK1-NEXT: [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]] 522 // CHECK1-NEXT: [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8 523 // CHECK1-NEXT: [[TMP89:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 524 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP89]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i64 80, i1 false) 525 // CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 526 // CHECK1-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i64* 527 // CHECK1-NEXT: store i64 [[TMP82]], i64* [[TMP91]], align 8 528 // CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 529 // CHECK1-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to i64* 530 // CHECK1-NEXT: store i64 [[TMP82]], i64* [[TMP93]], align 8 531 // CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 532 // CHECK1-NEXT: store i8* null, i8** [[TMP94]], align 8 533 // CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 534 // CHECK1-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 535 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8 536 // CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 537 // CHECK1-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]** 538 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8 539 // CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 540 // CHECK1-NEXT: store i8* null, i8** [[TMP99]], align 8 541 // CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 542 // CHECK1-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64* 543 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP101]], align 8 544 // CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 545 // CHECK1-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i64* 546 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP103]], align 8 547 // CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 548 // CHECK1-NEXT: store i8* null, i8** [[TMP104]], align 8 549 // CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 550 // CHECK1-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** 551 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP106]], align 8 552 // CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 553 // CHECK1-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** 554 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP108]], align 8 555 // CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 556 // CHECK1-NEXT: store i64 [[TMP86]], i64* [[TMP109]], align 8 557 // CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 558 // CHECK1-NEXT: store i8* null, i8** [[TMP110]], align 8 559 // CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 560 // CHECK1-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** 561 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 8 562 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 563 // CHECK1-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** 564 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8 565 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 566 // CHECK1-NEXT: store i8* null, i8** [[TMP115]], align 8 567 // CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 568 // CHECK1-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64* 569 // CHECK1-NEXT: store i64 5, i64* [[TMP117]], align 8 570 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 571 // CHECK1-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i64* 572 // CHECK1-NEXT: store i64 5, i64* [[TMP119]], align 8 573 // CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5 574 // CHECK1-NEXT: store i8* null, i8** [[TMP120]], align 8 575 // CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 576 // CHECK1-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64* 577 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP122]], align 8 578 // CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 579 // CHECK1-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i64* 580 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP124]], align 8 581 // CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6 582 // CHECK1-NEXT: store i8* null, i8** [[TMP125]], align 8 583 // CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 584 // CHECK1-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** 585 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP127]], align 8 586 // CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 587 // CHECK1-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to double** 588 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP129]], align 8 589 // CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 590 // CHECK1-NEXT: store i64 [[TMP88]], i64* [[TMP130]], align 8 591 // CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7 592 // CHECK1-NEXT: store i8* null, i8** [[TMP131]], align 8 593 // CHECK1-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 594 // CHECK1-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT** 595 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 8 596 // CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 597 // CHECK1-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to %struct.TT** 598 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP135]], align 8 599 // CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8 600 // CHECK1-NEXT: store i8* null, i8** [[TMP136]], align 8 601 // CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9 602 // CHECK1-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i64* 603 // CHECK1-NEXT: store i64 [[TMP84]], i64* [[TMP138]], align 8 604 // CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9 605 // CHECK1-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to i64* 606 // CHECK1-NEXT: store i64 [[TMP84]], i64* [[TMP140]], align 8 607 // CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9 608 // CHECK1-NEXT: store i8* null, i8** [[TMP141]], align 8 609 // CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 610 // CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 611 // CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 612 // CHECK1-NEXT: [[TMP145:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP142]], i8** [[TMP143]], i64* [[TMP144]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 613 // CHECK1-NEXT: [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 0 614 // CHECK1-NEXT: br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 615 // CHECK1: omp_offload.failed23: 616 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 617 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT24]] 618 // CHECK1: omp_offload.cont24: 619 // CHECK1-NEXT: br label [[OMP_IF_END26:%.*]] 620 // CHECK1: omp_if.else25: 621 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 622 // CHECK1-NEXT: br label [[OMP_IF_END26]] 623 // CHECK1: omp_if.end26: 624 // CHECK1-NEXT: [[TMP147:%.*]] = load i32, i32* [[A]], align 4 625 // CHECK1-NEXT: [[TMP148:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 626 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP148]]) 627 // CHECK1-NEXT: ret i32 [[TMP147]] 628 // 629 // 630 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 631 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] { 632 // CHECK1-NEXT: entry: 633 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 634 // CHECK1-NEXT: ret void 635 // 636 // 637 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 638 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 639 // CHECK1-NEXT: entry: 640 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 641 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 642 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 643 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 644 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 645 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 646 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 647 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 648 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 649 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 650 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 651 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 652 // CHECK1-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 653 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 654 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 655 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 656 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 657 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 658 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 659 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 660 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 661 // CHECK1: cond.true: 662 // CHECK1-NEXT: br label [[COND_END:%.*]] 663 // CHECK1: cond.false: 664 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 665 // CHECK1-NEXT: br label [[COND_END]] 666 // CHECK1: cond.end: 667 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 668 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 669 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 670 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 671 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 672 // CHECK1: omp.inner.for.cond: 673 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 674 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 675 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 676 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 677 // CHECK1: omp.inner.for.body: 678 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 679 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 680 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 681 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 682 // CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 683 // CHECK1-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 684 // CHECK1-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 685 // CHECK1: .cancel.exit: 686 // CHECK1-NEXT: br label [[CANCEL_EXIT:%.*]] 687 // CHECK1: .cancel.continue: 688 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 689 // CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 690 // CHECK1-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 691 // CHECK1: .cancel.exit2: 692 // CHECK1-NEXT: br label [[CANCEL_EXIT]] 693 // CHECK1: .cancel.continue3: 694 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 695 // CHECK1: omp.body.continue: 696 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 697 // CHECK1: omp.inner.for.inc: 698 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 699 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 700 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 701 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 702 // CHECK1: omp.inner.for.end: 703 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 704 // CHECK1: omp.loop.exit: 705 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 706 // CHECK1-NEXT: br label [[CANCEL_CONT:%.*]] 707 // CHECK1: cancel.cont: 708 // CHECK1-NEXT: ret void 709 // CHECK1: cancel.exit: 710 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 711 // CHECK1-NEXT: br label [[CANCEL_CONT]] 712 // 713 // 714 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 715 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 716 // CHECK1-NEXT: entry: 717 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 718 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 719 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 720 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 721 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 722 // CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 723 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 724 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 725 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 726 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 727 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 728 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 729 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 730 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 731 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 732 // CHECK1-NEXT: ret void 733 // 734 // 735 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 736 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 737 // CHECK1-NEXT: entry: 738 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 739 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 740 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 741 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 742 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 743 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 744 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 745 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 746 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 747 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 748 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 749 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 750 // CHECK1-NEXT: [[K1:%.*]] = alloca i64, align 8 751 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 752 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 753 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 754 // CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 755 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 756 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8 757 // CHECK1-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8 758 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 759 // CHECK1-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 760 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 761 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 762 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 763 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 764 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 765 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1) 766 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 767 // CHECK1: omp.dispatch.cond: 768 // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 769 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 770 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 771 // CHECK1: omp.dispatch.body: 772 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 773 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 774 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 775 // CHECK1: omp.inner.for.cond: 776 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 777 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 778 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 779 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 780 // CHECK1: omp.inner.for.body: 781 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 782 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 783 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 784 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12 785 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12 786 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 787 // CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 788 // CHECK1-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 789 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] 790 // CHECK1-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12 791 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12 792 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 793 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12 794 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 795 // CHECK1: omp.body.continue: 796 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 797 // CHECK1: omp.inner.for.inc: 798 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 799 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 800 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 801 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 802 // CHECK1: omp.inner.for.end: 803 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 804 // CHECK1: omp.dispatch.inc: 805 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 806 // CHECK1: omp.dispatch.end: 807 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 808 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 809 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 810 // CHECK1: .omp.linear.pu: 811 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[K1]], align 8 812 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[K_ADDR]], align 8 813 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 814 // CHECK1: .omp.linear.pu.done: 815 // CHECK1-NEXT: ret void 816 // 817 // 818 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 819 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 820 // CHECK1-NEXT: entry: 821 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 822 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 823 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 824 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 825 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 826 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 827 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 828 // CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 829 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 830 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 831 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 832 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 833 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 834 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 835 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 836 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 837 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 838 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 839 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 840 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 841 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 842 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 843 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 844 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 845 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 846 // CHECK1-NEXT: ret void 847 // 848 // 849 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 850 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 851 // CHECK1-NEXT: entry: 852 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 853 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 854 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 855 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 856 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 857 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 858 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 859 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 860 // CHECK1-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 861 // CHECK1-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 862 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 863 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 864 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 865 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 866 // CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8 867 // CHECK1-NEXT: [[LIN4:%.*]] = alloca i32, align 4 868 // CHECK1-NEXT: [[A5:%.*]] = alloca i32, align 4 869 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 870 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 871 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 872 // CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 873 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 874 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 875 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 876 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 877 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 878 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 879 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 880 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 881 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 882 // CHECK1-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 883 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 884 // CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 885 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 886 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 887 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 888 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 889 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 890 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 891 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 892 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 893 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 894 // CHECK1: cond.true: 895 // CHECK1-NEXT: br label [[COND_END:%.*]] 896 // CHECK1: cond.false: 897 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 898 // CHECK1-NEXT: br label [[COND_END]] 899 // CHECK1: cond.end: 900 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 901 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 902 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 903 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 904 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 905 // CHECK1: omp.inner.for.cond: 906 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 907 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 908 // CHECK1-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 909 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 910 // CHECK1: omp.inner.for.body: 911 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 912 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 913 // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 914 // CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 915 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 916 // CHECK1-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 917 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 918 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 919 // CHECK1-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 920 // CHECK1-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 921 // CHECK1-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 922 // CHECK1-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 923 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 924 // CHECK1-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 925 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 926 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 927 // CHECK1-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 928 // CHECK1-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 929 // CHECK1-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 930 // CHECK1-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 931 // CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 932 // CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 933 // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 934 // CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 935 // CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 936 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 937 // CHECK1: omp.body.continue: 938 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 939 // CHECK1: omp.inner.for.inc: 940 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 941 // CHECK1-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 942 // CHECK1-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 943 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 944 // CHECK1: omp.inner.for.end: 945 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 946 // CHECK1: omp.loop.exit: 947 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 948 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 949 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 950 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 951 // CHECK1: .omp.linear.pu: 952 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 953 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 954 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 955 // CHECK1-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 956 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 957 // CHECK1: .omp.linear.pu.done: 958 // CHECK1-NEXT: ret void 959 // 960 // 961 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. 962 // CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 963 // CHECK1-NEXT: entry: 964 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 965 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 966 // CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 967 // CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 968 // CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 969 // CHECK1-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 970 // CHECK1-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 971 // CHECK1-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 972 // CHECK1-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 973 // CHECK1-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 974 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 975 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 976 // CHECK1-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 977 // CHECK1-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 978 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 979 // CHECK1-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 980 // CHECK1-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 981 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 982 // CHECK1-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 983 // CHECK1-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 984 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 985 // CHECK1-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 986 // CHECK1-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 987 // CHECK1-NEXT: ret void 988 // 989 // 990 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 991 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 992 // CHECK1-NEXT: entry: 993 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 994 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 995 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 996 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 997 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 998 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 999 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 1000 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 1001 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 1002 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 1003 // CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 1004 // CHECK1-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8 1005 // CHECK1-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8 1006 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 1007 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 1008 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 1009 // CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 1010 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 1011 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 1012 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 1013 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 1014 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 1015 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 1016 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 1017 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 1018 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 1019 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 1020 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 1021 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 1022 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 1023 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 1024 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 1025 // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24 1026 // CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 1027 // CHECK1-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 1028 // CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24 1029 // CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 1030 // CHECK1-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 1031 // CHECK1-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 1032 // CHECK1-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 1033 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 1034 // CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 1035 // CHECK1-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 1036 // CHECK1-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 1037 // CHECK1-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 1038 // CHECK1-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24 1039 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 1040 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 1041 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 1042 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 1043 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 1044 // CHECK1-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 1045 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 1046 // CHECK1-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 1047 // CHECK1: omp_offload.failed.i: 1048 // CHECK1-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 1049 // CHECK1-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 1050 // CHECK1-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24 1051 // CHECK1-NEXT: [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24 1052 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 1053 // CHECK1-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32* 1054 // CHECK1-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !24 1055 // CHECK1-NEXT: [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !24 1056 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 1057 // CHECK1-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32* 1058 // CHECK1-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !24 1059 // CHECK1-NEXT: [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !24 1060 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR4]] 1061 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 1062 // CHECK1: .omp_outlined..3.exit: 1063 // CHECK1-NEXT: ret i32 0 1064 // 1065 // 1066 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 1067 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1068 // CHECK1-NEXT: entry: 1069 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1070 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1071 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1072 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1073 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1074 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1075 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1076 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1077 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1078 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1079 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 1080 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1081 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1082 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1083 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 1084 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1085 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 1086 // CHECK1-NEXT: ret void 1087 // 1088 // 1089 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 1090 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 1091 // CHECK1-NEXT: entry: 1092 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1093 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1094 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1095 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1096 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1097 // CHECK1-NEXT: [[TMP:%.*]] = alloca i16, align 2 1098 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1099 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1100 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1101 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1102 // CHECK1-NEXT: [[IT:%.*]] = alloca i16, align 2 1103 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1104 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1105 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1106 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1107 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1108 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1109 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1110 // CHECK1-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 1111 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1112 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1113 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1114 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1115 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1116 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1117 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 1118 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1119 // CHECK1: cond.true: 1120 // CHECK1-NEXT: br label [[COND_END:%.*]] 1121 // CHECK1: cond.false: 1122 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1123 // CHECK1-NEXT: br label [[COND_END]] 1124 // CHECK1: cond.end: 1125 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1126 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1127 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1128 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1129 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1130 // CHECK1: omp.inner.for.cond: 1131 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1132 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1133 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1134 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1135 // CHECK1: omp.inner.for.body: 1136 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1137 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 1138 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 1139 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 1140 // CHECK1-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 1141 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 1142 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 1143 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 1144 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 1145 // CHECK1-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 1146 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 1147 // CHECK1-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 1148 // CHECK1-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 1149 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1150 // CHECK1: omp.body.continue: 1151 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1152 // CHECK1: omp.inner.for.inc: 1153 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1154 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 1155 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 1156 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1157 // CHECK1: omp.inner.for.end: 1158 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1159 // CHECK1: omp.loop.exit: 1160 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 1161 // CHECK1-NEXT: ret void 1162 // 1163 // 1164 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 1165 // CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 1166 // CHECK1-NEXT: entry: 1167 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1168 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1169 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1170 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1171 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1172 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1173 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1174 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1175 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1176 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1177 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1178 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1179 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1180 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1181 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1182 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1183 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1184 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1185 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1186 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1187 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1188 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 1189 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1190 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1191 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1192 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1193 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1194 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1195 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1196 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1197 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1198 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 1199 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 1200 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1201 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 1202 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 1203 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 1204 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 1205 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 1206 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 1207 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 1208 // CHECK1-NEXT: ret void 1209 // 1210 // 1211 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 1212 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 1213 // CHECK1-NEXT: entry: 1214 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1215 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1216 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1217 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1218 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1219 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1220 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1221 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1222 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1223 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1224 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1225 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1226 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1227 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 1228 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1229 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1230 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1231 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1232 // CHECK1-NEXT: [[IT:%.*]] = alloca i8, align 1 1233 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1234 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1235 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1236 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1237 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1238 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1239 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1240 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1241 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1242 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1243 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1244 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 1245 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1246 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1247 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1248 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1249 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1250 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1251 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1252 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1253 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1254 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 1255 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1256 // CHECK1-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 1257 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1258 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1259 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 1260 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1261 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 1262 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 1263 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1264 // CHECK1: omp.dispatch.cond: 1265 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1266 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 1267 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1268 // CHECK1: cond.true: 1269 // CHECK1-NEXT: br label [[COND_END:%.*]] 1270 // CHECK1: cond.false: 1271 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1272 // CHECK1-NEXT: br label [[COND_END]] 1273 // CHECK1: cond.end: 1274 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 1275 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1276 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1277 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 1278 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1279 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1280 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 1281 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1282 // CHECK1: omp.dispatch.body: 1283 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1284 // CHECK1: omp.inner.for.cond: 1285 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1286 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1287 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 1288 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1289 // CHECK1: omp.inner.for.body: 1290 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1291 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 1292 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 1293 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 1294 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 1295 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 1296 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 1297 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1298 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 1299 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 1300 // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 1301 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 1302 // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 1303 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 1304 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 1305 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 1306 // CHECK1-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 1307 // CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 1308 // CHECK1-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 1309 // CHECK1-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 1310 // CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 1311 // CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 1312 // CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 1313 // CHECK1-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 1314 // CHECK1-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 1315 // CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 1316 // CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 1317 // CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 1318 // CHECK1-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 1319 // CHECK1-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 1320 // CHECK1-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 1321 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 1322 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 1323 // CHECK1-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 1324 // CHECK1-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 1325 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 1326 // CHECK1-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 1327 // CHECK1-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 1328 // CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 1329 // CHECK1-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 1330 // CHECK1-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 1331 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1332 // CHECK1: omp.body.continue: 1333 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1334 // CHECK1: omp.inner.for.inc: 1335 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1336 // CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 1337 // CHECK1-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 1338 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1339 // CHECK1: omp.inner.for.end: 1340 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1341 // CHECK1: omp.dispatch.inc: 1342 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1343 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1344 // CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 1345 // CHECK1-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 1346 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1347 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1348 // CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 1349 // CHECK1-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 1350 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1351 // CHECK1: omp.dispatch.end: 1352 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 1353 // CHECK1-NEXT: ret void 1354 // 1355 // 1356 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 1357 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1358 // CHECK1-NEXT: entry: 1359 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1360 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1361 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1362 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1363 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1364 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1365 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 1366 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1367 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1368 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1369 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1370 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 1371 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1372 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1373 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1374 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1375 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 1376 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1377 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1378 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 1379 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1380 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 1381 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 1382 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1383 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 1384 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 1385 // CHECK1-NEXT: ret i32 [[TMP8]] 1386 // 1387 // 1388 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1389 // CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1390 // CHECK1-NEXT: entry: 1391 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1392 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1393 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 1394 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1395 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1396 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1397 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1398 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1399 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1400 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1401 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1402 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1403 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1404 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1405 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1406 // CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4 1407 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1408 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1409 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 1410 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 1411 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 1412 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 1413 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1414 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 1415 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1416 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 1417 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 1418 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 1419 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 1420 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1421 // CHECK1: omp_if.then: 1422 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 1423 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 1424 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 1425 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1426 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false) 1427 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1428 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 1429 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 1430 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1431 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 1432 // CHECK1-NEXT: store double* [[A]], double** [[TMP14]], align 8 1433 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1434 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8 1435 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1436 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 1437 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 1438 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1439 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1440 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 1441 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1442 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8 1443 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1444 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 1445 // CHECK1-NEXT: store i64 2, i64* [[TMP22]], align 8 1446 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1447 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 1448 // CHECK1-NEXT: store i64 2, i64* [[TMP24]], align 8 1449 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1450 // CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8 1451 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1452 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 1453 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 1454 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1455 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1456 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 1457 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1458 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8 1459 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1460 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 1461 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 1462 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1463 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 1464 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 1465 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1466 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 1467 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1468 // CHECK1-NEXT: store i8* null, i8** [[TMP36]], align 8 1469 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1470 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1471 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1472 // CHECK1-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1473 // CHECK1-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 1474 // CHECK1-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1475 // CHECK1: omp_offload.failed: 1476 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 1477 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1478 // CHECK1: omp_offload.cont: 1479 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1480 // CHECK1: omp_if.else: 1481 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 1482 // CHECK1-NEXT: br label [[OMP_IF_END]] 1483 // CHECK1: omp_if.end: 1484 // CHECK1-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 1485 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 1486 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1487 // CHECK1-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 1488 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 1489 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 1490 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 1491 // CHECK1-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1492 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 1493 // CHECK1-NEXT: ret i32 [[ADD4]] 1494 // 1495 // 1496 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 1497 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1498 // CHECK1-NEXT: entry: 1499 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1500 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1501 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1502 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 1503 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1504 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1505 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1506 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1507 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1508 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1509 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1510 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1511 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1512 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1513 // CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1 1514 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1515 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1516 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1517 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1518 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1519 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1520 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1521 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1522 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 1523 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1524 // CHECK1-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 1525 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1526 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1527 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 1528 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1529 // CHECK1: omp_if.then: 1530 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1531 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1532 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1533 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1534 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 1535 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 1536 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1537 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8 1538 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1539 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1540 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1541 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1542 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 1543 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 1544 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1545 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8 1546 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1547 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 1548 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 1549 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1550 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 1551 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 1552 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1553 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 1554 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1555 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 1556 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 1557 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1558 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 1559 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 1560 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1561 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8 1562 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1563 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1564 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1565 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1566 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1567 // CHECK1: omp_offload.failed: 1568 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 1569 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1570 // CHECK1: omp_offload.cont: 1571 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1572 // CHECK1: omp_if.else: 1573 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 1574 // CHECK1-NEXT: br label [[OMP_IF_END]] 1575 // CHECK1: omp_if.end: 1576 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 1577 // CHECK1-NEXT: ret i32 [[TMP31]] 1578 // 1579 // 1580 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1581 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1582 // CHECK1-NEXT: entry: 1583 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1584 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1585 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1586 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1587 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1588 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1589 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1590 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1591 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1592 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1593 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1594 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1595 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1596 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1597 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1598 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1599 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1600 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1601 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1602 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1603 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1604 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1605 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1606 // CHECK1: omp_if.then: 1607 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1608 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 1609 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 1610 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1611 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1612 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1613 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1614 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 1615 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1616 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 1617 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 1618 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1619 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1620 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1621 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1622 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 1623 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1624 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 1625 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 1626 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1627 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 1628 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 1629 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1630 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 1631 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1632 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1633 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1634 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 1635 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1636 // CHECK1: omp_offload.failed: 1637 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1638 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1639 // CHECK1: omp_offload.cont: 1640 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1641 // CHECK1: omp_if.else: 1642 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1643 // CHECK1-NEXT: br label [[OMP_IF_END]] 1644 // CHECK1: omp_if.end: 1645 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 1646 // CHECK1-NEXT: ret i32 [[TMP24]] 1647 // 1648 // 1649 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 1650 // CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1651 // CHECK1-NEXT: entry: 1652 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1653 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1654 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1655 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1656 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1657 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1658 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1659 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1660 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1661 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1662 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1663 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1664 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1665 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1666 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1667 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1668 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1669 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1670 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 1671 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 1672 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 1673 // CHECK1-NEXT: ret void 1674 // 1675 // 1676 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 1677 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 1678 // CHECK1-NEXT: entry: 1679 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1680 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1681 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1682 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1683 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1684 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1685 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1686 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1687 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 1688 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1689 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1690 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1691 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1692 // CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8 1693 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1694 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1695 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1696 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1697 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1698 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1699 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1700 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1701 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1702 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1703 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1704 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1705 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1706 // CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 1707 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1708 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1709 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1710 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1711 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1712 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1713 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 1714 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1715 // CHECK1: cond.true: 1716 // CHECK1-NEXT: br label [[COND_END:%.*]] 1717 // CHECK1: cond.false: 1718 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1719 // CHECK1-NEXT: br label [[COND_END]] 1720 // CHECK1: cond.end: 1721 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1722 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1723 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1724 // CHECK1-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 1725 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1726 // CHECK1: omp.inner.for.cond: 1727 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1728 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1729 // CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 1730 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1731 // CHECK1: omp.inner.for.body: 1732 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1733 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 1734 // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 1735 // CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 1736 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 1737 // CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 1738 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 1739 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1740 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 1741 // CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1742 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 1743 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 1744 // CHECK1-NEXT: store double [[INC]], double* [[A5]], align 8 1745 // CHECK1-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 1746 // CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 1747 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 1748 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1749 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 1750 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1751 // CHECK1: omp.body.continue: 1752 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1753 // CHECK1: omp.inner.for.inc: 1754 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1755 // CHECK1-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 1756 // CHECK1-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 1757 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1758 // CHECK1: omp.inner.for.end: 1759 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1760 // CHECK1: omp.loop.exit: 1761 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1762 // CHECK1-NEXT: ret void 1763 // 1764 // 1765 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 1766 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1767 // CHECK1-NEXT: entry: 1768 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1769 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1770 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1771 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1772 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1773 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1774 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1775 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1776 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1777 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1778 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1779 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1780 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1781 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1782 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1783 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1784 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1785 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 1786 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1787 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1788 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1789 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 1790 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1791 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 1792 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1793 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 1794 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1795 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 1796 // CHECK1-NEXT: ret void 1797 // 1798 // 1799 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 1800 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1801 // CHECK1-NEXT: entry: 1802 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1803 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1804 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1805 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1806 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1807 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1808 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1809 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1810 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1811 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1812 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1813 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1814 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1815 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1816 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1817 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1818 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1819 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1820 // CHECK1-NEXT: ret void 1821 // 1822 // 1823 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 1824 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1825 // CHECK1-NEXT: entry: 1826 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1827 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1828 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1829 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1830 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1831 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1832 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1833 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1834 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1835 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1836 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1837 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1838 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1839 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 1840 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1841 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1842 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1843 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 1844 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1845 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 1846 // CHECK1-NEXT: ret void 1847 // 1848 // 1849 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 1850 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1851 // CHECK1-NEXT: entry: 1852 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1853 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1854 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1855 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1856 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1857 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1858 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 1859 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1860 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1861 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1862 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1863 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 1864 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1865 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1866 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1867 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1868 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1869 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1870 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1871 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1872 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1873 // CHECK1-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 1874 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1875 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1876 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1877 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1878 // CHECK1-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1879 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1880 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 1881 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1882 // CHECK1: cond.true: 1883 // CHECK1-NEXT: br label [[COND_END:%.*]] 1884 // CHECK1: cond.false: 1885 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1886 // CHECK1-NEXT: br label [[COND_END]] 1887 // CHECK1: cond.end: 1888 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1889 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1890 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1891 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 1892 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1893 // CHECK1: omp.inner.for.cond: 1894 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1895 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1896 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 1897 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1898 // CHECK1: omp.inner.for.body: 1899 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1900 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 1901 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 1902 // CHECK1-NEXT: store i64 [[ADD]], i64* [[I]], align 8 1903 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 1904 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 1905 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 1906 // CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 1907 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 1908 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 1909 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 1910 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 1911 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1912 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1913 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 1914 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 1915 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1916 // CHECK1: omp.body.continue: 1917 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1918 // CHECK1: omp.inner.for.inc: 1919 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1920 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 1921 // CHECK1-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 1922 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1923 // CHECK1: omp.inner.for.end: 1924 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1925 // CHECK1: omp.loop.exit: 1926 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1927 // CHECK1-NEXT: ret void 1928 // 1929 // 1930 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1931 // CHECK1-SAME: () #[[ATTR6]] { 1932 // CHECK1-NEXT: entry: 1933 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1934 // CHECK1-NEXT: ret void 1935 // 1936 // 1937 // CHECK3-LABEL: define {{[^@]+}}@_Z7get_valv 1938 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 1939 // CHECK3-NEXT: entry: 1940 // CHECK3-NEXT: ret i64 0 1941 // 1942 // 1943 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 1944 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 1945 // CHECK3-NEXT: entry: 1946 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1947 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 1948 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 1949 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 1950 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 1951 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1952 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 1953 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1954 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 1955 // CHECK3-NEXT: [[K:%.*]] = alloca i64, align 8 1956 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1957 // CHECK3-NEXT: [[LIN:%.*]] = alloca i32, align 4 1958 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1959 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 1960 // CHECK3-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 1961 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 1962 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 1963 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 1964 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 1965 // CHECK3-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 1966 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 1967 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 1968 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 1969 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 1970 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1971 // CHECK3-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 1972 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1973 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4 1974 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4 1975 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4 1976 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 1977 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 1978 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1979 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 1980 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 1981 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1982 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1983 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 1984 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 1985 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 1986 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 1987 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 1988 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 1989 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 1990 // CHECK3-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 1991 // CHECK3-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 1992 // CHECK3-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1993 // CHECK3: omp_offload.failed: 1994 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 1995 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1996 // CHECK3: omp_offload.cont: 1997 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 1998 // CHECK3-NEXT: store i64 [[CALL]], i64* [[K]], align 8 1999 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 2000 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 2001 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4 2002 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR4]] 2003 // CHECK3-NEXT: store i32 12, i32* [[LIN]], align 4 2004 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 2005 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2006 // CHECK3-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 2007 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2008 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4 2009 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4 2010 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 2011 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 2012 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4 2013 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4 2014 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2015 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 2016 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4 2017 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2018 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 2019 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4 2020 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2021 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 2022 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2023 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 2024 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4 2025 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2026 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 2027 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4 2028 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2029 // CHECK3-NEXT: store i8* null, i8** [[TMP24]], align 4 2030 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2031 // CHECK3-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 2032 // CHECK3-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4 2033 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2034 // CHECK3-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 2035 // CHECK3-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4 2036 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2037 // CHECK3-NEXT: store i8* null, i8** [[TMP29]], align 4 2038 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2039 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2040 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 2041 // CHECK3-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 2042 // CHECK3-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 2043 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 2044 // CHECK3-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4 2045 // CHECK3-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 2046 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 2047 // CHECK3-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4 2048 // CHECK3-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 2049 // CHECK3-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 2050 // CHECK3-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 2051 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 2052 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 2053 // CHECK3-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4 2054 // CHECK3-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 2055 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false) 2056 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 2057 // CHECK3-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 2058 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 2059 // CHECK3-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8* 2060 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 2061 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 2062 // CHECK3-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8* 2063 // CHECK3-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8* 2064 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false) 2065 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 2066 // CHECK3-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8* 2067 // CHECK3-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8* 2068 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false) 2069 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 2070 // CHECK3-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 2071 // CHECK3-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4 2072 // CHECK3-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) 2073 // CHECK3-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 2074 // CHECK3-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4 2075 // CHECK3-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4 2076 // CHECK3-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 2077 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 2078 // CHECK3-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2 2079 // CHECK3-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 2080 // CHECK3-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4 2081 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10 2082 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2083 // CHECK3: omp_if.then: 2084 // CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 2085 // CHECK3-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* 2086 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4 2087 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 2088 // CHECK3-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32* 2089 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4 2090 // CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 2091 // CHECK3-NEXT: store i8* null, i8** [[TMP66]], align 4 2092 // CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 2093 // CHECK3-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32* 2094 // CHECK3-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4 2095 // CHECK3-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 2096 // CHECK3-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32* 2097 // CHECK3-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4 2098 // CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 2099 // CHECK3-NEXT: store i8* null, i8** [[TMP71]], align 4 2100 // CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 2101 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 2102 // CHECK3-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2103 // CHECK3-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0 2104 // CHECK3-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 2105 // CHECK3: omp_offload.failed9: 2106 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 2107 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT10]] 2108 // CHECK3: omp_offload.cont10: 2109 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2110 // CHECK3: omp_if.else: 2111 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 2112 // CHECK3-NEXT: br label [[OMP_IF_END]] 2113 // CHECK3: omp_if.end: 2114 // CHECK3-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4 2115 // CHECK3-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4 2116 // CHECK3-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4 2117 // CHECK3-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4 2118 // CHECK3-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4 2119 // CHECK3-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2120 // CHECK3-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 2121 // CHECK3-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 2122 // CHECK3-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4 2123 // CHECK3-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20 2124 // CHECK3-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]] 2125 // CHECK3: omp_if.then13: 2126 // CHECK3-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4 2127 // CHECK3-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64 2128 // CHECK3-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]] 2129 // CHECK3-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8 2130 // CHECK3-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64 2131 // CHECK3-NEXT: [[TMP87:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2132 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP87]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i32 80, i1 false) 2133 // CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 2134 // CHECK3-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32* 2135 // CHECK3-NEXT: store i32 [[TMP78]], i32* [[TMP89]], align 4 2136 // CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 2137 // CHECK3-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32* 2138 // CHECK3-NEXT: store i32 [[TMP78]], i32* [[TMP91]], align 4 2139 // CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 2140 // CHECK3-NEXT: store i8* null, i8** [[TMP92]], align 4 2141 // CHECK3-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 2142 // CHECK3-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]** 2143 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4 2144 // CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 2145 // CHECK3-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 2146 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4 2147 // CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 2148 // CHECK3-NEXT: store i8* null, i8** [[TMP97]], align 4 2149 // CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 2150 // CHECK3-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* 2151 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP99]], align 4 2152 // CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 2153 // CHECK3-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32* 2154 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP101]], align 4 2155 // CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 2156 // CHECK3-NEXT: store i8* null, i8** [[TMP102]], align 4 2157 // CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 2158 // CHECK3-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to float** 2159 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP104]], align 4 2160 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 2161 // CHECK3-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** 2162 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP106]], align 4 2163 // CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 2164 // CHECK3-NEXT: store i64 [[TMP83]], i64* [[TMP107]], align 4 2165 // CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 2166 // CHECK3-NEXT: store i8* null, i8** [[TMP108]], align 4 2167 // CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 2168 // CHECK3-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to [5 x [10 x double]]** 2169 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP110]], align 4 2170 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 2171 // CHECK3-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** 2172 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4 2173 // CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 2174 // CHECK3-NEXT: store i8* null, i8** [[TMP113]], align 4 2175 // CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 2176 // CHECK3-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32* 2177 // CHECK3-NEXT: store i32 5, i32* [[TMP115]], align 4 2178 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 2179 // CHECK3-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32* 2180 // CHECK3-NEXT: store i32 5, i32* [[TMP117]], align 4 2181 // CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 2182 // CHECK3-NEXT: store i8* null, i8** [[TMP118]], align 4 2183 // CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 2184 // CHECK3-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32* 2185 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP120]], align 4 2186 // CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 2187 // CHECK3-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32* 2188 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP122]], align 4 2189 // CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 2190 // CHECK3-NEXT: store i8* null, i8** [[TMP123]], align 4 2191 // CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 2192 // CHECK3-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to double** 2193 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP125]], align 4 2194 // CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 2195 // CHECK3-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** 2196 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP127]], align 4 2197 // CHECK3-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 2198 // CHECK3-NEXT: store i64 [[TMP86]], i64* [[TMP128]], align 4 2199 // CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 2200 // CHECK3-NEXT: store i8* null, i8** [[TMP129]], align 4 2201 // CHECK3-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 2202 // CHECK3-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to %struct.TT** 2203 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP131]], align 4 2204 // CHECK3-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 2205 // CHECK3-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT** 2206 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 4 2207 // CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 2208 // CHECK3-NEXT: store i8* null, i8** [[TMP134]], align 4 2209 // CHECK3-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 2210 // CHECK3-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to i32* 2211 // CHECK3-NEXT: store i32 [[TMP80]], i32* [[TMP136]], align 4 2212 // CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 2213 // CHECK3-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i32* 2214 // CHECK3-NEXT: store i32 [[TMP80]], i32* [[TMP138]], align 4 2215 // CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 2216 // CHECK3-NEXT: store i8* null, i8** [[TMP139]], align 4 2217 // CHECK3-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 2218 // CHECK3-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 2219 // CHECK3-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2220 // CHECK3-NEXT: [[TMP143:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP140]], i8** [[TMP141]], i64* [[TMP142]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2221 // CHECK3-NEXT: [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 0 2222 // CHECK3-NEXT: br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] 2223 // CHECK3: omp_offload.failed17: 2224 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 2225 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT18]] 2226 // CHECK3: omp_offload.cont18: 2227 // CHECK3-NEXT: br label [[OMP_IF_END20:%.*]] 2228 // CHECK3: omp_if.else19: 2229 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 2230 // CHECK3-NEXT: br label [[OMP_IF_END20]] 2231 // CHECK3: omp_if.end20: 2232 // CHECK3-NEXT: [[TMP145:%.*]] = load i32, i32* [[A]], align 4 2233 // CHECK3-NEXT: [[TMP146:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2234 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP146]]) 2235 // CHECK3-NEXT: ret i32 [[TMP145]] 2236 // 2237 // 2238 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 2239 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] { 2240 // CHECK3-NEXT: entry: 2241 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2242 // CHECK3-NEXT: ret void 2243 // 2244 // 2245 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 2246 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 2247 // CHECK3-NEXT: entry: 2248 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2249 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2250 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2251 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2252 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2253 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2254 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2255 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2256 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2257 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2258 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2259 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2260 // CHECK3-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 2261 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2262 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2263 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2264 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2265 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2266 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2267 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 2268 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2269 // CHECK3: cond.true: 2270 // CHECK3-NEXT: br label [[COND_END:%.*]] 2271 // CHECK3: cond.false: 2272 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2273 // CHECK3-NEXT: br label [[COND_END]] 2274 // CHECK3: cond.end: 2275 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2276 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2277 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2278 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2279 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2280 // CHECK3: omp.inner.for.cond: 2281 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2282 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2283 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2284 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2285 // CHECK3: omp.inner.for.body: 2286 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2287 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 2288 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 2289 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2290 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 2291 // CHECK3-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 2292 // CHECK3-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 2293 // CHECK3: .cancel.exit: 2294 // CHECK3-NEXT: br label [[CANCEL_EXIT:%.*]] 2295 // CHECK3: .cancel.continue: 2296 // CHECK3-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 2297 // CHECK3-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 2298 // CHECK3-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 2299 // CHECK3: .cancel.exit2: 2300 // CHECK3-NEXT: br label [[CANCEL_EXIT]] 2301 // CHECK3: .cancel.continue3: 2302 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2303 // CHECK3: omp.body.continue: 2304 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2305 // CHECK3: omp.inner.for.inc: 2306 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2307 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 2308 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 2309 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2310 // CHECK3: omp.inner.for.end: 2311 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2312 // CHECK3: omp.loop.exit: 2313 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2314 // CHECK3-NEXT: br label [[CANCEL_CONT:%.*]] 2315 // CHECK3: cancel.cont: 2316 // CHECK3-NEXT: ret void 2317 // CHECK3: cancel.exit: 2318 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2319 // CHECK3-NEXT: br label [[CANCEL_CONT]] 2320 // 2321 // 2322 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 2323 // CHECK3-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 2324 // CHECK3-NEXT: entry: 2325 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2326 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 2327 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2328 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2329 // CHECK3-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 2330 // CHECK3-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 2331 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2332 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 2333 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 2334 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) 2335 // CHECK3-NEXT: ret void 2336 // 2337 // 2338 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 2339 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 2340 // CHECK3-NEXT: entry: 2341 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2342 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2343 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2344 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 2345 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2346 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2347 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 2348 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2349 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2350 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2351 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2352 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2353 // CHECK3-NEXT: [[K1:%.*]] = alloca i64, align 8 2354 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2355 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2356 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2357 // CHECK3-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 2358 // CHECK3-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 2359 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 2360 // CHECK3-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 2361 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2362 // CHECK3-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 2363 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2364 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2365 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2366 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2367 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 2368 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1) 2369 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2370 // CHECK3: omp.dispatch.cond: 2371 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 2372 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 2373 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2374 // CHECK3: omp.dispatch.body: 2375 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2376 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 2377 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2378 // CHECK3: omp.inner.for.cond: 2379 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 2380 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 2381 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 2382 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2383 // CHECK3: omp.inner.for.body: 2384 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 2385 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 2386 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 2387 // CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13 2388 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !13 2389 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 2390 // CHECK3-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 2391 // CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 2392 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 2393 // CHECK3-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13 2394 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !13 2395 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 2396 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13 2397 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2398 // CHECK3: omp.body.continue: 2399 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2400 // CHECK3: omp.inner.for.inc: 2401 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 2402 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 2403 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 2404 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 2405 // CHECK3: omp.inner.for.end: 2406 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2407 // CHECK3: omp.dispatch.inc: 2408 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2409 // CHECK3: omp.dispatch.end: 2410 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2411 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 2412 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 2413 // CHECK3: .omp.linear.pu: 2414 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[K1]], align 8 2415 // CHECK3-NEXT: store i64 [[TMP15]], i64* [[TMP0]], align 8 2416 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 2417 // CHECK3: .omp.linear.pu.done: 2418 // CHECK3-NEXT: ret void 2419 // 2420 // 2421 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 2422 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 2423 // CHECK3-NEXT: entry: 2424 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2425 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 2426 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2427 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2428 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 2429 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2430 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2431 // CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 2432 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2433 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2434 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2435 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2436 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 2437 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2438 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 2439 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 2440 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 2441 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 2442 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 2443 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 2444 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 2445 // CHECK3-NEXT: ret void 2446 // 2447 // 2448 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 2449 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 2450 // CHECK3-NEXT: entry: 2451 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2452 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2453 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2454 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 2455 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2456 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2457 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 2458 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 2459 // CHECK3-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 2460 // CHECK3-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 2461 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2462 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2463 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2464 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2465 // CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8 2466 // CHECK3-NEXT: [[LIN2:%.*]] = alloca i32, align 4 2467 // CHECK3-NEXT: [[A3:%.*]] = alloca i32, align 4 2468 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2469 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2470 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2471 // CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 2472 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2473 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2474 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 2475 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 2476 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2477 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 2478 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 2479 // CHECK3-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 2480 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2481 // CHECK3-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 2482 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2483 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2484 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2485 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2486 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 2487 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 2488 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2489 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 2490 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2491 // CHECK3: cond.true: 2492 // CHECK3-NEXT: br label [[COND_END:%.*]] 2493 // CHECK3: cond.false: 2494 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2495 // CHECK3-NEXT: br label [[COND_END]] 2496 // CHECK3: cond.end: 2497 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2498 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 2499 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2500 // CHECK3-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 2501 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2502 // CHECK3: omp.inner.for.cond: 2503 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2504 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2505 // CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 2506 // CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2507 // CHECK3: omp.inner.for.body: 2508 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2509 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 2510 // CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 2511 // CHECK3-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 2512 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 2513 // CHECK3-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 2514 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2515 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 2516 // CHECK3-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 2517 // CHECK3-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 2518 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 2519 // CHECK3-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 2520 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 2521 // CHECK3-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 2522 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2523 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 2524 // CHECK3-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 2525 // CHECK3-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 2526 // CHECK3-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 2527 // CHECK3-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 2528 // CHECK3-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 2529 // CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 2530 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 2531 // CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 2532 // CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 2533 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2534 // CHECK3: omp.body.continue: 2535 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2536 // CHECK3: omp.inner.for.inc: 2537 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2538 // CHECK3-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 2539 // CHECK3-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 2540 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2541 // CHECK3: omp.inner.for.end: 2542 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2543 // CHECK3: omp.loop.exit: 2544 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 2545 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2546 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 2547 // CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 2548 // CHECK3: .omp.linear.pu: 2549 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 2550 // CHECK3-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 2551 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 2552 // CHECK3-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 2553 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 2554 // CHECK3: .omp.linear.pu.done: 2555 // CHECK3-NEXT: ret void 2556 // 2557 // 2558 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. 2559 // CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 2560 // CHECK3-NEXT: entry: 2561 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 2562 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 2563 // CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 2564 // CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 2565 // CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 2566 // CHECK3-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 2567 // CHECK3-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 2568 // CHECK3-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 2569 // CHECK3-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 2570 // CHECK3-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 2571 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 2572 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 2573 // CHECK3-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 2574 // CHECK3-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 2575 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 2576 // CHECK3-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 2577 // CHECK3-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 2578 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 2579 // CHECK3-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 2580 // CHECK3-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 2581 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 2582 // CHECK3-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 2583 // CHECK3-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 2584 // CHECK3-NEXT: ret void 2585 // 2586 // 2587 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 2588 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 2589 // CHECK3-NEXT: entry: 2590 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 2591 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 2592 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 2593 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 2594 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 2595 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 2596 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 2597 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 2598 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 2599 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 2600 // CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 2601 // CHECK3-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4 2602 // CHECK3-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4 2603 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 2604 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 2605 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 2606 // CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 2607 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 2608 // CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 2609 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 2610 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 2611 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 2612 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 2613 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 2614 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 2615 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 2616 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 2617 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 2618 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 2619 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 2620 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 2621 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 2622 // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 2623 // CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 2624 // CHECK3-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 2625 // CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 2626 // CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 2627 // CHECK3-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 2628 // CHECK3-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 2629 // CHECK3-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 2630 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 2631 // CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 2632 // CHECK3-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 2633 // CHECK3-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 2634 // CHECK3-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 2635 // CHECK3-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 2636 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 2637 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 2638 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 2639 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 2640 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 2641 // CHECK3-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 2642 // CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 2643 // CHECK3-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 2644 // CHECK3: omp_offload.failed.i: 2645 // CHECK3-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 2646 // CHECK3-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 2647 // CHECK3-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25 2648 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 2649 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 2650 // CHECK3-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25 2651 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !25 2652 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 2653 // CHECK3-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25 2654 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !25 2655 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR4]] 2656 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 2657 // CHECK3: .omp_outlined..3.exit: 2658 // CHECK3-NEXT: ret i32 0 2659 // 2660 // 2661 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 2662 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2663 // CHECK3-NEXT: entry: 2664 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2665 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2666 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2667 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2668 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2669 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2670 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2671 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2672 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2673 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2674 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 2675 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2676 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 2677 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2678 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 2679 // CHECK3-NEXT: ret void 2680 // 2681 // 2682 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 2683 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 2684 // CHECK3-NEXT: entry: 2685 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2686 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2687 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2688 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2689 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2690 // CHECK3-NEXT: [[TMP:%.*]] = alloca i16, align 2 2691 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2692 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2693 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2694 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2695 // CHECK3-NEXT: [[IT:%.*]] = alloca i16, align 2 2696 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2697 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2698 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2699 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2700 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2701 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2702 // CHECK3-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 2703 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2704 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2705 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2706 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2707 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2708 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2709 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 2710 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2711 // CHECK3: cond.true: 2712 // CHECK3-NEXT: br label [[COND_END:%.*]] 2713 // CHECK3: cond.false: 2714 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2715 // CHECK3-NEXT: br label [[COND_END]] 2716 // CHECK3: cond.end: 2717 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2718 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2719 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2720 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2721 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2722 // CHECK3: omp.inner.for.cond: 2723 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2724 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2725 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2726 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2727 // CHECK3: omp.inner.for.body: 2728 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2729 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 2730 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 2731 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 2732 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 2733 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 2734 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 2735 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 2736 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 2737 // CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 2738 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 2739 // CHECK3-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 2740 // CHECK3-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 2741 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2742 // CHECK3: omp.body.continue: 2743 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2744 // CHECK3: omp.inner.for.inc: 2745 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2746 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 2747 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 2748 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2749 // CHECK3: omp.inner.for.end: 2750 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2751 // CHECK3: omp.loop.exit: 2752 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2753 // CHECK3-NEXT: ret void 2754 // 2755 // 2756 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 2757 // CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 2758 // CHECK3-NEXT: entry: 2759 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2760 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2761 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2762 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2763 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2764 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2765 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2766 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2767 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2768 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2769 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2770 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 2771 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2772 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2773 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2774 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2775 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2776 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2777 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2778 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2779 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2780 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2781 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2782 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2783 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2784 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2785 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2786 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2787 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2788 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2789 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 2790 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 2791 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 2792 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2793 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 2794 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 2795 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 2796 // CHECK3-NEXT: ret void 2797 // 2798 // 2799 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 2800 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 2801 // CHECK3-NEXT: entry: 2802 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2803 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2804 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2805 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2806 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2807 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2808 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2809 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2810 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2811 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2812 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2813 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2814 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2815 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 2816 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2817 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2818 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2819 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2820 // CHECK3-NEXT: [[IT:%.*]] = alloca i8, align 1 2821 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2822 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2823 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2824 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2825 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2826 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2827 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2828 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2829 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2830 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2831 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2832 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2833 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2834 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2835 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2836 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2837 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2838 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2839 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2840 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2841 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2842 // CHECK3-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 2843 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2844 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2845 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2846 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2847 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 2848 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 2849 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2850 // CHECK3: omp.dispatch.cond: 2851 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2852 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 2853 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2854 // CHECK3: cond.true: 2855 // CHECK3-NEXT: br label [[COND_END:%.*]] 2856 // CHECK3: cond.false: 2857 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2858 // CHECK3-NEXT: br label [[COND_END]] 2859 // CHECK3: cond.end: 2860 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 2861 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2862 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2863 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 2864 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2865 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2866 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 2867 // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2868 // CHECK3: omp.dispatch.body: 2869 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2870 // CHECK3: omp.inner.for.cond: 2871 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2872 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2873 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 2874 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2875 // CHECK3: omp.inner.for.body: 2876 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2877 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 2878 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 2879 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 2880 // CHECK3-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 2881 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 2882 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 2883 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2884 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 2885 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 2886 // CHECK3-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 2887 // CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 2888 // CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 2889 // CHECK3-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 2890 // CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 2891 // CHECK3-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 2892 // CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 2893 // CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 2894 // CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 2895 // CHECK3-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 2896 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 2897 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 2898 // CHECK3-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 2899 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 2900 // CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 2901 // CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 2902 // CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 2903 // CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 2904 // CHECK3-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 2905 // CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 2906 // CHECK3-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 2907 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 2908 // CHECK3-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 2909 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 2910 // CHECK3-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 2911 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 2912 // CHECK3-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 2913 // CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 2914 // CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 2915 // CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 2916 // CHECK3-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 2917 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2918 // CHECK3: omp.body.continue: 2919 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2920 // CHECK3: omp.inner.for.inc: 2921 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2922 // CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 2923 // CHECK3-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 2924 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2925 // CHECK3: omp.inner.for.end: 2926 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2927 // CHECK3: omp.dispatch.inc: 2928 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2929 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2930 // CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 2931 // CHECK3-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 2932 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2933 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2934 // CHECK3-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 2935 // CHECK3-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 2936 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2937 // CHECK3: omp.dispatch.end: 2938 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 2939 // CHECK3-NEXT: ret void 2940 // 2941 // 2942 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 2943 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2944 // CHECK3-NEXT: entry: 2945 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2946 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2947 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 2948 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2949 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2950 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2951 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 2952 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2953 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2954 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2955 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2956 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 2957 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2958 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2959 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2960 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2961 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 2962 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2963 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2964 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2965 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2966 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 2967 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 2968 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 2969 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 2970 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 2971 // CHECK3-NEXT: ret i32 [[TMP8]] 2972 // 2973 // 2974 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2975 // CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2976 // CHECK3-NEXT: entry: 2977 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2978 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2979 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 2980 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2981 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2982 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2983 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 2984 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 2985 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 2986 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 2987 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2988 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2989 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2990 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2991 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2992 // CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4 2993 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2994 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2995 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 2996 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 2997 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 2998 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 2999 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 3000 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3001 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3002 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3003 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 3004 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3005 // CHECK3: omp_if.then: 3006 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3007 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 3008 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 3009 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 3010 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 3011 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false) 3012 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3013 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 3014 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 3015 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3016 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 3017 // CHECK3-NEXT: store double* [[A]], double** [[TMP14]], align 4 3018 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3019 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4 3020 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3021 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 3022 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 3023 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3024 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 3025 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 3026 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3027 // CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4 3028 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3029 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 3030 // CHECK3-NEXT: store i32 2, i32* [[TMP22]], align 4 3031 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3032 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 3033 // CHECK3-NEXT: store i32 2, i32* [[TMP24]], align 4 3034 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3035 // CHECK3-NEXT: store i8* null, i8** [[TMP25]], align 4 3036 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3037 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 3038 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 3039 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3040 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 3041 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 3042 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3043 // CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4 3044 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3045 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 3046 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 3047 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3048 // CHECK3-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 3049 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 3050 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3051 // CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 3052 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 3053 // CHECK3-NEXT: store i8* null, i8** [[TMP36]], align 4 3054 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3055 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3056 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3057 // CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3058 // CHECK3-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 3059 // CHECK3-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3060 // CHECK3: omp_offload.failed: 3061 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 3062 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3063 // CHECK3: omp_offload.cont: 3064 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3065 // CHECK3: omp_if.else: 3066 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 3067 // CHECK3-NEXT: br label [[OMP_IF_END]] 3068 // CHECK3: omp_if.end: 3069 // CHECK3-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 3070 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 3071 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 3072 // CHECK3-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 3073 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 3074 // CHECK3-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 3075 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 3076 // CHECK3-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 3077 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 3078 // CHECK3-NEXT: ret i32 [[ADD3]] 3079 // 3080 // 3081 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 3082 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 3083 // CHECK3-NEXT: entry: 3084 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3085 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3086 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3087 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 3088 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3089 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3090 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3091 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3092 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 3093 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 3094 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 3095 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3096 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3097 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 3098 // CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1 3099 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 3100 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3101 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3102 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 3103 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3104 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 3105 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3106 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 3107 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 3108 // CHECK3-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 3109 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 3110 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3111 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 3112 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3113 // CHECK3: omp_if.then: 3114 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3115 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 3116 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 3117 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3118 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 3119 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 3120 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3121 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4 3122 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3123 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 3124 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 3125 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3126 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 3127 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 3128 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3129 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4 3130 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3131 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 3132 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 3133 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3134 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 3135 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 3136 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3137 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 3138 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3139 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 3140 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 3141 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3142 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 3143 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 3144 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3145 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4 3146 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3147 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3148 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3149 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 3150 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3151 // CHECK3: omp_offload.failed: 3152 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 3153 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3154 // CHECK3: omp_offload.cont: 3155 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3156 // CHECK3: omp_if.else: 3157 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 3158 // CHECK3-NEXT: br label [[OMP_IF_END]] 3159 // CHECK3: omp_if.end: 3160 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 3161 // CHECK3-NEXT: ret i32 [[TMP31]] 3162 // 3163 // 3164 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3165 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 3166 // CHECK3-NEXT: entry: 3167 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3168 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3169 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3170 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3171 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3172 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3173 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 3174 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 3175 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 3176 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3177 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3178 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 3179 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 3180 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3181 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3182 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 3183 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3184 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 3185 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3186 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3187 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 3188 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3189 // CHECK3: omp_if.then: 3190 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3191 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 3192 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 3193 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3194 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 3195 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 3196 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3197 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 3198 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3199 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 3200 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 3201 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3202 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 3203 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 3204 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3205 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 3206 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3207 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 3208 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 3209 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3210 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 3211 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 3212 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3213 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 3214 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3215 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3216 // CHECK3-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3217 // CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 3218 // CHECK3-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3219 // CHECK3: omp_offload.failed: 3220 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 3221 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3222 // CHECK3: omp_offload.cont: 3223 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3224 // CHECK3: omp_if.else: 3225 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 3226 // CHECK3-NEXT: br label [[OMP_IF_END]] 3227 // CHECK3: omp_if.end: 3228 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 3229 // CHECK3-NEXT: ret i32 [[TMP24]] 3230 // 3231 // 3232 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 3233 // CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3234 // CHECK3-NEXT: entry: 3235 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3236 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3237 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3238 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3239 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3240 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3241 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3242 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3243 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3244 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3245 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3246 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3247 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3248 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3249 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3250 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 3251 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3252 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3253 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 3254 // CHECK3-NEXT: ret void 3255 // 3256 // 3257 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 3258 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 3259 // CHECK3-NEXT: entry: 3260 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3261 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3262 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3263 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3264 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3265 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3266 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3267 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3268 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 3269 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3270 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3271 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3272 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3273 // CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8 3274 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3275 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3276 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3277 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3278 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3279 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3280 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3281 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3282 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3283 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3284 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3285 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3286 // CHECK3-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 3287 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3288 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3289 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3290 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3291 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 3292 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3293 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 3294 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3295 // CHECK3: cond.true: 3296 // CHECK3-NEXT: br label [[COND_END:%.*]] 3297 // CHECK3: cond.false: 3298 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3299 // CHECK3-NEXT: br label [[COND_END]] 3300 // CHECK3: cond.end: 3301 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3302 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 3303 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3304 // CHECK3-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 3305 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3306 // CHECK3: omp.inner.for.cond: 3307 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3308 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3309 // CHECK3-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 3310 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3311 // CHECK3: omp.inner.for.body: 3312 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3313 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 3314 // CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 3315 // CHECK3-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 3316 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 3317 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 3318 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3319 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3320 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4 3321 // CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 3322 // CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 3323 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 3324 // CHECK3-NEXT: store double [[INC]], double* [[A4]], align 4 3325 // CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 3326 // CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 3327 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 3328 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 3329 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 3330 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3331 // CHECK3: omp.body.continue: 3332 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3333 // CHECK3: omp.inner.for.inc: 3334 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3335 // CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 3336 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 3337 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 3338 // CHECK3: omp.inner.for.end: 3339 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3340 // CHECK3: omp.loop.exit: 3341 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 3342 // CHECK3-NEXT: ret void 3343 // 3344 // 3345 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 3346 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3347 // CHECK3-NEXT: entry: 3348 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3349 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3350 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3351 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3352 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3353 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3354 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3355 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3356 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3357 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3358 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3359 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3360 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3361 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3362 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3363 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3364 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3365 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3366 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3367 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 3368 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3369 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 3370 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 3371 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 3372 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 3373 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 3374 // CHECK3-NEXT: ret void 3375 // 3376 // 3377 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 3378 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3379 // CHECK3-NEXT: entry: 3380 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3381 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3382 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3383 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3384 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3385 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3386 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3387 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3388 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3389 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3390 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3391 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3392 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3393 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3394 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3395 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3396 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3397 // CHECK3-NEXT: ret void 3398 // 3399 // 3400 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 3401 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3402 // CHECK3-NEXT: entry: 3403 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3404 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3405 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3406 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3407 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3408 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3409 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3410 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3411 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3412 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3413 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3414 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3415 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3416 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3417 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3418 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 3419 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3420 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 3421 // CHECK3-NEXT: ret void 3422 // 3423 // 3424 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 3425 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3426 // CHECK3-NEXT: entry: 3427 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3428 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3429 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3430 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3431 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3432 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3433 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 3434 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3435 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3436 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3437 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3438 // CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 3439 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3440 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3441 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3442 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3443 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3444 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3445 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3446 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3447 // CHECK3-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 3448 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3449 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3450 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3451 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 3452 // CHECK3-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 3453 // CHECK3-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3454 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 3455 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3456 // CHECK3: cond.true: 3457 // CHECK3-NEXT: br label [[COND_END:%.*]] 3458 // CHECK3: cond.false: 3459 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3460 // CHECK3-NEXT: br label [[COND_END]] 3461 // CHECK3: cond.end: 3462 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 3463 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 3464 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3465 // CHECK3-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 3466 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3467 // CHECK3: omp.inner.for.cond: 3468 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3469 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3470 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 3471 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3472 // CHECK3: omp.inner.for.body: 3473 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3474 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 3475 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 3476 // CHECK3-NEXT: store i64 [[ADD]], i64* [[I]], align 8 3477 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 3478 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 3479 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 3480 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 3481 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 3482 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 3483 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 3484 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 3485 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 3486 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3487 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 3488 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 3489 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3490 // CHECK3: omp.body.continue: 3491 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3492 // CHECK3: omp.inner.for.inc: 3493 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3494 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 3495 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 3496 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 3497 // CHECK3: omp.inner.for.end: 3498 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3499 // CHECK3: omp.loop.exit: 3500 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 3501 // CHECK3-NEXT: ret void 3502 // 3503 // 3504 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3505 // CHECK3-SAME: () #[[ATTR6]] { 3506 // CHECK3-NEXT: entry: 3507 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 3508 // CHECK3-NEXT: ret void 3509 // 3510 // 3511 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 3512 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 3513 // CHECK9-NEXT: entry: 3514 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 3515 // CHECK9-NEXT: ret void 3516 // 3517 // 3518 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 3519 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 3520 // CHECK9-NEXT: entry: 3521 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3522 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3523 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3524 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 3525 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3526 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3527 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3528 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3529 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 3530 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3531 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3532 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3533 // CHECK9-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 3534 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3535 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3536 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3537 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3538 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3539 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3540 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 3541 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3542 // CHECK9: cond.true: 3543 // CHECK9-NEXT: br label [[COND_END:%.*]] 3544 // CHECK9: cond.false: 3545 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3546 // CHECK9-NEXT: br label [[COND_END]] 3547 // CHECK9: cond.end: 3548 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3549 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3550 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3551 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 3552 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3553 // CHECK9: omp.inner.for.cond: 3554 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3555 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3556 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3557 // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3558 // CHECK9: omp.inner.for.body: 3559 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3560 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 3561 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 3562 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3563 // CHECK9-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 3564 // CHECK9-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 3565 // CHECK9-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 3566 // CHECK9: .cancel.exit: 3567 // CHECK9-NEXT: br label [[CANCEL_EXIT:%.*]] 3568 // CHECK9: .cancel.continue: 3569 // CHECK9-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 3570 // CHECK9-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 3571 // CHECK9-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 3572 // CHECK9: .cancel.exit2: 3573 // CHECK9-NEXT: br label [[CANCEL_EXIT]] 3574 // CHECK9: .cancel.continue3: 3575 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3576 // CHECK9: omp.body.continue: 3577 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3578 // CHECK9: omp.inner.for.inc: 3579 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3580 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 3581 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 3582 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 3583 // CHECK9: omp.inner.for.end: 3584 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3585 // CHECK9: omp.loop.exit: 3586 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 3587 // CHECK9-NEXT: br label [[CANCEL_CONT:%.*]] 3588 // CHECK9: cancel.cont: 3589 // CHECK9-NEXT: ret void 3590 // CHECK9: cancel.exit: 3591 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 3592 // CHECK9-NEXT: br label [[CANCEL_CONT]] 3593 // 3594 // 3595 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 3596 // CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 3597 // CHECK9-NEXT: entry: 3598 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3599 // CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 3600 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3601 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3602 // CHECK9-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 3603 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3604 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3605 // CHECK9-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 3606 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3607 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3608 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 3609 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3610 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 3611 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3612 // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 3613 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3614 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 3615 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 3616 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 3617 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 3618 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 3619 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3620 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 3621 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 3622 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 3623 // CHECK9-NEXT: ret void 3624 // 3625 // 3626 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 3627 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 3628 // CHECK9-NEXT: entry: 3629 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3630 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3631 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3632 // CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 3633 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3634 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3635 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 3636 // CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 3637 // CHECK9-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 3638 // CHECK9-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 3639 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3640 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3641 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3642 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3643 // CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8 3644 // CHECK9-NEXT: [[LIN4:%.*]] = alloca i32, align 4 3645 // CHECK9-NEXT: [[A5:%.*]] = alloca i32, align 4 3646 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3647 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3648 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3649 // CHECK9-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 3650 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3651 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3652 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 3653 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3654 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 3655 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 3656 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 3657 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 3658 // CHECK9-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 3659 // CHECK9-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 3660 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3661 // CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 3662 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3663 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3664 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3665 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 3666 // CHECK9-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 3667 // CHECK9-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 3668 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3669 // CHECK9-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 3670 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3671 // CHECK9: cond.true: 3672 // CHECK9-NEXT: br label [[COND_END:%.*]] 3673 // CHECK9: cond.false: 3674 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3675 // CHECK9-NEXT: br label [[COND_END]] 3676 // CHECK9: cond.end: 3677 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 3678 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 3679 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3680 // CHECK9-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 3681 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3682 // CHECK9: omp.inner.for.cond: 3683 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3684 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3685 // CHECK9-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 3686 // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3687 // CHECK9: omp.inner.for.body: 3688 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3689 // CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 3690 // CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 3691 // CHECK9-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 3692 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 3693 // CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 3694 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3695 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 3696 // CHECK9-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 3697 // CHECK9-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 3698 // CHECK9-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 3699 // CHECK9-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 3700 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 3701 // CHECK9-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 3702 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3703 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 3704 // CHECK9-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 3705 // CHECK9-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 3706 // CHECK9-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 3707 // CHECK9-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 3708 // CHECK9-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 3709 // CHECK9-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 3710 // CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 3711 // CHECK9-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 3712 // CHECK9-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 3713 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3714 // CHECK9: omp.body.continue: 3715 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3716 // CHECK9: omp.inner.for.inc: 3717 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3718 // CHECK9-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 3719 // CHECK9-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 3720 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 3721 // CHECK9: omp.inner.for.end: 3722 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3723 // CHECK9: omp.loop.exit: 3724 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 3725 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3726 // CHECK9-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 3727 // CHECK9-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 3728 // CHECK9: .omp.linear.pu: 3729 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 3730 // CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 3731 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 3732 // CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 3733 // CHECK9-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 3734 // CHECK9: .omp.linear.pu.done: 3735 // CHECK9-NEXT: ret void 3736 // 3737 // 3738 // CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv 3739 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 3740 // CHECK9-NEXT: entry: 3741 // CHECK9-NEXT: ret i64 0 3742 // 3743 // 3744 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 3745 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3746 // CHECK9-NEXT: entry: 3747 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3748 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3749 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3750 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3751 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3752 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3753 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3754 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3755 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 3756 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3757 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 3758 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 3759 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 3760 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3761 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 3762 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3763 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 3764 // CHECK9-NEXT: ret void 3765 // 3766 // 3767 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 3768 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 3769 // CHECK9-NEXT: entry: 3770 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3771 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3772 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3773 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3774 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3775 // CHECK9-NEXT: [[TMP:%.*]] = alloca i16, align 2 3776 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3777 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3778 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3779 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3780 // CHECK9-NEXT: [[IT:%.*]] = alloca i16, align 2 3781 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3782 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3783 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3784 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3785 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3786 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3787 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3788 // CHECK9-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 3789 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3790 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3791 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3792 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3793 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3794 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3795 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 3796 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3797 // CHECK9: cond.true: 3798 // CHECK9-NEXT: br label [[COND_END:%.*]] 3799 // CHECK9: cond.false: 3800 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3801 // CHECK9-NEXT: br label [[COND_END]] 3802 // CHECK9: cond.end: 3803 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3804 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3805 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3806 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 3807 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3808 // CHECK9: omp.inner.for.cond: 3809 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3810 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3811 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3812 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3813 // CHECK9: omp.inner.for.body: 3814 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3815 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 3816 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 3817 // CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 3818 // CHECK9-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 3819 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 3820 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 3821 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 3822 // CHECK9-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 3823 // CHECK9-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 3824 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 3825 // CHECK9-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 3826 // CHECK9-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 3827 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3828 // CHECK9: omp.body.continue: 3829 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3830 // CHECK9: omp.inner.for.inc: 3831 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3832 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 3833 // CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 3834 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 3835 // CHECK9: omp.inner.for.end: 3836 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3837 // CHECK9: omp.loop.exit: 3838 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 3839 // CHECK9-NEXT: ret void 3840 // 3841 // 3842 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 3843 // CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 3844 // CHECK9-NEXT: entry: 3845 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3846 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 3847 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3848 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 3849 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 3850 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 3851 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 3852 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 3853 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 3854 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3855 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3856 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3857 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3858 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 3859 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3860 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 3861 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 3862 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 3863 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 3864 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 3865 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 3866 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 3867 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3868 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 3869 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3870 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 3871 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 3872 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 3873 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 3874 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 3875 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 3876 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 3877 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 3878 // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3879 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 3880 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 3881 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 3882 // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 3883 // CHECK9-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 3884 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 3885 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 3886 // CHECK9-NEXT: ret void 3887 // 3888 // 3889 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 3890 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 3891 // CHECK9-NEXT: entry: 3892 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3893 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3894 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3895 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 3896 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3897 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 3898 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 3899 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 3900 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 3901 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 3902 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 3903 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3904 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3905 // CHECK9-NEXT: [[TMP:%.*]] = alloca i8, align 1 3906 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3907 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3908 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3909 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3910 // CHECK9-NEXT: [[IT:%.*]] = alloca i8, align 1 3911 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3912 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3913 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3914 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 3915 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3916 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 3917 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 3918 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 3919 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 3920 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 3921 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 3922 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 3923 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3924 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 3925 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3926 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 3927 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 3928 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 3929 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 3930 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 3931 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 3932 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 3933 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3934 // CHECK9-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 3935 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3936 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3937 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 3938 // CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3939 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 3940 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 3941 // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3942 // CHECK9: omp.dispatch.cond: 3943 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3944 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 3945 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3946 // CHECK9: cond.true: 3947 // CHECK9-NEXT: br label [[COND_END:%.*]] 3948 // CHECK9: cond.false: 3949 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3950 // CHECK9-NEXT: br label [[COND_END]] 3951 // CHECK9: cond.end: 3952 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 3953 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3954 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3955 // CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 3956 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3957 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3958 // CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 3959 // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3960 // CHECK9: omp.dispatch.body: 3961 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3962 // CHECK9: omp.inner.for.cond: 3963 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3964 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3965 // CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 3966 // CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3967 // CHECK9: omp.inner.for.body: 3968 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3969 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 3970 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 3971 // CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 3972 // CHECK9-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 3973 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 3974 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 3975 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 3976 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 3977 // CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 3978 // CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 3979 // CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 3980 // CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 3981 // CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 3982 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 3983 // CHECK9-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 3984 // CHECK9-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 3985 // CHECK9-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 3986 // CHECK9-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 3987 // CHECK9-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 3988 // CHECK9-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 3989 // CHECK9-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 3990 // CHECK9-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 3991 // CHECK9-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 3992 // CHECK9-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 3993 // CHECK9-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 3994 // CHECK9-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 3995 // CHECK9-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 3996 // CHECK9-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 3997 // CHECK9-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 3998 // CHECK9-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 3999 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 4000 // CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 4001 // CHECK9-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 4002 // CHECK9-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 4003 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 4004 // CHECK9-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 4005 // CHECK9-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 4006 // CHECK9-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 4007 // CHECK9-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 4008 // CHECK9-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 4009 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4010 // CHECK9: omp.body.continue: 4011 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4012 // CHECK9: omp.inner.for.inc: 4013 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4014 // CHECK9-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 4015 // CHECK9-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 4016 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 4017 // CHECK9: omp.inner.for.end: 4018 // CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4019 // CHECK9: omp.dispatch.inc: 4020 // CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4021 // CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4022 // CHECK9-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 4023 // CHECK9-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 4024 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4025 // CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4026 // CHECK9-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 4027 // CHECK9-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 4028 // CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] 4029 // CHECK9: omp.dispatch.end: 4030 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 4031 // CHECK9-NEXT: ret void 4032 // 4033 // 4034 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 4035 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4036 // CHECK9-NEXT: entry: 4037 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4038 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4039 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 4040 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4041 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4042 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4043 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 4044 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4045 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4046 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 4047 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4048 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4049 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4050 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 4051 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4052 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 4053 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4054 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 4055 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 4056 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 4057 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4058 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 4059 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4060 // CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 4061 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 4062 // CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 4063 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 4064 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 4065 // CHECK9-NEXT: ret void 4066 // 4067 // 4068 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 4069 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 4070 // CHECK9-NEXT: entry: 4071 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4072 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4073 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4074 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4075 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 4076 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4077 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4078 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 4079 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4080 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4081 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4082 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4083 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 4084 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4085 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4086 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4087 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 4088 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4089 // CHECK9-NEXT: ret void 4090 // 4091 // 4092 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 4093 // CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 4094 // CHECK9-NEXT: entry: 4095 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4096 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4097 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4098 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4099 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 4100 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4101 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4102 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4103 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4104 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4105 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 4106 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4107 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4108 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4109 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4110 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 4111 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 4112 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 4113 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 4114 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 4115 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 4116 // CHECK9-NEXT: ret void 4117 // 4118 // 4119 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 4120 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 4121 // CHECK9-NEXT: entry: 4122 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4123 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4124 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4125 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4126 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4127 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4128 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 4129 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4130 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 4131 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4132 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4133 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4134 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4135 // CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8 4136 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4137 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4138 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4139 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4140 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4141 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4142 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 4143 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4144 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4145 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4146 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4147 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 4148 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4149 // CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 4150 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4151 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4152 // CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4153 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 4154 // CHECK9-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 4155 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4156 // CHECK9-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 4157 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4158 // CHECK9: cond.true: 4159 // CHECK9-NEXT: br label [[COND_END:%.*]] 4160 // CHECK9: cond.false: 4161 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4162 // CHECK9-NEXT: br label [[COND_END]] 4163 // CHECK9: cond.end: 4164 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 4165 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 4166 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4167 // CHECK9-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 4168 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4169 // CHECK9: omp.inner.for.cond: 4170 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4171 // CHECK9-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4172 // CHECK9-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 4173 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4174 // CHECK9: omp.inner.for.body: 4175 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4176 // CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 4177 // CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 4178 // CHECK9-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 4179 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 4180 // CHECK9-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 4181 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 4182 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4183 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 4184 // CHECK9-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 4185 // CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 4186 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 4187 // CHECK9-NEXT: store double [[INC]], double* [[A5]], align 8 4188 // CHECK9-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 4189 // CHECK9-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 4190 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 4191 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 4192 // CHECK9-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 4193 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4194 // CHECK9: omp.body.continue: 4195 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4196 // CHECK9: omp.inner.for.inc: 4197 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4198 // CHECK9-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 4199 // CHECK9-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 4200 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 4201 // CHECK9: omp.inner.for.end: 4202 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4203 // CHECK9: omp.loop.exit: 4204 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 4205 // CHECK9-NEXT: ret void 4206 // 4207 // 4208 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 4209 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4210 // CHECK9-NEXT: entry: 4211 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4212 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4213 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4214 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4215 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4216 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4217 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4218 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4219 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4220 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4221 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4222 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 4223 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4224 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 4225 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 4226 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 4227 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4228 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 4229 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4230 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 4231 // CHECK9-NEXT: ret void 4232 // 4233 // 4234 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 4235 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 4236 // CHECK9-NEXT: entry: 4237 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4238 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4239 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4240 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4241 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4242 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4243 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 4244 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4245 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4246 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4247 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4248 // CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8 4249 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4250 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4251 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4252 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4253 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4254 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4255 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4256 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4257 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4258 // CHECK9-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 4259 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4260 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4261 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4262 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 4263 // CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 4264 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4265 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 4266 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4267 // CHECK9: cond.true: 4268 // CHECK9-NEXT: br label [[COND_END:%.*]] 4269 // CHECK9: cond.false: 4270 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4271 // CHECK9-NEXT: br label [[COND_END]] 4272 // CHECK9: cond.end: 4273 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 4274 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 4275 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4276 // CHECK9-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 4277 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4278 // CHECK9: omp.inner.for.cond: 4279 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4280 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4281 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 4282 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4283 // CHECK9: omp.inner.for.body: 4284 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4285 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 4286 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 4287 // CHECK9-NEXT: store i64 [[ADD]], i64* [[I]], align 8 4288 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 4289 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 4290 // CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 4291 // CHECK9-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 4292 // CHECK9-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 4293 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 4294 // CHECK9-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 4295 // CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 4296 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 4297 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4298 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 4299 // CHECK9-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 4300 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4301 // CHECK9: omp.body.continue: 4302 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4303 // CHECK9: omp.inner.for.inc: 4304 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4305 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 4306 // CHECK9-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 4307 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 4308 // CHECK9: omp.inner.for.end: 4309 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4310 // CHECK9: omp.loop.exit: 4311 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 4312 // CHECK9-NEXT: ret void 4313 // 4314 // 4315 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 4316 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 4317 // CHECK11-NEXT: entry: 4318 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 4319 // CHECK11-NEXT: ret void 4320 // 4321 // 4322 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 4323 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 4324 // CHECK11-NEXT: entry: 4325 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4326 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4327 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4328 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4329 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4330 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4331 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4332 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4333 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4334 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4335 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4336 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4337 // CHECK11-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 4338 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4339 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4340 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4341 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4342 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4343 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4344 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 4345 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4346 // CHECK11: cond.true: 4347 // CHECK11-NEXT: br label [[COND_END:%.*]] 4348 // CHECK11: cond.false: 4349 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4350 // CHECK11-NEXT: br label [[COND_END]] 4351 // CHECK11: cond.end: 4352 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4353 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4354 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4355 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4356 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4357 // CHECK11: omp.inner.for.cond: 4358 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4359 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4360 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4361 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4362 // CHECK11: omp.inner.for.body: 4363 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4364 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 4365 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 4366 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4367 // CHECK11-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 4368 // CHECK11-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 4369 // CHECK11-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 4370 // CHECK11: .cancel.exit: 4371 // CHECK11-NEXT: br label [[CANCEL_EXIT:%.*]] 4372 // CHECK11: .cancel.continue: 4373 // CHECK11-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 4374 // CHECK11-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 4375 // CHECK11-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 4376 // CHECK11: .cancel.exit2: 4377 // CHECK11-NEXT: br label [[CANCEL_EXIT]] 4378 // CHECK11: .cancel.continue3: 4379 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4380 // CHECK11: omp.body.continue: 4381 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4382 // CHECK11: omp.inner.for.inc: 4383 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4384 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 4385 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 4386 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 4387 // CHECK11: omp.inner.for.end: 4388 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4389 // CHECK11: omp.loop.exit: 4390 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4391 // CHECK11-NEXT: br label [[CANCEL_CONT:%.*]] 4392 // CHECK11: cancel.cont: 4393 // CHECK11-NEXT: ret void 4394 // CHECK11: cancel.exit: 4395 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4396 // CHECK11-NEXT: br label [[CANCEL_CONT]] 4397 // 4398 // 4399 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 4400 // CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 4401 // CHECK11-NEXT: entry: 4402 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4403 // CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 4404 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4405 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4406 // CHECK11-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 4407 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4408 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4409 // CHECK11-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 4410 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4411 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4412 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 4413 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4414 // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 4415 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4416 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 4417 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 4418 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 4419 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 4420 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 4421 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 4422 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 4423 // CHECK11-NEXT: ret void 4424 // 4425 // 4426 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 4427 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 4428 // CHECK11-NEXT: entry: 4429 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4430 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4431 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4432 // CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 4433 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4434 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4435 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 4436 // CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 4437 // CHECK11-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 4438 // CHECK11-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 4439 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4440 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4441 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4442 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4443 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8 4444 // CHECK11-NEXT: [[LIN2:%.*]] = alloca i32, align 4 4445 // CHECK11-NEXT: [[A3:%.*]] = alloca i32, align 4 4446 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4447 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4448 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4449 // CHECK11-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 4450 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4451 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4452 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 4453 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 4454 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4455 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 4456 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 4457 // CHECK11-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 4458 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4459 // CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 4460 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4461 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4462 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4463 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 4464 // CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 4465 // CHECK11-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 4466 // CHECK11-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4467 // CHECK11-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 4468 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4469 // CHECK11: cond.true: 4470 // CHECK11-NEXT: br label [[COND_END:%.*]] 4471 // CHECK11: cond.false: 4472 // CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4473 // CHECK11-NEXT: br label [[COND_END]] 4474 // CHECK11: cond.end: 4475 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 4476 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 4477 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4478 // CHECK11-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 4479 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4480 // CHECK11: omp.inner.for.cond: 4481 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4482 // CHECK11-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4483 // CHECK11-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 4484 // CHECK11-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4485 // CHECK11: omp.inner.for.body: 4486 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4487 // CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 4488 // CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 4489 // CHECK11-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 4490 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 4491 // CHECK11-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 4492 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4493 // CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 4494 // CHECK11-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 4495 // CHECK11-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 4496 // CHECK11-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 4497 // CHECK11-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 4498 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 4499 // CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 4500 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4501 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 4502 // CHECK11-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 4503 // CHECK11-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 4504 // CHECK11-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 4505 // CHECK11-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 4506 // CHECK11-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 4507 // CHECK11-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 4508 // CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 4509 // CHECK11-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 4510 // CHECK11-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 4511 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4512 // CHECK11: omp.body.continue: 4513 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4514 // CHECK11: omp.inner.for.inc: 4515 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4516 // CHECK11-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 4517 // CHECK11-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 4518 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 4519 // CHECK11: omp.inner.for.end: 4520 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4521 // CHECK11: omp.loop.exit: 4522 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 4523 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4524 // CHECK11-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 4525 // CHECK11-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 4526 // CHECK11: .omp.linear.pu: 4527 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 4528 // CHECK11-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 4529 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 4530 // CHECK11-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 4531 // CHECK11-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 4532 // CHECK11: .omp.linear.pu.done: 4533 // CHECK11-NEXT: ret void 4534 // 4535 // 4536 // CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv 4537 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 4538 // CHECK11-NEXT: entry: 4539 // CHECK11-NEXT: ret i64 0 4540 // 4541 // 4542 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 4543 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4544 // CHECK11-NEXT: entry: 4545 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4546 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4547 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4548 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4549 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4550 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4551 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4552 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4553 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4554 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4555 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 4556 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4557 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 4558 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4559 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 4560 // CHECK11-NEXT: ret void 4561 // 4562 // 4563 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 4564 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 4565 // CHECK11-NEXT: entry: 4566 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4567 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4568 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4569 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4570 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4571 // CHECK11-NEXT: [[TMP:%.*]] = alloca i16, align 2 4572 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4573 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4574 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4575 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4576 // CHECK11-NEXT: [[IT:%.*]] = alloca i16, align 2 4577 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4578 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4579 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4580 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4581 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4582 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4583 // CHECK11-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 4584 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4585 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4586 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4587 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4588 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4589 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4590 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 4591 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4592 // CHECK11: cond.true: 4593 // CHECK11-NEXT: br label [[COND_END:%.*]] 4594 // CHECK11: cond.false: 4595 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4596 // CHECK11-NEXT: br label [[COND_END]] 4597 // CHECK11: cond.end: 4598 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4599 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4600 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4601 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4602 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4603 // CHECK11: omp.inner.for.cond: 4604 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4605 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4606 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4607 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4608 // CHECK11: omp.inner.for.body: 4609 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4610 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 4611 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 4612 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 4613 // CHECK11-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 4614 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 4615 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 4616 // CHECK11-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 4617 // CHECK11-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 4618 // CHECK11-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 4619 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 4620 // CHECK11-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 4621 // CHECK11-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 4622 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4623 // CHECK11: omp.body.continue: 4624 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4625 // CHECK11: omp.inner.for.inc: 4626 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4627 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 4628 // CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 4629 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 4630 // CHECK11: omp.inner.for.end: 4631 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4632 // CHECK11: omp.loop.exit: 4633 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4634 // CHECK11-NEXT: ret void 4635 // 4636 // 4637 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 4638 // CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 4639 // CHECK11-NEXT: entry: 4640 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4641 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 4642 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4643 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 4644 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 4645 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4646 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 4647 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 4648 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 4649 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4650 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4651 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 4652 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4653 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 4654 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4655 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 4656 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 4657 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4658 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 4659 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 4660 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 4661 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4662 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 4663 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4664 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 4665 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 4666 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4667 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 4668 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 4669 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 4670 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 4671 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 4672 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 4673 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4674 // CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4675 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4676 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 4677 // CHECK11-NEXT: ret void 4678 // 4679 // 4680 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 4681 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 4682 // CHECK11-NEXT: entry: 4683 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4684 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4685 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4686 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 4687 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4688 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 4689 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 4690 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4691 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 4692 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 4693 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 4694 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4695 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4696 // CHECK11-NEXT: [[TMP:%.*]] = alloca i8, align 1 4697 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4698 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4699 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4700 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4701 // CHECK11-NEXT: [[IT:%.*]] = alloca i8, align 1 4702 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4703 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4704 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4705 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 4706 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4707 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 4708 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 4709 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4710 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 4711 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 4712 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 4713 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4714 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 4715 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4716 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 4717 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 4718 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4719 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 4720 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 4721 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 4722 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4723 // CHECK11-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 4724 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4725 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4726 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4727 // CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4728 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 4729 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 4730 // CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4731 // CHECK11: omp.dispatch.cond: 4732 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4733 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 4734 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4735 // CHECK11: cond.true: 4736 // CHECK11-NEXT: br label [[COND_END:%.*]] 4737 // CHECK11: cond.false: 4738 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4739 // CHECK11-NEXT: br label [[COND_END]] 4740 // CHECK11: cond.end: 4741 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 4742 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4743 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4744 // CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 4745 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4746 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4747 // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 4748 // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4749 // CHECK11: omp.dispatch.body: 4750 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4751 // CHECK11: omp.inner.for.cond: 4752 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4753 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4754 // CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 4755 // CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4756 // CHECK11: omp.inner.for.body: 4757 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4758 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 4759 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 4760 // CHECK11-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 4761 // CHECK11-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 4762 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 4763 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 4764 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4765 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 4766 // CHECK11-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 4767 // CHECK11-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 4768 // CHECK11-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 4769 // CHECK11-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 4770 // CHECK11-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 4771 // CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 4772 // CHECK11-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 4773 // CHECK11-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 4774 // CHECK11-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 4775 // CHECK11-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 4776 // CHECK11-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 4777 // CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 4778 // CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 4779 // CHECK11-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 4780 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 4781 // CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 4782 // CHECK11-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 4783 // CHECK11-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 4784 // CHECK11-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 4785 // CHECK11-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 4786 // CHECK11-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 4787 // CHECK11-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 4788 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 4789 // CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 4790 // CHECK11-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 4791 // CHECK11-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 4792 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 4793 // CHECK11-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 4794 // CHECK11-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 4795 // CHECK11-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 4796 // CHECK11-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 4797 // CHECK11-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 4798 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4799 // CHECK11: omp.body.continue: 4800 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4801 // CHECK11: omp.inner.for.inc: 4802 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4803 // CHECK11-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 4804 // CHECK11-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 4805 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 4806 // CHECK11: omp.inner.for.end: 4807 // CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4808 // CHECK11: omp.dispatch.inc: 4809 // CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4810 // CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4811 // CHECK11-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 4812 // CHECK11-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 4813 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4814 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4815 // CHECK11-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 4816 // CHECK11-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 4817 // CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] 4818 // CHECK11: omp.dispatch.end: 4819 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 4820 // CHECK11-NEXT: ret void 4821 // 4822 // 4823 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 4824 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4825 // CHECK11-NEXT: entry: 4826 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4827 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4828 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 4829 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4830 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4831 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4832 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 4833 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4834 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4835 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 4836 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4837 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4838 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 4839 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4840 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4841 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 4842 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 4843 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 4844 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4845 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 4846 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4847 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 4848 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 4849 // CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 4850 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 4851 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 4852 // CHECK11-NEXT: ret void 4853 // 4854 // 4855 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 4856 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 4857 // CHECK11-NEXT: entry: 4858 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4859 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4860 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4861 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4862 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 4863 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4864 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4865 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4866 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4867 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4868 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4869 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4870 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 4871 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4872 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4873 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 4874 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4875 // CHECK11-NEXT: ret void 4876 // 4877 // 4878 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 4879 // CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 4880 // CHECK11-NEXT: entry: 4881 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4882 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4883 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4884 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4885 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 4886 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4887 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4888 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4889 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4890 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4891 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 4892 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4893 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4894 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4895 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 4896 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 4897 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 4898 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 4899 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 4900 // CHECK11-NEXT: ret void 4901 // 4902 // 4903 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 4904 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 4905 // CHECK11-NEXT: entry: 4906 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4907 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4908 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4909 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4910 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4911 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4912 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 4913 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4914 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 4915 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4916 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4917 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4918 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4919 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8 4920 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4921 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4922 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4923 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4924 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4925 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4926 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 4927 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4928 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4929 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4930 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 4931 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4932 // CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 4933 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4934 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4935 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4936 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 4937 // CHECK11-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 4938 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4939 // CHECK11-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 4940 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4941 // CHECK11: cond.true: 4942 // CHECK11-NEXT: br label [[COND_END:%.*]] 4943 // CHECK11: cond.false: 4944 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4945 // CHECK11-NEXT: br label [[COND_END]] 4946 // CHECK11: cond.end: 4947 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 4948 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 4949 // CHECK11-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4950 // CHECK11-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 4951 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4952 // CHECK11: omp.inner.for.cond: 4953 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4954 // CHECK11-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4955 // CHECK11-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 4956 // CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4957 // CHECK11: omp.inner.for.body: 4958 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4959 // CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 4960 // CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 4961 // CHECK11-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 4962 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 4963 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 4964 // CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 4965 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4966 // CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4 4967 // CHECK11-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 4968 // CHECK11-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 4969 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 4970 // CHECK11-NEXT: store double [[INC]], double* [[A4]], align 4 4971 // CHECK11-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 4972 // CHECK11-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 4973 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 4974 // CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 4975 // CHECK11-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 4976 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4977 // CHECK11: omp.body.continue: 4978 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4979 // CHECK11: omp.inner.for.inc: 4980 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4981 // CHECK11-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 4982 // CHECK11-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 4983 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 4984 // CHECK11: omp.inner.for.end: 4985 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4986 // CHECK11: omp.loop.exit: 4987 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 4988 // CHECK11-NEXT: ret void 4989 // 4990 // 4991 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 4992 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4993 // CHECK11-NEXT: entry: 4994 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4995 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4996 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4997 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4998 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4999 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5000 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5001 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5002 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5003 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5004 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5005 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5006 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5007 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 5008 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5009 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 5010 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5011 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 5012 // CHECK11-NEXT: ret void 5013 // 5014 // 5015 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 5016 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 5017 // CHECK11-NEXT: entry: 5018 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5019 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5020 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5021 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5022 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5023 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5024 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 5025 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5026 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5027 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5028 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5029 // CHECK11-NEXT: [[I:%.*]] = alloca i64, align 8 5030 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5031 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5032 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5033 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5034 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5035 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5036 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5037 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 5038 // CHECK11-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 5039 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 5040 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5041 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5042 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 5043 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 5044 // CHECK11-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5045 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 5046 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5047 // CHECK11: cond.true: 5048 // CHECK11-NEXT: br label [[COND_END:%.*]] 5049 // CHECK11: cond.false: 5050 // CHECK11-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5051 // CHECK11-NEXT: br label [[COND_END]] 5052 // CHECK11: cond.end: 5053 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 5054 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 5055 // CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 5056 // CHECK11-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 5057 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5058 // CHECK11: omp.inner.for.cond: 5059 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5060 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5061 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 5062 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5063 // CHECK11: omp.inner.for.body: 5064 // CHECK11-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5065 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 5066 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 5067 // CHECK11-NEXT: store i64 [[ADD]], i64* [[I]], align 8 5068 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 5069 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 5070 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 5071 // CHECK11-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 5072 // CHECK11-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 5073 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 5074 // CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 5075 // CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 5076 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 5077 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5078 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 5079 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 5080 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5081 // CHECK11: omp.body.continue: 5082 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5083 // CHECK11: omp.inner.for.inc: 5084 // CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5085 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 5086 // CHECK11-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 5087 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 5088 // CHECK11: omp.inner.for.end: 5089 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5090 // CHECK11: omp.loop.exit: 5091 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 5092 // CHECK11-NEXT: ret void 5093 // 5094 // 5095 // CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv 5096 // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { 5097 // CHECK17-NEXT: entry: 5098 // CHECK17-NEXT: ret i64 0 5099 // 5100 // 5101 // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi 5102 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 5103 // CHECK17-NEXT: entry: 5104 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5105 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 5106 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 5107 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 4 5108 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 5109 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 5110 // CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 5111 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 5112 // CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 5113 // CHECK17-NEXT: [[K:%.*]] = alloca i64, align 8 5114 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5115 // CHECK17-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 5116 // CHECK17-NEXT: [[LIN:%.*]] = alloca i32, align 4 5117 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5118 // CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 5119 // CHECK17-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8 5120 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 5121 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 5122 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 5123 // CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 5124 // CHECK17-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8 5125 // CHECK17-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8 5126 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 5127 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 5128 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 5129 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5130 // CHECK17-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8 5131 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 5132 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8 5133 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8 5134 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8 5135 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 5136 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 5137 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5138 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 5139 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 5140 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5141 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 5142 // CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 5143 // CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 5144 // CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 5145 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 5146 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 5147 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 5148 // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 5149 // CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 5150 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 5151 // CHECK17-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 5152 // CHECK17-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 5153 // CHECK17-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5154 // CHECK17: omp_offload.failed: 5155 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 5156 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 5157 // CHECK17: omp_offload.cont: 5158 // CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 5159 // CHECK17-NEXT: store i64 [[CALL]], i64* [[K]], align 8 5160 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 5161 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5162 // CHECK17-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4 5163 // CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8 5164 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[K]], align 8 5165 // CHECK17-NEXT: store i64 [[TMP11]], i64* [[K_CASTED]], align 8 5166 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8 5167 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR4]] 5168 // CHECK17-NEXT: store i32 12, i32* [[LIN]], align 4 5169 // CHECK17-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 5170 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 5171 // CHECK17-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 5172 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 5173 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4 5174 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 5175 // CHECK17-NEXT: store i32 [[TMP15]], i32* [[CONV3]], align 4 5176 // CHECK17-NEXT: [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 5177 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 5178 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32* 5179 // CHECK17-NEXT: store i32 [[TMP17]], i32* [[CONV5]], align 4 5180 // CHECK17-NEXT: [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8 5181 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5182 // CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 5183 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP20]], align 8 5184 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5185 // CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 5186 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP22]], align 8 5187 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 5188 // CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8 5189 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5190 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 5191 // CHECK17-NEXT: store i64 [[TMP16]], i64* [[TMP25]], align 8 5192 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5193 // CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 5194 // CHECK17-NEXT: store i64 [[TMP16]], i64* [[TMP27]], align 8 5195 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 5196 // CHECK17-NEXT: store i8* null, i8** [[TMP28]], align 8 5197 // CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5198 // CHECK17-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 5199 // CHECK17-NEXT: store i64 [[TMP18]], i64* [[TMP30]], align 8 5200 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5201 // CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 5202 // CHECK17-NEXT: store i64 [[TMP18]], i64* [[TMP32]], align 8 5203 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 5204 // CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 5205 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5206 // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5207 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 5208 // CHECK17-NEXT: [[TMP37:%.*]] = load i16, i16* [[AA]], align 2 5209 // CHECK17-NEXT: store i16 [[TMP37]], i16* [[TMP36]], align 4 5210 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 5211 // CHECK17-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4 5212 // CHECK17-NEXT: store i32 [[TMP39]], i32* [[TMP38]], align 4 5213 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 5214 // CHECK17-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 5215 // CHECK17-NEXT: store i32 [[TMP41]], i32* [[TMP40]], align 4 5216 // CHECK17-NEXT: [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 5217 // CHECK17-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates* 5218 // CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0 5219 // CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0 5220 // CHECK17-NEXT: [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8 5221 // CHECK17-NEXT: [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 5222 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false) 5223 // CHECK17-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1 5224 // CHECK17-NEXT: [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon* 5225 // CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0 5226 // CHECK17-NEXT: [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8* 5227 // CHECK17-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8* 5228 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false) 5229 // CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1 5230 // CHECK17-NEXT: [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8* 5231 // CHECK17-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8* 5232 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false) 5233 // CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2 5234 // CHECK17-NEXT: [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8* 5235 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 5236 // CHECK17-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3 5237 // CHECK17-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 5238 // CHECK17-NEXT: store i16 [[TMP59]], i16* [[TMP58]], align 8 5239 // CHECK17-NEXT: [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]]) 5240 // CHECK17-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4 5241 // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32* 5242 // CHECK17-NEXT: store i32 [[TMP61]], i32* [[CONV7]], align 4 5243 // CHECK17-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8 5244 // CHECK17-NEXT: [[TMP63:%.*]] = load i16, i16* [[AA]], align 2 5245 // CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16* 5246 // CHECK17-NEXT: store i16 [[TMP63]], i16* [[CONV9]], align 2 5247 // CHECK17-NEXT: [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8 5248 // CHECK17-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4 5249 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10 5250 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5251 // CHECK17: omp_if.then: 5252 // CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 5253 // CHECK17-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64* 5254 // CHECK17-NEXT: store i64 [[TMP62]], i64* [[TMP67]], align 8 5255 // CHECK17-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 5256 // CHECK17-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* 5257 // CHECK17-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8 5258 // CHECK17-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 5259 // CHECK17-NEXT: store i8* null, i8** [[TMP70]], align 8 5260 // CHECK17-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 5261 // CHECK17-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* 5262 // CHECK17-NEXT: store i64 [[TMP64]], i64* [[TMP72]], align 8 5263 // CHECK17-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 5264 // CHECK17-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64* 5265 // CHECK17-NEXT: store i64 [[TMP64]], i64* [[TMP74]], align 8 5266 // CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 5267 // CHECK17-NEXT: store i8* null, i8** [[TMP75]], align 8 5268 // CHECK17-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 5269 // CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 5270 // CHECK17-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 5271 // CHECK17-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0 5272 // CHECK17-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]] 5273 // CHECK17: omp_offload.failed13: 5274 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 5275 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT14]] 5276 // CHECK17: omp_offload.cont14: 5277 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 5278 // CHECK17: omp_if.else: 5279 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]] 5280 // CHECK17-NEXT: br label [[OMP_IF_END]] 5281 // CHECK17: omp_if.end: 5282 // CHECK17-NEXT: [[TMP80:%.*]] = load i32, i32* [[A]], align 4 5283 // CHECK17-NEXT: store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4 5284 // CHECK17-NEXT: [[TMP81:%.*]] = load i32, i32* [[A]], align 4 5285 // CHECK17-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32* 5286 // CHECK17-NEXT: store i32 [[TMP81]], i32* [[CONV16]], align 4 5287 // CHECK17-NEXT: [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8 5288 // CHECK17-NEXT: [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5289 // CHECK17-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 5290 // CHECK17-NEXT: store i32 [[TMP83]], i32* [[CONV17]], align 4 5291 // CHECK17-NEXT: [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 5292 // CHECK17-NEXT: [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4 5293 // CHECK17-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20 5294 // CHECK17-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 5295 // CHECK17: omp_if.then19: 5296 // CHECK17-NEXT: [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4 5297 // CHECK17-NEXT: [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]] 5298 // CHECK17-NEXT: [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8 5299 // CHECK17-NEXT: [[TMP89:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 5300 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP89]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i64 80, i1 false) 5301 // CHECK17-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 5302 // CHECK17-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i64* 5303 // CHECK17-NEXT: store i64 [[TMP82]], i64* [[TMP91]], align 8 5304 // CHECK17-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 5305 // CHECK17-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to i64* 5306 // CHECK17-NEXT: store i64 [[TMP82]], i64* [[TMP93]], align 8 5307 // CHECK17-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 5308 // CHECK17-NEXT: store i8* null, i8** [[TMP94]], align 8 5309 // CHECK17-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 5310 // CHECK17-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 5311 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8 5312 // CHECK17-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 5313 // CHECK17-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]** 5314 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8 5315 // CHECK17-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 5316 // CHECK17-NEXT: store i8* null, i8** [[TMP99]], align 8 5317 // CHECK17-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 5318 // CHECK17-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64* 5319 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP101]], align 8 5320 // CHECK17-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 5321 // CHECK17-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i64* 5322 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP103]], align 8 5323 // CHECK17-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 5324 // CHECK17-NEXT: store i8* null, i8** [[TMP104]], align 8 5325 // CHECK17-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 5326 // CHECK17-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** 5327 // CHECK17-NEXT: store float* [[VLA]], float** [[TMP106]], align 8 5328 // CHECK17-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 5329 // CHECK17-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float** 5330 // CHECK17-NEXT: store float* [[VLA]], float** [[TMP108]], align 8 5331 // CHECK17-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 5332 // CHECK17-NEXT: store i64 [[TMP86]], i64* [[TMP109]], align 8 5333 // CHECK17-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 5334 // CHECK17-NEXT: store i8* null, i8** [[TMP110]], align 8 5335 // CHECK17-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 5336 // CHECK17-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** 5337 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 8 5338 // CHECK17-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 5339 // CHECK17-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]** 5340 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8 5341 // CHECK17-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 5342 // CHECK17-NEXT: store i8* null, i8** [[TMP115]], align 8 5343 // CHECK17-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 5344 // CHECK17-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64* 5345 // CHECK17-NEXT: store i64 5, i64* [[TMP117]], align 8 5346 // CHECK17-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 5347 // CHECK17-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i64* 5348 // CHECK17-NEXT: store i64 5, i64* [[TMP119]], align 8 5349 // CHECK17-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5 5350 // CHECK17-NEXT: store i8* null, i8** [[TMP120]], align 8 5351 // CHECK17-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 5352 // CHECK17-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64* 5353 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP122]], align 8 5354 // CHECK17-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 5355 // CHECK17-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i64* 5356 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP124]], align 8 5357 // CHECK17-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6 5358 // CHECK17-NEXT: store i8* null, i8** [[TMP125]], align 8 5359 // CHECK17-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 5360 // CHECK17-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** 5361 // CHECK17-NEXT: store double* [[VLA1]], double** [[TMP127]], align 8 5362 // CHECK17-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 5363 // CHECK17-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to double** 5364 // CHECK17-NEXT: store double* [[VLA1]], double** [[TMP129]], align 8 5365 // CHECK17-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 5366 // CHECK17-NEXT: store i64 [[TMP88]], i64* [[TMP130]], align 8 5367 // CHECK17-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7 5368 // CHECK17-NEXT: store i8* null, i8** [[TMP131]], align 8 5369 // CHECK17-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 5370 // CHECK17-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT** 5371 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 8 5372 // CHECK17-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 5373 // CHECK17-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to %struct.TT** 5374 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP135]], align 8 5375 // CHECK17-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8 5376 // CHECK17-NEXT: store i8* null, i8** [[TMP136]], align 8 5377 // CHECK17-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9 5378 // CHECK17-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i64* 5379 // CHECK17-NEXT: store i64 [[TMP84]], i64* [[TMP138]], align 8 5380 // CHECK17-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9 5381 // CHECK17-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to i64* 5382 // CHECK17-NEXT: store i64 [[TMP84]], i64* [[TMP140]], align 8 5383 // CHECK17-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9 5384 // CHECK17-NEXT: store i8* null, i8** [[TMP141]], align 8 5385 // CHECK17-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 5386 // CHECK17-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 5387 // CHECK17-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5388 // CHECK17-NEXT: [[TMP145:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP142]], i8** [[TMP143]], i64* [[TMP144]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 5389 // CHECK17-NEXT: [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 0 5390 // CHECK17-NEXT: br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 5391 // CHECK17: omp_offload.failed23: 5392 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 5393 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT24]] 5394 // CHECK17: omp_offload.cont24: 5395 // CHECK17-NEXT: br label [[OMP_IF_END26:%.*]] 5396 // CHECK17: omp_if.else25: 5397 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]] 5398 // CHECK17-NEXT: br label [[OMP_IF_END26]] 5399 // CHECK17: omp_if.end26: 5400 // CHECK17-NEXT: [[TMP147:%.*]] = load i32, i32* [[A]], align 4 5401 // CHECK17-NEXT: [[TMP148:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 5402 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP148]]) 5403 // CHECK17-NEXT: ret i32 [[TMP147]] 5404 // 5405 // 5406 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 5407 // CHECK17-SAME: () #[[ATTR2:[0-9]+]] { 5408 // CHECK17-NEXT: entry: 5409 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 5410 // CHECK17-NEXT: ret void 5411 // 5412 // 5413 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 5414 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 5415 // CHECK17-NEXT: entry: 5416 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5417 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5418 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5419 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 5420 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5421 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5422 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5423 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5424 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 5425 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5426 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5427 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5428 // CHECK17-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 5429 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5430 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5431 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5432 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 5433 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5434 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5435 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 5436 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5437 // CHECK17: cond.true: 5438 // CHECK17-NEXT: br label [[COND_END:%.*]] 5439 // CHECK17: cond.false: 5440 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5441 // CHECK17-NEXT: br label [[COND_END]] 5442 // CHECK17: cond.end: 5443 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 5444 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5445 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5446 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 5447 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5448 // CHECK17: omp.inner.for.cond: 5449 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5450 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5451 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 5452 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5453 // CHECK17: omp.inner.for.body: 5454 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5455 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 5456 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 5457 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 5458 // CHECK17-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 5459 // CHECK17-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 5460 // CHECK17-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 5461 // CHECK17: .cancel.exit: 5462 // CHECK17-NEXT: br label [[CANCEL_EXIT:%.*]] 5463 // CHECK17: .cancel.continue: 5464 // CHECK17-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 5465 // CHECK17-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 5466 // CHECK17-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 5467 // CHECK17: .cancel.exit2: 5468 // CHECK17-NEXT: br label [[CANCEL_EXIT]] 5469 // CHECK17: .cancel.continue3: 5470 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5471 // CHECK17: omp.body.continue: 5472 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5473 // CHECK17: omp.inner.for.inc: 5474 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5475 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 5476 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 5477 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 5478 // CHECK17: omp.inner.for.end: 5479 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5480 // CHECK17: omp.loop.exit: 5481 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 5482 // CHECK17-NEXT: br label [[CANCEL_CONT:%.*]] 5483 // CHECK17: cancel.cont: 5484 // CHECK17-NEXT: ret void 5485 // CHECK17: cancel.exit: 5486 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 5487 // CHECK17-NEXT: br label [[CANCEL_CONT]] 5488 // 5489 // 5490 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 5491 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 5492 // CHECK17-NEXT: entry: 5493 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5494 // CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 5495 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5496 // CHECK17-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 5497 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5498 // CHECK17-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 5499 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5500 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 5501 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5502 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 5503 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 5504 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 5505 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 5506 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 5507 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 5508 // CHECK17-NEXT: ret void 5509 // 5510 // 5511 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 5512 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 5513 // CHECK17-NEXT: entry: 5514 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5515 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5516 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5517 // CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 5518 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5519 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 5520 // CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 5521 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5522 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5523 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5524 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5525 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 5526 // CHECK17-NEXT: [[K1:%.*]] = alloca i64, align 8 5527 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5528 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5529 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5530 // CHECK17-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 5531 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5532 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8 5533 // CHECK17-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8 5534 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5535 // CHECK17-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 5536 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5537 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5538 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5539 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 5540 // CHECK17-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 5541 // CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 5542 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 5543 // CHECK17: omp.dispatch.cond: 5544 // CHECK17-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 5545 // CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 5546 // CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 5547 // CHECK17: omp.dispatch.body: 5548 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5549 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 5550 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5551 // CHECK17: omp.inner.for.cond: 5552 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 5553 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 5554 // CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 5555 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5556 // CHECK17: omp.inner.for.body: 5557 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 5558 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 5559 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 5560 // CHECK17-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12 5561 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12 5562 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 5563 // CHECK17-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 5564 // CHECK17-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 5565 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] 5566 // CHECK17-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12 5567 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12 5568 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 5569 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12 5570 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5571 // CHECK17: omp.body.continue: 5572 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5573 // CHECK17: omp.inner.for.inc: 5574 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 5575 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 5576 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 5577 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 5578 // CHECK17: omp.inner.for.end: 5579 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 5580 // CHECK17: omp.dispatch.inc: 5581 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 5582 // CHECK17: omp.dispatch.end: 5583 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5584 // CHECK17-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 5585 // CHECK17-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 5586 // CHECK17: .omp.linear.pu: 5587 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[K1]], align 8 5588 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[K_ADDR]], align 8 5589 // CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 5590 // CHECK17: .omp.linear.pu.done: 5591 // CHECK17-NEXT: ret void 5592 // 5593 // 5594 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 5595 // CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 5596 // CHECK17-NEXT: entry: 5597 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5598 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 5599 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5600 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5601 // CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 5602 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5603 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5604 // CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 5605 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5606 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5607 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 5608 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5609 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 5610 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 5611 // CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 5612 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 5613 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 5614 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 5615 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 5616 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 5617 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 5618 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5619 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 5620 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 5621 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 5622 // CHECK17-NEXT: ret void 5623 // 5624 // 5625 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 5626 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 5627 // CHECK17-NEXT: entry: 5628 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5629 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5630 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5631 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 5632 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5633 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5634 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 5635 // CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 5636 // CHECK17-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 5637 // CHECK17-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 5638 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5639 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5640 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5641 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5642 // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 5643 // CHECK17-NEXT: [[LIN4:%.*]] = alloca i32, align 4 5644 // CHECK17-NEXT: [[A5:%.*]] = alloca i32, align 4 5645 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5646 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5647 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5648 // CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 5649 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5650 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5651 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 5652 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5653 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 5654 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 5655 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 5656 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 5657 // CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 5658 // CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 5659 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 5660 // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 5661 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 5662 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5663 // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5664 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 5665 // CHECK17-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 5666 // CHECK17-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 5667 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5668 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 5669 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5670 // CHECK17: cond.true: 5671 // CHECK17-NEXT: br label [[COND_END:%.*]] 5672 // CHECK17: cond.false: 5673 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5674 // CHECK17-NEXT: br label [[COND_END]] 5675 // CHECK17: cond.end: 5676 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 5677 // CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 5678 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 5679 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 5680 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5681 // CHECK17: omp.inner.for.cond: 5682 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5683 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5684 // CHECK17-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 5685 // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5686 // CHECK17: omp.inner.for.body: 5687 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5688 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 5689 // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 5690 // CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 5691 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 5692 // CHECK17-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 5693 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5694 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 5695 // CHECK17-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 5696 // CHECK17-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 5697 // CHECK17-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 5698 // CHECK17-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4 5699 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 5700 // CHECK17-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 5701 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5702 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 5703 // CHECK17-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 5704 // CHECK17-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 5705 // CHECK17-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 5706 // CHECK17-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 5707 // CHECK17-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 5708 // CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 5709 // CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 5710 // CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 5711 // CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2 5712 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5713 // CHECK17: omp.body.continue: 5714 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5715 // CHECK17: omp.inner.for.inc: 5716 // CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5717 // CHECK17-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 5718 // CHECK17-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 5719 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 5720 // CHECK17: omp.inner.for.end: 5721 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5722 // CHECK17: omp.loop.exit: 5723 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 5724 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5725 // CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 5726 // CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 5727 // CHECK17: .omp.linear.pu: 5728 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 5729 // CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4 5730 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 5731 // CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4 5732 // CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 5733 // CHECK17: .omp.linear.pu.done: 5734 // CHECK17-NEXT: ret void 5735 // 5736 // 5737 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map. 5738 // CHECK17-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 5739 // CHECK17-NEXT: entry: 5740 // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 5741 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 5742 // CHECK17-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 5743 // CHECK17-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 5744 // CHECK17-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 5745 // CHECK17-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 5746 // CHECK17-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 5747 // CHECK17-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 5748 // CHECK17-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 5749 // CHECK17-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 5750 // CHECK17-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 5751 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 5752 // CHECK17-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 5753 // CHECK17-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 5754 // CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 5755 // CHECK17-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 5756 // CHECK17-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 5757 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 5758 // CHECK17-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 5759 // CHECK17-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 5760 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 5761 // CHECK17-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 5762 // CHECK17-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 5763 // CHECK17-NEXT: ret void 5764 // 5765 // 5766 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. 5767 // CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 5768 // CHECK17-NEXT: entry: 5769 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 5770 // CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 5771 // CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 5772 // CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 5773 // CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 5774 // CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 5775 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 5776 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 5777 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 5778 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 5779 // CHECK17-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 5780 // CHECK17-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8 5781 // CHECK17-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8 5782 // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 5783 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 5784 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 5785 // CHECK17-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 5786 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 5787 // CHECK17-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 5788 // CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 5789 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 5790 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 5791 // CHECK17-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 5792 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 5793 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 5794 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 5795 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 5796 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 5797 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 5798 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 5799 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 5800 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 5801 // CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24 5802 // CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 5803 // CHECK17-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 5804 // CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24 5805 // CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 5806 // CHECK17-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 5807 // CHECK17-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 5808 // CHECK17-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 5809 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 5810 // CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 5811 // CHECK17-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 5812 // CHECK17-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 5813 // CHECK17-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 5814 // CHECK17-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24 5815 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 5816 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 5817 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 5818 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 5819 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 5820 // CHECK17-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 5821 // CHECK17-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 5822 // CHECK17-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 5823 // CHECK17: omp_offload.failed.i: 5824 // CHECK17-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 5825 // CHECK17-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 5826 // CHECK17-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24 5827 // CHECK17-NEXT: [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24 5828 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 5829 // CHECK17-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32* 5830 // CHECK17-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !24 5831 // CHECK17-NEXT: [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !24 5832 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 5833 // CHECK17-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32* 5834 // CHECK17-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !24 5835 // CHECK17-NEXT: [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !24 5836 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR4]] 5837 // CHECK17-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 5838 // CHECK17: .omp_outlined..3.exit: 5839 // CHECK17-NEXT: ret i32 0 5840 // 5841 // 5842 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 5843 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 5844 // CHECK17-NEXT: entry: 5845 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5846 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5847 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5848 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5849 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5850 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5851 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5852 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5853 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 5854 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5855 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 5856 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 5857 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 5858 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 5859 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 5860 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 5861 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 5862 // CHECK17-NEXT: ret void 5863 // 5864 // 5865 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 5866 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 5867 // CHECK17-NEXT: entry: 5868 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5869 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5870 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5871 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5872 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5873 // CHECK17-NEXT: [[TMP:%.*]] = alloca i16, align 2 5874 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5875 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5876 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5877 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5878 // CHECK17-NEXT: [[IT:%.*]] = alloca i16, align 2 5879 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5880 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5881 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5882 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5883 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5884 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5885 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5886 // CHECK17-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 5887 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5888 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5889 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5890 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 5891 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5892 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5893 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 5894 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5895 // CHECK17: cond.true: 5896 // CHECK17-NEXT: br label [[COND_END:%.*]] 5897 // CHECK17: cond.false: 5898 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5899 // CHECK17-NEXT: br label [[COND_END]] 5900 // CHECK17: cond.end: 5901 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 5902 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5903 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5904 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 5905 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5906 // CHECK17: omp.inner.for.cond: 5907 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5908 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5909 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 5910 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5911 // CHECK17: omp.inner.for.body: 5912 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5913 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 5914 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 5915 // CHECK17-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 5916 // CHECK17-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 5917 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 5918 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 5919 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4 5920 // CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 5921 // CHECK17-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 5922 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 5923 // CHECK17-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 5924 // CHECK17-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2 5925 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5926 // CHECK17: omp.body.continue: 5927 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5928 // CHECK17: omp.inner.for.inc: 5929 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5930 // CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 5931 // CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 5932 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 5933 // CHECK17: omp.inner.for.end: 5934 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5935 // CHECK17: omp.loop.exit: 5936 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 5937 // CHECK17-NEXT: ret void 5938 // 5939 // 5940 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 5941 // CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 5942 // CHECK17-NEXT: entry: 5943 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5944 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 5945 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 5946 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 5947 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 5948 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 5949 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 5950 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 5951 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 5952 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5953 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5954 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 5955 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5956 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 5957 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 5958 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 5959 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 5960 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 5961 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 5962 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 5963 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 5964 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5965 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5966 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 5967 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 5968 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 5969 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 5970 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 5971 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 5972 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 5973 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 5974 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 5975 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 5976 // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5977 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 5978 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 5979 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 5980 // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 5981 // CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 5982 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 5983 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 5984 // CHECK17-NEXT: ret void 5985 // 5986 // 5987 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 5988 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 5989 // CHECK17-NEXT: entry: 5990 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5991 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5992 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5993 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 5994 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 5995 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 5996 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 5997 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 5998 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 5999 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 6000 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 6001 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 6002 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6003 // CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1 6004 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6005 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6006 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6007 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6008 // CHECK17-NEXT: [[IT:%.*]] = alloca i8, align 1 6009 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6010 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6011 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6012 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 6013 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6014 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 6015 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 6016 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6017 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 6018 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 6019 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 6020 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 6021 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6022 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 6023 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6024 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 6025 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 6026 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6027 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 6028 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 6029 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 6030 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 6031 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6032 // CHECK17-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 6033 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6034 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6035 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 6036 // CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6037 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 6038 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 6039 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6040 // CHECK17: omp.dispatch.cond: 6041 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6042 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 6043 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6044 // CHECK17: cond.true: 6045 // CHECK17-NEXT: br label [[COND_END:%.*]] 6046 // CHECK17: cond.false: 6047 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6048 // CHECK17-NEXT: br label [[COND_END]] 6049 // CHECK17: cond.end: 6050 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 6051 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6052 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6053 // CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 6054 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6055 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6056 // CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 6057 // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6058 // CHECK17: omp.dispatch.body: 6059 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6060 // CHECK17: omp.inner.for.cond: 6061 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6062 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6063 // CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 6064 // CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6065 // CHECK17: omp.inner.for.body: 6066 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6067 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 6068 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 6069 // CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 6070 // CHECK17-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 6071 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4 6072 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 6073 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 6074 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 6075 // CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 6076 // CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 6077 // CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 6078 // CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 6079 // CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 6080 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 6081 // CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 6082 // CHECK17-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 6083 // CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 6084 // CHECK17-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 6085 // CHECK17-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 6086 // CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 6087 // CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 6088 // CHECK17-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8 6089 // CHECK17-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 6090 // CHECK17-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 6091 // CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 6092 // CHECK17-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 6093 // CHECK17-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 6094 // CHECK17-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8 6095 // CHECK17-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 6096 // CHECK17-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 6097 // CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 6098 // CHECK17-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8 6099 // CHECK17-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 6100 // CHECK17-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 6101 // CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 6102 // CHECK17-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8 6103 // CHECK17-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 6104 // CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 6105 // CHECK17-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 6106 // CHECK17-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 6107 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6108 // CHECK17: omp.body.continue: 6109 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6110 // CHECK17: omp.inner.for.inc: 6111 // CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6112 // CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 6113 // CHECK17-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 6114 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 6115 // CHECK17: omp.inner.for.end: 6116 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6117 // CHECK17: omp.dispatch.inc: 6118 // CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6119 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6120 // CHECK17-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 6121 // CHECK17-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 6122 // CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6123 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6124 // CHECK17-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 6125 // CHECK17-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 6126 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 6127 // CHECK17: omp.dispatch.end: 6128 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 6129 // CHECK17-NEXT: ret void 6130 // 6131 // 6132 // CHECK17-LABEL: define {{[^@]+}}@_Z3bari 6133 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 6134 // CHECK17-NEXT: entry: 6135 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6136 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 6137 // CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 6138 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6139 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 6140 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6141 // CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 6142 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6143 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6144 // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6145 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6146 // CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 6147 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6148 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6149 // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6150 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6151 // CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 6152 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6153 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6154 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6155 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6156 // CHECK17-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 6157 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 6158 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 6159 // CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 6160 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 6161 // CHECK17-NEXT: ret i32 [[TMP8]] 6162 // 6163 // 6164 // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6165 // CHECK17-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6166 // CHECK17-NEXT: entry: 6167 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6168 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6169 // CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 6170 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 6171 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 6172 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 6173 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 6174 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 6175 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 6176 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 6177 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 6178 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6179 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 6180 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6181 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6182 // CHECK17-NEXT: store i32 [[ADD]], i32* [[B]], align 4 6183 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6184 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 6185 // CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 6186 // CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 6187 // CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 6188 // CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 6189 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 6190 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 6191 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 6192 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 6193 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 6194 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 6195 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 6196 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6197 // CHECK17: omp_if.then: 6198 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6199 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 6200 // CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 6201 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 6202 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false) 6203 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6204 // CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 6205 // CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 6206 // CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6207 // CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 6208 // CHECK17-NEXT: store double* [[A]], double** [[TMP14]], align 8 6209 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 6210 // CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 6211 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6212 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 6213 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 6214 // CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6215 // CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 6216 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 6217 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 6218 // CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 6219 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6220 // CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 6221 // CHECK17-NEXT: store i64 2, i64* [[TMP22]], align 8 6222 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6223 // CHECK17-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 6224 // CHECK17-NEXT: store i64 2, i64* [[TMP24]], align 8 6225 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 6226 // CHECK17-NEXT: store i8* null, i8** [[TMP25]], align 8 6227 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6228 // CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 6229 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 6230 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6231 // CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 6232 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 6233 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 6234 // CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8 6235 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 6236 // CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 6237 // CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 6238 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 6239 // CHECK17-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 6240 // CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 6241 // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 6242 // CHECK17-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 6243 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 6244 // CHECK17-NEXT: store i8* null, i8** [[TMP36]], align 8 6245 // CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6246 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6247 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6248 // CHECK17-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6249 // CHECK17-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 6250 // CHECK17-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6251 // CHECK17: omp_offload.failed: 6252 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 6253 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 6254 // CHECK17: omp_offload.cont: 6255 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 6256 // CHECK17: omp_if.else: 6257 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 6258 // CHECK17-NEXT: br label [[OMP_IF_END]] 6259 // CHECK17: omp_if.end: 6260 // CHECK17-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 6261 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 6262 // CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 6263 // CHECK17-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 6264 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 6265 // CHECK17-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 6266 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 6267 // CHECK17-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 6268 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 6269 // CHECK17-NEXT: ret i32 [[ADD4]] 6270 // 6271 // 6272 // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici 6273 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 6274 // CHECK17-NEXT: entry: 6275 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6276 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 6277 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 6278 // CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1 6279 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6280 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6281 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6282 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 6283 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 6284 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 6285 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 6286 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6287 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 6288 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 6289 // CHECK17-NEXT: store i8 0, i8* [[AAA]], align 1 6290 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6291 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6292 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 6293 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 6294 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 6295 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6296 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 6297 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6298 // CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 6299 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 6300 // CHECK17-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 6301 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 6302 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6303 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 6304 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6305 // CHECK17: omp_if.then: 6306 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6307 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 6308 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 6309 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6310 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 6311 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 6312 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 6313 // CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8 6314 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6315 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 6316 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 6317 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6318 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 6319 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 6320 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 6321 // CHECK17-NEXT: store i8* null, i8** [[TMP16]], align 8 6322 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6323 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 6324 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 6325 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6326 // CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 6327 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 6328 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 6329 // CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 6330 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6331 // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 6332 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 6333 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6334 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 6335 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 6336 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 6337 // CHECK17-NEXT: store i8* null, i8** [[TMP26]], align 8 6338 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6339 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6340 // CHECK17-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6341 // CHECK17-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 6342 // CHECK17-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6343 // CHECK17: omp_offload.failed: 6344 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 6345 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 6346 // CHECK17: omp_offload.cont: 6347 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 6348 // CHECK17: omp_if.else: 6349 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 6350 // CHECK17-NEXT: br label [[OMP_IF_END]] 6351 // CHECK17: omp_if.end: 6352 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 6353 // CHECK17-NEXT: ret i32 [[TMP31]] 6354 // 6355 // 6356 // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6357 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 6358 // CHECK17-NEXT: entry: 6359 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6360 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 6361 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 6362 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6363 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6364 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6365 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 6366 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 6367 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 6368 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6369 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 6370 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 6371 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6372 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6373 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 6374 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 6375 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 6376 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6377 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 6378 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6379 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6380 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 6381 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6382 // CHECK17: omp_if.then: 6383 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6384 // CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 6385 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 6386 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6387 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 6388 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 6389 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 6390 // CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8 6391 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6392 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 6393 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 6394 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6395 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 6396 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 6397 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 6398 // CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8 6399 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6400 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 6401 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 6402 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6403 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 6404 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 6405 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 6406 // CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 6407 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6408 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6409 // CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6410 // CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 6411 // CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6412 // CHECK17: omp_offload.failed: 6413 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 6414 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 6415 // CHECK17: omp_offload.cont: 6416 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 6417 // CHECK17: omp_if.else: 6418 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 6419 // CHECK17-NEXT: br label [[OMP_IF_END]] 6420 // CHECK17: omp_if.end: 6421 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 6422 // CHECK17-NEXT: ret i32 [[TMP24]] 6423 // 6424 // 6425 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 6426 // CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 6427 // CHECK17-NEXT: entry: 6428 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6429 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 6430 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6431 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 6432 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 6433 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 6434 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 6435 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 6436 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6437 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6438 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 6439 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 6440 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 6441 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6442 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6443 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 6444 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 6445 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 6446 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 6447 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 6448 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 6449 // CHECK17-NEXT: ret void 6450 // 6451 // 6452 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10 6453 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 6454 // CHECK17-NEXT: entry: 6455 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6456 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6457 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6458 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 6459 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6460 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 6461 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 6462 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6463 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 6464 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6465 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6466 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6467 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6468 // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 6469 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6470 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6471 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 6472 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 6473 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6474 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6475 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 6476 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 6477 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 6478 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6479 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6480 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 6481 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 6482 // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 6483 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 6484 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6485 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6486 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 6487 // CHECK17-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 6488 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6489 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 6490 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6491 // CHECK17: cond.true: 6492 // CHECK17-NEXT: br label [[COND_END:%.*]] 6493 // CHECK17: cond.false: 6494 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6495 // CHECK17-NEXT: br label [[COND_END]] 6496 // CHECK17: cond.end: 6497 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 6498 // CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 6499 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6500 // CHECK17-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 6501 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6502 // CHECK17: omp.inner.for.cond: 6503 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6504 // CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6505 // CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 6506 // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6507 // CHECK17: omp.inner.for.body: 6508 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6509 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 6510 // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 6511 // CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 6512 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 6513 // CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 6514 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 6515 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 6516 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 6517 // CHECK17-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 6518 // CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 6519 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 6520 // CHECK17-NEXT: store double [[INC]], double* [[A5]], align 8 6521 // CHECK17-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 6522 // CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 6523 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 6524 // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 6525 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 6526 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6527 // CHECK17: omp.body.continue: 6528 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6529 // CHECK17: omp.inner.for.inc: 6530 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6531 // CHECK17-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 6532 // CHECK17-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 6533 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 6534 // CHECK17: omp.inner.for.end: 6535 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6536 // CHECK17: omp.loop.exit: 6537 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 6538 // CHECK17-NEXT: ret void 6539 // 6540 // 6541 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 6542 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6543 // CHECK17-NEXT: entry: 6544 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6545 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6546 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 6547 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6548 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6549 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6550 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 6551 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6552 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6553 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 6554 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6555 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6556 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6557 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 6558 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6559 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 6560 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6561 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 6562 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 6563 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 6564 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6565 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 6566 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6567 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 6568 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 6569 // CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 6570 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 6571 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 6572 // CHECK17-NEXT: ret void 6573 // 6574 // 6575 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..13 6576 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 6577 // CHECK17-NEXT: entry: 6578 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6579 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6580 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6581 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6582 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 6583 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6584 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6585 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 6586 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6587 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6588 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6589 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6590 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 6591 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6592 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6593 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6594 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 6595 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6596 // CHECK17-NEXT: ret void 6597 // 6598 // 6599 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 6600 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6601 // CHECK17-NEXT: entry: 6602 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6603 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6604 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6605 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6606 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6607 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6608 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6609 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6610 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6611 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6612 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6613 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 6614 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6615 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 6616 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 6617 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 6618 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6619 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 6620 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6621 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 6622 // CHECK17-NEXT: ret void 6623 // 6624 // 6625 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..16 6626 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 6627 // CHECK17-NEXT: entry: 6628 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6629 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6630 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6631 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6632 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6633 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6634 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 6635 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6636 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6637 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6638 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6639 // CHECK17-NEXT: [[I:%.*]] = alloca i64, align 8 6640 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6641 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6642 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6643 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6644 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6645 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6646 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6647 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6648 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 6649 // CHECK17-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 6650 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 6651 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6652 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6653 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 6654 // CHECK17-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 6655 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6656 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 6657 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6658 // CHECK17: cond.true: 6659 // CHECK17-NEXT: br label [[COND_END:%.*]] 6660 // CHECK17: cond.false: 6661 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6662 // CHECK17-NEXT: br label [[COND_END]] 6663 // CHECK17: cond.end: 6664 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 6665 // CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 6666 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6667 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 6668 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6669 // CHECK17: omp.inner.for.cond: 6670 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6671 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6672 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 6673 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6674 // CHECK17: omp.inner.for.body: 6675 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6676 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 6677 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 6678 // CHECK17-NEXT: store i64 [[ADD]], i64* [[I]], align 8 6679 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 6680 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 6681 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 6682 // CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 6683 // CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 6684 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 6685 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 6686 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 6687 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 6688 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 6689 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 6690 // CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 6691 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6692 // CHECK17: omp.body.continue: 6693 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6694 // CHECK17: omp.inner.for.inc: 6695 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6696 // CHECK17-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 6697 // CHECK17-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8 6698 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] 6699 // CHECK17: omp.inner.for.end: 6700 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6701 // CHECK17: omp.loop.exit: 6702 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 6703 // CHECK17-NEXT: ret void 6704 // 6705 // 6706 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 6707 // CHECK17-SAME: () #[[ATTR6]] { 6708 // CHECK17-NEXT: entry: 6709 // CHECK17-NEXT: call void @__tgt_register_requires(i64 1) 6710 // CHECK17-NEXT: ret void 6711 // 6712 // 6713 // CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv 6714 // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { 6715 // CHECK19-NEXT: entry: 6716 // CHECK19-NEXT: ret i64 0 6717 // 6718 // 6719 // CHECK19-LABEL: define {{[^@]+}}@_Z3fooi 6720 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 6721 // CHECK19-NEXT: entry: 6722 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6723 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 6724 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 6725 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 4 6726 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 6727 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 6728 // CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 6729 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 6730 // CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 6731 // CHECK19-NEXT: [[K:%.*]] = alloca i64, align 8 6732 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6733 // CHECK19-NEXT: [[LIN:%.*]] = alloca i32, align 4 6734 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6735 // CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 6736 // CHECK19-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 6737 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 6738 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 6739 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 6740 // CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 6741 // CHECK19-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 6742 // CHECK19-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 6743 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 6744 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 6745 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 6746 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6747 // CHECK19-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 6748 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 6749 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4 6750 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4 6751 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4 6752 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 6753 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 6754 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6755 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 6756 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 6757 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6758 // CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 6759 // CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 6760 // CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 6761 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 6762 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 6763 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 6764 // CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 6765 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 6766 // CHECK19-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) 6767 // CHECK19-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 6768 // CHECK19-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6769 // CHECK19: omp_offload.failed: 6770 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] 6771 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 6772 // CHECK19: omp_offload.cont: 6773 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 6774 // CHECK19-NEXT: store i64 [[CALL]], i64* [[K]], align 8 6775 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 6776 // CHECK19-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 6777 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4 6778 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR4]] 6779 // CHECK19-NEXT: store i32 12, i32* [[LIN]], align 4 6780 // CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 6781 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6782 // CHECK19-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 6783 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6784 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4 6785 // CHECK19-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4 6786 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 6787 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 6788 // CHECK19-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4 6789 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4 6790 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6791 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 6792 // CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4 6793 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6794 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 6795 // CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4 6796 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6797 // CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 6798 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6799 // CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 6800 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4 6801 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6802 // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 6803 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4 6804 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6805 // CHECK19-NEXT: store i8* null, i8** [[TMP24]], align 4 6806 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6807 // CHECK19-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 6808 // CHECK19-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4 6809 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6810 // CHECK19-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 6811 // CHECK19-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4 6812 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6813 // CHECK19-NEXT: store i8* null, i8** [[TMP29]], align 4 6814 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6815 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6816 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 6817 // CHECK19-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 6818 // CHECK19-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 6819 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 6820 // CHECK19-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4 6821 // CHECK19-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 6822 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 6823 // CHECK19-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4 6824 // CHECK19-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 6825 // CHECK19-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 6826 // CHECK19-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 6827 // CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 6828 // CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 6829 // CHECK19-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4 6830 // CHECK19-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 6831 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false) 6832 // CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 6833 // CHECK19-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 6834 // CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 6835 // CHECK19-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8* 6836 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 6837 // CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 6838 // CHECK19-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8* 6839 // CHECK19-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8* 6840 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false) 6841 // CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 6842 // CHECK19-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8* 6843 // CHECK19-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8* 6844 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false) 6845 // CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 6846 // CHECK19-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 6847 // CHECK19-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4 6848 // CHECK19-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) 6849 // CHECK19-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 6850 // CHECK19-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4 6851 // CHECK19-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4 6852 // CHECK19-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 6853 // CHECK19-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 6854 // CHECK19-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2 6855 // CHECK19-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 6856 // CHECK19-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4 6857 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10 6858 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6859 // CHECK19: omp_if.then: 6860 // CHECK19-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 6861 // CHECK19-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* 6862 // CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4 6863 // CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 6864 // CHECK19-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32* 6865 // CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4 6866 // CHECK19-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 6867 // CHECK19-NEXT: store i8* null, i8** [[TMP66]], align 4 6868 // CHECK19-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 6869 // CHECK19-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32* 6870 // CHECK19-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4 6871 // CHECK19-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 6872 // CHECK19-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32* 6873 // CHECK19-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4 6874 // CHECK19-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 6875 // CHECK19-NEXT: store i8* null, i8** [[TMP71]], align 4 6876 // CHECK19-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 6877 // CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 6878 // CHECK19-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6879 // CHECK19-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0 6880 // CHECK19-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 6881 // CHECK19: omp_offload.failed9: 6882 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 6883 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT10]] 6884 // CHECK19: omp_offload.cont10: 6885 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 6886 // CHECK19: omp_if.else: 6887 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]] 6888 // CHECK19-NEXT: br label [[OMP_IF_END]] 6889 // CHECK19: omp_if.end: 6890 // CHECK19-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4 6891 // CHECK19-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4 6892 // CHECK19-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4 6893 // CHECK19-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4 6894 // CHECK19-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4 6895 // CHECK19-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 6896 // CHECK19-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 6897 // CHECK19-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 6898 // CHECK19-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4 6899 // CHECK19-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20 6900 // CHECK19-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]] 6901 // CHECK19: omp_if.then13: 6902 // CHECK19-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4 6903 // CHECK19-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64 6904 // CHECK19-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]] 6905 // CHECK19-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8 6906 // CHECK19-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64 6907 // CHECK19-NEXT: [[TMP87:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 6908 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP87]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i32 80, i1 false) 6909 // CHECK19-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 6910 // CHECK19-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32* 6911 // CHECK19-NEXT: store i32 [[TMP78]], i32* [[TMP89]], align 4 6912 // CHECK19-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 6913 // CHECK19-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32* 6914 // CHECK19-NEXT: store i32 [[TMP78]], i32* [[TMP91]], align 4 6915 // CHECK19-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 6916 // CHECK19-NEXT: store i8* null, i8** [[TMP92]], align 4 6917 // CHECK19-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 6918 // CHECK19-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]** 6919 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4 6920 // CHECK19-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 6921 // CHECK19-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]** 6922 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4 6923 // CHECK19-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 6924 // CHECK19-NEXT: store i8* null, i8** [[TMP97]], align 4 6925 // CHECK19-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 6926 // CHECK19-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* 6927 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP99]], align 4 6928 // CHECK19-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 6929 // CHECK19-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32* 6930 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP101]], align 4 6931 // CHECK19-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 6932 // CHECK19-NEXT: store i8* null, i8** [[TMP102]], align 4 6933 // CHECK19-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 6934 // CHECK19-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to float** 6935 // CHECK19-NEXT: store float* [[VLA]], float** [[TMP104]], align 4 6936 // CHECK19-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 6937 // CHECK19-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float** 6938 // CHECK19-NEXT: store float* [[VLA]], float** [[TMP106]], align 4 6939 // CHECK19-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 6940 // CHECK19-NEXT: store i64 [[TMP83]], i64* [[TMP107]], align 4 6941 // CHECK19-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 6942 // CHECK19-NEXT: store i8* null, i8** [[TMP108]], align 4 6943 // CHECK19-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 6944 // CHECK19-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to [5 x [10 x double]]** 6945 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP110]], align 4 6946 // CHECK19-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 6947 // CHECK19-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]** 6948 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4 6949 // CHECK19-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 6950 // CHECK19-NEXT: store i8* null, i8** [[TMP113]], align 4 6951 // CHECK19-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 6952 // CHECK19-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32* 6953 // CHECK19-NEXT: store i32 5, i32* [[TMP115]], align 4 6954 // CHECK19-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 6955 // CHECK19-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32* 6956 // CHECK19-NEXT: store i32 5, i32* [[TMP117]], align 4 6957 // CHECK19-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 6958 // CHECK19-NEXT: store i8* null, i8** [[TMP118]], align 4 6959 // CHECK19-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 6960 // CHECK19-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32* 6961 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP120]], align 4 6962 // CHECK19-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 6963 // CHECK19-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32* 6964 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP122]], align 4 6965 // CHECK19-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 6966 // CHECK19-NEXT: store i8* null, i8** [[TMP123]], align 4 6967 // CHECK19-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 6968 // CHECK19-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to double** 6969 // CHECK19-NEXT: store double* [[VLA1]], double** [[TMP125]], align 4 6970 // CHECK19-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 6971 // CHECK19-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double** 6972 // CHECK19-NEXT: store double* [[VLA1]], double** [[TMP127]], align 4 6973 // CHECK19-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 6974 // CHECK19-NEXT: store i64 [[TMP86]], i64* [[TMP128]], align 4 6975 // CHECK19-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 6976 // CHECK19-NEXT: store i8* null, i8** [[TMP129]], align 4 6977 // CHECK19-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 6978 // CHECK19-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to %struct.TT** 6979 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP131]], align 4 6980 // CHECK19-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 6981 // CHECK19-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT** 6982 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 4 6983 // CHECK19-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 6984 // CHECK19-NEXT: store i8* null, i8** [[TMP134]], align 4 6985 // CHECK19-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 6986 // CHECK19-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to i32* 6987 // CHECK19-NEXT: store i32 [[TMP80]], i32* [[TMP136]], align 4 6988 // CHECK19-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 6989 // CHECK19-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i32* 6990 // CHECK19-NEXT: store i32 [[TMP80]], i32* [[TMP138]], align 4 6991 // CHECK19-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 6992 // CHECK19-NEXT: store i8* null, i8** [[TMP139]], align 4 6993 // CHECK19-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 6994 // CHECK19-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 6995 // CHECK19-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6996 // CHECK19-NEXT: [[TMP143:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP140]], i8** [[TMP141]], i64* [[TMP142]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6997 // CHECK19-NEXT: [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 0 6998 // CHECK19-NEXT: br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] 6999 // CHECK19: omp_offload.failed17: 7000 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 7001 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT18]] 7002 // CHECK19: omp_offload.cont18: 7003 // CHECK19-NEXT: br label [[OMP_IF_END20:%.*]] 7004 // CHECK19: omp_if.else19: 7005 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]] 7006 // CHECK19-NEXT: br label [[OMP_IF_END20]] 7007 // CHECK19: omp_if.end20: 7008 // CHECK19-NEXT: [[TMP145:%.*]] = load i32, i32* [[A]], align 4 7009 // CHECK19-NEXT: [[TMP146:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 7010 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP146]]) 7011 // CHECK19-NEXT: ret i32 [[TMP145]] 7012 // 7013 // 7014 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 7015 // CHECK19-SAME: () #[[ATTR2:[0-9]+]] { 7016 // CHECK19-NEXT: entry: 7017 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 7018 // CHECK19-NEXT: ret void 7019 // 7020 // 7021 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 7022 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 7023 // CHECK19-NEXT: entry: 7024 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7025 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7026 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7027 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 7028 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7029 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7030 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7031 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7032 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 7033 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7034 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7035 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7036 // CHECK19-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 7037 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7038 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7039 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 7040 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 7041 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 7042 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7043 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 7044 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7045 // CHECK19: cond.true: 7046 // CHECK19-NEXT: br label [[COND_END:%.*]] 7047 // CHECK19: cond.false: 7048 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7049 // CHECK19-NEXT: br label [[COND_END]] 7050 // CHECK19: cond.end: 7051 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 7052 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7053 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7054 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 7055 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7056 // CHECK19: omp.inner.for.cond: 7057 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7058 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7059 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 7060 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7061 // CHECK19: omp.inner.for.body: 7062 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7063 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 7064 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 7065 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7066 // CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 7067 // CHECK19-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 7068 // CHECK19-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 7069 // CHECK19: .cancel.exit: 7070 // CHECK19-NEXT: br label [[CANCEL_EXIT:%.*]] 7071 // CHECK19: .cancel.continue: 7072 // CHECK19-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2) 7073 // CHECK19-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 7074 // CHECK19-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]] 7075 // CHECK19: .cancel.exit2: 7076 // CHECK19-NEXT: br label [[CANCEL_EXIT]] 7077 // CHECK19: .cancel.continue3: 7078 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7079 // CHECK19: omp.body.continue: 7080 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7081 // CHECK19: omp.inner.for.inc: 7082 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7083 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 7084 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 7085 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 7086 // CHECK19: omp.inner.for.end: 7087 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7088 // CHECK19: omp.loop.exit: 7089 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 7090 // CHECK19-NEXT: br label [[CANCEL_CONT:%.*]] 7091 // CHECK19: cancel.cont: 7092 // CHECK19-NEXT: ret void 7093 // CHECK19: cancel.exit: 7094 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 7095 // CHECK19-NEXT: br label [[CANCEL_CONT]] 7096 // 7097 // 7098 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 7099 // CHECK19-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 7100 // CHECK19-NEXT: entry: 7101 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7102 // CHECK19-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 7103 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 7104 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7105 // CHECK19-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 7106 // CHECK19-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 7107 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 7108 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 7109 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 7110 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) 7111 // CHECK19-NEXT: ret void 7112 // 7113 // 7114 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 7115 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 7116 // CHECK19-NEXT: entry: 7117 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7118 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7119 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7120 // CHECK19-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 7121 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7122 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 7123 // CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 7124 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7125 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7126 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7127 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7128 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 7129 // CHECK19-NEXT: [[K1:%.*]] = alloca i64, align 8 7130 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7131 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7132 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7133 // CHECK19-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 7134 // CHECK19-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 7135 // CHECK19-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 7136 // CHECK19-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 7137 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7138 // CHECK19-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 7139 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7140 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7141 // CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 7142 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 7143 // CHECK19-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 7144 // CHECK19-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 7145 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 7146 // CHECK19: omp.dispatch.cond: 7147 // CHECK19-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 7148 // CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 7149 // CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 7150 // CHECK19: omp.dispatch.body: 7151 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7152 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 7153 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7154 // CHECK19: omp.inner.for.cond: 7155 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 7156 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 7157 // CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 7158 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7159 // CHECK19: omp.inner.for.body: 7160 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 7161 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 7162 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 7163 // CHECK19-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13 7164 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !13 7165 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 7166 // CHECK19-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 7167 // CHECK19-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 7168 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 7169 // CHECK19-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13 7170 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !13 7171 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 7172 // CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13 7173 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7174 // CHECK19: omp.body.continue: 7175 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7176 // CHECK19: omp.inner.for.inc: 7177 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 7178 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 7179 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 7180 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 7181 // CHECK19: omp.inner.for.end: 7182 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 7183 // CHECK19: omp.dispatch.inc: 7184 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 7185 // CHECK19: omp.dispatch.end: 7186 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 7187 // CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 7188 // CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 7189 // CHECK19: .omp.linear.pu: 7190 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[K1]], align 8 7191 // CHECK19-NEXT: store i64 [[TMP15]], i64* [[TMP0]], align 8 7192 // CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 7193 // CHECK19: .omp.linear.pu.done: 7194 // CHECK19-NEXT: ret void 7195 // 7196 // 7197 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 7198 // CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 7199 // CHECK19-NEXT: entry: 7200 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7201 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 7202 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7203 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 7204 // CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 7205 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 7206 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7207 // CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 7208 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7209 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7210 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 7211 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 7212 // CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 7213 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 7214 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 7215 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 7216 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 7217 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 7218 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 7219 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 7220 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 7221 // CHECK19-NEXT: ret void 7222 // 7223 // 7224 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 7225 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 7226 // CHECK19-NEXT: entry: 7227 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7228 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7229 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7230 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 7231 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7232 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7233 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 7234 // CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 7235 // CHECK19-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 7236 // CHECK19-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 7237 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7238 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7239 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 7240 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7241 // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 7242 // CHECK19-NEXT: [[LIN2:%.*]] = alloca i32, align 4 7243 // CHECK19-NEXT: [[A3:%.*]] = alloca i32, align 4 7244 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7245 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7246 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7247 // CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 7248 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7249 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7250 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 7251 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 7252 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 7253 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 7254 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 7255 // CHECK19-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 7256 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 7257 // CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 7258 // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 7259 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7260 // CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 7261 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 7262 // CHECK19-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 7263 // CHECK19-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 7264 // CHECK19-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7265 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 7266 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7267 // CHECK19: cond.true: 7268 // CHECK19-NEXT: br label [[COND_END:%.*]] 7269 // CHECK19: cond.false: 7270 // CHECK19-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7271 // CHECK19-NEXT: br label [[COND_END]] 7272 // CHECK19: cond.end: 7273 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 7274 // CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 7275 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 7276 // CHECK19-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 7277 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7278 // CHECK19: omp.inner.for.cond: 7279 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7280 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7281 // CHECK19-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 7282 // CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7283 // CHECK19: omp.inner.for.body: 7284 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7285 // CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 7286 // CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 7287 // CHECK19-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 7288 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 7289 // CHECK19-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 7290 // CHECK19-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7291 // CHECK19-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 7292 // CHECK19-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 7293 // CHECK19-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 7294 // CHECK19-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 7295 // CHECK19-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4 7296 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 7297 // CHECK19-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 7298 // CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7299 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 7300 // CHECK19-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 7301 // CHECK19-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 7302 // CHECK19-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 7303 // CHECK19-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 7304 // CHECK19-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2 7305 // CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 7306 // CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 7307 // CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 7308 // CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 7309 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7310 // CHECK19: omp.body.continue: 7311 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7312 // CHECK19: omp.inner.for.inc: 7313 // CHECK19-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7314 // CHECK19-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 7315 // CHECK19-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 7316 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 7317 // CHECK19: omp.inner.for.end: 7318 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7319 // CHECK19: omp.loop.exit: 7320 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 7321 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 7322 // CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 7323 // CHECK19-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 7324 // CHECK19: .omp.linear.pu: 7325 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4 7326 // CHECK19-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4 7327 // CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4 7328 // CHECK19-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4 7329 // CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 7330 // CHECK19: .omp.linear.pu.done: 7331 // CHECK19-NEXT: ret void 7332 // 7333 // 7334 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map. 7335 // CHECK19-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { 7336 // CHECK19-NEXT: entry: 7337 // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 7338 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 7339 // CHECK19-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 7340 // CHECK19-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 7341 // CHECK19-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 7342 // CHECK19-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 7343 // CHECK19-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 7344 // CHECK19-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 7345 // CHECK19-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 7346 // CHECK19-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 7347 // CHECK19-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 7348 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 7349 // CHECK19-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 7350 // CHECK19-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 7351 // CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 7352 // CHECK19-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 7353 // CHECK19-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 7354 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 7355 // CHECK19-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 7356 // CHECK19-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 7357 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 7358 // CHECK19-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 7359 // CHECK19-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 7360 // CHECK19-NEXT: ret void 7361 // 7362 // 7363 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. 7364 // CHECK19-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { 7365 // CHECK19-NEXT: entry: 7366 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 7367 // CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 7368 // CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 7369 // CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 7370 // CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 7371 // CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 7372 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 7373 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 7374 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 7375 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 7376 // CHECK19-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 7377 // CHECK19-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4 7378 // CHECK19-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4 7379 // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 7380 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 7381 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 7382 // CHECK19-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 7383 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 7384 // CHECK19-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 7385 // CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 7386 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 7387 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 7388 // CHECK19-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 7389 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 7390 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 7391 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 7392 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 7393 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 7394 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 7395 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 7396 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 7397 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 7398 // CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 7399 // CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 7400 // CHECK19-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 7401 // CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 7402 // CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 7403 // CHECK19-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 7404 // CHECK19-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 7405 // CHECK19-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 7406 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 7407 // CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 7408 // CHECK19-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 7409 // CHECK19-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 7410 // CHECK19-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 7411 // CHECK19-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 7412 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 7413 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 7414 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 7415 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 7416 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 7417 // CHECK19-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 7418 // CHECK19-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 7419 // CHECK19-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] 7420 // CHECK19: omp_offload.failed.i: 7421 // CHECK19-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2 7422 // CHECK19-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 7423 // CHECK19-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25 7424 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 7425 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4 7426 // CHECK19-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25 7427 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !25 7428 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4 7429 // CHECK19-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25 7430 // CHECK19-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !25 7431 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR4]] 7432 // CHECK19-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] 7433 // CHECK19: .omp_outlined..3.exit: 7434 // CHECK19-NEXT: ret i32 0 7435 // 7436 // 7437 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 7438 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 7439 // CHECK19-NEXT: entry: 7440 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7441 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7442 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 7443 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 7444 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7445 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7446 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7447 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 7448 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 7449 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 7450 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 7451 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 7452 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 7453 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 7454 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 7455 // CHECK19-NEXT: ret void 7456 // 7457 // 7458 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 7459 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 7460 // CHECK19-NEXT: entry: 7461 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7462 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7463 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7464 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7465 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7466 // CHECK19-NEXT: [[TMP:%.*]] = alloca i16, align 2 7467 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7468 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7469 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7470 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7471 // CHECK19-NEXT: [[IT:%.*]] = alloca i16, align 2 7472 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7473 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7474 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7475 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7476 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7477 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7478 // CHECK19-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 7479 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7480 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7481 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 7482 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 7483 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 7484 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7485 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 7486 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7487 // CHECK19: cond.true: 7488 // CHECK19-NEXT: br label [[COND_END:%.*]] 7489 // CHECK19: cond.false: 7490 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7491 // CHECK19-NEXT: br label [[COND_END]] 7492 // CHECK19: cond.end: 7493 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 7494 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7495 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7496 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 7497 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7498 // CHECK19: omp.inner.for.cond: 7499 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7500 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7501 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 7502 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7503 // CHECK19: omp.inner.for.body: 7504 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7505 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 7506 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 7507 // CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 7508 // CHECK19-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 7509 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 7510 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 7511 // CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 7512 // CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 7513 // CHECK19-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 7514 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 7515 // CHECK19-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 7516 // CHECK19-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2 7517 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7518 // CHECK19: omp.body.continue: 7519 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7520 // CHECK19: omp.inner.for.inc: 7521 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7522 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 7523 // CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 7524 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 7525 // CHECK19: omp.inner.for.end: 7526 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7527 // CHECK19: omp.loop.exit: 7528 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 7529 // CHECK19-NEXT: ret void 7530 // 7531 // 7532 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 7533 // CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 7534 // CHECK19-NEXT: entry: 7535 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7536 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 7537 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 7538 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 7539 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 7540 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 7541 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 7542 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 7543 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 7544 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 7545 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 7546 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 7547 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7548 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 7549 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 7550 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 7551 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 7552 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 7553 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 7554 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 7555 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 7556 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 7557 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 7558 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 7559 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 7560 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 7561 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 7562 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 7563 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 7564 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 7565 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 7566 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 7567 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 7568 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 7569 // CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 7570 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 7571 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 7572 // CHECK19-NEXT: ret void 7573 // 7574 // 7575 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 7576 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 7577 // CHECK19-NEXT: entry: 7578 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7579 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7580 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7581 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 7582 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 7583 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 7584 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 7585 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 7586 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 7587 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 7588 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 7589 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 7590 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7591 // CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1 7592 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7593 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7594 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7595 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7596 // CHECK19-NEXT: [[IT:%.*]] = alloca i8, align 1 7597 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7598 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7599 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7600 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 7601 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 7602 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 7603 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 7604 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 7605 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 7606 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 7607 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 7608 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 7609 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 7610 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 7611 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 7612 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 7613 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 7614 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 7615 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 7616 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 7617 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7618 // CHECK19-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 7619 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7620 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7621 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 7622 // CHECK19-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 7623 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 7624 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 7625 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 7626 // CHECK19: omp.dispatch.cond: 7627 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7628 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 7629 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7630 // CHECK19: cond.true: 7631 // CHECK19-NEXT: br label [[COND_END:%.*]] 7632 // CHECK19: cond.false: 7633 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7634 // CHECK19-NEXT: br label [[COND_END]] 7635 // CHECK19: cond.end: 7636 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 7637 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7638 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7639 // CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 7640 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7641 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7642 // CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 7643 // CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 7644 // CHECK19: omp.dispatch.body: 7645 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7646 // CHECK19: omp.inner.for.cond: 7647 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7648 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7649 // CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 7650 // CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7651 // CHECK19: omp.inner.for.body: 7652 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7653 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 7654 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 7655 // CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 7656 // CHECK19-NEXT: store i8 [[CONV]], i8* [[IT]], align 1 7657 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4 7658 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 7659 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 7660 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 7661 // CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 7662 // CHECK19-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 7663 // CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 7664 // CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 7665 // CHECK19-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4 7666 // CHECK19-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 7667 // CHECK19-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4 7668 // CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 7669 // CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 7670 // CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 7671 // CHECK19-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4 7672 // CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 7673 // CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 7674 // CHECK19-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8 7675 // CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 7676 // CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 7677 // CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 7678 // CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 7679 // CHECK19-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 7680 // CHECK19-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8 7681 // CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 7682 // CHECK19-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 7683 // CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 7684 // CHECK19-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4 7685 // CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 7686 // CHECK19-NEXT: store i64 [[ADD20]], i64* [[X]], align 4 7687 // CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 7688 // CHECK19-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4 7689 // CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 7690 // CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 7691 // CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 7692 // CHECK19-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4 7693 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7694 // CHECK19: omp.body.continue: 7695 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7696 // CHECK19: omp.inner.for.inc: 7697 // CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7698 // CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 7699 // CHECK19-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 7700 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 7701 // CHECK19: omp.inner.for.end: 7702 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 7703 // CHECK19: omp.dispatch.inc: 7704 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7705 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 7706 // CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 7707 // CHECK19-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 7708 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7709 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 7710 // CHECK19-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 7711 // CHECK19-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 7712 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 7713 // CHECK19: omp.dispatch.end: 7714 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 7715 // CHECK19-NEXT: ret void 7716 // 7717 // 7718 // CHECK19-LABEL: define {{[^@]+}}@_Z3bari 7719 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 7720 // CHECK19-NEXT: entry: 7721 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7722 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 7723 // CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 7724 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7725 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 7726 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7727 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 7728 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 7729 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 7730 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 7731 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 7732 // CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 7733 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 7734 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 7735 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 7736 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 7737 // CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 7738 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 7739 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 7740 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 7741 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 7742 // CHECK19-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 7743 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 7744 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 7745 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 7746 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 7747 // CHECK19-NEXT: ret i32 [[TMP8]] 7748 // 7749 // 7750 // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 7751 // CHECK19-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 7752 // CHECK19-NEXT: entry: 7753 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 7754 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7755 // CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 7756 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 7757 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 7758 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 7759 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 7760 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 7761 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 7762 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 7763 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 7764 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7765 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 7766 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7767 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7768 // CHECK19-NEXT: store i32 [[ADD]], i32* [[B]], align 4 7769 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 7770 // CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 7771 // CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 7772 // CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 7773 // CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 7774 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 7775 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 7776 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 7777 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 7778 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 7779 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 7780 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 7781 // CHECK19: omp_if.then: 7782 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 7783 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 7784 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 7785 // CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 7786 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 7787 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false) 7788 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7789 // CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 7790 // CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 7791 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7792 // CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 7793 // CHECK19-NEXT: store double* [[A]], double** [[TMP14]], align 4 7794 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 7795 // CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 7796 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 7797 // CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 7798 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 7799 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 7800 // CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 7801 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 7802 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 7803 // CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 7804 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 7805 // CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 7806 // CHECK19-NEXT: store i32 2, i32* [[TMP22]], align 4 7807 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 7808 // CHECK19-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 7809 // CHECK19-NEXT: store i32 2, i32* [[TMP24]], align 4 7810 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 7811 // CHECK19-NEXT: store i8* null, i8** [[TMP25]], align 4 7812 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 7813 // CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 7814 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 7815 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 7816 // CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 7817 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 7818 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 7819 // CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 7820 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 7821 // CHECK19-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 7822 // CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 7823 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 7824 // CHECK19-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 7825 // CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 7826 // CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 7827 // CHECK19-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 7828 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 7829 // CHECK19-NEXT: store i8* null, i8** [[TMP36]], align 4 7830 // CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7831 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7832 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 7833 // CHECK19-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 7834 // CHECK19-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 7835 // CHECK19-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 7836 // CHECK19: omp_offload.failed: 7837 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 7838 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 7839 // CHECK19: omp_offload.cont: 7840 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 7841 // CHECK19: omp_if.else: 7842 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 7843 // CHECK19-NEXT: br label [[OMP_IF_END]] 7844 // CHECK19: omp_if.end: 7845 // CHECK19-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 7846 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 7847 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 7848 // CHECK19-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 7849 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 7850 // CHECK19-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 7851 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 7852 // CHECK19-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 7853 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 7854 // CHECK19-NEXT: ret i32 [[ADD3]] 7855 // 7856 // 7857 // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici 7858 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 7859 // CHECK19-NEXT: entry: 7860 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7861 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 7862 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 7863 // CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1 7864 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7865 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 7866 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 7867 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 7868 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 7869 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 7870 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 7871 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7872 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 7873 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 7874 // CHECK19-NEXT: store i8 0, i8* [[AAA]], align 1 7875 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 7876 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 7877 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 7878 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 7879 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 7880 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 7881 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 7882 // CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 7883 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 7884 // CHECK19-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 7885 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 7886 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 7887 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 7888 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 7889 // CHECK19: omp_if.then: 7890 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7891 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 7892 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 7893 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7894 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 7895 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 7896 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 7897 // CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4 7898 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 7899 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 7900 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 7901 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 7902 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 7903 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 7904 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 7905 // CHECK19-NEXT: store i8* null, i8** [[TMP16]], align 4 7906 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 7907 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 7908 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 7909 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 7910 // CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 7911 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 7912 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 7913 // CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 7914 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 7915 // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 7916 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 7917 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 7918 // CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 7919 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 7920 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 7921 // CHECK19-NEXT: store i8* null, i8** [[TMP26]], align 4 7922 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7923 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7924 // CHECK19-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 7925 // CHECK19-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 7926 // CHECK19-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 7927 // CHECK19: omp_offload.failed: 7928 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 7929 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 7930 // CHECK19: omp_offload.cont: 7931 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 7932 // CHECK19: omp_if.else: 7933 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 7934 // CHECK19-NEXT: br label [[OMP_IF_END]] 7935 // CHECK19: omp_if.end: 7936 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 7937 // CHECK19-NEXT: ret i32 [[TMP31]] 7938 // 7939 // 7940 // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 7941 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 7942 // CHECK19-NEXT: entry: 7943 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7944 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 7945 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 7946 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7947 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 7948 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 7949 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 7950 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 7951 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 7952 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7953 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 7954 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 7955 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 7956 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 7957 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 7958 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 7959 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 7960 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 7961 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 7962 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 7963 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 7964 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 7965 // CHECK19: omp_if.then: 7966 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7967 // CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 7968 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 7969 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7970 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 7971 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 7972 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 7973 // CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4 7974 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 7975 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 7976 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 7977 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 7978 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 7979 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 7980 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 7981 // CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4 7982 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 7983 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 7984 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 7985 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 7986 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 7987 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 7988 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 7989 // CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 7990 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7991 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7992 // CHECK19-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 7993 // CHECK19-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 7994 // CHECK19-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 7995 // CHECK19: omp_offload.failed: 7996 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 7997 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 7998 // CHECK19: omp_offload.cont: 7999 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 8000 // CHECK19: omp_if.else: 8001 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 8002 // CHECK19-NEXT: br label [[OMP_IF_END]] 8003 // CHECK19: omp_if.end: 8004 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 8005 // CHECK19-NEXT: ret i32 [[TMP24]] 8006 // 8007 // 8008 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 8009 // CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 8010 // CHECK19-NEXT: entry: 8011 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8012 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 8013 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8014 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8015 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 8016 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 8017 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8018 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 8019 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8020 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8021 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 8022 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 8023 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8024 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8025 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 8026 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 8027 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 8028 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 8029 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 8030 // CHECK19-NEXT: ret void 8031 // 8032 // 8033 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10 8034 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 8035 // CHECK19-NEXT: entry: 8036 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8037 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8038 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8039 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 8040 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8041 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8042 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 8043 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8044 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 8045 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8046 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8047 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 8048 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8049 // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 8050 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8051 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8052 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8053 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 8054 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8055 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8056 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 8057 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 8058 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8059 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8060 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 8061 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8062 // CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 8063 // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 8064 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8065 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 8066 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 8067 // CHECK19-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 8068 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8069 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 8070 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8071 // CHECK19: cond.true: 8072 // CHECK19-NEXT: br label [[COND_END:%.*]] 8073 // CHECK19: cond.false: 8074 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8075 // CHECK19-NEXT: br label [[COND_END]] 8076 // CHECK19: cond.end: 8077 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 8078 // CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 8079 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8080 // CHECK19-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 8081 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8082 // CHECK19: omp.inner.for.cond: 8083 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8084 // CHECK19-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8085 // CHECK19-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 8086 // CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8087 // CHECK19: omp.inner.for.body: 8088 // CHECK19-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8089 // CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 8090 // CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 8091 // CHECK19-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 8092 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 8093 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 8094 // CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 8095 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 8096 // CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 8097 // CHECK19-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 8098 // CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4 8099 // CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 8100 // CHECK19-NEXT: store double [[INC]], double* [[A4]], align 4 8101 // CHECK19-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 8102 // CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 8103 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 8104 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 8105 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 8106 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8107 // CHECK19: omp.body.continue: 8108 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8109 // CHECK19: omp.inner.for.inc: 8110 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8111 // CHECK19-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 8112 // CHECK19-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 8113 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 8114 // CHECK19: omp.inner.for.end: 8115 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8116 // CHECK19: omp.loop.exit: 8117 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 8118 // CHECK19-NEXT: ret void 8119 // 8120 // 8121 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 8122 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 8123 // CHECK19-NEXT: entry: 8124 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8125 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8126 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 8127 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8128 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8129 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8130 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 8131 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8132 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8133 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 8134 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8135 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8136 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 8137 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8138 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8139 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 8140 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 8141 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 8142 // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8143 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 8144 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8145 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 8146 // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 8147 // CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 8148 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 8149 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 8150 // CHECK19-NEXT: ret void 8151 // 8152 // 8153 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..13 8154 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 8155 // CHECK19-NEXT: entry: 8156 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8157 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8158 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8159 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8160 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 8161 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8162 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8163 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 8164 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8165 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8166 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8167 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8168 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 8169 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8170 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8171 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 8172 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8173 // CHECK19-NEXT: ret void 8174 // 8175 // 8176 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 8177 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 8178 // CHECK19-NEXT: entry: 8179 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8180 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8181 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8182 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8183 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8184 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8185 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8186 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8187 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8188 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8189 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8190 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 8191 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 8192 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 8193 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8194 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 8195 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8196 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 8197 // CHECK19-NEXT: ret void 8198 // 8199 // 8200 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..16 8201 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 8202 // CHECK19-NEXT: entry: 8203 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8204 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8205 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8206 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8207 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8208 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8209 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 8210 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8211 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8212 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 8213 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8214 // CHECK19-NEXT: [[I:%.*]] = alloca i64, align 8 8215 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8216 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8217 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8218 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8219 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8220 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8221 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8222 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8223 // CHECK19-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 8224 // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 8225 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8226 // CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 8227 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 8228 // CHECK19-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 8229 // CHECK19-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8230 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 8231 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8232 // CHECK19: cond.true: 8233 // CHECK19-NEXT: br label [[COND_END:%.*]] 8234 // CHECK19: cond.false: 8235 // CHECK19-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8236 // CHECK19-NEXT: br label [[COND_END]] 8237 // CHECK19: cond.end: 8238 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 8239 // CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 8240 // CHECK19-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8241 // CHECK19-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 8242 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8243 // CHECK19: omp.inner.for.cond: 8244 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8245 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8246 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 8247 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8248 // CHECK19: omp.inner.for.body: 8249 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8250 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 8251 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 8252 // CHECK19-NEXT: store i64 [[ADD]], i64* [[I]], align 8 8253 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 8254 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 8255 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 8256 // CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 8257 // CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 8258 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 8259 // CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 8260 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 8261 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 8262 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 8263 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 8264 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 8265 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8266 // CHECK19: omp.body.continue: 8267 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8268 // CHECK19: omp.inner.for.inc: 8269 // CHECK19-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8270 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 8271 // CHECK19-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 8272 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] 8273 // CHECK19: omp.inner.for.end: 8274 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8275 // CHECK19: omp.loop.exit: 8276 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 8277 // CHECK19-NEXT: ret void 8278 // 8279 // 8280 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 8281 // CHECK19-SAME: () #[[ATTR6]] { 8282 // CHECK19-NEXT: entry: 8283 // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) 8284 // CHECK19-NEXT: ret void 8285 // 8286