1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test host codegen.
3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1
4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK2
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK3
7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK4
9 
10 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK5
11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
12 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK6
13 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK7
14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK8
16 
17 // Test target codegen - host bc file has to be created first.
18 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
19 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK9
20 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
21 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK10
22 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
23 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK11
24 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
25 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK12
26 
27 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
28 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK13
29 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
30 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK14
31 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
32 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK15
33 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
34 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK16
35 
36 // Test host codegen.
37 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK17
38 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
39 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK18
40 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK19
41 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
42 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK20
43 
44 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK21
45 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
46 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK22
47 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK23
48 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
49 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK24
50 
51 // Test target codegen - host bc file has to be created first.
52 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
53 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK25
54 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
55 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK26
56 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
57 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK27
58 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
59 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK28
60 
61 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
62 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK29
63 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
64 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK30
65 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
66 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK31
67 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
68 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK32
69 
70 // expected-no-diagnostics
71 #ifndef HEADER
72 #define HEADER
73 
74 
75 
76 
77 // We have 8 target regions, but only 7 that actually will generate offloading
78 // code, only 6 will have mapped arguments, and only 4 have all-constant map
79 // sizes.
80 
81 
82 
83 // Check target registration is registered as a Ctor.
84 
85 
86 template<typename tx, typename ty>
87 struct TT{
88   tx X;
89   ty Y;
90 };
91 
92 long long get_val() { return 0; }
93 
94 int foo(int n) {
95   int a = 0;
96   short aa = 0;
97   float b[10];
98   float bn[n];
99   double c[5][10];
100   double cn[5][n];
101   TT<long long, char> d;
102 
103   #pragma omp target parallel for
104   for (int i = 3; i < 32; i += 5) {
105 #pragma omp cancel for
106 #pragma omp cancellation point for
107   }
108 
109   long long k = get_val();
110   #pragma omp target parallel for if(target: 0) linear(k : 3) schedule(dynamic)
111   for (int i = 10; i > 1; i--) {
112     a += 1;
113   }
114 
115   // CEHCK-32:    [[FPSIZEGEP]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 0
116   // CEHCK-32:    [[FPSIZEADDR:%.+]] = bitcast [3 x i64]* [[FPSIZEGEP]] to i8*
117   // CEHCK-32:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPSIZEADDR]], i8* align 8 bitcast ([3 x i64]* [[SIZET2]] to i8*), i64 24, i1 false)
118   // CEHCK-32:    [[FPBPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 1
119   // CEHCK-32:    [[FPBPADDR:%.+]] = bitcast [3 x i8*]* [[FPBPGEP]] to i8*
120   // CEHCK-32:    [[BPCAST:%.+]] = bitcast i8** [[BPGEP]] to i8*
121   // CEHCK-32:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPBPADDR]], i8* align 8 [[BPCAST]], i64 24, i1 false)
122   // CEHCK-32:    [[FPPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 2
123   // CEHCK-32:    [[FPPADDR:%.+]] = bitcast [3 x i8*]* [[FPPGEP]] to i8*
124   // CEHCK-32:    [[PCAST:%.+]] = bitcast i8** [[PGEP]] to i8*
125   // CEHCK-32:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPPADDR]], i8* align 8 [[BCAST]], i64 24, i1 false)
126   // CEHCK-64:    [[FPBPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 0
127   // CEHCK-64:    [[FPBPADDR:%.+]] = bitcast [3 x i8*]* [[FPBPGEP]] to i8*
128   // CEHCK-64:    [[BPCAST:%.+]] = bitcast i8** [[BPGEP]] to i8*
129   // CEHCK-64:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPBPADDR]], i8* align 8 [[BPCAST]], i64 24, i1 false)
130   // CEHCK-64:    [[FPPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 1
131   // CEHCK-64:    [[FPPADDR:%.+]] = bitcast [3 x i8*]* [[FPPGEP]] to i8*
132   // CEHCK-64:    [[PCAST:%.+]] = bitcast i8** [[PGEP]] to i8*
133   // CEHCK-64:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPPADDR]], i8* align 8 [[BCAST]], i64 24, i1 false)
134   // CEHCK-64:    [[FPSIZEGEP]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 2
135   // CEHCK-64:    [[FPSIZEADDR:%.+]] = bitcast [3 x i64]* [[FPSIZEGEP]] to i8*
136   // CEHCK-64:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPSIZEADDR]], i8* align 8 bitcast ([3 x i64]* [[SIZET2]] to i8*), i64 24, i1 false)
137   int lin = 12;
138   #pragma omp target parallel for if(target: 1) linear(lin, a : get_val()) nowait
139   for (unsigned long long it = 2000; it >= 600; it-=400) {
140     aa += 1;
141   }
142 
143 
144 
145 
146   #pragma omp target parallel for if(target: n>10)
147   for (short it = 6; it <= 20; it-=-4) {
148     a += 1;
149     aa += 1;
150   }
151 
152   // We capture 3 VLA sizes in this target region
153 
154 
155 
156 
157 
158   // The names below are not necessarily consistent with the names used for the
159   // addresses above as some are repeated.
160 
161 
162 
163 
164 
165 
166 
167 
168 
169 
170   #pragma omp target parallel for if(target: n>20) schedule(static, a)
171   for (unsigned char it = 'z'; it >= 'a'; it+=-1) {
172     a += 1;
173     b[2] += 1.0;
174     bn[3] += 1.0;
175     c[1][2] += 1.0;
176     cn[1][3] += 1.0;
177     d.X += 1;
178     d.Y += 1;
179   }
180 
181   return a;
182 }
183 
184 // Check that the offloading functions are emitted and that the arguments are
185 // correct and loaded correctly for the target regions in foo().
186 
187 
188 // Create stack storage and store argument in there.
189 
190 // Create stack storage and store argument in there.
191 
192 
193 // Create stack storage and store argument in there.
194 
195 // Create local storage for each capture.
196 
197 
198 
199 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
200 
201 template<typename tx>
202 tx ftemplate(int n) {
203   tx a = 0;
204   short aa = 0;
205   tx b[10];
206 
207   #pragma omp target parallel for if(target: n>40)
208   for (long long i = -10; i < 10; i += 3) {
209     a += 1;
210     aa += 1;
211     b[2] += 1;
212   }
213 
214   return a;
215 }
216 
217 static
218 int fstatic(int n) {
219   int a = 0;
220   short aa = 0;
221   char aaa = 0;
222   int b[10];
223 
224   #pragma omp target parallel for if(target: n>50)
225   for (unsigned i=100; i<10; i+=10) {
226     a += 1;
227     aa += 1;
228     aaa += 1;
229     b[2] += 1;
230   }
231 
232   return a;
233 }
234 
235 struct S1 {
236   double a;
237 
238   int r1(int n){
239     int b = n+1;
240     short int c[2][n];
241 
242     #pragma omp target parallel for if(target: n>60)
243     for (unsigned long long it = 2000; it >= 600; it -= 400) {
244       this->a = (double)b + 1.5;
245       c[1][1] = ++a;
246     }
247 
248     return c[1][1] + (int)b;
249   }
250 };
251 
252 int bar(int n){
253   int a = 0;
254 
255   a += foo(n);
256 
257   S1 S;
258   a += S.r1(n);
259 
260   a += fstatic(n);
261 
262   a += ftemplate<int>(n);
263 
264   return a;
265 }
266 
267 
268 
269 // We capture 2 VLA sizes in this target region
270 
271 
272 // The names below are not necessarily consistent with the names used for the
273 // addresses above as some are repeated.
274 
275 
276 
277 
278 
279 
280 
281 
282 
283 
284 
285 
286 
287 
288 
289 
290 
291 
292 // Check that the offloading functions are emitted and that the arguments are
293 // correct and loaded correctly for the target regions of the callees of bar().
294 
295 // Create local storage for each capture.
296 // Store captures in the context.
297 
298 
299 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
300 
301 
302 // Create local storage for each capture.
303 // Store captures in the context.
304 
305 
306 
307 
308 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
309 
310 // Create local storage for each capture.
311 // Store captures in the context.
312 
313 
314 
315 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
316 
317 
318 #endif
319 // CHECK1-LABEL: define {{[^@]+}}@_Z7get_valv
320 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
321 // CHECK1-NEXT:  entry:
322 // CHECK1-NEXT:    ret i64 0
323 //
324 //
325 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi
326 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
327 // CHECK1-NEXT:  entry:
328 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
329 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
330 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
331 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
332 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
333 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
334 // CHECK1-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
335 // CHECK1-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
336 // CHECK1-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
337 // CHECK1-NEXT:    [[K:%.*]] = alloca i64, align 8
338 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
339 // CHECK1-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
340 // CHECK1-NEXT:    [[LIN:%.*]] = alloca i32, align 4
341 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
342 // CHECK1-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
343 // CHECK1-NEXT:    [[A_CASTED4:%.*]] = alloca i64, align 8
344 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
345 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
346 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
347 // CHECK1-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
348 // CHECK1-NEXT:    [[A_CASTED6:%.*]] = alloca i64, align 8
349 // CHECK1-NEXT:    [[AA_CASTED8:%.*]] = alloca i64, align 8
350 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
351 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
352 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
353 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
354 // CHECK1-NEXT:    [[A_CASTED15:%.*]] = alloca i64, align 8
355 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
356 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8
357 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8
358 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8
359 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
360 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
361 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
362 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
363 // CHECK1-NEXT:    store i16 0, i16* [[AA]], align 2
364 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
365 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
366 // CHECK1-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
367 // CHECK1-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
368 // CHECK1-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
369 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
370 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
371 // CHECK1-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
372 // CHECK1-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
373 // CHECK1-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
374 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
375 // CHECK1-NEXT:    [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
376 // CHECK1-NEXT:    [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
377 // CHECK1-NEXT:    br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
378 // CHECK1:       omp_offload.failed:
379 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]]
380 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
381 // CHECK1:       omp_offload.cont:
382 // CHECK1-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
383 // CHECK1-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
384 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
385 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
386 // CHECK1-NEXT:    store i32 [[TMP9]], i32* [[CONV]], align 4
387 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8
388 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, i64* [[K]], align 8
389 // CHECK1-NEXT:    store i64 [[TMP11]], i64* [[K_CASTED]], align 8
390 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8
391 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR3]]
392 // CHECK1-NEXT:    store i32 12, i32* [[LIN]], align 4
393 // CHECK1-NEXT:    [[TMP13:%.*]] = load i16, i16* [[AA]], align 2
394 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
395 // CHECK1-NEXT:    store i16 [[TMP13]], i16* [[CONV2]], align 2
396 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8
397 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4
398 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
399 // CHECK1-NEXT:    store i32 [[TMP15]], i32* [[CONV3]], align 4
400 // CHECK1-NEXT:    [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
401 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, i32* [[A]], align 4
402 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32*
403 // CHECK1-NEXT:    store i32 [[TMP17]], i32* [[CONV5]], align 4
404 // CHECK1-NEXT:    [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8
405 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
406 // CHECK1-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
407 // CHECK1-NEXT:    store i64 [[TMP14]], i64* [[TMP20]], align 8
408 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
409 // CHECK1-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
410 // CHECK1-NEXT:    store i64 [[TMP14]], i64* [[TMP22]], align 8
411 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
412 // CHECK1-NEXT:    store i8* null, i8** [[TMP23]], align 8
413 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
414 // CHECK1-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
415 // CHECK1-NEXT:    store i64 [[TMP16]], i64* [[TMP25]], align 8
416 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
417 // CHECK1-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
418 // CHECK1-NEXT:    store i64 [[TMP16]], i64* [[TMP27]], align 8
419 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
420 // CHECK1-NEXT:    store i8* null, i8** [[TMP28]], align 8
421 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
422 // CHECK1-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64*
423 // CHECK1-NEXT:    store i64 [[TMP18]], i64* [[TMP30]], align 8
424 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
425 // CHECK1-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
426 // CHECK1-NEXT:    store i64 [[TMP18]], i64* [[TMP32]], align 8
427 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
428 // CHECK1-NEXT:    store i8* null, i8** [[TMP33]], align 8
429 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
430 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
431 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
432 // CHECK1-NEXT:    [[TMP37:%.*]] = load i16, i16* [[AA]], align 2
433 // CHECK1-NEXT:    store i16 [[TMP37]], i16* [[TMP36]], align 4
434 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
435 // CHECK1-NEXT:    [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4
436 // CHECK1-NEXT:    store i32 [[TMP39]], i32* [[TMP38]], align 4
437 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
438 // CHECK1-NEXT:    [[TMP41:%.*]] = load i32, i32* [[A]], align 4
439 // CHECK1-NEXT:    store i32 [[TMP41]], i32* [[TMP40]], align 4
440 // CHECK1-NEXT:    [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
441 // CHECK1-NEXT:    [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates*
442 // CHECK1-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0
443 // CHECK1-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0
444 // CHECK1-NEXT:    [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8
445 // CHECK1-NEXT:    [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
446 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false)
447 // CHECK1-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1
448 // CHECK1-NEXT:    [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon*
449 // CHECK1-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0
450 // CHECK1-NEXT:    [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8*
451 // CHECK1-NEXT:    [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8*
452 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false)
453 // CHECK1-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1
454 // CHECK1-NEXT:    [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8*
455 // CHECK1-NEXT:    [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8*
456 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false)
457 // CHECK1-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2
458 // CHECK1-NEXT:    [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8*
459 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
460 // CHECK1-NEXT:    [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3
461 // CHECK1-NEXT:    [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
462 // CHECK1-NEXT:    store i16 [[TMP59]], i16* [[TMP58]], align 8
463 // CHECK1-NEXT:    [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]])
464 // CHECK1-NEXT:    [[TMP61:%.*]] = load i32, i32* [[A]], align 4
465 // CHECK1-NEXT:    [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32*
466 // CHECK1-NEXT:    store i32 [[TMP61]], i32* [[CONV7]], align 4
467 // CHECK1-NEXT:    [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8
468 // CHECK1-NEXT:    [[TMP63:%.*]] = load i16, i16* [[AA]], align 2
469 // CHECK1-NEXT:    [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16*
470 // CHECK1-NEXT:    store i16 [[TMP63]], i16* [[CONV9]], align 2
471 // CHECK1-NEXT:    [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8
472 // CHECK1-NEXT:    [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4
473 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10
474 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
475 // CHECK1:       omp_if.then:
476 // CHECK1-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
477 // CHECK1-NEXT:    [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64*
478 // CHECK1-NEXT:    store i64 [[TMP62]], i64* [[TMP67]], align 8
479 // CHECK1-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
480 // CHECK1-NEXT:    [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64*
481 // CHECK1-NEXT:    store i64 [[TMP62]], i64* [[TMP69]], align 8
482 // CHECK1-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
483 // CHECK1-NEXT:    store i8* null, i8** [[TMP70]], align 8
484 // CHECK1-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
485 // CHECK1-NEXT:    [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64*
486 // CHECK1-NEXT:    store i64 [[TMP64]], i64* [[TMP72]], align 8
487 // CHECK1-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
488 // CHECK1-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64*
489 // CHECK1-NEXT:    store i64 [[TMP64]], i64* [[TMP74]], align 8
490 // CHECK1-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
491 // CHECK1-NEXT:    store i8* null, i8** [[TMP75]], align 8
492 // CHECK1-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
493 // CHECK1-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
494 // CHECK1-NEXT:    [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
495 // CHECK1-NEXT:    [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0
496 // CHECK1-NEXT:    br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]]
497 // CHECK1:       omp_offload.failed13:
498 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR3]]
499 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT14]]
500 // CHECK1:       omp_offload.cont14:
501 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
502 // CHECK1:       omp_if.else:
503 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR3]]
504 // CHECK1-NEXT:    br label [[OMP_IF_END]]
505 // CHECK1:       omp_if.end:
506 // CHECK1-NEXT:    [[TMP80:%.*]] = load i32, i32* [[A]], align 4
507 // CHECK1-NEXT:    store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4
508 // CHECK1-NEXT:    [[TMP81:%.*]] = load i32, i32* [[A]], align 4
509 // CHECK1-NEXT:    [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32*
510 // CHECK1-NEXT:    store i32 [[TMP81]], i32* [[CONV16]], align 4
511 // CHECK1-NEXT:    [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8
512 // CHECK1-NEXT:    [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
513 // CHECK1-NEXT:    [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
514 // CHECK1-NEXT:    store i32 [[TMP83]], i32* [[CONV17]], align 4
515 // CHECK1-NEXT:    [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
516 // CHECK1-NEXT:    [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4
517 // CHECK1-NEXT:    [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20
518 // CHECK1-NEXT:    br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
519 // CHECK1:       omp_if.then19:
520 // CHECK1-NEXT:    [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4
521 // CHECK1-NEXT:    [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]]
522 // CHECK1-NEXT:    [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8
523 // CHECK1-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
524 // CHECK1-NEXT:    [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64*
525 // CHECK1-NEXT:    store i64 [[TMP82]], i64* [[TMP90]], align 8
526 // CHECK1-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
527 // CHECK1-NEXT:    [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i64*
528 // CHECK1-NEXT:    store i64 [[TMP82]], i64* [[TMP92]], align 8
529 // CHECK1-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
530 // CHECK1-NEXT:    store i64 4, i64* [[TMP93]], align 8
531 // CHECK1-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
532 // CHECK1-NEXT:    store i8* null, i8** [[TMP94]], align 8
533 // CHECK1-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
534 // CHECK1-NEXT:    [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]**
535 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8
536 // CHECK1-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
537 // CHECK1-NEXT:    [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]**
538 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8
539 // CHECK1-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
540 // CHECK1-NEXT:    store i64 40, i64* [[TMP99]], align 8
541 // CHECK1-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
542 // CHECK1-NEXT:    store i8* null, i8** [[TMP100]], align 8
543 // CHECK1-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
544 // CHECK1-NEXT:    [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i64*
545 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP102]], align 8
546 // CHECK1-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
547 // CHECK1-NEXT:    [[TMP104:%.*]] = bitcast i8** [[TMP103]] to i64*
548 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP104]], align 8
549 // CHECK1-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
550 // CHECK1-NEXT:    store i64 8, i64* [[TMP105]], align 8
551 // CHECK1-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
552 // CHECK1-NEXT:    store i8* null, i8** [[TMP106]], align 8
553 // CHECK1-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
554 // CHECK1-NEXT:    [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float**
555 // CHECK1-NEXT:    store float* [[VLA]], float** [[TMP108]], align 8
556 // CHECK1-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
557 // CHECK1-NEXT:    [[TMP110:%.*]] = bitcast i8** [[TMP109]] to float**
558 // CHECK1-NEXT:    store float* [[VLA]], float** [[TMP110]], align 8
559 // CHECK1-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
560 // CHECK1-NEXT:    store i64 [[TMP86]], i64* [[TMP111]], align 8
561 // CHECK1-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3
562 // CHECK1-NEXT:    store i8* null, i8** [[TMP112]], align 8
563 // CHECK1-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
564 // CHECK1-NEXT:    [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]**
565 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8
566 // CHECK1-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
567 // CHECK1-NEXT:    [[TMP116:%.*]] = bitcast i8** [[TMP115]] to [5 x [10 x double]]**
568 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP116]], align 8
569 // CHECK1-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
570 // CHECK1-NEXT:    store i64 400, i64* [[TMP117]], align 8
571 // CHECK1-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4
572 // CHECK1-NEXT:    store i8* null, i8** [[TMP118]], align 8
573 // CHECK1-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
574 // CHECK1-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i64*
575 // CHECK1-NEXT:    store i64 5, i64* [[TMP120]], align 8
576 // CHECK1-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
577 // CHECK1-NEXT:    [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64*
578 // CHECK1-NEXT:    store i64 5, i64* [[TMP122]], align 8
579 // CHECK1-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
580 // CHECK1-NEXT:    store i64 8, i64* [[TMP123]], align 8
581 // CHECK1-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5
582 // CHECK1-NEXT:    store i8* null, i8** [[TMP124]], align 8
583 // CHECK1-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
584 // CHECK1-NEXT:    [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64*
585 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP126]], align 8
586 // CHECK1-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
587 // CHECK1-NEXT:    [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64*
588 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP128]], align 8
589 // CHECK1-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
590 // CHECK1-NEXT:    store i64 8, i64* [[TMP129]], align 8
591 // CHECK1-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6
592 // CHECK1-NEXT:    store i8* null, i8** [[TMP130]], align 8
593 // CHECK1-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
594 // CHECK1-NEXT:    [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double**
595 // CHECK1-NEXT:    store double* [[VLA1]], double** [[TMP132]], align 8
596 // CHECK1-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
597 // CHECK1-NEXT:    [[TMP134:%.*]] = bitcast i8** [[TMP133]] to double**
598 // CHECK1-NEXT:    store double* [[VLA1]], double** [[TMP134]], align 8
599 // CHECK1-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
600 // CHECK1-NEXT:    store i64 [[TMP88]], i64* [[TMP135]], align 8
601 // CHECK1-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7
602 // CHECK1-NEXT:    store i8* null, i8** [[TMP136]], align 8
603 // CHECK1-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
604 // CHECK1-NEXT:    [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT**
605 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 8
606 // CHECK1-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
607 // CHECK1-NEXT:    [[TMP140:%.*]] = bitcast i8** [[TMP139]] to %struct.TT**
608 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP140]], align 8
609 // CHECK1-NEXT:    [[TMP141:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
610 // CHECK1-NEXT:    store i64 16, i64* [[TMP141]], align 8
611 // CHECK1-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8
612 // CHECK1-NEXT:    store i8* null, i8** [[TMP142]], align 8
613 // CHECK1-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9
614 // CHECK1-NEXT:    [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i64*
615 // CHECK1-NEXT:    store i64 [[TMP84]], i64* [[TMP144]], align 8
616 // CHECK1-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9
617 // CHECK1-NEXT:    [[TMP146:%.*]] = bitcast i8** [[TMP145]] to i64*
618 // CHECK1-NEXT:    store i64 [[TMP84]], i64* [[TMP146]], align 8
619 // CHECK1-NEXT:    [[TMP147:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
620 // CHECK1-NEXT:    store i64 4, i64* [[TMP147]], align 8
621 // CHECK1-NEXT:    [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9
622 // CHECK1-NEXT:    store i8* null, i8** [[TMP148]], align 8
623 // CHECK1-NEXT:    [[TMP149:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
624 // CHECK1-NEXT:    [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
625 // CHECK1-NEXT:    [[TMP151:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
626 // CHECK1-NEXT:    [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
627 // CHECK1-NEXT:    [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0
628 // CHECK1-NEXT:    br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
629 // CHECK1:       omp_offload.failed23:
630 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR3]]
631 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT24]]
632 // CHECK1:       omp_offload.cont24:
633 // CHECK1-NEXT:    br label [[OMP_IF_END26:%.*]]
634 // CHECK1:       omp_if.else25:
635 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR3]]
636 // CHECK1-NEXT:    br label [[OMP_IF_END26]]
637 // CHECK1:       omp_if.end26:
638 // CHECK1-NEXT:    [[TMP154:%.*]] = load i32, i32* [[A]], align 4
639 // CHECK1-NEXT:    [[TMP155:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
640 // CHECK1-NEXT:    call void @llvm.stackrestore(i8* [[TMP155]])
641 // CHECK1-NEXT:    ret i32 [[TMP154]]
642 //
643 //
644 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
645 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] {
646 // CHECK1-NEXT:  entry:
647 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
648 // CHECK1-NEXT:    ret void
649 //
650 //
651 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
652 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
653 // CHECK1-NEXT:  entry:
654 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
655 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
656 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
657 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
658 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
659 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
660 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
661 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
662 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
663 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
664 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
665 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
666 // CHECK1-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
667 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
668 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
669 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
670 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
671 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
672 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
673 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
674 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
675 // CHECK1:       cond.true:
676 // CHECK1-NEXT:    br label [[COND_END:%.*]]
677 // CHECK1:       cond.false:
678 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
679 // CHECK1-NEXT:    br label [[COND_END]]
680 // CHECK1:       cond.end:
681 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
682 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
683 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
684 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
685 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
686 // CHECK1:       omp.inner.for.cond:
687 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
688 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
689 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
690 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
691 // CHECK1:       omp.inner.for.body:
692 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
693 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
694 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
695 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
696 // CHECK1-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
697 // CHECK1-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
698 // CHECK1-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
699 // CHECK1:       .cancel.exit:
700 // CHECK1-NEXT:    br label [[CANCEL_EXIT:%.*]]
701 // CHECK1:       .cancel.continue:
702 // CHECK1-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
703 // CHECK1-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
704 // CHECK1-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
705 // CHECK1:       .cancel.exit2:
706 // CHECK1-NEXT:    br label [[CANCEL_EXIT]]
707 // CHECK1:       .cancel.continue3:
708 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
709 // CHECK1:       omp.body.continue:
710 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
711 // CHECK1:       omp.inner.for.inc:
712 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
713 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
714 // CHECK1-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
715 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
716 // CHECK1:       omp.inner.for.end:
717 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
718 // CHECK1:       omp.loop.exit:
719 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
720 // CHECK1-NEXT:    br label [[CANCEL_CONT:%.*]]
721 // CHECK1:       cancel.cont:
722 // CHECK1-NEXT:    ret void
723 // CHECK1:       cancel.exit:
724 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
725 // CHECK1-NEXT:    br label [[CANCEL_CONT]]
726 //
727 //
728 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
729 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR2]] {
730 // CHECK1-NEXT:  entry:
731 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
732 // CHECK1-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
733 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
734 // CHECK1-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
735 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
736 // CHECK1-NEXT:    store i64 [[K]], i64* [[K_ADDR]], align 8
737 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
738 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
739 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
740 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
741 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
742 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
743 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[K_CASTED]], align 8
744 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
745 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
746 // CHECK1-NEXT:    ret void
747 //
748 //
749 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
750 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR2]] {
751 // CHECK1-NEXT:  entry:
752 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
753 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
754 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
755 // CHECK1-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
756 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
757 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
758 // CHECK1-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
759 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
760 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
761 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
762 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
763 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
764 // CHECK1-NEXT:    [[K1:%.*]] = alloca i64, align 8
765 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
766 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
767 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
768 // CHECK1-NEXT:    store i64 [[K]], i64* [[K_ADDR]], align 8
769 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
770 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8
771 // CHECK1-NEXT:    store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8
772 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
773 // CHECK1-NEXT:    store i32 8, i32* [[DOTOMP_UB]], align 4
774 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
775 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
776 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
777 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
778 // CHECK1-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]])
779 // CHECK1-NEXT:    call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1)
780 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
781 // CHECK1:       omp.dispatch.cond:
782 // CHECK1-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
783 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
784 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
785 // CHECK1:       omp.dispatch.body:
786 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
787 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
788 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
789 // CHECK1:       omp.inner.for.cond:
790 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
791 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
792 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
793 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
794 // CHECK1:       omp.inner.for.body:
795 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
796 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
797 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
798 // CHECK1-NEXT:    store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !11
799 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !11
800 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
801 // CHECK1-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
802 // CHECK1-NEXT:    [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
803 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
804 // CHECK1-NEXT:    store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !11
805 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11
806 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
807 // CHECK1-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !11
808 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
809 // CHECK1:       omp.body.continue:
810 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
811 // CHECK1:       omp.inner.for.inc:
812 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
813 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
814 // CHECK1-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
815 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
816 // CHECK1:       omp.inner.for.end:
817 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
818 // CHECK1:       omp.dispatch.inc:
819 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
820 // CHECK1:       omp.dispatch.end:
821 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
822 // CHECK1-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
823 // CHECK1-NEXT:    br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
824 // CHECK1:       .omp.linear.pu:
825 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
826 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i64 [[TMP14]], 27
827 // CHECK1-NEXT:    store i64 [[ADD6]], i64* [[K_ADDR]], align 8
828 // CHECK1-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
829 // CHECK1:       .omp.linear.pu.done:
830 // CHECK1-NEXT:    ret void
831 //
832 //
833 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
834 // CHECK1-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
835 // CHECK1-NEXT:  entry:
836 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
837 // CHECK1-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
838 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
839 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
840 // CHECK1-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
841 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
842 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
843 // CHECK1-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
844 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
845 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
846 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
847 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
848 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
849 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
850 // CHECK1-NEXT:    store i16 [[TMP0]], i16* [[CONV3]], align 2
851 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
852 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
853 // CHECK1-NEXT:    [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
854 // CHECK1-NEXT:    store i32 [[TMP2]], i32* [[CONV4]], align 4
855 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
856 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
857 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
858 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[CONV5]], align 4
859 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
860 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
861 // CHECK1-NEXT:    ret void
862 //
863 //
864 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
865 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
866 // CHECK1-NEXT:  entry:
867 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
868 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
869 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
870 // CHECK1-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
871 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
872 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
873 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i64, align 8
874 // CHECK1-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
875 // CHECK1-NEXT:    [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
876 // CHECK1-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
877 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
878 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
879 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
880 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
881 // CHECK1-NEXT:    [[IT:%.*]] = alloca i64, align 8
882 // CHECK1-NEXT:    [[LIN4:%.*]] = alloca i32, align 4
883 // CHECK1-NEXT:    [[A5:%.*]] = alloca i32, align 4
884 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
885 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
886 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
887 // CHECK1-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
888 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
889 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
890 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
891 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
892 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
893 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
894 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
895 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
896 // CHECK1-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
897 // CHECK1-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
898 // CHECK1-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
899 // CHECK1-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
900 // CHECK1-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
901 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
902 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
903 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
904 // CHECK1-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
905 // CHECK1-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
906 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
907 // CHECK1-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
908 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
909 // CHECK1:       cond.true:
910 // CHECK1-NEXT:    br label [[COND_END:%.*]]
911 // CHECK1:       cond.false:
912 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
913 // CHECK1-NEXT:    br label [[COND_END]]
914 // CHECK1:       cond.end:
915 // CHECK1-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
916 // CHECK1-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
917 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
918 // CHECK1-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
919 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
920 // CHECK1:       omp.inner.for.cond:
921 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
922 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
923 // CHECK1-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
924 // CHECK1-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
925 // CHECK1:       omp.inner.for.body:
926 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
927 // CHECK1-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
928 // CHECK1-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
929 // CHECK1-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
930 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
931 // CHECK1-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
932 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
933 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
934 // CHECK1-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
935 // CHECK1-NEXT:    [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
936 // CHECK1-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
937 // CHECK1-NEXT:    store i32 [[CONV9]], i32* [[LIN4]], align 4
938 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
939 // CHECK1-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
940 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
941 // CHECK1-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
942 // CHECK1-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
943 // CHECK1-NEXT:    [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
944 // CHECK1-NEXT:    [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
945 // CHECK1-NEXT:    store i32 [[CONV13]], i32* [[A5]], align 4
946 // CHECK1-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8
947 // CHECK1-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
948 // CHECK1-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
949 // CHECK1-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
950 // CHECK1-NEXT:    store i16 [[CONV16]], i16* [[CONV]], align 8
951 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
952 // CHECK1:       omp.body.continue:
953 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
954 // CHECK1:       omp.inner.for.inc:
955 // CHECK1-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
956 // CHECK1-NEXT:    [[ADD17:%.*]] = add i64 [[TMP17]], 1
957 // CHECK1-NEXT:    store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
958 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
959 // CHECK1:       omp.inner.for.end:
960 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
961 // CHECK1:       omp.loop.exit:
962 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
963 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
964 // CHECK1-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
965 // CHECK1-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
966 // CHECK1:       .omp.linear.pu:
967 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
968 // CHECK1-NEXT:    [[CONV18:%.*]] = sext i32 [[TMP20]] to i64
969 // CHECK1-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
970 // CHECK1-NEXT:    [[MUL19:%.*]] = mul i64 4, [[TMP21]]
971 // CHECK1-NEXT:    [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
972 // CHECK1-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
973 // CHECK1-NEXT:    store i32 [[CONV21]], i32* [[CONV1]], align 8
974 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
975 // CHECK1-NEXT:    [[CONV22:%.*]] = sext i32 [[TMP22]] to i64
976 // CHECK1-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
977 // CHECK1-NEXT:    [[MUL23:%.*]] = mul i64 4, [[TMP23]]
978 // CHECK1-NEXT:    [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
979 // CHECK1-NEXT:    [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
980 // CHECK1-NEXT:    store i32 [[CONV25]], i32* [[CONV2]], align 8
981 // CHECK1-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
982 // CHECK1:       .omp.linear.pu.done:
983 // CHECK1-NEXT:    ret void
984 //
985 //
986 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.
987 // CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
988 // CHECK1-NEXT:  entry:
989 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
990 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 8
991 // CHECK1-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
992 // CHECK1-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
993 // CHECK1-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
994 // CHECK1-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
995 // CHECK1-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
996 // CHECK1-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
997 // CHECK1-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
998 // CHECK1-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
999 // CHECK1-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
1000 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
1001 // CHECK1-NEXT:    [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
1002 // CHECK1-NEXT:    store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
1003 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
1004 // CHECK1-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
1005 // CHECK1-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
1006 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
1007 // CHECK1-NEXT:    [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
1008 // CHECK1-NEXT:    store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
1009 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
1010 // CHECK1-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
1011 // CHECK1-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 8
1012 // CHECK1-NEXT:    ret void
1013 //
1014 //
1015 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.
1016 // CHECK1-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
1017 // CHECK1-NEXT:  entry:
1018 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
1019 // CHECK1-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
1020 // CHECK1-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
1021 // CHECK1-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
1022 // CHECK1-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
1023 // CHECK1-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
1024 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
1025 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
1026 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
1027 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
1028 // CHECK1-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
1029 // CHECK1-NEXT:    [[LIN_CASTED_I:%.*]] = alloca i64, align 8
1030 // CHECK1-NEXT:    [[A_CASTED_I:%.*]] = alloca i64, align 8
1031 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
1032 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
1033 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
1034 // CHECK1-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
1035 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
1036 // CHECK1-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
1037 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
1038 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
1039 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
1040 // CHECK1-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
1041 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
1042 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
1043 // CHECK1-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
1044 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
1045 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])
1046 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
1047 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
1048 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
1049 // CHECK1-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23
1050 // CHECK1-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23
1051 // CHECK1-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23
1052 // CHECK1-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23
1053 // CHECK1-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23
1054 // CHECK1-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23
1055 // CHECK1-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23
1056 // CHECK1-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23
1057 // CHECK1-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23
1058 // CHECK1-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
1059 // CHECK1-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
1060 // CHECK1-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23
1061 // CHECK1-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23
1062 // CHECK1-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23
1063 // CHECK1-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23
1064 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
1065 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
1066 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
1067 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
1068 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
1069 // CHECK1-NEXT:    [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) #[[ATTR3]]
1070 // CHECK1-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
1071 // CHECK1-NEXT:    br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
1072 // CHECK1:       omp_offload.failed.i:
1073 // CHECK1-NEXT:    [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2
1074 // CHECK1-NEXT:    [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
1075 // CHECK1-NEXT:    store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !23
1076 // CHECK1-NEXT:    [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !23
1077 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4
1078 // CHECK1-NEXT:    [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32*
1079 // CHECK1-NEXT:    store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !23
1080 // CHECK1-NEXT:    [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !23
1081 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4
1082 // CHECK1-NEXT:    [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32*
1083 // CHECK1-NEXT:    store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !23
1084 // CHECK1-NEXT:    [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !23
1085 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR3]]
1086 // CHECK1-NEXT:    br label [[DOTOMP_OUTLINED__3_EXIT]]
1087 // CHECK1:       .omp_outlined..3.exit:
1088 // CHECK1-NEXT:    ret i32 0
1089 //
1090 //
1091 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
1092 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
1093 // CHECK1-NEXT:  entry:
1094 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1095 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1096 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1097 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1098 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1099 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1100 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1101 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1102 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
1103 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1104 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
1105 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1106 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
1107 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1108 // CHECK1-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
1109 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1110 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
1111 // CHECK1-NEXT:    ret void
1112 //
1113 //
1114 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
1115 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
1116 // CHECK1-NEXT:  entry:
1117 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1118 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1119 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1120 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1121 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1122 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i16, align 2
1123 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1124 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1125 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1126 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1127 // CHECK1-NEXT:    [[IT:%.*]] = alloca i16, align 2
1128 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1129 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1130 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1131 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1132 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1133 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1134 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1135 // CHECK1-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
1136 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1137 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1138 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1139 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1140 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1141 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1142 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
1143 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1144 // CHECK1:       cond.true:
1145 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1146 // CHECK1:       cond.false:
1147 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1148 // CHECK1-NEXT:    br label [[COND_END]]
1149 // CHECK1:       cond.end:
1150 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1151 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1152 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1153 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1154 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1155 // CHECK1:       omp.inner.for.cond:
1156 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1157 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1158 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1159 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1160 // CHECK1:       omp.inner.for.body:
1161 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1162 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
1163 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
1164 // CHECK1-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
1165 // CHECK1-NEXT:    store i16 [[CONV3]], i16* [[IT]], align 2
1166 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
1167 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
1168 // CHECK1-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8
1169 // CHECK1-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
1170 // CHECK1-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
1171 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
1172 // CHECK1-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
1173 // CHECK1-NEXT:    store i16 [[CONV7]], i16* [[CONV1]], align 8
1174 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1175 // CHECK1:       omp.body.continue:
1176 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1177 // CHECK1:       omp.inner.for.inc:
1178 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1179 // CHECK1-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
1180 // CHECK1-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
1181 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1182 // CHECK1:       omp.inner.for.end:
1183 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1184 // CHECK1:       omp.loop.exit:
1185 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
1186 // CHECK1-NEXT:    ret void
1187 //
1188 //
1189 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
1190 // CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
1191 // CHECK1-NEXT:  entry:
1192 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1193 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
1194 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1195 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
1196 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
1197 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1198 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
1199 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
1200 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
1201 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1202 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1203 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
1204 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1205 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
1206 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1207 // CHECK1-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
1208 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
1209 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1210 // CHECK1-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
1211 // CHECK1-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
1212 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
1213 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
1214 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1215 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
1216 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1217 // CHECK1-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
1218 // CHECK1-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
1219 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1220 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
1221 // CHECK1-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
1222 // CHECK1-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
1223 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
1224 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
1225 // CHECK1-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1226 // CHECK1-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
1227 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
1228 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
1229 // CHECK1-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
1230 // CHECK1-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
1231 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
1232 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
1233 // CHECK1-NEXT:    ret void
1234 //
1235 //
1236 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
1237 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
1238 // CHECK1-NEXT:  entry:
1239 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1240 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1241 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1242 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
1243 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1244 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
1245 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
1246 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1247 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
1248 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
1249 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
1250 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1251 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1252 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i8, align 1
1253 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1254 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1255 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1256 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1257 // CHECK1-NEXT:    [[IT:%.*]] = alloca i8, align 1
1258 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1259 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1260 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1261 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
1262 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1263 // CHECK1-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
1264 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
1265 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1266 // CHECK1-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
1267 // CHECK1-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
1268 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
1269 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
1270 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1271 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
1272 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1273 // CHECK1-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
1274 // CHECK1-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
1275 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1276 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
1277 // CHECK1-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
1278 // CHECK1-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
1279 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
1280 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1281 // CHECK1-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
1282 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1283 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1284 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
1285 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1286 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
1287 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
1288 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1289 // CHECK1:       omp.dispatch.cond:
1290 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1291 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
1292 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1293 // CHECK1:       cond.true:
1294 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1295 // CHECK1:       cond.false:
1296 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1297 // CHECK1-NEXT:    br label [[COND_END]]
1298 // CHECK1:       cond.end:
1299 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
1300 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1301 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1302 // CHECK1-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
1303 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1304 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1305 // CHECK1-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
1306 // CHECK1-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1307 // CHECK1:       omp.dispatch.body:
1308 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1309 // CHECK1:       omp.inner.for.cond:
1310 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1311 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1312 // CHECK1-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
1313 // CHECK1-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1314 // CHECK1:       omp.inner.for.body:
1315 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1316 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
1317 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
1318 // CHECK1-NEXT:    [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
1319 // CHECK1-NEXT:    store i8 [[CONV8]], i8* [[IT]], align 1
1320 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
1321 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
1322 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
1323 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
1324 // CHECK1-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
1325 // CHECK1-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
1326 // CHECK1-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
1327 // CHECK1-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
1328 // CHECK1-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
1329 // CHECK1-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
1330 // CHECK1-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
1331 // CHECK1-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
1332 // CHECK1-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
1333 // CHECK1-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
1334 // CHECK1-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
1335 // CHECK1-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
1336 // CHECK1-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
1337 // CHECK1-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
1338 // CHECK1-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
1339 // CHECK1-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
1340 // CHECK1-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
1341 // CHECK1-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
1342 // CHECK1-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
1343 // CHECK1-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
1344 // CHECK1-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
1345 // CHECK1-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
1346 // CHECK1-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
1347 // CHECK1-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8
1348 // CHECK1-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
1349 // CHECK1-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8
1350 // CHECK1-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
1351 // CHECK1-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
1352 // CHECK1-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
1353 // CHECK1-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
1354 // CHECK1-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
1355 // CHECK1-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8
1356 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1357 // CHECK1:       omp.body.continue:
1358 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1359 // CHECK1:       omp.inner.for.inc:
1360 // CHECK1-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1361 // CHECK1-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
1362 // CHECK1-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
1363 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1364 // CHECK1:       omp.inner.for.end:
1365 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1366 // CHECK1:       omp.dispatch.inc:
1367 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1368 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1369 // CHECK1-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
1370 // CHECK1-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
1371 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1372 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1373 // CHECK1-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
1374 // CHECK1-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
1375 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
1376 // CHECK1:       omp.dispatch.end:
1377 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
1378 // CHECK1-NEXT:    ret void
1379 //
1380 //
1381 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari
1382 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
1383 // CHECK1-NEXT:  entry:
1384 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1385 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1386 // CHECK1-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
1387 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1388 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
1389 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1390 // CHECK1-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
1391 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
1392 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
1393 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
1394 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
1395 // CHECK1-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
1396 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
1397 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
1398 // CHECK1-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
1399 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1400 // CHECK1-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
1401 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
1402 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
1403 // CHECK1-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
1404 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
1405 // CHECK1-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
1406 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
1407 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
1408 // CHECK1-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
1409 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
1410 // CHECK1-NEXT:    ret i32 [[TMP8]]
1411 //
1412 //
1413 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
1414 // CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
1415 // CHECK1-NEXT:  entry:
1416 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1417 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1418 // CHECK1-NEXT:    [[B:%.*]] = alloca i32, align 4
1419 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
1420 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1421 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1422 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
1423 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
1424 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
1425 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
1426 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1427 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1428 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1429 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1430 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1431 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
1432 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
1433 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
1434 // CHECK1-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
1435 // CHECK1-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
1436 // CHECK1-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
1437 // CHECK1-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
1438 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
1439 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
1440 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
1441 // CHECK1-NEXT:    store i32 [[TMP5]], i32* [[CONV]], align 4
1442 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
1443 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
1444 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
1445 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1446 // CHECK1:       omp_if.then:
1447 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
1448 // CHECK1-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
1449 // CHECK1-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
1450 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1451 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
1452 // CHECK1-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
1453 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1454 // CHECK1-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
1455 // CHECK1-NEXT:    store double* [[A]], double** [[TMP13]], align 8
1456 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1457 // CHECK1-NEXT:    store i64 8, i64* [[TMP14]], align 8
1458 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1459 // CHECK1-NEXT:    store i8* null, i8** [[TMP15]], align 8
1460 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1461 // CHECK1-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
1462 // CHECK1-NEXT:    store i64 [[TMP6]], i64* [[TMP17]], align 8
1463 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1464 // CHECK1-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
1465 // CHECK1-NEXT:    store i64 [[TMP6]], i64* [[TMP19]], align 8
1466 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
1467 // CHECK1-NEXT:    store i64 4, i64* [[TMP20]], align 8
1468 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1469 // CHECK1-NEXT:    store i8* null, i8** [[TMP21]], align 8
1470 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1471 // CHECK1-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
1472 // CHECK1-NEXT:    store i64 2, i64* [[TMP23]], align 8
1473 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1474 // CHECK1-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
1475 // CHECK1-NEXT:    store i64 2, i64* [[TMP25]], align 8
1476 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
1477 // CHECK1-NEXT:    store i64 8, i64* [[TMP26]], align 8
1478 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1479 // CHECK1-NEXT:    store i8* null, i8** [[TMP27]], align 8
1480 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1481 // CHECK1-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
1482 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP29]], align 8
1483 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1484 // CHECK1-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
1485 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP31]], align 8
1486 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
1487 // CHECK1-NEXT:    store i64 8, i64* [[TMP32]], align 8
1488 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1489 // CHECK1-NEXT:    store i8* null, i8** [[TMP33]], align 8
1490 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1491 // CHECK1-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
1492 // CHECK1-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 8
1493 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1494 // CHECK1-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
1495 // CHECK1-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 8
1496 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1497 // CHECK1-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 8
1498 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1499 // CHECK1-NEXT:    store i8* null, i8** [[TMP39]], align 8
1500 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1501 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1502 // CHECK1-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1503 // CHECK1-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
1504 // CHECK1-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
1505 // CHECK1-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1506 // CHECK1:       omp_offload.failed:
1507 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
1508 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1509 // CHECK1:       omp_offload.cont:
1510 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1511 // CHECK1:       omp_if.else:
1512 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
1513 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1514 // CHECK1:       omp_if.end:
1515 // CHECK1-NEXT:    [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
1516 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
1517 // CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
1518 // CHECK1-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
1519 // CHECK1-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
1520 // CHECK1-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
1521 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
1522 // CHECK1-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
1523 // CHECK1-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
1524 // CHECK1-NEXT:    ret i32 [[ADD4]]
1525 //
1526 //
1527 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
1528 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
1529 // CHECK1-NEXT:  entry:
1530 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1531 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1532 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1533 // CHECK1-NEXT:    [[AAA:%.*]] = alloca i8, align 1
1534 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1535 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1536 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1537 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1538 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
1539 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
1540 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
1541 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1542 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
1543 // CHECK1-NEXT:    store i16 0, i16* [[AA]], align 2
1544 // CHECK1-NEXT:    store i8 0, i8* [[AAA]], align 1
1545 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
1546 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1547 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
1548 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1549 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
1550 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1551 // CHECK1-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
1552 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1553 // CHECK1-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
1554 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
1555 // CHECK1-NEXT:    store i8 [[TMP4]], i8* [[CONV2]], align 1
1556 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
1557 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
1558 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
1559 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1560 // CHECK1:       omp_if.then:
1561 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1562 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
1563 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
1564 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1565 // CHECK1-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
1566 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
1567 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1568 // CHECK1-NEXT:    store i8* null, i8** [[TMP11]], align 8
1569 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1570 // CHECK1-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1571 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
1572 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1573 // CHECK1-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
1574 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
1575 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1576 // CHECK1-NEXT:    store i8* null, i8** [[TMP16]], align 8
1577 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1578 // CHECK1-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
1579 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP18]], align 8
1580 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1581 // CHECK1-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
1582 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
1583 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1584 // CHECK1-NEXT:    store i8* null, i8** [[TMP21]], align 8
1585 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1586 // CHECK1-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
1587 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
1588 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1589 // CHECK1-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
1590 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
1591 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1592 // CHECK1-NEXT:    store i8* null, i8** [[TMP26]], align 8
1593 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1594 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1595 // CHECK1-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
1596 // CHECK1-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
1597 // CHECK1-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1598 // CHECK1:       omp_offload.failed:
1599 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
1600 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1601 // CHECK1:       omp_offload.cont:
1602 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1603 // CHECK1:       omp_if.else:
1604 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
1605 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1606 // CHECK1:       omp_if.end:
1607 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
1608 // CHECK1-NEXT:    ret i32 [[TMP31]]
1609 //
1610 //
1611 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
1612 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
1613 // CHECK1-NEXT:  entry:
1614 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1615 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1616 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1617 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1618 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1619 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1620 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
1621 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
1622 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
1623 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1624 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
1625 // CHECK1-NEXT:    store i16 0, i16* [[AA]], align 2
1626 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
1627 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1628 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
1629 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1630 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
1631 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1632 // CHECK1-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
1633 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1634 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1635 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
1636 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1637 // CHECK1:       omp_if.then:
1638 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1639 // CHECK1-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
1640 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
1641 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1642 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
1643 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
1644 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1645 // CHECK1-NEXT:    store i8* null, i8** [[TMP9]], align 8
1646 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1647 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
1648 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
1649 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1650 // CHECK1-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1651 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
1652 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1653 // CHECK1-NEXT:    store i8* null, i8** [[TMP14]], align 8
1654 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1655 // CHECK1-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
1656 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
1657 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1658 // CHECK1-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
1659 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
1660 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1661 // CHECK1-NEXT:    store i8* null, i8** [[TMP19]], align 8
1662 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1663 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1664 // CHECK1-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
1665 // CHECK1-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
1666 // CHECK1-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1667 // CHECK1:       omp_offload.failed:
1668 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
1669 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1670 // CHECK1:       omp_offload.cont:
1671 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1672 // CHECK1:       omp_if.else:
1673 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
1674 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1675 // CHECK1:       omp_if.end:
1676 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
1677 // CHECK1-NEXT:    ret i32 [[TMP24]]
1678 //
1679 //
1680 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
1681 // CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1682 // CHECK1-NEXT:  entry:
1683 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1684 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1685 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1686 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1687 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
1688 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1689 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1690 // CHECK1-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
1691 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1692 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1693 // CHECK1-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
1694 // CHECK1-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1695 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1696 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1697 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1698 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
1699 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
1700 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
1701 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
1702 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
1703 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
1704 // CHECK1-NEXT:    ret void
1705 //
1706 //
1707 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9
1708 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1709 // CHECK1-NEXT:  entry:
1710 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1711 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1712 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1713 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1714 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1715 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1716 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
1717 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
1718 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i64, align 8
1719 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
1720 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
1721 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1722 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1723 // CHECK1-NEXT:    [[IT:%.*]] = alloca i64, align 8
1724 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1725 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1726 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1727 // CHECK1-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
1728 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1729 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1730 // CHECK1-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
1731 // CHECK1-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1732 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1733 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1734 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1735 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
1736 // CHECK1-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
1737 // CHECK1-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
1738 // CHECK1-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
1739 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1740 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1741 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
1742 // CHECK1-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
1743 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1744 // CHECK1-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
1745 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1746 // CHECK1:       cond.true:
1747 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1748 // CHECK1:       cond.false:
1749 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1750 // CHECK1-NEXT:    br label [[COND_END]]
1751 // CHECK1:       cond.end:
1752 // CHECK1-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1753 // CHECK1-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
1754 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
1755 // CHECK1-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
1756 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1757 // CHECK1:       omp.inner.for.cond:
1758 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1759 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1760 // CHECK1-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
1761 // CHECK1-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1762 // CHECK1:       omp.inner.for.body:
1763 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1764 // CHECK1-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
1765 // CHECK1-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
1766 // CHECK1-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
1767 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
1768 // CHECK1-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
1769 // CHECK1-NEXT:    [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
1770 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
1771 // CHECK1-NEXT:    store double [[ADD]], double* [[A]], align 8
1772 // CHECK1-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
1773 // CHECK1-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 8
1774 // CHECK1-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
1775 // CHECK1-NEXT:    store double [[INC]], double* [[A5]], align 8
1776 // CHECK1-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
1777 // CHECK1-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
1778 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
1779 // CHECK1-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
1780 // CHECK1-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
1781 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1782 // CHECK1:       omp.body.continue:
1783 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1784 // CHECK1:       omp.inner.for.inc:
1785 // CHECK1-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1786 // CHECK1-NEXT:    [[ADD8:%.*]] = add i64 [[TMP15]], 1
1787 // CHECK1-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
1788 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1789 // CHECK1:       omp.inner.for.end:
1790 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1791 // CHECK1:       omp.loop.exit:
1792 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
1793 // CHECK1-NEXT:    ret void
1794 //
1795 //
1796 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
1797 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1798 // CHECK1-NEXT:  entry:
1799 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1800 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1801 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1802 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1803 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1804 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1805 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1806 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1807 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1808 // CHECK1-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
1809 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1810 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1811 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1812 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
1813 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1814 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
1815 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1816 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
1817 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
1818 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
1819 // CHECK1-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1820 // CHECK1-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
1821 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1822 // CHECK1-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
1823 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
1824 // CHECK1-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
1825 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
1826 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
1827 // CHECK1-NEXT:    ret void
1828 //
1829 //
1830 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
1831 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1832 // CHECK1-NEXT:  entry:
1833 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1834 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1835 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1836 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1837 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1838 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1839 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1840 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1841 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1842 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1843 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1844 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1845 // CHECK1-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
1846 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1847 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1848 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1849 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
1850 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1851 // CHECK1-NEXT:    ret void
1852 //
1853 //
1854 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
1855 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1856 // CHECK1-NEXT:  entry:
1857 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1858 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1859 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1860 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1861 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1862 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1863 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1864 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1865 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1866 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1867 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1868 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
1869 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1870 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
1871 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
1872 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
1873 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1874 // CHECK1-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
1875 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1876 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
1877 // CHECK1-NEXT:    ret void
1878 //
1879 //
1880 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14
1881 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1882 // CHECK1-NEXT:  entry:
1883 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1884 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1885 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1886 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1887 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1888 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
1889 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i64, align 8
1890 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
1891 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
1892 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1893 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1894 // CHECK1-NEXT:    [[I:%.*]] = alloca i64, align 8
1895 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1896 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1897 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1898 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1899 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1900 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1901 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1902 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1903 // CHECK1-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
1904 // CHECK1-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
1905 // CHECK1-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
1906 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1907 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1908 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
1909 // CHECK1-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
1910 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1911 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
1912 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1913 // CHECK1:       cond.true:
1914 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1915 // CHECK1:       cond.false:
1916 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1917 // CHECK1-NEXT:    br label [[COND_END]]
1918 // CHECK1:       cond.end:
1919 // CHECK1-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1920 // CHECK1-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
1921 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
1922 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
1923 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1924 // CHECK1:       omp.inner.for.cond:
1925 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1926 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1927 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
1928 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1929 // CHECK1:       omp.inner.for.body:
1930 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1931 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
1932 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
1933 // CHECK1-NEXT:    store i64 [[ADD]], i64* [[I]], align 8
1934 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
1935 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
1936 // CHECK1-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
1937 // CHECK1-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
1938 // CHECK1-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
1939 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
1940 // CHECK1-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
1941 // CHECK1-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
1942 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
1943 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
1944 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
1945 // CHECK1-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
1946 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1947 // CHECK1:       omp.body.continue:
1948 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1949 // CHECK1:       omp.inner.for.inc:
1950 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1951 // CHECK1-NEXT:    [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
1952 // CHECK1-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
1953 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1954 // CHECK1:       omp.inner.for.end:
1955 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1956 // CHECK1:       omp.loop.exit:
1957 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
1958 // CHECK1-NEXT:    ret void
1959 //
1960 //
1961 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1962 // CHECK1-SAME: () #[[ATTR5]] {
1963 // CHECK1-NEXT:  entry:
1964 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
1965 // CHECK1-NEXT:    ret void
1966 //
1967 //
1968 // CHECK2-LABEL: define {{[^@]+}}@_Z7get_valv
1969 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
1970 // CHECK2-NEXT:  entry:
1971 // CHECK2-NEXT:    ret i64 0
1972 //
1973 //
1974 // CHECK2-LABEL: define {{[^@]+}}@_Z3fooi
1975 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
1976 // CHECK2-NEXT:  entry:
1977 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1978 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
1979 // CHECK2-NEXT:    [[AA:%.*]] = alloca i16, align 2
1980 // CHECK2-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
1981 // CHECK2-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
1982 // CHECK2-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1983 // CHECK2-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
1984 // CHECK2-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
1985 // CHECK2-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
1986 // CHECK2-NEXT:    [[K:%.*]] = alloca i64, align 8
1987 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1988 // CHECK2-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
1989 // CHECK2-NEXT:    [[LIN:%.*]] = alloca i32, align 4
1990 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1991 // CHECK2-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
1992 // CHECK2-NEXT:    [[A_CASTED4:%.*]] = alloca i64, align 8
1993 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
1994 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
1995 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
1996 // CHECK2-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
1997 // CHECK2-NEXT:    [[A_CASTED6:%.*]] = alloca i64, align 8
1998 // CHECK2-NEXT:    [[AA_CASTED8:%.*]] = alloca i64, align 8
1999 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
2000 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
2001 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
2002 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2003 // CHECK2-NEXT:    [[A_CASTED15:%.*]] = alloca i64, align 8
2004 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
2005 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8
2006 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8
2007 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8
2008 // CHECK2-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
2009 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
2010 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2011 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
2012 // CHECK2-NEXT:    store i16 0, i16* [[AA]], align 2
2013 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
2014 // CHECK2-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
2015 // CHECK2-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
2016 // CHECK2-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
2017 // CHECK2-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
2018 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
2019 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
2020 // CHECK2-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
2021 // CHECK2-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
2022 // CHECK2-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
2023 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
2024 // CHECK2-NEXT:    [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
2025 // CHECK2-NEXT:    [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
2026 // CHECK2-NEXT:    br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2027 // CHECK2:       omp_offload.failed:
2028 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]]
2029 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2030 // CHECK2:       omp_offload.cont:
2031 // CHECK2-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
2032 // CHECK2-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
2033 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
2034 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2035 // CHECK2-NEXT:    store i32 [[TMP9]], i32* [[CONV]], align 4
2036 // CHECK2-NEXT:    [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8
2037 // CHECK2-NEXT:    [[TMP11:%.*]] = load i64, i64* [[K]], align 8
2038 // CHECK2-NEXT:    store i64 [[TMP11]], i64* [[K_CASTED]], align 8
2039 // CHECK2-NEXT:    [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8
2040 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR3]]
2041 // CHECK2-NEXT:    store i32 12, i32* [[LIN]], align 4
2042 // CHECK2-NEXT:    [[TMP13:%.*]] = load i16, i16* [[AA]], align 2
2043 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2044 // CHECK2-NEXT:    store i16 [[TMP13]], i16* [[CONV2]], align 2
2045 // CHECK2-NEXT:    [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2046 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4
2047 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
2048 // CHECK2-NEXT:    store i32 [[TMP15]], i32* [[CONV3]], align 4
2049 // CHECK2-NEXT:    [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
2050 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, i32* [[A]], align 4
2051 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32*
2052 // CHECK2-NEXT:    store i32 [[TMP17]], i32* [[CONV5]], align 4
2053 // CHECK2-NEXT:    [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8
2054 // CHECK2-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2055 // CHECK2-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
2056 // CHECK2-NEXT:    store i64 [[TMP14]], i64* [[TMP20]], align 8
2057 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2058 // CHECK2-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
2059 // CHECK2-NEXT:    store i64 [[TMP14]], i64* [[TMP22]], align 8
2060 // CHECK2-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2061 // CHECK2-NEXT:    store i8* null, i8** [[TMP23]], align 8
2062 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2063 // CHECK2-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
2064 // CHECK2-NEXT:    store i64 [[TMP16]], i64* [[TMP25]], align 8
2065 // CHECK2-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2066 // CHECK2-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
2067 // CHECK2-NEXT:    store i64 [[TMP16]], i64* [[TMP27]], align 8
2068 // CHECK2-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2069 // CHECK2-NEXT:    store i8* null, i8** [[TMP28]], align 8
2070 // CHECK2-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2071 // CHECK2-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64*
2072 // CHECK2-NEXT:    store i64 [[TMP18]], i64* [[TMP30]], align 8
2073 // CHECK2-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2074 // CHECK2-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
2075 // CHECK2-NEXT:    store i64 [[TMP18]], i64* [[TMP32]], align 8
2076 // CHECK2-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
2077 // CHECK2-NEXT:    store i8* null, i8** [[TMP33]], align 8
2078 // CHECK2-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2079 // CHECK2-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2080 // CHECK2-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
2081 // CHECK2-NEXT:    [[TMP37:%.*]] = load i16, i16* [[AA]], align 2
2082 // CHECK2-NEXT:    store i16 [[TMP37]], i16* [[TMP36]], align 4
2083 // CHECK2-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
2084 // CHECK2-NEXT:    [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4
2085 // CHECK2-NEXT:    store i32 [[TMP39]], i32* [[TMP38]], align 4
2086 // CHECK2-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
2087 // CHECK2-NEXT:    [[TMP41:%.*]] = load i32, i32* [[A]], align 4
2088 // CHECK2-NEXT:    store i32 [[TMP41]], i32* [[TMP40]], align 4
2089 // CHECK2-NEXT:    [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
2090 // CHECK2-NEXT:    [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates*
2091 // CHECK2-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0
2092 // CHECK2-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0
2093 // CHECK2-NEXT:    [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8
2094 // CHECK2-NEXT:    [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
2095 // CHECK2-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false)
2096 // CHECK2-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1
2097 // CHECK2-NEXT:    [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon*
2098 // CHECK2-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0
2099 // CHECK2-NEXT:    [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8*
2100 // CHECK2-NEXT:    [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8*
2101 // CHECK2-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false)
2102 // CHECK2-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1
2103 // CHECK2-NEXT:    [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8*
2104 // CHECK2-NEXT:    [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8*
2105 // CHECK2-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false)
2106 // CHECK2-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2
2107 // CHECK2-NEXT:    [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8*
2108 // CHECK2-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
2109 // CHECK2-NEXT:    [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3
2110 // CHECK2-NEXT:    [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
2111 // CHECK2-NEXT:    store i16 [[TMP59]], i16* [[TMP58]], align 8
2112 // CHECK2-NEXT:    [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]])
2113 // CHECK2-NEXT:    [[TMP61:%.*]] = load i32, i32* [[A]], align 4
2114 // CHECK2-NEXT:    [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32*
2115 // CHECK2-NEXT:    store i32 [[TMP61]], i32* [[CONV7]], align 4
2116 // CHECK2-NEXT:    [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8
2117 // CHECK2-NEXT:    [[TMP63:%.*]] = load i16, i16* [[AA]], align 2
2118 // CHECK2-NEXT:    [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16*
2119 // CHECK2-NEXT:    store i16 [[TMP63]], i16* [[CONV9]], align 2
2120 // CHECK2-NEXT:    [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8
2121 // CHECK2-NEXT:    [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4
2122 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10
2123 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2124 // CHECK2:       omp_if.then:
2125 // CHECK2-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
2126 // CHECK2-NEXT:    [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64*
2127 // CHECK2-NEXT:    store i64 [[TMP62]], i64* [[TMP67]], align 8
2128 // CHECK2-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
2129 // CHECK2-NEXT:    [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64*
2130 // CHECK2-NEXT:    store i64 [[TMP62]], i64* [[TMP69]], align 8
2131 // CHECK2-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
2132 // CHECK2-NEXT:    store i8* null, i8** [[TMP70]], align 8
2133 // CHECK2-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
2134 // CHECK2-NEXT:    [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64*
2135 // CHECK2-NEXT:    store i64 [[TMP64]], i64* [[TMP72]], align 8
2136 // CHECK2-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
2137 // CHECK2-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64*
2138 // CHECK2-NEXT:    store i64 [[TMP64]], i64* [[TMP74]], align 8
2139 // CHECK2-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
2140 // CHECK2-NEXT:    store i8* null, i8** [[TMP75]], align 8
2141 // CHECK2-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
2142 // CHECK2-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
2143 // CHECK2-NEXT:    [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
2144 // CHECK2-NEXT:    [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0
2145 // CHECK2-NEXT:    br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]]
2146 // CHECK2:       omp_offload.failed13:
2147 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR3]]
2148 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT14]]
2149 // CHECK2:       omp_offload.cont14:
2150 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
2151 // CHECK2:       omp_if.else:
2152 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR3]]
2153 // CHECK2-NEXT:    br label [[OMP_IF_END]]
2154 // CHECK2:       omp_if.end:
2155 // CHECK2-NEXT:    [[TMP80:%.*]] = load i32, i32* [[A]], align 4
2156 // CHECK2-NEXT:    store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4
2157 // CHECK2-NEXT:    [[TMP81:%.*]] = load i32, i32* [[A]], align 4
2158 // CHECK2-NEXT:    [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32*
2159 // CHECK2-NEXT:    store i32 [[TMP81]], i32* [[CONV16]], align 4
2160 // CHECK2-NEXT:    [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8
2161 // CHECK2-NEXT:    [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2162 // CHECK2-NEXT:    [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
2163 // CHECK2-NEXT:    store i32 [[TMP83]], i32* [[CONV17]], align 4
2164 // CHECK2-NEXT:    [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
2165 // CHECK2-NEXT:    [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4
2166 // CHECK2-NEXT:    [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20
2167 // CHECK2-NEXT:    br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
2168 // CHECK2:       omp_if.then19:
2169 // CHECK2-NEXT:    [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4
2170 // CHECK2-NEXT:    [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]]
2171 // CHECK2-NEXT:    [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8
2172 // CHECK2-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
2173 // CHECK2-NEXT:    [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64*
2174 // CHECK2-NEXT:    store i64 [[TMP82]], i64* [[TMP90]], align 8
2175 // CHECK2-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
2176 // CHECK2-NEXT:    [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i64*
2177 // CHECK2-NEXT:    store i64 [[TMP82]], i64* [[TMP92]], align 8
2178 // CHECK2-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2179 // CHECK2-NEXT:    store i64 4, i64* [[TMP93]], align 8
2180 // CHECK2-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
2181 // CHECK2-NEXT:    store i8* null, i8** [[TMP94]], align 8
2182 // CHECK2-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
2183 // CHECK2-NEXT:    [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]**
2184 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8
2185 // CHECK2-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
2186 // CHECK2-NEXT:    [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]**
2187 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8
2188 // CHECK2-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
2189 // CHECK2-NEXT:    store i64 40, i64* [[TMP99]], align 8
2190 // CHECK2-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
2191 // CHECK2-NEXT:    store i8* null, i8** [[TMP100]], align 8
2192 // CHECK2-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
2193 // CHECK2-NEXT:    [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i64*
2194 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP102]], align 8
2195 // CHECK2-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
2196 // CHECK2-NEXT:    [[TMP104:%.*]] = bitcast i8** [[TMP103]] to i64*
2197 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP104]], align 8
2198 // CHECK2-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
2199 // CHECK2-NEXT:    store i64 8, i64* [[TMP105]], align 8
2200 // CHECK2-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
2201 // CHECK2-NEXT:    store i8* null, i8** [[TMP106]], align 8
2202 // CHECK2-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
2203 // CHECK2-NEXT:    [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float**
2204 // CHECK2-NEXT:    store float* [[VLA]], float** [[TMP108]], align 8
2205 // CHECK2-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
2206 // CHECK2-NEXT:    [[TMP110:%.*]] = bitcast i8** [[TMP109]] to float**
2207 // CHECK2-NEXT:    store float* [[VLA]], float** [[TMP110]], align 8
2208 // CHECK2-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
2209 // CHECK2-NEXT:    store i64 [[TMP86]], i64* [[TMP111]], align 8
2210 // CHECK2-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3
2211 // CHECK2-NEXT:    store i8* null, i8** [[TMP112]], align 8
2212 // CHECK2-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
2213 // CHECK2-NEXT:    [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]**
2214 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8
2215 // CHECK2-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
2216 // CHECK2-NEXT:    [[TMP116:%.*]] = bitcast i8** [[TMP115]] to [5 x [10 x double]]**
2217 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP116]], align 8
2218 // CHECK2-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
2219 // CHECK2-NEXT:    store i64 400, i64* [[TMP117]], align 8
2220 // CHECK2-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4
2221 // CHECK2-NEXT:    store i8* null, i8** [[TMP118]], align 8
2222 // CHECK2-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
2223 // CHECK2-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i64*
2224 // CHECK2-NEXT:    store i64 5, i64* [[TMP120]], align 8
2225 // CHECK2-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
2226 // CHECK2-NEXT:    [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64*
2227 // CHECK2-NEXT:    store i64 5, i64* [[TMP122]], align 8
2228 // CHECK2-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
2229 // CHECK2-NEXT:    store i64 8, i64* [[TMP123]], align 8
2230 // CHECK2-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5
2231 // CHECK2-NEXT:    store i8* null, i8** [[TMP124]], align 8
2232 // CHECK2-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
2233 // CHECK2-NEXT:    [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64*
2234 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP126]], align 8
2235 // CHECK2-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
2236 // CHECK2-NEXT:    [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64*
2237 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP128]], align 8
2238 // CHECK2-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
2239 // CHECK2-NEXT:    store i64 8, i64* [[TMP129]], align 8
2240 // CHECK2-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6
2241 // CHECK2-NEXT:    store i8* null, i8** [[TMP130]], align 8
2242 // CHECK2-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
2243 // CHECK2-NEXT:    [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double**
2244 // CHECK2-NEXT:    store double* [[VLA1]], double** [[TMP132]], align 8
2245 // CHECK2-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
2246 // CHECK2-NEXT:    [[TMP134:%.*]] = bitcast i8** [[TMP133]] to double**
2247 // CHECK2-NEXT:    store double* [[VLA1]], double** [[TMP134]], align 8
2248 // CHECK2-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
2249 // CHECK2-NEXT:    store i64 [[TMP88]], i64* [[TMP135]], align 8
2250 // CHECK2-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7
2251 // CHECK2-NEXT:    store i8* null, i8** [[TMP136]], align 8
2252 // CHECK2-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
2253 // CHECK2-NEXT:    [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT**
2254 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 8
2255 // CHECK2-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
2256 // CHECK2-NEXT:    [[TMP140:%.*]] = bitcast i8** [[TMP139]] to %struct.TT**
2257 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP140]], align 8
2258 // CHECK2-NEXT:    [[TMP141:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
2259 // CHECK2-NEXT:    store i64 16, i64* [[TMP141]], align 8
2260 // CHECK2-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8
2261 // CHECK2-NEXT:    store i8* null, i8** [[TMP142]], align 8
2262 // CHECK2-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9
2263 // CHECK2-NEXT:    [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i64*
2264 // CHECK2-NEXT:    store i64 [[TMP84]], i64* [[TMP144]], align 8
2265 // CHECK2-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9
2266 // CHECK2-NEXT:    [[TMP146:%.*]] = bitcast i8** [[TMP145]] to i64*
2267 // CHECK2-NEXT:    store i64 [[TMP84]], i64* [[TMP146]], align 8
2268 // CHECK2-NEXT:    [[TMP147:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
2269 // CHECK2-NEXT:    store i64 4, i64* [[TMP147]], align 8
2270 // CHECK2-NEXT:    [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9
2271 // CHECK2-NEXT:    store i8* null, i8** [[TMP148]], align 8
2272 // CHECK2-NEXT:    [[TMP149:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
2273 // CHECK2-NEXT:    [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
2274 // CHECK2-NEXT:    [[TMP151:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2275 // CHECK2-NEXT:    [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
2276 // CHECK2-NEXT:    [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0
2277 // CHECK2-NEXT:    br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
2278 // CHECK2:       omp_offload.failed23:
2279 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR3]]
2280 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT24]]
2281 // CHECK2:       omp_offload.cont24:
2282 // CHECK2-NEXT:    br label [[OMP_IF_END26:%.*]]
2283 // CHECK2:       omp_if.else25:
2284 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR3]]
2285 // CHECK2-NEXT:    br label [[OMP_IF_END26]]
2286 // CHECK2:       omp_if.end26:
2287 // CHECK2-NEXT:    [[TMP154:%.*]] = load i32, i32* [[A]], align 4
2288 // CHECK2-NEXT:    [[TMP155:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
2289 // CHECK2-NEXT:    call void @llvm.stackrestore(i8* [[TMP155]])
2290 // CHECK2-NEXT:    ret i32 [[TMP154]]
2291 //
2292 //
2293 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
2294 // CHECK2-SAME: () #[[ATTR2:[0-9]+]] {
2295 // CHECK2-NEXT:  entry:
2296 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
2297 // CHECK2-NEXT:    ret void
2298 //
2299 //
2300 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
2301 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
2302 // CHECK2-NEXT:  entry:
2303 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2304 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2305 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2306 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2307 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2308 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2309 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2310 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2311 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2312 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2313 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2314 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2315 // CHECK2-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
2316 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2317 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2318 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2319 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2320 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2321 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2322 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
2323 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2324 // CHECK2:       cond.true:
2325 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2326 // CHECK2:       cond.false:
2327 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2328 // CHECK2-NEXT:    br label [[COND_END]]
2329 // CHECK2:       cond.end:
2330 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2331 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2332 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2333 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2334 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2335 // CHECK2:       omp.inner.for.cond:
2336 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2337 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2338 // CHECK2-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2339 // CHECK2-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2340 // CHECK2:       omp.inner.for.body:
2341 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2342 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
2343 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
2344 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
2345 // CHECK2-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
2346 // CHECK2-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
2347 // CHECK2-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
2348 // CHECK2:       .cancel.exit:
2349 // CHECK2-NEXT:    br label [[CANCEL_EXIT:%.*]]
2350 // CHECK2:       .cancel.continue:
2351 // CHECK2-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
2352 // CHECK2-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
2353 // CHECK2-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
2354 // CHECK2:       .cancel.exit2:
2355 // CHECK2-NEXT:    br label [[CANCEL_EXIT]]
2356 // CHECK2:       .cancel.continue3:
2357 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2358 // CHECK2:       omp.body.continue:
2359 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2360 // CHECK2:       omp.inner.for.inc:
2361 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2362 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
2363 // CHECK2-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
2364 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2365 // CHECK2:       omp.inner.for.end:
2366 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2367 // CHECK2:       omp.loop.exit:
2368 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2369 // CHECK2-NEXT:    br label [[CANCEL_CONT:%.*]]
2370 // CHECK2:       cancel.cont:
2371 // CHECK2-NEXT:    ret void
2372 // CHECK2:       cancel.exit:
2373 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2374 // CHECK2-NEXT:    br label [[CANCEL_CONT]]
2375 //
2376 //
2377 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
2378 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR2]] {
2379 // CHECK2-NEXT:  entry:
2380 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2381 // CHECK2-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
2382 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2383 // CHECK2-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
2384 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2385 // CHECK2-NEXT:    store i64 [[K]], i64* [[K_ADDR]], align 8
2386 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2387 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
2388 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2389 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
2390 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
2391 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
2392 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[K_CASTED]], align 8
2393 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
2394 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
2395 // CHECK2-NEXT:    ret void
2396 //
2397 //
2398 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1
2399 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR2]] {
2400 // CHECK2-NEXT:  entry:
2401 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2402 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2403 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2404 // CHECK2-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
2405 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2406 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2407 // CHECK2-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
2408 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2409 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2410 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2411 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2412 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2413 // CHECK2-NEXT:    [[K1:%.*]] = alloca i64, align 8
2414 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2415 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2416 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2417 // CHECK2-NEXT:    store i64 [[K]], i64* [[K_ADDR]], align 8
2418 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2419 // CHECK2-NEXT:    [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8
2420 // CHECK2-NEXT:    store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8
2421 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2422 // CHECK2-NEXT:    store i32 8, i32* [[DOTOMP_UB]], align 4
2423 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2424 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2425 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2426 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
2427 // CHECK2-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]])
2428 // CHECK2-NEXT:    call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1)
2429 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2430 // CHECK2:       omp.dispatch.cond:
2431 // CHECK2-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
2432 // CHECK2-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
2433 // CHECK2-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2434 // CHECK2:       omp.dispatch.body:
2435 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2436 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2437 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2438 // CHECK2:       omp.inner.for.cond:
2439 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
2440 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
2441 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2442 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2443 // CHECK2:       omp.inner.for.body:
2444 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
2445 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2446 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
2447 // CHECK2-NEXT:    store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !11
2448 // CHECK2-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !11
2449 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
2450 // CHECK2-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
2451 // CHECK2-NEXT:    [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
2452 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
2453 // CHECK2-NEXT:    store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !11
2454 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11
2455 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
2456 // CHECK2-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !11
2457 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2458 // CHECK2:       omp.body.continue:
2459 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2460 // CHECK2:       omp.inner.for.inc:
2461 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
2462 // CHECK2-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
2463 // CHECK2-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
2464 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
2465 // CHECK2:       omp.inner.for.end:
2466 // CHECK2-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2467 // CHECK2:       omp.dispatch.inc:
2468 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND]]
2469 // CHECK2:       omp.dispatch.end:
2470 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2471 // CHECK2-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
2472 // CHECK2-NEXT:    br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
2473 // CHECK2:       .omp.linear.pu:
2474 // CHECK2-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
2475 // CHECK2-NEXT:    [[ADD6:%.*]] = add nsw i64 [[TMP14]], 27
2476 // CHECK2-NEXT:    store i64 [[ADD6]], i64* [[K_ADDR]], align 8
2477 // CHECK2-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
2478 // CHECK2:       .omp.linear.pu.done:
2479 // CHECK2-NEXT:    ret void
2480 //
2481 //
2482 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
2483 // CHECK2-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
2484 // CHECK2-NEXT:  entry:
2485 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2486 // CHECK2-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
2487 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2488 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2489 // CHECK2-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
2490 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2491 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2492 // CHECK2-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
2493 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2494 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2495 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
2496 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2497 // CHECK2-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
2498 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2499 // CHECK2-NEXT:    store i16 [[TMP0]], i16* [[CONV3]], align 2
2500 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2501 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
2502 // CHECK2-NEXT:    [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
2503 // CHECK2-NEXT:    store i32 [[TMP2]], i32* [[CONV4]], align 4
2504 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
2505 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
2506 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2507 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[CONV5]], align 4
2508 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
2509 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
2510 // CHECK2-NEXT:    ret void
2511 //
2512 //
2513 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2
2514 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
2515 // CHECK2-NEXT:  entry:
2516 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2517 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2518 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2519 // CHECK2-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
2520 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2521 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
2522 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i64, align 8
2523 // CHECK2-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
2524 // CHECK2-NEXT:    [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
2525 // CHECK2-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
2526 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
2527 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
2528 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
2529 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2530 // CHECK2-NEXT:    [[IT:%.*]] = alloca i64, align 8
2531 // CHECK2-NEXT:    [[LIN4:%.*]] = alloca i32, align 4
2532 // CHECK2-NEXT:    [[A5:%.*]] = alloca i32, align 4
2533 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2534 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2535 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2536 // CHECK2-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
2537 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2538 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2539 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
2540 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2541 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
2542 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
2543 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
2544 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
2545 // CHECK2-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
2546 // CHECK2-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
2547 // CHECK2-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
2548 // CHECK2-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
2549 // CHECK2-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
2550 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2551 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2552 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2553 // CHECK2-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
2554 // CHECK2-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
2555 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
2556 // CHECK2-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
2557 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2558 // CHECK2:       cond.true:
2559 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2560 // CHECK2:       cond.false:
2561 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
2562 // CHECK2-NEXT:    br label [[COND_END]]
2563 // CHECK2:       cond.end:
2564 // CHECK2-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2565 // CHECK2-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
2566 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
2567 // CHECK2-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
2568 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2569 // CHECK2:       omp.inner.for.cond:
2570 // CHECK2-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2571 // CHECK2-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
2572 // CHECK2-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
2573 // CHECK2-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2574 // CHECK2:       omp.inner.for.body:
2575 // CHECK2-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2576 // CHECK2-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
2577 // CHECK2-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
2578 // CHECK2-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
2579 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
2580 // CHECK2-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
2581 // CHECK2-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2582 // CHECK2-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
2583 // CHECK2-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
2584 // CHECK2-NEXT:    [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
2585 // CHECK2-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
2586 // CHECK2-NEXT:    store i32 [[CONV9]], i32* [[LIN4]], align 4
2587 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
2588 // CHECK2-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
2589 // CHECK2-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2590 // CHECK2-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
2591 // CHECK2-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
2592 // CHECK2-NEXT:    [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
2593 // CHECK2-NEXT:    [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
2594 // CHECK2-NEXT:    store i32 [[CONV13]], i32* [[A5]], align 4
2595 // CHECK2-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8
2596 // CHECK2-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
2597 // CHECK2-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
2598 // CHECK2-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
2599 // CHECK2-NEXT:    store i16 [[CONV16]], i16* [[CONV]], align 8
2600 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2601 // CHECK2:       omp.body.continue:
2602 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2603 // CHECK2:       omp.inner.for.inc:
2604 // CHECK2-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2605 // CHECK2-NEXT:    [[ADD17:%.*]] = add i64 [[TMP17]], 1
2606 // CHECK2-NEXT:    store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
2607 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2608 // CHECK2:       omp.inner.for.end:
2609 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2610 // CHECK2:       omp.loop.exit:
2611 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
2612 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2613 // CHECK2-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
2614 // CHECK2-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
2615 // CHECK2:       .omp.linear.pu:
2616 // CHECK2-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
2617 // CHECK2-NEXT:    [[CONV18:%.*]] = sext i32 [[TMP20]] to i64
2618 // CHECK2-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
2619 // CHECK2-NEXT:    [[MUL19:%.*]] = mul i64 4, [[TMP21]]
2620 // CHECK2-NEXT:    [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
2621 // CHECK2-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
2622 // CHECK2-NEXT:    store i32 [[CONV21]], i32* [[CONV1]], align 8
2623 // CHECK2-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
2624 // CHECK2-NEXT:    [[CONV22:%.*]] = sext i32 [[TMP22]] to i64
2625 // CHECK2-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
2626 // CHECK2-NEXT:    [[MUL23:%.*]] = mul i64 4, [[TMP23]]
2627 // CHECK2-NEXT:    [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
2628 // CHECK2-NEXT:    [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
2629 // CHECK2-NEXT:    store i32 [[CONV25]], i32* [[CONV2]], align 8
2630 // CHECK2-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
2631 // CHECK2:       .omp.linear.pu.done:
2632 // CHECK2-NEXT:    ret void
2633 //
2634 //
2635 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map.
2636 // CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
2637 // CHECK2-NEXT:  entry:
2638 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
2639 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 8
2640 // CHECK2-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
2641 // CHECK2-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
2642 // CHECK2-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
2643 // CHECK2-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
2644 // CHECK2-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
2645 // CHECK2-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
2646 // CHECK2-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
2647 // CHECK2-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
2648 // CHECK2-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
2649 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
2650 // CHECK2-NEXT:    [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
2651 // CHECK2-NEXT:    store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
2652 // CHECK2-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
2653 // CHECK2-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
2654 // CHECK2-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
2655 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
2656 // CHECK2-NEXT:    [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
2657 // CHECK2-NEXT:    store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
2658 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
2659 // CHECK2-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
2660 // CHECK2-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 8
2661 // CHECK2-NEXT:    ret void
2662 //
2663 //
2664 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry.
2665 // CHECK2-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
2666 // CHECK2-NEXT:  entry:
2667 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
2668 // CHECK2-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
2669 // CHECK2-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
2670 // CHECK2-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
2671 // CHECK2-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
2672 // CHECK2-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
2673 // CHECK2-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
2674 // CHECK2-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
2675 // CHECK2-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
2676 // CHECK2-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
2677 // CHECK2-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
2678 // CHECK2-NEXT:    [[LIN_CASTED_I:%.*]] = alloca i64, align 8
2679 // CHECK2-NEXT:    [[A_CASTED_I:%.*]] = alloca i64, align 8
2680 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
2681 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
2682 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
2683 // CHECK2-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
2684 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
2685 // CHECK2-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
2686 // CHECK2-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
2687 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
2688 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
2689 // CHECK2-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
2690 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
2691 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
2692 // CHECK2-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
2693 // CHECK2-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
2694 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])
2695 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
2696 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
2697 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
2698 // CHECK2-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23
2699 // CHECK2-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23
2700 // CHECK2-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23
2701 // CHECK2-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23
2702 // CHECK2-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23
2703 // CHECK2-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23
2704 // CHECK2-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23
2705 // CHECK2-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23
2706 // CHECK2-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23
2707 // CHECK2-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
2708 // CHECK2-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
2709 // CHECK2-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23
2710 // CHECK2-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23
2711 // CHECK2-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23
2712 // CHECK2-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23
2713 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
2714 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
2715 // CHECK2-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
2716 // CHECK2-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
2717 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
2718 // CHECK2-NEXT:    [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) #[[ATTR3]]
2719 // CHECK2-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
2720 // CHECK2-NEXT:    br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
2721 // CHECK2:       omp_offload.failed.i:
2722 // CHECK2-NEXT:    [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2
2723 // CHECK2-NEXT:    [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
2724 // CHECK2-NEXT:    store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !23
2725 // CHECK2-NEXT:    [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !23
2726 // CHECK2-NEXT:    [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4
2727 // CHECK2-NEXT:    [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32*
2728 // CHECK2-NEXT:    store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !23
2729 // CHECK2-NEXT:    [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !23
2730 // CHECK2-NEXT:    [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4
2731 // CHECK2-NEXT:    [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32*
2732 // CHECK2-NEXT:    store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !23
2733 // CHECK2-NEXT:    [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !23
2734 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR3]]
2735 // CHECK2-NEXT:    br label [[DOTOMP_OUTLINED__3_EXIT]]
2736 // CHECK2:       .omp_outlined..3.exit:
2737 // CHECK2-NEXT:    ret i32 0
2738 //
2739 //
2740 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
2741 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
2742 // CHECK2-NEXT:  entry:
2743 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2744 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2745 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2746 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2747 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2748 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2749 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2750 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2751 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
2752 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2753 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
2754 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
2755 // CHECK2-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
2756 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2757 // CHECK2-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
2758 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2759 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
2760 // CHECK2-NEXT:    ret void
2761 //
2762 //
2763 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
2764 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
2765 // CHECK2-NEXT:  entry:
2766 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2767 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2768 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2769 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2770 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2771 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i16, align 2
2772 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2773 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2774 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2775 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2776 // CHECK2-NEXT:    [[IT:%.*]] = alloca i16, align 2
2777 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2778 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2779 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2780 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2781 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2782 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2783 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2784 // CHECK2-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
2785 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2786 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2787 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2788 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2789 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2790 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2791 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
2792 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2793 // CHECK2:       cond.true:
2794 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2795 // CHECK2:       cond.false:
2796 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2797 // CHECK2-NEXT:    br label [[COND_END]]
2798 // CHECK2:       cond.end:
2799 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2800 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2801 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2802 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2803 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2804 // CHECK2:       omp.inner.for.cond:
2805 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2806 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2807 // CHECK2-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2808 // CHECK2-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2809 // CHECK2:       omp.inner.for.body:
2810 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2811 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
2812 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
2813 // CHECK2-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
2814 // CHECK2-NEXT:    store i16 [[CONV3]], i16* [[IT]], align 2
2815 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
2816 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
2817 // CHECK2-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8
2818 // CHECK2-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
2819 // CHECK2-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
2820 // CHECK2-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
2821 // CHECK2-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
2822 // CHECK2-NEXT:    store i16 [[CONV7]], i16* [[CONV1]], align 8
2823 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2824 // CHECK2:       omp.body.continue:
2825 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2826 // CHECK2:       omp.inner.for.inc:
2827 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2828 // CHECK2-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
2829 // CHECK2-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
2830 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2831 // CHECK2:       omp.inner.for.end:
2832 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2833 // CHECK2:       omp.loop.exit:
2834 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2835 // CHECK2-NEXT:    ret void
2836 //
2837 //
2838 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
2839 // CHECK2-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
2840 // CHECK2-NEXT:  entry:
2841 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2842 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
2843 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
2844 // CHECK2-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
2845 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
2846 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
2847 // CHECK2-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
2848 // CHECK2-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
2849 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
2850 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
2851 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2852 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
2853 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2854 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
2855 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2856 // CHECK2-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
2857 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
2858 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
2859 // CHECK2-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
2860 // CHECK2-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
2861 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
2862 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
2863 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2864 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
2865 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2866 // CHECK2-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
2867 // CHECK2-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
2868 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
2869 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
2870 // CHECK2-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
2871 // CHECK2-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
2872 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
2873 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
2874 // CHECK2-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2875 // CHECK2-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
2876 // CHECK2-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
2877 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
2878 // CHECK2-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
2879 // CHECK2-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
2880 // CHECK2-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
2881 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
2882 // CHECK2-NEXT:    ret void
2883 //
2884 //
2885 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7
2886 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
2887 // CHECK2-NEXT:  entry:
2888 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2889 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2890 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2891 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
2892 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
2893 // CHECK2-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
2894 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
2895 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
2896 // CHECK2-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
2897 // CHECK2-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
2898 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
2899 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
2900 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2901 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i8, align 1
2902 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2903 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2904 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2905 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2906 // CHECK2-NEXT:    [[IT:%.*]] = alloca i8, align 1
2907 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2908 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2909 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2910 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
2911 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2912 // CHECK2-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
2913 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
2914 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
2915 // CHECK2-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
2916 // CHECK2-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
2917 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
2918 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
2919 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2920 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
2921 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2922 // CHECK2-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
2923 // CHECK2-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
2924 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
2925 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
2926 // CHECK2-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
2927 // CHECK2-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
2928 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
2929 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2930 // CHECK2-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
2931 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2932 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2933 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
2934 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2935 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
2936 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
2937 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2938 // CHECK2:       omp.dispatch.cond:
2939 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2940 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
2941 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2942 // CHECK2:       cond.true:
2943 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2944 // CHECK2:       cond.false:
2945 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2946 // CHECK2-NEXT:    br label [[COND_END]]
2947 // CHECK2:       cond.end:
2948 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
2949 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2950 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2951 // CHECK2-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
2952 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2953 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2954 // CHECK2-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
2955 // CHECK2-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2956 // CHECK2:       omp.dispatch.body:
2957 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2958 // CHECK2:       omp.inner.for.cond:
2959 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2960 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2961 // CHECK2-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
2962 // CHECK2-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2963 // CHECK2:       omp.inner.for.body:
2964 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2965 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
2966 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
2967 // CHECK2-NEXT:    [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
2968 // CHECK2-NEXT:    store i8 [[CONV8]], i8* [[IT]], align 1
2969 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
2970 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
2971 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
2972 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
2973 // CHECK2-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
2974 // CHECK2-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
2975 // CHECK2-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
2976 // CHECK2-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
2977 // CHECK2-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
2978 // CHECK2-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
2979 // CHECK2-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
2980 // CHECK2-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
2981 // CHECK2-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
2982 // CHECK2-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
2983 // CHECK2-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
2984 // CHECK2-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
2985 // CHECK2-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
2986 // CHECK2-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
2987 // CHECK2-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
2988 // CHECK2-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
2989 // CHECK2-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
2990 // CHECK2-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
2991 // CHECK2-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
2992 // CHECK2-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
2993 // CHECK2-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
2994 // CHECK2-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
2995 // CHECK2-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
2996 // CHECK2-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8
2997 // CHECK2-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
2998 // CHECK2-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8
2999 // CHECK2-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
3000 // CHECK2-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
3001 // CHECK2-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
3002 // CHECK2-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
3003 // CHECK2-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
3004 // CHECK2-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8
3005 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3006 // CHECK2:       omp.body.continue:
3007 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3008 // CHECK2:       omp.inner.for.inc:
3009 // CHECK2-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3010 // CHECK2-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
3011 // CHECK2-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
3012 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
3013 // CHECK2:       omp.inner.for.end:
3014 // CHECK2-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
3015 // CHECK2:       omp.dispatch.inc:
3016 // CHECK2-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3017 // CHECK2-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3018 // CHECK2-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
3019 // CHECK2-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
3020 // CHECK2-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3021 // CHECK2-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3022 // CHECK2-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
3023 // CHECK2-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
3024 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND]]
3025 // CHECK2:       omp.dispatch.end:
3026 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
3027 // CHECK2-NEXT:    ret void
3028 //
3029 //
3030 // CHECK2-LABEL: define {{[^@]+}}@_Z3bari
3031 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
3032 // CHECK2-NEXT:  entry:
3033 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3034 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
3035 // CHECK2-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
3036 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3037 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
3038 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3039 // CHECK2-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
3040 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
3041 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
3042 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
3043 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
3044 // CHECK2-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
3045 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
3046 // CHECK2-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
3047 // CHECK2-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
3048 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
3049 // CHECK2-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
3050 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
3051 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
3052 // CHECK2-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
3053 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
3054 // CHECK2-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
3055 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
3056 // CHECK2-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
3057 // CHECK2-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
3058 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
3059 // CHECK2-NEXT:    ret i32 [[TMP8]]
3060 //
3061 //
3062 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
3063 // CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
3064 // CHECK2-NEXT:  entry:
3065 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
3066 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3067 // CHECK2-NEXT:    [[B:%.*]] = alloca i32, align 4
3068 // CHECK2-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
3069 // CHECK2-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
3070 // CHECK2-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
3071 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
3072 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
3073 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
3074 // CHECK2-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
3075 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
3076 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3077 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
3078 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3079 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3080 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
3081 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
3082 // CHECK2-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
3083 // CHECK2-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
3084 // CHECK2-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
3085 // CHECK2-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
3086 // CHECK2-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
3087 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
3088 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
3089 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
3090 // CHECK2-NEXT:    store i32 [[TMP5]], i32* [[CONV]], align 4
3091 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
3092 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
3093 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
3094 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3095 // CHECK2:       omp_if.then:
3096 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
3097 // CHECK2-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
3098 // CHECK2-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
3099 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3100 // CHECK2-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
3101 // CHECK2-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
3102 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3103 // CHECK2-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
3104 // CHECK2-NEXT:    store double* [[A]], double** [[TMP13]], align 8
3105 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3106 // CHECK2-NEXT:    store i64 8, i64* [[TMP14]], align 8
3107 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
3108 // CHECK2-NEXT:    store i8* null, i8** [[TMP15]], align 8
3109 // CHECK2-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3110 // CHECK2-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
3111 // CHECK2-NEXT:    store i64 [[TMP6]], i64* [[TMP17]], align 8
3112 // CHECK2-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3113 // CHECK2-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
3114 // CHECK2-NEXT:    store i64 [[TMP6]], i64* [[TMP19]], align 8
3115 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
3116 // CHECK2-NEXT:    store i64 4, i64* [[TMP20]], align 8
3117 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
3118 // CHECK2-NEXT:    store i8* null, i8** [[TMP21]], align 8
3119 // CHECK2-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3120 // CHECK2-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
3121 // CHECK2-NEXT:    store i64 2, i64* [[TMP23]], align 8
3122 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3123 // CHECK2-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
3124 // CHECK2-NEXT:    store i64 2, i64* [[TMP25]], align 8
3125 // CHECK2-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
3126 // CHECK2-NEXT:    store i64 8, i64* [[TMP26]], align 8
3127 // CHECK2-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
3128 // CHECK2-NEXT:    store i8* null, i8** [[TMP27]], align 8
3129 // CHECK2-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3130 // CHECK2-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
3131 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP29]], align 8
3132 // CHECK2-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3133 // CHECK2-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
3134 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP31]], align 8
3135 // CHECK2-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
3136 // CHECK2-NEXT:    store i64 8, i64* [[TMP32]], align 8
3137 // CHECK2-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
3138 // CHECK2-NEXT:    store i8* null, i8** [[TMP33]], align 8
3139 // CHECK2-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3140 // CHECK2-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
3141 // CHECK2-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 8
3142 // CHECK2-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3143 // CHECK2-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
3144 // CHECK2-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 8
3145 // CHECK2-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
3146 // CHECK2-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 8
3147 // CHECK2-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
3148 // CHECK2-NEXT:    store i8* null, i8** [[TMP39]], align 8
3149 // CHECK2-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3150 // CHECK2-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3151 // CHECK2-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3152 // CHECK2-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
3153 // CHECK2-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
3154 // CHECK2-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3155 // CHECK2:       omp_offload.failed:
3156 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
3157 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3158 // CHECK2:       omp_offload.cont:
3159 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
3160 // CHECK2:       omp_if.else:
3161 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
3162 // CHECK2-NEXT:    br label [[OMP_IF_END]]
3163 // CHECK2:       omp_if.end:
3164 // CHECK2-NEXT:    [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
3165 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
3166 // CHECK2-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
3167 // CHECK2-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
3168 // CHECK2-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
3169 // CHECK2-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
3170 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
3171 // CHECK2-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
3172 // CHECK2-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
3173 // CHECK2-NEXT:    ret i32 [[ADD4]]
3174 //
3175 //
3176 // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici
3177 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
3178 // CHECK2-NEXT:  entry:
3179 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3180 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
3181 // CHECK2-NEXT:    [[AA:%.*]] = alloca i16, align 2
3182 // CHECK2-NEXT:    [[AAA:%.*]] = alloca i8, align 1
3183 // CHECK2-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
3184 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3185 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3186 // CHECK2-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
3187 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
3188 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
3189 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
3190 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3191 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
3192 // CHECK2-NEXT:    store i16 0, i16* [[AA]], align 2
3193 // CHECK2-NEXT:    store i8 0, i8* [[AAA]], align 1
3194 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
3195 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3196 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
3197 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
3198 // CHECK2-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
3199 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
3200 // CHECK2-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
3201 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
3202 // CHECK2-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
3203 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
3204 // CHECK2-NEXT:    store i8 [[TMP4]], i8* [[CONV2]], align 1
3205 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
3206 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
3207 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
3208 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3209 // CHECK2:       omp_if.then:
3210 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3211 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
3212 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
3213 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3214 // CHECK2-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
3215 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
3216 // CHECK2-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
3217 // CHECK2-NEXT:    store i8* null, i8** [[TMP11]], align 8
3218 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3219 // CHECK2-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
3220 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
3221 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3222 // CHECK2-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
3223 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
3224 // CHECK2-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
3225 // CHECK2-NEXT:    store i8* null, i8** [[TMP16]], align 8
3226 // CHECK2-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3227 // CHECK2-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
3228 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP18]], align 8
3229 // CHECK2-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3230 // CHECK2-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
3231 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
3232 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
3233 // CHECK2-NEXT:    store i8* null, i8** [[TMP21]], align 8
3234 // CHECK2-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3235 // CHECK2-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
3236 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
3237 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3238 // CHECK2-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
3239 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
3240 // CHECK2-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
3241 // CHECK2-NEXT:    store i8* null, i8** [[TMP26]], align 8
3242 // CHECK2-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3243 // CHECK2-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3244 // CHECK2-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
3245 // CHECK2-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
3246 // CHECK2-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3247 // CHECK2:       omp_offload.failed:
3248 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
3249 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3250 // CHECK2:       omp_offload.cont:
3251 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
3252 // CHECK2:       omp_if.else:
3253 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
3254 // CHECK2-NEXT:    br label [[OMP_IF_END]]
3255 // CHECK2:       omp_if.end:
3256 // CHECK2-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
3257 // CHECK2-NEXT:    ret i32 [[TMP31]]
3258 //
3259 //
3260 // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
3261 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
3262 // CHECK2-NEXT:  entry:
3263 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3264 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
3265 // CHECK2-NEXT:    [[AA:%.*]] = alloca i16, align 2
3266 // CHECK2-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
3267 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3268 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3269 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
3270 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
3271 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
3272 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3273 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
3274 // CHECK2-NEXT:    store i16 0, i16* [[AA]], align 2
3275 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
3276 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3277 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
3278 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
3279 // CHECK2-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
3280 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
3281 // CHECK2-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
3282 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
3283 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
3284 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
3285 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3286 // CHECK2:       omp_if.then:
3287 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3288 // CHECK2-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
3289 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
3290 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3291 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
3292 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
3293 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
3294 // CHECK2-NEXT:    store i8* null, i8** [[TMP9]], align 8
3295 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3296 // CHECK2-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
3297 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
3298 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3299 // CHECK2-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
3300 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
3301 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
3302 // CHECK2-NEXT:    store i8* null, i8** [[TMP14]], align 8
3303 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3304 // CHECK2-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
3305 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
3306 // CHECK2-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3307 // CHECK2-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
3308 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
3309 // CHECK2-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
3310 // CHECK2-NEXT:    store i8* null, i8** [[TMP19]], align 8
3311 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3312 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3313 // CHECK2-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
3314 // CHECK2-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
3315 // CHECK2-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3316 // CHECK2:       omp_offload.failed:
3317 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
3318 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3319 // CHECK2:       omp_offload.cont:
3320 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
3321 // CHECK2:       omp_if.else:
3322 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
3323 // CHECK2-NEXT:    br label [[OMP_IF_END]]
3324 // CHECK2:       omp_if.end:
3325 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
3326 // CHECK2-NEXT:    ret i32 [[TMP24]]
3327 //
3328 //
3329 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
3330 // CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
3331 // CHECK2-NEXT:  entry:
3332 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
3333 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
3334 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
3335 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
3336 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
3337 // CHECK2-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
3338 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
3339 // CHECK2-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
3340 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
3341 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
3342 // CHECK2-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
3343 // CHECK2-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
3344 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
3345 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
3346 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
3347 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
3348 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
3349 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
3350 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
3351 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
3352 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
3353 // CHECK2-NEXT:    ret void
3354 //
3355 //
3356 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9
3357 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
3358 // CHECK2-NEXT:  entry:
3359 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3360 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3361 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
3362 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
3363 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
3364 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
3365 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
3366 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
3367 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i64, align 8
3368 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
3369 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
3370 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
3371 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3372 // CHECK2-NEXT:    [[IT:%.*]] = alloca i64, align 8
3373 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3374 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3375 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
3376 // CHECK2-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
3377 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
3378 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
3379 // CHECK2-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
3380 // CHECK2-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
3381 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
3382 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
3383 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
3384 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
3385 // CHECK2-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
3386 // CHECK2-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
3387 // CHECK2-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
3388 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3389 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3390 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
3391 // CHECK2-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
3392 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3393 // CHECK2-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
3394 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3395 // CHECK2:       cond.true:
3396 // CHECK2-NEXT:    br label [[COND_END:%.*]]
3397 // CHECK2:       cond.false:
3398 // CHECK2-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3399 // CHECK2-NEXT:    br label [[COND_END]]
3400 // CHECK2:       cond.end:
3401 // CHECK2-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3402 // CHECK2-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
3403 // CHECK2-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
3404 // CHECK2-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
3405 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3406 // CHECK2:       omp.inner.for.cond:
3407 // CHECK2-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3408 // CHECK2-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3409 // CHECK2-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
3410 // CHECK2-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3411 // CHECK2:       omp.inner.for.body:
3412 // CHECK2-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3413 // CHECK2-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
3414 // CHECK2-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
3415 // CHECK2-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
3416 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
3417 // CHECK2-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
3418 // CHECK2-NEXT:    [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
3419 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
3420 // CHECK2-NEXT:    store double [[ADD]], double* [[A]], align 8
3421 // CHECK2-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
3422 // CHECK2-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 8
3423 // CHECK2-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
3424 // CHECK2-NEXT:    store double [[INC]], double* [[A5]], align 8
3425 // CHECK2-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
3426 // CHECK2-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
3427 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
3428 // CHECK2-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
3429 // CHECK2-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
3430 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3431 // CHECK2:       omp.body.continue:
3432 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3433 // CHECK2:       omp.inner.for.inc:
3434 // CHECK2-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3435 // CHECK2-NEXT:    [[ADD8:%.*]] = add i64 [[TMP15]], 1
3436 // CHECK2-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
3437 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
3438 // CHECK2:       omp.inner.for.end:
3439 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3440 // CHECK2:       omp.loop.exit:
3441 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
3442 // CHECK2-NEXT:    ret void
3443 //
3444 //
3445 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
3446 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3447 // CHECK2-NEXT:  entry:
3448 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3449 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3450 // CHECK2-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
3451 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
3452 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3453 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3454 // CHECK2-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
3455 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3456 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
3457 // CHECK2-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
3458 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
3459 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3460 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3461 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
3462 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
3463 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
3464 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3465 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
3466 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
3467 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
3468 // CHECK2-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
3469 // CHECK2-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
3470 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
3471 // CHECK2-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
3472 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
3473 // CHECK2-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
3474 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
3475 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
3476 // CHECK2-NEXT:    ret void
3477 //
3478 //
3479 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
3480 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3481 // CHECK2-NEXT:  entry:
3482 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3483 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3484 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3485 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3486 // CHECK2-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
3487 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
3488 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3489 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3490 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3491 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3492 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3493 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
3494 // CHECK2-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
3495 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
3496 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3497 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3498 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
3499 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
3500 // CHECK2-NEXT:    ret void
3501 //
3502 //
3503 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
3504 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3505 // CHECK2-NEXT:  entry:
3506 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3507 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3508 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
3509 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3510 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3511 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3512 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
3513 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
3514 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3515 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3516 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
3517 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
3518 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3519 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
3520 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
3521 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
3522 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
3523 // CHECK2-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
3524 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
3525 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
3526 // CHECK2-NEXT:    ret void
3527 //
3528 //
3529 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14
3530 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3531 // CHECK2-NEXT:  entry:
3532 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3533 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3534 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3535 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3536 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
3537 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
3538 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i64, align 8
3539 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
3540 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
3541 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
3542 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3543 // CHECK2-NEXT:    [[I:%.*]] = alloca i64, align 8
3544 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3545 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3546 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3547 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
3548 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
3549 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3550 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3551 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
3552 // CHECK2-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
3553 // CHECK2-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
3554 // CHECK2-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
3555 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3556 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3557 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
3558 // CHECK2-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
3559 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3560 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
3561 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3562 // CHECK2:       cond.true:
3563 // CHECK2-NEXT:    br label [[COND_END:%.*]]
3564 // CHECK2:       cond.false:
3565 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3566 // CHECK2-NEXT:    br label [[COND_END]]
3567 // CHECK2:       cond.end:
3568 // CHECK2-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
3569 // CHECK2-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
3570 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
3571 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
3572 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3573 // CHECK2:       omp.inner.for.cond:
3574 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3575 // CHECK2-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3576 // CHECK2-NEXT:    [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
3577 // CHECK2-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3578 // CHECK2:       omp.inner.for.body:
3579 // CHECK2-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3580 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
3581 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
3582 // CHECK2-NEXT:    store i64 [[ADD]], i64* [[I]], align 8
3583 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
3584 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
3585 // CHECK2-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
3586 // CHECK2-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
3587 // CHECK2-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
3588 // CHECK2-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
3589 // CHECK2-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
3590 // CHECK2-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
3591 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
3592 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
3593 // CHECK2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
3594 // CHECK2-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
3595 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3596 // CHECK2:       omp.body.continue:
3597 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3598 // CHECK2:       omp.inner.for.inc:
3599 // CHECK2-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3600 // CHECK2-NEXT:    [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
3601 // CHECK2-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
3602 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
3603 // CHECK2:       omp.inner.for.end:
3604 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3605 // CHECK2:       omp.loop.exit:
3606 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
3607 // CHECK2-NEXT:    ret void
3608 //
3609 //
3610 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3611 // CHECK2-SAME: () #[[ATTR5]] {
3612 // CHECK2-NEXT:  entry:
3613 // CHECK2-NEXT:    call void @__tgt_register_requires(i64 1)
3614 // CHECK2-NEXT:    ret void
3615 //
3616 //
3617 // CHECK3-LABEL: define {{[^@]+}}@_Z7get_valv
3618 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
3619 // CHECK3-NEXT:  entry:
3620 // CHECK3-NEXT:    ret i64 0
3621 //
3622 //
3623 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi
3624 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
3625 // CHECK3-NEXT:  entry:
3626 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3627 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
3628 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
3629 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
3630 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
3631 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
3632 // CHECK3-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
3633 // CHECK3-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
3634 // CHECK3-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
3635 // CHECK3-NEXT:    [[K:%.*]] = alloca i64, align 8
3636 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3637 // CHECK3-NEXT:    [[LIN:%.*]] = alloca i32, align 4
3638 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3639 // CHECK3-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
3640 // CHECK3-NEXT:    [[A_CASTED2:%.*]] = alloca i32, align 4
3641 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
3642 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
3643 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
3644 // CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
3645 // CHECK3-NEXT:    [[A_CASTED3:%.*]] = alloca i32, align 4
3646 // CHECK3-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
3647 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4
3648 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4
3649 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4
3650 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3651 // CHECK3-NEXT:    [[A_CASTED11:%.*]] = alloca i32, align 4
3652 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
3653 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4
3654 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4
3655 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4
3656 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
3657 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
3658 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3659 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
3660 // CHECK3-NEXT:    store i16 0, i16* [[AA]], align 2
3661 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
3662 // CHECK3-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
3663 // CHECK3-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
3664 // CHECK3-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
3665 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
3666 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
3667 // CHECK3-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
3668 // CHECK3-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
3669 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
3670 // CHECK3-NEXT:    [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
3671 // CHECK3-NEXT:    [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
3672 // CHECK3-NEXT:    br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3673 // CHECK3:       omp_offload.failed:
3674 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]]
3675 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3676 // CHECK3:       omp_offload.cont:
3677 // CHECK3-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
3678 // CHECK3-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
3679 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
3680 // CHECK3-NEXT:    store i32 [[TMP7]], i32* [[A_CASTED]], align 4
3681 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4
3682 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR3]]
3683 // CHECK3-NEXT:    store i32 12, i32* [[LIN]], align 4
3684 // CHECK3-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
3685 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3686 // CHECK3-NEXT:    store i16 [[TMP9]], i16* [[CONV]], align 2
3687 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3688 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4
3689 // CHECK3-NEXT:    store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4
3690 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
3691 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4
3692 // CHECK3-NEXT:    store i32 [[TMP13]], i32* [[A_CASTED2]], align 4
3693 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4
3694 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3695 // CHECK3-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
3696 // CHECK3-NEXT:    store i32 [[TMP10]], i32* [[TMP16]], align 4
3697 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3698 // CHECK3-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
3699 // CHECK3-NEXT:    store i32 [[TMP10]], i32* [[TMP18]], align 4
3700 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3701 // CHECK3-NEXT:    store i8* null, i8** [[TMP19]], align 4
3702 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3703 // CHECK3-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
3704 // CHECK3-NEXT:    store i32 [[TMP12]], i32* [[TMP21]], align 4
3705 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3706 // CHECK3-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
3707 // CHECK3-NEXT:    store i32 [[TMP12]], i32* [[TMP23]], align 4
3708 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3709 // CHECK3-NEXT:    store i8* null, i8** [[TMP24]], align 4
3710 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3711 // CHECK3-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
3712 // CHECK3-NEXT:    store i32 [[TMP14]], i32* [[TMP26]], align 4
3713 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3714 // CHECK3-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
3715 // CHECK3-NEXT:    store i32 [[TMP14]], i32* [[TMP28]], align 4
3716 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3717 // CHECK3-NEXT:    store i8* null, i8** [[TMP29]], align 4
3718 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3719 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3720 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
3721 // CHECK3-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
3722 // CHECK3-NEXT:    store i16 [[TMP33]], i16* [[TMP32]], align 4
3723 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
3724 // CHECK3-NEXT:    [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4
3725 // CHECK3-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
3726 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
3727 // CHECK3-NEXT:    [[TMP37:%.*]] = load i32, i32* [[A]], align 4
3728 // CHECK3-NEXT:    store i32 [[TMP37]], i32* [[TMP36]], align 4
3729 // CHECK3-NEXT:    [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
3730 // CHECK3-NEXT:    [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
3731 // CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
3732 // CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
3733 // CHECK3-NEXT:    [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4
3734 // CHECK3-NEXT:    [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
3735 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false)
3736 // CHECK3-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
3737 // CHECK3-NEXT:    [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
3738 // CHECK3-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
3739 // CHECK3-NEXT:    [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8*
3740 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
3741 // CHECK3-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
3742 // CHECK3-NEXT:    [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8*
3743 // CHECK3-NEXT:    [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8*
3744 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false)
3745 // CHECK3-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
3746 // CHECK3-NEXT:    [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8*
3747 // CHECK3-NEXT:    [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8*
3748 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false)
3749 // CHECK3-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
3750 // CHECK3-NEXT:    [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
3751 // CHECK3-NEXT:    store i16 [[TMP55]], i16* [[TMP54]], align 4
3752 // CHECK3-NEXT:    [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]])
3753 // CHECK3-NEXT:    [[TMP57:%.*]] = load i32, i32* [[A]], align 4
3754 // CHECK3-NEXT:    store i32 [[TMP57]], i32* [[A_CASTED3]], align 4
3755 // CHECK3-NEXT:    [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4
3756 // CHECK3-NEXT:    [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
3757 // CHECK3-NEXT:    [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
3758 // CHECK3-NEXT:    store i16 [[TMP59]], i16* [[CONV5]], align 2
3759 // CHECK3-NEXT:    [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
3760 // CHECK3-NEXT:    [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4
3761 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10
3762 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3763 // CHECK3:       omp_if.then:
3764 // CHECK3-NEXT:    [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
3765 // CHECK3-NEXT:    [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32*
3766 // CHECK3-NEXT:    store i32 [[TMP58]], i32* [[TMP63]], align 4
3767 // CHECK3-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
3768 // CHECK3-NEXT:    [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32*
3769 // CHECK3-NEXT:    store i32 [[TMP58]], i32* [[TMP65]], align 4
3770 // CHECK3-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
3771 // CHECK3-NEXT:    store i8* null, i8** [[TMP66]], align 4
3772 // CHECK3-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1
3773 // CHECK3-NEXT:    [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32*
3774 // CHECK3-NEXT:    store i32 [[TMP60]], i32* [[TMP68]], align 4
3775 // CHECK3-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1
3776 // CHECK3-NEXT:    [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32*
3777 // CHECK3-NEXT:    store i32 [[TMP60]], i32* [[TMP70]], align 4
3778 // CHECK3-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1
3779 // CHECK3-NEXT:    store i8* null, i8** [[TMP71]], align 4
3780 // CHECK3-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
3781 // CHECK3-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
3782 // CHECK3-NEXT:    [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
3783 // CHECK3-NEXT:    [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0
3784 // CHECK3-NEXT:    br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
3785 // CHECK3:       omp_offload.failed9:
3786 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR3]]
3787 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT10]]
3788 // CHECK3:       omp_offload.cont10:
3789 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
3790 // CHECK3:       omp_if.else:
3791 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR3]]
3792 // CHECK3-NEXT:    br label [[OMP_IF_END]]
3793 // CHECK3:       omp_if.end:
3794 // CHECK3-NEXT:    [[TMP76:%.*]] = load i32, i32* [[A]], align 4
3795 // CHECK3-NEXT:    store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4
3796 // CHECK3-NEXT:    [[TMP77:%.*]] = load i32, i32* [[A]], align 4
3797 // CHECK3-NEXT:    store i32 [[TMP77]], i32* [[A_CASTED11]], align 4
3798 // CHECK3-NEXT:    [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4
3799 // CHECK3-NEXT:    [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3800 // CHECK3-NEXT:    store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
3801 // CHECK3-NEXT:    [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
3802 // CHECK3-NEXT:    [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4
3803 // CHECK3-NEXT:    [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20
3804 // CHECK3-NEXT:    br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]]
3805 // CHECK3:       omp_if.then13:
3806 // CHECK3-NEXT:    [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4
3807 // CHECK3-NEXT:    [[TMP83:%.*]] = sext i32 [[TMP82]] to i64
3808 // CHECK3-NEXT:    [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]]
3809 // CHECK3-NEXT:    [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8
3810 // CHECK3-NEXT:    [[TMP86:%.*]] = sext i32 [[TMP85]] to i64
3811 // CHECK3-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
3812 // CHECK3-NEXT:    [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32*
3813 // CHECK3-NEXT:    store i32 [[TMP78]], i32* [[TMP88]], align 4
3814 // CHECK3-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
3815 // CHECK3-NEXT:    [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32*
3816 // CHECK3-NEXT:    store i32 [[TMP78]], i32* [[TMP90]], align 4
3817 // CHECK3-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3818 // CHECK3-NEXT:    store i64 4, i64* [[TMP91]], align 4
3819 // CHECK3-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
3820 // CHECK3-NEXT:    store i8* null, i8** [[TMP92]], align 4
3821 // CHECK3-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
3822 // CHECK3-NEXT:    [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]**
3823 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4
3824 // CHECK3-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
3825 // CHECK3-NEXT:    [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]**
3826 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4
3827 // CHECK3-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
3828 // CHECK3-NEXT:    store i64 40, i64* [[TMP97]], align 4
3829 // CHECK3-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
3830 // CHECK3-NEXT:    store i8* null, i8** [[TMP98]], align 4
3831 // CHECK3-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
3832 // CHECK3-NEXT:    [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i32*
3833 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP100]], align 4
3834 // CHECK3-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
3835 // CHECK3-NEXT:    [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i32*
3836 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP102]], align 4
3837 // CHECK3-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
3838 // CHECK3-NEXT:    store i64 4, i64* [[TMP103]], align 4
3839 // CHECK3-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
3840 // CHECK3-NEXT:    store i8* null, i8** [[TMP104]], align 4
3841 // CHECK3-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
3842 // CHECK3-NEXT:    [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float**
3843 // CHECK3-NEXT:    store float* [[VLA]], float** [[TMP106]], align 4
3844 // CHECK3-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
3845 // CHECK3-NEXT:    [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float**
3846 // CHECK3-NEXT:    store float* [[VLA]], float** [[TMP108]], align 4
3847 // CHECK3-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
3848 // CHECK3-NEXT:    store i64 [[TMP83]], i64* [[TMP109]], align 4
3849 // CHECK3-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
3850 // CHECK3-NEXT:    store i8* null, i8** [[TMP110]], align 4
3851 // CHECK3-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
3852 // CHECK3-NEXT:    [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]**
3853 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4
3854 // CHECK3-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
3855 // CHECK3-NEXT:    [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]**
3856 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 4
3857 // CHECK3-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
3858 // CHECK3-NEXT:    store i64 400, i64* [[TMP115]], align 4
3859 // CHECK3-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
3860 // CHECK3-NEXT:    store i8* null, i8** [[TMP116]], align 4
3861 // CHECK3-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
3862 // CHECK3-NEXT:    [[TMP118:%.*]] = bitcast i8** [[TMP117]] to i32*
3863 // CHECK3-NEXT:    store i32 5, i32* [[TMP118]], align 4
3864 // CHECK3-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
3865 // CHECK3-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32*
3866 // CHECK3-NEXT:    store i32 5, i32* [[TMP120]], align 4
3867 // CHECK3-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
3868 // CHECK3-NEXT:    store i64 4, i64* [[TMP121]], align 4
3869 // CHECK3-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
3870 // CHECK3-NEXT:    store i8* null, i8** [[TMP122]], align 4
3871 // CHECK3-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
3872 // CHECK3-NEXT:    [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32*
3873 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP124]], align 4
3874 // CHECK3-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
3875 // CHECK3-NEXT:    [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32*
3876 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP126]], align 4
3877 // CHECK3-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
3878 // CHECK3-NEXT:    store i64 4, i64* [[TMP127]], align 4
3879 // CHECK3-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
3880 // CHECK3-NEXT:    store i8* null, i8** [[TMP128]], align 4
3881 // CHECK3-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
3882 // CHECK3-NEXT:    [[TMP130:%.*]] = bitcast i8** [[TMP129]] to double**
3883 // CHECK3-NEXT:    store double* [[VLA1]], double** [[TMP130]], align 4
3884 // CHECK3-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
3885 // CHECK3-NEXT:    [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double**
3886 // CHECK3-NEXT:    store double* [[VLA1]], double** [[TMP132]], align 4
3887 // CHECK3-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
3888 // CHECK3-NEXT:    store i64 [[TMP86]], i64* [[TMP133]], align 4
3889 // CHECK3-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
3890 // CHECK3-NEXT:    store i8* null, i8** [[TMP134]], align 4
3891 // CHECK3-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
3892 // CHECK3-NEXT:    [[TMP136:%.*]] = bitcast i8** [[TMP135]] to %struct.TT**
3893 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP136]], align 4
3894 // CHECK3-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
3895 // CHECK3-NEXT:    [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT**
3896 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 4
3897 // CHECK3-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
3898 // CHECK3-NEXT:    store i64 12, i64* [[TMP139]], align 4
3899 // CHECK3-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
3900 // CHECK3-NEXT:    store i8* null, i8** [[TMP140]], align 4
3901 // CHECK3-NEXT:    [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
3902 // CHECK3-NEXT:    [[TMP142:%.*]] = bitcast i8** [[TMP141]] to i32*
3903 // CHECK3-NEXT:    store i32 [[TMP80]], i32* [[TMP142]], align 4
3904 // CHECK3-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
3905 // CHECK3-NEXT:    [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i32*
3906 // CHECK3-NEXT:    store i32 [[TMP80]], i32* [[TMP144]], align 4
3907 // CHECK3-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
3908 // CHECK3-NEXT:    store i64 4, i64* [[TMP145]], align 4
3909 // CHECK3-NEXT:    [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
3910 // CHECK3-NEXT:    store i8* null, i8** [[TMP146]], align 4
3911 // CHECK3-NEXT:    [[TMP147:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
3912 // CHECK3-NEXT:    [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
3913 // CHECK3-NEXT:    [[TMP149:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3914 // CHECK3-NEXT:    [[TMP150:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP147]], i8** [[TMP148]], i64* [[TMP149]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
3915 // CHECK3-NEXT:    [[TMP151:%.*]] = icmp ne i32 [[TMP150]], 0
3916 // CHECK3-NEXT:    br i1 [[TMP151]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
3917 // CHECK3:       omp_offload.failed17:
3918 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR3]]
3919 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT18]]
3920 // CHECK3:       omp_offload.cont18:
3921 // CHECK3-NEXT:    br label [[OMP_IF_END20:%.*]]
3922 // CHECK3:       omp_if.else19:
3923 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR3]]
3924 // CHECK3-NEXT:    br label [[OMP_IF_END20]]
3925 // CHECK3:       omp_if.end20:
3926 // CHECK3-NEXT:    [[TMP152:%.*]] = load i32, i32* [[A]], align 4
3927 // CHECK3-NEXT:    [[TMP153:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
3928 // CHECK3-NEXT:    call void @llvm.stackrestore(i8* [[TMP153]])
3929 // CHECK3-NEXT:    ret i32 [[TMP152]]
3930 //
3931 //
3932 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
3933 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] {
3934 // CHECK3-NEXT:  entry:
3935 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
3936 // CHECK3-NEXT:    ret void
3937 //
3938 //
3939 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
3940 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
3941 // CHECK3-NEXT:  entry:
3942 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3943 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3944 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3945 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3946 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3947 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3948 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3949 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3950 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3951 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3952 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3953 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
3954 // CHECK3-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
3955 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3956 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3957 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3958 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
3959 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3960 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3961 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
3962 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3963 // CHECK3:       cond.true:
3964 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3965 // CHECK3:       cond.false:
3966 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3967 // CHECK3-NEXT:    br label [[COND_END]]
3968 // CHECK3:       cond.end:
3969 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
3970 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3971 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3972 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
3973 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3974 // CHECK3:       omp.inner.for.cond:
3975 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3976 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3977 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
3978 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3979 // CHECK3:       omp.inner.for.body:
3980 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3981 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
3982 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
3983 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
3984 // CHECK3-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
3985 // CHECK3-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
3986 // CHECK3-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
3987 // CHECK3:       .cancel.exit:
3988 // CHECK3-NEXT:    br label [[CANCEL_EXIT:%.*]]
3989 // CHECK3:       .cancel.continue:
3990 // CHECK3-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
3991 // CHECK3-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
3992 // CHECK3-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
3993 // CHECK3:       .cancel.exit2:
3994 // CHECK3-NEXT:    br label [[CANCEL_EXIT]]
3995 // CHECK3:       .cancel.continue3:
3996 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3997 // CHECK3:       omp.body.continue:
3998 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3999 // CHECK3:       omp.inner.for.inc:
4000 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4001 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
4002 // CHECK3-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
4003 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
4004 // CHECK3:       omp.inner.for.end:
4005 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4006 // CHECK3:       omp.loop.exit:
4007 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4008 // CHECK3-NEXT:    br label [[CANCEL_CONT:%.*]]
4009 // CHECK3:       cancel.cont:
4010 // CHECK3-NEXT:    ret void
4011 // CHECK3:       cancel.exit:
4012 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4013 // CHECK3-NEXT:    br label [[CANCEL_CONT]]
4014 //
4015 //
4016 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
4017 // CHECK3-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {
4018 // CHECK3-NEXT:  entry:
4019 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4020 // CHECK3-NEXT:    [[K_ADDR:%.*]] = alloca i64*, align 4
4021 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4022 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4023 // CHECK3-NEXT:    store i64* [[K]], i64** [[K_ADDR]], align 4
4024 // CHECK3-NEXT:    [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
4025 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
4026 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
4027 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
4028 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]])
4029 // CHECK3-NEXT:    ret void
4030 //
4031 //
4032 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
4033 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {
4034 // CHECK3-NEXT:  entry:
4035 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4036 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4037 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4038 // CHECK3-NEXT:    [[K_ADDR:%.*]] = alloca i64*, align 4
4039 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4040 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4041 // CHECK3-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
4042 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4043 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4044 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4045 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4046 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
4047 // CHECK3-NEXT:    [[K1:%.*]] = alloca i64, align 8
4048 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4049 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4050 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4051 // CHECK3-NEXT:    store i64* [[K]], i64** [[K_ADDR]], align 4
4052 // CHECK3-NEXT:    [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
4053 // CHECK3-NEXT:    [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8
4054 // CHECK3-NEXT:    store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8
4055 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4056 // CHECK3-NEXT:    store i32 8, i32* [[DOTOMP_UB]], align 4
4057 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4058 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4059 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4060 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
4061 // CHECK3-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
4062 // CHECK3-NEXT:    call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1)
4063 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
4064 // CHECK3:       omp.dispatch.cond:
4065 // CHECK3-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
4066 // CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
4067 // CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
4068 // CHECK3:       omp.dispatch.body:
4069 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4070 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
4071 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4072 // CHECK3:       omp.inner.for.cond:
4073 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
4074 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
4075 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
4076 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4077 // CHECK3:       omp.inner.for.body:
4078 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
4079 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
4080 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
4081 // CHECK3-NEXT:    store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12
4082 // CHECK3-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12
4083 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
4084 // CHECK3-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
4085 // CHECK3-NEXT:    [[CONV:%.*]] = sext i32 [[MUL2]] to i64
4086 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
4087 // CHECK3-NEXT:    store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
4088 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12
4089 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
4090 // CHECK3-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !12
4091 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4092 // CHECK3:       omp.body.continue:
4093 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4094 // CHECK3:       omp.inner.for.inc:
4095 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
4096 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
4097 // CHECK3-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
4098 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
4099 // CHECK3:       omp.inner.for.end:
4100 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
4101 // CHECK3:       omp.dispatch.inc:
4102 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
4103 // CHECK3:       omp.dispatch.end:
4104 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4105 // CHECK3-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
4106 // CHECK3-NEXT:    br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
4107 // CHECK3:       .omp.linear.pu:
4108 // CHECK3-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
4109 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP15]], 27
4110 // CHECK3-NEXT:    store i64 [[ADD5]], i64* [[TMP0]], align 8
4111 // CHECK3-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
4112 // CHECK3:       .omp.linear.pu.done:
4113 // CHECK3-NEXT:    ret void
4114 //
4115 //
4116 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
4117 // CHECK3-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
4118 // CHECK3-NEXT:  entry:
4119 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4120 // CHECK3-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
4121 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4122 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4123 // CHECK3-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
4124 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4125 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4126 // CHECK3-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
4127 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4128 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4129 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
4130 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4131 // CHECK3-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
4132 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4133 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
4134 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
4135 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
4136 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
4137 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[A_CASTED]], align 4
4138 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
4139 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
4140 // CHECK3-NEXT:    ret void
4141 //
4142 //
4143 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2
4144 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
4145 // CHECK3-NEXT:  entry:
4146 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4147 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4148 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4149 // CHECK3-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
4150 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4151 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
4152 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i64, align 4
4153 // CHECK3-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
4154 // CHECK3-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
4155 // CHECK3-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
4156 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
4157 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
4158 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
4159 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4160 // CHECK3-NEXT:    [[IT:%.*]] = alloca i64, align 8
4161 // CHECK3-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
4162 // CHECK3-NEXT:    [[A3:%.*]] = alloca i32, align 4
4163 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4164 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4165 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4166 // CHECK3-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
4167 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4168 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4169 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
4170 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
4171 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
4172 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
4173 // CHECK3-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
4174 // CHECK3-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
4175 // CHECK3-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
4176 // CHECK3-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
4177 // CHECK3-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
4178 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4179 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4180 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
4181 // CHECK3-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
4182 // CHECK3-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
4183 // CHECK3-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
4184 // CHECK3-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
4185 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4186 // CHECK3:       cond.true:
4187 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4188 // CHECK3:       cond.false:
4189 // CHECK3-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
4190 // CHECK3-NEXT:    br label [[COND_END]]
4191 // CHECK3:       cond.end:
4192 // CHECK3-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
4193 // CHECK3-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
4194 // CHECK3-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
4195 // CHECK3-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
4196 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4197 // CHECK3:       omp.inner.for.cond:
4198 // CHECK3-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
4199 // CHECK3-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
4200 // CHECK3-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
4201 // CHECK3-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4202 // CHECK3:       omp.inner.for.body:
4203 // CHECK3-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
4204 // CHECK3-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
4205 // CHECK3-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
4206 // CHECK3-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
4207 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
4208 // CHECK3-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
4209 // CHECK3-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
4210 // CHECK3-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
4211 // CHECK3-NEXT:    [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
4212 // CHECK3-NEXT:    [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
4213 // CHECK3-NEXT:    [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
4214 // CHECK3-NEXT:    store i32 [[CONV7]], i32* [[LIN2]], align 4
4215 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
4216 // CHECK3-NEXT:    [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
4217 // CHECK3-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
4218 // CHECK3-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
4219 // CHECK3-NEXT:    [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
4220 // CHECK3-NEXT:    [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
4221 // CHECK3-NEXT:    [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
4222 // CHECK3-NEXT:    store i32 [[CONV11]], i32* [[A3]], align 4
4223 // CHECK3-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4
4224 // CHECK3-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
4225 // CHECK3-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
4226 // CHECK3-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
4227 // CHECK3-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4
4228 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4229 // CHECK3:       omp.body.continue:
4230 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4231 // CHECK3:       omp.inner.for.inc:
4232 // CHECK3-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
4233 // CHECK3-NEXT:    [[ADD15:%.*]] = add i64 [[TMP17]], 1
4234 // CHECK3-NEXT:    store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
4235 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
4236 // CHECK3:       omp.inner.for.end:
4237 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4238 // CHECK3:       omp.loop.exit:
4239 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
4240 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4241 // CHECK3-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
4242 // CHECK3-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
4243 // CHECK3:       .omp.linear.pu:
4244 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
4245 // CHECK3-NEXT:    [[CONV16:%.*]] = sext i32 [[TMP20]] to i64
4246 // CHECK3-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
4247 // CHECK3-NEXT:    [[MUL17:%.*]] = mul i64 4, [[TMP21]]
4248 // CHECK3-NEXT:    [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
4249 // CHECK3-NEXT:    [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
4250 // CHECK3-NEXT:    store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
4251 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
4252 // CHECK3-NEXT:    [[CONV20:%.*]] = sext i32 [[TMP22]] to i64
4253 // CHECK3-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
4254 // CHECK3-NEXT:    [[MUL21:%.*]] = mul i64 4, [[TMP23]]
4255 // CHECK3-NEXT:    [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
4256 // CHECK3-NEXT:    [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
4257 // CHECK3-NEXT:    store i32 [[CONV23]], i32* [[A_ADDR]], align 4
4258 // CHECK3-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
4259 // CHECK3:       .omp.linear.pu.done:
4260 // CHECK3-NEXT:    ret void
4261 //
4262 //
4263 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.
4264 // CHECK3-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
4265 // CHECK3-NEXT:  entry:
4266 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
4267 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 4
4268 // CHECK3-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
4269 // CHECK3-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
4270 // CHECK3-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
4271 // CHECK3-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
4272 // CHECK3-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
4273 // CHECK3-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
4274 // CHECK3-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
4275 // CHECK3-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
4276 // CHECK3-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
4277 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
4278 // CHECK3-NEXT:    [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
4279 // CHECK3-NEXT:    store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
4280 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
4281 // CHECK3-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
4282 // CHECK3-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
4283 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
4284 // CHECK3-NEXT:    [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
4285 // CHECK3-NEXT:    store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
4286 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
4287 // CHECK3-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
4288 // CHECK3-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 4
4289 // CHECK3-NEXT:    ret void
4290 //
4291 //
4292 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.
4293 // CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
4294 // CHECK3-NEXT:  entry:
4295 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
4296 // CHECK3-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
4297 // CHECK3-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
4298 // CHECK3-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
4299 // CHECK3-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
4300 // CHECK3-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
4301 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
4302 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
4303 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
4304 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
4305 // CHECK3-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
4306 // CHECK3-NEXT:    [[LIN_CASTED_I:%.*]] = alloca i32, align 4
4307 // CHECK3-NEXT:    [[A_CASTED_I:%.*]] = alloca i32, align 4
4308 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
4309 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
4310 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
4311 // CHECK3-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
4312 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
4313 // CHECK3-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
4314 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
4315 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
4316 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
4317 // CHECK3-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
4318 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
4319 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
4320 // CHECK3-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
4321 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
4322 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
4323 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
4324 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
4325 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
4326 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
4327 // CHECK3-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24
4328 // CHECK3-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24
4329 // CHECK3-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24
4330 // CHECK3-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24
4331 // CHECK3-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24
4332 // CHECK3-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24
4333 // CHECK3-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24
4334 // CHECK3-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24
4335 // CHECK3-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
4336 // CHECK3-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
4337 // CHECK3-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24
4338 // CHECK3-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24
4339 // CHECK3-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24
4340 // CHECK3-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24
4341 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
4342 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
4343 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
4344 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
4345 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
4346 // CHECK3-NEXT:    [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) #[[ATTR3]]
4347 // CHECK3-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
4348 // CHECK3-NEXT:    br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
4349 // CHECK3:       omp_offload.failed.i:
4350 // CHECK3-NEXT:    [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2
4351 // CHECK3-NEXT:    [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
4352 // CHECK3-NEXT:    store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24
4353 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !24
4354 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4
4355 // CHECK3-NEXT:    store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !24
4356 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !24
4357 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4
4358 // CHECK3-NEXT:    store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !24
4359 // CHECK3-NEXT:    [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !24
4360 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR3]]
4361 // CHECK3-NEXT:    br label [[DOTOMP_OUTLINED__3_EXIT]]
4362 // CHECK3:       .omp_outlined..3.exit:
4363 // CHECK3-NEXT:    ret i32 0
4364 //
4365 //
4366 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
4367 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
4368 // CHECK3-NEXT:  entry:
4369 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4370 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4371 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4372 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4373 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4374 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4375 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4376 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4377 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4378 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4379 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
4380 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4381 // CHECK3-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
4382 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4383 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
4384 // CHECK3-NEXT:    ret void
4385 //
4386 //
4387 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
4388 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
4389 // CHECK3-NEXT:  entry:
4390 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4391 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4392 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4393 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4394 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4395 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i16, align 2
4396 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4397 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4398 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4399 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4400 // CHECK3-NEXT:    [[IT:%.*]] = alloca i16, align 2
4401 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4402 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4403 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4404 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4405 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4406 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4407 // CHECK3-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
4408 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4409 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4410 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4411 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4412 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4413 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4414 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
4415 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4416 // CHECK3:       cond.true:
4417 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4418 // CHECK3:       cond.false:
4419 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4420 // CHECK3-NEXT:    br label [[COND_END]]
4421 // CHECK3:       cond.end:
4422 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4423 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4424 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4425 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4426 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4427 // CHECK3:       omp.inner.for.cond:
4428 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4429 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4430 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4431 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4432 // CHECK3:       omp.inner.for.body:
4433 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4434 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
4435 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
4436 // CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
4437 // CHECK3-NEXT:    store i16 [[CONV2]], i16* [[IT]], align 2
4438 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
4439 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
4440 // CHECK3-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4
4441 // CHECK3-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
4442 // CHECK3-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
4443 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
4444 // CHECK3-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
4445 // CHECK3-NEXT:    store i16 [[CONV6]], i16* [[CONV]], align 4
4446 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4447 // CHECK3:       omp.body.continue:
4448 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4449 // CHECK3:       omp.inner.for.inc:
4450 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4451 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
4452 // CHECK3-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
4453 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
4454 // CHECK3:       omp.inner.for.end:
4455 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4456 // CHECK3:       omp.loop.exit:
4457 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4458 // CHECK3-NEXT:    ret void
4459 //
4460 //
4461 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
4462 // CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
4463 // CHECK3-NEXT:  entry:
4464 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4465 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
4466 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4467 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
4468 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
4469 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4470 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
4471 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
4472 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
4473 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
4474 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4475 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
4476 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4477 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
4478 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
4479 // CHECK3-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
4480 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
4481 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
4482 // CHECK3-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
4483 // CHECK3-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
4484 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
4485 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4486 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
4487 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
4488 // CHECK3-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
4489 // CHECK3-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
4490 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
4491 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
4492 // CHECK3-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
4493 // CHECK3-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
4494 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
4495 // CHECK3-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
4496 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
4497 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4498 // CHECK3-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
4499 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
4500 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
4501 // CHECK3-NEXT:    ret void
4502 //
4503 //
4504 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7
4505 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
4506 // CHECK3-NEXT:  entry:
4507 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4508 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4509 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4510 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
4511 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4512 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
4513 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
4514 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4515 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
4516 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
4517 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
4518 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
4519 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4520 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i8, align 1
4521 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4522 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4523 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4524 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4525 // CHECK3-NEXT:    [[IT:%.*]] = alloca i8, align 1
4526 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4527 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4528 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4529 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
4530 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
4531 // CHECK3-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
4532 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
4533 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
4534 // CHECK3-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
4535 // CHECK3-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
4536 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
4537 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4538 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
4539 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
4540 // CHECK3-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
4541 // CHECK3-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
4542 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
4543 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
4544 // CHECK3-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
4545 // CHECK3-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
4546 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4547 // CHECK3-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
4548 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4549 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4550 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4551 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4552 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
4553 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
4554 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
4555 // CHECK3:       omp.dispatch.cond:
4556 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4557 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
4558 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4559 // CHECK3:       cond.true:
4560 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4561 // CHECK3:       cond.false:
4562 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4563 // CHECK3-NEXT:    br label [[COND_END]]
4564 // CHECK3:       cond.end:
4565 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
4566 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4567 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4568 // CHECK3-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
4569 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4570 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4571 // CHECK3-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
4572 // CHECK3-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
4573 // CHECK3:       omp.dispatch.body:
4574 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4575 // CHECK3:       omp.inner.for.cond:
4576 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4577 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4578 // CHECK3-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
4579 // CHECK3-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4580 // CHECK3:       omp.inner.for.body:
4581 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4582 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
4583 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
4584 // CHECK3-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
4585 // CHECK3-NEXT:    store i8 [[CONV]], i8* [[IT]], align 1
4586 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
4587 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
4588 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
4589 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
4590 // CHECK3-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
4591 // CHECK3-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
4592 // CHECK3-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
4593 // CHECK3-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
4594 // CHECK3-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4
4595 // CHECK3-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
4596 // CHECK3-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
4597 // CHECK3-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
4598 // CHECK3-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
4599 // CHECK3-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
4600 // CHECK3-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4
4601 // CHECK3-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
4602 // CHECK3-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
4603 // CHECK3-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
4604 // CHECK3-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
4605 // CHECK3-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8
4606 // CHECK3-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
4607 // CHECK3-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
4608 // CHECK3-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
4609 // CHECK3-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
4610 // CHECK3-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
4611 // CHECK3-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8
4612 // CHECK3-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
4613 // CHECK3-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4
4614 // CHECK3-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
4615 // CHECK3-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4
4616 // CHECK3-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
4617 // CHECK3-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
4618 // CHECK3-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
4619 // CHECK3-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
4620 // CHECK3-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
4621 // CHECK3-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4
4622 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4623 // CHECK3:       omp.body.continue:
4624 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4625 // CHECK3:       omp.inner.for.inc:
4626 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4627 // CHECK3-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
4628 // CHECK3-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
4629 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
4630 // CHECK3:       omp.inner.for.end:
4631 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
4632 // CHECK3:       omp.dispatch.inc:
4633 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4634 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4635 // CHECK3-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
4636 // CHECK3-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
4637 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4638 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4639 // CHECK3-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
4640 // CHECK3-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
4641 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
4642 // CHECK3:       omp.dispatch.end:
4643 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
4644 // CHECK3-NEXT:    ret void
4645 //
4646 //
4647 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari
4648 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
4649 // CHECK3-NEXT:  entry:
4650 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4651 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
4652 // CHECK3-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
4653 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4654 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
4655 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4656 // CHECK3-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
4657 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
4658 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
4659 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
4660 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
4661 // CHECK3-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
4662 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
4663 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
4664 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
4665 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
4666 // CHECK3-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
4667 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
4668 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
4669 // CHECK3-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
4670 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
4671 // CHECK3-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
4672 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
4673 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
4674 // CHECK3-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
4675 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
4676 // CHECK3-NEXT:    ret i32 [[TMP8]]
4677 //
4678 //
4679 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
4680 // CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
4681 // CHECK3-NEXT:  entry:
4682 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
4683 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4684 // CHECK3-NEXT:    [[B:%.*]] = alloca i32, align 4
4685 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
4686 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
4687 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
4688 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
4689 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
4690 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
4691 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
4692 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
4693 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4694 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
4695 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4696 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
4697 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
4698 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
4699 // CHECK3-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
4700 // CHECK3-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
4701 // CHECK3-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
4702 // CHECK3-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
4703 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
4704 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
4705 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
4706 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
4707 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
4708 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
4709 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4710 // CHECK3:       omp_if.then:
4711 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
4712 // CHECK3-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
4713 // CHECK3-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
4714 // CHECK3-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
4715 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4716 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
4717 // CHECK3-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
4718 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4719 // CHECK3-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
4720 // CHECK3-NEXT:    store double* [[A]], double** [[TMP13]], align 4
4721 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
4722 // CHECK3-NEXT:    store i64 8, i64* [[TMP14]], align 4
4723 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4724 // CHECK3-NEXT:    store i8* null, i8** [[TMP15]], align 4
4725 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4726 // CHECK3-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
4727 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP17]], align 4
4728 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4729 // CHECK3-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
4730 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP19]], align 4
4731 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
4732 // CHECK3-NEXT:    store i64 4, i64* [[TMP20]], align 4
4733 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4734 // CHECK3-NEXT:    store i8* null, i8** [[TMP21]], align 4
4735 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4736 // CHECK3-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
4737 // CHECK3-NEXT:    store i32 2, i32* [[TMP23]], align 4
4738 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4739 // CHECK3-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
4740 // CHECK3-NEXT:    store i32 2, i32* [[TMP25]], align 4
4741 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
4742 // CHECK3-NEXT:    store i64 4, i64* [[TMP26]], align 4
4743 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4744 // CHECK3-NEXT:    store i8* null, i8** [[TMP27]], align 4
4745 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
4746 // CHECK3-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
4747 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP29]], align 4
4748 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
4749 // CHECK3-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
4750 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP31]], align 4
4751 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
4752 // CHECK3-NEXT:    store i64 4, i64* [[TMP32]], align 4
4753 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
4754 // CHECK3-NEXT:    store i8* null, i8** [[TMP33]], align 4
4755 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
4756 // CHECK3-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
4757 // CHECK3-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 4
4758 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
4759 // CHECK3-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
4760 // CHECK3-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 4
4761 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
4762 // CHECK3-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 4
4763 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
4764 // CHECK3-NEXT:    store i8* null, i8** [[TMP39]], align 4
4765 // CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4766 // CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4767 // CHECK3-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
4768 // CHECK3-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
4769 // CHECK3-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
4770 // CHECK3-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4771 // CHECK3:       omp_offload.failed:
4772 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
4773 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4774 // CHECK3:       omp_offload.cont:
4775 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
4776 // CHECK3:       omp_if.else:
4777 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
4778 // CHECK3-NEXT:    br label [[OMP_IF_END]]
4779 // CHECK3:       omp_if.end:
4780 // CHECK3-NEXT:    [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
4781 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
4782 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
4783 // CHECK3-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
4784 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP46]] to i32
4785 // CHECK3-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
4786 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
4787 // CHECK3-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
4788 // CHECK3-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
4789 // CHECK3-NEXT:    ret i32 [[ADD3]]
4790 //
4791 //
4792 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
4793 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
4794 // CHECK3-NEXT:  entry:
4795 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4796 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
4797 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
4798 // CHECK3-NEXT:    [[AAA:%.*]] = alloca i8, align 1
4799 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
4800 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4801 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4802 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
4803 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
4804 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
4805 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
4806 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4807 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
4808 // CHECK3-NEXT:    store i16 0, i16* [[AA]], align 2
4809 // CHECK3-NEXT:    store i8 0, i8* [[AAA]], align 1
4810 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4811 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4812 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4813 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
4814 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4815 // CHECK3-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
4816 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4817 // CHECK3-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
4818 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
4819 // CHECK3-NEXT:    store i8 [[TMP4]], i8* [[CONV1]], align 1
4820 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
4821 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
4822 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
4823 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4824 // CHECK3:       omp_if.then:
4825 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4826 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
4827 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
4828 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4829 // CHECK3-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
4830 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
4831 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4832 // CHECK3-NEXT:    store i8* null, i8** [[TMP11]], align 4
4833 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4834 // CHECK3-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
4835 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
4836 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4837 // CHECK3-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
4838 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
4839 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4840 // CHECK3-NEXT:    store i8* null, i8** [[TMP16]], align 4
4841 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4842 // CHECK3-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
4843 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP18]], align 4
4844 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4845 // CHECK3-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
4846 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
4847 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4848 // CHECK3-NEXT:    store i8* null, i8** [[TMP21]], align 4
4849 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
4850 // CHECK3-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
4851 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
4852 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
4853 // CHECK3-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
4854 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
4855 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
4856 // CHECK3-NEXT:    store i8* null, i8** [[TMP26]], align 4
4857 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4858 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4859 // CHECK3-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
4860 // CHECK3-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
4861 // CHECK3-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4862 // CHECK3:       omp_offload.failed:
4863 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
4864 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4865 // CHECK3:       omp_offload.cont:
4866 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
4867 // CHECK3:       omp_if.else:
4868 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
4869 // CHECK3-NEXT:    br label [[OMP_IF_END]]
4870 // CHECK3:       omp_if.end:
4871 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
4872 // CHECK3-NEXT:    ret i32 [[TMP31]]
4873 //
4874 //
4875 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
4876 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
4877 // CHECK3-NEXT:  entry:
4878 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4879 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
4880 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
4881 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
4882 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4883 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4884 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
4885 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
4886 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
4887 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4888 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
4889 // CHECK3-NEXT:    store i16 0, i16* [[AA]], align 2
4890 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4891 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4892 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4893 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
4894 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4895 // CHECK3-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
4896 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4897 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
4898 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
4899 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4900 // CHECK3:       omp_if.then:
4901 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4902 // CHECK3-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
4903 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
4904 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4905 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
4906 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
4907 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4908 // CHECK3-NEXT:    store i8* null, i8** [[TMP9]], align 4
4909 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4910 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
4911 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
4912 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4913 // CHECK3-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
4914 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
4915 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4916 // CHECK3-NEXT:    store i8* null, i8** [[TMP14]], align 4
4917 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4918 // CHECK3-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
4919 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
4920 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4921 // CHECK3-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
4922 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
4923 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4924 // CHECK3-NEXT:    store i8* null, i8** [[TMP19]], align 4
4925 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4926 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4927 // CHECK3-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
4928 // CHECK3-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
4929 // CHECK3-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4930 // CHECK3:       omp_offload.failed:
4931 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
4932 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4933 // CHECK3:       omp_offload.cont:
4934 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
4935 // CHECK3:       omp_if.else:
4936 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
4937 // CHECK3-NEXT:    br label [[OMP_IF_END]]
4938 // CHECK3:       omp_if.end:
4939 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
4940 // CHECK3-NEXT:    ret i32 [[TMP24]]
4941 //
4942 //
4943 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
4944 // CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
4945 // CHECK3-NEXT:  entry:
4946 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
4947 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
4948 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4949 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4950 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
4951 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
4952 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
4953 // CHECK3-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
4954 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
4955 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
4956 // CHECK3-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
4957 // CHECK3-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
4958 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
4959 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
4960 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
4961 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
4962 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
4963 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
4964 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
4965 // CHECK3-NEXT:    ret void
4966 //
4967 //
4968 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9
4969 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
4970 // CHECK3-NEXT:  entry:
4971 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4972 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4973 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
4974 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
4975 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4976 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4977 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
4978 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
4979 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i64, align 4
4980 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
4981 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
4982 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
4983 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4984 // CHECK3-NEXT:    [[IT:%.*]] = alloca i64, align 8
4985 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4986 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4987 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
4988 // CHECK3-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
4989 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
4990 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
4991 // CHECK3-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
4992 // CHECK3-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
4993 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
4994 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
4995 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
4996 // CHECK3-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
4997 // CHECK3-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
4998 // CHECK3-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
4999 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5000 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5001 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
5002 // CHECK3-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
5003 // CHECK3-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5004 // CHECK3-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
5005 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5006 // CHECK3:       cond.true:
5007 // CHECK3-NEXT:    br label [[COND_END:%.*]]
5008 // CHECK3:       cond.false:
5009 // CHECK3-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5010 // CHECK3-NEXT:    br label [[COND_END]]
5011 // CHECK3:       cond.end:
5012 // CHECK3-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
5013 // CHECK3-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
5014 // CHECK3-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
5015 // CHECK3-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
5016 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5017 // CHECK3:       omp.inner.for.cond:
5018 // CHECK3-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
5019 // CHECK3-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5020 // CHECK3-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
5021 // CHECK3-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5022 // CHECK3:       omp.inner.for.body:
5023 // CHECK3-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
5024 // CHECK3-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
5025 // CHECK3-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
5026 // CHECK3-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
5027 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
5028 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
5029 // CHECK3-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
5030 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
5031 // CHECK3-NEXT:    store double [[ADD]], double* [[A]], align 4
5032 // CHECK3-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
5033 // CHECK3-NEXT:    [[TMP13:%.*]] = load double, double* [[A4]], align 4
5034 // CHECK3-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
5035 // CHECK3-NEXT:    store double [[INC]], double* [[A4]], align 4
5036 // CHECK3-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
5037 // CHECK3-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
5038 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
5039 // CHECK3-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
5040 // CHECK3-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
5041 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5042 // CHECK3:       omp.body.continue:
5043 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5044 // CHECK3:       omp.inner.for.inc:
5045 // CHECK3-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
5046 // CHECK3-NEXT:    [[ADD7:%.*]] = add i64 [[TMP15]], 1
5047 // CHECK3-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
5048 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
5049 // CHECK3:       omp.inner.for.end:
5050 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5051 // CHECK3:       omp.loop.exit:
5052 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
5053 // CHECK3-NEXT:    ret void
5054 //
5055 //
5056 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
5057 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5058 // CHECK3-NEXT:  entry:
5059 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5060 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5061 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
5062 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5063 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5064 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5065 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
5066 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5067 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5068 // CHECK3-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
5069 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5070 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5071 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
5072 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5073 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5074 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
5075 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
5076 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
5077 // CHECK3-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5078 // CHECK3-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
5079 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5080 // CHECK3-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
5081 // CHECK3-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
5082 // CHECK3-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
5083 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
5084 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
5085 // CHECK3-NEXT:    ret void
5086 //
5087 //
5088 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11
5089 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5090 // CHECK3-NEXT:  entry:
5091 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5092 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5093 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5094 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5095 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
5096 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5097 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5098 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5099 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5100 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5101 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5102 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5103 // CHECK3-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
5104 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5105 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5106 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
5107 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5108 // CHECK3-NEXT:    ret void
5109 //
5110 //
5111 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
5112 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5113 // CHECK3-NEXT:  entry:
5114 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5115 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5116 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5117 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5118 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5119 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5120 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5121 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5122 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5123 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5124 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5125 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
5126 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
5127 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
5128 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5129 // CHECK3-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
5130 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5131 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
5132 // CHECK3-NEXT:    ret void
5133 //
5134 //
5135 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14
5136 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5137 // CHECK3-NEXT:  entry:
5138 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5139 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5140 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5141 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5142 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5143 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
5144 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i64, align 4
5145 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
5146 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
5147 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
5148 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5149 // CHECK3-NEXT:    [[I:%.*]] = alloca i64, align 8
5150 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5151 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5152 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5153 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5154 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5155 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5156 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5157 // CHECK3-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
5158 // CHECK3-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
5159 // CHECK3-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
5160 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5161 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5162 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
5163 // CHECK3-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
5164 // CHECK3-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5165 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
5166 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5167 // CHECK3:       cond.true:
5168 // CHECK3-NEXT:    br label [[COND_END:%.*]]
5169 // CHECK3:       cond.false:
5170 // CHECK3-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5171 // CHECK3-NEXT:    br label [[COND_END]]
5172 // CHECK3:       cond.end:
5173 // CHECK3-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
5174 // CHECK3-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
5175 // CHECK3-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
5176 // CHECK3-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
5177 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5178 // CHECK3:       omp.inner.for.cond:
5179 // CHECK3-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
5180 // CHECK3-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5181 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
5182 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5183 // CHECK3:       omp.inner.for.body:
5184 // CHECK3-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
5185 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
5186 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
5187 // CHECK3-NEXT:    store i64 [[ADD]], i64* [[I]], align 8
5188 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
5189 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
5190 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
5191 // CHECK3-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
5192 // CHECK3-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
5193 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
5194 // CHECK3-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
5195 // CHECK3-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
5196 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
5197 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
5198 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
5199 // CHECK3-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
5200 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5201 // CHECK3:       omp.body.continue:
5202 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5203 // CHECK3:       omp.inner.for.inc:
5204 // CHECK3-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
5205 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
5206 // CHECK3-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
5207 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
5208 // CHECK3:       omp.inner.for.end:
5209 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5210 // CHECK3:       omp.loop.exit:
5211 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
5212 // CHECK3-NEXT:    ret void
5213 //
5214 //
5215 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
5216 // CHECK3-SAME: () #[[ATTR5]] {
5217 // CHECK3-NEXT:  entry:
5218 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
5219 // CHECK3-NEXT:    ret void
5220 //
5221 //
5222 // CHECK4-LABEL: define {{[^@]+}}@_Z7get_valv
5223 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] {
5224 // CHECK4-NEXT:  entry:
5225 // CHECK4-NEXT:    ret i64 0
5226 //
5227 //
5228 // CHECK4-LABEL: define {{[^@]+}}@_Z3fooi
5229 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
5230 // CHECK4-NEXT:  entry:
5231 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5232 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
5233 // CHECK4-NEXT:    [[AA:%.*]] = alloca i16, align 2
5234 // CHECK4-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
5235 // CHECK4-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
5236 // CHECK4-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
5237 // CHECK4-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
5238 // CHECK4-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
5239 // CHECK4-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
5240 // CHECK4-NEXT:    [[K:%.*]] = alloca i64, align 8
5241 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5242 // CHECK4-NEXT:    [[LIN:%.*]] = alloca i32, align 4
5243 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5244 // CHECK4-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
5245 // CHECK4-NEXT:    [[A_CASTED2:%.*]] = alloca i32, align 4
5246 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
5247 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
5248 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
5249 // CHECK4-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
5250 // CHECK4-NEXT:    [[A_CASTED3:%.*]] = alloca i32, align 4
5251 // CHECK4-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
5252 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4
5253 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4
5254 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4
5255 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
5256 // CHECK4-NEXT:    [[A_CASTED11:%.*]] = alloca i32, align 4
5257 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
5258 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4
5259 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4
5260 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4
5261 // CHECK4-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
5262 // CHECK4-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
5263 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5264 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
5265 // CHECK4-NEXT:    store i16 0, i16* [[AA]], align 2
5266 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
5267 // CHECK4-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
5268 // CHECK4-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
5269 // CHECK4-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
5270 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
5271 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
5272 // CHECK4-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
5273 // CHECK4-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
5274 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
5275 // CHECK4-NEXT:    [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
5276 // CHECK4-NEXT:    [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
5277 // CHECK4-NEXT:    br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5278 // CHECK4:       omp_offload.failed:
5279 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]]
5280 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5281 // CHECK4:       omp_offload.cont:
5282 // CHECK4-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
5283 // CHECK4-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
5284 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
5285 // CHECK4-NEXT:    store i32 [[TMP7]], i32* [[A_CASTED]], align 4
5286 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4
5287 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR3]]
5288 // CHECK4-NEXT:    store i32 12, i32* [[LIN]], align 4
5289 // CHECK4-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
5290 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5291 // CHECK4-NEXT:    store i16 [[TMP9]], i16* [[CONV]], align 2
5292 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5293 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4
5294 // CHECK4-NEXT:    store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4
5295 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
5296 // CHECK4-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4
5297 // CHECK4-NEXT:    store i32 [[TMP13]], i32* [[A_CASTED2]], align 4
5298 // CHECK4-NEXT:    [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4
5299 // CHECK4-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5300 // CHECK4-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
5301 // CHECK4-NEXT:    store i32 [[TMP10]], i32* [[TMP16]], align 4
5302 // CHECK4-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5303 // CHECK4-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
5304 // CHECK4-NEXT:    store i32 [[TMP10]], i32* [[TMP18]], align 4
5305 // CHECK4-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5306 // CHECK4-NEXT:    store i8* null, i8** [[TMP19]], align 4
5307 // CHECK4-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5308 // CHECK4-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
5309 // CHECK4-NEXT:    store i32 [[TMP12]], i32* [[TMP21]], align 4
5310 // CHECK4-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5311 // CHECK4-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
5312 // CHECK4-NEXT:    store i32 [[TMP12]], i32* [[TMP23]], align 4
5313 // CHECK4-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
5314 // CHECK4-NEXT:    store i8* null, i8** [[TMP24]], align 4
5315 // CHECK4-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5316 // CHECK4-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
5317 // CHECK4-NEXT:    store i32 [[TMP14]], i32* [[TMP26]], align 4
5318 // CHECK4-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5319 // CHECK4-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
5320 // CHECK4-NEXT:    store i32 [[TMP14]], i32* [[TMP28]], align 4
5321 // CHECK4-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
5322 // CHECK4-NEXT:    store i8* null, i8** [[TMP29]], align 4
5323 // CHECK4-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5324 // CHECK4-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5325 // CHECK4-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
5326 // CHECK4-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
5327 // CHECK4-NEXT:    store i16 [[TMP33]], i16* [[TMP32]], align 4
5328 // CHECK4-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
5329 // CHECK4-NEXT:    [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4
5330 // CHECK4-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
5331 // CHECK4-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
5332 // CHECK4-NEXT:    [[TMP37:%.*]] = load i32, i32* [[A]], align 4
5333 // CHECK4-NEXT:    store i32 [[TMP37]], i32* [[TMP36]], align 4
5334 // CHECK4-NEXT:    [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
5335 // CHECK4-NEXT:    [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
5336 // CHECK4-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
5337 // CHECK4-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
5338 // CHECK4-NEXT:    [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4
5339 // CHECK4-NEXT:    [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
5340 // CHECK4-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false)
5341 // CHECK4-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
5342 // CHECK4-NEXT:    [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
5343 // CHECK4-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
5344 // CHECK4-NEXT:    [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8*
5345 // CHECK4-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
5346 // CHECK4-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
5347 // CHECK4-NEXT:    [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8*
5348 // CHECK4-NEXT:    [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8*
5349 // CHECK4-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false)
5350 // CHECK4-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
5351 // CHECK4-NEXT:    [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8*
5352 // CHECK4-NEXT:    [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8*
5353 // CHECK4-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false)
5354 // CHECK4-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
5355 // CHECK4-NEXT:    [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
5356 // CHECK4-NEXT:    store i16 [[TMP55]], i16* [[TMP54]], align 4
5357 // CHECK4-NEXT:    [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]])
5358 // CHECK4-NEXT:    [[TMP57:%.*]] = load i32, i32* [[A]], align 4
5359 // CHECK4-NEXT:    store i32 [[TMP57]], i32* [[A_CASTED3]], align 4
5360 // CHECK4-NEXT:    [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4
5361 // CHECK4-NEXT:    [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
5362 // CHECK4-NEXT:    [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
5363 // CHECK4-NEXT:    store i16 [[TMP59]], i16* [[CONV5]], align 2
5364 // CHECK4-NEXT:    [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
5365 // CHECK4-NEXT:    [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4
5366 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10
5367 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5368 // CHECK4:       omp_if.then:
5369 // CHECK4-NEXT:    [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
5370 // CHECK4-NEXT:    [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32*
5371 // CHECK4-NEXT:    store i32 [[TMP58]], i32* [[TMP63]], align 4
5372 // CHECK4-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
5373 // CHECK4-NEXT:    [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32*
5374 // CHECK4-NEXT:    store i32 [[TMP58]], i32* [[TMP65]], align 4
5375 // CHECK4-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
5376 // CHECK4-NEXT:    store i8* null, i8** [[TMP66]], align 4
5377 // CHECK4-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1
5378 // CHECK4-NEXT:    [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32*
5379 // CHECK4-NEXT:    store i32 [[TMP60]], i32* [[TMP68]], align 4
5380 // CHECK4-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1
5381 // CHECK4-NEXT:    [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32*
5382 // CHECK4-NEXT:    store i32 [[TMP60]], i32* [[TMP70]], align 4
5383 // CHECK4-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1
5384 // CHECK4-NEXT:    store i8* null, i8** [[TMP71]], align 4
5385 // CHECK4-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
5386 // CHECK4-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
5387 // CHECK4-NEXT:    [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
5388 // CHECK4-NEXT:    [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0
5389 // CHECK4-NEXT:    br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
5390 // CHECK4:       omp_offload.failed9:
5391 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR3]]
5392 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT10]]
5393 // CHECK4:       omp_offload.cont10:
5394 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
5395 // CHECK4:       omp_if.else:
5396 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR3]]
5397 // CHECK4-NEXT:    br label [[OMP_IF_END]]
5398 // CHECK4:       omp_if.end:
5399 // CHECK4-NEXT:    [[TMP76:%.*]] = load i32, i32* [[A]], align 4
5400 // CHECK4-NEXT:    store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4
5401 // CHECK4-NEXT:    [[TMP77:%.*]] = load i32, i32* [[A]], align 4
5402 // CHECK4-NEXT:    store i32 [[TMP77]], i32* [[A_CASTED11]], align 4
5403 // CHECK4-NEXT:    [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4
5404 // CHECK4-NEXT:    [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5405 // CHECK4-NEXT:    store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
5406 // CHECK4-NEXT:    [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
5407 // CHECK4-NEXT:    [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4
5408 // CHECK4-NEXT:    [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20
5409 // CHECK4-NEXT:    br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]]
5410 // CHECK4:       omp_if.then13:
5411 // CHECK4-NEXT:    [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4
5412 // CHECK4-NEXT:    [[TMP83:%.*]] = sext i32 [[TMP82]] to i64
5413 // CHECK4-NEXT:    [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]]
5414 // CHECK4-NEXT:    [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8
5415 // CHECK4-NEXT:    [[TMP86:%.*]] = sext i32 [[TMP85]] to i64
5416 // CHECK4-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
5417 // CHECK4-NEXT:    [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32*
5418 // CHECK4-NEXT:    store i32 [[TMP78]], i32* [[TMP88]], align 4
5419 // CHECK4-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
5420 // CHECK4-NEXT:    [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32*
5421 // CHECK4-NEXT:    store i32 [[TMP78]], i32* [[TMP90]], align 4
5422 // CHECK4-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
5423 // CHECK4-NEXT:    store i64 4, i64* [[TMP91]], align 4
5424 // CHECK4-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
5425 // CHECK4-NEXT:    store i8* null, i8** [[TMP92]], align 4
5426 // CHECK4-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
5427 // CHECK4-NEXT:    [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]**
5428 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4
5429 // CHECK4-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
5430 // CHECK4-NEXT:    [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]**
5431 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4
5432 // CHECK4-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
5433 // CHECK4-NEXT:    store i64 40, i64* [[TMP97]], align 4
5434 // CHECK4-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
5435 // CHECK4-NEXT:    store i8* null, i8** [[TMP98]], align 4
5436 // CHECK4-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
5437 // CHECK4-NEXT:    [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i32*
5438 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP100]], align 4
5439 // CHECK4-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
5440 // CHECK4-NEXT:    [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i32*
5441 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP102]], align 4
5442 // CHECK4-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
5443 // CHECK4-NEXT:    store i64 4, i64* [[TMP103]], align 4
5444 // CHECK4-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
5445 // CHECK4-NEXT:    store i8* null, i8** [[TMP104]], align 4
5446 // CHECK4-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
5447 // CHECK4-NEXT:    [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float**
5448 // CHECK4-NEXT:    store float* [[VLA]], float** [[TMP106]], align 4
5449 // CHECK4-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
5450 // CHECK4-NEXT:    [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float**
5451 // CHECK4-NEXT:    store float* [[VLA]], float** [[TMP108]], align 4
5452 // CHECK4-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
5453 // CHECK4-NEXT:    store i64 [[TMP83]], i64* [[TMP109]], align 4
5454 // CHECK4-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
5455 // CHECK4-NEXT:    store i8* null, i8** [[TMP110]], align 4
5456 // CHECK4-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
5457 // CHECK4-NEXT:    [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]**
5458 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4
5459 // CHECK4-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
5460 // CHECK4-NEXT:    [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]**
5461 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 4
5462 // CHECK4-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
5463 // CHECK4-NEXT:    store i64 400, i64* [[TMP115]], align 4
5464 // CHECK4-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
5465 // CHECK4-NEXT:    store i8* null, i8** [[TMP116]], align 4
5466 // CHECK4-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
5467 // CHECK4-NEXT:    [[TMP118:%.*]] = bitcast i8** [[TMP117]] to i32*
5468 // CHECK4-NEXT:    store i32 5, i32* [[TMP118]], align 4
5469 // CHECK4-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
5470 // CHECK4-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32*
5471 // CHECK4-NEXT:    store i32 5, i32* [[TMP120]], align 4
5472 // CHECK4-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
5473 // CHECK4-NEXT:    store i64 4, i64* [[TMP121]], align 4
5474 // CHECK4-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
5475 // CHECK4-NEXT:    store i8* null, i8** [[TMP122]], align 4
5476 // CHECK4-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
5477 // CHECK4-NEXT:    [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32*
5478 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP124]], align 4
5479 // CHECK4-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
5480 // CHECK4-NEXT:    [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32*
5481 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP126]], align 4
5482 // CHECK4-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
5483 // CHECK4-NEXT:    store i64 4, i64* [[TMP127]], align 4
5484 // CHECK4-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
5485 // CHECK4-NEXT:    store i8* null, i8** [[TMP128]], align 4
5486 // CHECK4-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
5487 // CHECK4-NEXT:    [[TMP130:%.*]] = bitcast i8** [[TMP129]] to double**
5488 // CHECK4-NEXT:    store double* [[VLA1]], double** [[TMP130]], align 4
5489 // CHECK4-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
5490 // CHECK4-NEXT:    [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double**
5491 // CHECK4-NEXT:    store double* [[VLA1]], double** [[TMP132]], align 4
5492 // CHECK4-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
5493 // CHECK4-NEXT:    store i64 [[TMP86]], i64* [[TMP133]], align 4
5494 // CHECK4-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
5495 // CHECK4-NEXT:    store i8* null, i8** [[TMP134]], align 4
5496 // CHECK4-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
5497 // CHECK4-NEXT:    [[TMP136:%.*]] = bitcast i8** [[TMP135]] to %struct.TT**
5498 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP136]], align 4
5499 // CHECK4-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
5500 // CHECK4-NEXT:    [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT**
5501 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 4
5502 // CHECK4-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
5503 // CHECK4-NEXT:    store i64 12, i64* [[TMP139]], align 4
5504 // CHECK4-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
5505 // CHECK4-NEXT:    store i8* null, i8** [[TMP140]], align 4
5506 // CHECK4-NEXT:    [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
5507 // CHECK4-NEXT:    [[TMP142:%.*]] = bitcast i8** [[TMP141]] to i32*
5508 // CHECK4-NEXT:    store i32 [[TMP80]], i32* [[TMP142]], align 4
5509 // CHECK4-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
5510 // CHECK4-NEXT:    [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i32*
5511 // CHECK4-NEXT:    store i32 [[TMP80]], i32* [[TMP144]], align 4
5512 // CHECK4-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
5513 // CHECK4-NEXT:    store i64 4, i64* [[TMP145]], align 4
5514 // CHECK4-NEXT:    [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
5515 // CHECK4-NEXT:    store i8* null, i8** [[TMP146]], align 4
5516 // CHECK4-NEXT:    [[TMP147:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
5517 // CHECK4-NEXT:    [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
5518 // CHECK4-NEXT:    [[TMP149:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
5519 // CHECK4-NEXT:    [[TMP150:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP147]], i8** [[TMP148]], i64* [[TMP149]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
5520 // CHECK4-NEXT:    [[TMP151:%.*]] = icmp ne i32 [[TMP150]], 0
5521 // CHECK4-NEXT:    br i1 [[TMP151]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
5522 // CHECK4:       omp_offload.failed17:
5523 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR3]]
5524 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT18]]
5525 // CHECK4:       omp_offload.cont18:
5526 // CHECK4-NEXT:    br label [[OMP_IF_END20:%.*]]
5527 // CHECK4:       omp_if.else19:
5528 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR3]]
5529 // CHECK4-NEXT:    br label [[OMP_IF_END20]]
5530 // CHECK4:       omp_if.end20:
5531 // CHECK4-NEXT:    [[TMP152:%.*]] = load i32, i32* [[A]], align 4
5532 // CHECK4-NEXT:    [[TMP153:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
5533 // CHECK4-NEXT:    call void @llvm.stackrestore(i8* [[TMP153]])
5534 // CHECK4-NEXT:    ret i32 [[TMP152]]
5535 //
5536 //
5537 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
5538 // CHECK4-SAME: () #[[ATTR2:[0-9]+]] {
5539 // CHECK4-NEXT:  entry:
5540 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
5541 // CHECK4-NEXT:    ret void
5542 //
5543 //
5544 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
5545 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
5546 // CHECK4-NEXT:  entry:
5547 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5548 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5549 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5550 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5551 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5552 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5553 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5554 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5555 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
5556 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5557 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5558 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5559 // CHECK4-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
5560 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5561 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5562 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5563 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
5564 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5565 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5566 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
5567 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5568 // CHECK4:       cond.true:
5569 // CHECK4-NEXT:    br label [[COND_END:%.*]]
5570 // CHECK4:       cond.false:
5571 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5572 // CHECK4-NEXT:    br label [[COND_END]]
5573 // CHECK4:       cond.end:
5574 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
5575 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5576 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5577 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
5578 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5579 // CHECK4:       omp.inner.for.cond:
5580 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5581 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5582 // CHECK4-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
5583 // CHECK4-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5584 // CHECK4:       omp.inner.for.body:
5585 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5586 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
5587 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
5588 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
5589 // CHECK4-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
5590 // CHECK4-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
5591 // CHECK4-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
5592 // CHECK4:       .cancel.exit:
5593 // CHECK4-NEXT:    br label [[CANCEL_EXIT:%.*]]
5594 // CHECK4:       .cancel.continue:
5595 // CHECK4-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
5596 // CHECK4-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
5597 // CHECK4-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
5598 // CHECK4:       .cancel.exit2:
5599 // CHECK4-NEXT:    br label [[CANCEL_EXIT]]
5600 // CHECK4:       .cancel.continue3:
5601 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5602 // CHECK4:       omp.body.continue:
5603 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5604 // CHECK4:       omp.inner.for.inc:
5605 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5606 // CHECK4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
5607 // CHECK4-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
5608 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]]
5609 // CHECK4:       omp.inner.for.end:
5610 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5611 // CHECK4:       omp.loop.exit:
5612 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
5613 // CHECK4-NEXT:    br label [[CANCEL_CONT:%.*]]
5614 // CHECK4:       cancel.cont:
5615 // CHECK4-NEXT:    ret void
5616 // CHECK4:       cancel.exit:
5617 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
5618 // CHECK4-NEXT:    br label [[CANCEL_CONT]]
5619 //
5620 //
5621 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
5622 // CHECK4-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {
5623 // CHECK4-NEXT:  entry:
5624 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5625 // CHECK4-NEXT:    [[K_ADDR:%.*]] = alloca i64*, align 4
5626 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5627 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5628 // CHECK4-NEXT:    store i64* [[K]], i64** [[K_ADDR]], align 4
5629 // CHECK4-NEXT:    [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
5630 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5631 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
5632 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
5633 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]])
5634 // CHECK4-NEXT:    ret void
5635 //
5636 //
5637 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1
5638 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {
5639 // CHECK4-NEXT:  entry:
5640 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5641 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5642 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5643 // CHECK4-NEXT:    [[K_ADDR:%.*]] = alloca i64*, align 4
5644 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5645 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5646 // CHECK4-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
5647 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5648 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5649 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5650 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5651 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
5652 // CHECK4-NEXT:    [[K1:%.*]] = alloca i64, align 8
5653 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5654 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5655 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5656 // CHECK4-NEXT:    store i64* [[K]], i64** [[K_ADDR]], align 4
5657 // CHECK4-NEXT:    [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
5658 // CHECK4-NEXT:    [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8
5659 // CHECK4-NEXT:    store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8
5660 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5661 // CHECK4-NEXT:    store i32 8, i32* [[DOTOMP_UB]], align 4
5662 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5663 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5664 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5665 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
5666 // CHECK4-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
5667 // CHECK4-NEXT:    call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1)
5668 // CHECK4-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
5669 // CHECK4:       omp.dispatch.cond:
5670 // CHECK4-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
5671 // CHECK4-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
5672 // CHECK4-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
5673 // CHECK4:       omp.dispatch.body:
5674 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5675 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
5676 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5677 // CHECK4:       omp.inner.for.cond:
5678 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
5679 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
5680 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
5681 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5682 // CHECK4:       omp.inner.for.body:
5683 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
5684 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
5685 // CHECK4-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
5686 // CHECK4-NEXT:    store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12
5687 // CHECK4-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12
5688 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
5689 // CHECK4-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
5690 // CHECK4-NEXT:    [[CONV:%.*]] = sext i32 [[MUL2]] to i64
5691 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
5692 // CHECK4-NEXT:    store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
5693 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12
5694 // CHECK4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
5695 // CHECK4-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !12
5696 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5697 // CHECK4:       omp.body.continue:
5698 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5699 // CHECK4:       omp.inner.for.inc:
5700 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
5701 // CHECK4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
5702 // CHECK4-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
5703 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
5704 // CHECK4:       omp.inner.for.end:
5705 // CHECK4-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
5706 // CHECK4:       omp.dispatch.inc:
5707 // CHECK4-NEXT:    br label [[OMP_DISPATCH_COND]]
5708 // CHECK4:       omp.dispatch.end:
5709 // CHECK4-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5710 // CHECK4-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
5711 // CHECK4-NEXT:    br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
5712 // CHECK4:       .omp.linear.pu:
5713 // CHECK4-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
5714 // CHECK4-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP15]], 27
5715 // CHECK4-NEXT:    store i64 [[ADD5]], i64* [[TMP0]], align 8
5716 // CHECK4-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
5717 // CHECK4:       .omp.linear.pu.done:
5718 // CHECK4-NEXT:    ret void
5719 //
5720 //
5721 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
5722 // CHECK4-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
5723 // CHECK4-NEXT:  entry:
5724 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5725 // CHECK4-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
5726 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5727 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5728 // CHECK4-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
5729 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5730 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5731 // CHECK4-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
5732 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5733 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5734 // CHECK4-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
5735 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5736 // CHECK4-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
5737 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5738 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
5739 // CHECK4-NEXT:    store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
5740 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
5741 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
5742 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[A_CASTED]], align 4
5743 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
5744 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
5745 // CHECK4-NEXT:    ret void
5746 //
5747 //
5748 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2
5749 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
5750 // CHECK4-NEXT:  entry:
5751 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5752 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5753 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5754 // CHECK4-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
5755 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5756 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
5757 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i64, align 4
5758 // CHECK4-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
5759 // CHECK4-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
5760 // CHECK4-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
5761 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
5762 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
5763 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
5764 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5765 // CHECK4-NEXT:    [[IT:%.*]] = alloca i64, align 8
5766 // CHECK4-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
5767 // CHECK4-NEXT:    [[A3:%.*]] = alloca i32, align 4
5768 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5769 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5770 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5771 // CHECK4-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
5772 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5773 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5774 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
5775 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
5776 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5777 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
5778 // CHECK4-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
5779 // CHECK4-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
5780 // CHECK4-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
5781 // CHECK4-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
5782 // CHECK4-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
5783 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5784 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5785 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
5786 // CHECK4-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
5787 // CHECK4-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
5788 // CHECK4-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5789 // CHECK4-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
5790 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5791 // CHECK4:       cond.true:
5792 // CHECK4-NEXT:    br label [[COND_END:%.*]]
5793 // CHECK4:       cond.false:
5794 // CHECK4-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5795 // CHECK4-NEXT:    br label [[COND_END]]
5796 // CHECK4:       cond.end:
5797 // CHECK4-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
5798 // CHECK4-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
5799 // CHECK4-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
5800 // CHECK4-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
5801 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5802 // CHECK4:       omp.inner.for.cond:
5803 // CHECK4-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
5804 // CHECK4-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5805 // CHECK4-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
5806 // CHECK4-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5807 // CHECK4:       omp.inner.for.body:
5808 // CHECK4-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
5809 // CHECK4-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
5810 // CHECK4-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
5811 // CHECK4-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
5812 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
5813 // CHECK4-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
5814 // CHECK4-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
5815 // CHECK4-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
5816 // CHECK4-NEXT:    [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
5817 // CHECK4-NEXT:    [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
5818 // CHECK4-NEXT:    [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
5819 // CHECK4-NEXT:    store i32 [[CONV7]], i32* [[LIN2]], align 4
5820 // CHECK4-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
5821 // CHECK4-NEXT:    [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
5822 // CHECK4-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
5823 // CHECK4-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
5824 // CHECK4-NEXT:    [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
5825 // CHECK4-NEXT:    [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
5826 // CHECK4-NEXT:    [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
5827 // CHECK4-NEXT:    store i32 [[CONV11]], i32* [[A3]], align 4
5828 // CHECK4-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4
5829 // CHECK4-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
5830 // CHECK4-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
5831 // CHECK4-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
5832 // CHECK4-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4
5833 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5834 // CHECK4:       omp.body.continue:
5835 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5836 // CHECK4:       omp.inner.for.inc:
5837 // CHECK4-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
5838 // CHECK4-NEXT:    [[ADD15:%.*]] = add i64 [[TMP17]], 1
5839 // CHECK4-NEXT:    store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
5840 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]]
5841 // CHECK4:       omp.inner.for.end:
5842 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5843 // CHECK4:       omp.loop.exit:
5844 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
5845 // CHECK4-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5846 // CHECK4-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
5847 // CHECK4-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
5848 // CHECK4:       .omp.linear.pu:
5849 // CHECK4-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
5850 // CHECK4-NEXT:    [[CONV16:%.*]] = sext i32 [[TMP20]] to i64
5851 // CHECK4-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
5852 // CHECK4-NEXT:    [[MUL17:%.*]] = mul i64 4, [[TMP21]]
5853 // CHECK4-NEXT:    [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
5854 // CHECK4-NEXT:    [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
5855 // CHECK4-NEXT:    store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
5856 // CHECK4-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
5857 // CHECK4-NEXT:    [[CONV20:%.*]] = sext i32 [[TMP22]] to i64
5858 // CHECK4-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
5859 // CHECK4-NEXT:    [[MUL21:%.*]] = mul i64 4, [[TMP23]]
5860 // CHECK4-NEXT:    [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
5861 // CHECK4-NEXT:    [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
5862 // CHECK4-NEXT:    store i32 [[CONV23]], i32* [[A_ADDR]], align 4
5863 // CHECK4-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
5864 // CHECK4:       .omp.linear.pu.done:
5865 // CHECK4-NEXT:    ret void
5866 //
5867 //
5868 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map.
5869 // CHECK4-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
5870 // CHECK4-NEXT:  entry:
5871 // CHECK4-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
5872 // CHECK4-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 4
5873 // CHECK4-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
5874 // CHECK4-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
5875 // CHECK4-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
5876 // CHECK4-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
5877 // CHECK4-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
5878 // CHECK4-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
5879 // CHECK4-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
5880 // CHECK4-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
5881 // CHECK4-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
5882 // CHECK4-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
5883 // CHECK4-NEXT:    [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
5884 // CHECK4-NEXT:    store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
5885 // CHECK4-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
5886 // CHECK4-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
5887 // CHECK4-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
5888 // CHECK4-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
5889 // CHECK4-NEXT:    [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
5890 // CHECK4-NEXT:    store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
5891 // CHECK4-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
5892 // CHECK4-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
5893 // CHECK4-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 4
5894 // CHECK4-NEXT:    ret void
5895 //
5896 //
5897 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry.
5898 // CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
5899 // CHECK4-NEXT:  entry:
5900 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
5901 // CHECK4-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
5902 // CHECK4-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
5903 // CHECK4-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
5904 // CHECK4-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
5905 // CHECK4-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
5906 // CHECK4-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
5907 // CHECK4-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
5908 // CHECK4-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
5909 // CHECK4-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
5910 // CHECK4-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
5911 // CHECK4-NEXT:    [[LIN_CASTED_I:%.*]] = alloca i32, align 4
5912 // CHECK4-NEXT:    [[A_CASTED_I:%.*]] = alloca i32, align 4
5913 // CHECK4-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
5914 // CHECK4-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
5915 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
5916 // CHECK4-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
5917 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
5918 // CHECK4-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
5919 // CHECK4-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
5920 // CHECK4-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
5921 // CHECK4-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
5922 // CHECK4-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
5923 // CHECK4-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
5924 // CHECK4-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
5925 // CHECK4-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
5926 // CHECK4-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
5927 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
5928 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
5929 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
5930 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
5931 // CHECK4-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
5932 // CHECK4-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24
5933 // CHECK4-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24
5934 // CHECK4-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24
5935 // CHECK4-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24
5936 // CHECK4-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24
5937 // CHECK4-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24
5938 // CHECK4-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24
5939 // CHECK4-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24
5940 // CHECK4-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
5941 // CHECK4-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
5942 // CHECK4-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24
5943 // CHECK4-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24
5944 // CHECK4-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24
5945 // CHECK4-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24
5946 // CHECK4-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
5947 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
5948 // CHECK4-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
5949 // CHECK4-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
5950 // CHECK4-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
5951 // CHECK4-NEXT:    [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) #[[ATTR3]]
5952 // CHECK4-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
5953 // CHECK4-NEXT:    br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
5954 // CHECK4:       omp_offload.failed.i:
5955 // CHECK4-NEXT:    [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2
5956 // CHECK4-NEXT:    [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
5957 // CHECK4-NEXT:    store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24
5958 // CHECK4-NEXT:    [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !24
5959 // CHECK4-NEXT:    [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4
5960 // CHECK4-NEXT:    store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !24
5961 // CHECK4-NEXT:    [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !24
5962 // CHECK4-NEXT:    [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4
5963 // CHECK4-NEXT:    store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !24
5964 // CHECK4-NEXT:    [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !24
5965 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR3]]
5966 // CHECK4-NEXT:    br label [[DOTOMP_OUTLINED__3_EXIT]]
5967 // CHECK4:       .omp_outlined..3.exit:
5968 // CHECK4-NEXT:    ret i32 0
5969 //
5970 //
5971 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
5972 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
5973 // CHECK4-NEXT:  entry:
5974 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5975 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5976 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5977 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5978 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5979 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5980 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5981 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
5982 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
5983 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
5984 // CHECK4-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
5985 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5986 // CHECK4-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
5987 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5988 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
5989 // CHECK4-NEXT:    ret void
5990 //
5991 //
5992 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4
5993 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
5994 // CHECK4-NEXT:  entry:
5995 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5996 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5997 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5998 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5999 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6000 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i16, align 2
6001 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6002 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6003 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6004 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6005 // CHECK4-NEXT:    [[IT:%.*]] = alloca i16, align 2
6006 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6007 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6008 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6009 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6010 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6011 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
6012 // CHECK4-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
6013 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6014 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6015 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6016 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
6017 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6018 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6019 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
6020 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6021 // CHECK4:       cond.true:
6022 // CHECK4-NEXT:    br label [[COND_END:%.*]]
6023 // CHECK4:       cond.false:
6024 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6025 // CHECK4-NEXT:    br label [[COND_END]]
6026 // CHECK4:       cond.end:
6027 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
6028 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6029 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6030 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
6031 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6032 // CHECK4:       omp.inner.for.cond:
6033 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6034 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6035 // CHECK4-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
6036 // CHECK4-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6037 // CHECK4:       omp.inner.for.body:
6038 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6039 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
6040 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
6041 // CHECK4-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
6042 // CHECK4-NEXT:    store i16 [[CONV2]], i16* [[IT]], align 2
6043 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
6044 // CHECK4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
6045 // CHECK4-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4
6046 // CHECK4-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
6047 // CHECK4-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
6048 // CHECK4-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
6049 // CHECK4-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
6050 // CHECK4-NEXT:    store i16 [[CONV6]], i16* [[CONV]], align 4
6051 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6052 // CHECK4:       omp.body.continue:
6053 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6054 // CHECK4:       omp.inner.for.inc:
6055 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6056 // CHECK4-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
6057 // CHECK4-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
6058 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]]
6059 // CHECK4:       omp.inner.for.end:
6060 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6061 // CHECK4:       omp.loop.exit:
6062 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
6063 // CHECK4-NEXT:    ret void
6064 //
6065 //
6066 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
6067 // CHECK4-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
6068 // CHECK4-NEXT:  entry:
6069 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6070 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
6071 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6072 // CHECK4-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
6073 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
6074 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6075 // CHECK4-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
6076 // CHECK4-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
6077 // CHECK4-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
6078 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
6079 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6080 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
6081 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6082 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
6083 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6084 // CHECK4-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
6085 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
6086 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6087 // CHECK4-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
6088 // CHECK4-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
6089 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
6090 // CHECK4-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
6091 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
6092 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6093 // CHECK4-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
6094 // CHECK4-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
6095 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6096 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
6097 // CHECK4-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
6098 // CHECK4-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
6099 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
6100 // CHECK4-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
6101 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
6102 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
6103 // CHECK4-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
6104 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
6105 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
6106 // CHECK4-NEXT:    ret void
6107 //
6108 //
6109 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7
6110 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
6111 // CHECK4-NEXT:  entry:
6112 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6113 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6114 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6115 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
6116 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6117 // CHECK4-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
6118 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
6119 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6120 // CHECK4-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
6121 // CHECK4-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
6122 // CHECK4-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
6123 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
6124 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6125 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i8, align 1
6126 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6127 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6128 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6129 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6130 // CHECK4-NEXT:    [[IT:%.*]] = alloca i8, align 1
6131 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6132 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6133 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6134 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
6135 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6136 // CHECK4-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
6137 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
6138 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6139 // CHECK4-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
6140 // CHECK4-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
6141 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
6142 // CHECK4-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
6143 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
6144 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6145 // CHECK4-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
6146 // CHECK4-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
6147 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6148 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
6149 // CHECK4-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
6150 // CHECK4-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
6151 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
6152 // CHECK4-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
6153 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6154 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6155 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
6156 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6157 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
6158 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
6159 // CHECK4-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
6160 // CHECK4:       omp.dispatch.cond:
6161 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6162 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
6163 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6164 // CHECK4:       cond.true:
6165 // CHECK4-NEXT:    br label [[COND_END:%.*]]
6166 // CHECK4:       cond.false:
6167 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6168 // CHECK4-NEXT:    br label [[COND_END]]
6169 // CHECK4:       cond.end:
6170 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
6171 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6172 // CHECK4-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6173 // CHECK4-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
6174 // CHECK4-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6175 // CHECK4-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6176 // CHECK4-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
6177 // CHECK4-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
6178 // CHECK4:       omp.dispatch.body:
6179 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6180 // CHECK4:       omp.inner.for.cond:
6181 // CHECK4-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6182 // CHECK4-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6183 // CHECK4-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
6184 // CHECK4-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6185 // CHECK4:       omp.inner.for.body:
6186 // CHECK4-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6187 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
6188 // CHECK4-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
6189 // CHECK4-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
6190 // CHECK4-NEXT:    store i8 [[CONV]], i8* [[IT]], align 1
6191 // CHECK4-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
6192 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
6193 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
6194 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
6195 // CHECK4-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
6196 // CHECK4-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
6197 // CHECK4-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
6198 // CHECK4-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
6199 // CHECK4-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4
6200 // CHECK4-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
6201 // CHECK4-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
6202 // CHECK4-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
6203 // CHECK4-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
6204 // CHECK4-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
6205 // CHECK4-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4
6206 // CHECK4-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
6207 // CHECK4-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
6208 // CHECK4-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
6209 // CHECK4-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
6210 // CHECK4-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8
6211 // CHECK4-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
6212 // CHECK4-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
6213 // CHECK4-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
6214 // CHECK4-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
6215 // CHECK4-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
6216 // CHECK4-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8
6217 // CHECK4-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
6218 // CHECK4-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4
6219 // CHECK4-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
6220 // CHECK4-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4
6221 // CHECK4-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
6222 // CHECK4-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
6223 // CHECK4-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
6224 // CHECK4-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
6225 // CHECK4-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
6226 // CHECK4-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4
6227 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6228 // CHECK4:       omp.body.continue:
6229 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6230 // CHECK4:       omp.inner.for.inc:
6231 // CHECK4-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6232 // CHECK4-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
6233 // CHECK4-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
6234 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]]
6235 // CHECK4:       omp.inner.for.end:
6236 // CHECK4-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
6237 // CHECK4:       omp.dispatch.inc:
6238 // CHECK4-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6239 // CHECK4-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6240 // CHECK4-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
6241 // CHECK4-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
6242 // CHECK4-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6243 // CHECK4-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6244 // CHECK4-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
6245 // CHECK4-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
6246 // CHECK4-NEXT:    br label [[OMP_DISPATCH_COND]]
6247 // CHECK4:       omp.dispatch.end:
6248 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
6249 // CHECK4-NEXT:    ret void
6250 //
6251 //
6252 // CHECK4-LABEL: define {{[^@]+}}@_Z3bari
6253 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
6254 // CHECK4-NEXT:  entry:
6255 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6256 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
6257 // CHECK4-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
6258 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6259 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
6260 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6261 // CHECK4-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
6262 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
6263 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
6264 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
6265 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
6266 // CHECK4-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
6267 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
6268 // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
6269 // CHECK4-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
6270 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
6271 // CHECK4-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
6272 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
6273 // CHECK4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
6274 // CHECK4-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
6275 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
6276 // CHECK4-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
6277 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
6278 // CHECK4-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
6279 // CHECK4-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
6280 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
6281 // CHECK4-NEXT:    ret i32 [[TMP8]]
6282 //
6283 //
6284 // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
6285 // CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
6286 // CHECK4-NEXT:  entry:
6287 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6288 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6289 // CHECK4-NEXT:    [[B:%.*]] = alloca i32, align 4
6290 // CHECK4-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
6291 // CHECK4-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
6292 // CHECK4-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
6293 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
6294 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
6295 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
6296 // CHECK4-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
6297 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6298 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6299 // CHECK4-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6300 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6301 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6302 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
6303 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
6304 // CHECK4-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
6305 // CHECK4-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
6306 // CHECK4-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
6307 // CHECK4-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
6308 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
6309 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
6310 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
6311 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
6312 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
6313 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
6314 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6315 // CHECK4:       omp_if.then:
6316 // CHECK4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
6317 // CHECK4-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
6318 // CHECK4-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
6319 // CHECK4-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
6320 // CHECK4-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6321 // CHECK4-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
6322 // CHECK4-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
6323 // CHECK4-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6324 // CHECK4-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
6325 // CHECK4-NEXT:    store double* [[A]], double** [[TMP13]], align 4
6326 // CHECK4-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
6327 // CHECK4-NEXT:    store i64 8, i64* [[TMP14]], align 4
6328 // CHECK4-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6329 // CHECK4-NEXT:    store i8* null, i8** [[TMP15]], align 4
6330 // CHECK4-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6331 // CHECK4-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
6332 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP17]], align 4
6333 // CHECK4-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6334 // CHECK4-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
6335 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP19]], align 4
6336 // CHECK4-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
6337 // CHECK4-NEXT:    store i64 4, i64* [[TMP20]], align 4
6338 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6339 // CHECK4-NEXT:    store i8* null, i8** [[TMP21]], align 4
6340 // CHECK4-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6341 // CHECK4-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
6342 // CHECK4-NEXT:    store i32 2, i32* [[TMP23]], align 4
6343 // CHECK4-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6344 // CHECK4-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
6345 // CHECK4-NEXT:    store i32 2, i32* [[TMP25]], align 4
6346 // CHECK4-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
6347 // CHECK4-NEXT:    store i64 4, i64* [[TMP26]], align 4
6348 // CHECK4-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
6349 // CHECK4-NEXT:    store i8* null, i8** [[TMP27]], align 4
6350 // CHECK4-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
6351 // CHECK4-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
6352 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP29]], align 4
6353 // CHECK4-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
6354 // CHECK4-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
6355 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP31]], align 4
6356 // CHECK4-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
6357 // CHECK4-NEXT:    store i64 4, i64* [[TMP32]], align 4
6358 // CHECK4-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
6359 // CHECK4-NEXT:    store i8* null, i8** [[TMP33]], align 4
6360 // CHECK4-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
6361 // CHECK4-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
6362 // CHECK4-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 4
6363 // CHECK4-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
6364 // CHECK4-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
6365 // CHECK4-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 4
6366 // CHECK4-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
6367 // CHECK4-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 4
6368 // CHECK4-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
6369 // CHECK4-NEXT:    store i8* null, i8** [[TMP39]], align 4
6370 // CHECK4-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6371 // CHECK4-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6372 // CHECK4-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
6373 // CHECK4-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
6374 // CHECK4-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
6375 // CHECK4-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6376 // CHECK4:       omp_offload.failed:
6377 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
6378 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6379 // CHECK4:       omp_offload.cont:
6380 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
6381 // CHECK4:       omp_if.else:
6382 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
6383 // CHECK4-NEXT:    br label [[OMP_IF_END]]
6384 // CHECK4:       omp_if.end:
6385 // CHECK4-NEXT:    [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
6386 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
6387 // CHECK4-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
6388 // CHECK4-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
6389 // CHECK4-NEXT:    [[CONV:%.*]] = sext i16 [[TMP46]] to i32
6390 // CHECK4-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
6391 // CHECK4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
6392 // CHECK4-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
6393 // CHECK4-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
6394 // CHECK4-NEXT:    ret i32 [[ADD3]]
6395 //
6396 //
6397 // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici
6398 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
6399 // CHECK4-NEXT:  entry:
6400 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6401 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
6402 // CHECK4-NEXT:    [[AA:%.*]] = alloca i16, align 2
6403 // CHECK4-NEXT:    [[AAA:%.*]] = alloca i8, align 1
6404 // CHECK4-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
6405 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6406 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6407 // CHECK4-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
6408 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
6409 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
6410 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
6411 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6412 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
6413 // CHECK4-NEXT:    store i16 0, i16* [[AA]], align 2
6414 // CHECK4-NEXT:    store i8 0, i8* [[AAA]], align 1
6415 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
6416 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
6417 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
6418 // CHECK4-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
6419 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6420 // CHECK4-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
6421 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6422 // CHECK4-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
6423 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
6424 // CHECK4-NEXT:    store i8 [[TMP4]], i8* [[CONV1]], align 1
6425 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
6426 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
6427 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
6428 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6429 // CHECK4:       omp_if.then:
6430 // CHECK4-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6431 // CHECK4-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
6432 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
6433 // CHECK4-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6434 // CHECK4-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
6435 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
6436 // CHECK4-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6437 // CHECK4-NEXT:    store i8* null, i8** [[TMP11]], align 4
6438 // CHECK4-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6439 // CHECK4-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
6440 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
6441 // CHECK4-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6442 // CHECK4-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
6443 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
6444 // CHECK4-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6445 // CHECK4-NEXT:    store i8* null, i8** [[TMP16]], align 4
6446 // CHECK4-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6447 // CHECK4-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
6448 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP18]], align 4
6449 // CHECK4-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6450 // CHECK4-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
6451 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
6452 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
6453 // CHECK4-NEXT:    store i8* null, i8** [[TMP21]], align 4
6454 // CHECK4-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
6455 // CHECK4-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
6456 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
6457 // CHECK4-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
6458 // CHECK4-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
6459 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
6460 // CHECK4-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
6461 // CHECK4-NEXT:    store i8* null, i8** [[TMP26]], align 4
6462 // CHECK4-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6463 // CHECK4-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6464 // CHECK4-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
6465 // CHECK4-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
6466 // CHECK4-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6467 // CHECK4:       omp_offload.failed:
6468 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
6469 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6470 // CHECK4:       omp_offload.cont:
6471 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
6472 // CHECK4:       omp_if.else:
6473 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
6474 // CHECK4-NEXT:    br label [[OMP_IF_END]]
6475 // CHECK4:       omp_if.end:
6476 // CHECK4-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
6477 // CHECK4-NEXT:    ret i32 [[TMP31]]
6478 //
6479 //
6480 // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
6481 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
6482 // CHECK4-NEXT:  entry:
6483 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6484 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
6485 // CHECK4-NEXT:    [[AA:%.*]] = alloca i16, align 2
6486 // CHECK4-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
6487 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6488 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6489 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
6490 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
6491 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
6492 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6493 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
6494 // CHECK4-NEXT:    store i16 0, i16* [[AA]], align 2
6495 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
6496 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
6497 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
6498 // CHECK4-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
6499 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6500 // CHECK4-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
6501 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6502 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
6503 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
6504 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6505 // CHECK4:       omp_if.then:
6506 // CHECK4-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6507 // CHECK4-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
6508 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
6509 // CHECK4-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6510 // CHECK4-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
6511 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
6512 // CHECK4-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6513 // CHECK4-NEXT:    store i8* null, i8** [[TMP9]], align 4
6514 // CHECK4-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6515 // CHECK4-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
6516 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
6517 // CHECK4-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6518 // CHECK4-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
6519 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
6520 // CHECK4-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6521 // CHECK4-NEXT:    store i8* null, i8** [[TMP14]], align 4
6522 // CHECK4-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6523 // CHECK4-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
6524 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
6525 // CHECK4-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6526 // CHECK4-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
6527 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
6528 // CHECK4-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
6529 // CHECK4-NEXT:    store i8* null, i8** [[TMP19]], align 4
6530 // CHECK4-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6531 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6532 // CHECK4-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
6533 // CHECK4-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
6534 // CHECK4-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6535 // CHECK4:       omp_offload.failed:
6536 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
6537 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6538 // CHECK4:       omp_offload.cont:
6539 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
6540 // CHECK4:       omp_if.else:
6541 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
6542 // CHECK4-NEXT:    br label [[OMP_IF_END]]
6543 // CHECK4:       omp_if.end:
6544 // CHECK4-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
6545 // CHECK4-NEXT:    ret i32 [[TMP24]]
6546 //
6547 //
6548 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
6549 // CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
6550 // CHECK4-NEXT:  entry:
6551 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6552 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
6553 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6554 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6555 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
6556 // CHECK4-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
6557 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6558 // CHECK4-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
6559 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6560 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6561 // CHECK4-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
6562 // CHECK4-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6563 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6564 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6565 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
6566 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
6567 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
6568 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
6569 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
6570 // CHECK4-NEXT:    ret void
6571 //
6572 //
6573 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9
6574 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
6575 // CHECK4-NEXT:  entry:
6576 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6577 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6578 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6579 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
6580 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6581 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6582 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
6583 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
6584 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i64, align 4
6585 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
6586 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
6587 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
6588 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6589 // CHECK4-NEXT:    [[IT:%.*]] = alloca i64, align 8
6590 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6591 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6592 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6593 // CHECK4-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
6594 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6595 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6596 // CHECK4-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
6597 // CHECK4-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6598 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6599 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6600 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
6601 // CHECK4-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
6602 // CHECK4-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
6603 // CHECK4-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
6604 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6605 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6606 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
6607 // CHECK4-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
6608 // CHECK4-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
6609 // CHECK4-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
6610 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6611 // CHECK4:       cond.true:
6612 // CHECK4-NEXT:    br label [[COND_END:%.*]]
6613 // CHECK4:       cond.false:
6614 // CHECK4-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
6615 // CHECK4-NEXT:    br label [[COND_END]]
6616 // CHECK4:       cond.end:
6617 // CHECK4-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
6618 // CHECK4-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
6619 // CHECK4-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
6620 // CHECK4-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
6621 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6622 // CHECK4:       omp.inner.for.cond:
6623 // CHECK4-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
6624 // CHECK4-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
6625 // CHECK4-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
6626 // CHECK4-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6627 // CHECK4:       omp.inner.for.body:
6628 // CHECK4-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
6629 // CHECK4-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
6630 // CHECK4-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
6631 // CHECK4-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
6632 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
6633 // CHECK4-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
6634 // CHECK4-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
6635 // CHECK4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
6636 // CHECK4-NEXT:    store double [[ADD]], double* [[A]], align 4
6637 // CHECK4-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
6638 // CHECK4-NEXT:    [[TMP13:%.*]] = load double, double* [[A4]], align 4
6639 // CHECK4-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
6640 // CHECK4-NEXT:    store double [[INC]], double* [[A4]], align 4
6641 // CHECK4-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
6642 // CHECK4-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
6643 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
6644 // CHECK4-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
6645 // CHECK4-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
6646 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6647 // CHECK4:       omp.body.continue:
6648 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6649 // CHECK4:       omp.inner.for.inc:
6650 // CHECK4-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
6651 // CHECK4-NEXT:    [[ADD7:%.*]] = add i64 [[TMP15]], 1
6652 // CHECK4-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
6653 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]]
6654 // CHECK4:       omp.inner.for.end:
6655 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6656 // CHECK4:       omp.loop.exit:
6657 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
6658 // CHECK4-NEXT:    ret void
6659 //
6660 //
6661 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
6662 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
6663 // CHECK4-NEXT:  entry:
6664 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6665 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6666 // CHECK4-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
6667 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6668 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6669 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6670 // CHECK4-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
6671 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6672 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6673 // CHECK4-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
6674 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6675 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6676 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
6677 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6678 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
6679 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
6680 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
6681 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
6682 // CHECK4-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6683 // CHECK4-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
6684 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6685 // CHECK4-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
6686 // CHECK4-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
6687 // CHECK4-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
6688 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
6689 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
6690 // CHECK4-NEXT:    ret void
6691 //
6692 //
6693 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11
6694 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
6695 // CHECK4-NEXT:  entry:
6696 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6697 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6698 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6699 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6700 // CHECK4-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
6701 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6702 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6703 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6704 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6705 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6706 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6707 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6708 // CHECK4-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
6709 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6710 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6711 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
6712 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6713 // CHECK4-NEXT:    ret void
6714 //
6715 //
6716 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
6717 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
6718 // CHECK4-NEXT:  entry:
6719 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6720 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6721 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6722 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6723 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6724 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6725 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6726 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6727 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6728 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6729 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
6730 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
6731 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
6732 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
6733 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6734 // CHECK4-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
6735 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6736 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
6737 // CHECK4-NEXT:    ret void
6738 //
6739 //
6740 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14
6741 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
6742 // CHECK4-NEXT:  entry:
6743 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6744 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6745 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6746 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6747 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6748 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
6749 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i64, align 4
6750 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
6751 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
6752 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
6753 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6754 // CHECK4-NEXT:    [[I:%.*]] = alloca i64, align 8
6755 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6756 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6757 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6758 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6759 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6760 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6761 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6762 // CHECK4-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
6763 // CHECK4-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
6764 // CHECK4-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
6765 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6766 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6767 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
6768 // CHECK4-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
6769 // CHECK4-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
6770 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
6771 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6772 // CHECK4:       cond.true:
6773 // CHECK4-NEXT:    br label [[COND_END:%.*]]
6774 // CHECK4:       cond.false:
6775 // CHECK4-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
6776 // CHECK4-NEXT:    br label [[COND_END]]
6777 // CHECK4:       cond.end:
6778 // CHECK4-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
6779 // CHECK4-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
6780 // CHECK4-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
6781 // CHECK4-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
6782 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6783 // CHECK4:       omp.inner.for.cond:
6784 // CHECK4-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
6785 // CHECK4-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
6786 // CHECK4-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
6787 // CHECK4-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6788 // CHECK4:       omp.inner.for.body:
6789 // CHECK4-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
6790 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
6791 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
6792 // CHECK4-NEXT:    store i64 [[ADD]], i64* [[I]], align 8
6793 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
6794 // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
6795 // CHECK4-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
6796 // CHECK4-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
6797 // CHECK4-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
6798 // CHECK4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
6799 // CHECK4-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
6800 // CHECK4-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
6801 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
6802 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
6803 // CHECK4-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
6804 // CHECK4-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
6805 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6806 // CHECK4:       omp.body.continue:
6807 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6808 // CHECK4:       omp.inner.for.inc:
6809 // CHECK4-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
6810 // CHECK4-NEXT:    [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
6811 // CHECK4-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
6812 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]]
6813 // CHECK4:       omp.inner.for.end:
6814 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6815 // CHECK4:       omp.loop.exit:
6816 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
6817 // CHECK4-NEXT:    ret void
6818 //
6819 //
6820 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
6821 // CHECK4-SAME: () #[[ATTR5]] {
6822 // CHECK4-NEXT:  entry:
6823 // CHECK4-NEXT:    call void @__tgt_register_requires(i64 1)
6824 // CHECK4-NEXT:    ret void
6825 //
6826 //
6827 // CHECK5-LABEL: define {{[^@]+}}@_Z7get_valv
6828 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
6829 // CHECK5-NEXT:  entry:
6830 // CHECK5-NEXT:    ret i64 0
6831 //
6832 //
6833 // CHECK5-LABEL: define {{[^@]+}}@_Z3fooi
6834 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
6835 // CHECK5-NEXT:  entry:
6836 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6837 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
6838 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
6839 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
6840 // CHECK5-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
6841 // CHECK5-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
6842 // CHECK5-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
6843 // CHECK5-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
6844 // CHECK5-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
6845 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
6846 // CHECK5-NEXT:    [[K:%.*]] = alloca i64, align 8
6847 // CHECK5-NEXT:    [[I2:%.*]] = alloca i32, align 4
6848 // CHECK5-NEXT:    [[LIN:%.*]] = alloca i32, align 4
6849 // CHECK5-NEXT:    [[IT:%.*]] = alloca i64, align 8
6850 // CHECK5-NEXT:    [[IT16:%.*]] = alloca i16, align 2
6851 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
6852 // CHECK5-NEXT:    [[IT30:%.*]] = alloca i8, align 1
6853 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6854 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
6855 // CHECK5-NEXT:    store i16 0, i16* [[AA]], align 2
6856 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6857 // CHECK5-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
6858 // CHECK5-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
6859 // CHECK5-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
6860 // CHECK5-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
6861 // CHECK5-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
6862 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
6863 // CHECK5-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
6864 // CHECK5-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
6865 // CHECK5-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
6866 // CHECK5-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
6867 // CHECK5-NEXT:    store i32 3, i32* [[I]], align 4
6868 // CHECK5-NEXT:    br label [[FOR_COND:%.*]]
6869 // CHECK5:       for.cond:
6870 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I]], align 4
6871 // CHECK5-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32
6872 // CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
6873 // CHECK5:       for.body:
6874 // CHECK5-NEXT:    br label [[FOR_INC:%.*]]
6875 // CHECK5:       for.inc:
6876 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
6877 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP7]], 5
6878 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
6879 // CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
6880 // CHECK5:       for.end:
6881 // CHECK5-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
6882 // CHECK5-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
6883 // CHECK5-NEXT:    store i32 10, i32* [[I2]], align 4
6884 // CHECK5-NEXT:    br label [[FOR_COND3:%.*]]
6885 // CHECK5:       for.cond3:
6886 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I2]], align 4
6887 // CHECK5-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1
6888 // CHECK5-NEXT:    br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]]
6889 // CHECK5:       for.body5:
6890 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
6891 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1
6892 // CHECK5-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
6893 // CHECK5-NEXT:    br label [[FOR_INC7:%.*]]
6894 // CHECK5:       for.inc7:
6895 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I2]], align 4
6896 // CHECK5-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP10]], -1
6897 // CHECK5-NEXT:    store i32 [[DEC]], i32* [[I2]], align 4
6898 // CHECK5-NEXT:    br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]]
6899 // CHECK5:       for.end8:
6900 // CHECK5-NEXT:    store i32 12, i32* [[LIN]], align 4
6901 // CHECK5-NEXT:    store i64 2000, i64* [[IT]], align 8
6902 // CHECK5-NEXT:    br label [[FOR_COND9:%.*]]
6903 // CHECK5:       for.cond9:
6904 // CHECK5-NEXT:    [[TMP11:%.*]] = load i64, i64* [[IT]], align 8
6905 // CHECK5-NEXT:    [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600
6906 // CHECK5-NEXT:    br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]]
6907 // CHECK5:       for.body11:
6908 // CHECK5-NEXT:    [[TMP12:%.*]] = load i16, i16* [[AA]], align 2
6909 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP12]] to i32
6910 // CHECK5-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV]], 1
6911 // CHECK5-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
6912 // CHECK5-NEXT:    store i16 [[CONV13]], i16* [[AA]], align 2
6913 // CHECK5-NEXT:    br label [[FOR_INC14:%.*]]
6914 // CHECK5:       for.inc14:
6915 // CHECK5-NEXT:    [[TMP13:%.*]] = load i64, i64* [[IT]], align 8
6916 // CHECK5-NEXT:    [[SUB:%.*]] = sub i64 [[TMP13]], 400
6917 // CHECK5-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
6918 // CHECK5-NEXT:    br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]]
6919 // CHECK5:       for.end15:
6920 // CHECK5-NEXT:    store i16 6, i16* [[IT16]], align 2
6921 // CHECK5-NEXT:    br label [[FOR_COND17:%.*]]
6922 // CHECK5:       for.cond17:
6923 // CHECK5-NEXT:    [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2
6924 // CHECK5-NEXT:    [[CONV18:%.*]] = sext i16 [[TMP14]] to i32
6925 // CHECK5-NEXT:    [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20
6926 // CHECK5-NEXT:    br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]]
6927 // CHECK5:       for.body20:
6928 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
6929 // CHECK5-NEXT:    [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1
6930 // CHECK5-NEXT:    store i32 [[ADD21]], i32* [[A]], align 4
6931 // CHECK5-NEXT:    [[TMP16:%.*]] = load i16, i16* [[AA]], align 2
6932 // CHECK5-NEXT:    [[CONV22:%.*]] = sext i16 [[TMP16]] to i32
6933 // CHECK5-NEXT:    [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1
6934 // CHECK5-NEXT:    [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16
6935 // CHECK5-NEXT:    store i16 [[CONV24]], i16* [[AA]], align 2
6936 // CHECK5-NEXT:    br label [[FOR_INC25:%.*]]
6937 // CHECK5:       for.inc25:
6938 // CHECK5-NEXT:    [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2
6939 // CHECK5-NEXT:    [[CONV26:%.*]] = sext i16 [[TMP17]] to i32
6940 // CHECK5-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4
6941 // CHECK5-NEXT:    [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16
6942 // CHECK5-NEXT:    store i16 [[CONV28]], i16* [[IT16]], align 2
6943 // CHECK5-NEXT:    br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]]
6944 // CHECK5:       for.end29:
6945 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
6946 // CHECK5-NEXT:    store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4
6947 // CHECK5-NEXT:    store i8 122, i8* [[IT30]], align 1
6948 // CHECK5-NEXT:    br label [[FOR_COND31:%.*]]
6949 // CHECK5:       for.cond31:
6950 // CHECK5-NEXT:    [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1
6951 // CHECK5-NEXT:    [[CONV32:%.*]] = zext i8 [[TMP19]] to i32
6952 // CHECK5-NEXT:    [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97
6953 // CHECK5-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]]
6954 // CHECK5:       for.body34:
6955 // CHECK5-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A]], align 4
6956 // CHECK5-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1
6957 // CHECK5-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
6958 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
6959 // CHECK5-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4
6960 // CHECK5-NEXT:    [[CONV36:%.*]] = fpext float [[TMP21]] to double
6961 // CHECK5-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
6962 // CHECK5-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
6963 // CHECK5-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
6964 // CHECK5-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
6965 // CHECK5-NEXT:    [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4
6966 // CHECK5-NEXT:    [[CONV40:%.*]] = fpext float [[TMP22]] to double
6967 // CHECK5-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
6968 // CHECK5-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
6969 // CHECK5-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
6970 // CHECK5-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
6971 // CHECK5-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2
6972 // CHECK5-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8
6973 // CHECK5-NEXT:    [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00
6974 // CHECK5-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
6975 // CHECK5-NEXT:    [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]]
6976 // CHECK5-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]]
6977 // CHECK5-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3
6978 // CHECK5-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8
6979 // CHECK5-NEXT:    [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00
6980 // CHECK5-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
6981 // CHECK5-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
6982 // CHECK5-NEXT:    [[TMP26:%.*]] = load i64, i64* [[X]], align 8
6983 // CHECK5-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1
6984 // CHECK5-NEXT:    store i64 [[ADD49]], i64* [[X]], align 8
6985 // CHECK5-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
6986 // CHECK5-NEXT:    [[TMP27:%.*]] = load i8, i8* [[Y]], align 8
6987 // CHECK5-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP27]] to i32
6988 // CHECK5-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
6989 // CHECK5-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
6990 // CHECK5-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 8
6991 // CHECK5-NEXT:    br label [[FOR_INC53:%.*]]
6992 // CHECK5:       for.inc53:
6993 // CHECK5-NEXT:    [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1
6994 // CHECK5-NEXT:    [[CONV54:%.*]] = zext i8 [[TMP28]] to i32
6995 // CHECK5-NEXT:    [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1
6996 // CHECK5-NEXT:    [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8
6997 // CHECK5-NEXT:    store i8 [[CONV56]], i8* [[IT30]], align 1
6998 // CHECK5-NEXT:    br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]]
6999 // CHECK5:       for.end57:
7000 // CHECK5-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
7001 // CHECK5-NEXT:    [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
7002 // CHECK5-NEXT:    call void @llvm.stackrestore(i8* [[TMP30]])
7003 // CHECK5-NEXT:    ret i32 [[TMP29]]
7004 //
7005 //
7006 // CHECK5-LABEL: define {{[^@]+}}@_Z3bari
7007 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
7008 // CHECK5-NEXT:  entry:
7009 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7010 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
7011 // CHECK5-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
7012 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7013 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
7014 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7015 // CHECK5-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
7016 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7017 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
7018 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7019 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7020 // CHECK5-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
7021 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7022 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
7023 // CHECK5-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
7024 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7025 // CHECK5-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
7026 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7027 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
7028 // CHECK5-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
7029 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
7030 // CHECK5-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
7031 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
7032 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
7033 // CHECK5-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
7034 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
7035 // CHECK5-NEXT:    ret i32 [[TMP8]]
7036 //
7037 //
7038 // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
7039 // CHECK5-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
7040 // CHECK5-NEXT:  entry:
7041 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
7042 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7043 // CHECK5-NEXT:    [[B:%.*]] = alloca i32, align 4
7044 // CHECK5-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
7045 // CHECK5-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
7046 // CHECK5-NEXT:    [[IT:%.*]] = alloca i64, align 8
7047 // CHECK5-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
7048 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7049 // CHECK5-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
7050 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7051 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7052 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
7053 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
7054 // CHECK5-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
7055 // CHECK5-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
7056 // CHECK5-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
7057 // CHECK5-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
7058 // CHECK5-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
7059 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
7060 // CHECK5-NEXT:    store i64 2000, i64* [[IT]], align 8
7061 // CHECK5-NEXT:    br label [[FOR_COND:%.*]]
7062 // CHECK5:       for.cond:
7063 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, i64* [[IT]], align 8
7064 // CHECK5-NEXT:    [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600
7065 // CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7066 // CHECK5:       for.body:
7067 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
7068 // CHECK5-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP6]] to double
7069 // CHECK5-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
7070 // CHECK5-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
7071 // CHECK5-NEXT:    store double [[ADD2]], double* [[A]], align 8
7072 // CHECK5-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
7073 // CHECK5-NEXT:    [[TMP7:%.*]] = load double, double* [[A3]], align 8
7074 // CHECK5-NEXT:    [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
7075 // CHECK5-NEXT:    store double [[INC]], double* [[A3]], align 8
7076 // CHECK5-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
7077 // CHECK5-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
7078 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
7079 // CHECK5-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
7080 // CHECK5-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
7081 // CHECK5-NEXT:    br label [[FOR_INC:%.*]]
7082 // CHECK5:       for.inc:
7083 // CHECK5-NEXT:    [[TMP9:%.*]] = load i64, i64* [[IT]], align 8
7084 // CHECK5-NEXT:    [[SUB:%.*]] = sub i64 [[TMP9]], 400
7085 // CHECK5-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
7086 // CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
7087 // CHECK5:       for.end:
7088 // CHECK5-NEXT:    [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
7089 // CHECK5-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]]
7090 // CHECK5-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
7091 // CHECK5-NEXT:    [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
7092 // CHECK5-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP11]] to i32
7093 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B]], align 4
7094 // CHECK5-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]]
7095 // CHECK5-NEXT:    [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
7096 // CHECK5-NEXT:    call void @llvm.stackrestore(i8* [[TMP13]])
7097 // CHECK5-NEXT:    ret i32 [[ADD9]]
7098 //
7099 //
7100 // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici
7101 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
7102 // CHECK5-NEXT:  entry:
7103 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7104 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
7105 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
7106 // CHECK5-NEXT:    [[AAA:%.*]] = alloca i8, align 1
7107 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7108 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
7109 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7110 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
7111 // CHECK5-NEXT:    store i16 0, i16* [[AA]], align 2
7112 // CHECK5-NEXT:    store i8 0, i8* [[AAA]], align 1
7113 // CHECK5-NEXT:    store i32 100, i32* [[I]], align 4
7114 // CHECK5-NEXT:    br label [[FOR_COND:%.*]]
7115 // CHECK5:       for.cond:
7116 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
7117 // CHECK5-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10
7118 // CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7119 // CHECK5:       for.body:
7120 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7121 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
7122 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7123 // CHECK5-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
7124 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
7125 // CHECK5-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
7126 // CHECK5-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
7127 // CHECK5-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
7128 // CHECK5-NEXT:    [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1
7129 // CHECK5-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
7130 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
7131 // CHECK5-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
7132 // CHECK5-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
7133 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
7134 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7135 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
7136 // CHECK5-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
7137 // CHECK5-NEXT:    br label [[FOR_INC:%.*]]
7138 // CHECK5:       for.inc:
7139 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
7140 // CHECK5-NEXT:    [[ADD7:%.*]] = add i32 [[TMP5]], 10
7141 // CHECK5-NEXT:    store i32 [[ADD7]], i32* [[I]], align 4
7142 // CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
7143 // CHECK5:       for.end:
7144 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
7145 // CHECK5-NEXT:    ret i32 [[TMP6]]
7146 //
7147 //
7148 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
7149 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
7150 // CHECK5-NEXT:  entry:
7151 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7152 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
7153 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
7154 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7155 // CHECK5-NEXT:    [[I:%.*]] = alloca i64, align 8
7156 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7157 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
7158 // CHECK5-NEXT:    store i16 0, i16* [[AA]], align 2
7159 // CHECK5-NEXT:    store i64 -10, i64* [[I]], align 8
7160 // CHECK5-NEXT:    br label [[FOR_COND:%.*]]
7161 // CHECK5:       for.cond:
7162 // CHECK5-NEXT:    [[TMP0:%.*]] = load i64, i64* [[I]], align 8
7163 // CHECK5-NEXT:    [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10
7164 // CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7165 // CHECK5:       for.body:
7166 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7167 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
7168 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7169 // CHECK5-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
7170 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
7171 // CHECK5-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
7172 // CHECK5-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
7173 // CHECK5-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
7174 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
7175 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7176 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
7177 // CHECK5-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
7178 // CHECK5-NEXT:    br label [[FOR_INC:%.*]]
7179 // CHECK5:       for.inc:
7180 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, i64* [[I]], align 8
7181 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3
7182 // CHECK5-NEXT:    store i64 [[ADD4]], i64* [[I]], align 8
7183 // CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
7184 // CHECK5:       for.end:
7185 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7186 // CHECK5-NEXT:    ret i32 [[TMP5]]
7187 //
7188 //
7189 // CHECK6-LABEL: define {{[^@]+}}@_Z7get_valv
7190 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
7191 // CHECK6-NEXT:  entry:
7192 // CHECK6-NEXT:    ret i64 0
7193 //
7194 //
7195 // CHECK6-LABEL: define {{[^@]+}}@_Z3fooi
7196 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
7197 // CHECK6-NEXT:  entry:
7198 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7199 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
7200 // CHECK6-NEXT:    [[AA:%.*]] = alloca i16, align 2
7201 // CHECK6-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
7202 // CHECK6-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
7203 // CHECK6-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
7204 // CHECK6-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
7205 // CHECK6-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
7206 // CHECK6-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
7207 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
7208 // CHECK6-NEXT:    [[K:%.*]] = alloca i64, align 8
7209 // CHECK6-NEXT:    [[I2:%.*]] = alloca i32, align 4
7210 // CHECK6-NEXT:    [[LIN:%.*]] = alloca i32, align 4
7211 // CHECK6-NEXT:    [[IT:%.*]] = alloca i64, align 8
7212 // CHECK6-NEXT:    [[IT16:%.*]] = alloca i16, align 2
7213 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
7214 // CHECK6-NEXT:    [[IT30:%.*]] = alloca i8, align 1
7215 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7216 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
7217 // CHECK6-NEXT:    store i16 0, i16* [[AA]], align 2
7218 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7219 // CHECK6-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
7220 // CHECK6-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
7221 // CHECK6-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
7222 // CHECK6-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
7223 // CHECK6-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
7224 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
7225 // CHECK6-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
7226 // CHECK6-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
7227 // CHECK6-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
7228 // CHECK6-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
7229 // CHECK6-NEXT:    store i32 3, i32* [[I]], align 4
7230 // CHECK6-NEXT:    br label [[FOR_COND:%.*]]
7231 // CHECK6:       for.cond:
7232 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I]], align 4
7233 // CHECK6-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32
7234 // CHECK6-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7235 // CHECK6:       for.body:
7236 // CHECK6-NEXT:    br label [[FOR_INC:%.*]]
7237 // CHECK6:       for.inc:
7238 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
7239 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP7]], 5
7240 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
7241 // CHECK6-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
7242 // CHECK6:       for.end:
7243 // CHECK6-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
7244 // CHECK6-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
7245 // CHECK6-NEXT:    store i32 10, i32* [[I2]], align 4
7246 // CHECK6-NEXT:    br label [[FOR_COND3:%.*]]
7247 // CHECK6:       for.cond3:
7248 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I2]], align 4
7249 // CHECK6-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1
7250 // CHECK6-NEXT:    br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]]
7251 // CHECK6:       for.body5:
7252 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
7253 // CHECK6-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1
7254 // CHECK6-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
7255 // CHECK6-NEXT:    br label [[FOR_INC7:%.*]]
7256 // CHECK6:       for.inc7:
7257 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I2]], align 4
7258 // CHECK6-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP10]], -1
7259 // CHECK6-NEXT:    store i32 [[DEC]], i32* [[I2]], align 4
7260 // CHECK6-NEXT:    br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]]
7261 // CHECK6:       for.end8:
7262 // CHECK6-NEXT:    store i32 12, i32* [[LIN]], align 4
7263 // CHECK6-NEXT:    store i64 2000, i64* [[IT]], align 8
7264 // CHECK6-NEXT:    br label [[FOR_COND9:%.*]]
7265 // CHECK6:       for.cond9:
7266 // CHECK6-NEXT:    [[TMP11:%.*]] = load i64, i64* [[IT]], align 8
7267 // CHECK6-NEXT:    [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600
7268 // CHECK6-NEXT:    br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]]
7269 // CHECK6:       for.body11:
7270 // CHECK6-NEXT:    [[TMP12:%.*]] = load i16, i16* [[AA]], align 2
7271 // CHECK6-NEXT:    [[CONV:%.*]] = sext i16 [[TMP12]] to i32
7272 // CHECK6-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV]], 1
7273 // CHECK6-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
7274 // CHECK6-NEXT:    store i16 [[CONV13]], i16* [[AA]], align 2
7275 // CHECK6-NEXT:    br label [[FOR_INC14:%.*]]
7276 // CHECK6:       for.inc14:
7277 // CHECK6-NEXT:    [[TMP13:%.*]] = load i64, i64* [[IT]], align 8
7278 // CHECK6-NEXT:    [[SUB:%.*]] = sub i64 [[TMP13]], 400
7279 // CHECK6-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
7280 // CHECK6-NEXT:    br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]]
7281 // CHECK6:       for.end15:
7282 // CHECK6-NEXT:    store i16 6, i16* [[IT16]], align 2
7283 // CHECK6-NEXT:    br label [[FOR_COND17:%.*]]
7284 // CHECK6:       for.cond17:
7285 // CHECK6-NEXT:    [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2
7286 // CHECK6-NEXT:    [[CONV18:%.*]] = sext i16 [[TMP14]] to i32
7287 // CHECK6-NEXT:    [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20
7288 // CHECK6-NEXT:    br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]]
7289 // CHECK6:       for.body20:
7290 // CHECK6-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
7291 // CHECK6-NEXT:    [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1
7292 // CHECK6-NEXT:    store i32 [[ADD21]], i32* [[A]], align 4
7293 // CHECK6-NEXT:    [[TMP16:%.*]] = load i16, i16* [[AA]], align 2
7294 // CHECK6-NEXT:    [[CONV22:%.*]] = sext i16 [[TMP16]] to i32
7295 // CHECK6-NEXT:    [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1
7296 // CHECK6-NEXT:    [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16
7297 // CHECK6-NEXT:    store i16 [[CONV24]], i16* [[AA]], align 2
7298 // CHECK6-NEXT:    br label [[FOR_INC25:%.*]]
7299 // CHECK6:       for.inc25:
7300 // CHECK6-NEXT:    [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2
7301 // CHECK6-NEXT:    [[CONV26:%.*]] = sext i16 [[TMP17]] to i32
7302 // CHECK6-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4
7303 // CHECK6-NEXT:    [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16
7304 // CHECK6-NEXT:    store i16 [[CONV28]], i16* [[IT16]], align 2
7305 // CHECK6-NEXT:    br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]]
7306 // CHECK6:       for.end29:
7307 // CHECK6-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
7308 // CHECK6-NEXT:    store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4
7309 // CHECK6-NEXT:    store i8 122, i8* [[IT30]], align 1
7310 // CHECK6-NEXT:    br label [[FOR_COND31:%.*]]
7311 // CHECK6:       for.cond31:
7312 // CHECK6-NEXT:    [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1
7313 // CHECK6-NEXT:    [[CONV32:%.*]] = zext i8 [[TMP19]] to i32
7314 // CHECK6-NEXT:    [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97
7315 // CHECK6-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]]
7316 // CHECK6:       for.body34:
7317 // CHECK6-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A]], align 4
7318 // CHECK6-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1
7319 // CHECK6-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
7320 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
7321 // CHECK6-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4
7322 // CHECK6-NEXT:    [[CONV36:%.*]] = fpext float [[TMP21]] to double
7323 // CHECK6-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
7324 // CHECK6-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
7325 // CHECK6-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
7326 // CHECK6-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
7327 // CHECK6-NEXT:    [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4
7328 // CHECK6-NEXT:    [[CONV40:%.*]] = fpext float [[TMP22]] to double
7329 // CHECK6-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
7330 // CHECK6-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
7331 // CHECK6-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
7332 // CHECK6-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
7333 // CHECK6-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2
7334 // CHECK6-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8
7335 // CHECK6-NEXT:    [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00
7336 // CHECK6-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
7337 // CHECK6-NEXT:    [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]]
7338 // CHECK6-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]]
7339 // CHECK6-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3
7340 // CHECK6-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8
7341 // CHECK6-NEXT:    [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00
7342 // CHECK6-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
7343 // CHECK6-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
7344 // CHECK6-NEXT:    [[TMP26:%.*]] = load i64, i64* [[X]], align 8
7345 // CHECK6-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1
7346 // CHECK6-NEXT:    store i64 [[ADD49]], i64* [[X]], align 8
7347 // CHECK6-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
7348 // CHECK6-NEXT:    [[TMP27:%.*]] = load i8, i8* [[Y]], align 8
7349 // CHECK6-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP27]] to i32
7350 // CHECK6-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
7351 // CHECK6-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
7352 // CHECK6-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 8
7353 // CHECK6-NEXT:    br label [[FOR_INC53:%.*]]
7354 // CHECK6:       for.inc53:
7355 // CHECK6-NEXT:    [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1
7356 // CHECK6-NEXT:    [[CONV54:%.*]] = zext i8 [[TMP28]] to i32
7357 // CHECK6-NEXT:    [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1
7358 // CHECK6-NEXT:    [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8
7359 // CHECK6-NEXT:    store i8 [[CONV56]], i8* [[IT30]], align 1
7360 // CHECK6-NEXT:    br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]]
7361 // CHECK6:       for.end57:
7362 // CHECK6-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
7363 // CHECK6-NEXT:    [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
7364 // CHECK6-NEXT:    call void @llvm.stackrestore(i8* [[TMP30]])
7365 // CHECK6-NEXT:    ret i32 [[TMP29]]
7366 //
7367 //
7368 // CHECK6-LABEL: define {{[^@]+}}@_Z3bari
7369 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
7370 // CHECK6-NEXT:  entry:
7371 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7372 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
7373 // CHECK6-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
7374 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7375 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
7376 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7377 // CHECK6-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
7378 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7379 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
7380 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7381 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7382 // CHECK6-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
7383 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7384 // CHECK6-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
7385 // CHECK6-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
7386 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7387 // CHECK6-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
7388 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7389 // CHECK6-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
7390 // CHECK6-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
7391 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
7392 // CHECK6-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
7393 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
7394 // CHECK6-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
7395 // CHECK6-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
7396 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
7397 // CHECK6-NEXT:    ret i32 [[TMP8]]
7398 //
7399 //
7400 // CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
7401 // CHECK6-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
7402 // CHECK6-NEXT:  entry:
7403 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
7404 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7405 // CHECK6-NEXT:    [[B:%.*]] = alloca i32, align 4
7406 // CHECK6-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
7407 // CHECK6-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
7408 // CHECK6-NEXT:    [[IT:%.*]] = alloca i64, align 8
7409 // CHECK6-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
7410 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7411 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
7412 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7413 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7414 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
7415 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
7416 // CHECK6-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
7417 // CHECK6-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
7418 // CHECK6-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
7419 // CHECK6-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
7420 // CHECK6-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
7421 // CHECK6-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
7422 // CHECK6-NEXT:    store i64 2000, i64* [[IT]], align 8
7423 // CHECK6-NEXT:    br label [[FOR_COND:%.*]]
7424 // CHECK6:       for.cond:
7425 // CHECK6-NEXT:    [[TMP5:%.*]] = load i64, i64* [[IT]], align 8
7426 // CHECK6-NEXT:    [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600
7427 // CHECK6-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7428 // CHECK6:       for.body:
7429 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
7430 // CHECK6-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP6]] to double
7431 // CHECK6-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
7432 // CHECK6-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
7433 // CHECK6-NEXT:    store double [[ADD2]], double* [[A]], align 8
7434 // CHECK6-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
7435 // CHECK6-NEXT:    [[TMP7:%.*]] = load double, double* [[A3]], align 8
7436 // CHECK6-NEXT:    [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
7437 // CHECK6-NEXT:    store double [[INC]], double* [[A3]], align 8
7438 // CHECK6-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
7439 // CHECK6-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
7440 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
7441 // CHECK6-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
7442 // CHECK6-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
7443 // CHECK6-NEXT:    br label [[FOR_INC:%.*]]
7444 // CHECK6:       for.inc:
7445 // CHECK6-NEXT:    [[TMP9:%.*]] = load i64, i64* [[IT]], align 8
7446 // CHECK6-NEXT:    [[SUB:%.*]] = sub i64 [[TMP9]], 400
7447 // CHECK6-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
7448 // CHECK6-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
7449 // CHECK6:       for.end:
7450 // CHECK6-NEXT:    [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
7451 // CHECK6-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]]
7452 // CHECK6-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
7453 // CHECK6-NEXT:    [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
7454 // CHECK6-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP11]] to i32
7455 // CHECK6-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B]], align 4
7456 // CHECK6-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]]
7457 // CHECK6-NEXT:    [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
7458 // CHECK6-NEXT:    call void @llvm.stackrestore(i8* [[TMP13]])
7459 // CHECK6-NEXT:    ret i32 [[ADD9]]
7460 //
7461 //
7462 // CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici
7463 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
7464 // CHECK6-NEXT:  entry:
7465 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7466 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
7467 // CHECK6-NEXT:    [[AA:%.*]] = alloca i16, align 2
7468 // CHECK6-NEXT:    [[AAA:%.*]] = alloca i8, align 1
7469 // CHECK6-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7470 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
7471 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7472 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
7473 // CHECK6-NEXT:    store i16 0, i16* [[AA]], align 2
7474 // CHECK6-NEXT:    store i8 0, i8* [[AAA]], align 1
7475 // CHECK6-NEXT:    store i32 100, i32* [[I]], align 4
7476 // CHECK6-NEXT:    br label [[FOR_COND:%.*]]
7477 // CHECK6:       for.cond:
7478 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
7479 // CHECK6-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10
7480 // CHECK6-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7481 // CHECK6:       for.body:
7482 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7483 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
7484 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7485 // CHECK6-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
7486 // CHECK6-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
7487 // CHECK6-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
7488 // CHECK6-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
7489 // CHECK6-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
7490 // CHECK6-NEXT:    [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1
7491 // CHECK6-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
7492 // CHECK6-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
7493 // CHECK6-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
7494 // CHECK6-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
7495 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
7496 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7497 // CHECK6-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
7498 // CHECK6-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
7499 // CHECK6-NEXT:    br label [[FOR_INC:%.*]]
7500 // CHECK6:       for.inc:
7501 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
7502 // CHECK6-NEXT:    [[ADD7:%.*]] = add i32 [[TMP5]], 10
7503 // CHECK6-NEXT:    store i32 [[ADD7]], i32* [[I]], align 4
7504 // CHECK6-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
7505 // CHECK6:       for.end:
7506 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
7507 // CHECK6-NEXT:    ret i32 [[TMP6]]
7508 //
7509 //
7510 // CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
7511 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
7512 // CHECK6-NEXT:  entry:
7513 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7514 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
7515 // CHECK6-NEXT:    [[AA:%.*]] = alloca i16, align 2
7516 // CHECK6-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7517 // CHECK6-NEXT:    [[I:%.*]] = alloca i64, align 8
7518 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7519 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
7520 // CHECK6-NEXT:    store i16 0, i16* [[AA]], align 2
7521 // CHECK6-NEXT:    store i64 -10, i64* [[I]], align 8
7522 // CHECK6-NEXT:    br label [[FOR_COND:%.*]]
7523 // CHECK6:       for.cond:
7524 // CHECK6-NEXT:    [[TMP0:%.*]] = load i64, i64* [[I]], align 8
7525 // CHECK6-NEXT:    [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10
7526 // CHECK6-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7527 // CHECK6:       for.body:
7528 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7529 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
7530 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7531 // CHECK6-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
7532 // CHECK6-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
7533 // CHECK6-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
7534 // CHECK6-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
7535 // CHECK6-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
7536 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
7537 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7538 // CHECK6-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
7539 // CHECK6-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
7540 // CHECK6-NEXT:    br label [[FOR_INC:%.*]]
7541 // CHECK6:       for.inc:
7542 // CHECK6-NEXT:    [[TMP4:%.*]] = load i64, i64* [[I]], align 8
7543 // CHECK6-NEXT:    [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3
7544 // CHECK6-NEXT:    store i64 [[ADD4]], i64* [[I]], align 8
7545 // CHECK6-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
7546 // CHECK6:       for.end:
7547 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7548 // CHECK6-NEXT:    ret i32 [[TMP5]]
7549 //
7550 //
7551 // CHECK7-LABEL: define {{[^@]+}}@_Z7get_valv
7552 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
7553 // CHECK7-NEXT:  entry:
7554 // CHECK7-NEXT:    ret i64 0
7555 //
7556 //
7557 // CHECK7-LABEL: define {{[^@]+}}@_Z3fooi
7558 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
7559 // CHECK7-NEXT:  entry:
7560 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7561 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
7562 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
7563 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
7564 // CHECK7-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
7565 // CHECK7-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
7566 // CHECK7-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
7567 // CHECK7-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
7568 // CHECK7-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
7569 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
7570 // CHECK7-NEXT:    [[K:%.*]] = alloca i64, align 8
7571 // CHECK7-NEXT:    [[I2:%.*]] = alloca i32, align 4
7572 // CHECK7-NEXT:    [[LIN:%.*]] = alloca i32, align 4
7573 // CHECK7-NEXT:    [[IT:%.*]] = alloca i64, align 8
7574 // CHECK7-NEXT:    [[IT16:%.*]] = alloca i16, align 2
7575 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
7576 // CHECK7-NEXT:    [[IT30:%.*]] = alloca i8, align 1
7577 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7578 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
7579 // CHECK7-NEXT:    store i16 0, i16* [[AA]], align 2
7580 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7581 // CHECK7-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
7582 // CHECK7-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
7583 // CHECK7-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
7584 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
7585 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7586 // CHECK7-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
7587 // CHECK7-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
7588 // CHECK7-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
7589 // CHECK7-NEXT:    store i32 3, i32* [[I]], align 4
7590 // CHECK7-NEXT:    br label [[FOR_COND:%.*]]
7591 // CHECK7:       for.cond:
7592 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
7593 // CHECK7-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32
7594 // CHECK7-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7595 // CHECK7:       for.body:
7596 // CHECK7-NEXT:    br label [[FOR_INC:%.*]]
7597 // CHECK7:       for.inc:
7598 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
7599 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP5]], 5
7600 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
7601 // CHECK7-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
7602 // CHECK7:       for.end:
7603 // CHECK7-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
7604 // CHECK7-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
7605 // CHECK7-NEXT:    store i32 10, i32* [[I2]], align 4
7606 // CHECK7-NEXT:    br label [[FOR_COND3:%.*]]
7607 // CHECK7:       for.cond3:
7608 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I2]], align 4
7609 // CHECK7-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1
7610 // CHECK7-NEXT:    br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]]
7611 // CHECK7:       for.body5:
7612 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
7613 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1
7614 // CHECK7-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
7615 // CHECK7-NEXT:    br label [[FOR_INC7:%.*]]
7616 // CHECK7:       for.inc7:
7617 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I2]], align 4
7618 // CHECK7-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP8]], -1
7619 // CHECK7-NEXT:    store i32 [[DEC]], i32* [[I2]], align 4
7620 // CHECK7-NEXT:    br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]]
7621 // CHECK7:       for.end8:
7622 // CHECK7-NEXT:    store i32 12, i32* [[LIN]], align 4
7623 // CHECK7-NEXT:    store i64 2000, i64* [[IT]], align 8
7624 // CHECK7-NEXT:    br label [[FOR_COND9:%.*]]
7625 // CHECK7:       for.cond9:
7626 // CHECK7-NEXT:    [[TMP9:%.*]] = load i64, i64* [[IT]], align 8
7627 // CHECK7-NEXT:    [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600
7628 // CHECK7-NEXT:    br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]]
7629 // CHECK7:       for.body11:
7630 // CHECK7-NEXT:    [[TMP10:%.*]] = load i16, i16* [[AA]], align 2
7631 // CHECK7-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
7632 // CHECK7-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV]], 1
7633 // CHECK7-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
7634 // CHECK7-NEXT:    store i16 [[CONV13]], i16* [[AA]], align 2
7635 // CHECK7-NEXT:    br label [[FOR_INC14:%.*]]
7636 // CHECK7:       for.inc14:
7637 // CHECK7-NEXT:    [[TMP11:%.*]] = load i64, i64* [[IT]], align 8
7638 // CHECK7-NEXT:    [[SUB:%.*]] = sub i64 [[TMP11]], 400
7639 // CHECK7-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
7640 // CHECK7-NEXT:    br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]]
7641 // CHECK7:       for.end15:
7642 // CHECK7-NEXT:    store i16 6, i16* [[IT16]], align 2
7643 // CHECK7-NEXT:    br label [[FOR_COND17:%.*]]
7644 // CHECK7:       for.cond17:
7645 // CHECK7-NEXT:    [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2
7646 // CHECK7-NEXT:    [[CONV18:%.*]] = sext i16 [[TMP12]] to i32
7647 // CHECK7-NEXT:    [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20
7648 // CHECK7-NEXT:    br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]]
7649 // CHECK7:       for.body20:
7650 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4
7651 // CHECK7-NEXT:    [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1
7652 // CHECK7-NEXT:    store i32 [[ADD21]], i32* [[A]], align 4
7653 // CHECK7-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2
7654 // CHECK7-NEXT:    [[CONV22:%.*]] = sext i16 [[TMP14]] to i32
7655 // CHECK7-NEXT:    [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1
7656 // CHECK7-NEXT:    [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16
7657 // CHECK7-NEXT:    store i16 [[CONV24]], i16* [[AA]], align 2
7658 // CHECK7-NEXT:    br label [[FOR_INC25:%.*]]
7659 // CHECK7:       for.inc25:
7660 // CHECK7-NEXT:    [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2
7661 // CHECK7-NEXT:    [[CONV26:%.*]] = sext i16 [[TMP15]] to i32
7662 // CHECK7-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4
7663 // CHECK7-NEXT:    [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16
7664 // CHECK7-NEXT:    store i16 [[CONV28]], i16* [[IT16]], align 2
7665 // CHECK7-NEXT:    br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]]
7666 // CHECK7:       for.end29:
7667 // CHECK7-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4
7668 // CHECK7-NEXT:    store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4
7669 // CHECK7-NEXT:    store i8 122, i8* [[IT30]], align 1
7670 // CHECK7-NEXT:    br label [[FOR_COND31:%.*]]
7671 // CHECK7:       for.cond31:
7672 // CHECK7-NEXT:    [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1
7673 // CHECK7-NEXT:    [[CONV32:%.*]] = zext i8 [[TMP17]] to i32
7674 // CHECK7-NEXT:    [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97
7675 // CHECK7-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]]
7676 // CHECK7:       for.body34:
7677 // CHECK7-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
7678 // CHECK7-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1
7679 // CHECK7-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
7680 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
7681 // CHECK7-NEXT:    [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4
7682 // CHECK7-NEXT:    [[CONV36:%.*]] = fpext float [[TMP19]] to double
7683 // CHECK7-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
7684 // CHECK7-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
7685 // CHECK7-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
7686 // CHECK7-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
7687 // CHECK7-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4
7688 // CHECK7-NEXT:    [[CONV40:%.*]] = fpext float [[TMP20]] to double
7689 // CHECK7-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
7690 // CHECK7-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
7691 // CHECK7-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
7692 // CHECK7-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
7693 // CHECK7-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2
7694 // CHECK7-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8
7695 // CHECK7-NEXT:    [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00
7696 // CHECK7-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
7697 // CHECK7-NEXT:    [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]]
7698 // CHECK7-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]]
7699 // CHECK7-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3
7700 // CHECK7-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8
7701 // CHECK7-NEXT:    [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00
7702 // CHECK7-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
7703 // CHECK7-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
7704 // CHECK7-NEXT:    [[TMP24:%.*]] = load i64, i64* [[X]], align 4
7705 // CHECK7-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1
7706 // CHECK7-NEXT:    store i64 [[ADD49]], i64* [[X]], align 4
7707 // CHECK7-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
7708 // CHECK7-NEXT:    [[TMP25:%.*]] = load i8, i8* [[Y]], align 4
7709 // CHECK7-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP25]] to i32
7710 // CHECK7-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
7711 // CHECK7-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
7712 // CHECK7-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 4
7713 // CHECK7-NEXT:    br label [[FOR_INC53:%.*]]
7714 // CHECK7:       for.inc53:
7715 // CHECK7-NEXT:    [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1
7716 // CHECK7-NEXT:    [[CONV54:%.*]] = zext i8 [[TMP26]] to i32
7717 // CHECK7-NEXT:    [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1
7718 // CHECK7-NEXT:    [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8
7719 // CHECK7-NEXT:    store i8 [[CONV56]], i8* [[IT30]], align 1
7720 // CHECK7-NEXT:    br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]]
7721 // CHECK7:       for.end57:
7722 // CHECK7-NEXT:    [[TMP27:%.*]] = load i32, i32* [[A]], align 4
7723 // CHECK7-NEXT:    [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
7724 // CHECK7-NEXT:    call void @llvm.stackrestore(i8* [[TMP28]])
7725 // CHECK7-NEXT:    ret i32 [[TMP27]]
7726 //
7727 //
7728 // CHECK7-LABEL: define {{[^@]+}}@_Z3bari
7729 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
7730 // CHECK7-NEXT:  entry:
7731 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7732 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
7733 // CHECK7-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
7734 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7735 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
7736 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7737 // CHECK7-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
7738 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7739 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
7740 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7741 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7742 // CHECK7-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
7743 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7744 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
7745 // CHECK7-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
7746 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7747 // CHECK7-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
7748 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7749 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
7750 // CHECK7-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
7751 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
7752 // CHECK7-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
7753 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
7754 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
7755 // CHECK7-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
7756 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
7757 // CHECK7-NEXT:    ret i32 [[TMP8]]
7758 //
7759 //
7760 // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
7761 // CHECK7-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
7762 // CHECK7-NEXT:  entry:
7763 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7764 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7765 // CHECK7-NEXT:    [[B:%.*]] = alloca i32, align 4
7766 // CHECK7-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
7767 // CHECK7-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
7768 // CHECK7-NEXT:    [[IT:%.*]] = alloca i64, align 8
7769 // CHECK7-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7770 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7771 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7772 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7773 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7774 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
7775 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
7776 // CHECK7-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
7777 // CHECK7-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
7778 // CHECK7-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
7779 // CHECK7-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
7780 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
7781 // CHECK7-NEXT:    store i64 2000, i64* [[IT]], align 8
7782 // CHECK7-NEXT:    br label [[FOR_COND:%.*]]
7783 // CHECK7:       for.cond:
7784 // CHECK7-NEXT:    [[TMP4:%.*]] = load i64, i64* [[IT]], align 8
7785 // CHECK7-NEXT:    [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600
7786 // CHECK7-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7787 // CHECK7:       for.body:
7788 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
7789 // CHECK7-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
7790 // CHECK7-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
7791 // CHECK7-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
7792 // CHECK7-NEXT:    store double [[ADD2]], double* [[A]], align 4
7793 // CHECK7-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
7794 // CHECK7-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 4
7795 // CHECK7-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
7796 // CHECK7-NEXT:    store double [[INC]], double* [[A3]], align 4
7797 // CHECK7-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
7798 // CHECK7-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
7799 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
7800 // CHECK7-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
7801 // CHECK7-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
7802 // CHECK7-NEXT:    br label [[FOR_INC:%.*]]
7803 // CHECK7:       for.inc:
7804 // CHECK7-NEXT:    [[TMP8:%.*]] = load i64, i64* [[IT]], align 8
7805 // CHECK7-NEXT:    [[SUB:%.*]] = sub i64 [[TMP8]], 400
7806 // CHECK7-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
7807 // CHECK7-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
7808 // CHECK7:       for.end:
7809 // CHECK7-NEXT:    [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]]
7810 // CHECK7-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]]
7811 // CHECK7-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
7812 // CHECK7-NEXT:    [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
7813 // CHECK7-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP10]] to i32
7814 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4
7815 // CHECK7-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]]
7816 // CHECK7-NEXT:    [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
7817 // CHECK7-NEXT:    call void @llvm.stackrestore(i8* [[TMP12]])
7818 // CHECK7-NEXT:    ret i32 [[ADD9]]
7819 //
7820 //
7821 // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici
7822 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
7823 // CHECK7-NEXT:  entry:
7824 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7825 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
7826 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
7827 // CHECK7-NEXT:    [[AAA:%.*]] = alloca i8, align 1
7828 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7829 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
7830 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7831 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
7832 // CHECK7-NEXT:    store i16 0, i16* [[AA]], align 2
7833 // CHECK7-NEXT:    store i8 0, i8* [[AAA]], align 1
7834 // CHECK7-NEXT:    store i32 100, i32* [[I]], align 4
7835 // CHECK7-NEXT:    br label [[FOR_COND:%.*]]
7836 // CHECK7:       for.cond:
7837 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
7838 // CHECK7-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10
7839 // CHECK7-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7840 // CHECK7:       for.body:
7841 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7842 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
7843 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7844 // CHECK7-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
7845 // CHECK7-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
7846 // CHECK7-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
7847 // CHECK7-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
7848 // CHECK7-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
7849 // CHECK7-NEXT:    [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1
7850 // CHECK7-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
7851 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
7852 // CHECK7-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
7853 // CHECK7-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
7854 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
7855 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7856 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
7857 // CHECK7-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
7858 // CHECK7-NEXT:    br label [[FOR_INC:%.*]]
7859 // CHECK7:       for.inc:
7860 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
7861 // CHECK7-NEXT:    [[ADD7:%.*]] = add i32 [[TMP5]], 10
7862 // CHECK7-NEXT:    store i32 [[ADD7]], i32* [[I]], align 4
7863 // CHECK7-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
7864 // CHECK7:       for.end:
7865 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
7866 // CHECK7-NEXT:    ret i32 [[TMP6]]
7867 //
7868 //
7869 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
7870 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
7871 // CHECK7-NEXT:  entry:
7872 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7873 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
7874 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
7875 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7876 // CHECK7-NEXT:    [[I:%.*]] = alloca i64, align 8
7877 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7878 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
7879 // CHECK7-NEXT:    store i16 0, i16* [[AA]], align 2
7880 // CHECK7-NEXT:    store i64 -10, i64* [[I]], align 8
7881 // CHECK7-NEXT:    br label [[FOR_COND:%.*]]
7882 // CHECK7:       for.cond:
7883 // CHECK7-NEXT:    [[TMP0:%.*]] = load i64, i64* [[I]], align 8
7884 // CHECK7-NEXT:    [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10
7885 // CHECK7-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7886 // CHECK7:       for.body:
7887 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7888 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
7889 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7890 // CHECK7-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
7891 // CHECK7-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
7892 // CHECK7-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
7893 // CHECK7-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
7894 // CHECK7-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
7895 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
7896 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7897 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
7898 // CHECK7-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
7899 // CHECK7-NEXT:    br label [[FOR_INC:%.*]]
7900 // CHECK7:       for.inc:
7901 // CHECK7-NEXT:    [[TMP4:%.*]] = load i64, i64* [[I]], align 8
7902 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3
7903 // CHECK7-NEXT:    store i64 [[ADD4]], i64* [[I]], align 8
7904 // CHECK7-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
7905 // CHECK7:       for.end:
7906 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7907 // CHECK7-NEXT:    ret i32 [[TMP5]]
7908 //
7909 //
7910 // CHECK8-LABEL: define {{[^@]+}}@_Z7get_valv
7911 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] {
7912 // CHECK8-NEXT:  entry:
7913 // CHECK8-NEXT:    ret i64 0
7914 //
7915 //
7916 // CHECK8-LABEL: define {{[^@]+}}@_Z3fooi
7917 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
7918 // CHECK8-NEXT:  entry:
7919 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7920 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
7921 // CHECK8-NEXT:    [[AA:%.*]] = alloca i16, align 2
7922 // CHECK8-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
7923 // CHECK8-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
7924 // CHECK8-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
7925 // CHECK8-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
7926 // CHECK8-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
7927 // CHECK8-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
7928 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
7929 // CHECK8-NEXT:    [[K:%.*]] = alloca i64, align 8
7930 // CHECK8-NEXT:    [[I2:%.*]] = alloca i32, align 4
7931 // CHECK8-NEXT:    [[LIN:%.*]] = alloca i32, align 4
7932 // CHECK8-NEXT:    [[IT:%.*]] = alloca i64, align 8
7933 // CHECK8-NEXT:    [[IT16:%.*]] = alloca i16, align 2
7934 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
7935 // CHECK8-NEXT:    [[IT30:%.*]] = alloca i8, align 1
7936 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7937 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
7938 // CHECK8-NEXT:    store i16 0, i16* [[AA]], align 2
7939 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7940 // CHECK8-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
7941 // CHECK8-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
7942 // CHECK8-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
7943 // CHECK8-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
7944 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7945 // CHECK8-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
7946 // CHECK8-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
7947 // CHECK8-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
7948 // CHECK8-NEXT:    store i32 3, i32* [[I]], align 4
7949 // CHECK8-NEXT:    br label [[FOR_COND:%.*]]
7950 // CHECK8:       for.cond:
7951 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
7952 // CHECK8-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32
7953 // CHECK8-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7954 // CHECK8:       for.body:
7955 // CHECK8-NEXT:    br label [[FOR_INC:%.*]]
7956 // CHECK8:       for.inc:
7957 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
7958 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP5]], 5
7959 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
7960 // CHECK8-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
7961 // CHECK8:       for.end:
7962 // CHECK8-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
7963 // CHECK8-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
7964 // CHECK8-NEXT:    store i32 10, i32* [[I2]], align 4
7965 // CHECK8-NEXT:    br label [[FOR_COND3:%.*]]
7966 // CHECK8:       for.cond3:
7967 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I2]], align 4
7968 // CHECK8-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1
7969 // CHECK8-NEXT:    br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]]
7970 // CHECK8:       for.body5:
7971 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
7972 // CHECK8-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1
7973 // CHECK8-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
7974 // CHECK8-NEXT:    br label [[FOR_INC7:%.*]]
7975 // CHECK8:       for.inc7:
7976 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I2]], align 4
7977 // CHECK8-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP8]], -1
7978 // CHECK8-NEXT:    store i32 [[DEC]], i32* [[I2]], align 4
7979 // CHECK8-NEXT:    br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]]
7980 // CHECK8:       for.end8:
7981 // CHECK8-NEXT:    store i32 12, i32* [[LIN]], align 4
7982 // CHECK8-NEXT:    store i64 2000, i64* [[IT]], align 8
7983 // CHECK8-NEXT:    br label [[FOR_COND9:%.*]]
7984 // CHECK8:       for.cond9:
7985 // CHECK8-NEXT:    [[TMP9:%.*]] = load i64, i64* [[IT]], align 8
7986 // CHECK8-NEXT:    [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600
7987 // CHECK8-NEXT:    br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]]
7988 // CHECK8:       for.body11:
7989 // CHECK8-NEXT:    [[TMP10:%.*]] = load i16, i16* [[AA]], align 2
7990 // CHECK8-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
7991 // CHECK8-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV]], 1
7992 // CHECK8-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
7993 // CHECK8-NEXT:    store i16 [[CONV13]], i16* [[AA]], align 2
7994 // CHECK8-NEXT:    br label [[FOR_INC14:%.*]]
7995 // CHECK8:       for.inc14:
7996 // CHECK8-NEXT:    [[TMP11:%.*]] = load i64, i64* [[IT]], align 8
7997 // CHECK8-NEXT:    [[SUB:%.*]] = sub i64 [[TMP11]], 400
7998 // CHECK8-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
7999 // CHECK8-NEXT:    br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]]
8000 // CHECK8:       for.end15:
8001 // CHECK8-NEXT:    store i16 6, i16* [[IT16]], align 2
8002 // CHECK8-NEXT:    br label [[FOR_COND17:%.*]]
8003 // CHECK8:       for.cond17:
8004 // CHECK8-NEXT:    [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2
8005 // CHECK8-NEXT:    [[CONV18:%.*]] = sext i16 [[TMP12]] to i32
8006 // CHECK8-NEXT:    [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20
8007 // CHECK8-NEXT:    br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]]
8008 // CHECK8:       for.body20:
8009 // CHECK8-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4
8010 // CHECK8-NEXT:    [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1
8011 // CHECK8-NEXT:    store i32 [[ADD21]], i32* [[A]], align 4
8012 // CHECK8-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2
8013 // CHECK8-NEXT:    [[CONV22:%.*]] = sext i16 [[TMP14]] to i32
8014 // CHECK8-NEXT:    [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1
8015 // CHECK8-NEXT:    [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16
8016 // CHECK8-NEXT:    store i16 [[CONV24]], i16* [[AA]], align 2
8017 // CHECK8-NEXT:    br label [[FOR_INC25:%.*]]
8018 // CHECK8:       for.inc25:
8019 // CHECK8-NEXT:    [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2
8020 // CHECK8-NEXT:    [[CONV26:%.*]] = sext i16 [[TMP15]] to i32
8021 // CHECK8-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4
8022 // CHECK8-NEXT:    [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16
8023 // CHECK8-NEXT:    store i16 [[CONV28]], i16* [[IT16]], align 2
8024 // CHECK8-NEXT:    br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]]
8025 // CHECK8:       for.end29:
8026 // CHECK8-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4
8027 // CHECK8-NEXT:    store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4
8028 // CHECK8-NEXT:    store i8 122, i8* [[IT30]], align 1
8029 // CHECK8-NEXT:    br label [[FOR_COND31:%.*]]
8030 // CHECK8:       for.cond31:
8031 // CHECK8-NEXT:    [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1
8032 // CHECK8-NEXT:    [[CONV32:%.*]] = zext i8 [[TMP17]] to i32
8033 // CHECK8-NEXT:    [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97
8034 // CHECK8-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]]
8035 // CHECK8:       for.body34:
8036 // CHECK8-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
8037 // CHECK8-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1
8038 // CHECK8-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
8039 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
8040 // CHECK8-NEXT:    [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4
8041 // CHECK8-NEXT:    [[CONV36:%.*]] = fpext float [[TMP19]] to double
8042 // CHECK8-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
8043 // CHECK8-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
8044 // CHECK8-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
8045 // CHECK8-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
8046 // CHECK8-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4
8047 // CHECK8-NEXT:    [[CONV40:%.*]] = fpext float [[TMP20]] to double
8048 // CHECK8-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
8049 // CHECK8-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
8050 // CHECK8-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
8051 // CHECK8-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
8052 // CHECK8-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2
8053 // CHECK8-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8
8054 // CHECK8-NEXT:    [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00
8055 // CHECK8-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
8056 // CHECK8-NEXT:    [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]]
8057 // CHECK8-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]]
8058 // CHECK8-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3
8059 // CHECK8-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8
8060 // CHECK8-NEXT:    [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00
8061 // CHECK8-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
8062 // CHECK8-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
8063 // CHECK8-NEXT:    [[TMP24:%.*]] = load i64, i64* [[X]], align 4
8064 // CHECK8-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1
8065 // CHECK8-NEXT:    store i64 [[ADD49]], i64* [[X]], align 4
8066 // CHECK8-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
8067 // CHECK8-NEXT:    [[TMP25:%.*]] = load i8, i8* [[Y]], align 4
8068 // CHECK8-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP25]] to i32
8069 // CHECK8-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
8070 // CHECK8-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
8071 // CHECK8-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 4
8072 // CHECK8-NEXT:    br label [[FOR_INC53:%.*]]
8073 // CHECK8:       for.inc53:
8074 // CHECK8-NEXT:    [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1
8075 // CHECK8-NEXT:    [[CONV54:%.*]] = zext i8 [[TMP26]] to i32
8076 // CHECK8-NEXT:    [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1
8077 // CHECK8-NEXT:    [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8
8078 // CHECK8-NEXT:    store i8 [[CONV56]], i8* [[IT30]], align 1
8079 // CHECK8-NEXT:    br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]]
8080 // CHECK8:       for.end57:
8081 // CHECK8-NEXT:    [[TMP27:%.*]] = load i32, i32* [[A]], align 4
8082 // CHECK8-NEXT:    [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
8083 // CHECK8-NEXT:    call void @llvm.stackrestore(i8* [[TMP28]])
8084 // CHECK8-NEXT:    ret i32 [[TMP27]]
8085 //
8086 //
8087 // CHECK8-LABEL: define {{[^@]+}}@_Z3bari
8088 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
8089 // CHECK8-NEXT:  entry:
8090 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8091 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
8092 // CHECK8-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
8093 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8094 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
8095 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8096 // CHECK8-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
8097 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
8098 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
8099 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
8100 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
8101 // CHECK8-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
8102 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
8103 // CHECK8-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
8104 // CHECK8-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
8105 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
8106 // CHECK8-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
8107 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
8108 // CHECK8-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
8109 // CHECK8-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
8110 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
8111 // CHECK8-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
8112 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
8113 // CHECK8-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
8114 // CHECK8-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
8115 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
8116 // CHECK8-NEXT:    ret i32 [[TMP8]]
8117 //
8118 //
8119 // CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
8120 // CHECK8-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
8121 // CHECK8-NEXT:  entry:
8122 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
8123 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8124 // CHECK8-NEXT:    [[B:%.*]] = alloca i32, align 4
8125 // CHECK8-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
8126 // CHECK8-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
8127 // CHECK8-NEXT:    [[IT:%.*]] = alloca i64, align 8
8128 // CHECK8-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
8129 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8130 // CHECK8-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
8131 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8132 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
8133 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
8134 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
8135 // CHECK8-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
8136 // CHECK8-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
8137 // CHECK8-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
8138 // CHECK8-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
8139 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
8140 // CHECK8-NEXT:    store i64 2000, i64* [[IT]], align 8
8141 // CHECK8-NEXT:    br label [[FOR_COND:%.*]]
8142 // CHECK8:       for.cond:
8143 // CHECK8-NEXT:    [[TMP4:%.*]] = load i64, i64* [[IT]], align 8
8144 // CHECK8-NEXT:    [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600
8145 // CHECK8-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
8146 // CHECK8:       for.body:
8147 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
8148 // CHECK8-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
8149 // CHECK8-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
8150 // CHECK8-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
8151 // CHECK8-NEXT:    store double [[ADD2]], double* [[A]], align 4
8152 // CHECK8-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
8153 // CHECK8-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 4
8154 // CHECK8-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
8155 // CHECK8-NEXT:    store double [[INC]], double* [[A3]], align 4
8156 // CHECK8-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
8157 // CHECK8-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
8158 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
8159 // CHECK8-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
8160 // CHECK8-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
8161 // CHECK8-NEXT:    br label [[FOR_INC:%.*]]
8162 // CHECK8:       for.inc:
8163 // CHECK8-NEXT:    [[TMP8:%.*]] = load i64, i64* [[IT]], align 8
8164 // CHECK8-NEXT:    [[SUB:%.*]] = sub i64 [[TMP8]], 400
8165 // CHECK8-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
8166 // CHECK8-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
8167 // CHECK8:       for.end:
8168 // CHECK8-NEXT:    [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]]
8169 // CHECK8-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]]
8170 // CHECK8-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
8171 // CHECK8-NEXT:    [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
8172 // CHECK8-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP10]] to i32
8173 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4
8174 // CHECK8-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]]
8175 // CHECK8-NEXT:    [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
8176 // CHECK8-NEXT:    call void @llvm.stackrestore(i8* [[TMP12]])
8177 // CHECK8-NEXT:    ret i32 [[ADD9]]
8178 //
8179 //
8180 // CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici
8181 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
8182 // CHECK8-NEXT:  entry:
8183 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8184 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
8185 // CHECK8-NEXT:    [[AA:%.*]] = alloca i16, align 2
8186 // CHECK8-NEXT:    [[AAA:%.*]] = alloca i8, align 1
8187 // CHECK8-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8188 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
8189 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8190 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
8191 // CHECK8-NEXT:    store i16 0, i16* [[AA]], align 2
8192 // CHECK8-NEXT:    store i8 0, i8* [[AAA]], align 1
8193 // CHECK8-NEXT:    store i32 100, i32* [[I]], align 4
8194 // CHECK8-NEXT:    br label [[FOR_COND:%.*]]
8195 // CHECK8:       for.cond:
8196 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
8197 // CHECK8-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10
8198 // CHECK8-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
8199 // CHECK8:       for.body:
8200 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
8201 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
8202 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
8203 // CHECK8-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
8204 // CHECK8-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
8205 // CHECK8-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
8206 // CHECK8-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
8207 // CHECK8-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
8208 // CHECK8-NEXT:    [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1
8209 // CHECK8-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
8210 // CHECK8-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
8211 // CHECK8-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
8212 // CHECK8-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
8213 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
8214 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
8215 // CHECK8-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
8216 // CHECK8-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
8217 // CHECK8-NEXT:    br label [[FOR_INC:%.*]]
8218 // CHECK8:       for.inc:
8219 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
8220 // CHECK8-NEXT:    [[ADD7:%.*]] = add i32 [[TMP5]], 10
8221 // CHECK8-NEXT:    store i32 [[ADD7]], i32* [[I]], align 4
8222 // CHECK8-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
8223 // CHECK8:       for.end:
8224 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
8225 // CHECK8-NEXT:    ret i32 [[TMP6]]
8226 //
8227 //
8228 // CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
8229 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
8230 // CHECK8-NEXT:  entry:
8231 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8232 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
8233 // CHECK8-NEXT:    [[AA:%.*]] = alloca i16, align 2
8234 // CHECK8-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8235 // CHECK8-NEXT:    [[I:%.*]] = alloca i64, align 8
8236 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8237 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
8238 // CHECK8-NEXT:    store i16 0, i16* [[AA]], align 2
8239 // CHECK8-NEXT:    store i64 -10, i64* [[I]], align 8
8240 // CHECK8-NEXT:    br label [[FOR_COND:%.*]]
8241 // CHECK8:       for.cond:
8242 // CHECK8-NEXT:    [[TMP0:%.*]] = load i64, i64* [[I]], align 8
8243 // CHECK8-NEXT:    [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10
8244 // CHECK8-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
8245 // CHECK8:       for.body:
8246 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
8247 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
8248 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
8249 // CHECK8-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
8250 // CHECK8-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
8251 // CHECK8-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
8252 // CHECK8-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
8253 // CHECK8-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
8254 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
8255 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
8256 // CHECK8-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
8257 // CHECK8-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
8258 // CHECK8-NEXT:    br label [[FOR_INC:%.*]]
8259 // CHECK8:       for.inc:
8260 // CHECK8-NEXT:    [[TMP4:%.*]] = load i64, i64* [[I]], align 8
8261 // CHECK8-NEXT:    [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3
8262 // CHECK8-NEXT:    store i64 [[ADD4]], i64* [[I]], align 8
8263 // CHECK8-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
8264 // CHECK8:       for.end:
8265 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
8266 // CHECK8-NEXT:    ret i32 [[TMP5]]
8267 //
8268 //
8269 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
8270 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
8271 // CHECK9-NEXT:  entry:
8272 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
8273 // CHECK9-NEXT:    ret void
8274 //
8275 //
8276 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
8277 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
8278 // CHECK9-NEXT:  entry:
8279 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8280 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8281 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8282 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8283 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8284 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8285 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
8286 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8287 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
8288 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8289 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8290 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8291 // CHECK9-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
8292 // CHECK9-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
8293 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8294 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8295 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
8296 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
8297 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8298 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
8299 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8300 // CHECK9:       cond.true:
8301 // CHECK9-NEXT:    br label [[COND_END:%.*]]
8302 // CHECK9:       cond.false:
8303 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8304 // CHECK9-NEXT:    br label [[COND_END]]
8305 // CHECK9:       cond.end:
8306 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
8307 // CHECK9-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
8308 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8309 // CHECK9-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
8310 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8311 // CHECK9:       omp.inner.for.cond:
8312 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8313 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8314 // CHECK9-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
8315 // CHECK9-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8316 // CHECK9:       omp.inner.for.body:
8317 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8318 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
8319 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
8320 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
8321 // CHECK9-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
8322 // CHECK9-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
8323 // CHECK9-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
8324 // CHECK9:       .cancel.exit:
8325 // CHECK9-NEXT:    br label [[CANCEL_EXIT:%.*]]
8326 // CHECK9:       .cancel.continue:
8327 // CHECK9-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
8328 // CHECK9-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
8329 // CHECK9-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
8330 // CHECK9:       .cancel.exit2:
8331 // CHECK9-NEXT:    br label [[CANCEL_EXIT]]
8332 // CHECK9:       .cancel.continue3:
8333 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8334 // CHECK9:       omp.body.continue:
8335 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8336 // CHECK9:       omp.inner.for.inc:
8337 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8338 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
8339 // CHECK9-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
8340 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]
8341 // CHECK9:       omp.inner.for.end:
8342 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
8343 // CHECK9:       omp.loop.exit:
8344 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
8345 // CHECK9-NEXT:    br label [[CANCEL_CONT:%.*]]
8346 // CHECK9:       cancel.cont:
8347 // CHECK9-NEXT:    ret void
8348 // CHECK9:       cancel.exit:
8349 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
8350 // CHECK9-NEXT:    br label [[CANCEL_CONT]]
8351 //
8352 //
8353 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
8354 // CHECK9-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
8355 // CHECK9-NEXT:  entry:
8356 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8357 // CHECK9-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
8358 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8359 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8360 // CHECK9-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
8361 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8362 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8363 // CHECK9-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
8364 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8365 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8366 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
8367 // CHECK9-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8368 // CHECK9-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
8369 // CHECK9-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8370 // CHECK9-NEXT:    store i16 [[TMP0]], i16* [[CONV3]], align 2
8371 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8372 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
8373 // CHECK9-NEXT:    [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
8374 // CHECK9-NEXT:    store i32 [[TMP2]], i32* [[CONV4]], align 4
8375 // CHECK9-NEXT:    [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
8376 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
8377 // CHECK9-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8378 // CHECK9-NEXT:    store i32 [[TMP4]], i32* [[CONV5]], align 4
8379 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
8380 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
8381 // CHECK9-NEXT:    ret void
8382 //
8383 //
8384 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
8385 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
8386 // CHECK9-NEXT:  entry:
8387 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8388 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8389 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8390 // CHECK9-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
8391 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8392 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
8393 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i64, align 8
8394 // CHECK9-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
8395 // CHECK9-NEXT:    [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
8396 // CHECK9-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
8397 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
8398 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
8399 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
8400 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8401 // CHECK9-NEXT:    [[IT:%.*]] = alloca i64, align 8
8402 // CHECK9-NEXT:    [[LIN4:%.*]] = alloca i32, align 4
8403 // CHECK9-NEXT:    [[A5:%.*]] = alloca i32, align 4
8404 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8405 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8406 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8407 // CHECK9-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
8408 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8409 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8410 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
8411 // CHECK9-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8412 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
8413 // CHECK9-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
8414 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
8415 // CHECK9-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
8416 // CHECK9-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]]
8417 // CHECK9-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
8418 // CHECK9-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
8419 // CHECK9-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
8420 // CHECK9-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
8421 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8422 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8423 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
8424 // CHECK9-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
8425 // CHECK9-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
8426 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8427 // CHECK9-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
8428 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8429 // CHECK9:       cond.true:
8430 // CHECK9-NEXT:    br label [[COND_END:%.*]]
8431 // CHECK9:       cond.false:
8432 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8433 // CHECK9-NEXT:    br label [[COND_END]]
8434 // CHECK9:       cond.end:
8435 // CHECK9-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
8436 // CHECK9-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
8437 // CHECK9-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
8438 // CHECK9-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
8439 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8440 // CHECK9:       omp.inner.for.cond:
8441 // CHECK9-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
8442 // CHECK9-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8443 // CHECK9-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
8444 // CHECK9-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8445 // CHECK9:       omp.inner.for.body:
8446 // CHECK9-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
8447 // CHECK9-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
8448 // CHECK9-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
8449 // CHECK9-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
8450 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
8451 // CHECK9-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
8452 // CHECK9-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
8453 // CHECK9-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
8454 // CHECK9-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
8455 // CHECK9-NEXT:    [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
8456 // CHECK9-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
8457 // CHECK9-NEXT:    store i32 [[CONV9]], i32* [[LIN4]], align 4
8458 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
8459 // CHECK9-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
8460 // CHECK9-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
8461 // CHECK9-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
8462 // CHECK9-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
8463 // CHECK9-NEXT:    [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
8464 // CHECK9-NEXT:    [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
8465 // CHECK9-NEXT:    store i32 [[CONV13]], i32* [[A5]], align 4
8466 // CHECK9-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8
8467 // CHECK9-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
8468 // CHECK9-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
8469 // CHECK9-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
8470 // CHECK9-NEXT:    store i16 [[CONV16]], i16* [[CONV]], align 8
8471 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8472 // CHECK9:       omp.body.continue:
8473 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8474 // CHECK9:       omp.inner.for.inc:
8475 // CHECK9-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
8476 // CHECK9-NEXT:    [[ADD17:%.*]] = add i64 [[TMP17]], 1
8477 // CHECK9-NEXT:    store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
8478 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]
8479 // CHECK9:       omp.inner.for.end:
8480 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
8481 // CHECK9:       omp.loop.exit:
8482 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
8483 // CHECK9-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
8484 // CHECK9-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
8485 // CHECK9-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
8486 // CHECK9:       .omp.linear.pu:
8487 // CHECK9-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
8488 // CHECK9-NEXT:    [[CONV18:%.*]] = sext i32 [[TMP20]] to i64
8489 // CHECK9-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
8490 // CHECK9-NEXT:    [[MUL19:%.*]] = mul i64 4, [[TMP21]]
8491 // CHECK9-NEXT:    [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
8492 // CHECK9-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
8493 // CHECK9-NEXT:    store i32 [[CONV21]], i32* [[CONV1]], align 8
8494 // CHECK9-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
8495 // CHECK9-NEXT:    [[CONV22:%.*]] = sext i32 [[TMP22]] to i64
8496 // CHECK9-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
8497 // CHECK9-NEXT:    [[MUL23:%.*]] = mul i64 4, [[TMP23]]
8498 // CHECK9-NEXT:    [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
8499 // CHECK9-NEXT:    [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
8500 // CHECK9-NEXT:    store i32 [[CONV25]], i32* [[CONV2]], align 8
8501 // CHECK9-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
8502 // CHECK9:       .omp.linear.pu.done:
8503 // CHECK9-NEXT:    ret void
8504 //
8505 //
8506 // CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv
8507 // CHECK9-SAME: () #[[ATTR2:[0-9]+]] {
8508 // CHECK9-NEXT:  entry:
8509 // CHECK9-NEXT:    ret i64 0
8510 //
8511 //
8512 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
8513 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
8514 // CHECK9-NEXT:  entry:
8515 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8516 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8517 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8518 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8519 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8520 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8521 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8522 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8523 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
8524 // CHECK9-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8525 // CHECK9-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
8526 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
8527 // CHECK9-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
8528 // CHECK9-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8529 // CHECK9-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
8530 // CHECK9-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8531 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
8532 // CHECK9-NEXT:    ret void
8533 //
8534 //
8535 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
8536 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
8537 // CHECK9-NEXT:  entry:
8538 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8539 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8540 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8541 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8542 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8543 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i16, align 2
8544 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8545 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8546 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
8547 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8548 // CHECK9-NEXT:    [[IT:%.*]] = alloca i16, align 2
8549 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8550 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8551 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8552 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8553 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8554 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8555 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8556 // CHECK9-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
8557 // CHECK9-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
8558 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8559 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8560 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
8561 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
8562 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8563 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
8564 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8565 // CHECK9:       cond.true:
8566 // CHECK9-NEXT:    br label [[COND_END:%.*]]
8567 // CHECK9:       cond.false:
8568 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8569 // CHECK9-NEXT:    br label [[COND_END]]
8570 // CHECK9:       cond.end:
8571 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
8572 // CHECK9-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
8573 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8574 // CHECK9-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
8575 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8576 // CHECK9:       omp.inner.for.cond:
8577 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8578 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8579 // CHECK9-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
8580 // CHECK9-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8581 // CHECK9:       omp.inner.for.body:
8582 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8583 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
8584 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
8585 // CHECK9-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
8586 // CHECK9-NEXT:    store i16 [[CONV3]], i16* [[IT]], align 2
8587 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
8588 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
8589 // CHECK9-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8
8590 // CHECK9-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
8591 // CHECK9-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
8592 // CHECK9-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
8593 // CHECK9-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
8594 // CHECK9-NEXT:    store i16 [[CONV7]], i16* [[CONV1]], align 8
8595 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8596 // CHECK9:       omp.body.continue:
8597 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8598 // CHECK9:       omp.inner.for.inc:
8599 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8600 // CHECK9-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
8601 // CHECK9-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
8602 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]
8603 // CHECK9:       omp.inner.for.end:
8604 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
8605 // CHECK9:       omp.loop.exit:
8606 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
8607 // CHECK9-NEXT:    ret void
8608 //
8609 //
8610 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
8611 // CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
8612 // CHECK9-NEXT:  entry:
8613 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8614 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
8615 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
8616 // CHECK9-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
8617 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
8618 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
8619 // CHECK9-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
8620 // CHECK9-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
8621 // CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
8622 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
8623 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8624 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
8625 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8626 // CHECK9-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
8627 // CHECK9-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
8628 // CHECK9-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
8629 // CHECK9-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
8630 // CHECK9-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
8631 // CHECK9-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
8632 // CHECK9-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
8633 // CHECK9-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
8634 // CHECK9-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
8635 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8636 // CHECK9-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
8637 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
8638 // CHECK9-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
8639 // CHECK9-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
8640 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
8641 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
8642 // CHECK9-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
8643 // CHECK9-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
8644 // CHECK9-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
8645 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
8646 // CHECK9-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8647 // CHECK9-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
8648 // CHECK9-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
8649 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
8650 // CHECK9-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
8651 // CHECK9-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
8652 // CHECK9-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
8653 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
8654 // CHECK9-NEXT:    ret void
8655 //
8656 //
8657 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
8658 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
8659 // CHECK9-NEXT:  entry:
8660 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8661 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8662 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8663 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
8664 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
8665 // CHECK9-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
8666 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
8667 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
8668 // CHECK9-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
8669 // CHECK9-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
8670 // CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
8671 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
8672 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8673 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i8, align 1
8674 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8675 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8676 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
8677 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8678 // CHECK9-NEXT:    [[IT:%.*]] = alloca i8, align 1
8679 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8680 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8681 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8682 // CHECK9-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
8683 // CHECK9-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
8684 // CHECK9-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
8685 // CHECK9-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
8686 // CHECK9-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
8687 // CHECK9-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
8688 // CHECK9-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
8689 // CHECK9-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
8690 // CHECK9-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
8691 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8692 // CHECK9-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
8693 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
8694 // CHECK9-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
8695 // CHECK9-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
8696 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
8697 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
8698 // CHECK9-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
8699 // CHECK9-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
8700 // CHECK9-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
8701 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8702 // CHECK9-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
8703 // CHECK9-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
8704 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8705 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
8706 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8707 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
8708 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
8709 // CHECK9-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
8710 // CHECK9:       omp.dispatch.cond:
8711 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8712 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
8713 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8714 // CHECK9:       cond.true:
8715 // CHECK9-NEXT:    br label [[COND_END:%.*]]
8716 // CHECK9:       cond.false:
8717 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8718 // CHECK9-NEXT:    br label [[COND_END]]
8719 // CHECK9:       cond.end:
8720 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
8721 // CHECK9-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
8722 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8723 // CHECK9-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
8724 // CHECK9-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8725 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8726 // CHECK9-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
8727 // CHECK9-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
8728 // CHECK9:       omp.dispatch.body:
8729 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8730 // CHECK9:       omp.inner.for.cond:
8731 // CHECK9-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8732 // CHECK9-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8733 // CHECK9-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
8734 // CHECK9-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8735 // CHECK9:       omp.inner.for.body:
8736 // CHECK9-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8737 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
8738 // CHECK9-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
8739 // CHECK9-NEXT:    [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
8740 // CHECK9-NEXT:    store i8 [[CONV8]], i8* [[IT]], align 1
8741 // CHECK9-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
8742 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
8743 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
8744 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
8745 // CHECK9-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
8746 // CHECK9-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
8747 // CHECK9-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
8748 // CHECK9-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
8749 // CHECK9-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
8750 // CHECK9-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
8751 // CHECK9-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
8752 // CHECK9-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
8753 // CHECK9-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
8754 // CHECK9-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
8755 // CHECK9-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
8756 // CHECK9-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
8757 // CHECK9-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
8758 // CHECK9-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
8759 // CHECK9-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
8760 // CHECK9-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
8761 // CHECK9-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
8762 // CHECK9-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
8763 // CHECK9-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
8764 // CHECK9-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
8765 // CHECK9-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
8766 // CHECK9-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
8767 // CHECK9-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
8768 // CHECK9-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8
8769 // CHECK9-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
8770 // CHECK9-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8
8771 // CHECK9-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
8772 // CHECK9-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
8773 // CHECK9-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
8774 // CHECK9-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
8775 // CHECK9-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
8776 // CHECK9-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8
8777 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8778 // CHECK9:       omp.body.continue:
8779 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8780 // CHECK9:       omp.inner.for.inc:
8781 // CHECK9-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8782 // CHECK9-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
8783 // CHECK9-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
8784 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]
8785 // CHECK9:       omp.inner.for.end:
8786 // CHECK9-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
8787 // CHECK9:       omp.dispatch.inc:
8788 // CHECK9-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8789 // CHECK9-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
8790 // CHECK9-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
8791 // CHECK9-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
8792 // CHECK9-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8793 // CHECK9-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
8794 // CHECK9-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
8795 // CHECK9-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
8796 // CHECK9-NEXT:    br label [[OMP_DISPATCH_COND]]
8797 // CHECK9:       omp.dispatch.end:
8798 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
8799 // CHECK9-NEXT:    ret void
8800 //
8801 //
8802 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
8803 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
8804 // CHECK9-NEXT:  entry:
8805 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8806 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8807 // CHECK9-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
8808 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
8809 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8810 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8811 // CHECK9-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
8812 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8813 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8814 // CHECK9-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
8815 // CHECK9-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
8816 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8817 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8818 // CHECK9-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
8819 // CHECK9-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
8820 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
8821 // CHECK9-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8822 // CHECK9-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
8823 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
8824 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
8825 // CHECK9-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8826 // CHECK9-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
8827 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8828 // CHECK9-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
8829 // CHECK9-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
8830 // CHECK9-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
8831 // CHECK9-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
8832 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
8833 // CHECK9-NEXT:    ret void
8834 //
8835 //
8836 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4
8837 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
8838 // CHECK9-NEXT:  entry:
8839 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8840 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8841 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8842 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8843 // CHECK9-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
8844 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
8845 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8846 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8847 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8848 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8849 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8850 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8851 // CHECK9-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
8852 // CHECK9-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
8853 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8854 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8855 // CHECK9-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
8856 // CHECK9-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
8857 // CHECK9-NEXT:    ret void
8858 //
8859 //
8860 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
8861 // CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
8862 // CHECK9-NEXT:  entry:
8863 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
8864 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
8865 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
8866 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
8867 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
8868 // CHECK9-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
8869 // CHECK9-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
8870 // CHECK9-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
8871 // CHECK9-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
8872 // CHECK9-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
8873 // CHECK9-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
8874 // CHECK9-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
8875 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
8876 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
8877 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
8878 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
8879 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
8880 // CHECK9-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
8881 // CHECK9-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
8882 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
8883 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
8884 // CHECK9-NEXT:    ret void
8885 //
8886 //
8887 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
8888 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
8889 // CHECK9-NEXT:  entry:
8890 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8891 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8892 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
8893 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
8894 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
8895 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
8896 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
8897 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
8898 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i64, align 8
8899 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
8900 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
8901 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
8902 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8903 // CHECK9-NEXT:    [[IT:%.*]] = alloca i64, align 8
8904 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8905 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8906 // CHECK9-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
8907 // CHECK9-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
8908 // CHECK9-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
8909 // CHECK9-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
8910 // CHECK9-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
8911 // CHECK9-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
8912 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
8913 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
8914 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
8915 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
8916 // CHECK9-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
8917 // CHECK9-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
8918 // CHECK9-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
8919 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8920 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8921 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
8922 // CHECK9-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
8923 // CHECK9-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8924 // CHECK9-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
8925 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8926 // CHECK9:       cond.true:
8927 // CHECK9-NEXT:    br label [[COND_END:%.*]]
8928 // CHECK9:       cond.false:
8929 // CHECK9-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8930 // CHECK9-NEXT:    br label [[COND_END]]
8931 // CHECK9:       cond.end:
8932 // CHECK9-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
8933 // CHECK9-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
8934 // CHECK9-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
8935 // CHECK9-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
8936 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8937 // CHECK9:       omp.inner.for.cond:
8938 // CHECK9-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
8939 // CHECK9-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8940 // CHECK9-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
8941 // CHECK9-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8942 // CHECK9:       omp.inner.for.body:
8943 // CHECK9-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
8944 // CHECK9-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
8945 // CHECK9-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
8946 // CHECK9-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
8947 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
8948 // CHECK9-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
8949 // CHECK9-NEXT:    [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
8950 // CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
8951 // CHECK9-NEXT:    store double [[ADD]], double* [[A]], align 8
8952 // CHECK9-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
8953 // CHECK9-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 8
8954 // CHECK9-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
8955 // CHECK9-NEXT:    store double [[INC]], double* [[A5]], align 8
8956 // CHECK9-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
8957 // CHECK9-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
8958 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
8959 // CHECK9-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
8960 // CHECK9-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
8961 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8962 // CHECK9:       omp.body.continue:
8963 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8964 // CHECK9:       omp.inner.for.inc:
8965 // CHECK9-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
8966 // CHECK9-NEXT:    [[ADD8:%.*]] = add i64 [[TMP15]], 1
8967 // CHECK9-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
8968 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]
8969 // CHECK9:       omp.inner.for.end:
8970 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
8971 // CHECK9:       omp.loop.exit:
8972 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
8973 // CHECK9-NEXT:    ret void
8974 //
8975 //
8976 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
8977 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
8978 // CHECK9-NEXT:  entry:
8979 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8980 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8981 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
8982 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8983 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8984 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8985 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8986 // CHECK9-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
8987 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8988 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8989 // CHECK9-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
8990 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
8991 // CHECK9-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8992 // CHECK9-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
8993 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
8994 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
8995 // CHECK9-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8996 // CHECK9-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
8997 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8998 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
8999 // CHECK9-NEXT:    ret void
9000 //
9001 //
9002 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6
9003 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
9004 // CHECK9-NEXT:  entry:
9005 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9006 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9007 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9008 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9009 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9010 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
9011 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i64, align 8
9012 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
9013 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
9014 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
9015 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9016 // CHECK9-NEXT:    [[I:%.*]] = alloca i64, align 8
9017 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9018 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9019 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9020 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9021 // CHECK9-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9022 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9023 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9024 // CHECK9-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9025 // CHECK9-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
9026 // CHECK9-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
9027 // CHECK9-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
9028 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9029 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9030 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
9031 // CHECK9-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
9032 // CHECK9-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9033 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
9034 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9035 // CHECK9:       cond.true:
9036 // CHECK9-NEXT:    br label [[COND_END:%.*]]
9037 // CHECK9:       cond.false:
9038 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9039 // CHECK9-NEXT:    br label [[COND_END]]
9040 // CHECK9:       cond.end:
9041 // CHECK9-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
9042 // CHECK9-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
9043 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
9044 // CHECK9-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
9045 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9046 // CHECK9:       omp.inner.for.cond:
9047 // CHECK9-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
9048 // CHECK9-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9049 // CHECK9-NEXT:    [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
9050 // CHECK9-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9051 // CHECK9:       omp.inner.for.body:
9052 // CHECK9-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
9053 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
9054 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
9055 // CHECK9-NEXT:    store i64 [[ADD]], i64* [[I]], align 8
9056 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
9057 // CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
9058 // CHECK9-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
9059 // CHECK9-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
9060 // CHECK9-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
9061 // CHECK9-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
9062 // CHECK9-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
9063 // CHECK9-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
9064 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
9065 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
9066 // CHECK9-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
9067 // CHECK9-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
9068 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9069 // CHECK9:       omp.body.continue:
9070 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9071 // CHECK9:       omp.inner.for.inc:
9072 // CHECK9-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
9073 // CHECK9-NEXT:    [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
9074 // CHECK9-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
9075 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]
9076 // CHECK9:       omp.inner.for.end:
9077 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9078 // CHECK9:       omp.loop.exit:
9079 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
9080 // CHECK9-NEXT:    ret void
9081 //
9082 //
9083 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
9084 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] {
9085 // CHECK10-NEXT:  entry:
9086 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
9087 // CHECK10-NEXT:    ret void
9088 //
9089 //
9090 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
9091 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
9092 // CHECK10-NEXT:  entry:
9093 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9094 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9095 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9096 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9097 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9098 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9099 // CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9100 // CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9101 // CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 4
9102 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9103 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9104 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9105 // CHECK10-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
9106 // CHECK10-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9107 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9108 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9109 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
9110 // CHECK10-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
9111 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9112 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
9113 // CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9114 // CHECK10:       cond.true:
9115 // CHECK10-NEXT:    br label [[COND_END:%.*]]
9116 // CHECK10:       cond.false:
9117 // CHECK10-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9118 // CHECK10-NEXT:    br label [[COND_END]]
9119 // CHECK10:       cond.end:
9120 // CHECK10-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
9121 // CHECK10-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9122 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9123 // CHECK10-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
9124 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9125 // CHECK10:       omp.inner.for.cond:
9126 // CHECK10-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9127 // CHECK10-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9128 // CHECK10-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
9129 // CHECK10-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9130 // CHECK10:       omp.inner.for.body:
9131 // CHECK10-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9132 // CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
9133 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
9134 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
9135 // CHECK10-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
9136 // CHECK10-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
9137 // CHECK10-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
9138 // CHECK10:       .cancel.exit:
9139 // CHECK10-NEXT:    br label [[CANCEL_EXIT:%.*]]
9140 // CHECK10:       .cancel.continue:
9141 // CHECK10-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
9142 // CHECK10-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
9143 // CHECK10-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
9144 // CHECK10:       .cancel.exit2:
9145 // CHECK10-NEXT:    br label [[CANCEL_EXIT]]
9146 // CHECK10:       .cancel.continue3:
9147 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9148 // CHECK10:       omp.body.continue:
9149 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9150 // CHECK10:       omp.inner.for.inc:
9151 // CHECK10-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9152 // CHECK10-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
9153 // CHECK10-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
9154 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]]
9155 // CHECK10:       omp.inner.for.end:
9156 // CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9157 // CHECK10:       omp.loop.exit:
9158 // CHECK10-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
9159 // CHECK10-NEXT:    br label [[CANCEL_CONT:%.*]]
9160 // CHECK10:       cancel.cont:
9161 // CHECK10-NEXT:    ret void
9162 // CHECK10:       cancel.exit:
9163 // CHECK10-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
9164 // CHECK10-NEXT:    br label [[CANCEL_CONT]]
9165 //
9166 //
9167 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
9168 // CHECK10-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
9169 // CHECK10-NEXT:  entry:
9170 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9171 // CHECK10-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
9172 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9173 // CHECK10-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9174 // CHECK10-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
9175 // CHECK10-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9176 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9177 // CHECK10-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
9178 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9179 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9180 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
9181 // CHECK10-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9182 // CHECK10-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
9183 // CHECK10-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9184 // CHECK10-NEXT:    store i16 [[TMP0]], i16* [[CONV3]], align 2
9185 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9186 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
9187 // CHECK10-NEXT:    [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
9188 // CHECK10-NEXT:    store i32 [[TMP2]], i32* [[CONV4]], align 4
9189 // CHECK10-NEXT:    [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
9190 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
9191 // CHECK10-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9192 // CHECK10-NEXT:    store i32 [[TMP4]], i32* [[CONV5]], align 4
9193 // CHECK10-NEXT:    [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
9194 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
9195 // CHECK10-NEXT:    ret void
9196 //
9197 //
9198 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
9199 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
9200 // CHECK10-NEXT:  entry:
9201 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9202 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9203 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9204 // CHECK10-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
9205 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9206 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
9207 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i64, align 8
9208 // CHECK10-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
9209 // CHECK10-NEXT:    [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
9210 // CHECK10-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
9211 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
9212 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
9213 // CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
9214 // CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9215 // CHECK10-NEXT:    [[IT:%.*]] = alloca i64, align 8
9216 // CHECK10-NEXT:    [[LIN4:%.*]] = alloca i32, align 4
9217 // CHECK10-NEXT:    [[A5:%.*]] = alloca i32, align 4
9218 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9219 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9220 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9221 // CHECK10-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
9222 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9223 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9224 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
9225 // CHECK10-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9226 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
9227 // CHECK10-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
9228 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
9229 // CHECK10-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
9230 // CHECK10-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]]
9231 // CHECK10-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
9232 // CHECK10-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
9233 // CHECK10-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
9234 // CHECK10-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
9235 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9236 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9237 // CHECK10-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
9238 // CHECK10-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
9239 // CHECK10-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
9240 // CHECK10-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9241 // CHECK10-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
9242 // CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9243 // CHECK10:       cond.true:
9244 // CHECK10-NEXT:    br label [[COND_END:%.*]]
9245 // CHECK10:       cond.false:
9246 // CHECK10-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9247 // CHECK10-NEXT:    br label [[COND_END]]
9248 // CHECK10:       cond.end:
9249 // CHECK10-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
9250 // CHECK10-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
9251 // CHECK10-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
9252 // CHECK10-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
9253 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9254 // CHECK10:       omp.inner.for.cond:
9255 // CHECK10-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
9256 // CHECK10-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9257 // CHECK10-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
9258 // CHECK10-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9259 // CHECK10:       omp.inner.for.body:
9260 // CHECK10-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
9261 // CHECK10-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
9262 // CHECK10-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
9263 // CHECK10-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
9264 // CHECK10-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
9265 // CHECK10-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
9266 // CHECK10-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
9267 // CHECK10-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
9268 // CHECK10-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
9269 // CHECK10-NEXT:    [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
9270 // CHECK10-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
9271 // CHECK10-NEXT:    store i32 [[CONV9]], i32* [[LIN4]], align 4
9272 // CHECK10-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
9273 // CHECK10-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
9274 // CHECK10-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
9275 // CHECK10-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
9276 // CHECK10-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
9277 // CHECK10-NEXT:    [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
9278 // CHECK10-NEXT:    [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
9279 // CHECK10-NEXT:    store i32 [[CONV13]], i32* [[A5]], align 4
9280 // CHECK10-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8
9281 // CHECK10-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
9282 // CHECK10-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
9283 // CHECK10-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
9284 // CHECK10-NEXT:    store i16 [[CONV16]], i16* [[CONV]], align 8
9285 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9286 // CHECK10:       omp.body.continue:
9287 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9288 // CHECK10:       omp.inner.for.inc:
9289 // CHECK10-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
9290 // CHECK10-NEXT:    [[ADD17:%.*]] = add i64 [[TMP17]], 1
9291 // CHECK10-NEXT:    store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
9292 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]]
9293 // CHECK10:       omp.inner.for.end:
9294 // CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9295 // CHECK10:       omp.loop.exit:
9296 // CHECK10-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
9297 // CHECK10-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
9298 // CHECK10-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
9299 // CHECK10-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
9300 // CHECK10:       .omp.linear.pu:
9301 // CHECK10-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
9302 // CHECK10-NEXT:    [[CONV18:%.*]] = sext i32 [[TMP20]] to i64
9303 // CHECK10-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
9304 // CHECK10-NEXT:    [[MUL19:%.*]] = mul i64 4, [[TMP21]]
9305 // CHECK10-NEXT:    [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
9306 // CHECK10-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
9307 // CHECK10-NEXT:    store i32 [[CONV21]], i32* [[CONV1]], align 8
9308 // CHECK10-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
9309 // CHECK10-NEXT:    [[CONV22:%.*]] = sext i32 [[TMP22]] to i64
9310 // CHECK10-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
9311 // CHECK10-NEXT:    [[MUL23:%.*]] = mul i64 4, [[TMP23]]
9312 // CHECK10-NEXT:    [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
9313 // CHECK10-NEXT:    [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
9314 // CHECK10-NEXT:    store i32 [[CONV25]], i32* [[CONV2]], align 8
9315 // CHECK10-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
9316 // CHECK10:       .omp.linear.pu.done:
9317 // CHECK10-NEXT:    ret void
9318 //
9319 //
9320 // CHECK10-LABEL: define {{[^@]+}}@_Z7get_valv
9321 // CHECK10-SAME: () #[[ATTR2:[0-9]+]] {
9322 // CHECK10-NEXT:  entry:
9323 // CHECK10-NEXT:    ret i64 0
9324 //
9325 //
9326 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
9327 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
9328 // CHECK10-NEXT:  entry:
9329 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9330 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9331 // CHECK10-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9332 // CHECK10-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9333 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9334 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9335 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9336 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9337 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
9338 // CHECK10-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9339 // CHECK10-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
9340 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
9341 // CHECK10-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
9342 // CHECK10-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9343 // CHECK10-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
9344 // CHECK10-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9345 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
9346 // CHECK10-NEXT:    ret void
9347 //
9348 //
9349 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2
9350 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
9351 // CHECK10-NEXT:  entry:
9352 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9353 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9354 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9355 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9356 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9357 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i16, align 2
9358 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9359 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9360 // CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9361 // CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9362 // CHECK10-NEXT:    [[IT:%.*]] = alloca i16, align 2
9363 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9364 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9365 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9366 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9367 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9368 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9369 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9370 // CHECK10-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
9371 // CHECK10-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9372 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9373 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9374 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
9375 // CHECK10-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
9376 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9377 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
9378 // CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9379 // CHECK10:       cond.true:
9380 // CHECK10-NEXT:    br label [[COND_END:%.*]]
9381 // CHECK10:       cond.false:
9382 // CHECK10-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9383 // CHECK10-NEXT:    br label [[COND_END]]
9384 // CHECK10:       cond.end:
9385 // CHECK10-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
9386 // CHECK10-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9387 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9388 // CHECK10-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
9389 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9390 // CHECK10:       omp.inner.for.cond:
9391 // CHECK10-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9392 // CHECK10-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9393 // CHECK10-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
9394 // CHECK10-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9395 // CHECK10:       omp.inner.for.body:
9396 // CHECK10-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9397 // CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
9398 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
9399 // CHECK10-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
9400 // CHECK10-NEXT:    store i16 [[CONV3]], i16* [[IT]], align 2
9401 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
9402 // CHECK10-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
9403 // CHECK10-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8
9404 // CHECK10-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
9405 // CHECK10-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
9406 // CHECK10-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
9407 // CHECK10-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
9408 // CHECK10-NEXT:    store i16 [[CONV7]], i16* [[CONV1]], align 8
9409 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9410 // CHECK10:       omp.body.continue:
9411 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9412 // CHECK10:       omp.inner.for.inc:
9413 // CHECK10-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9414 // CHECK10-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
9415 // CHECK10-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
9416 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]]
9417 // CHECK10:       omp.inner.for.end:
9418 // CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9419 // CHECK10:       omp.loop.exit:
9420 // CHECK10-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
9421 // CHECK10-NEXT:    ret void
9422 //
9423 //
9424 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
9425 // CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
9426 // CHECK10-NEXT:  entry:
9427 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9428 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
9429 // CHECK10-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9430 // CHECK10-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
9431 // CHECK10-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
9432 // CHECK10-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9433 // CHECK10-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
9434 // CHECK10-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
9435 // CHECK10-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
9436 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
9437 // CHECK10-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9438 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
9439 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9440 // CHECK10-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
9441 // CHECK10-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9442 // CHECK10-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
9443 // CHECK10-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
9444 // CHECK10-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9445 // CHECK10-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
9446 // CHECK10-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
9447 // CHECK10-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
9448 // CHECK10-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
9449 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9450 // CHECK10-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
9451 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9452 // CHECK10-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
9453 // CHECK10-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
9454 // CHECK10-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9455 // CHECK10-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
9456 // CHECK10-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
9457 // CHECK10-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
9458 // CHECK10-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
9459 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
9460 // CHECK10-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9461 // CHECK10-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
9462 // CHECK10-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
9463 // CHECK10-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
9464 // CHECK10-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
9465 // CHECK10-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
9466 // CHECK10-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
9467 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
9468 // CHECK10-NEXT:    ret void
9469 //
9470 //
9471 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3
9472 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
9473 // CHECK10-NEXT:  entry:
9474 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9475 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9476 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9477 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
9478 // CHECK10-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9479 // CHECK10-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
9480 // CHECK10-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
9481 // CHECK10-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9482 // CHECK10-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
9483 // CHECK10-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
9484 // CHECK10-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
9485 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
9486 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9487 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i8, align 1
9488 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9489 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9490 // CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9491 // CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9492 // CHECK10-NEXT:    [[IT:%.*]] = alloca i8, align 1
9493 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9494 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9495 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9496 // CHECK10-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
9497 // CHECK10-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9498 // CHECK10-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
9499 // CHECK10-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
9500 // CHECK10-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9501 // CHECK10-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
9502 // CHECK10-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
9503 // CHECK10-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
9504 // CHECK10-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
9505 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9506 // CHECK10-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
9507 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9508 // CHECK10-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
9509 // CHECK10-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
9510 // CHECK10-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9511 // CHECK10-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
9512 // CHECK10-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
9513 // CHECK10-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
9514 // CHECK10-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
9515 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9516 // CHECK10-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
9517 // CHECK10-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9518 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9519 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
9520 // CHECK10-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9521 // CHECK10-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
9522 // CHECK10-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
9523 // CHECK10-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
9524 // CHECK10:       omp.dispatch.cond:
9525 // CHECK10-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9526 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
9527 // CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9528 // CHECK10:       cond.true:
9529 // CHECK10-NEXT:    br label [[COND_END:%.*]]
9530 // CHECK10:       cond.false:
9531 // CHECK10-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9532 // CHECK10-NEXT:    br label [[COND_END]]
9533 // CHECK10:       cond.end:
9534 // CHECK10-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
9535 // CHECK10-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9536 // CHECK10-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9537 // CHECK10-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
9538 // CHECK10-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9539 // CHECK10-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9540 // CHECK10-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
9541 // CHECK10-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
9542 // CHECK10:       omp.dispatch.body:
9543 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9544 // CHECK10:       omp.inner.for.cond:
9545 // CHECK10-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9546 // CHECK10-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9547 // CHECK10-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
9548 // CHECK10-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9549 // CHECK10:       omp.inner.for.body:
9550 // CHECK10-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9551 // CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
9552 // CHECK10-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
9553 // CHECK10-NEXT:    [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
9554 // CHECK10-NEXT:    store i8 [[CONV8]], i8* [[IT]], align 1
9555 // CHECK10-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
9556 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
9557 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
9558 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
9559 // CHECK10-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
9560 // CHECK10-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
9561 // CHECK10-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
9562 // CHECK10-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
9563 // CHECK10-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
9564 // CHECK10-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
9565 // CHECK10-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
9566 // CHECK10-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
9567 // CHECK10-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
9568 // CHECK10-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
9569 // CHECK10-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
9570 // CHECK10-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
9571 // CHECK10-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
9572 // CHECK10-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
9573 // CHECK10-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
9574 // CHECK10-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
9575 // CHECK10-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
9576 // CHECK10-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
9577 // CHECK10-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
9578 // CHECK10-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
9579 // CHECK10-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
9580 // CHECK10-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
9581 // CHECK10-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
9582 // CHECK10-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8
9583 // CHECK10-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
9584 // CHECK10-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8
9585 // CHECK10-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
9586 // CHECK10-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
9587 // CHECK10-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
9588 // CHECK10-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
9589 // CHECK10-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
9590 // CHECK10-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8
9591 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9592 // CHECK10:       omp.body.continue:
9593 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9594 // CHECK10:       omp.inner.for.inc:
9595 // CHECK10-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9596 // CHECK10-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
9597 // CHECK10-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
9598 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]]
9599 // CHECK10:       omp.inner.for.end:
9600 // CHECK10-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
9601 // CHECK10:       omp.dispatch.inc:
9602 // CHECK10-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9603 // CHECK10-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
9604 // CHECK10-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
9605 // CHECK10-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
9606 // CHECK10-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9607 // CHECK10-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
9608 // CHECK10-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
9609 // CHECK10-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
9610 // CHECK10-NEXT:    br label [[OMP_DISPATCH_COND]]
9611 // CHECK10:       omp.dispatch.end:
9612 // CHECK10-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
9613 // CHECK10-NEXT:    ret void
9614 //
9615 //
9616 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
9617 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
9618 // CHECK10-NEXT:  entry:
9619 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9620 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9621 // CHECK10-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
9622 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9623 // CHECK10-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9624 // CHECK10-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9625 // CHECK10-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
9626 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9627 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9628 // CHECK10-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
9629 // CHECK10-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9630 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9631 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9632 // CHECK10-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
9633 // CHECK10-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9634 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
9635 // CHECK10-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9636 // CHECK10-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
9637 // CHECK10-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
9638 // CHECK10-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
9639 // CHECK10-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9640 // CHECK10-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
9641 // CHECK10-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9642 // CHECK10-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
9643 // CHECK10-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
9644 // CHECK10-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
9645 // CHECK10-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
9646 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
9647 // CHECK10-NEXT:    ret void
9648 //
9649 //
9650 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4
9651 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
9652 // CHECK10-NEXT:  entry:
9653 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9654 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9655 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9656 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9657 // CHECK10-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
9658 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9659 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9660 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9661 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9662 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9663 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9664 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9665 // CHECK10-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
9666 // CHECK10-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9667 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9668 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9669 // CHECK10-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
9670 // CHECK10-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9671 // CHECK10-NEXT:    ret void
9672 //
9673 //
9674 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
9675 // CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
9676 // CHECK10-NEXT:  entry:
9677 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
9678 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
9679 // CHECK10-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9680 // CHECK10-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9681 // CHECK10-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
9682 // CHECK10-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
9683 // CHECK10-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
9684 // CHECK10-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
9685 // CHECK10-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9686 // CHECK10-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9687 // CHECK10-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
9688 // CHECK10-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
9689 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
9690 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9691 // CHECK10-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9692 // CHECK10-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
9693 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
9694 // CHECK10-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
9695 // CHECK10-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
9696 // CHECK10-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
9697 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
9698 // CHECK10-NEXT:    ret void
9699 //
9700 //
9701 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
9702 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
9703 // CHECK10-NEXT:  entry:
9704 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9705 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9706 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
9707 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
9708 // CHECK10-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9709 // CHECK10-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9710 // CHECK10-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
9711 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
9712 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i64, align 8
9713 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
9714 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
9715 // CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
9716 // CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9717 // CHECK10-NEXT:    [[IT:%.*]] = alloca i64, align 8
9718 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9719 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9720 // CHECK10-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
9721 // CHECK10-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
9722 // CHECK10-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9723 // CHECK10-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9724 // CHECK10-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
9725 // CHECK10-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
9726 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
9727 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9728 // CHECK10-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9729 // CHECK10-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
9730 // CHECK10-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
9731 // CHECK10-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
9732 // CHECK10-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
9733 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9734 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9735 // CHECK10-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
9736 // CHECK10-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
9737 // CHECK10-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9738 // CHECK10-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
9739 // CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9740 // CHECK10:       cond.true:
9741 // CHECK10-NEXT:    br label [[COND_END:%.*]]
9742 // CHECK10:       cond.false:
9743 // CHECK10-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9744 // CHECK10-NEXT:    br label [[COND_END]]
9745 // CHECK10:       cond.end:
9746 // CHECK10-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
9747 // CHECK10-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
9748 // CHECK10-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
9749 // CHECK10-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
9750 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9751 // CHECK10:       omp.inner.for.cond:
9752 // CHECK10-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
9753 // CHECK10-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9754 // CHECK10-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
9755 // CHECK10-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9756 // CHECK10:       omp.inner.for.body:
9757 // CHECK10-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
9758 // CHECK10-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
9759 // CHECK10-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
9760 // CHECK10-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
9761 // CHECK10-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
9762 // CHECK10-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
9763 // CHECK10-NEXT:    [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
9764 // CHECK10-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
9765 // CHECK10-NEXT:    store double [[ADD]], double* [[A]], align 8
9766 // CHECK10-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
9767 // CHECK10-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 8
9768 // CHECK10-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
9769 // CHECK10-NEXT:    store double [[INC]], double* [[A5]], align 8
9770 // CHECK10-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
9771 // CHECK10-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
9772 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
9773 // CHECK10-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
9774 // CHECK10-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
9775 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9776 // CHECK10:       omp.body.continue:
9777 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9778 // CHECK10:       omp.inner.for.inc:
9779 // CHECK10-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
9780 // CHECK10-NEXT:    [[ADD8:%.*]] = add i64 [[TMP15]], 1
9781 // CHECK10-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
9782 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]]
9783 // CHECK10:       omp.inner.for.end:
9784 // CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9785 // CHECK10:       omp.loop.exit:
9786 // CHECK10-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
9787 // CHECK10-NEXT:    ret void
9788 //
9789 //
9790 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
9791 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
9792 // CHECK10-NEXT:  entry:
9793 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9794 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9795 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9796 // CHECK10-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9797 // CHECK10-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9798 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9799 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9800 // CHECK10-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9801 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9802 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9803 // CHECK10-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9804 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
9805 // CHECK10-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9806 // CHECK10-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
9807 // CHECK10-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
9808 // CHECK10-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
9809 // CHECK10-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9810 // CHECK10-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
9811 // CHECK10-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9812 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
9813 // CHECK10-NEXT:    ret void
9814 //
9815 //
9816 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6
9817 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
9818 // CHECK10-NEXT:  entry:
9819 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9820 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9821 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9822 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9823 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9824 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
9825 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i64, align 8
9826 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
9827 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
9828 // CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
9829 // CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9830 // CHECK10-NEXT:    [[I:%.*]] = alloca i64, align 8
9831 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9832 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9833 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9834 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9835 // CHECK10-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9836 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9837 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9838 // CHECK10-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9839 // CHECK10-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
9840 // CHECK10-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
9841 // CHECK10-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
9842 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9843 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9844 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
9845 // CHECK10-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
9846 // CHECK10-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9847 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
9848 // CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9849 // CHECK10:       cond.true:
9850 // CHECK10-NEXT:    br label [[COND_END:%.*]]
9851 // CHECK10:       cond.false:
9852 // CHECK10-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9853 // CHECK10-NEXT:    br label [[COND_END]]
9854 // CHECK10:       cond.end:
9855 // CHECK10-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
9856 // CHECK10-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
9857 // CHECK10-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
9858 // CHECK10-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
9859 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9860 // CHECK10:       omp.inner.for.cond:
9861 // CHECK10-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
9862 // CHECK10-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9863 // CHECK10-NEXT:    [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
9864 // CHECK10-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9865 // CHECK10:       omp.inner.for.body:
9866 // CHECK10-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
9867 // CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
9868 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
9869 // CHECK10-NEXT:    store i64 [[ADD]], i64* [[I]], align 8
9870 // CHECK10-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
9871 // CHECK10-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
9872 // CHECK10-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
9873 // CHECK10-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
9874 // CHECK10-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
9875 // CHECK10-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
9876 // CHECK10-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
9877 // CHECK10-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
9878 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
9879 // CHECK10-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
9880 // CHECK10-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
9881 // CHECK10-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
9882 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9883 // CHECK10:       omp.body.continue:
9884 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9885 // CHECK10:       omp.inner.for.inc:
9886 // CHECK10-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
9887 // CHECK10-NEXT:    [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
9888 // CHECK10-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
9889 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]]
9890 // CHECK10:       omp.inner.for.end:
9891 // CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9892 // CHECK10:       omp.loop.exit:
9893 // CHECK10-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
9894 // CHECK10-NEXT:    ret void
9895 //
9896 //
9897 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
9898 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
9899 // CHECK11-NEXT:  entry:
9900 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
9901 // CHECK11-NEXT:    ret void
9902 //
9903 //
9904 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
9905 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
9906 // CHECK11-NEXT:  entry:
9907 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
9908 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
9909 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9910 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9911 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9912 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9913 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9914 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9915 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
9916 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
9917 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
9918 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9919 // CHECK11-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
9920 // CHECK11-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9921 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9922 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
9923 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
9924 // CHECK11-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
9925 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9926 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
9927 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9928 // CHECK11:       cond.true:
9929 // CHECK11-NEXT:    br label [[COND_END:%.*]]
9930 // CHECK11:       cond.false:
9931 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9932 // CHECK11-NEXT:    br label [[COND_END]]
9933 // CHECK11:       cond.end:
9934 // CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
9935 // CHECK11-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9936 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9937 // CHECK11-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
9938 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9939 // CHECK11:       omp.inner.for.cond:
9940 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9941 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9942 // CHECK11-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
9943 // CHECK11-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9944 // CHECK11:       omp.inner.for.body:
9945 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9946 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
9947 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
9948 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
9949 // CHECK11-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
9950 // CHECK11-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
9951 // CHECK11-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
9952 // CHECK11:       .cancel.exit:
9953 // CHECK11-NEXT:    br label [[CANCEL_EXIT:%.*]]
9954 // CHECK11:       .cancel.continue:
9955 // CHECK11-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
9956 // CHECK11-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
9957 // CHECK11-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
9958 // CHECK11:       .cancel.exit2:
9959 // CHECK11-NEXT:    br label [[CANCEL_EXIT]]
9960 // CHECK11:       .cancel.continue3:
9961 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9962 // CHECK11:       omp.body.continue:
9963 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9964 // CHECK11:       omp.inner.for.inc:
9965 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9966 // CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
9967 // CHECK11-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
9968 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
9969 // CHECK11:       omp.inner.for.end:
9970 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9971 // CHECK11:       omp.loop.exit:
9972 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
9973 // CHECK11-NEXT:    br label [[CANCEL_CONT:%.*]]
9974 // CHECK11:       cancel.cont:
9975 // CHECK11-NEXT:    ret void
9976 // CHECK11:       cancel.exit:
9977 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
9978 // CHECK11-NEXT:    br label [[CANCEL_CONT]]
9979 //
9980 //
9981 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
9982 // CHECK11-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
9983 // CHECK11-NEXT:  entry:
9984 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
9985 // CHECK11-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
9986 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
9987 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
9988 // CHECK11-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
9989 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
9990 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
9991 // CHECK11-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
9992 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
9993 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
9994 // CHECK11-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
9995 // CHECK11-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
9996 // CHECK11-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
9997 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
9998 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
9999 // CHECK11-NEXT:    store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
10000 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
10001 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
10002 // CHECK11-NEXT:    store i32 [[TMP4]], i32* [[A_CASTED]], align 4
10003 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
10004 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
10005 // CHECK11-NEXT:    ret void
10006 //
10007 //
10008 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1
10009 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
10010 // CHECK11-NEXT:  entry:
10011 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10012 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10013 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10014 // CHECK11-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
10015 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10016 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
10017 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i64, align 4
10018 // CHECK11-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
10019 // CHECK11-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
10020 // CHECK11-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
10021 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
10022 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
10023 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
10024 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10025 // CHECK11-NEXT:    [[IT:%.*]] = alloca i64, align 8
10026 // CHECK11-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
10027 // CHECK11-NEXT:    [[A3:%.*]] = alloca i32, align 4
10028 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10029 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10030 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10031 // CHECK11-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
10032 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10033 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10034 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
10035 // CHECK11-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
10036 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
10037 // CHECK11-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
10038 // CHECK11-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]]
10039 // CHECK11-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
10040 // CHECK11-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
10041 // CHECK11-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
10042 // CHECK11-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
10043 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10044 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10045 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
10046 // CHECK11-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
10047 // CHECK11-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
10048 // CHECK11-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
10049 // CHECK11-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
10050 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10051 // CHECK11:       cond.true:
10052 // CHECK11-NEXT:    br label [[COND_END:%.*]]
10053 // CHECK11:       cond.false:
10054 // CHECK11-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
10055 // CHECK11-NEXT:    br label [[COND_END]]
10056 // CHECK11:       cond.end:
10057 // CHECK11-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
10058 // CHECK11-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
10059 // CHECK11-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
10060 // CHECK11-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
10061 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10062 // CHECK11:       omp.inner.for.cond:
10063 // CHECK11-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
10064 // CHECK11-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
10065 // CHECK11-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
10066 // CHECK11-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10067 // CHECK11:       omp.inner.for.body:
10068 // CHECK11-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
10069 // CHECK11-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
10070 // CHECK11-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
10071 // CHECK11-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
10072 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
10073 // CHECK11-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
10074 // CHECK11-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
10075 // CHECK11-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
10076 // CHECK11-NEXT:    [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
10077 // CHECK11-NEXT:    [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
10078 // CHECK11-NEXT:    [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
10079 // CHECK11-NEXT:    store i32 [[CONV7]], i32* [[LIN2]], align 4
10080 // CHECK11-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
10081 // CHECK11-NEXT:    [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
10082 // CHECK11-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
10083 // CHECK11-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
10084 // CHECK11-NEXT:    [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
10085 // CHECK11-NEXT:    [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
10086 // CHECK11-NEXT:    [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
10087 // CHECK11-NEXT:    store i32 [[CONV11]], i32* [[A3]], align 4
10088 // CHECK11-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4
10089 // CHECK11-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
10090 // CHECK11-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
10091 // CHECK11-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
10092 // CHECK11-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4
10093 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10094 // CHECK11:       omp.body.continue:
10095 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10096 // CHECK11:       omp.inner.for.inc:
10097 // CHECK11-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
10098 // CHECK11-NEXT:    [[ADD15:%.*]] = add i64 [[TMP17]], 1
10099 // CHECK11-NEXT:    store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
10100 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
10101 // CHECK11:       omp.inner.for.end:
10102 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10103 // CHECK11:       omp.loop.exit:
10104 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
10105 // CHECK11-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10106 // CHECK11-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
10107 // CHECK11-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
10108 // CHECK11:       .omp.linear.pu:
10109 // CHECK11-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
10110 // CHECK11-NEXT:    [[CONV16:%.*]] = sext i32 [[TMP20]] to i64
10111 // CHECK11-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
10112 // CHECK11-NEXT:    [[MUL17:%.*]] = mul i64 4, [[TMP21]]
10113 // CHECK11-NEXT:    [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
10114 // CHECK11-NEXT:    [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
10115 // CHECK11-NEXT:    store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
10116 // CHECK11-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
10117 // CHECK11-NEXT:    [[CONV20:%.*]] = sext i32 [[TMP22]] to i64
10118 // CHECK11-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
10119 // CHECK11-NEXT:    [[MUL21:%.*]] = mul i64 4, [[TMP23]]
10120 // CHECK11-NEXT:    [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
10121 // CHECK11-NEXT:    [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
10122 // CHECK11-NEXT:    store i32 [[CONV23]], i32* [[A_ADDR]], align 4
10123 // CHECK11-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
10124 // CHECK11:       .omp.linear.pu.done:
10125 // CHECK11-NEXT:    ret void
10126 //
10127 //
10128 // CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv
10129 // CHECK11-SAME: () #[[ATTR2:[0-9]+]] {
10130 // CHECK11-NEXT:  entry:
10131 // CHECK11-NEXT:    ret i64 0
10132 //
10133 //
10134 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
10135 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
10136 // CHECK11-NEXT:  entry:
10137 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10138 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10139 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10140 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10141 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10142 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10143 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10144 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
10145 // CHECK11-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
10146 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
10147 // CHECK11-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
10148 // CHECK11-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10149 // CHECK11-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
10150 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10151 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
10152 // CHECK11-NEXT:    ret void
10153 //
10154 //
10155 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2
10156 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
10157 // CHECK11-NEXT:  entry:
10158 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10159 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10160 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10161 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10162 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10163 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i16, align 2
10164 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10165 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10166 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10167 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10168 // CHECK11-NEXT:    [[IT:%.*]] = alloca i16, align 2
10169 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10170 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10171 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10172 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10173 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10174 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10175 // CHECK11-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
10176 // CHECK11-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10177 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10178 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10179 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
10180 // CHECK11-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10181 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10182 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
10183 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10184 // CHECK11:       cond.true:
10185 // CHECK11-NEXT:    br label [[COND_END:%.*]]
10186 // CHECK11:       cond.false:
10187 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10188 // CHECK11-NEXT:    br label [[COND_END]]
10189 // CHECK11:       cond.end:
10190 // CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
10191 // CHECK11-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10192 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10193 // CHECK11-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
10194 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10195 // CHECK11:       omp.inner.for.cond:
10196 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10197 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10198 // CHECK11-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
10199 // CHECK11-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10200 // CHECK11:       omp.inner.for.body:
10201 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10202 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
10203 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
10204 // CHECK11-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
10205 // CHECK11-NEXT:    store i16 [[CONV2]], i16* [[IT]], align 2
10206 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
10207 // CHECK11-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
10208 // CHECK11-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4
10209 // CHECK11-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
10210 // CHECK11-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
10211 // CHECK11-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
10212 // CHECK11-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
10213 // CHECK11-NEXT:    store i16 [[CONV6]], i16* [[CONV]], align 4
10214 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10215 // CHECK11:       omp.body.continue:
10216 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10217 // CHECK11:       omp.inner.for.inc:
10218 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10219 // CHECK11-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
10220 // CHECK11-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
10221 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
10222 // CHECK11:       omp.inner.for.end:
10223 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10224 // CHECK11:       omp.loop.exit:
10225 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
10226 // CHECK11-NEXT:    ret void
10227 //
10228 //
10229 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
10230 // CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
10231 // CHECK11-NEXT:  entry:
10232 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10233 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
10234 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
10235 // CHECK11-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
10236 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
10237 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
10238 // CHECK11-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
10239 // CHECK11-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
10240 // CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
10241 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
10242 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10243 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
10244 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10245 // CHECK11-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
10246 // CHECK11-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
10247 // CHECK11-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
10248 // CHECK11-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
10249 // CHECK11-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
10250 // CHECK11-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
10251 // CHECK11-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
10252 // CHECK11-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
10253 // CHECK11-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
10254 // CHECK11-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
10255 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
10256 // CHECK11-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
10257 // CHECK11-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
10258 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
10259 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
10260 // CHECK11-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
10261 // CHECK11-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
10262 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
10263 // CHECK11-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
10264 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
10265 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
10266 // CHECK11-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
10267 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
10268 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
10269 // CHECK11-NEXT:    ret void
10270 //
10271 //
10272 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3
10273 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
10274 // CHECK11-NEXT:  entry:
10275 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10276 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10277 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10278 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
10279 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
10280 // CHECK11-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
10281 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
10282 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
10283 // CHECK11-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
10284 // CHECK11-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
10285 // CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
10286 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
10287 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10288 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i8, align 1
10289 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10290 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10291 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10292 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10293 // CHECK11-NEXT:    [[IT:%.*]] = alloca i8, align 1
10294 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10295 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10296 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10297 // CHECK11-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
10298 // CHECK11-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
10299 // CHECK11-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
10300 // CHECK11-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
10301 // CHECK11-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
10302 // CHECK11-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
10303 // CHECK11-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
10304 // CHECK11-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
10305 // CHECK11-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
10306 // CHECK11-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
10307 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
10308 // CHECK11-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
10309 // CHECK11-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
10310 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
10311 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
10312 // CHECK11-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
10313 // CHECK11-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
10314 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10315 // CHECK11-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
10316 // CHECK11-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10317 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10318 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
10319 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10320 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
10321 // CHECK11-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
10322 // CHECK11-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
10323 // CHECK11:       omp.dispatch.cond:
10324 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10325 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
10326 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10327 // CHECK11:       cond.true:
10328 // CHECK11-NEXT:    br label [[COND_END:%.*]]
10329 // CHECK11:       cond.false:
10330 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10331 // CHECK11-NEXT:    br label [[COND_END]]
10332 // CHECK11:       cond.end:
10333 // CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
10334 // CHECK11-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10335 // CHECK11-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10336 // CHECK11-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
10337 // CHECK11-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10338 // CHECK11-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10339 // CHECK11-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
10340 // CHECK11-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
10341 // CHECK11:       omp.dispatch.body:
10342 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10343 // CHECK11:       omp.inner.for.cond:
10344 // CHECK11-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10345 // CHECK11-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10346 // CHECK11-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
10347 // CHECK11-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10348 // CHECK11:       omp.inner.for.body:
10349 // CHECK11-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10350 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
10351 // CHECK11-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
10352 // CHECK11-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
10353 // CHECK11-NEXT:    store i8 [[CONV]], i8* [[IT]], align 1
10354 // CHECK11-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
10355 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
10356 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
10357 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
10358 // CHECK11-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
10359 // CHECK11-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
10360 // CHECK11-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
10361 // CHECK11-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
10362 // CHECK11-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4
10363 // CHECK11-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
10364 // CHECK11-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
10365 // CHECK11-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
10366 // CHECK11-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
10367 // CHECK11-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
10368 // CHECK11-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4
10369 // CHECK11-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
10370 // CHECK11-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
10371 // CHECK11-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
10372 // CHECK11-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
10373 // CHECK11-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8
10374 // CHECK11-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
10375 // CHECK11-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
10376 // CHECK11-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
10377 // CHECK11-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
10378 // CHECK11-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
10379 // CHECK11-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8
10380 // CHECK11-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
10381 // CHECK11-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4
10382 // CHECK11-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
10383 // CHECK11-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4
10384 // CHECK11-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
10385 // CHECK11-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
10386 // CHECK11-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
10387 // CHECK11-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
10388 // CHECK11-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
10389 // CHECK11-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4
10390 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10391 // CHECK11:       omp.body.continue:
10392 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10393 // CHECK11:       omp.inner.for.inc:
10394 // CHECK11-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10395 // CHECK11-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
10396 // CHECK11-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
10397 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
10398 // CHECK11:       omp.inner.for.end:
10399 // CHECK11-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
10400 // CHECK11:       omp.dispatch.inc:
10401 // CHECK11-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10402 // CHECK11-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
10403 // CHECK11-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
10404 // CHECK11-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
10405 // CHECK11-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10406 // CHECK11-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
10407 // CHECK11-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
10408 // CHECK11-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
10409 // CHECK11-NEXT:    br label [[OMP_DISPATCH_COND]]
10410 // CHECK11:       omp.dispatch.end:
10411 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
10412 // CHECK11-NEXT:    ret void
10413 //
10414 //
10415 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
10416 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
10417 // CHECK11-NEXT:  entry:
10418 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10419 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10420 // CHECK11-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
10421 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
10422 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10423 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10424 // CHECK11-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
10425 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10426 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10427 // CHECK11-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
10428 // CHECK11-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
10429 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10430 // CHECK11-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
10431 // CHECK11-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
10432 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
10433 // CHECK11-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
10434 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
10435 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
10436 // CHECK11-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10437 // CHECK11-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
10438 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10439 // CHECK11-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
10440 // CHECK11-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
10441 // CHECK11-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
10442 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
10443 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
10444 // CHECK11-NEXT:    ret void
10445 //
10446 //
10447 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4
10448 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
10449 // CHECK11-NEXT:  entry:
10450 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10451 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10452 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10453 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10454 // CHECK11-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
10455 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
10456 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10457 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10458 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10459 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10460 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10461 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10462 // CHECK11-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
10463 // CHECK11-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
10464 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10465 // CHECK11-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
10466 // CHECK11-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
10467 // CHECK11-NEXT:    ret void
10468 //
10469 //
10470 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
10471 // CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
10472 // CHECK11-NEXT:  entry:
10473 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
10474 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
10475 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
10476 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
10477 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
10478 // CHECK11-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
10479 // CHECK11-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
10480 // CHECK11-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
10481 // CHECK11-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
10482 // CHECK11-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
10483 // CHECK11-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
10484 // CHECK11-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
10485 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
10486 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
10487 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
10488 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
10489 // CHECK11-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
10490 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
10491 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
10492 // CHECK11-NEXT:    ret void
10493 //
10494 //
10495 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5
10496 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
10497 // CHECK11-NEXT:  entry:
10498 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10499 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10500 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
10501 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
10502 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
10503 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
10504 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
10505 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
10506 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i64, align 4
10507 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
10508 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
10509 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
10510 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10511 // CHECK11-NEXT:    [[IT:%.*]] = alloca i64, align 8
10512 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10513 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10514 // CHECK11-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
10515 // CHECK11-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
10516 // CHECK11-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
10517 // CHECK11-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
10518 // CHECK11-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
10519 // CHECK11-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
10520 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
10521 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
10522 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
10523 // CHECK11-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
10524 // CHECK11-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
10525 // CHECK11-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
10526 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10527 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10528 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
10529 // CHECK11-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
10530 // CHECK11-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
10531 // CHECK11-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
10532 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10533 // CHECK11:       cond.true:
10534 // CHECK11-NEXT:    br label [[COND_END:%.*]]
10535 // CHECK11:       cond.false:
10536 // CHECK11-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
10537 // CHECK11-NEXT:    br label [[COND_END]]
10538 // CHECK11:       cond.end:
10539 // CHECK11-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
10540 // CHECK11-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
10541 // CHECK11-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
10542 // CHECK11-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
10543 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10544 // CHECK11:       omp.inner.for.cond:
10545 // CHECK11-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
10546 // CHECK11-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
10547 // CHECK11-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
10548 // CHECK11-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10549 // CHECK11:       omp.inner.for.body:
10550 // CHECK11-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
10551 // CHECK11-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
10552 // CHECK11-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
10553 // CHECK11-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
10554 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
10555 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
10556 // CHECK11-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
10557 // CHECK11-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
10558 // CHECK11-NEXT:    store double [[ADD]], double* [[A]], align 4
10559 // CHECK11-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
10560 // CHECK11-NEXT:    [[TMP13:%.*]] = load double, double* [[A4]], align 4
10561 // CHECK11-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
10562 // CHECK11-NEXT:    store double [[INC]], double* [[A4]], align 4
10563 // CHECK11-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
10564 // CHECK11-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
10565 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
10566 // CHECK11-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
10567 // CHECK11-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
10568 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10569 // CHECK11:       omp.body.continue:
10570 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10571 // CHECK11:       omp.inner.for.inc:
10572 // CHECK11-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
10573 // CHECK11-NEXT:    [[ADD7:%.*]] = add i64 [[TMP15]], 1
10574 // CHECK11-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
10575 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
10576 // CHECK11:       omp.inner.for.end:
10577 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10578 // CHECK11:       omp.loop.exit:
10579 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
10580 // CHECK11-NEXT:    ret void
10581 //
10582 //
10583 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
10584 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
10585 // CHECK11-NEXT:  entry:
10586 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10587 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10588 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
10589 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10590 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10591 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10592 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10593 // CHECK11-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
10594 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10595 // CHECK11-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
10596 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
10597 // CHECK11-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
10598 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
10599 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
10600 // CHECK11-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10601 // CHECK11-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
10602 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10603 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
10604 // CHECK11-NEXT:    ret void
10605 //
10606 //
10607 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6
10608 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
10609 // CHECK11-NEXT:  entry:
10610 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10611 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10612 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10613 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10614 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
10615 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
10616 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i64, align 4
10617 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
10618 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
10619 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
10620 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10621 // CHECK11-NEXT:    [[I:%.*]] = alloca i64, align 8
10622 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10623 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10624 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10625 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10626 // CHECK11-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
10627 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10628 // CHECK11-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
10629 // CHECK11-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
10630 // CHECK11-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
10631 // CHECK11-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
10632 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10633 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10634 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
10635 // CHECK11-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
10636 // CHECK11-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
10637 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
10638 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10639 // CHECK11:       cond.true:
10640 // CHECK11-NEXT:    br label [[COND_END:%.*]]
10641 // CHECK11:       cond.false:
10642 // CHECK11-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
10643 // CHECK11-NEXT:    br label [[COND_END]]
10644 // CHECK11:       cond.end:
10645 // CHECK11-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
10646 // CHECK11-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
10647 // CHECK11-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
10648 // CHECK11-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
10649 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10650 // CHECK11:       omp.inner.for.cond:
10651 // CHECK11-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
10652 // CHECK11-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
10653 // CHECK11-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
10654 // CHECK11-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10655 // CHECK11:       omp.inner.for.body:
10656 // CHECK11-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
10657 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
10658 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
10659 // CHECK11-NEXT:    store i64 [[ADD]], i64* [[I]], align 8
10660 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
10661 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
10662 // CHECK11-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
10663 // CHECK11-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
10664 // CHECK11-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
10665 // CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
10666 // CHECK11-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
10667 // CHECK11-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
10668 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
10669 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
10670 // CHECK11-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
10671 // CHECK11-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
10672 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10673 // CHECK11:       omp.body.continue:
10674 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10675 // CHECK11:       omp.inner.for.inc:
10676 // CHECK11-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
10677 // CHECK11-NEXT:    [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
10678 // CHECK11-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
10679 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
10680 // CHECK11:       omp.inner.for.end:
10681 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10682 // CHECK11:       omp.loop.exit:
10683 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
10684 // CHECK11-NEXT:    ret void
10685 //
10686 //
10687 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
10688 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] {
10689 // CHECK12-NEXT:  entry:
10690 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
10691 // CHECK12-NEXT:    ret void
10692 //
10693 //
10694 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.
10695 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
10696 // CHECK12-NEXT:  entry:
10697 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10698 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10699 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10700 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10701 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10702 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10703 // CHECK12-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10704 // CHECK12-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10705 // CHECK12-NEXT:    [[I:%.*]] = alloca i32, align 4
10706 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10707 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10708 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10709 // CHECK12-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
10710 // CHECK12-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10711 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10712 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10713 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
10714 // CHECK12-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10715 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10716 // CHECK12-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
10717 // CHECK12-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10718 // CHECK12:       cond.true:
10719 // CHECK12-NEXT:    br label [[COND_END:%.*]]
10720 // CHECK12:       cond.false:
10721 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10722 // CHECK12-NEXT:    br label [[COND_END]]
10723 // CHECK12:       cond.end:
10724 // CHECK12-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
10725 // CHECK12-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10726 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10727 // CHECK12-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
10728 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10729 // CHECK12:       omp.inner.for.cond:
10730 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10731 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10732 // CHECK12-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
10733 // CHECK12-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10734 // CHECK12:       omp.inner.for.body:
10735 // CHECK12-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10736 // CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
10737 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
10738 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
10739 // CHECK12-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
10740 // CHECK12-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
10741 // CHECK12-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
10742 // CHECK12:       .cancel.exit:
10743 // CHECK12-NEXT:    br label [[CANCEL_EXIT:%.*]]
10744 // CHECK12:       .cancel.continue:
10745 // CHECK12-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
10746 // CHECK12-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
10747 // CHECK12-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
10748 // CHECK12:       .cancel.exit2:
10749 // CHECK12-NEXT:    br label [[CANCEL_EXIT]]
10750 // CHECK12:       .cancel.continue3:
10751 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10752 // CHECK12:       omp.body.continue:
10753 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10754 // CHECK12:       omp.inner.for.inc:
10755 // CHECK12-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10756 // CHECK12-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
10757 // CHECK12-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
10758 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]]
10759 // CHECK12:       omp.inner.for.end:
10760 // CHECK12-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10761 // CHECK12:       omp.loop.exit:
10762 // CHECK12-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
10763 // CHECK12-NEXT:    br label [[CANCEL_CONT:%.*]]
10764 // CHECK12:       cancel.cont:
10765 // CHECK12-NEXT:    ret void
10766 // CHECK12:       cancel.exit:
10767 // CHECK12-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
10768 // CHECK12-NEXT:    br label [[CANCEL_CONT]]
10769 //
10770 //
10771 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
10772 // CHECK12-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
10773 // CHECK12-NEXT:  entry:
10774 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10775 // CHECK12-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
10776 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10777 // CHECK12-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10778 // CHECK12-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
10779 // CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10780 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10781 // CHECK12-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
10782 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10783 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10784 // CHECK12-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
10785 // CHECK12-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10786 // CHECK12-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
10787 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10788 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
10789 // CHECK12-NEXT:    store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
10790 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
10791 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
10792 // CHECK12-NEXT:    store i32 [[TMP4]], i32* [[A_CASTED]], align 4
10793 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
10794 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
10795 // CHECK12-NEXT:    ret void
10796 //
10797 //
10798 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1
10799 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
10800 // CHECK12-NEXT:  entry:
10801 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10802 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10803 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10804 // CHECK12-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
10805 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10806 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
10807 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i64, align 4
10808 // CHECK12-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
10809 // CHECK12-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
10810 // CHECK12-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
10811 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
10812 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
10813 // CHECK12-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
10814 // CHECK12-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10815 // CHECK12-NEXT:    [[IT:%.*]] = alloca i64, align 8
10816 // CHECK12-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
10817 // CHECK12-NEXT:    [[A3:%.*]] = alloca i32, align 4
10818 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10819 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10820 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10821 // CHECK12-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
10822 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10823 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10824 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
10825 // CHECK12-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
10826 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
10827 // CHECK12-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
10828 // CHECK12-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]]
10829 // CHECK12-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
10830 // CHECK12-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
10831 // CHECK12-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
10832 // CHECK12-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
10833 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10834 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10835 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
10836 // CHECK12-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
10837 // CHECK12-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
10838 // CHECK12-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
10839 // CHECK12-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
10840 // CHECK12-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10841 // CHECK12:       cond.true:
10842 // CHECK12-NEXT:    br label [[COND_END:%.*]]
10843 // CHECK12:       cond.false:
10844 // CHECK12-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
10845 // CHECK12-NEXT:    br label [[COND_END]]
10846 // CHECK12:       cond.end:
10847 // CHECK12-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
10848 // CHECK12-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
10849 // CHECK12-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
10850 // CHECK12-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
10851 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10852 // CHECK12:       omp.inner.for.cond:
10853 // CHECK12-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
10854 // CHECK12-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
10855 // CHECK12-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
10856 // CHECK12-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10857 // CHECK12:       omp.inner.for.body:
10858 // CHECK12-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
10859 // CHECK12-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
10860 // CHECK12-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
10861 // CHECK12-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
10862 // CHECK12-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
10863 // CHECK12-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
10864 // CHECK12-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
10865 // CHECK12-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
10866 // CHECK12-NEXT:    [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
10867 // CHECK12-NEXT:    [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
10868 // CHECK12-NEXT:    [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
10869 // CHECK12-NEXT:    store i32 [[CONV7]], i32* [[LIN2]], align 4
10870 // CHECK12-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
10871 // CHECK12-NEXT:    [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
10872 // CHECK12-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
10873 // CHECK12-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
10874 // CHECK12-NEXT:    [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
10875 // CHECK12-NEXT:    [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
10876 // CHECK12-NEXT:    [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
10877 // CHECK12-NEXT:    store i32 [[CONV11]], i32* [[A3]], align 4
10878 // CHECK12-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4
10879 // CHECK12-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
10880 // CHECK12-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
10881 // CHECK12-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
10882 // CHECK12-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4
10883 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10884 // CHECK12:       omp.body.continue:
10885 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10886 // CHECK12:       omp.inner.for.inc:
10887 // CHECK12-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
10888 // CHECK12-NEXT:    [[ADD15:%.*]] = add i64 [[TMP17]], 1
10889 // CHECK12-NEXT:    store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
10890 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]]
10891 // CHECK12:       omp.inner.for.end:
10892 // CHECK12-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10893 // CHECK12:       omp.loop.exit:
10894 // CHECK12-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
10895 // CHECK12-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10896 // CHECK12-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
10897 // CHECK12-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
10898 // CHECK12:       .omp.linear.pu:
10899 // CHECK12-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
10900 // CHECK12-NEXT:    [[CONV16:%.*]] = sext i32 [[TMP20]] to i64
10901 // CHECK12-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
10902 // CHECK12-NEXT:    [[MUL17:%.*]] = mul i64 4, [[TMP21]]
10903 // CHECK12-NEXT:    [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
10904 // CHECK12-NEXT:    [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
10905 // CHECK12-NEXT:    store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
10906 // CHECK12-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
10907 // CHECK12-NEXT:    [[CONV20:%.*]] = sext i32 [[TMP22]] to i64
10908 // CHECK12-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
10909 // CHECK12-NEXT:    [[MUL21:%.*]] = mul i64 4, [[TMP23]]
10910 // CHECK12-NEXT:    [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
10911 // CHECK12-NEXT:    [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
10912 // CHECK12-NEXT:    store i32 [[CONV23]], i32* [[A_ADDR]], align 4
10913 // CHECK12-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
10914 // CHECK12:       .omp.linear.pu.done:
10915 // CHECK12-NEXT:    ret void
10916 //
10917 //
10918 // CHECK12-LABEL: define {{[^@]+}}@_Z7get_valv
10919 // CHECK12-SAME: () #[[ATTR2:[0-9]+]] {
10920 // CHECK12-NEXT:  entry:
10921 // CHECK12-NEXT:    ret i64 0
10922 //
10923 //
10924 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
10925 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
10926 // CHECK12-NEXT:  entry:
10927 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10928 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10929 // CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10930 // CHECK12-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10931 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10932 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10933 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10934 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
10935 // CHECK12-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
10936 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
10937 // CHECK12-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
10938 // CHECK12-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10939 // CHECK12-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
10940 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10941 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
10942 // CHECK12-NEXT:    ret void
10943 //
10944 //
10945 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2
10946 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
10947 // CHECK12-NEXT:  entry:
10948 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10949 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10950 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10951 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10952 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10953 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i16, align 2
10954 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10955 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10956 // CHECK12-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10957 // CHECK12-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10958 // CHECK12-NEXT:    [[IT:%.*]] = alloca i16, align 2
10959 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10960 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10961 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10962 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10963 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10964 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10965 // CHECK12-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
10966 // CHECK12-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10967 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10968 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10969 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
10970 // CHECK12-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10971 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10972 // CHECK12-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
10973 // CHECK12-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10974 // CHECK12:       cond.true:
10975 // CHECK12-NEXT:    br label [[COND_END:%.*]]
10976 // CHECK12:       cond.false:
10977 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10978 // CHECK12-NEXT:    br label [[COND_END]]
10979 // CHECK12:       cond.end:
10980 // CHECK12-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
10981 // CHECK12-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10982 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10983 // CHECK12-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
10984 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10985 // CHECK12:       omp.inner.for.cond:
10986 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10987 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10988 // CHECK12-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
10989 // CHECK12-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10990 // CHECK12:       omp.inner.for.body:
10991 // CHECK12-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10992 // CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
10993 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
10994 // CHECK12-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
10995 // CHECK12-NEXT:    store i16 [[CONV2]], i16* [[IT]], align 2
10996 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
10997 // CHECK12-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
10998 // CHECK12-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4
10999 // CHECK12-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
11000 // CHECK12-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
11001 // CHECK12-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
11002 // CHECK12-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
11003 // CHECK12-NEXT:    store i16 [[CONV6]], i16* [[CONV]], align 4
11004 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11005 // CHECK12:       omp.body.continue:
11006 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11007 // CHECK12:       omp.inner.for.inc:
11008 // CHECK12-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11009 // CHECK12-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
11010 // CHECK12-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
11011 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]]
11012 // CHECK12:       omp.inner.for.end:
11013 // CHECK12-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11014 // CHECK12:       omp.loop.exit:
11015 // CHECK12-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
11016 // CHECK12-NEXT:    ret void
11017 //
11018 //
11019 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
11020 // CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
11021 // CHECK12-NEXT:  entry:
11022 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11023 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
11024 // CHECK12-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11025 // CHECK12-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
11026 // CHECK12-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
11027 // CHECK12-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11028 // CHECK12-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
11029 // CHECK12-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
11030 // CHECK12-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
11031 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
11032 // CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11033 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
11034 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11035 // CHECK12-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
11036 // CHECK12-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11037 // CHECK12-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
11038 // CHECK12-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
11039 // CHECK12-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11040 // CHECK12-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
11041 // CHECK12-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
11042 // CHECK12-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
11043 // CHECK12-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
11044 // CHECK12-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
11045 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11046 // CHECK12-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
11047 // CHECK12-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
11048 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11049 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
11050 // CHECK12-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
11051 // CHECK12-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
11052 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
11053 // CHECK12-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
11054 // CHECK12-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
11055 // CHECK12-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
11056 // CHECK12-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
11057 // CHECK12-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
11058 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
11059 // CHECK12-NEXT:    ret void
11060 //
11061 //
11062 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3
11063 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
11064 // CHECK12-NEXT:  entry:
11065 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11066 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11067 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11068 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
11069 // CHECK12-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11070 // CHECK12-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
11071 // CHECK12-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
11072 // CHECK12-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11073 // CHECK12-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
11074 // CHECK12-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
11075 // CHECK12-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
11076 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
11077 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11078 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i8, align 1
11079 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11080 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11081 // CHECK12-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11082 // CHECK12-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11083 // CHECK12-NEXT:    [[IT:%.*]] = alloca i8, align 1
11084 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11085 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11086 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11087 // CHECK12-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
11088 // CHECK12-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11089 // CHECK12-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
11090 // CHECK12-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
11091 // CHECK12-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11092 // CHECK12-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
11093 // CHECK12-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
11094 // CHECK12-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
11095 // CHECK12-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
11096 // CHECK12-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
11097 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11098 // CHECK12-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
11099 // CHECK12-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
11100 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11101 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
11102 // CHECK12-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
11103 // CHECK12-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
11104 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11105 // CHECK12-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
11106 // CHECK12-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11107 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11108 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
11109 // CHECK12-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11110 // CHECK12-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
11111 // CHECK12-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
11112 // CHECK12-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
11113 // CHECK12:       omp.dispatch.cond:
11114 // CHECK12-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11115 // CHECK12-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
11116 // CHECK12-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11117 // CHECK12:       cond.true:
11118 // CHECK12-NEXT:    br label [[COND_END:%.*]]
11119 // CHECK12:       cond.false:
11120 // CHECK12-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11121 // CHECK12-NEXT:    br label [[COND_END]]
11122 // CHECK12:       cond.end:
11123 // CHECK12-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
11124 // CHECK12-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11125 // CHECK12-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11126 // CHECK12-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
11127 // CHECK12-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11128 // CHECK12-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11129 // CHECK12-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
11130 // CHECK12-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
11131 // CHECK12:       omp.dispatch.body:
11132 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11133 // CHECK12:       omp.inner.for.cond:
11134 // CHECK12-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11135 // CHECK12-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11136 // CHECK12-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
11137 // CHECK12-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11138 // CHECK12:       omp.inner.for.body:
11139 // CHECK12-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11140 // CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
11141 // CHECK12-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
11142 // CHECK12-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
11143 // CHECK12-NEXT:    store i8 [[CONV]], i8* [[IT]], align 1
11144 // CHECK12-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
11145 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
11146 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
11147 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
11148 // CHECK12-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
11149 // CHECK12-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
11150 // CHECK12-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
11151 // CHECK12-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
11152 // CHECK12-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4
11153 // CHECK12-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
11154 // CHECK12-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
11155 // CHECK12-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
11156 // CHECK12-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
11157 // CHECK12-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
11158 // CHECK12-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4
11159 // CHECK12-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
11160 // CHECK12-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
11161 // CHECK12-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
11162 // CHECK12-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
11163 // CHECK12-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8
11164 // CHECK12-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
11165 // CHECK12-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
11166 // CHECK12-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
11167 // CHECK12-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
11168 // CHECK12-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
11169 // CHECK12-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8
11170 // CHECK12-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
11171 // CHECK12-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4
11172 // CHECK12-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
11173 // CHECK12-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4
11174 // CHECK12-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
11175 // CHECK12-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
11176 // CHECK12-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
11177 // CHECK12-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
11178 // CHECK12-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
11179 // CHECK12-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4
11180 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11181 // CHECK12:       omp.body.continue:
11182 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11183 // CHECK12:       omp.inner.for.inc:
11184 // CHECK12-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11185 // CHECK12-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
11186 // CHECK12-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
11187 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]]
11188 // CHECK12:       omp.inner.for.end:
11189 // CHECK12-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
11190 // CHECK12:       omp.dispatch.inc:
11191 // CHECK12-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11192 // CHECK12-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
11193 // CHECK12-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
11194 // CHECK12-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
11195 // CHECK12-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11196 // CHECK12-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
11197 // CHECK12-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
11198 // CHECK12-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
11199 // CHECK12-NEXT:    br label [[OMP_DISPATCH_COND]]
11200 // CHECK12:       omp.dispatch.end:
11201 // CHECK12-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
11202 // CHECK12-NEXT:    ret void
11203 //
11204 //
11205 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
11206 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
11207 // CHECK12-NEXT:  entry:
11208 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11209 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11210 // CHECK12-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
11211 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11212 // CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11213 // CHECK12-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11214 // CHECK12-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
11215 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11216 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11217 // CHECK12-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
11218 // CHECK12-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11219 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11220 // CHECK12-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
11221 // CHECK12-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11222 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
11223 // CHECK12-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
11224 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
11225 // CHECK12-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
11226 // CHECK12-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11227 // CHECK12-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
11228 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11229 // CHECK12-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
11230 // CHECK12-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
11231 // CHECK12-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
11232 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
11233 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
11234 // CHECK12-NEXT:    ret void
11235 //
11236 //
11237 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4
11238 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
11239 // CHECK12-NEXT:  entry:
11240 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11241 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11242 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11243 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11244 // CHECK12-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
11245 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11246 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11247 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11248 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11249 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11250 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11251 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11252 // CHECK12-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
11253 // CHECK12-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11254 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11255 // CHECK12-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
11256 // CHECK12-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11257 // CHECK12-NEXT:    ret void
11258 //
11259 //
11260 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
11261 // CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
11262 // CHECK12-NEXT:  entry:
11263 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
11264 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
11265 // CHECK12-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11266 // CHECK12-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11267 // CHECK12-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
11268 // CHECK12-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
11269 // CHECK12-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
11270 // CHECK12-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
11271 // CHECK12-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11272 // CHECK12-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11273 // CHECK12-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
11274 // CHECK12-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
11275 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11276 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11277 // CHECK12-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
11278 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
11279 // CHECK12-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
11280 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
11281 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
11282 // CHECK12-NEXT:    ret void
11283 //
11284 //
11285 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5
11286 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
11287 // CHECK12-NEXT:  entry:
11288 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11289 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11290 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
11291 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
11292 // CHECK12-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11293 // CHECK12-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11294 // CHECK12-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
11295 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
11296 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i64, align 4
11297 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
11298 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
11299 // CHECK12-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
11300 // CHECK12-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11301 // CHECK12-NEXT:    [[IT:%.*]] = alloca i64, align 8
11302 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11303 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11304 // CHECK12-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
11305 // CHECK12-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
11306 // CHECK12-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11307 // CHECK12-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11308 // CHECK12-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
11309 // CHECK12-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
11310 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11311 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11312 // CHECK12-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
11313 // CHECK12-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
11314 // CHECK12-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
11315 // CHECK12-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
11316 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11317 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11318 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
11319 // CHECK12-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
11320 // CHECK12-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
11321 // CHECK12-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
11322 // CHECK12-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11323 // CHECK12:       cond.true:
11324 // CHECK12-NEXT:    br label [[COND_END:%.*]]
11325 // CHECK12:       cond.false:
11326 // CHECK12-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
11327 // CHECK12-NEXT:    br label [[COND_END]]
11328 // CHECK12:       cond.end:
11329 // CHECK12-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
11330 // CHECK12-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
11331 // CHECK12-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
11332 // CHECK12-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
11333 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11334 // CHECK12:       omp.inner.for.cond:
11335 // CHECK12-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
11336 // CHECK12-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
11337 // CHECK12-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
11338 // CHECK12-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11339 // CHECK12:       omp.inner.for.body:
11340 // CHECK12-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
11341 // CHECK12-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
11342 // CHECK12-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
11343 // CHECK12-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
11344 // CHECK12-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
11345 // CHECK12-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
11346 // CHECK12-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
11347 // CHECK12-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
11348 // CHECK12-NEXT:    store double [[ADD]], double* [[A]], align 4
11349 // CHECK12-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
11350 // CHECK12-NEXT:    [[TMP13:%.*]] = load double, double* [[A4]], align 4
11351 // CHECK12-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
11352 // CHECK12-NEXT:    store double [[INC]], double* [[A4]], align 4
11353 // CHECK12-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
11354 // CHECK12-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
11355 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
11356 // CHECK12-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
11357 // CHECK12-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
11358 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11359 // CHECK12:       omp.body.continue:
11360 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11361 // CHECK12:       omp.inner.for.inc:
11362 // CHECK12-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
11363 // CHECK12-NEXT:    [[ADD7:%.*]] = add i64 [[TMP15]], 1
11364 // CHECK12-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
11365 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]]
11366 // CHECK12:       omp.inner.for.end:
11367 // CHECK12-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11368 // CHECK12:       omp.loop.exit:
11369 // CHECK12-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
11370 // CHECK12-NEXT:    ret void
11371 //
11372 //
11373 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
11374 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
11375 // CHECK12-NEXT:  entry:
11376 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11377 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11378 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11379 // CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11380 // CHECK12-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11381 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11382 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11383 // CHECK12-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11384 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11385 // CHECK12-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11386 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
11387 // CHECK12-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
11388 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
11389 // CHECK12-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
11390 // CHECK12-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11391 // CHECK12-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
11392 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11393 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
11394 // CHECK12-NEXT:    ret void
11395 //
11396 //
11397 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6
11398 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
11399 // CHECK12-NEXT:  entry:
11400 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11401 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11402 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11403 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11404 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11405 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
11406 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i64, align 4
11407 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
11408 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
11409 // CHECK12-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
11410 // CHECK12-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11411 // CHECK12-NEXT:    [[I:%.*]] = alloca i64, align 8
11412 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11413 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11414 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11415 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11416 // CHECK12-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11417 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11418 // CHECK12-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11419 // CHECK12-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
11420 // CHECK12-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
11421 // CHECK12-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
11422 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11423 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11424 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
11425 // CHECK12-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
11426 // CHECK12-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
11427 // CHECK12-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
11428 // CHECK12-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11429 // CHECK12:       cond.true:
11430 // CHECK12-NEXT:    br label [[COND_END:%.*]]
11431 // CHECK12:       cond.false:
11432 // CHECK12-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
11433 // CHECK12-NEXT:    br label [[COND_END]]
11434 // CHECK12:       cond.end:
11435 // CHECK12-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
11436 // CHECK12-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
11437 // CHECK12-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
11438 // CHECK12-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
11439 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11440 // CHECK12:       omp.inner.for.cond:
11441 // CHECK12-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
11442 // CHECK12-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
11443 // CHECK12-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
11444 // CHECK12-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11445 // CHECK12:       omp.inner.for.body:
11446 // CHECK12-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
11447 // CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
11448 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
11449 // CHECK12-NEXT:    store i64 [[ADD]], i64* [[I]], align 8
11450 // CHECK12-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
11451 // CHECK12-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
11452 // CHECK12-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
11453 // CHECK12-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
11454 // CHECK12-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
11455 // CHECK12-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
11456 // CHECK12-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
11457 // CHECK12-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
11458 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
11459 // CHECK12-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
11460 // CHECK12-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
11461 // CHECK12-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
11462 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11463 // CHECK12:       omp.body.continue:
11464 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11465 // CHECK12:       omp.inner.for.inc:
11466 // CHECK12-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
11467 // CHECK12-NEXT:    [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
11468 // CHECK12-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
11469 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]]
11470 // CHECK12:       omp.inner.for.end:
11471 // CHECK12-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11472 // CHECK12:       omp.loop.exit:
11473 // CHECK12-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
11474 // CHECK12-NEXT:    ret void
11475 //
11476 //
11477 // CHECK13-LABEL: define {{[^@]+}}@_Z7get_valv
11478 // CHECK13-SAME: () #[[ATTR0:[0-9]+]] {
11479 // CHECK13-NEXT:  entry:
11480 // CHECK13-NEXT:    ret i64 0
11481 //
11482 //
11483 // CHECK13-LABEL: define {{[^@]+}}@_Z3fooi
11484 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
11485 // CHECK13-NEXT:  entry:
11486 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11487 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
11488 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
11489 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
11490 // CHECK13-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
11491 // CHECK13-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
11492 // CHECK13-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
11493 // CHECK13-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
11494 // CHECK13-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
11495 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
11496 // CHECK13-NEXT:    [[K:%.*]] = alloca i64, align 8
11497 // CHECK13-NEXT:    [[I2:%.*]] = alloca i32, align 4
11498 // CHECK13-NEXT:    [[LIN:%.*]] = alloca i32, align 4
11499 // CHECK13-NEXT:    [[IT:%.*]] = alloca i64, align 8
11500 // CHECK13-NEXT:    [[IT16:%.*]] = alloca i16, align 2
11501 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
11502 // CHECK13-NEXT:    [[IT30:%.*]] = alloca i8, align 1
11503 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11504 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
11505 // CHECK13-NEXT:    store i16 0, i16* [[AA]], align 2
11506 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
11507 // CHECK13-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
11508 // CHECK13-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
11509 // CHECK13-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
11510 // CHECK13-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
11511 // CHECK13-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
11512 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
11513 // CHECK13-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
11514 // CHECK13-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
11515 // CHECK13-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
11516 // CHECK13-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
11517 // CHECK13-NEXT:    store i32 3, i32* [[I]], align 4
11518 // CHECK13-NEXT:    br label [[FOR_COND:%.*]]
11519 // CHECK13:       for.cond:
11520 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I]], align 4
11521 // CHECK13-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32
11522 // CHECK13-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
11523 // CHECK13:       for.body:
11524 // CHECK13-NEXT:    br label [[FOR_INC:%.*]]
11525 // CHECK13:       for.inc:
11526 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
11527 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP7]], 5
11528 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
11529 // CHECK13-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
11530 // CHECK13:       for.end:
11531 // CHECK13-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
11532 // CHECK13-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
11533 // CHECK13-NEXT:    store i32 10, i32* [[I2]], align 4
11534 // CHECK13-NEXT:    br label [[FOR_COND3:%.*]]
11535 // CHECK13:       for.cond3:
11536 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I2]], align 4
11537 // CHECK13-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1
11538 // CHECK13-NEXT:    br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]]
11539 // CHECK13:       for.body5:
11540 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
11541 // CHECK13-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1
11542 // CHECK13-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
11543 // CHECK13-NEXT:    br label [[FOR_INC7:%.*]]
11544 // CHECK13:       for.inc7:
11545 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I2]], align 4
11546 // CHECK13-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP10]], -1
11547 // CHECK13-NEXT:    store i32 [[DEC]], i32* [[I2]], align 4
11548 // CHECK13-NEXT:    br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]]
11549 // CHECK13:       for.end8:
11550 // CHECK13-NEXT:    store i32 12, i32* [[LIN]], align 4
11551 // CHECK13-NEXT:    store i64 2000, i64* [[IT]], align 8
11552 // CHECK13-NEXT:    br label [[FOR_COND9:%.*]]
11553 // CHECK13:       for.cond9:
11554 // CHECK13-NEXT:    [[TMP11:%.*]] = load i64, i64* [[IT]], align 8
11555 // CHECK13-NEXT:    [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600
11556 // CHECK13-NEXT:    br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]]
11557 // CHECK13:       for.body11:
11558 // CHECK13-NEXT:    [[TMP12:%.*]] = load i16, i16* [[AA]], align 2
11559 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP12]] to i32
11560 // CHECK13-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV]], 1
11561 // CHECK13-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
11562 // CHECK13-NEXT:    store i16 [[CONV13]], i16* [[AA]], align 2
11563 // CHECK13-NEXT:    br label [[FOR_INC14:%.*]]
11564 // CHECK13:       for.inc14:
11565 // CHECK13-NEXT:    [[TMP13:%.*]] = load i64, i64* [[IT]], align 8
11566 // CHECK13-NEXT:    [[SUB:%.*]] = sub i64 [[TMP13]], 400
11567 // CHECK13-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
11568 // CHECK13-NEXT:    br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]]
11569 // CHECK13:       for.end15:
11570 // CHECK13-NEXT:    store i16 6, i16* [[IT16]], align 2
11571 // CHECK13-NEXT:    br label [[FOR_COND17:%.*]]
11572 // CHECK13:       for.cond17:
11573 // CHECK13-NEXT:    [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2
11574 // CHECK13-NEXT:    [[CONV18:%.*]] = sext i16 [[TMP14]] to i32
11575 // CHECK13-NEXT:    [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20
11576 // CHECK13-NEXT:    br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]]
11577 // CHECK13:       for.body20:
11578 // CHECK13-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
11579 // CHECK13-NEXT:    [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1
11580 // CHECK13-NEXT:    store i32 [[ADD21]], i32* [[A]], align 4
11581 // CHECK13-NEXT:    [[TMP16:%.*]] = load i16, i16* [[AA]], align 2
11582 // CHECK13-NEXT:    [[CONV22:%.*]] = sext i16 [[TMP16]] to i32
11583 // CHECK13-NEXT:    [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1
11584 // CHECK13-NEXT:    [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16
11585 // CHECK13-NEXT:    store i16 [[CONV24]], i16* [[AA]], align 2
11586 // CHECK13-NEXT:    br label [[FOR_INC25:%.*]]
11587 // CHECK13:       for.inc25:
11588 // CHECK13-NEXT:    [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2
11589 // CHECK13-NEXT:    [[CONV26:%.*]] = sext i16 [[TMP17]] to i32
11590 // CHECK13-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4
11591 // CHECK13-NEXT:    [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16
11592 // CHECK13-NEXT:    store i16 [[CONV28]], i16* [[IT16]], align 2
11593 // CHECK13-NEXT:    br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]]
11594 // CHECK13:       for.end29:
11595 // CHECK13-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
11596 // CHECK13-NEXT:    store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4
11597 // CHECK13-NEXT:    store i8 122, i8* [[IT30]], align 1
11598 // CHECK13-NEXT:    br label [[FOR_COND31:%.*]]
11599 // CHECK13:       for.cond31:
11600 // CHECK13-NEXT:    [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1
11601 // CHECK13-NEXT:    [[CONV32:%.*]] = zext i8 [[TMP19]] to i32
11602 // CHECK13-NEXT:    [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97
11603 // CHECK13-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]]
11604 // CHECK13:       for.body34:
11605 // CHECK13-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A]], align 4
11606 // CHECK13-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1
11607 // CHECK13-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
11608 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
11609 // CHECK13-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4
11610 // CHECK13-NEXT:    [[CONV36:%.*]] = fpext float [[TMP21]] to double
11611 // CHECK13-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
11612 // CHECK13-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
11613 // CHECK13-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
11614 // CHECK13-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
11615 // CHECK13-NEXT:    [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4
11616 // CHECK13-NEXT:    [[CONV40:%.*]] = fpext float [[TMP22]] to double
11617 // CHECK13-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
11618 // CHECK13-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
11619 // CHECK13-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
11620 // CHECK13-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
11621 // CHECK13-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2
11622 // CHECK13-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8
11623 // CHECK13-NEXT:    [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00
11624 // CHECK13-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
11625 // CHECK13-NEXT:    [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]]
11626 // CHECK13-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]]
11627 // CHECK13-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3
11628 // CHECK13-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8
11629 // CHECK13-NEXT:    [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00
11630 // CHECK13-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
11631 // CHECK13-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
11632 // CHECK13-NEXT:    [[TMP26:%.*]] = load i64, i64* [[X]], align 8
11633 // CHECK13-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1
11634 // CHECK13-NEXT:    store i64 [[ADD49]], i64* [[X]], align 8
11635 // CHECK13-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
11636 // CHECK13-NEXT:    [[TMP27:%.*]] = load i8, i8* [[Y]], align 8
11637 // CHECK13-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP27]] to i32
11638 // CHECK13-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
11639 // CHECK13-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
11640 // CHECK13-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 8
11641 // CHECK13-NEXT:    br label [[FOR_INC53:%.*]]
11642 // CHECK13:       for.inc53:
11643 // CHECK13-NEXT:    [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1
11644 // CHECK13-NEXT:    [[CONV54:%.*]] = zext i8 [[TMP28]] to i32
11645 // CHECK13-NEXT:    [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1
11646 // CHECK13-NEXT:    [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8
11647 // CHECK13-NEXT:    store i8 [[CONV56]], i8* [[IT30]], align 1
11648 // CHECK13-NEXT:    br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]]
11649 // CHECK13:       for.end57:
11650 // CHECK13-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
11651 // CHECK13-NEXT:    [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
11652 // CHECK13-NEXT:    call void @llvm.stackrestore(i8* [[TMP30]])
11653 // CHECK13-NEXT:    ret i32 [[TMP29]]
11654 //
11655 //
11656 // CHECK13-LABEL: define {{[^@]+}}@_Z3bari
11657 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
11658 // CHECK13-NEXT:  entry:
11659 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11660 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
11661 // CHECK13-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
11662 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11663 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
11664 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
11665 // CHECK13-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
11666 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
11667 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
11668 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
11669 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
11670 // CHECK13-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
11671 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
11672 // CHECK13-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
11673 // CHECK13-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
11674 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
11675 // CHECK13-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
11676 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
11677 // CHECK13-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
11678 // CHECK13-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
11679 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
11680 // CHECK13-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
11681 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
11682 // CHECK13-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
11683 // CHECK13-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
11684 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
11685 // CHECK13-NEXT:    ret i32 [[TMP8]]
11686 //
11687 //
11688 // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
11689 // CHECK13-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
11690 // CHECK13-NEXT:  entry:
11691 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
11692 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11693 // CHECK13-NEXT:    [[B:%.*]] = alloca i32, align 4
11694 // CHECK13-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
11695 // CHECK13-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
11696 // CHECK13-NEXT:    [[IT:%.*]] = alloca i64, align 8
11697 // CHECK13-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
11698 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11699 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
11700 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
11701 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
11702 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
11703 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
11704 // CHECK13-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
11705 // CHECK13-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
11706 // CHECK13-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
11707 // CHECK13-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
11708 // CHECK13-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
11709 // CHECK13-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
11710 // CHECK13-NEXT:    store i64 2000, i64* [[IT]], align 8
11711 // CHECK13-NEXT:    br label [[FOR_COND:%.*]]
11712 // CHECK13:       for.cond:
11713 // CHECK13-NEXT:    [[TMP5:%.*]] = load i64, i64* [[IT]], align 8
11714 // CHECK13-NEXT:    [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600
11715 // CHECK13-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
11716 // CHECK13:       for.body:
11717 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
11718 // CHECK13-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP6]] to double
11719 // CHECK13-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
11720 // CHECK13-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
11721 // CHECK13-NEXT:    store double [[ADD2]], double* [[A]], align 8
11722 // CHECK13-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
11723 // CHECK13-NEXT:    [[TMP7:%.*]] = load double, double* [[A3]], align 8
11724 // CHECK13-NEXT:    [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
11725 // CHECK13-NEXT:    store double [[INC]], double* [[A3]], align 8
11726 // CHECK13-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
11727 // CHECK13-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
11728 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
11729 // CHECK13-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
11730 // CHECK13-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
11731 // CHECK13-NEXT:    br label [[FOR_INC:%.*]]
11732 // CHECK13:       for.inc:
11733 // CHECK13-NEXT:    [[TMP9:%.*]] = load i64, i64* [[IT]], align 8
11734 // CHECK13-NEXT:    [[SUB:%.*]] = sub i64 [[TMP9]], 400
11735 // CHECK13-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
11736 // CHECK13-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
11737 // CHECK13:       for.end:
11738 // CHECK13-NEXT:    [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
11739 // CHECK13-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]]
11740 // CHECK13-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
11741 // CHECK13-NEXT:    [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
11742 // CHECK13-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP11]] to i32
11743 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B]], align 4
11744 // CHECK13-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]]
11745 // CHECK13-NEXT:    [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
11746 // CHECK13-NEXT:    call void @llvm.stackrestore(i8* [[TMP13]])
11747 // CHECK13-NEXT:    ret i32 [[ADD9]]
11748 //
11749 //
11750 // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici
11751 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
11752 // CHECK13-NEXT:  entry:
11753 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11754 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
11755 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
11756 // CHECK13-NEXT:    [[AAA:%.*]] = alloca i8, align 1
11757 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
11758 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
11759 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11760 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
11761 // CHECK13-NEXT:    store i16 0, i16* [[AA]], align 2
11762 // CHECK13-NEXT:    store i8 0, i8* [[AAA]], align 1
11763 // CHECK13-NEXT:    store i32 100, i32* [[I]], align 4
11764 // CHECK13-NEXT:    br label [[FOR_COND:%.*]]
11765 // CHECK13:       for.cond:
11766 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
11767 // CHECK13-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10
11768 // CHECK13-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
11769 // CHECK13:       for.body:
11770 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
11771 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
11772 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
11773 // CHECK13-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
11774 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
11775 // CHECK13-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
11776 // CHECK13-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
11777 // CHECK13-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
11778 // CHECK13-NEXT:    [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1
11779 // CHECK13-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
11780 // CHECK13-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
11781 // CHECK13-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
11782 // CHECK13-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
11783 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
11784 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
11785 // CHECK13-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
11786 // CHECK13-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
11787 // CHECK13-NEXT:    br label [[FOR_INC:%.*]]
11788 // CHECK13:       for.inc:
11789 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
11790 // CHECK13-NEXT:    [[ADD7:%.*]] = add i32 [[TMP5]], 10
11791 // CHECK13-NEXT:    store i32 [[ADD7]], i32* [[I]], align 4
11792 // CHECK13-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
11793 // CHECK13:       for.end:
11794 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
11795 // CHECK13-NEXT:    ret i32 [[TMP6]]
11796 //
11797 //
11798 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
11799 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
11800 // CHECK13-NEXT:  entry:
11801 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11802 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
11803 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
11804 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
11805 // CHECK13-NEXT:    [[I:%.*]] = alloca i64, align 8
11806 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11807 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
11808 // CHECK13-NEXT:    store i16 0, i16* [[AA]], align 2
11809 // CHECK13-NEXT:    store i64 -10, i64* [[I]], align 8
11810 // CHECK13-NEXT:    br label [[FOR_COND:%.*]]
11811 // CHECK13:       for.cond:
11812 // CHECK13-NEXT:    [[TMP0:%.*]] = load i64, i64* [[I]], align 8
11813 // CHECK13-NEXT:    [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10
11814 // CHECK13-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
11815 // CHECK13:       for.body:
11816 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
11817 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
11818 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
11819 // CHECK13-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
11820 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
11821 // CHECK13-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
11822 // CHECK13-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
11823 // CHECK13-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
11824 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
11825 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
11826 // CHECK13-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
11827 // CHECK13-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
11828 // CHECK13-NEXT:    br label [[FOR_INC:%.*]]
11829 // CHECK13:       for.inc:
11830 // CHECK13-NEXT:    [[TMP4:%.*]] = load i64, i64* [[I]], align 8
11831 // CHECK13-NEXT:    [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3
11832 // CHECK13-NEXT:    store i64 [[ADD4]], i64* [[I]], align 8
11833 // CHECK13-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
11834 // CHECK13:       for.end:
11835 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
11836 // CHECK13-NEXT:    ret i32 [[TMP5]]
11837 //
11838 //
11839 // CHECK14-LABEL: define {{[^@]+}}@_Z7get_valv
11840 // CHECK14-SAME: () #[[ATTR0:[0-9]+]] {
11841 // CHECK14-NEXT:  entry:
11842 // CHECK14-NEXT:    ret i64 0
11843 //
11844 //
11845 // CHECK14-LABEL: define {{[^@]+}}@_Z3fooi
11846 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
11847 // CHECK14-NEXT:  entry:
11848 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11849 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
11850 // CHECK14-NEXT:    [[AA:%.*]] = alloca i16, align 2
11851 // CHECK14-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
11852 // CHECK14-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
11853 // CHECK14-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
11854 // CHECK14-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
11855 // CHECK14-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
11856 // CHECK14-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
11857 // CHECK14-NEXT:    [[I:%.*]] = alloca i32, align 4
11858 // CHECK14-NEXT:    [[K:%.*]] = alloca i64, align 8
11859 // CHECK14-NEXT:    [[I2:%.*]] = alloca i32, align 4
11860 // CHECK14-NEXT:    [[LIN:%.*]] = alloca i32, align 4
11861 // CHECK14-NEXT:    [[IT:%.*]] = alloca i64, align 8
11862 // CHECK14-NEXT:    [[IT16:%.*]] = alloca i16, align 2
11863 // CHECK14-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
11864 // CHECK14-NEXT:    [[IT30:%.*]] = alloca i8, align 1
11865 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11866 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
11867 // CHECK14-NEXT:    store i16 0, i16* [[AA]], align 2
11868 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
11869 // CHECK14-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
11870 // CHECK14-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
11871 // CHECK14-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
11872 // CHECK14-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
11873 // CHECK14-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
11874 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
11875 // CHECK14-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
11876 // CHECK14-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
11877 // CHECK14-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
11878 // CHECK14-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
11879 // CHECK14-NEXT:    store i32 3, i32* [[I]], align 4
11880 // CHECK14-NEXT:    br label [[FOR_COND:%.*]]
11881 // CHECK14:       for.cond:
11882 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I]], align 4
11883 // CHECK14-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32
11884 // CHECK14-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
11885 // CHECK14:       for.body:
11886 // CHECK14-NEXT:    br label [[FOR_INC:%.*]]
11887 // CHECK14:       for.inc:
11888 // CHECK14-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
11889 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP7]], 5
11890 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
11891 // CHECK14-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
11892 // CHECK14:       for.end:
11893 // CHECK14-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
11894 // CHECK14-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
11895 // CHECK14-NEXT:    store i32 10, i32* [[I2]], align 4
11896 // CHECK14-NEXT:    br label [[FOR_COND3:%.*]]
11897 // CHECK14:       for.cond3:
11898 // CHECK14-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I2]], align 4
11899 // CHECK14-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1
11900 // CHECK14-NEXT:    br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]]
11901 // CHECK14:       for.body5:
11902 // CHECK14-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
11903 // CHECK14-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1
11904 // CHECK14-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
11905 // CHECK14-NEXT:    br label [[FOR_INC7:%.*]]
11906 // CHECK14:       for.inc7:
11907 // CHECK14-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I2]], align 4
11908 // CHECK14-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP10]], -1
11909 // CHECK14-NEXT:    store i32 [[DEC]], i32* [[I2]], align 4
11910 // CHECK14-NEXT:    br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]]
11911 // CHECK14:       for.end8:
11912 // CHECK14-NEXT:    store i32 12, i32* [[LIN]], align 4
11913 // CHECK14-NEXT:    store i64 2000, i64* [[IT]], align 8
11914 // CHECK14-NEXT:    br label [[FOR_COND9:%.*]]
11915 // CHECK14:       for.cond9:
11916 // CHECK14-NEXT:    [[TMP11:%.*]] = load i64, i64* [[IT]], align 8
11917 // CHECK14-NEXT:    [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600
11918 // CHECK14-NEXT:    br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]]
11919 // CHECK14:       for.body11:
11920 // CHECK14-NEXT:    [[TMP12:%.*]] = load i16, i16* [[AA]], align 2
11921 // CHECK14-NEXT:    [[CONV:%.*]] = sext i16 [[TMP12]] to i32
11922 // CHECK14-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV]], 1
11923 // CHECK14-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
11924 // CHECK14-NEXT:    store i16 [[CONV13]], i16* [[AA]], align 2
11925 // CHECK14-NEXT:    br label [[FOR_INC14:%.*]]
11926 // CHECK14:       for.inc14:
11927 // CHECK14-NEXT:    [[TMP13:%.*]] = load i64, i64* [[IT]], align 8
11928 // CHECK14-NEXT:    [[SUB:%.*]] = sub i64 [[TMP13]], 400
11929 // CHECK14-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
11930 // CHECK14-NEXT:    br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]]
11931 // CHECK14:       for.end15:
11932 // CHECK14-NEXT:    store i16 6, i16* [[IT16]], align 2
11933 // CHECK14-NEXT:    br label [[FOR_COND17:%.*]]
11934 // CHECK14:       for.cond17:
11935 // CHECK14-NEXT:    [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2
11936 // CHECK14-NEXT:    [[CONV18:%.*]] = sext i16 [[TMP14]] to i32
11937 // CHECK14-NEXT:    [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20
11938 // CHECK14-NEXT:    br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]]
11939 // CHECK14:       for.body20:
11940 // CHECK14-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
11941 // CHECK14-NEXT:    [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1
11942 // CHECK14-NEXT:    store i32 [[ADD21]], i32* [[A]], align 4
11943 // CHECK14-NEXT:    [[TMP16:%.*]] = load i16, i16* [[AA]], align 2
11944 // CHECK14-NEXT:    [[CONV22:%.*]] = sext i16 [[TMP16]] to i32
11945 // CHECK14-NEXT:    [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1
11946 // CHECK14-NEXT:    [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16
11947 // CHECK14-NEXT:    store i16 [[CONV24]], i16* [[AA]], align 2
11948 // CHECK14-NEXT:    br label [[FOR_INC25:%.*]]
11949 // CHECK14:       for.inc25:
11950 // CHECK14-NEXT:    [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2
11951 // CHECK14-NEXT:    [[CONV26:%.*]] = sext i16 [[TMP17]] to i32
11952 // CHECK14-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4
11953 // CHECK14-NEXT:    [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16
11954 // CHECK14-NEXT:    store i16 [[CONV28]], i16* [[IT16]], align 2
11955 // CHECK14-NEXT:    br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]]
11956 // CHECK14:       for.end29:
11957 // CHECK14-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
11958 // CHECK14-NEXT:    store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4
11959 // CHECK14-NEXT:    store i8 122, i8* [[IT30]], align 1
11960 // CHECK14-NEXT:    br label [[FOR_COND31:%.*]]
11961 // CHECK14:       for.cond31:
11962 // CHECK14-NEXT:    [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1
11963 // CHECK14-NEXT:    [[CONV32:%.*]] = zext i8 [[TMP19]] to i32
11964 // CHECK14-NEXT:    [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97
11965 // CHECK14-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]]
11966 // CHECK14:       for.body34:
11967 // CHECK14-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A]], align 4
11968 // CHECK14-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1
11969 // CHECK14-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
11970 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
11971 // CHECK14-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4
11972 // CHECK14-NEXT:    [[CONV36:%.*]] = fpext float [[TMP21]] to double
11973 // CHECK14-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
11974 // CHECK14-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
11975 // CHECK14-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
11976 // CHECK14-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
11977 // CHECK14-NEXT:    [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4
11978 // CHECK14-NEXT:    [[CONV40:%.*]] = fpext float [[TMP22]] to double
11979 // CHECK14-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
11980 // CHECK14-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
11981 // CHECK14-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
11982 // CHECK14-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
11983 // CHECK14-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2
11984 // CHECK14-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8
11985 // CHECK14-NEXT:    [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00
11986 // CHECK14-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
11987 // CHECK14-NEXT:    [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]]
11988 // CHECK14-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]]
11989 // CHECK14-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3
11990 // CHECK14-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8
11991 // CHECK14-NEXT:    [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00
11992 // CHECK14-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
11993 // CHECK14-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
11994 // CHECK14-NEXT:    [[TMP26:%.*]] = load i64, i64* [[X]], align 8
11995 // CHECK14-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1
11996 // CHECK14-NEXT:    store i64 [[ADD49]], i64* [[X]], align 8
11997 // CHECK14-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
11998 // CHECK14-NEXT:    [[TMP27:%.*]] = load i8, i8* [[Y]], align 8
11999 // CHECK14-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP27]] to i32
12000 // CHECK14-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
12001 // CHECK14-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
12002 // CHECK14-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 8
12003 // CHECK14-NEXT:    br label [[FOR_INC53:%.*]]
12004 // CHECK14:       for.inc53:
12005 // CHECK14-NEXT:    [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1
12006 // CHECK14-NEXT:    [[CONV54:%.*]] = zext i8 [[TMP28]] to i32
12007 // CHECK14-NEXT:    [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1
12008 // CHECK14-NEXT:    [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8
12009 // CHECK14-NEXT:    store i8 [[CONV56]], i8* [[IT30]], align 1
12010 // CHECK14-NEXT:    br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]]
12011 // CHECK14:       for.end57:
12012 // CHECK14-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
12013 // CHECK14-NEXT:    [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
12014 // CHECK14-NEXT:    call void @llvm.stackrestore(i8* [[TMP30]])
12015 // CHECK14-NEXT:    ret i32 [[TMP29]]
12016 //
12017 //
12018 // CHECK14-LABEL: define {{[^@]+}}@_Z3bari
12019 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
12020 // CHECK14-NEXT:  entry:
12021 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12022 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
12023 // CHECK14-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
12024 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12025 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
12026 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12027 // CHECK14-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
12028 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12029 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
12030 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12031 // CHECK14-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12032 // CHECK14-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
12033 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
12034 // CHECK14-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
12035 // CHECK14-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
12036 // CHECK14-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
12037 // CHECK14-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
12038 // CHECK14-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12039 // CHECK14-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
12040 // CHECK14-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
12041 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
12042 // CHECK14-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
12043 // CHECK14-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
12044 // CHECK14-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
12045 // CHECK14-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
12046 // CHECK14-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
12047 // CHECK14-NEXT:    ret i32 [[TMP8]]
12048 //
12049 //
12050 // CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
12051 // CHECK14-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
12052 // CHECK14-NEXT:  entry:
12053 // CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
12054 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12055 // CHECK14-NEXT:    [[B:%.*]] = alloca i32, align 4
12056 // CHECK14-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
12057 // CHECK14-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
12058 // CHECK14-NEXT:    [[IT:%.*]] = alloca i64, align 8
12059 // CHECK14-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
12060 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12061 // CHECK14-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
12062 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12063 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12064 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
12065 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
12066 // CHECK14-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
12067 // CHECK14-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
12068 // CHECK14-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
12069 // CHECK14-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
12070 // CHECK14-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
12071 // CHECK14-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
12072 // CHECK14-NEXT:    store i64 2000, i64* [[IT]], align 8
12073 // CHECK14-NEXT:    br label [[FOR_COND:%.*]]
12074 // CHECK14:       for.cond:
12075 // CHECK14-NEXT:    [[TMP5:%.*]] = load i64, i64* [[IT]], align 8
12076 // CHECK14-NEXT:    [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600
12077 // CHECK14-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12078 // CHECK14:       for.body:
12079 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
12080 // CHECK14-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP6]] to double
12081 // CHECK14-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
12082 // CHECK14-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
12083 // CHECK14-NEXT:    store double [[ADD2]], double* [[A]], align 8
12084 // CHECK14-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
12085 // CHECK14-NEXT:    [[TMP7:%.*]] = load double, double* [[A3]], align 8
12086 // CHECK14-NEXT:    [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
12087 // CHECK14-NEXT:    store double [[INC]], double* [[A3]], align 8
12088 // CHECK14-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
12089 // CHECK14-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
12090 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
12091 // CHECK14-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
12092 // CHECK14-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
12093 // CHECK14-NEXT:    br label [[FOR_INC:%.*]]
12094 // CHECK14:       for.inc:
12095 // CHECK14-NEXT:    [[TMP9:%.*]] = load i64, i64* [[IT]], align 8
12096 // CHECK14-NEXT:    [[SUB:%.*]] = sub i64 [[TMP9]], 400
12097 // CHECK14-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
12098 // CHECK14-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
12099 // CHECK14:       for.end:
12100 // CHECK14-NEXT:    [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
12101 // CHECK14-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]]
12102 // CHECK14-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
12103 // CHECK14-NEXT:    [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
12104 // CHECK14-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP11]] to i32
12105 // CHECK14-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B]], align 4
12106 // CHECK14-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]]
12107 // CHECK14-NEXT:    [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
12108 // CHECK14-NEXT:    call void @llvm.stackrestore(i8* [[TMP13]])
12109 // CHECK14-NEXT:    ret i32 [[ADD9]]
12110 //
12111 //
12112 // CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici
12113 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
12114 // CHECK14-NEXT:  entry:
12115 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12116 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
12117 // CHECK14-NEXT:    [[AA:%.*]] = alloca i16, align 2
12118 // CHECK14-NEXT:    [[AAA:%.*]] = alloca i8, align 1
12119 // CHECK14-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12120 // CHECK14-NEXT:    [[I:%.*]] = alloca i32, align 4
12121 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12122 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
12123 // CHECK14-NEXT:    store i16 0, i16* [[AA]], align 2
12124 // CHECK14-NEXT:    store i8 0, i8* [[AAA]], align 1
12125 // CHECK14-NEXT:    store i32 100, i32* [[I]], align 4
12126 // CHECK14-NEXT:    br label [[FOR_COND:%.*]]
12127 // CHECK14:       for.cond:
12128 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
12129 // CHECK14-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10
12130 // CHECK14-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12131 // CHECK14:       for.body:
12132 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12133 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
12134 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12135 // CHECK14-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
12136 // CHECK14-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
12137 // CHECK14-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12138 // CHECK14-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12139 // CHECK14-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12140 // CHECK14-NEXT:    [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1
12141 // CHECK14-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
12142 // CHECK14-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
12143 // CHECK14-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
12144 // CHECK14-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
12145 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
12146 // CHECK14-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12147 // CHECK14-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
12148 // CHECK14-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
12149 // CHECK14-NEXT:    br label [[FOR_INC:%.*]]
12150 // CHECK14:       for.inc:
12151 // CHECK14-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
12152 // CHECK14-NEXT:    [[ADD7:%.*]] = add i32 [[TMP5]], 10
12153 // CHECK14-NEXT:    store i32 [[ADD7]], i32* [[I]], align 4
12154 // CHECK14-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
12155 // CHECK14:       for.end:
12156 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
12157 // CHECK14-NEXT:    ret i32 [[TMP6]]
12158 //
12159 //
12160 // CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
12161 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
12162 // CHECK14-NEXT:  entry:
12163 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12164 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
12165 // CHECK14-NEXT:    [[AA:%.*]] = alloca i16, align 2
12166 // CHECK14-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12167 // CHECK14-NEXT:    [[I:%.*]] = alloca i64, align 8
12168 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12169 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
12170 // CHECK14-NEXT:    store i16 0, i16* [[AA]], align 2
12171 // CHECK14-NEXT:    store i64 -10, i64* [[I]], align 8
12172 // CHECK14-NEXT:    br label [[FOR_COND:%.*]]
12173 // CHECK14:       for.cond:
12174 // CHECK14-NEXT:    [[TMP0:%.*]] = load i64, i64* [[I]], align 8
12175 // CHECK14-NEXT:    [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10
12176 // CHECK14-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12177 // CHECK14:       for.body:
12178 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12179 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
12180 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12181 // CHECK14-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
12182 // CHECK14-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
12183 // CHECK14-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12184 // CHECK14-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12185 // CHECK14-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12186 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
12187 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12188 // CHECK14-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
12189 // CHECK14-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
12190 // CHECK14-NEXT:    br label [[FOR_INC:%.*]]
12191 // CHECK14:       for.inc:
12192 // CHECK14-NEXT:    [[TMP4:%.*]] = load i64, i64* [[I]], align 8
12193 // CHECK14-NEXT:    [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3
12194 // CHECK14-NEXT:    store i64 [[ADD4]], i64* [[I]], align 8
12195 // CHECK14-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
12196 // CHECK14:       for.end:
12197 // CHECK14-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12198 // CHECK14-NEXT:    ret i32 [[TMP5]]
12199 //
12200 //
12201 // CHECK15-LABEL: define {{[^@]+}}@_Z7get_valv
12202 // CHECK15-SAME: () #[[ATTR0:[0-9]+]] {
12203 // CHECK15-NEXT:  entry:
12204 // CHECK15-NEXT:    ret i64 0
12205 //
12206 //
12207 // CHECK15-LABEL: define {{[^@]+}}@_Z3fooi
12208 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
12209 // CHECK15-NEXT:  entry:
12210 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12211 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
12212 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
12213 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
12214 // CHECK15-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
12215 // CHECK15-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
12216 // CHECK15-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
12217 // CHECK15-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
12218 // CHECK15-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
12219 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
12220 // CHECK15-NEXT:    [[K:%.*]] = alloca i64, align 8
12221 // CHECK15-NEXT:    [[I2:%.*]] = alloca i32, align 4
12222 // CHECK15-NEXT:    [[LIN:%.*]] = alloca i32, align 4
12223 // CHECK15-NEXT:    [[IT:%.*]] = alloca i64, align 8
12224 // CHECK15-NEXT:    [[IT16:%.*]] = alloca i16, align 2
12225 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
12226 // CHECK15-NEXT:    [[IT30:%.*]] = alloca i8, align 1
12227 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12228 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
12229 // CHECK15-NEXT:    store i16 0, i16* [[AA]], align 2
12230 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12231 // CHECK15-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
12232 // CHECK15-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
12233 // CHECK15-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
12234 // CHECK15-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
12235 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12236 // CHECK15-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
12237 // CHECK15-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
12238 // CHECK15-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
12239 // CHECK15-NEXT:    store i32 3, i32* [[I]], align 4
12240 // CHECK15-NEXT:    br label [[FOR_COND:%.*]]
12241 // CHECK15:       for.cond:
12242 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
12243 // CHECK15-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32
12244 // CHECK15-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12245 // CHECK15:       for.body:
12246 // CHECK15-NEXT:    br label [[FOR_INC:%.*]]
12247 // CHECK15:       for.inc:
12248 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
12249 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP5]], 5
12250 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
12251 // CHECK15-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
12252 // CHECK15:       for.end:
12253 // CHECK15-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
12254 // CHECK15-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
12255 // CHECK15-NEXT:    store i32 10, i32* [[I2]], align 4
12256 // CHECK15-NEXT:    br label [[FOR_COND3:%.*]]
12257 // CHECK15:       for.cond3:
12258 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I2]], align 4
12259 // CHECK15-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1
12260 // CHECK15-NEXT:    br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]]
12261 // CHECK15:       for.body5:
12262 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
12263 // CHECK15-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1
12264 // CHECK15-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
12265 // CHECK15-NEXT:    br label [[FOR_INC7:%.*]]
12266 // CHECK15:       for.inc7:
12267 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I2]], align 4
12268 // CHECK15-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP8]], -1
12269 // CHECK15-NEXT:    store i32 [[DEC]], i32* [[I2]], align 4
12270 // CHECK15-NEXT:    br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]]
12271 // CHECK15:       for.end8:
12272 // CHECK15-NEXT:    store i32 12, i32* [[LIN]], align 4
12273 // CHECK15-NEXT:    store i64 2000, i64* [[IT]], align 8
12274 // CHECK15-NEXT:    br label [[FOR_COND9:%.*]]
12275 // CHECK15:       for.cond9:
12276 // CHECK15-NEXT:    [[TMP9:%.*]] = load i64, i64* [[IT]], align 8
12277 // CHECK15-NEXT:    [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600
12278 // CHECK15-NEXT:    br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]]
12279 // CHECK15:       for.body11:
12280 // CHECK15-NEXT:    [[TMP10:%.*]] = load i16, i16* [[AA]], align 2
12281 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
12282 // CHECK15-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV]], 1
12283 // CHECK15-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
12284 // CHECK15-NEXT:    store i16 [[CONV13]], i16* [[AA]], align 2
12285 // CHECK15-NEXT:    br label [[FOR_INC14:%.*]]
12286 // CHECK15:       for.inc14:
12287 // CHECK15-NEXT:    [[TMP11:%.*]] = load i64, i64* [[IT]], align 8
12288 // CHECK15-NEXT:    [[SUB:%.*]] = sub i64 [[TMP11]], 400
12289 // CHECK15-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
12290 // CHECK15-NEXT:    br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]]
12291 // CHECK15:       for.end15:
12292 // CHECK15-NEXT:    store i16 6, i16* [[IT16]], align 2
12293 // CHECK15-NEXT:    br label [[FOR_COND17:%.*]]
12294 // CHECK15:       for.cond17:
12295 // CHECK15-NEXT:    [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2
12296 // CHECK15-NEXT:    [[CONV18:%.*]] = sext i16 [[TMP12]] to i32
12297 // CHECK15-NEXT:    [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20
12298 // CHECK15-NEXT:    br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]]
12299 // CHECK15:       for.body20:
12300 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4
12301 // CHECK15-NEXT:    [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1
12302 // CHECK15-NEXT:    store i32 [[ADD21]], i32* [[A]], align 4
12303 // CHECK15-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2
12304 // CHECK15-NEXT:    [[CONV22:%.*]] = sext i16 [[TMP14]] to i32
12305 // CHECK15-NEXT:    [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1
12306 // CHECK15-NEXT:    [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16
12307 // CHECK15-NEXT:    store i16 [[CONV24]], i16* [[AA]], align 2
12308 // CHECK15-NEXT:    br label [[FOR_INC25:%.*]]
12309 // CHECK15:       for.inc25:
12310 // CHECK15-NEXT:    [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2
12311 // CHECK15-NEXT:    [[CONV26:%.*]] = sext i16 [[TMP15]] to i32
12312 // CHECK15-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4
12313 // CHECK15-NEXT:    [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16
12314 // CHECK15-NEXT:    store i16 [[CONV28]], i16* [[IT16]], align 2
12315 // CHECK15-NEXT:    br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]]
12316 // CHECK15:       for.end29:
12317 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4
12318 // CHECK15-NEXT:    store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4
12319 // CHECK15-NEXT:    store i8 122, i8* [[IT30]], align 1
12320 // CHECK15-NEXT:    br label [[FOR_COND31:%.*]]
12321 // CHECK15:       for.cond31:
12322 // CHECK15-NEXT:    [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1
12323 // CHECK15-NEXT:    [[CONV32:%.*]] = zext i8 [[TMP17]] to i32
12324 // CHECK15-NEXT:    [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97
12325 // CHECK15-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]]
12326 // CHECK15:       for.body34:
12327 // CHECK15-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
12328 // CHECK15-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1
12329 // CHECK15-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
12330 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
12331 // CHECK15-NEXT:    [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4
12332 // CHECK15-NEXT:    [[CONV36:%.*]] = fpext float [[TMP19]] to double
12333 // CHECK15-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
12334 // CHECK15-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
12335 // CHECK15-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
12336 // CHECK15-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
12337 // CHECK15-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4
12338 // CHECK15-NEXT:    [[CONV40:%.*]] = fpext float [[TMP20]] to double
12339 // CHECK15-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
12340 // CHECK15-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
12341 // CHECK15-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
12342 // CHECK15-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
12343 // CHECK15-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2
12344 // CHECK15-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8
12345 // CHECK15-NEXT:    [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00
12346 // CHECK15-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
12347 // CHECK15-NEXT:    [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]]
12348 // CHECK15-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]]
12349 // CHECK15-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3
12350 // CHECK15-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8
12351 // CHECK15-NEXT:    [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00
12352 // CHECK15-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
12353 // CHECK15-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
12354 // CHECK15-NEXT:    [[TMP24:%.*]] = load i64, i64* [[X]], align 4
12355 // CHECK15-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1
12356 // CHECK15-NEXT:    store i64 [[ADD49]], i64* [[X]], align 4
12357 // CHECK15-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
12358 // CHECK15-NEXT:    [[TMP25:%.*]] = load i8, i8* [[Y]], align 4
12359 // CHECK15-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP25]] to i32
12360 // CHECK15-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
12361 // CHECK15-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
12362 // CHECK15-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 4
12363 // CHECK15-NEXT:    br label [[FOR_INC53:%.*]]
12364 // CHECK15:       for.inc53:
12365 // CHECK15-NEXT:    [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1
12366 // CHECK15-NEXT:    [[CONV54:%.*]] = zext i8 [[TMP26]] to i32
12367 // CHECK15-NEXT:    [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1
12368 // CHECK15-NEXT:    [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8
12369 // CHECK15-NEXT:    store i8 [[CONV56]], i8* [[IT30]], align 1
12370 // CHECK15-NEXT:    br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]]
12371 // CHECK15:       for.end57:
12372 // CHECK15-NEXT:    [[TMP27:%.*]] = load i32, i32* [[A]], align 4
12373 // CHECK15-NEXT:    [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
12374 // CHECK15-NEXT:    call void @llvm.stackrestore(i8* [[TMP28]])
12375 // CHECK15-NEXT:    ret i32 [[TMP27]]
12376 //
12377 //
12378 // CHECK15-LABEL: define {{[^@]+}}@_Z3bari
12379 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
12380 // CHECK15-NEXT:  entry:
12381 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12382 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
12383 // CHECK15-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
12384 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12385 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
12386 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12387 // CHECK15-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
12388 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12389 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
12390 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12391 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12392 // CHECK15-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
12393 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
12394 // CHECK15-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
12395 // CHECK15-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
12396 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
12397 // CHECK15-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
12398 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12399 // CHECK15-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
12400 // CHECK15-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
12401 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
12402 // CHECK15-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
12403 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
12404 // CHECK15-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
12405 // CHECK15-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
12406 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
12407 // CHECK15-NEXT:    ret i32 [[TMP8]]
12408 //
12409 //
12410 // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
12411 // CHECK15-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
12412 // CHECK15-NEXT:  entry:
12413 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
12414 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12415 // CHECK15-NEXT:    [[B:%.*]] = alloca i32, align 4
12416 // CHECK15-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
12417 // CHECK15-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
12418 // CHECK15-NEXT:    [[IT:%.*]] = alloca i64, align 8
12419 // CHECK15-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
12420 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12421 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
12422 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12423 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12424 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
12425 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
12426 // CHECK15-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
12427 // CHECK15-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
12428 // CHECK15-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
12429 // CHECK15-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
12430 // CHECK15-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
12431 // CHECK15-NEXT:    store i64 2000, i64* [[IT]], align 8
12432 // CHECK15-NEXT:    br label [[FOR_COND:%.*]]
12433 // CHECK15:       for.cond:
12434 // CHECK15-NEXT:    [[TMP4:%.*]] = load i64, i64* [[IT]], align 8
12435 // CHECK15-NEXT:    [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600
12436 // CHECK15-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12437 // CHECK15:       for.body:
12438 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
12439 // CHECK15-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
12440 // CHECK15-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
12441 // CHECK15-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
12442 // CHECK15-NEXT:    store double [[ADD2]], double* [[A]], align 4
12443 // CHECK15-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
12444 // CHECK15-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 4
12445 // CHECK15-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
12446 // CHECK15-NEXT:    store double [[INC]], double* [[A3]], align 4
12447 // CHECK15-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
12448 // CHECK15-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
12449 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
12450 // CHECK15-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
12451 // CHECK15-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
12452 // CHECK15-NEXT:    br label [[FOR_INC:%.*]]
12453 // CHECK15:       for.inc:
12454 // CHECK15-NEXT:    [[TMP8:%.*]] = load i64, i64* [[IT]], align 8
12455 // CHECK15-NEXT:    [[SUB:%.*]] = sub i64 [[TMP8]], 400
12456 // CHECK15-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
12457 // CHECK15-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
12458 // CHECK15:       for.end:
12459 // CHECK15-NEXT:    [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]]
12460 // CHECK15-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]]
12461 // CHECK15-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
12462 // CHECK15-NEXT:    [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
12463 // CHECK15-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP10]] to i32
12464 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4
12465 // CHECK15-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]]
12466 // CHECK15-NEXT:    [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
12467 // CHECK15-NEXT:    call void @llvm.stackrestore(i8* [[TMP12]])
12468 // CHECK15-NEXT:    ret i32 [[ADD9]]
12469 //
12470 //
12471 // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici
12472 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
12473 // CHECK15-NEXT:  entry:
12474 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12475 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
12476 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
12477 // CHECK15-NEXT:    [[AAA:%.*]] = alloca i8, align 1
12478 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12479 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
12480 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12481 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
12482 // CHECK15-NEXT:    store i16 0, i16* [[AA]], align 2
12483 // CHECK15-NEXT:    store i8 0, i8* [[AAA]], align 1
12484 // CHECK15-NEXT:    store i32 100, i32* [[I]], align 4
12485 // CHECK15-NEXT:    br label [[FOR_COND:%.*]]
12486 // CHECK15:       for.cond:
12487 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
12488 // CHECK15-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10
12489 // CHECK15-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12490 // CHECK15:       for.body:
12491 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12492 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
12493 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12494 // CHECK15-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
12495 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
12496 // CHECK15-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12497 // CHECK15-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12498 // CHECK15-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12499 // CHECK15-NEXT:    [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1
12500 // CHECK15-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
12501 // CHECK15-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
12502 // CHECK15-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
12503 // CHECK15-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
12504 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
12505 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12506 // CHECK15-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
12507 // CHECK15-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
12508 // CHECK15-NEXT:    br label [[FOR_INC:%.*]]
12509 // CHECK15:       for.inc:
12510 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
12511 // CHECK15-NEXT:    [[ADD7:%.*]] = add i32 [[TMP5]], 10
12512 // CHECK15-NEXT:    store i32 [[ADD7]], i32* [[I]], align 4
12513 // CHECK15-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
12514 // CHECK15:       for.end:
12515 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
12516 // CHECK15-NEXT:    ret i32 [[TMP6]]
12517 //
12518 //
12519 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
12520 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
12521 // CHECK15-NEXT:  entry:
12522 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12523 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
12524 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
12525 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12526 // CHECK15-NEXT:    [[I:%.*]] = alloca i64, align 8
12527 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12528 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
12529 // CHECK15-NEXT:    store i16 0, i16* [[AA]], align 2
12530 // CHECK15-NEXT:    store i64 -10, i64* [[I]], align 8
12531 // CHECK15-NEXT:    br label [[FOR_COND:%.*]]
12532 // CHECK15:       for.cond:
12533 // CHECK15-NEXT:    [[TMP0:%.*]] = load i64, i64* [[I]], align 8
12534 // CHECK15-NEXT:    [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10
12535 // CHECK15-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12536 // CHECK15:       for.body:
12537 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12538 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
12539 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12540 // CHECK15-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
12541 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
12542 // CHECK15-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12543 // CHECK15-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12544 // CHECK15-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12545 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
12546 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12547 // CHECK15-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
12548 // CHECK15-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
12549 // CHECK15-NEXT:    br label [[FOR_INC:%.*]]
12550 // CHECK15:       for.inc:
12551 // CHECK15-NEXT:    [[TMP4:%.*]] = load i64, i64* [[I]], align 8
12552 // CHECK15-NEXT:    [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3
12553 // CHECK15-NEXT:    store i64 [[ADD4]], i64* [[I]], align 8
12554 // CHECK15-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
12555 // CHECK15:       for.end:
12556 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12557 // CHECK15-NEXT:    ret i32 [[TMP5]]
12558 //
12559 //
12560 // CHECK16-LABEL: define {{[^@]+}}@_Z7get_valv
12561 // CHECK16-SAME: () #[[ATTR0:[0-9]+]] {
12562 // CHECK16-NEXT:  entry:
12563 // CHECK16-NEXT:    ret i64 0
12564 //
12565 //
12566 // CHECK16-LABEL: define {{[^@]+}}@_Z3fooi
12567 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
12568 // CHECK16-NEXT:  entry:
12569 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12570 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
12571 // CHECK16-NEXT:    [[AA:%.*]] = alloca i16, align 2
12572 // CHECK16-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
12573 // CHECK16-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
12574 // CHECK16-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
12575 // CHECK16-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
12576 // CHECK16-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
12577 // CHECK16-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
12578 // CHECK16-NEXT:    [[I:%.*]] = alloca i32, align 4
12579 // CHECK16-NEXT:    [[K:%.*]] = alloca i64, align 8
12580 // CHECK16-NEXT:    [[I2:%.*]] = alloca i32, align 4
12581 // CHECK16-NEXT:    [[LIN:%.*]] = alloca i32, align 4
12582 // CHECK16-NEXT:    [[IT:%.*]] = alloca i64, align 8
12583 // CHECK16-NEXT:    [[IT16:%.*]] = alloca i16, align 2
12584 // CHECK16-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
12585 // CHECK16-NEXT:    [[IT30:%.*]] = alloca i8, align 1
12586 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12587 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
12588 // CHECK16-NEXT:    store i16 0, i16* [[AA]], align 2
12589 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12590 // CHECK16-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
12591 // CHECK16-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
12592 // CHECK16-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
12593 // CHECK16-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
12594 // CHECK16-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12595 // CHECK16-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
12596 // CHECK16-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
12597 // CHECK16-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
12598 // CHECK16-NEXT:    store i32 3, i32* [[I]], align 4
12599 // CHECK16-NEXT:    br label [[FOR_COND:%.*]]
12600 // CHECK16:       for.cond:
12601 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
12602 // CHECK16-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32
12603 // CHECK16-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12604 // CHECK16:       for.body:
12605 // CHECK16-NEXT:    br label [[FOR_INC:%.*]]
12606 // CHECK16:       for.inc:
12607 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
12608 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP5]], 5
12609 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
12610 // CHECK16-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
12611 // CHECK16:       for.end:
12612 // CHECK16-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
12613 // CHECK16-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
12614 // CHECK16-NEXT:    store i32 10, i32* [[I2]], align 4
12615 // CHECK16-NEXT:    br label [[FOR_COND3:%.*]]
12616 // CHECK16:       for.cond3:
12617 // CHECK16-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I2]], align 4
12618 // CHECK16-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1
12619 // CHECK16-NEXT:    br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]]
12620 // CHECK16:       for.body5:
12621 // CHECK16-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
12622 // CHECK16-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1
12623 // CHECK16-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
12624 // CHECK16-NEXT:    br label [[FOR_INC7:%.*]]
12625 // CHECK16:       for.inc7:
12626 // CHECK16-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I2]], align 4
12627 // CHECK16-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP8]], -1
12628 // CHECK16-NEXT:    store i32 [[DEC]], i32* [[I2]], align 4
12629 // CHECK16-NEXT:    br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]]
12630 // CHECK16:       for.end8:
12631 // CHECK16-NEXT:    store i32 12, i32* [[LIN]], align 4
12632 // CHECK16-NEXT:    store i64 2000, i64* [[IT]], align 8
12633 // CHECK16-NEXT:    br label [[FOR_COND9:%.*]]
12634 // CHECK16:       for.cond9:
12635 // CHECK16-NEXT:    [[TMP9:%.*]] = load i64, i64* [[IT]], align 8
12636 // CHECK16-NEXT:    [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600
12637 // CHECK16-NEXT:    br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]]
12638 // CHECK16:       for.body11:
12639 // CHECK16-NEXT:    [[TMP10:%.*]] = load i16, i16* [[AA]], align 2
12640 // CHECK16-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
12641 // CHECK16-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV]], 1
12642 // CHECK16-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
12643 // CHECK16-NEXT:    store i16 [[CONV13]], i16* [[AA]], align 2
12644 // CHECK16-NEXT:    br label [[FOR_INC14:%.*]]
12645 // CHECK16:       for.inc14:
12646 // CHECK16-NEXT:    [[TMP11:%.*]] = load i64, i64* [[IT]], align 8
12647 // CHECK16-NEXT:    [[SUB:%.*]] = sub i64 [[TMP11]], 400
12648 // CHECK16-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
12649 // CHECK16-NEXT:    br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]]
12650 // CHECK16:       for.end15:
12651 // CHECK16-NEXT:    store i16 6, i16* [[IT16]], align 2
12652 // CHECK16-NEXT:    br label [[FOR_COND17:%.*]]
12653 // CHECK16:       for.cond17:
12654 // CHECK16-NEXT:    [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2
12655 // CHECK16-NEXT:    [[CONV18:%.*]] = sext i16 [[TMP12]] to i32
12656 // CHECK16-NEXT:    [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20
12657 // CHECK16-NEXT:    br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]]
12658 // CHECK16:       for.body20:
12659 // CHECK16-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4
12660 // CHECK16-NEXT:    [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1
12661 // CHECK16-NEXT:    store i32 [[ADD21]], i32* [[A]], align 4
12662 // CHECK16-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2
12663 // CHECK16-NEXT:    [[CONV22:%.*]] = sext i16 [[TMP14]] to i32
12664 // CHECK16-NEXT:    [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1
12665 // CHECK16-NEXT:    [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16
12666 // CHECK16-NEXT:    store i16 [[CONV24]], i16* [[AA]], align 2
12667 // CHECK16-NEXT:    br label [[FOR_INC25:%.*]]
12668 // CHECK16:       for.inc25:
12669 // CHECK16-NEXT:    [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2
12670 // CHECK16-NEXT:    [[CONV26:%.*]] = sext i16 [[TMP15]] to i32
12671 // CHECK16-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4
12672 // CHECK16-NEXT:    [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16
12673 // CHECK16-NEXT:    store i16 [[CONV28]], i16* [[IT16]], align 2
12674 // CHECK16-NEXT:    br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]]
12675 // CHECK16:       for.end29:
12676 // CHECK16-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4
12677 // CHECK16-NEXT:    store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4
12678 // CHECK16-NEXT:    store i8 122, i8* [[IT30]], align 1
12679 // CHECK16-NEXT:    br label [[FOR_COND31:%.*]]
12680 // CHECK16:       for.cond31:
12681 // CHECK16-NEXT:    [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1
12682 // CHECK16-NEXT:    [[CONV32:%.*]] = zext i8 [[TMP17]] to i32
12683 // CHECK16-NEXT:    [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97
12684 // CHECK16-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]]
12685 // CHECK16:       for.body34:
12686 // CHECK16-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
12687 // CHECK16-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1
12688 // CHECK16-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
12689 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
12690 // CHECK16-NEXT:    [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4
12691 // CHECK16-NEXT:    [[CONV36:%.*]] = fpext float [[TMP19]] to double
12692 // CHECK16-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
12693 // CHECK16-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
12694 // CHECK16-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
12695 // CHECK16-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
12696 // CHECK16-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4
12697 // CHECK16-NEXT:    [[CONV40:%.*]] = fpext float [[TMP20]] to double
12698 // CHECK16-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
12699 // CHECK16-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
12700 // CHECK16-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
12701 // CHECK16-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
12702 // CHECK16-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2
12703 // CHECK16-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8
12704 // CHECK16-NEXT:    [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00
12705 // CHECK16-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
12706 // CHECK16-NEXT:    [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]]
12707 // CHECK16-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]]
12708 // CHECK16-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3
12709 // CHECK16-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8
12710 // CHECK16-NEXT:    [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00
12711 // CHECK16-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
12712 // CHECK16-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
12713 // CHECK16-NEXT:    [[TMP24:%.*]] = load i64, i64* [[X]], align 4
12714 // CHECK16-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1
12715 // CHECK16-NEXT:    store i64 [[ADD49]], i64* [[X]], align 4
12716 // CHECK16-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
12717 // CHECK16-NEXT:    [[TMP25:%.*]] = load i8, i8* [[Y]], align 4
12718 // CHECK16-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP25]] to i32
12719 // CHECK16-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
12720 // CHECK16-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
12721 // CHECK16-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 4
12722 // CHECK16-NEXT:    br label [[FOR_INC53:%.*]]
12723 // CHECK16:       for.inc53:
12724 // CHECK16-NEXT:    [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1
12725 // CHECK16-NEXT:    [[CONV54:%.*]] = zext i8 [[TMP26]] to i32
12726 // CHECK16-NEXT:    [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1
12727 // CHECK16-NEXT:    [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8
12728 // CHECK16-NEXT:    store i8 [[CONV56]], i8* [[IT30]], align 1
12729 // CHECK16-NEXT:    br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]]
12730 // CHECK16:       for.end57:
12731 // CHECK16-NEXT:    [[TMP27:%.*]] = load i32, i32* [[A]], align 4
12732 // CHECK16-NEXT:    [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
12733 // CHECK16-NEXT:    call void @llvm.stackrestore(i8* [[TMP28]])
12734 // CHECK16-NEXT:    ret i32 [[TMP27]]
12735 //
12736 //
12737 // CHECK16-LABEL: define {{[^@]+}}@_Z3bari
12738 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
12739 // CHECK16-NEXT:  entry:
12740 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12741 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
12742 // CHECK16-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
12743 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12744 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
12745 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12746 // CHECK16-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
12747 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12748 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
12749 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12750 // CHECK16-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12751 // CHECK16-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
12752 // CHECK16-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
12753 // CHECK16-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
12754 // CHECK16-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
12755 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
12756 // CHECK16-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
12757 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12758 // CHECK16-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
12759 // CHECK16-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
12760 // CHECK16-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
12761 // CHECK16-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
12762 // CHECK16-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
12763 // CHECK16-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
12764 // CHECK16-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
12765 // CHECK16-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
12766 // CHECK16-NEXT:    ret i32 [[TMP8]]
12767 //
12768 //
12769 // CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
12770 // CHECK16-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
12771 // CHECK16-NEXT:  entry:
12772 // CHECK16-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
12773 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12774 // CHECK16-NEXT:    [[B:%.*]] = alloca i32, align 4
12775 // CHECK16-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
12776 // CHECK16-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
12777 // CHECK16-NEXT:    [[IT:%.*]] = alloca i64, align 8
12778 // CHECK16-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
12779 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12780 // CHECK16-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
12781 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12782 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12783 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
12784 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
12785 // CHECK16-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
12786 // CHECK16-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
12787 // CHECK16-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
12788 // CHECK16-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
12789 // CHECK16-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
12790 // CHECK16-NEXT:    store i64 2000, i64* [[IT]], align 8
12791 // CHECK16-NEXT:    br label [[FOR_COND:%.*]]
12792 // CHECK16:       for.cond:
12793 // CHECK16-NEXT:    [[TMP4:%.*]] = load i64, i64* [[IT]], align 8
12794 // CHECK16-NEXT:    [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600
12795 // CHECK16-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12796 // CHECK16:       for.body:
12797 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
12798 // CHECK16-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
12799 // CHECK16-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
12800 // CHECK16-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
12801 // CHECK16-NEXT:    store double [[ADD2]], double* [[A]], align 4
12802 // CHECK16-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
12803 // CHECK16-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 4
12804 // CHECK16-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
12805 // CHECK16-NEXT:    store double [[INC]], double* [[A3]], align 4
12806 // CHECK16-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
12807 // CHECK16-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
12808 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
12809 // CHECK16-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
12810 // CHECK16-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
12811 // CHECK16-NEXT:    br label [[FOR_INC:%.*]]
12812 // CHECK16:       for.inc:
12813 // CHECK16-NEXT:    [[TMP8:%.*]] = load i64, i64* [[IT]], align 8
12814 // CHECK16-NEXT:    [[SUB:%.*]] = sub i64 [[TMP8]], 400
12815 // CHECK16-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
12816 // CHECK16-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
12817 // CHECK16:       for.end:
12818 // CHECK16-NEXT:    [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]]
12819 // CHECK16-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]]
12820 // CHECK16-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
12821 // CHECK16-NEXT:    [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
12822 // CHECK16-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP10]] to i32
12823 // CHECK16-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4
12824 // CHECK16-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]]
12825 // CHECK16-NEXT:    [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
12826 // CHECK16-NEXT:    call void @llvm.stackrestore(i8* [[TMP12]])
12827 // CHECK16-NEXT:    ret i32 [[ADD9]]
12828 //
12829 //
12830 // CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici
12831 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
12832 // CHECK16-NEXT:  entry:
12833 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12834 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
12835 // CHECK16-NEXT:    [[AA:%.*]] = alloca i16, align 2
12836 // CHECK16-NEXT:    [[AAA:%.*]] = alloca i8, align 1
12837 // CHECK16-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12838 // CHECK16-NEXT:    [[I:%.*]] = alloca i32, align 4
12839 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12840 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
12841 // CHECK16-NEXT:    store i16 0, i16* [[AA]], align 2
12842 // CHECK16-NEXT:    store i8 0, i8* [[AAA]], align 1
12843 // CHECK16-NEXT:    store i32 100, i32* [[I]], align 4
12844 // CHECK16-NEXT:    br label [[FOR_COND:%.*]]
12845 // CHECK16:       for.cond:
12846 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
12847 // CHECK16-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10
12848 // CHECK16-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12849 // CHECK16:       for.body:
12850 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12851 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
12852 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12853 // CHECK16-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
12854 // CHECK16-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
12855 // CHECK16-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12856 // CHECK16-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12857 // CHECK16-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12858 // CHECK16-NEXT:    [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1
12859 // CHECK16-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
12860 // CHECK16-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
12861 // CHECK16-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
12862 // CHECK16-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
12863 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
12864 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12865 // CHECK16-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
12866 // CHECK16-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
12867 // CHECK16-NEXT:    br label [[FOR_INC:%.*]]
12868 // CHECK16:       for.inc:
12869 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
12870 // CHECK16-NEXT:    [[ADD7:%.*]] = add i32 [[TMP5]], 10
12871 // CHECK16-NEXT:    store i32 [[ADD7]], i32* [[I]], align 4
12872 // CHECK16-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
12873 // CHECK16:       for.end:
12874 // CHECK16-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
12875 // CHECK16-NEXT:    ret i32 [[TMP6]]
12876 //
12877 //
12878 // CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
12879 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
12880 // CHECK16-NEXT:  entry:
12881 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12882 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
12883 // CHECK16-NEXT:    [[AA:%.*]] = alloca i16, align 2
12884 // CHECK16-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12885 // CHECK16-NEXT:    [[I:%.*]] = alloca i64, align 8
12886 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12887 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
12888 // CHECK16-NEXT:    store i16 0, i16* [[AA]], align 2
12889 // CHECK16-NEXT:    store i64 -10, i64* [[I]], align 8
12890 // CHECK16-NEXT:    br label [[FOR_COND:%.*]]
12891 // CHECK16:       for.cond:
12892 // CHECK16-NEXT:    [[TMP0:%.*]] = load i64, i64* [[I]], align 8
12893 // CHECK16-NEXT:    [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10
12894 // CHECK16-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12895 // CHECK16:       for.body:
12896 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12897 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
12898 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12899 // CHECK16-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
12900 // CHECK16-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
12901 // CHECK16-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12902 // CHECK16-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12903 // CHECK16-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12904 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
12905 // CHECK16-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12906 // CHECK16-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
12907 // CHECK16-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
12908 // CHECK16-NEXT:    br label [[FOR_INC:%.*]]
12909 // CHECK16:       for.inc:
12910 // CHECK16-NEXT:    [[TMP4:%.*]] = load i64, i64* [[I]], align 8
12911 // CHECK16-NEXT:    [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3
12912 // CHECK16-NEXT:    store i64 [[ADD4]], i64* [[I]], align 8
12913 // CHECK16-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
12914 // CHECK16:       for.end:
12915 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12916 // CHECK16-NEXT:    ret i32 [[TMP5]]
12917 //
12918 //
12919 // CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv
12920 // CHECK17-SAME: () #[[ATTR0:[0-9]+]] {
12921 // CHECK17-NEXT:  entry:
12922 // CHECK17-NEXT:    ret i64 0
12923 //
12924 //
12925 // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi
12926 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
12927 // CHECK17-NEXT:  entry:
12928 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12929 // CHECK17-NEXT:    [[A:%.*]] = alloca i32, align 4
12930 // CHECK17-NEXT:    [[AA:%.*]] = alloca i16, align 2
12931 // CHECK17-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
12932 // CHECK17-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
12933 // CHECK17-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
12934 // CHECK17-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
12935 // CHECK17-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
12936 // CHECK17-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
12937 // CHECK17-NEXT:    [[K:%.*]] = alloca i64, align 8
12938 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
12939 // CHECK17-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
12940 // CHECK17-NEXT:    [[LIN:%.*]] = alloca i32, align 4
12941 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
12942 // CHECK17-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
12943 // CHECK17-NEXT:    [[A_CASTED4:%.*]] = alloca i64, align 8
12944 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
12945 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
12946 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
12947 // CHECK17-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
12948 // CHECK17-NEXT:    [[A_CASTED6:%.*]] = alloca i64, align 8
12949 // CHECK17-NEXT:    [[AA_CASTED8:%.*]] = alloca i64, align 8
12950 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
12951 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
12952 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
12953 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
12954 // CHECK17-NEXT:    [[A_CASTED15:%.*]] = alloca i64, align 8
12955 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
12956 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8
12957 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8
12958 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8
12959 // CHECK17-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
12960 // CHECK17-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
12961 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12962 // CHECK17-NEXT:    store i32 0, i32* [[A]], align 4
12963 // CHECK17-NEXT:    store i16 0, i16* [[AA]], align 2
12964 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
12965 // CHECK17-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
12966 // CHECK17-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
12967 // CHECK17-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
12968 // CHECK17-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
12969 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
12970 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
12971 // CHECK17-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
12972 // CHECK17-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
12973 // CHECK17-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
12974 // CHECK17-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
12975 // CHECK17-NEXT:    [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
12976 // CHECK17-NEXT:    [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
12977 // CHECK17-NEXT:    br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
12978 // CHECK17:       omp_offload.failed:
12979 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]]
12980 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
12981 // CHECK17:       omp_offload.cont:
12982 // CHECK17-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
12983 // CHECK17-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
12984 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
12985 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
12986 // CHECK17-NEXT:    store i32 [[TMP9]], i32* [[CONV]], align 4
12987 // CHECK17-NEXT:    [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8
12988 // CHECK17-NEXT:    [[TMP11:%.*]] = load i64, i64* [[K]], align 8
12989 // CHECK17-NEXT:    store i64 [[TMP11]], i64* [[K_CASTED]], align 8
12990 // CHECK17-NEXT:    [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8
12991 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR3]]
12992 // CHECK17-NEXT:    store i32 12, i32* [[LIN]], align 4
12993 // CHECK17-NEXT:    [[TMP13:%.*]] = load i16, i16* [[AA]], align 2
12994 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
12995 // CHECK17-NEXT:    store i16 [[TMP13]], i16* [[CONV2]], align 2
12996 // CHECK17-NEXT:    [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8
12997 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4
12998 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
12999 // CHECK17-NEXT:    store i32 [[TMP15]], i32* [[CONV3]], align 4
13000 // CHECK17-NEXT:    [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
13001 // CHECK17-NEXT:    [[TMP17:%.*]] = load i32, i32* [[A]], align 4
13002 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32*
13003 // CHECK17-NEXT:    store i32 [[TMP17]], i32* [[CONV5]], align 4
13004 // CHECK17-NEXT:    [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8
13005 // CHECK17-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
13006 // CHECK17-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
13007 // CHECK17-NEXT:    store i64 [[TMP14]], i64* [[TMP20]], align 8
13008 // CHECK17-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
13009 // CHECK17-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
13010 // CHECK17-NEXT:    store i64 [[TMP14]], i64* [[TMP22]], align 8
13011 // CHECK17-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
13012 // CHECK17-NEXT:    store i8* null, i8** [[TMP23]], align 8
13013 // CHECK17-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
13014 // CHECK17-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
13015 // CHECK17-NEXT:    store i64 [[TMP16]], i64* [[TMP25]], align 8
13016 // CHECK17-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
13017 // CHECK17-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
13018 // CHECK17-NEXT:    store i64 [[TMP16]], i64* [[TMP27]], align 8
13019 // CHECK17-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
13020 // CHECK17-NEXT:    store i8* null, i8** [[TMP28]], align 8
13021 // CHECK17-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
13022 // CHECK17-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64*
13023 // CHECK17-NEXT:    store i64 [[TMP18]], i64* [[TMP30]], align 8
13024 // CHECK17-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
13025 // CHECK17-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
13026 // CHECK17-NEXT:    store i64 [[TMP18]], i64* [[TMP32]], align 8
13027 // CHECK17-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
13028 // CHECK17-NEXT:    store i8* null, i8** [[TMP33]], align 8
13029 // CHECK17-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
13030 // CHECK17-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
13031 // CHECK17-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
13032 // CHECK17-NEXT:    [[TMP37:%.*]] = load i16, i16* [[AA]], align 2
13033 // CHECK17-NEXT:    store i16 [[TMP37]], i16* [[TMP36]], align 4
13034 // CHECK17-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
13035 // CHECK17-NEXT:    [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4
13036 // CHECK17-NEXT:    store i32 [[TMP39]], i32* [[TMP38]], align 4
13037 // CHECK17-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
13038 // CHECK17-NEXT:    [[TMP41:%.*]] = load i32, i32* [[A]], align 4
13039 // CHECK17-NEXT:    store i32 [[TMP41]], i32* [[TMP40]], align 4
13040 // CHECK17-NEXT:    [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
13041 // CHECK17-NEXT:    [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates*
13042 // CHECK17-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0
13043 // CHECK17-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0
13044 // CHECK17-NEXT:    [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8
13045 // CHECK17-NEXT:    [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
13046 // CHECK17-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false)
13047 // CHECK17-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1
13048 // CHECK17-NEXT:    [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon*
13049 // CHECK17-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0
13050 // CHECK17-NEXT:    [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8*
13051 // CHECK17-NEXT:    [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8*
13052 // CHECK17-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false)
13053 // CHECK17-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1
13054 // CHECK17-NEXT:    [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8*
13055 // CHECK17-NEXT:    [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8*
13056 // CHECK17-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false)
13057 // CHECK17-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2
13058 // CHECK17-NEXT:    [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8*
13059 // CHECK17-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
13060 // CHECK17-NEXT:    [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3
13061 // CHECK17-NEXT:    [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
13062 // CHECK17-NEXT:    store i16 [[TMP59]], i16* [[TMP58]], align 8
13063 // CHECK17-NEXT:    [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]])
13064 // CHECK17-NEXT:    [[TMP61:%.*]] = load i32, i32* [[A]], align 4
13065 // CHECK17-NEXT:    [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32*
13066 // CHECK17-NEXT:    store i32 [[TMP61]], i32* [[CONV7]], align 4
13067 // CHECK17-NEXT:    [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8
13068 // CHECK17-NEXT:    [[TMP63:%.*]] = load i16, i16* [[AA]], align 2
13069 // CHECK17-NEXT:    [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16*
13070 // CHECK17-NEXT:    store i16 [[TMP63]], i16* [[CONV9]], align 2
13071 // CHECK17-NEXT:    [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8
13072 // CHECK17-NEXT:    [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4
13073 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10
13074 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
13075 // CHECK17:       omp_if.then:
13076 // CHECK17-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
13077 // CHECK17-NEXT:    [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64*
13078 // CHECK17-NEXT:    store i64 [[TMP62]], i64* [[TMP67]], align 8
13079 // CHECK17-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
13080 // CHECK17-NEXT:    [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64*
13081 // CHECK17-NEXT:    store i64 [[TMP62]], i64* [[TMP69]], align 8
13082 // CHECK17-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
13083 // CHECK17-NEXT:    store i8* null, i8** [[TMP70]], align 8
13084 // CHECK17-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
13085 // CHECK17-NEXT:    [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64*
13086 // CHECK17-NEXT:    store i64 [[TMP64]], i64* [[TMP72]], align 8
13087 // CHECK17-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
13088 // CHECK17-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64*
13089 // CHECK17-NEXT:    store i64 [[TMP64]], i64* [[TMP74]], align 8
13090 // CHECK17-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
13091 // CHECK17-NEXT:    store i8* null, i8** [[TMP75]], align 8
13092 // CHECK17-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
13093 // CHECK17-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
13094 // CHECK17-NEXT:    [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
13095 // CHECK17-NEXT:    [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0
13096 // CHECK17-NEXT:    br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]]
13097 // CHECK17:       omp_offload.failed13:
13098 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR3]]
13099 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT14]]
13100 // CHECK17:       omp_offload.cont14:
13101 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
13102 // CHECK17:       omp_if.else:
13103 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR3]]
13104 // CHECK17-NEXT:    br label [[OMP_IF_END]]
13105 // CHECK17:       omp_if.end:
13106 // CHECK17-NEXT:    [[TMP80:%.*]] = load i32, i32* [[A]], align 4
13107 // CHECK17-NEXT:    store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4
13108 // CHECK17-NEXT:    [[TMP81:%.*]] = load i32, i32* [[A]], align 4
13109 // CHECK17-NEXT:    [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32*
13110 // CHECK17-NEXT:    store i32 [[TMP81]], i32* [[CONV16]], align 4
13111 // CHECK17-NEXT:    [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8
13112 // CHECK17-NEXT:    [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
13113 // CHECK17-NEXT:    [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
13114 // CHECK17-NEXT:    store i32 [[TMP83]], i32* [[CONV17]], align 4
13115 // CHECK17-NEXT:    [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
13116 // CHECK17-NEXT:    [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4
13117 // CHECK17-NEXT:    [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20
13118 // CHECK17-NEXT:    br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
13119 // CHECK17:       omp_if.then19:
13120 // CHECK17-NEXT:    [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4
13121 // CHECK17-NEXT:    [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]]
13122 // CHECK17-NEXT:    [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8
13123 // CHECK17-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
13124 // CHECK17-NEXT:    [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64*
13125 // CHECK17-NEXT:    store i64 [[TMP82]], i64* [[TMP90]], align 8
13126 // CHECK17-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
13127 // CHECK17-NEXT:    [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i64*
13128 // CHECK17-NEXT:    store i64 [[TMP82]], i64* [[TMP92]], align 8
13129 // CHECK17-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
13130 // CHECK17-NEXT:    store i64 4, i64* [[TMP93]], align 8
13131 // CHECK17-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
13132 // CHECK17-NEXT:    store i8* null, i8** [[TMP94]], align 8
13133 // CHECK17-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
13134 // CHECK17-NEXT:    [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]**
13135 // CHECK17-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8
13136 // CHECK17-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
13137 // CHECK17-NEXT:    [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]**
13138 // CHECK17-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8
13139 // CHECK17-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
13140 // CHECK17-NEXT:    store i64 40, i64* [[TMP99]], align 8
13141 // CHECK17-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
13142 // CHECK17-NEXT:    store i8* null, i8** [[TMP100]], align 8
13143 // CHECK17-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
13144 // CHECK17-NEXT:    [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i64*
13145 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[TMP102]], align 8
13146 // CHECK17-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
13147 // CHECK17-NEXT:    [[TMP104:%.*]] = bitcast i8** [[TMP103]] to i64*
13148 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[TMP104]], align 8
13149 // CHECK17-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
13150 // CHECK17-NEXT:    store i64 8, i64* [[TMP105]], align 8
13151 // CHECK17-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
13152 // CHECK17-NEXT:    store i8* null, i8** [[TMP106]], align 8
13153 // CHECK17-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
13154 // CHECK17-NEXT:    [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float**
13155 // CHECK17-NEXT:    store float* [[VLA]], float** [[TMP108]], align 8
13156 // CHECK17-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
13157 // CHECK17-NEXT:    [[TMP110:%.*]] = bitcast i8** [[TMP109]] to float**
13158 // CHECK17-NEXT:    store float* [[VLA]], float** [[TMP110]], align 8
13159 // CHECK17-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
13160 // CHECK17-NEXT:    store i64 [[TMP86]], i64* [[TMP111]], align 8
13161 // CHECK17-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3
13162 // CHECK17-NEXT:    store i8* null, i8** [[TMP112]], align 8
13163 // CHECK17-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
13164 // CHECK17-NEXT:    [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]**
13165 // CHECK17-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8
13166 // CHECK17-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
13167 // CHECK17-NEXT:    [[TMP116:%.*]] = bitcast i8** [[TMP115]] to [5 x [10 x double]]**
13168 // CHECK17-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP116]], align 8
13169 // CHECK17-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
13170 // CHECK17-NEXT:    store i64 400, i64* [[TMP117]], align 8
13171 // CHECK17-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4
13172 // CHECK17-NEXT:    store i8* null, i8** [[TMP118]], align 8
13173 // CHECK17-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
13174 // CHECK17-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i64*
13175 // CHECK17-NEXT:    store i64 5, i64* [[TMP120]], align 8
13176 // CHECK17-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
13177 // CHECK17-NEXT:    [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64*
13178 // CHECK17-NEXT:    store i64 5, i64* [[TMP122]], align 8
13179 // CHECK17-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
13180 // CHECK17-NEXT:    store i64 8, i64* [[TMP123]], align 8
13181 // CHECK17-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5
13182 // CHECK17-NEXT:    store i8* null, i8** [[TMP124]], align 8
13183 // CHECK17-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
13184 // CHECK17-NEXT:    [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64*
13185 // CHECK17-NEXT:    store i64 [[TMP5]], i64* [[TMP126]], align 8
13186 // CHECK17-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
13187 // CHECK17-NEXT:    [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64*
13188 // CHECK17-NEXT:    store i64 [[TMP5]], i64* [[TMP128]], align 8
13189 // CHECK17-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
13190 // CHECK17-NEXT:    store i64 8, i64* [[TMP129]], align 8
13191 // CHECK17-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6
13192 // CHECK17-NEXT:    store i8* null, i8** [[TMP130]], align 8
13193 // CHECK17-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
13194 // CHECK17-NEXT:    [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double**
13195 // CHECK17-NEXT:    store double* [[VLA1]], double** [[TMP132]], align 8
13196 // CHECK17-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
13197 // CHECK17-NEXT:    [[TMP134:%.*]] = bitcast i8** [[TMP133]] to double**
13198 // CHECK17-NEXT:    store double* [[VLA1]], double** [[TMP134]], align 8
13199 // CHECK17-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
13200 // CHECK17-NEXT:    store i64 [[TMP88]], i64* [[TMP135]], align 8
13201 // CHECK17-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7
13202 // CHECK17-NEXT:    store i8* null, i8** [[TMP136]], align 8
13203 // CHECK17-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
13204 // CHECK17-NEXT:    [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT**
13205 // CHECK17-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 8
13206 // CHECK17-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
13207 // CHECK17-NEXT:    [[TMP140:%.*]] = bitcast i8** [[TMP139]] to %struct.TT**
13208 // CHECK17-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP140]], align 8
13209 // CHECK17-NEXT:    [[TMP141:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
13210 // CHECK17-NEXT:    store i64 16, i64* [[TMP141]], align 8
13211 // CHECK17-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8
13212 // CHECK17-NEXT:    store i8* null, i8** [[TMP142]], align 8
13213 // CHECK17-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9
13214 // CHECK17-NEXT:    [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i64*
13215 // CHECK17-NEXT:    store i64 [[TMP84]], i64* [[TMP144]], align 8
13216 // CHECK17-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9
13217 // CHECK17-NEXT:    [[TMP146:%.*]] = bitcast i8** [[TMP145]] to i64*
13218 // CHECK17-NEXT:    store i64 [[TMP84]], i64* [[TMP146]], align 8
13219 // CHECK17-NEXT:    [[TMP147:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
13220 // CHECK17-NEXT:    store i64 4, i64* [[TMP147]], align 8
13221 // CHECK17-NEXT:    [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9
13222 // CHECK17-NEXT:    store i8* null, i8** [[TMP148]], align 8
13223 // CHECK17-NEXT:    [[TMP149:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
13224 // CHECK17-NEXT:    [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
13225 // CHECK17-NEXT:    [[TMP151:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
13226 // CHECK17-NEXT:    [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
13227 // CHECK17-NEXT:    [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0
13228 // CHECK17-NEXT:    br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
13229 // CHECK17:       omp_offload.failed23:
13230 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR3]]
13231 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT24]]
13232 // CHECK17:       omp_offload.cont24:
13233 // CHECK17-NEXT:    br label [[OMP_IF_END26:%.*]]
13234 // CHECK17:       omp_if.else25:
13235 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR3]]
13236 // CHECK17-NEXT:    br label [[OMP_IF_END26]]
13237 // CHECK17:       omp_if.end26:
13238 // CHECK17-NEXT:    [[TMP154:%.*]] = load i32, i32* [[A]], align 4
13239 // CHECK17-NEXT:    [[TMP155:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
13240 // CHECK17-NEXT:    call void @llvm.stackrestore(i8* [[TMP155]])
13241 // CHECK17-NEXT:    ret i32 [[TMP154]]
13242 //
13243 //
13244 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
13245 // CHECK17-SAME: () #[[ATTR2:[0-9]+]] {
13246 // CHECK17-NEXT:  entry:
13247 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
13248 // CHECK17-NEXT:    ret void
13249 //
13250 //
13251 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
13252 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
13253 // CHECK17-NEXT:  entry:
13254 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13255 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13256 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13257 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13258 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13259 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13260 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13261 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13262 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
13263 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13264 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13265 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
13266 // CHECK17-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
13267 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13268 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13269 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
13270 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
13271 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
13272 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13273 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
13274 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13275 // CHECK17:       cond.true:
13276 // CHECK17-NEXT:    br label [[COND_END:%.*]]
13277 // CHECK17:       cond.false:
13278 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13279 // CHECK17-NEXT:    br label [[COND_END]]
13280 // CHECK17:       cond.end:
13281 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
13282 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13283 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13284 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
13285 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13286 // CHECK17:       omp.inner.for.cond:
13287 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13288 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13289 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
13290 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13291 // CHECK17:       omp.inner.for.body:
13292 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13293 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
13294 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
13295 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
13296 // CHECK17-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
13297 // CHECK17-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
13298 // CHECK17-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
13299 // CHECK17:       .cancel.exit:
13300 // CHECK17-NEXT:    br label [[CANCEL_EXIT:%.*]]
13301 // CHECK17:       .cancel.continue:
13302 // CHECK17-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
13303 // CHECK17-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
13304 // CHECK17-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
13305 // CHECK17:       .cancel.exit2:
13306 // CHECK17-NEXT:    br label [[CANCEL_EXIT]]
13307 // CHECK17:       .cancel.continue3:
13308 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13309 // CHECK17:       omp.body.continue:
13310 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13311 // CHECK17:       omp.inner.for.inc:
13312 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13313 // CHECK17-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
13314 // CHECK17-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
13315 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
13316 // CHECK17:       omp.inner.for.end:
13317 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13318 // CHECK17:       omp.loop.exit:
13319 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
13320 // CHECK17-NEXT:    br label [[CANCEL_CONT:%.*]]
13321 // CHECK17:       cancel.cont:
13322 // CHECK17-NEXT:    ret void
13323 // CHECK17:       cancel.exit:
13324 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
13325 // CHECK17-NEXT:    br label [[CANCEL_CONT]]
13326 //
13327 //
13328 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
13329 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR2]] {
13330 // CHECK17-NEXT:  entry:
13331 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13332 // CHECK17-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
13333 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
13334 // CHECK17-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
13335 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13336 // CHECK17-NEXT:    store i64 [[K]], i64* [[K_ADDR]], align 8
13337 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13338 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
13339 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
13340 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
13341 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
13342 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
13343 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[K_CASTED]], align 8
13344 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
13345 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
13346 // CHECK17-NEXT:    ret void
13347 //
13348 //
13349 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1
13350 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR2]] {
13351 // CHECK17-NEXT:  entry:
13352 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13353 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13354 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13355 // CHECK17-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
13356 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13357 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13358 // CHECK17-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
13359 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13360 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13361 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13362 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13363 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
13364 // CHECK17-NEXT:    [[K1:%.*]] = alloca i64, align 8
13365 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13366 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13367 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13368 // CHECK17-NEXT:    store i64 [[K]], i64* [[K_ADDR]], align 8
13369 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13370 // CHECK17-NEXT:    [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8
13371 // CHECK17-NEXT:    store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8
13372 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
13373 // CHECK17-NEXT:    store i32 8, i32* [[DOTOMP_UB]], align 4
13374 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13375 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13376 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
13377 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
13378 // CHECK17-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]])
13379 // CHECK17-NEXT:    call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
13380 // CHECK17-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
13381 // CHECK17:       omp.dispatch.cond:
13382 // CHECK17-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
13383 // CHECK17-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
13384 // CHECK17-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
13385 // CHECK17:       omp.dispatch.body:
13386 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13387 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
13388 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13389 // CHECK17:       omp.inner.for.cond:
13390 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
13391 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
13392 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
13393 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13394 // CHECK17:       omp.inner.for.body:
13395 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
13396 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
13397 // CHECK17-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
13398 // CHECK17-NEXT:    store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !11
13399 // CHECK17-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !11
13400 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
13401 // CHECK17-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
13402 // CHECK17-NEXT:    [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
13403 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
13404 // CHECK17-NEXT:    store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !11
13405 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11
13406 // CHECK17-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
13407 // CHECK17-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !11
13408 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13409 // CHECK17:       omp.body.continue:
13410 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13411 // CHECK17:       omp.inner.for.inc:
13412 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
13413 // CHECK17-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
13414 // CHECK17-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
13415 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
13416 // CHECK17:       omp.inner.for.end:
13417 // CHECK17-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
13418 // CHECK17:       omp.dispatch.inc:
13419 // CHECK17-NEXT:    br label [[OMP_DISPATCH_COND]]
13420 // CHECK17:       omp.dispatch.end:
13421 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13422 // CHECK17-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
13423 // CHECK17-NEXT:    br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
13424 // CHECK17:       .omp.linear.pu:
13425 // CHECK17-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
13426 // CHECK17-NEXT:    [[ADD6:%.*]] = add nsw i64 [[TMP14]], 27
13427 // CHECK17-NEXT:    store i64 [[ADD6]], i64* [[K_ADDR]], align 8
13428 // CHECK17-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
13429 // CHECK17:       .omp.linear.pu.done:
13430 // CHECK17-NEXT:    ret void
13431 //
13432 //
13433 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
13434 // CHECK17-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
13435 // CHECK17-NEXT:  entry:
13436 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13437 // CHECK17-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
13438 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13439 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
13440 // CHECK17-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
13441 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
13442 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13443 // CHECK17-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
13444 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13445 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13446 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
13447 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13448 // CHECK17-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
13449 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13450 // CHECK17-NEXT:    store i16 [[TMP0]], i16* [[CONV3]], align 2
13451 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13452 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
13453 // CHECK17-NEXT:    [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
13454 // CHECK17-NEXT:    store i32 [[TMP2]], i32* [[CONV4]], align 4
13455 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
13456 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
13457 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
13458 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[CONV5]], align 4
13459 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
13460 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
13461 // CHECK17-NEXT:    ret void
13462 //
13463 //
13464 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
13465 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
13466 // CHECK17-NEXT:  entry:
13467 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13468 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13469 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13470 // CHECK17-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
13471 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13472 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
13473 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i64, align 8
13474 // CHECK17-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
13475 // CHECK17-NEXT:    [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
13476 // CHECK17-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
13477 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
13478 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
13479 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
13480 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13481 // CHECK17-NEXT:    [[IT:%.*]] = alloca i64, align 8
13482 // CHECK17-NEXT:    [[LIN4:%.*]] = alloca i32, align 4
13483 // CHECK17-NEXT:    [[A5:%.*]] = alloca i32, align 4
13484 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13485 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13486 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13487 // CHECK17-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
13488 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13489 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13490 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
13491 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13492 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
13493 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
13494 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
13495 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
13496 // CHECK17-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
13497 // CHECK17-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
13498 // CHECK17-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
13499 // CHECK17-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
13500 // CHECK17-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
13501 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13502 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
13503 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
13504 // CHECK17-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
13505 // CHECK17-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
13506 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
13507 // CHECK17-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
13508 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13509 // CHECK17:       cond.true:
13510 // CHECK17-NEXT:    br label [[COND_END:%.*]]
13511 // CHECK17:       cond.false:
13512 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
13513 // CHECK17-NEXT:    br label [[COND_END]]
13514 // CHECK17:       cond.end:
13515 // CHECK17-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
13516 // CHECK17-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
13517 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
13518 // CHECK17-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
13519 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13520 // CHECK17:       omp.inner.for.cond:
13521 // CHECK17-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
13522 // CHECK17-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
13523 // CHECK17-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
13524 // CHECK17-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13525 // CHECK17:       omp.inner.for.body:
13526 // CHECK17-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
13527 // CHECK17-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
13528 // CHECK17-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
13529 // CHECK17-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
13530 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
13531 // CHECK17-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
13532 // CHECK17-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
13533 // CHECK17-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
13534 // CHECK17-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
13535 // CHECK17-NEXT:    [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
13536 // CHECK17-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
13537 // CHECK17-NEXT:    store i32 [[CONV9]], i32* [[LIN4]], align 4
13538 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
13539 // CHECK17-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
13540 // CHECK17-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
13541 // CHECK17-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
13542 // CHECK17-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
13543 // CHECK17-NEXT:    [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
13544 // CHECK17-NEXT:    [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
13545 // CHECK17-NEXT:    store i32 [[CONV13]], i32* [[A5]], align 4
13546 // CHECK17-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8
13547 // CHECK17-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
13548 // CHECK17-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
13549 // CHECK17-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
13550 // CHECK17-NEXT:    store i16 [[CONV16]], i16* [[CONV]], align 8
13551 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13552 // CHECK17:       omp.body.continue:
13553 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13554 // CHECK17:       omp.inner.for.inc:
13555 // CHECK17-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
13556 // CHECK17-NEXT:    [[ADD17:%.*]] = add i64 [[TMP17]], 1
13557 // CHECK17-NEXT:    store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
13558 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
13559 // CHECK17:       omp.inner.for.end:
13560 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13561 // CHECK17:       omp.loop.exit:
13562 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
13563 // CHECK17-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13564 // CHECK17-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
13565 // CHECK17-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
13566 // CHECK17:       .omp.linear.pu:
13567 // CHECK17-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
13568 // CHECK17-NEXT:    [[CONV18:%.*]] = sext i32 [[TMP20]] to i64
13569 // CHECK17-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
13570 // CHECK17-NEXT:    [[MUL19:%.*]] = mul i64 4, [[TMP21]]
13571 // CHECK17-NEXT:    [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
13572 // CHECK17-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
13573 // CHECK17-NEXT:    store i32 [[CONV21]], i32* [[CONV1]], align 8
13574 // CHECK17-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
13575 // CHECK17-NEXT:    [[CONV22:%.*]] = sext i32 [[TMP22]] to i64
13576 // CHECK17-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
13577 // CHECK17-NEXT:    [[MUL23:%.*]] = mul i64 4, [[TMP23]]
13578 // CHECK17-NEXT:    [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
13579 // CHECK17-NEXT:    [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
13580 // CHECK17-NEXT:    store i32 [[CONV25]], i32* [[CONV2]], align 8
13581 // CHECK17-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
13582 // CHECK17:       .omp.linear.pu.done:
13583 // CHECK17-NEXT:    ret void
13584 //
13585 //
13586 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map.
13587 // CHECK17-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
13588 // CHECK17-NEXT:  entry:
13589 // CHECK17-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
13590 // CHECK17-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 8
13591 // CHECK17-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
13592 // CHECK17-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
13593 // CHECK17-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
13594 // CHECK17-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
13595 // CHECK17-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
13596 // CHECK17-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
13597 // CHECK17-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
13598 // CHECK17-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
13599 // CHECK17-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
13600 // CHECK17-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
13601 // CHECK17-NEXT:    [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
13602 // CHECK17-NEXT:    store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
13603 // CHECK17-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
13604 // CHECK17-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
13605 // CHECK17-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
13606 // CHECK17-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
13607 // CHECK17-NEXT:    [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
13608 // CHECK17-NEXT:    store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
13609 // CHECK17-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
13610 // CHECK17-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
13611 // CHECK17-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 8
13612 // CHECK17-NEXT:    ret void
13613 //
13614 //
13615 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry.
13616 // CHECK17-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
13617 // CHECK17-NEXT:  entry:
13618 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
13619 // CHECK17-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
13620 // CHECK17-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
13621 // CHECK17-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
13622 // CHECK17-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
13623 // CHECK17-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
13624 // CHECK17-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
13625 // CHECK17-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
13626 // CHECK17-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
13627 // CHECK17-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
13628 // CHECK17-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
13629 // CHECK17-NEXT:    [[LIN_CASTED_I:%.*]] = alloca i64, align 8
13630 // CHECK17-NEXT:    [[A_CASTED_I:%.*]] = alloca i64, align 8
13631 // CHECK17-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
13632 // CHECK17-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
13633 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
13634 // CHECK17-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
13635 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
13636 // CHECK17-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
13637 // CHECK17-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
13638 // CHECK17-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
13639 // CHECK17-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
13640 // CHECK17-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
13641 // CHECK17-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
13642 // CHECK17-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
13643 // CHECK17-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
13644 // CHECK17-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
13645 // CHECK17-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])
13646 // CHECK17-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
13647 // CHECK17-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
13648 // CHECK17-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
13649 // CHECK17-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23
13650 // CHECK17-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23
13651 // CHECK17-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23
13652 // CHECK17-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23
13653 // CHECK17-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23
13654 // CHECK17-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23
13655 // CHECK17-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23
13656 // CHECK17-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23
13657 // CHECK17-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23
13658 // CHECK17-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
13659 // CHECK17-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
13660 // CHECK17-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23
13661 // CHECK17-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23
13662 // CHECK17-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23
13663 // CHECK17-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23
13664 // CHECK17-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
13665 // CHECK17-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
13666 // CHECK17-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
13667 // CHECK17-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
13668 // CHECK17-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
13669 // CHECK17-NEXT:    [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) #[[ATTR3]]
13670 // CHECK17-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
13671 // CHECK17-NEXT:    br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
13672 // CHECK17:       omp_offload.failed.i:
13673 // CHECK17-NEXT:    [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2
13674 // CHECK17-NEXT:    [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
13675 // CHECK17-NEXT:    store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !23
13676 // CHECK17-NEXT:    [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !23
13677 // CHECK17-NEXT:    [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4
13678 // CHECK17-NEXT:    [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32*
13679 // CHECK17-NEXT:    store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !23
13680 // CHECK17-NEXT:    [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !23
13681 // CHECK17-NEXT:    [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4
13682 // CHECK17-NEXT:    [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32*
13683 // CHECK17-NEXT:    store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !23
13684 // CHECK17-NEXT:    [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !23
13685 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR3]]
13686 // CHECK17-NEXT:    br label [[DOTOMP_OUTLINED__3_EXIT]]
13687 // CHECK17:       .omp_outlined..3.exit:
13688 // CHECK17-NEXT:    ret i32 0
13689 //
13690 //
13691 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
13692 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
13693 // CHECK17-NEXT:  entry:
13694 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13695 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13696 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
13697 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
13698 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13699 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13700 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13701 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13702 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
13703 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
13704 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
13705 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
13706 // CHECK17-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
13707 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13708 // CHECK17-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
13709 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13710 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
13711 // CHECK17-NEXT:    ret void
13712 //
13713 //
13714 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
13715 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
13716 // CHECK17-NEXT:  entry:
13717 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13718 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13719 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13720 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13721 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13722 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i16, align 2
13723 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13724 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13725 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13726 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13727 // CHECK17-NEXT:    [[IT:%.*]] = alloca i16, align 2
13728 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13729 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13730 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13731 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13732 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13733 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13734 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
13735 // CHECK17-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
13736 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13737 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13738 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
13739 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
13740 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
13741 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13742 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
13743 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13744 // CHECK17:       cond.true:
13745 // CHECK17-NEXT:    br label [[COND_END:%.*]]
13746 // CHECK17:       cond.false:
13747 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13748 // CHECK17-NEXT:    br label [[COND_END]]
13749 // CHECK17:       cond.end:
13750 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
13751 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13752 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13753 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
13754 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13755 // CHECK17:       omp.inner.for.cond:
13756 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13757 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13758 // CHECK17-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
13759 // CHECK17-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13760 // CHECK17:       omp.inner.for.body:
13761 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13762 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
13763 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
13764 // CHECK17-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
13765 // CHECK17-NEXT:    store i16 [[CONV3]], i16* [[IT]], align 2
13766 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
13767 // CHECK17-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
13768 // CHECK17-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8
13769 // CHECK17-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
13770 // CHECK17-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
13771 // CHECK17-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
13772 // CHECK17-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
13773 // CHECK17-NEXT:    store i16 [[CONV7]], i16* [[CONV1]], align 8
13774 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13775 // CHECK17:       omp.body.continue:
13776 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13777 // CHECK17:       omp.inner.for.inc:
13778 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13779 // CHECK17-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
13780 // CHECK17-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
13781 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
13782 // CHECK17:       omp.inner.for.end:
13783 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13784 // CHECK17:       omp.loop.exit:
13785 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
13786 // CHECK17-NEXT:    ret void
13787 //
13788 //
13789 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
13790 // CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
13791 // CHECK17-NEXT:  entry:
13792 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13793 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
13794 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
13795 // CHECK17-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
13796 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
13797 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
13798 // CHECK17-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
13799 // CHECK17-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
13800 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
13801 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
13802 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
13803 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
13804 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13805 // CHECK17-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
13806 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
13807 // CHECK17-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
13808 // CHECK17-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
13809 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
13810 // CHECK17-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
13811 // CHECK17-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
13812 // CHECK17-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
13813 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
13814 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13815 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
13816 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
13817 // CHECK17-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
13818 // CHECK17-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
13819 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
13820 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
13821 // CHECK17-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
13822 // CHECK17-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
13823 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
13824 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
13825 // CHECK17-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
13826 // CHECK17-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
13827 // CHECK17-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
13828 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
13829 // CHECK17-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
13830 // CHECK17-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
13831 // CHECK17-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
13832 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
13833 // CHECK17-NEXT:    ret void
13834 //
13835 //
13836 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7
13837 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
13838 // CHECK17-NEXT:  entry:
13839 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13840 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13841 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13842 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
13843 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
13844 // CHECK17-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
13845 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
13846 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
13847 // CHECK17-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
13848 // CHECK17-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
13849 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
13850 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
13851 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13852 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i8, align 1
13853 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13854 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13855 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13856 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13857 // CHECK17-NEXT:    [[IT:%.*]] = alloca i8, align 1
13858 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13859 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13860 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13861 // CHECK17-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
13862 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
13863 // CHECK17-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
13864 // CHECK17-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
13865 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
13866 // CHECK17-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
13867 // CHECK17-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
13868 // CHECK17-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
13869 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
13870 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13871 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
13872 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
13873 // CHECK17-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
13874 // CHECK17-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
13875 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
13876 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
13877 // CHECK17-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
13878 // CHECK17-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
13879 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
13880 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
13881 // CHECK17-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
13882 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13883 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13884 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
13885 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
13886 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
13887 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
13888 // CHECK17-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
13889 // CHECK17:       omp.dispatch.cond:
13890 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13891 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
13892 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13893 // CHECK17:       cond.true:
13894 // CHECK17-NEXT:    br label [[COND_END:%.*]]
13895 // CHECK17:       cond.false:
13896 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13897 // CHECK17-NEXT:    br label [[COND_END]]
13898 // CHECK17:       cond.end:
13899 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
13900 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13901 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13902 // CHECK17-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
13903 // CHECK17-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13904 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13905 // CHECK17-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
13906 // CHECK17-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
13907 // CHECK17:       omp.dispatch.body:
13908 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13909 // CHECK17:       omp.inner.for.cond:
13910 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13911 // CHECK17-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13912 // CHECK17-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
13913 // CHECK17-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13914 // CHECK17:       omp.inner.for.body:
13915 // CHECK17-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13916 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
13917 // CHECK17-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
13918 // CHECK17-NEXT:    [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
13919 // CHECK17-NEXT:    store i8 [[CONV8]], i8* [[IT]], align 1
13920 // CHECK17-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
13921 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
13922 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
13923 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
13924 // CHECK17-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
13925 // CHECK17-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
13926 // CHECK17-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
13927 // CHECK17-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
13928 // CHECK17-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
13929 // CHECK17-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
13930 // CHECK17-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
13931 // CHECK17-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
13932 // CHECK17-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
13933 // CHECK17-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
13934 // CHECK17-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
13935 // CHECK17-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
13936 // CHECK17-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
13937 // CHECK17-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
13938 // CHECK17-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
13939 // CHECK17-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
13940 // CHECK17-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
13941 // CHECK17-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
13942 // CHECK17-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
13943 // CHECK17-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
13944 // CHECK17-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
13945 // CHECK17-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
13946 // CHECK17-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
13947 // CHECK17-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8
13948 // CHECK17-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
13949 // CHECK17-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8
13950 // CHECK17-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
13951 // CHECK17-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
13952 // CHECK17-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
13953 // CHECK17-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
13954 // CHECK17-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
13955 // CHECK17-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8
13956 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13957 // CHECK17:       omp.body.continue:
13958 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13959 // CHECK17:       omp.inner.for.inc:
13960 // CHECK17-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13961 // CHECK17-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
13962 // CHECK17-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
13963 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
13964 // CHECK17:       omp.inner.for.end:
13965 // CHECK17-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
13966 // CHECK17:       omp.dispatch.inc:
13967 // CHECK17-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13968 // CHECK17-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
13969 // CHECK17-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
13970 // CHECK17-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
13971 // CHECK17-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13972 // CHECK17-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
13973 // CHECK17-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
13974 // CHECK17-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
13975 // CHECK17-NEXT:    br label [[OMP_DISPATCH_COND]]
13976 // CHECK17:       omp.dispatch.end:
13977 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
13978 // CHECK17-NEXT:    ret void
13979 //
13980 //
13981 // CHECK17-LABEL: define {{[^@]+}}@_Z3bari
13982 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
13983 // CHECK17-NEXT:  entry:
13984 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13985 // CHECK17-NEXT:    [[A:%.*]] = alloca i32, align 4
13986 // CHECK17-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
13987 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13988 // CHECK17-NEXT:    store i32 0, i32* [[A]], align 4
13989 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
13990 // CHECK17-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
13991 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
13992 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
13993 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
13994 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
13995 // CHECK17-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
13996 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
13997 // CHECK17-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
13998 // CHECK17-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
13999 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
14000 // CHECK17-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
14001 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
14002 // CHECK17-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
14003 // CHECK17-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
14004 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
14005 // CHECK17-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
14006 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
14007 // CHECK17-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
14008 // CHECK17-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
14009 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
14010 // CHECK17-NEXT:    ret i32 [[TMP8]]
14011 //
14012 //
14013 // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
14014 // CHECK17-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
14015 // CHECK17-NEXT:  entry:
14016 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
14017 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14018 // CHECK17-NEXT:    [[B:%.*]] = alloca i32, align 4
14019 // CHECK17-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
14020 // CHECK17-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
14021 // CHECK17-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
14022 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
14023 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
14024 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
14025 // CHECK17-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
14026 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
14027 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14028 // CHECK17-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
14029 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14030 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
14031 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
14032 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
14033 // CHECK17-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
14034 // CHECK17-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
14035 // CHECK17-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
14036 // CHECK17-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
14037 // CHECK17-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
14038 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
14039 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
14040 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
14041 // CHECK17-NEXT:    store i32 [[TMP5]], i32* [[CONV]], align 4
14042 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
14043 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
14044 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
14045 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
14046 // CHECK17:       omp_if.then:
14047 // CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
14048 // CHECK17-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
14049 // CHECK17-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
14050 // CHECK17-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
14051 // CHECK17-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
14052 // CHECK17-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
14053 // CHECK17-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
14054 // CHECK17-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
14055 // CHECK17-NEXT:    store double* [[A]], double** [[TMP13]], align 8
14056 // CHECK17-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
14057 // CHECK17-NEXT:    store i64 8, i64* [[TMP14]], align 8
14058 // CHECK17-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
14059 // CHECK17-NEXT:    store i8* null, i8** [[TMP15]], align 8
14060 // CHECK17-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
14061 // CHECK17-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
14062 // CHECK17-NEXT:    store i64 [[TMP6]], i64* [[TMP17]], align 8
14063 // CHECK17-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
14064 // CHECK17-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
14065 // CHECK17-NEXT:    store i64 [[TMP6]], i64* [[TMP19]], align 8
14066 // CHECK17-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
14067 // CHECK17-NEXT:    store i64 4, i64* [[TMP20]], align 8
14068 // CHECK17-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
14069 // CHECK17-NEXT:    store i8* null, i8** [[TMP21]], align 8
14070 // CHECK17-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
14071 // CHECK17-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
14072 // CHECK17-NEXT:    store i64 2, i64* [[TMP23]], align 8
14073 // CHECK17-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
14074 // CHECK17-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
14075 // CHECK17-NEXT:    store i64 2, i64* [[TMP25]], align 8
14076 // CHECK17-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
14077 // CHECK17-NEXT:    store i64 8, i64* [[TMP26]], align 8
14078 // CHECK17-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
14079 // CHECK17-NEXT:    store i8* null, i8** [[TMP27]], align 8
14080 // CHECK17-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
14081 // CHECK17-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
14082 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[TMP29]], align 8
14083 // CHECK17-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
14084 // CHECK17-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
14085 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[TMP31]], align 8
14086 // CHECK17-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
14087 // CHECK17-NEXT:    store i64 8, i64* [[TMP32]], align 8
14088 // CHECK17-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
14089 // CHECK17-NEXT:    store i8* null, i8** [[TMP33]], align 8
14090 // CHECK17-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
14091 // CHECK17-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
14092 // CHECK17-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 8
14093 // CHECK17-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
14094 // CHECK17-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
14095 // CHECK17-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 8
14096 // CHECK17-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
14097 // CHECK17-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 8
14098 // CHECK17-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
14099 // CHECK17-NEXT:    store i8* null, i8** [[TMP39]], align 8
14100 // CHECK17-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
14101 // CHECK17-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
14102 // CHECK17-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
14103 // CHECK17-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
14104 // CHECK17-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
14105 // CHECK17-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
14106 // CHECK17:       omp_offload.failed:
14107 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
14108 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
14109 // CHECK17:       omp_offload.cont:
14110 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
14111 // CHECK17:       omp_if.else:
14112 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
14113 // CHECK17-NEXT:    br label [[OMP_IF_END]]
14114 // CHECK17:       omp_if.end:
14115 // CHECK17-NEXT:    [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
14116 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
14117 // CHECK17-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
14118 // CHECK17-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
14119 // CHECK17-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
14120 // CHECK17-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
14121 // CHECK17-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
14122 // CHECK17-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
14123 // CHECK17-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
14124 // CHECK17-NEXT:    ret i32 [[ADD4]]
14125 //
14126 //
14127 // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici
14128 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
14129 // CHECK17-NEXT:  entry:
14130 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14131 // CHECK17-NEXT:    [[A:%.*]] = alloca i32, align 4
14132 // CHECK17-NEXT:    [[AA:%.*]] = alloca i16, align 2
14133 // CHECK17-NEXT:    [[AAA:%.*]] = alloca i8, align 1
14134 // CHECK17-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
14135 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
14136 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
14137 // CHECK17-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
14138 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
14139 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
14140 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
14141 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14142 // CHECK17-NEXT:    store i32 0, i32* [[A]], align 4
14143 // CHECK17-NEXT:    store i16 0, i16* [[AA]], align 2
14144 // CHECK17-NEXT:    store i8 0, i8* [[AAA]], align 1
14145 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
14146 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
14147 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
14148 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
14149 // CHECK17-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
14150 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
14151 // CHECK17-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
14152 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
14153 // CHECK17-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
14154 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
14155 // CHECK17-NEXT:    store i8 [[TMP4]], i8* [[CONV2]], align 1
14156 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
14157 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
14158 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
14159 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
14160 // CHECK17:       omp_if.then:
14161 // CHECK17-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
14162 // CHECK17-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
14163 // CHECK17-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
14164 // CHECK17-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
14165 // CHECK17-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
14166 // CHECK17-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
14167 // CHECK17-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
14168 // CHECK17-NEXT:    store i8* null, i8** [[TMP11]], align 8
14169 // CHECK17-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
14170 // CHECK17-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
14171 // CHECK17-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
14172 // CHECK17-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
14173 // CHECK17-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
14174 // CHECK17-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
14175 // CHECK17-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
14176 // CHECK17-NEXT:    store i8* null, i8** [[TMP16]], align 8
14177 // CHECK17-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
14178 // CHECK17-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
14179 // CHECK17-NEXT:    store i64 [[TMP5]], i64* [[TMP18]], align 8
14180 // CHECK17-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
14181 // CHECK17-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
14182 // CHECK17-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
14183 // CHECK17-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
14184 // CHECK17-NEXT:    store i8* null, i8** [[TMP21]], align 8
14185 // CHECK17-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
14186 // CHECK17-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
14187 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
14188 // CHECK17-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
14189 // CHECK17-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
14190 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
14191 // CHECK17-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
14192 // CHECK17-NEXT:    store i8* null, i8** [[TMP26]], align 8
14193 // CHECK17-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
14194 // CHECK17-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
14195 // CHECK17-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
14196 // CHECK17-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
14197 // CHECK17-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
14198 // CHECK17:       omp_offload.failed:
14199 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
14200 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
14201 // CHECK17:       omp_offload.cont:
14202 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
14203 // CHECK17:       omp_if.else:
14204 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
14205 // CHECK17-NEXT:    br label [[OMP_IF_END]]
14206 // CHECK17:       omp_if.end:
14207 // CHECK17-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
14208 // CHECK17-NEXT:    ret i32 [[TMP31]]
14209 //
14210 //
14211 // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
14212 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
14213 // CHECK17-NEXT:  entry:
14214 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14215 // CHECK17-NEXT:    [[A:%.*]] = alloca i32, align 4
14216 // CHECK17-NEXT:    [[AA:%.*]] = alloca i16, align 2
14217 // CHECK17-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
14218 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
14219 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
14220 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
14221 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
14222 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
14223 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14224 // CHECK17-NEXT:    store i32 0, i32* [[A]], align 4
14225 // CHECK17-NEXT:    store i16 0, i16* [[AA]], align 2
14226 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
14227 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
14228 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
14229 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
14230 // CHECK17-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
14231 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
14232 // CHECK17-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
14233 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
14234 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
14235 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
14236 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
14237 // CHECK17:       omp_if.then:
14238 // CHECK17-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
14239 // CHECK17-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
14240 // CHECK17-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
14241 // CHECK17-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
14242 // CHECK17-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
14243 // CHECK17-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
14244 // CHECK17-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
14245 // CHECK17-NEXT:    store i8* null, i8** [[TMP9]], align 8
14246 // CHECK17-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
14247 // CHECK17-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
14248 // CHECK17-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
14249 // CHECK17-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
14250 // CHECK17-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
14251 // CHECK17-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
14252 // CHECK17-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
14253 // CHECK17-NEXT:    store i8* null, i8** [[TMP14]], align 8
14254 // CHECK17-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
14255 // CHECK17-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
14256 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
14257 // CHECK17-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
14258 // CHECK17-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
14259 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
14260 // CHECK17-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
14261 // CHECK17-NEXT:    store i8* null, i8** [[TMP19]], align 8
14262 // CHECK17-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
14263 // CHECK17-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
14264 // CHECK17-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
14265 // CHECK17-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
14266 // CHECK17-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
14267 // CHECK17:       omp_offload.failed:
14268 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
14269 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
14270 // CHECK17:       omp_offload.cont:
14271 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
14272 // CHECK17:       omp_if.else:
14273 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
14274 // CHECK17-NEXT:    br label [[OMP_IF_END]]
14275 // CHECK17:       omp_if.end:
14276 // CHECK17-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
14277 // CHECK17-NEXT:    ret i32 [[TMP24]]
14278 //
14279 //
14280 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
14281 // CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
14282 // CHECK17-NEXT:  entry:
14283 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
14284 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
14285 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
14286 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
14287 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
14288 // CHECK17-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
14289 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
14290 // CHECK17-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
14291 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
14292 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
14293 // CHECK17-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
14294 // CHECK17-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
14295 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
14296 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
14297 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
14298 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
14299 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
14300 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
14301 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
14302 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
14303 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
14304 // CHECK17-NEXT:    ret void
14305 //
14306 //
14307 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9
14308 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
14309 // CHECK17-NEXT:  entry:
14310 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
14311 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
14312 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
14313 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
14314 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
14315 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
14316 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
14317 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
14318 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i64, align 8
14319 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
14320 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
14321 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
14322 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
14323 // CHECK17-NEXT:    [[IT:%.*]] = alloca i64, align 8
14324 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
14325 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
14326 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
14327 // CHECK17-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
14328 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
14329 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
14330 // CHECK17-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
14331 // CHECK17-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
14332 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
14333 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
14334 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
14335 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
14336 // CHECK17-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
14337 // CHECK17-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
14338 // CHECK17-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
14339 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
14340 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
14341 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
14342 // CHECK17-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
14343 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
14344 // CHECK17-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
14345 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
14346 // CHECK17:       cond.true:
14347 // CHECK17-NEXT:    br label [[COND_END:%.*]]
14348 // CHECK17:       cond.false:
14349 // CHECK17-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
14350 // CHECK17-NEXT:    br label [[COND_END]]
14351 // CHECK17:       cond.end:
14352 // CHECK17-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
14353 // CHECK17-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
14354 // CHECK17-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
14355 // CHECK17-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
14356 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14357 // CHECK17:       omp.inner.for.cond:
14358 // CHECK17-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
14359 // CHECK17-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
14360 // CHECK17-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
14361 // CHECK17-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14362 // CHECK17:       omp.inner.for.body:
14363 // CHECK17-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
14364 // CHECK17-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
14365 // CHECK17-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
14366 // CHECK17-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
14367 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
14368 // CHECK17-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
14369 // CHECK17-NEXT:    [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
14370 // CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
14371 // CHECK17-NEXT:    store double [[ADD]], double* [[A]], align 8
14372 // CHECK17-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
14373 // CHECK17-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 8
14374 // CHECK17-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
14375 // CHECK17-NEXT:    store double [[INC]], double* [[A5]], align 8
14376 // CHECK17-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
14377 // CHECK17-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
14378 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
14379 // CHECK17-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
14380 // CHECK17-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
14381 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14382 // CHECK17:       omp.body.continue:
14383 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14384 // CHECK17:       omp.inner.for.inc:
14385 // CHECK17-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
14386 // CHECK17-NEXT:    [[ADD8:%.*]] = add i64 [[TMP15]], 1
14387 // CHECK17-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
14388 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
14389 // CHECK17:       omp.inner.for.end:
14390 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
14391 // CHECK17:       omp.loop.exit:
14392 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
14393 // CHECK17-NEXT:    ret void
14394 //
14395 //
14396 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
14397 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
14398 // CHECK17-NEXT:  entry:
14399 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
14400 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
14401 // CHECK17-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
14402 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
14403 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
14404 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
14405 // CHECK17-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
14406 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
14407 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
14408 // CHECK17-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
14409 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
14410 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
14411 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
14412 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
14413 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
14414 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
14415 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
14416 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
14417 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
14418 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
14419 // CHECK17-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
14420 // CHECK17-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
14421 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
14422 // CHECK17-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
14423 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
14424 // CHECK17-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
14425 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
14426 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
14427 // CHECK17-NEXT:    ret void
14428 //
14429 //
14430 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11
14431 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
14432 // CHECK17-NEXT:  entry:
14433 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
14434 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
14435 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
14436 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
14437 // CHECK17-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
14438 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
14439 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
14440 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14441 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
14442 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
14443 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
14444 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
14445 // CHECK17-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
14446 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
14447 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
14448 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
14449 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
14450 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
14451 // CHECK17-NEXT:    ret void
14452 //
14453 //
14454 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
14455 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
14456 // CHECK17-NEXT:  entry:
14457 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
14458 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
14459 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
14460 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
14461 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
14462 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
14463 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
14464 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
14465 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
14466 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
14467 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
14468 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
14469 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
14470 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
14471 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
14472 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
14473 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
14474 // CHECK17-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
14475 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
14476 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
14477 // CHECK17-NEXT:    ret void
14478 //
14479 //
14480 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..14
14481 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
14482 // CHECK17-NEXT:  entry:
14483 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
14484 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
14485 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
14486 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
14487 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
14488 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
14489 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i64, align 8
14490 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
14491 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
14492 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
14493 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
14494 // CHECK17-NEXT:    [[I:%.*]] = alloca i64, align 8
14495 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
14496 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
14497 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
14498 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
14499 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
14500 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
14501 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
14502 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
14503 // CHECK17-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
14504 // CHECK17-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
14505 // CHECK17-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
14506 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
14507 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
14508 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
14509 // CHECK17-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
14510 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
14511 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
14512 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
14513 // CHECK17:       cond.true:
14514 // CHECK17-NEXT:    br label [[COND_END:%.*]]
14515 // CHECK17:       cond.false:
14516 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
14517 // CHECK17-NEXT:    br label [[COND_END]]
14518 // CHECK17:       cond.end:
14519 // CHECK17-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
14520 // CHECK17-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
14521 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
14522 // CHECK17-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
14523 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14524 // CHECK17:       omp.inner.for.cond:
14525 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
14526 // CHECK17-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
14527 // CHECK17-NEXT:    [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
14528 // CHECK17-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14529 // CHECK17:       omp.inner.for.body:
14530 // CHECK17-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
14531 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
14532 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
14533 // CHECK17-NEXT:    store i64 [[ADD]], i64* [[I]], align 8
14534 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
14535 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
14536 // CHECK17-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
14537 // CHECK17-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
14538 // CHECK17-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
14539 // CHECK17-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
14540 // CHECK17-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
14541 // CHECK17-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
14542 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
14543 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
14544 // CHECK17-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
14545 // CHECK17-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
14546 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14547 // CHECK17:       omp.body.continue:
14548 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14549 // CHECK17:       omp.inner.for.inc:
14550 // CHECK17-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
14551 // CHECK17-NEXT:    [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
14552 // CHECK17-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
14553 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
14554 // CHECK17:       omp.inner.for.end:
14555 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
14556 // CHECK17:       omp.loop.exit:
14557 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
14558 // CHECK17-NEXT:    ret void
14559 //
14560 //
14561 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
14562 // CHECK17-SAME: () #[[ATTR5]] {
14563 // CHECK17-NEXT:  entry:
14564 // CHECK17-NEXT:    call void @__tgt_register_requires(i64 1)
14565 // CHECK17-NEXT:    ret void
14566 //
14567 //
14568 // CHECK18-LABEL: define {{[^@]+}}@_Z7get_valv
14569 // CHECK18-SAME: () #[[ATTR0:[0-9]+]] {
14570 // CHECK18-NEXT:  entry:
14571 // CHECK18-NEXT:    ret i64 0
14572 //
14573 //
14574 // CHECK18-LABEL: define {{[^@]+}}@_Z3fooi
14575 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
14576 // CHECK18-NEXT:  entry:
14577 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14578 // CHECK18-NEXT:    [[A:%.*]] = alloca i32, align 4
14579 // CHECK18-NEXT:    [[AA:%.*]] = alloca i16, align 2
14580 // CHECK18-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
14581 // CHECK18-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
14582 // CHECK18-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
14583 // CHECK18-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
14584 // CHECK18-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
14585 // CHECK18-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
14586 // CHECK18-NEXT:    [[K:%.*]] = alloca i64, align 8
14587 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
14588 // CHECK18-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
14589 // CHECK18-NEXT:    [[LIN:%.*]] = alloca i32, align 4
14590 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
14591 // CHECK18-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
14592 // CHECK18-NEXT:    [[A_CASTED4:%.*]] = alloca i64, align 8
14593 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
14594 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
14595 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
14596 // CHECK18-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
14597 // CHECK18-NEXT:    [[A_CASTED6:%.*]] = alloca i64, align 8
14598 // CHECK18-NEXT:    [[AA_CASTED8:%.*]] = alloca i64, align 8
14599 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
14600 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
14601 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
14602 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
14603 // CHECK18-NEXT:    [[A_CASTED15:%.*]] = alloca i64, align 8
14604 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
14605 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8
14606 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8
14607 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8
14608 // CHECK18-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
14609 // CHECK18-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
14610 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14611 // CHECK18-NEXT:    store i32 0, i32* [[A]], align 4
14612 // CHECK18-NEXT:    store i16 0, i16* [[AA]], align 2
14613 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
14614 // CHECK18-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
14615 // CHECK18-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
14616 // CHECK18-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
14617 // CHECK18-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
14618 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
14619 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
14620 // CHECK18-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
14621 // CHECK18-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
14622 // CHECK18-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
14623 // CHECK18-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
14624 // CHECK18-NEXT:    [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
14625 // CHECK18-NEXT:    [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
14626 // CHECK18-NEXT:    br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
14627 // CHECK18:       omp_offload.failed:
14628 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]]
14629 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT]]
14630 // CHECK18:       omp_offload.cont:
14631 // CHECK18-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
14632 // CHECK18-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
14633 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
14634 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
14635 // CHECK18-NEXT:    store i32 [[TMP9]], i32* [[CONV]], align 4
14636 // CHECK18-NEXT:    [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8
14637 // CHECK18-NEXT:    [[TMP11:%.*]] = load i64, i64* [[K]], align 8
14638 // CHECK18-NEXT:    store i64 [[TMP11]], i64* [[K_CASTED]], align 8
14639 // CHECK18-NEXT:    [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8
14640 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR3]]
14641 // CHECK18-NEXT:    store i32 12, i32* [[LIN]], align 4
14642 // CHECK18-NEXT:    [[TMP13:%.*]] = load i16, i16* [[AA]], align 2
14643 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
14644 // CHECK18-NEXT:    store i16 [[TMP13]], i16* [[CONV2]], align 2
14645 // CHECK18-NEXT:    [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8
14646 // CHECK18-NEXT:    [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4
14647 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
14648 // CHECK18-NEXT:    store i32 [[TMP15]], i32* [[CONV3]], align 4
14649 // CHECK18-NEXT:    [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
14650 // CHECK18-NEXT:    [[TMP17:%.*]] = load i32, i32* [[A]], align 4
14651 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32*
14652 // CHECK18-NEXT:    store i32 [[TMP17]], i32* [[CONV5]], align 4
14653 // CHECK18-NEXT:    [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8
14654 // CHECK18-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
14655 // CHECK18-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
14656 // CHECK18-NEXT:    store i64 [[TMP14]], i64* [[TMP20]], align 8
14657 // CHECK18-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
14658 // CHECK18-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
14659 // CHECK18-NEXT:    store i64 [[TMP14]], i64* [[TMP22]], align 8
14660 // CHECK18-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
14661 // CHECK18-NEXT:    store i8* null, i8** [[TMP23]], align 8
14662 // CHECK18-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
14663 // CHECK18-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
14664 // CHECK18-NEXT:    store i64 [[TMP16]], i64* [[TMP25]], align 8
14665 // CHECK18-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
14666 // CHECK18-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
14667 // CHECK18-NEXT:    store i64 [[TMP16]], i64* [[TMP27]], align 8
14668 // CHECK18-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
14669 // CHECK18-NEXT:    store i8* null, i8** [[TMP28]], align 8
14670 // CHECK18-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
14671 // CHECK18-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64*
14672 // CHECK18-NEXT:    store i64 [[TMP18]], i64* [[TMP30]], align 8
14673 // CHECK18-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
14674 // CHECK18-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
14675 // CHECK18-NEXT:    store i64 [[TMP18]], i64* [[TMP32]], align 8
14676 // CHECK18-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
14677 // CHECK18-NEXT:    store i8* null, i8** [[TMP33]], align 8
14678 // CHECK18-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
14679 // CHECK18-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
14680 // CHECK18-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
14681 // CHECK18-NEXT:    [[TMP37:%.*]] = load i16, i16* [[AA]], align 2
14682 // CHECK18-NEXT:    store i16 [[TMP37]], i16* [[TMP36]], align 4
14683 // CHECK18-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
14684 // CHECK18-NEXT:    [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4
14685 // CHECK18-NEXT:    store i32 [[TMP39]], i32* [[TMP38]], align 4
14686 // CHECK18-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
14687 // CHECK18-NEXT:    [[TMP41:%.*]] = load i32, i32* [[A]], align 4
14688 // CHECK18-NEXT:    store i32 [[TMP41]], i32* [[TMP40]], align 4
14689 // CHECK18-NEXT:    [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
14690 // CHECK18-NEXT:    [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates*
14691 // CHECK18-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0
14692 // CHECK18-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0
14693 // CHECK18-NEXT:    [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8
14694 // CHECK18-NEXT:    [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
14695 // CHECK18-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false)
14696 // CHECK18-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1
14697 // CHECK18-NEXT:    [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon*
14698 // CHECK18-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0
14699 // CHECK18-NEXT:    [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8*
14700 // CHECK18-NEXT:    [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8*
14701 // CHECK18-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false)
14702 // CHECK18-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1
14703 // CHECK18-NEXT:    [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8*
14704 // CHECK18-NEXT:    [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8*
14705 // CHECK18-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false)
14706 // CHECK18-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2
14707 // CHECK18-NEXT:    [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8*
14708 // CHECK18-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
14709 // CHECK18-NEXT:    [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3
14710 // CHECK18-NEXT:    [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
14711 // CHECK18-NEXT:    store i16 [[TMP59]], i16* [[TMP58]], align 8
14712 // CHECK18-NEXT:    [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]])
14713 // CHECK18-NEXT:    [[TMP61:%.*]] = load i32, i32* [[A]], align 4
14714 // CHECK18-NEXT:    [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32*
14715 // CHECK18-NEXT:    store i32 [[TMP61]], i32* [[CONV7]], align 4
14716 // CHECK18-NEXT:    [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8
14717 // CHECK18-NEXT:    [[TMP63:%.*]] = load i16, i16* [[AA]], align 2
14718 // CHECK18-NEXT:    [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16*
14719 // CHECK18-NEXT:    store i16 [[TMP63]], i16* [[CONV9]], align 2
14720 // CHECK18-NEXT:    [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8
14721 // CHECK18-NEXT:    [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4
14722 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10
14723 // CHECK18-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
14724 // CHECK18:       omp_if.then:
14725 // CHECK18-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
14726 // CHECK18-NEXT:    [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64*
14727 // CHECK18-NEXT:    store i64 [[TMP62]], i64* [[TMP67]], align 8
14728 // CHECK18-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
14729 // CHECK18-NEXT:    [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64*
14730 // CHECK18-NEXT:    store i64 [[TMP62]], i64* [[TMP69]], align 8
14731 // CHECK18-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
14732 // CHECK18-NEXT:    store i8* null, i8** [[TMP70]], align 8
14733 // CHECK18-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
14734 // CHECK18-NEXT:    [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64*
14735 // CHECK18-NEXT:    store i64 [[TMP64]], i64* [[TMP72]], align 8
14736 // CHECK18-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
14737 // CHECK18-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64*
14738 // CHECK18-NEXT:    store i64 [[TMP64]], i64* [[TMP74]], align 8
14739 // CHECK18-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
14740 // CHECK18-NEXT:    store i8* null, i8** [[TMP75]], align 8
14741 // CHECK18-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
14742 // CHECK18-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
14743 // CHECK18-NEXT:    [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
14744 // CHECK18-NEXT:    [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0
14745 // CHECK18-NEXT:    br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]]
14746 // CHECK18:       omp_offload.failed13:
14747 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR3]]
14748 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT14]]
14749 // CHECK18:       omp_offload.cont14:
14750 // CHECK18-NEXT:    br label [[OMP_IF_END:%.*]]
14751 // CHECK18:       omp_if.else:
14752 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR3]]
14753 // CHECK18-NEXT:    br label [[OMP_IF_END]]
14754 // CHECK18:       omp_if.end:
14755 // CHECK18-NEXT:    [[TMP80:%.*]] = load i32, i32* [[A]], align 4
14756 // CHECK18-NEXT:    store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4
14757 // CHECK18-NEXT:    [[TMP81:%.*]] = load i32, i32* [[A]], align 4
14758 // CHECK18-NEXT:    [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32*
14759 // CHECK18-NEXT:    store i32 [[TMP81]], i32* [[CONV16]], align 4
14760 // CHECK18-NEXT:    [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8
14761 // CHECK18-NEXT:    [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
14762 // CHECK18-NEXT:    [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
14763 // CHECK18-NEXT:    store i32 [[TMP83]], i32* [[CONV17]], align 4
14764 // CHECK18-NEXT:    [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
14765 // CHECK18-NEXT:    [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4
14766 // CHECK18-NEXT:    [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20
14767 // CHECK18-NEXT:    br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
14768 // CHECK18:       omp_if.then19:
14769 // CHECK18-NEXT:    [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4
14770 // CHECK18-NEXT:    [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]]
14771 // CHECK18-NEXT:    [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8
14772 // CHECK18-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
14773 // CHECK18-NEXT:    [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64*
14774 // CHECK18-NEXT:    store i64 [[TMP82]], i64* [[TMP90]], align 8
14775 // CHECK18-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
14776 // CHECK18-NEXT:    [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i64*
14777 // CHECK18-NEXT:    store i64 [[TMP82]], i64* [[TMP92]], align 8
14778 // CHECK18-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
14779 // CHECK18-NEXT:    store i64 4, i64* [[TMP93]], align 8
14780 // CHECK18-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
14781 // CHECK18-NEXT:    store i8* null, i8** [[TMP94]], align 8
14782 // CHECK18-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
14783 // CHECK18-NEXT:    [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]**
14784 // CHECK18-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8
14785 // CHECK18-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
14786 // CHECK18-NEXT:    [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]**
14787 // CHECK18-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8
14788 // CHECK18-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
14789 // CHECK18-NEXT:    store i64 40, i64* [[TMP99]], align 8
14790 // CHECK18-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
14791 // CHECK18-NEXT:    store i8* null, i8** [[TMP100]], align 8
14792 // CHECK18-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
14793 // CHECK18-NEXT:    [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i64*
14794 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[TMP102]], align 8
14795 // CHECK18-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
14796 // CHECK18-NEXT:    [[TMP104:%.*]] = bitcast i8** [[TMP103]] to i64*
14797 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[TMP104]], align 8
14798 // CHECK18-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
14799 // CHECK18-NEXT:    store i64 8, i64* [[TMP105]], align 8
14800 // CHECK18-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
14801 // CHECK18-NEXT:    store i8* null, i8** [[TMP106]], align 8
14802 // CHECK18-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
14803 // CHECK18-NEXT:    [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float**
14804 // CHECK18-NEXT:    store float* [[VLA]], float** [[TMP108]], align 8
14805 // CHECK18-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
14806 // CHECK18-NEXT:    [[TMP110:%.*]] = bitcast i8** [[TMP109]] to float**
14807 // CHECK18-NEXT:    store float* [[VLA]], float** [[TMP110]], align 8
14808 // CHECK18-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
14809 // CHECK18-NEXT:    store i64 [[TMP86]], i64* [[TMP111]], align 8
14810 // CHECK18-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3
14811 // CHECK18-NEXT:    store i8* null, i8** [[TMP112]], align 8
14812 // CHECK18-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
14813 // CHECK18-NEXT:    [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]**
14814 // CHECK18-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8
14815 // CHECK18-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
14816 // CHECK18-NEXT:    [[TMP116:%.*]] = bitcast i8** [[TMP115]] to [5 x [10 x double]]**
14817 // CHECK18-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP116]], align 8
14818 // CHECK18-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
14819 // CHECK18-NEXT:    store i64 400, i64* [[TMP117]], align 8
14820 // CHECK18-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4
14821 // CHECK18-NEXT:    store i8* null, i8** [[TMP118]], align 8
14822 // CHECK18-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
14823 // CHECK18-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i64*
14824 // CHECK18-NEXT:    store i64 5, i64* [[TMP120]], align 8
14825 // CHECK18-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
14826 // CHECK18-NEXT:    [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64*
14827 // CHECK18-NEXT:    store i64 5, i64* [[TMP122]], align 8
14828 // CHECK18-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
14829 // CHECK18-NEXT:    store i64 8, i64* [[TMP123]], align 8
14830 // CHECK18-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5
14831 // CHECK18-NEXT:    store i8* null, i8** [[TMP124]], align 8
14832 // CHECK18-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
14833 // CHECK18-NEXT:    [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64*
14834 // CHECK18-NEXT:    store i64 [[TMP5]], i64* [[TMP126]], align 8
14835 // CHECK18-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
14836 // CHECK18-NEXT:    [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64*
14837 // CHECK18-NEXT:    store i64 [[TMP5]], i64* [[TMP128]], align 8
14838 // CHECK18-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
14839 // CHECK18-NEXT:    store i64 8, i64* [[TMP129]], align 8
14840 // CHECK18-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6
14841 // CHECK18-NEXT:    store i8* null, i8** [[TMP130]], align 8
14842 // CHECK18-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
14843 // CHECK18-NEXT:    [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double**
14844 // CHECK18-NEXT:    store double* [[VLA1]], double** [[TMP132]], align 8
14845 // CHECK18-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
14846 // CHECK18-NEXT:    [[TMP134:%.*]] = bitcast i8** [[TMP133]] to double**
14847 // CHECK18-NEXT:    store double* [[VLA1]], double** [[TMP134]], align 8
14848 // CHECK18-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
14849 // CHECK18-NEXT:    store i64 [[TMP88]], i64* [[TMP135]], align 8
14850 // CHECK18-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7
14851 // CHECK18-NEXT:    store i8* null, i8** [[TMP136]], align 8
14852 // CHECK18-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
14853 // CHECK18-NEXT:    [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT**
14854 // CHECK18-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 8
14855 // CHECK18-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
14856 // CHECK18-NEXT:    [[TMP140:%.*]] = bitcast i8** [[TMP139]] to %struct.TT**
14857 // CHECK18-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP140]], align 8
14858 // CHECK18-NEXT:    [[TMP141:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
14859 // CHECK18-NEXT:    store i64 16, i64* [[TMP141]], align 8
14860 // CHECK18-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8
14861 // CHECK18-NEXT:    store i8* null, i8** [[TMP142]], align 8
14862 // CHECK18-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9
14863 // CHECK18-NEXT:    [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i64*
14864 // CHECK18-NEXT:    store i64 [[TMP84]], i64* [[TMP144]], align 8
14865 // CHECK18-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9
14866 // CHECK18-NEXT:    [[TMP146:%.*]] = bitcast i8** [[TMP145]] to i64*
14867 // CHECK18-NEXT:    store i64 [[TMP84]], i64* [[TMP146]], align 8
14868 // CHECK18-NEXT:    [[TMP147:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
14869 // CHECK18-NEXT:    store i64 4, i64* [[TMP147]], align 8
14870 // CHECK18-NEXT:    [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9
14871 // CHECK18-NEXT:    store i8* null, i8** [[TMP148]], align 8
14872 // CHECK18-NEXT:    [[TMP149:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
14873 // CHECK18-NEXT:    [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
14874 // CHECK18-NEXT:    [[TMP151:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
14875 // CHECK18-NEXT:    [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
14876 // CHECK18-NEXT:    [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0
14877 // CHECK18-NEXT:    br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
14878 // CHECK18:       omp_offload.failed23:
14879 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR3]]
14880 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT24]]
14881 // CHECK18:       omp_offload.cont24:
14882 // CHECK18-NEXT:    br label [[OMP_IF_END26:%.*]]
14883 // CHECK18:       omp_if.else25:
14884 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR3]]
14885 // CHECK18-NEXT:    br label [[OMP_IF_END26]]
14886 // CHECK18:       omp_if.end26:
14887 // CHECK18-NEXT:    [[TMP154:%.*]] = load i32, i32* [[A]], align 4
14888 // CHECK18-NEXT:    [[TMP155:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
14889 // CHECK18-NEXT:    call void @llvm.stackrestore(i8* [[TMP155]])
14890 // CHECK18-NEXT:    ret i32 [[TMP154]]
14891 //
14892 //
14893 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
14894 // CHECK18-SAME: () #[[ATTR2:[0-9]+]] {
14895 // CHECK18-NEXT:  entry:
14896 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
14897 // CHECK18-NEXT:    ret void
14898 //
14899 //
14900 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
14901 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
14902 // CHECK18-NEXT:  entry:
14903 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
14904 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
14905 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
14906 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14907 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
14908 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
14909 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
14910 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
14911 // CHECK18-NEXT:    [[I:%.*]] = alloca i32, align 4
14912 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
14913 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
14914 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
14915 // CHECK18-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
14916 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
14917 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
14918 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
14919 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
14920 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
14921 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14922 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
14923 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
14924 // CHECK18:       cond.true:
14925 // CHECK18-NEXT:    br label [[COND_END:%.*]]
14926 // CHECK18:       cond.false:
14927 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14928 // CHECK18-NEXT:    br label [[COND_END]]
14929 // CHECK18:       cond.end:
14930 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
14931 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
14932 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14933 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
14934 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14935 // CHECK18:       omp.inner.for.cond:
14936 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14937 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14938 // CHECK18-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
14939 // CHECK18-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14940 // CHECK18:       omp.inner.for.body:
14941 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14942 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
14943 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
14944 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
14945 // CHECK18-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
14946 // CHECK18-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
14947 // CHECK18-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
14948 // CHECK18:       .cancel.exit:
14949 // CHECK18-NEXT:    br label [[CANCEL_EXIT:%.*]]
14950 // CHECK18:       .cancel.continue:
14951 // CHECK18-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
14952 // CHECK18-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
14953 // CHECK18-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
14954 // CHECK18:       .cancel.exit2:
14955 // CHECK18-NEXT:    br label [[CANCEL_EXIT]]
14956 // CHECK18:       .cancel.continue3:
14957 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14958 // CHECK18:       omp.body.continue:
14959 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14960 // CHECK18:       omp.inner.for.inc:
14961 // CHECK18-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14962 // CHECK18-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
14963 // CHECK18-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
14964 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]]
14965 // CHECK18:       omp.inner.for.end:
14966 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
14967 // CHECK18:       omp.loop.exit:
14968 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
14969 // CHECK18-NEXT:    br label [[CANCEL_CONT:%.*]]
14970 // CHECK18:       cancel.cont:
14971 // CHECK18-NEXT:    ret void
14972 // CHECK18:       cancel.exit:
14973 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
14974 // CHECK18-NEXT:    br label [[CANCEL_CONT]]
14975 //
14976 //
14977 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
14978 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR2]] {
14979 // CHECK18-NEXT:  entry:
14980 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
14981 // CHECK18-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
14982 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
14983 // CHECK18-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
14984 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
14985 // CHECK18-NEXT:    store i64 [[K]], i64* [[K_ADDR]], align 8
14986 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
14987 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
14988 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
14989 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
14990 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
14991 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
14992 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[K_CASTED]], align 8
14993 // CHECK18-NEXT:    [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
14994 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
14995 // CHECK18-NEXT:    ret void
14996 //
14997 //
14998 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1
14999 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR2]] {
15000 // CHECK18-NEXT:  entry:
15001 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
15002 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
15003 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
15004 // CHECK18-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
15005 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
15006 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15007 // CHECK18-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
15008 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15009 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15010 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
15011 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
15012 // CHECK18-NEXT:    [[I:%.*]] = alloca i32, align 4
15013 // CHECK18-NEXT:    [[K1:%.*]] = alloca i64, align 8
15014 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
15015 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
15016 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
15017 // CHECK18-NEXT:    store i64 [[K]], i64* [[K_ADDR]], align 8
15018 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
15019 // CHECK18-NEXT:    [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8
15020 // CHECK18-NEXT:    store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8
15021 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15022 // CHECK18-NEXT:    store i32 8, i32* [[DOTOMP_UB]], align 4
15023 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
15024 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
15025 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
15026 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
15027 // CHECK18-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]])
15028 // CHECK18-NEXT:    call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
15029 // CHECK18-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
15030 // CHECK18:       omp.dispatch.cond:
15031 // CHECK18-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
15032 // CHECK18-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
15033 // CHECK18-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
15034 // CHECK18:       omp.dispatch.body:
15035 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15036 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
15037 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15038 // CHECK18:       omp.inner.for.cond:
15039 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
15040 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
15041 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
15042 // CHECK18-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15043 // CHECK18:       omp.inner.for.body:
15044 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
15045 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
15046 // CHECK18-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
15047 // CHECK18-NEXT:    store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !11
15048 // CHECK18-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !11
15049 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
15050 // CHECK18-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
15051 // CHECK18-NEXT:    [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
15052 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
15053 // CHECK18-NEXT:    store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !11
15054 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11
15055 // CHECK18-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
15056 // CHECK18-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !11
15057 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15058 // CHECK18:       omp.body.continue:
15059 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15060 // CHECK18:       omp.inner.for.inc:
15061 // CHECK18-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
15062 // CHECK18-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
15063 // CHECK18-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
15064 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
15065 // CHECK18:       omp.inner.for.end:
15066 // CHECK18-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
15067 // CHECK18:       omp.dispatch.inc:
15068 // CHECK18-NEXT:    br label [[OMP_DISPATCH_COND]]
15069 // CHECK18:       omp.dispatch.end:
15070 // CHECK18-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
15071 // CHECK18-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
15072 // CHECK18-NEXT:    br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
15073 // CHECK18:       .omp.linear.pu:
15074 // CHECK18-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
15075 // CHECK18-NEXT:    [[ADD6:%.*]] = add nsw i64 [[TMP14]], 27
15076 // CHECK18-NEXT:    store i64 [[ADD6]], i64* [[K_ADDR]], align 8
15077 // CHECK18-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
15078 // CHECK18:       .omp.linear.pu.done:
15079 // CHECK18-NEXT:    ret void
15080 //
15081 //
15082 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
15083 // CHECK18-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
15084 // CHECK18-NEXT:  entry:
15085 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
15086 // CHECK18-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
15087 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
15088 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
15089 // CHECK18-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
15090 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
15091 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
15092 // CHECK18-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
15093 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
15094 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
15095 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
15096 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
15097 // CHECK18-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
15098 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
15099 // CHECK18-NEXT:    store i16 [[TMP0]], i16* [[CONV3]], align 2
15100 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
15101 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
15102 // CHECK18-NEXT:    [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
15103 // CHECK18-NEXT:    store i32 [[TMP2]], i32* [[CONV4]], align 4
15104 // CHECK18-NEXT:    [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
15105 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
15106 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
15107 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[CONV5]], align 4
15108 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
15109 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
15110 // CHECK18-NEXT:    ret void
15111 //
15112 //
15113 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2
15114 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
15115 // CHECK18-NEXT:  entry:
15116 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
15117 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
15118 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
15119 // CHECK18-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
15120 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
15121 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
15122 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i64, align 8
15123 // CHECK18-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
15124 // CHECK18-NEXT:    [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
15125 // CHECK18-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
15126 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
15127 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
15128 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
15129 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
15130 // CHECK18-NEXT:    [[IT:%.*]] = alloca i64, align 8
15131 // CHECK18-NEXT:    [[LIN4:%.*]] = alloca i32, align 4
15132 // CHECK18-NEXT:    [[A5:%.*]] = alloca i32, align 4
15133 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
15134 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
15135 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
15136 // CHECK18-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
15137 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
15138 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
15139 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
15140 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
15141 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
15142 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
15143 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
15144 // CHECK18-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
15145 // CHECK18-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
15146 // CHECK18-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
15147 // CHECK18-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
15148 // CHECK18-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
15149 // CHECK18-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
15150 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
15151 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
15152 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
15153 // CHECK18-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
15154 // CHECK18-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
15155 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
15156 // CHECK18-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
15157 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
15158 // CHECK18:       cond.true:
15159 // CHECK18-NEXT:    br label [[COND_END:%.*]]
15160 // CHECK18:       cond.false:
15161 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
15162 // CHECK18-NEXT:    br label [[COND_END]]
15163 // CHECK18:       cond.end:
15164 // CHECK18-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
15165 // CHECK18-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
15166 // CHECK18-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
15167 // CHECK18-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
15168 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15169 // CHECK18:       omp.inner.for.cond:
15170 // CHECK18-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
15171 // CHECK18-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
15172 // CHECK18-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
15173 // CHECK18-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15174 // CHECK18:       omp.inner.for.body:
15175 // CHECK18-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
15176 // CHECK18-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
15177 // CHECK18-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
15178 // CHECK18-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
15179 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
15180 // CHECK18-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
15181 // CHECK18-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
15182 // CHECK18-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
15183 // CHECK18-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
15184 // CHECK18-NEXT:    [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
15185 // CHECK18-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
15186 // CHECK18-NEXT:    store i32 [[CONV9]], i32* [[LIN4]], align 4
15187 // CHECK18-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
15188 // CHECK18-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
15189 // CHECK18-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
15190 // CHECK18-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
15191 // CHECK18-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
15192 // CHECK18-NEXT:    [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
15193 // CHECK18-NEXT:    [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
15194 // CHECK18-NEXT:    store i32 [[CONV13]], i32* [[A5]], align 4
15195 // CHECK18-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8
15196 // CHECK18-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
15197 // CHECK18-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
15198 // CHECK18-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
15199 // CHECK18-NEXT:    store i16 [[CONV16]], i16* [[CONV]], align 8
15200 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15201 // CHECK18:       omp.body.continue:
15202 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15203 // CHECK18:       omp.inner.for.inc:
15204 // CHECK18-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
15205 // CHECK18-NEXT:    [[ADD17:%.*]] = add i64 [[TMP17]], 1
15206 // CHECK18-NEXT:    store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
15207 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]]
15208 // CHECK18:       omp.inner.for.end:
15209 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
15210 // CHECK18:       omp.loop.exit:
15211 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
15212 // CHECK18-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
15213 // CHECK18-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
15214 // CHECK18-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
15215 // CHECK18:       .omp.linear.pu:
15216 // CHECK18-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
15217 // CHECK18-NEXT:    [[CONV18:%.*]] = sext i32 [[TMP20]] to i64
15218 // CHECK18-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
15219 // CHECK18-NEXT:    [[MUL19:%.*]] = mul i64 4, [[TMP21]]
15220 // CHECK18-NEXT:    [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
15221 // CHECK18-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
15222 // CHECK18-NEXT:    store i32 [[CONV21]], i32* [[CONV1]], align 8
15223 // CHECK18-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
15224 // CHECK18-NEXT:    [[CONV22:%.*]] = sext i32 [[TMP22]] to i64
15225 // CHECK18-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
15226 // CHECK18-NEXT:    [[MUL23:%.*]] = mul i64 4, [[TMP23]]
15227 // CHECK18-NEXT:    [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
15228 // CHECK18-NEXT:    [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
15229 // CHECK18-NEXT:    store i32 [[CONV25]], i32* [[CONV2]], align 8
15230 // CHECK18-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
15231 // CHECK18:       .omp.linear.pu.done:
15232 // CHECK18-NEXT:    ret void
15233 //
15234 //
15235 // CHECK18-LABEL: define {{[^@]+}}@.omp_task_privates_map.
15236 // CHECK18-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
15237 // CHECK18-NEXT:  entry:
15238 // CHECK18-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
15239 // CHECK18-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 8
15240 // CHECK18-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
15241 // CHECK18-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
15242 // CHECK18-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
15243 // CHECK18-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
15244 // CHECK18-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
15245 // CHECK18-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
15246 // CHECK18-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
15247 // CHECK18-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
15248 // CHECK18-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
15249 // CHECK18-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
15250 // CHECK18-NEXT:    [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
15251 // CHECK18-NEXT:    store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
15252 // CHECK18-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
15253 // CHECK18-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
15254 // CHECK18-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
15255 // CHECK18-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
15256 // CHECK18-NEXT:    [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
15257 // CHECK18-NEXT:    store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
15258 // CHECK18-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
15259 // CHECK18-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
15260 // CHECK18-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 8
15261 // CHECK18-NEXT:    ret void
15262 //
15263 //
15264 // CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry.
15265 // CHECK18-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
15266 // CHECK18-NEXT:  entry:
15267 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
15268 // CHECK18-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
15269 // CHECK18-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
15270 // CHECK18-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
15271 // CHECK18-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
15272 // CHECK18-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
15273 // CHECK18-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
15274 // CHECK18-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
15275 // CHECK18-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
15276 // CHECK18-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
15277 // CHECK18-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
15278 // CHECK18-NEXT:    [[LIN_CASTED_I:%.*]] = alloca i64, align 8
15279 // CHECK18-NEXT:    [[A_CASTED_I:%.*]] = alloca i64, align 8
15280 // CHECK18-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
15281 // CHECK18-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
15282 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
15283 // CHECK18-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
15284 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
15285 // CHECK18-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
15286 // CHECK18-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
15287 // CHECK18-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
15288 // CHECK18-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
15289 // CHECK18-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
15290 // CHECK18-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
15291 // CHECK18-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
15292 // CHECK18-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
15293 // CHECK18-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
15294 // CHECK18-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])
15295 // CHECK18-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
15296 // CHECK18-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
15297 // CHECK18-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
15298 // CHECK18-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23
15299 // CHECK18-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23
15300 // CHECK18-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23
15301 // CHECK18-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23
15302 // CHECK18-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23
15303 // CHECK18-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23
15304 // CHECK18-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23
15305 // CHECK18-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23
15306 // CHECK18-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23
15307 // CHECK18-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
15308 // CHECK18-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
15309 // CHECK18-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23
15310 // CHECK18-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23
15311 // CHECK18-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23
15312 // CHECK18-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23
15313 // CHECK18-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
15314 // CHECK18-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
15315 // CHECK18-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
15316 // CHECK18-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
15317 // CHECK18-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
15318 // CHECK18-NEXT:    [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) #[[ATTR3]]
15319 // CHECK18-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
15320 // CHECK18-NEXT:    br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
15321 // CHECK18:       omp_offload.failed.i:
15322 // CHECK18-NEXT:    [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2
15323 // CHECK18-NEXT:    [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
15324 // CHECK18-NEXT:    store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !23
15325 // CHECK18-NEXT:    [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !23
15326 // CHECK18-NEXT:    [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4
15327 // CHECK18-NEXT:    [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32*
15328 // CHECK18-NEXT:    store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !23
15329 // CHECK18-NEXT:    [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !23
15330 // CHECK18-NEXT:    [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4
15331 // CHECK18-NEXT:    [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32*
15332 // CHECK18-NEXT:    store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !23
15333 // CHECK18-NEXT:    [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !23
15334 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR3]]
15335 // CHECK18-NEXT:    br label [[DOTOMP_OUTLINED__3_EXIT]]
15336 // CHECK18:       .omp_outlined..3.exit:
15337 // CHECK18-NEXT:    ret i32 0
15338 //
15339 //
15340 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
15341 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
15342 // CHECK18-NEXT:  entry:
15343 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
15344 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
15345 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
15346 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
15347 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
15348 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
15349 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
15350 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
15351 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
15352 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
15353 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
15354 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
15355 // CHECK18-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
15356 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
15357 // CHECK18-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
15358 // CHECK18-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
15359 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
15360 // CHECK18-NEXT:    ret void
15361 //
15362 //
15363 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4
15364 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
15365 // CHECK18-NEXT:  entry:
15366 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
15367 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
15368 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
15369 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
15370 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
15371 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i16, align 2
15372 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15373 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15374 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
15375 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
15376 // CHECK18-NEXT:    [[IT:%.*]] = alloca i16, align 2
15377 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
15378 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
15379 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
15380 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
15381 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
15382 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
15383 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15384 // CHECK18-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
15385 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
15386 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
15387 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
15388 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
15389 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
15390 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15391 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
15392 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
15393 // CHECK18:       cond.true:
15394 // CHECK18-NEXT:    br label [[COND_END:%.*]]
15395 // CHECK18:       cond.false:
15396 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15397 // CHECK18-NEXT:    br label [[COND_END]]
15398 // CHECK18:       cond.end:
15399 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
15400 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
15401 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15402 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
15403 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15404 // CHECK18:       omp.inner.for.cond:
15405 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15406 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15407 // CHECK18-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
15408 // CHECK18-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15409 // CHECK18:       omp.inner.for.body:
15410 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15411 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
15412 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
15413 // CHECK18-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
15414 // CHECK18-NEXT:    store i16 [[CONV3]], i16* [[IT]], align 2
15415 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
15416 // CHECK18-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
15417 // CHECK18-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8
15418 // CHECK18-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
15419 // CHECK18-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
15420 // CHECK18-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
15421 // CHECK18-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
15422 // CHECK18-NEXT:    store i16 [[CONV7]], i16* [[CONV1]], align 8
15423 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15424 // CHECK18:       omp.body.continue:
15425 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15426 // CHECK18:       omp.inner.for.inc:
15427 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15428 // CHECK18-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
15429 // CHECK18-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
15430 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]]
15431 // CHECK18:       omp.inner.for.end:
15432 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
15433 // CHECK18:       omp.loop.exit:
15434 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
15435 // CHECK18-NEXT:    ret void
15436 //
15437 //
15438 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
15439 // CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
15440 // CHECK18-NEXT:  entry:
15441 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
15442 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
15443 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
15444 // CHECK18-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
15445 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
15446 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
15447 // CHECK18-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
15448 // CHECK18-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
15449 // CHECK18-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
15450 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
15451 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
15452 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
15453 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
15454 // CHECK18-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
15455 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
15456 // CHECK18-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
15457 // CHECK18-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
15458 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
15459 // CHECK18-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
15460 // CHECK18-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
15461 // CHECK18-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
15462 // CHECK18-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
15463 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
15464 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
15465 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
15466 // CHECK18-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
15467 // CHECK18-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
15468 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
15469 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
15470 // CHECK18-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
15471 // CHECK18-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
15472 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
15473 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
15474 // CHECK18-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
15475 // CHECK18-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
15476 // CHECK18-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
15477 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
15478 // CHECK18-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
15479 // CHECK18-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
15480 // CHECK18-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
15481 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
15482 // CHECK18-NEXT:    ret void
15483 //
15484 //
15485 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7
15486 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
15487 // CHECK18-NEXT:  entry:
15488 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
15489 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
15490 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
15491 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
15492 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
15493 // CHECK18-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
15494 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
15495 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
15496 // CHECK18-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
15497 // CHECK18-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
15498 // CHECK18-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
15499 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
15500 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
15501 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i8, align 1
15502 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15503 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15504 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
15505 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
15506 // CHECK18-NEXT:    [[IT:%.*]] = alloca i8, align 1
15507 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
15508 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
15509 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
15510 // CHECK18-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
15511 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
15512 // CHECK18-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
15513 // CHECK18-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
15514 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
15515 // CHECK18-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
15516 // CHECK18-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
15517 // CHECK18-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
15518 // CHECK18-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
15519 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
15520 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
15521 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
15522 // CHECK18-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
15523 // CHECK18-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
15524 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
15525 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
15526 // CHECK18-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
15527 // CHECK18-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
15528 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
15529 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15530 // CHECK18-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
15531 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
15532 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
15533 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
15534 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
15535 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
15536 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
15537 // CHECK18-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
15538 // CHECK18:       omp.dispatch.cond:
15539 // CHECK18-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15540 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
15541 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
15542 // CHECK18:       cond.true:
15543 // CHECK18-NEXT:    br label [[COND_END:%.*]]
15544 // CHECK18:       cond.false:
15545 // CHECK18-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15546 // CHECK18-NEXT:    br label [[COND_END]]
15547 // CHECK18:       cond.end:
15548 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
15549 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
15550 // CHECK18-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15551 // CHECK18-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
15552 // CHECK18-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15553 // CHECK18-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15554 // CHECK18-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
15555 // CHECK18-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
15556 // CHECK18:       omp.dispatch.body:
15557 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15558 // CHECK18:       omp.inner.for.cond:
15559 // CHECK18-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15560 // CHECK18-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15561 // CHECK18-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
15562 // CHECK18-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15563 // CHECK18:       omp.inner.for.body:
15564 // CHECK18-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15565 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
15566 // CHECK18-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
15567 // CHECK18-NEXT:    [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
15568 // CHECK18-NEXT:    store i8 [[CONV8]], i8* [[IT]], align 1
15569 // CHECK18-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
15570 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
15571 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
15572 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
15573 // CHECK18-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
15574 // CHECK18-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
15575 // CHECK18-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
15576 // CHECK18-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
15577 // CHECK18-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
15578 // CHECK18-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
15579 // CHECK18-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
15580 // CHECK18-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
15581 // CHECK18-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
15582 // CHECK18-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
15583 // CHECK18-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
15584 // CHECK18-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
15585 // CHECK18-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
15586 // CHECK18-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
15587 // CHECK18-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
15588 // CHECK18-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
15589 // CHECK18-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
15590 // CHECK18-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
15591 // CHECK18-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
15592 // CHECK18-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
15593 // CHECK18-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
15594 // CHECK18-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
15595 // CHECK18-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
15596 // CHECK18-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8
15597 // CHECK18-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
15598 // CHECK18-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8
15599 // CHECK18-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
15600 // CHECK18-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
15601 // CHECK18-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
15602 // CHECK18-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
15603 // CHECK18-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
15604 // CHECK18-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8
15605 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15606 // CHECK18:       omp.body.continue:
15607 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15608 // CHECK18:       omp.inner.for.inc:
15609 // CHECK18-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15610 // CHECK18-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
15611 // CHECK18-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
15612 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]]
15613 // CHECK18:       omp.inner.for.end:
15614 // CHECK18-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
15615 // CHECK18:       omp.dispatch.inc:
15616 // CHECK18-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15617 // CHECK18-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
15618 // CHECK18-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
15619 // CHECK18-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
15620 // CHECK18-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15621 // CHECK18-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
15622 // CHECK18-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
15623 // CHECK18-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
15624 // CHECK18-NEXT:    br label [[OMP_DISPATCH_COND]]
15625 // CHECK18:       omp.dispatch.end:
15626 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
15627 // CHECK18-NEXT:    ret void
15628 //
15629 //
15630 // CHECK18-LABEL: define {{[^@]+}}@_Z3bari
15631 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
15632 // CHECK18-NEXT:  entry:
15633 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15634 // CHECK18-NEXT:    [[A:%.*]] = alloca i32, align 4
15635 // CHECK18-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
15636 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15637 // CHECK18-NEXT:    store i32 0, i32* [[A]], align 4
15638 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
15639 // CHECK18-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
15640 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
15641 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
15642 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
15643 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
15644 // CHECK18-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
15645 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
15646 // CHECK18-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
15647 // CHECK18-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
15648 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
15649 // CHECK18-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
15650 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
15651 // CHECK18-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
15652 // CHECK18-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
15653 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
15654 // CHECK18-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
15655 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
15656 // CHECK18-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
15657 // CHECK18-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
15658 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
15659 // CHECK18-NEXT:    ret i32 [[TMP8]]
15660 //
15661 //
15662 // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
15663 // CHECK18-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
15664 // CHECK18-NEXT:  entry:
15665 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
15666 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15667 // CHECK18-NEXT:    [[B:%.*]] = alloca i32, align 4
15668 // CHECK18-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
15669 // CHECK18-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
15670 // CHECK18-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
15671 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
15672 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
15673 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
15674 // CHECK18-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
15675 // CHECK18-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
15676 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15677 // CHECK18-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
15678 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
15679 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
15680 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
15681 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
15682 // CHECK18-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
15683 // CHECK18-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
15684 // CHECK18-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
15685 // CHECK18-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
15686 // CHECK18-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
15687 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
15688 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
15689 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
15690 // CHECK18-NEXT:    store i32 [[TMP5]], i32* [[CONV]], align 4
15691 // CHECK18-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
15692 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
15693 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
15694 // CHECK18-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
15695 // CHECK18:       omp_if.then:
15696 // CHECK18-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
15697 // CHECK18-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
15698 // CHECK18-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
15699 // CHECK18-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
15700 // CHECK18-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
15701 // CHECK18-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
15702 // CHECK18-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
15703 // CHECK18-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
15704 // CHECK18-NEXT:    store double* [[A]], double** [[TMP13]], align 8
15705 // CHECK18-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
15706 // CHECK18-NEXT:    store i64 8, i64* [[TMP14]], align 8
15707 // CHECK18-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
15708 // CHECK18-NEXT:    store i8* null, i8** [[TMP15]], align 8
15709 // CHECK18-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
15710 // CHECK18-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
15711 // CHECK18-NEXT:    store i64 [[TMP6]], i64* [[TMP17]], align 8
15712 // CHECK18-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
15713 // CHECK18-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
15714 // CHECK18-NEXT:    store i64 [[TMP6]], i64* [[TMP19]], align 8
15715 // CHECK18-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
15716 // CHECK18-NEXT:    store i64 4, i64* [[TMP20]], align 8
15717 // CHECK18-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
15718 // CHECK18-NEXT:    store i8* null, i8** [[TMP21]], align 8
15719 // CHECK18-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
15720 // CHECK18-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
15721 // CHECK18-NEXT:    store i64 2, i64* [[TMP23]], align 8
15722 // CHECK18-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
15723 // CHECK18-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
15724 // CHECK18-NEXT:    store i64 2, i64* [[TMP25]], align 8
15725 // CHECK18-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
15726 // CHECK18-NEXT:    store i64 8, i64* [[TMP26]], align 8
15727 // CHECK18-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
15728 // CHECK18-NEXT:    store i8* null, i8** [[TMP27]], align 8
15729 // CHECK18-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
15730 // CHECK18-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
15731 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[TMP29]], align 8
15732 // CHECK18-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
15733 // CHECK18-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
15734 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[TMP31]], align 8
15735 // CHECK18-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
15736 // CHECK18-NEXT:    store i64 8, i64* [[TMP32]], align 8
15737 // CHECK18-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
15738 // CHECK18-NEXT:    store i8* null, i8** [[TMP33]], align 8
15739 // CHECK18-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
15740 // CHECK18-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
15741 // CHECK18-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 8
15742 // CHECK18-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
15743 // CHECK18-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
15744 // CHECK18-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 8
15745 // CHECK18-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
15746 // CHECK18-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 8
15747 // CHECK18-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
15748 // CHECK18-NEXT:    store i8* null, i8** [[TMP39]], align 8
15749 // CHECK18-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
15750 // CHECK18-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
15751 // CHECK18-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
15752 // CHECK18-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
15753 // CHECK18-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
15754 // CHECK18-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
15755 // CHECK18:       omp_offload.failed:
15756 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
15757 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT]]
15758 // CHECK18:       omp_offload.cont:
15759 // CHECK18-NEXT:    br label [[OMP_IF_END:%.*]]
15760 // CHECK18:       omp_if.else:
15761 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
15762 // CHECK18-NEXT:    br label [[OMP_IF_END]]
15763 // CHECK18:       omp_if.end:
15764 // CHECK18-NEXT:    [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
15765 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
15766 // CHECK18-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
15767 // CHECK18-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
15768 // CHECK18-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
15769 // CHECK18-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
15770 // CHECK18-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
15771 // CHECK18-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
15772 // CHECK18-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
15773 // CHECK18-NEXT:    ret i32 [[ADD4]]
15774 //
15775 //
15776 // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici
15777 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
15778 // CHECK18-NEXT:  entry:
15779 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15780 // CHECK18-NEXT:    [[A:%.*]] = alloca i32, align 4
15781 // CHECK18-NEXT:    [[AA:%.*]] = alloca i16, align 2
15782 // CHECK18-NEXT:    [[AAA:%.*]] = alloca i8, align 1
15783 // CHECK18-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
15784 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
15785 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
15786 // CHECK18-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
15787 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
15788 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
15789 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
15790 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15791 // CHECK18-NEXT:    store i32 0, i32* [[A]], align 4
15792 // CHECK18-NEXT:    store i16 0, i16* [[AA]], align 2
15793 // CHECK18-NEXT:    store i8 0, i8* [[AAA]], align 1
15794 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
15795 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
15796 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
15797 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
15798 // CHECK18-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
15799 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
15800 // CHECK18-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
15801 // CHECK18-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
15802 // CHECK18-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
15803 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
15804 // CHECK18-NEXT:    store i8 [[TMP4]], i8* [[CONV2]], align 1
15805 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
15806 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
15807 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
15808 // CHECK18-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
15809 // CHECK18:       omp_if.then:
15810 // CHECK18-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
15811 // CHECK18-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
15812 // CHECK18-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
15813 // CHECK18-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
15814 // CHECK18-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
15815 // CHECK18-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
15816 // CHECK18-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
15817 // CHECK18-NEXT:    store i8* null, i8** [[TMP11]], align 8
15818 // CHECK18-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
15819 // CHECK18-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
15820 // CHECK18-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
15821 // CHECK18-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
15822 // CHECK18-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
15823 // CHECK18-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
15824 // CHECK18-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
15825 // CHECK18-NEXT:    store i8* null, i8** [[TMP16]], align 8
15826 // CHECK18-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
15827 // CHECK18-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
15828 // CHECK18-NEXT:    store i64 [[TMP5]], i64* [[TMP18]], align 8
15829 // CHECK18-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
15830 // CHECK18-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
15831 // CHECK18-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
15832 // CHECK18-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
15833 // CHECK18-NEXT:    store i8* null, i8** [[TMP21]], align 8
15834 // CHECK18-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
15835 // CHECK18-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
15836 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
15837 // CHECK18-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
15838 // CHECK18-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
15839 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
15840 // CHECK18-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
15841 // CHECK18-NEXT:    store i8* null, i8** [[TMP26]], align 8
15842 // CHECK18-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
15843 // CHECK18-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
15844 // CHECK18-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
15845 // CHECK18-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
15846 // CHECK18-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
15847 // CHECK18:       omp_offload.failed:
15848 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
15849 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT]]
15850 // CHECK18:       omp_offload.cont:
15851 // CHECK18-NEXT:    br label [[OMP_IF_END:%.*]]
15852 // CHECK18:       omp_if.else:
15853 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
15854 // CHECK18-NEXT:    br label [[OMP_IF_END]]
15855 // CHECK18:       omp_if.end:
15856 // CHECK18-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
15857 // CHECK18-NEXT:    ret i32 [[TMP31]]
15858 //
15859 //
15860 // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
15861 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
15862 // CHECK18-NEXT:  entry:
15863 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15864 // CHECK18-NEXT:    [[A:%.*]] = alloca i32, align 4
15865 // CHECK18-NEXT:    [[AA:%.*]] = alloca i16, align 2
15866 // CHECK18-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
15867 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
15868 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
15869 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
15870 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
15871 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
15872 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15873 // CHECK18-NEXT:    store i32 0, i32* [[A]], align 4
15874 // CHECK18-NEXT:    store i16 0, i16* [[AA]], align 2
15875 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
15876 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
15877 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
15878 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
15879 // CHECK18-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
15880 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
15881 // CHECK18-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
15882 // CHECK18-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
15883 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
15884 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
15885 // CHECK18-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
15886 // CHECK18:       omp_if.then:
15887 // CHECK18-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
15888 // CHECK18-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
15889 // CHECK18-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
15890 // CHECK18-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
15891 // CHECK18-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
15892 // CHECK18-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
15893 // CHECK18-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
15894 // CHECK18-NEXT:    store i8* null, i8** [[TMP9]], align 8
15895 // CHECK18-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
15896 // CHECK18-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
15897 // CHECK18-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
15898 // CHECK18-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
15899 // CHECK18-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
15900 // CHECK18-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
15901 // CHECK18-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
15902 // CHECK18-NEXT:    store i8* null, i8** [[TMP14]], align 8
15903 // CHECK18-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
15904 // CHECK18-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
15905 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
15906 // CHECK18-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
15907 // CHECK18-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
15908 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
15909 // CHECK18-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
15910 // CHECK18-NEXT:    store i8* null, i8** [[TMP19]], align 8
15911 // CHECK18-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
15912 // CHECK18-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
15913 // CHECK18-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
15914 // CHECK18-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
15915 // CHECK18-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
15916 // CHECK18:       omp_offload.failed:
15917 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
15918 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT]]
15919 // CHECK18:       omp_offload.cont:
15920 // CHECK18-NEXT:    br label [[OMP_IF_END:%.*]]
15921 // CHECK18:       omp_if.else:
15922 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
15923 // CHECK18-NEXT:    br label [[OMP_IF_END]]
15924 // CHECK18:       omp_if.end:
15925 // CHECK18-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
15926 // CHECK18-NEXT:    ret i32 [[TMP24]]
15927 //
15928 //
15929 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
15930 // CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
15931 // CHECK18-NEXT:  entry:
15932 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
15933 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
15934 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
15935 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
15936 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
15937 // CHECK18-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
15938 // CHECK18-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
15939 // CHECK18-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
15940 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
15941 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
15942 // CHECK18-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
15943 // CHECK18-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
15944 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
15945 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
15946 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
15947 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
15948 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
15949 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
15950 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
15951 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
15952 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
15953 // CHECK18-NEXT:    ret void
15954 //
15955 //
15956 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9
15957 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
15958 // CHECK18-NEXT:  entry:
15959 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
15960 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
15961 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
15962 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
15963 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
15964 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
15965 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
15966 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
15967 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i64, align 8
15968 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
15969 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
15970 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
15971 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
15972 // CHECK18-NEXT:    [[IT:%.*]] = alloca i64, align 8
15973 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
15974 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
15975 // CHECK18-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
15976 // CHECK18-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
15977 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
15978 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
15979 // CHECK18-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
15980 // CHECK18-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
15981 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
15982 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
15983 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
15984 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
15985 // CHECK18-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
15986 // CHECK18-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
15987 // CHECK18-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
15988 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
15989 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
15990 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
15991 // CHECK18-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
15992 // CHECK18-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
15993 // CHECK18-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
15994 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
15995 // CHECK18:       cond.true:
15996 // CHECK18-NEXT:    br label [[COND_END:%.*]]
15997 // CHECK18:       cond.false:
15998 // CHECK18-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
15999 // CHECK18-NEXT:    br label [[COND_END]]
16000 // CHECK18:       cond.end:
16001 // CHECK18-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
16002 // CHECK18-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
16003 // CHECK18-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
16004 // CHECK18-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
16005 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16006 // CHECK18:       omp.inner.for.cond:
16007 // CHECK18-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
16008 // CHECK18-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
16009 // CHECK18-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
16010 // CHECK18-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16011 // CHECK18:       omp.inner.for.body:
16012 // CHECK18-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
16013 // CHECK18-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
16014 // CHECK18-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
16015 // CHECK18-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
16016 // CHECK18-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
16017 // CHECK18-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
16018 // CHECK18-NEXT:    [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
16019 // CHECK18-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
16020 // CHECK18-NEXT:    store double [[ADD]], double* [[A]], align 8
16021 // CHECK18-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
16022 // CHECK18-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 8
16023 // CHECK18-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
16024 // CHECK18-NEXT:    store double [[INC]], double* [[A5]], align 8
16025 // CHECK18-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
16026 // CHECK18-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
16027 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
16028 // CHECK18-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
16029 // CHECK18-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
16030 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16031 // CHECK18:       omp.body.continue:
16032 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16033 // CHECK18:       omp.inner.for.inc:
16034 // CHECK18-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
16035 // CHECK18-NEXT:    [[ADD8:%.*]] = add i64 [[TMP15]], 1
16036 // CHECK18-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
16037 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]]
16038 // CHECK18:       omp.inner.for.end:
16039 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
16040 // CHECK18:       omp.loop.exit:
16041 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
16042 // CHECK18-NEXT:    ret void
16043 //
16044 //
16045 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
16046 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
16047 // CHECK18-NEXT:  entry:
16048 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
16049 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
16050 // CHECK18-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
16051 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
16052 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
16053 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
16054 // CHECK18-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
16055 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
16056 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
16057 // CHECK18-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
16058 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
16059 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
16060 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
16061 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
16062 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
16063 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
16064 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
16065 // CHECK18-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
16066 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
16067 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
16068 // CHECK18-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
16069 // CHECK18-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
16070 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
16071 // CHECK18-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
16072 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
16073 // CHECK18-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
16074 // CHECK18-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
16075 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
16076 // CHECK18-NEXT:    ret void
16077 //
16078 //
16079 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11
16080 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
16081 // CHECK18-NEXT:  entry:
16082 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
16083 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
16084 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
16085 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
16086 // CHECK18-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
16087 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
16088 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
16089 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16090 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
16091 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
16092 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
16093 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
16094 // CHECK18-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
16095 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
16096 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
16097 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
16098 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
16099 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
16100 // CHECK18-NEXT:    ret void
16101 //
16102 //
16103 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
16104 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
16105 // CHECK18-NEXT:  entry:
16106 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
16107 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
16108 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
16109 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
16110 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
16111 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
16112 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
16113 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
16114 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
16115 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
16116 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
16117 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
16118 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
16119 // CHECK18-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
16120 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
16121 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
16122 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
16123 // CHECK18-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
16124 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
16125 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
16126 // CHECK18-NEXT:    ret void
16127 //
16128 //
16129 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..14
16130 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
16131 // CHECK18-NEXT:  entry:
16132 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
16133 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
16134 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
16135 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
16136 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
16137 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
16138 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i64, align 8
16139 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
16140 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
16141 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
16142 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
16143 // CHECK18-NEXT:    [[I:%.*]] = alloca i64, align 8
16144 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
16145 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
16146 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
16147 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
16148 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
16149 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
16150 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
16151 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
16152 // CHECK18-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
16153 // CHECK18-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
16154 // CHECK18-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
16155 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
16156 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
16157 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
16158 // CHECK18-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
16159 // CHECK18-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
16160 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
16161 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
16162 // CHECK18:       cond.true:
16163 // CHECK18-NEXT:    br label [[COND_END:%.*]]
16164 // CHECK18:       cond.false:
16165 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
16166 // CHECK18-NEXT:    br label [[COND_END]]
16167 // CHECK18:       cond.end:
16168 // CHECK18-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
16169 // CHECK18-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
16170 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
16171 // CHECK18-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
16172 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16173 // CHECK18:       omp.inner.for.cond:
16174 // CHECK18-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
16175 // CHECK18-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
16176 // CHECK18-NEXT:    [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
16177 // CHECK18-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16178 // CHECK18:       omp.inner.for.body:
16179 // CHECK18-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
16180 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
16181 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
16182 // CHECK18-NEXT:    store i64 [[ADD]], i64* [[I]], align 8
16183 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
16184 // CHECK18-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
16185 // CHECK18-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
16186 // CHECK18-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
16187 // CHECK18-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
16188 // CHECK18-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
16189 // CHECK18-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
16190 // CHECK18-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
16191 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
16192 // CHECK18-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
16193 // CHECK18-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
16194 // CHECK18-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
16195 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16196 // CHECK18:       omp.body.continue:
16197 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16198 // CHECK18:       omp.inner.for.inc:
16199 // CHECK18-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
16200 // CHECK18-NEXT:    [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
16201 // CHECK18-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
16202 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]]
16203 // CHECK18:       omp.inner.for.end:
16204 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
16205 // CHECK18:       omp.loop.exit:
16206 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
16207 // CHECK18-NEXT:    ret void
16208 //
16209 //
16210 // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
16211 // CHECK18-SAME: () #[[ATTR5]] {
16212 // CHECK18-NEXT:  entry:
16213 // CHECK18-NEXT:    call void @__tgt_register_requires(i64 1)
16214 // CHECK18-NEXT:    ret void
16215 //
16216 //
16217 // CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv
16218 // CHECK19-SAME: () #[[ATTR0:[0-9]+]] {
16219 // CHECK19-NEXT:  entry:
16220 // CHECK19-NEXT:    ret i64 0
16221 //
16222 //
16223 // CHECK19-LABEL: define {{[^@]+}}@_Z3fooi
16224 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
16225 // CHECK19-NEXT:  entry:
16226 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16227 // CHECK19-NEXT:    [[A:%.*]] = alloca i32, align 4
16228 // CHECK19-NEXT:    [[AA:%.*]] = alloca i16, align 2
16229 // CHECK19-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
16230 // CHECK19-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
16231 // CHECK19-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
16232 // CHECK19-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
16233 // CHECK19-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
16234 // CHECK19-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
16235 // CHECK19-NEXT:    [[K:%.*]] = alloca i64, align 8
16236 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
16237 // CHECK19-NEXT:    [[LIN:%.*]] = alloca i32, align 4
16238 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
16239 // CHECK19-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
16240 // CHECK19-NEXT:    [[A_CASTED2:%.*]] = alloca i32, align 4
16241 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
16242 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
16243 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
16244 // CHECK19-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
16245 // CHECK19-NEXT:    [[A_CASTED3:%.*]] = alloca i32, align 4
16246 // CHECK19-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
16247 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4
16248 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4
16249 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4
16250 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
16251 // CHECK19-NEXT:    [[A_CASTED11:%.*]] = alloca i32, align 4
16252 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
16253 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4
16254 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4
16255 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4
16256 // CHECK19-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
16257 // CHECK19-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
16258 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16259 // CHECK19-NEXT:    store i32 0, i32* [[A]], align 4
16260 // CHECK19-NEXT:    store i16 0, i16* [[AA]], align 2
16261 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
16262 // CHECK19-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
16263 // CHECK19-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
16264 // CHECK19-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
16265 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
16266 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
16267 // CHECK19-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
16268 // CHECK19-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
16269 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
16270 // CHECK19-NEXT:    [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
16271 // CHECK19-NEXT:    [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
16272 // CHECK19-NEXT:    br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
16273 // CHECK19:       omp_offload.failed:
16274 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]]
16275 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
16276 // CHECK19:       omp_offload.cont:
16277 // CHECK19-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
16278 // CHECK19-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
16279 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
16280 // CHECK19-NEXT:    store i32 [[TMP7]], i32* [[A_CASTED]], align 4
16281 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4
16282 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR3]]
16283 // CHECK19-NEXT:    store i32 12, i32* [[LIN]], align 4
16284 // CHECK19-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
16285 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
16286 // CHECK19-NEXT:    store i16 [[TMP9]], i16* [[CONV]], align 2
16287 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4
16288 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4
16289 // CHECK19-NEXT:    store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4
16290 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
16291 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4
16292 // CHECK19-NEXT:    store i32 [[TMP13]], i32* [[A_CASTED2]], align 4
16293 // CHECK19-NEXT:    [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4
16294 // CHECK19-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
16295 // CHECK19-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
16296 // CHECK19-NEXT:    store i32 [[TMP10]], i32* [[TMP16]], align 4
16297 // CHECK19-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
16298 // CHECK19-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
16299 // CHECK19-NEXT:    store i32 [[TMP10]], i32* [[TMP18]], align 4
16300 // CHECK19-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
16301 // CHECK19-NEXT:    store i8* null, i8** [[TMP19]], align 4
16302 // CHECK19-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
16303 // CHECK19-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
16304 // CHECK19-NEXT:    store i32 [[TMP12]], i32* [[TMP21]], align 4
16305 // CHECK19-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
16306 // CHECK19-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
16307 // CHECK19-NEXT:    store i32 [[TMP12]], i32* [[TMP23]], align 4
16308 // CHECK19-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
16309 // CHECK19-NEXT:    store i8* null, i8** [[TMP24]], align 4
16310 // CHECK19-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
16311 // CHECK19-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
16312 // CHECK19-NEXT:    store i32 [[TMP14]], i32* [[TMP26]], align 4
16313 // CHECK19-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
16314 // CHECK19-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
16315 // CHECK19-NEXT:    store i32 [[TMP14]], i32* [[TMP28]], align 4
16316 // CHECK19-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
16317 // CHECK19-NEXT:    store i8* null, i8** [[TMP29]], align 4
16318 // CHECK19-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
16319 // CHECK19-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
16320 // CHECK19-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
16321 // CHECK19-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
16322 // CHECK19-NEXT:    store i16 [[TMP33]], i16* [[TMP32]], align 4
16323 // CHECK19-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
16324 // CHECK19-NEXT:    [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4
16325 // CHECK19-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
16326 // CHECK19-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
16327 // CHECK19-NEXT:    [[TMP37:%.*]] = load i32, i32* [[A]], align 4
16328 // CHECK19-NEXT:    store i32 [[TMP37]], i32* [[TMP36]], align 4
16329 // CHECK19-NEXT:    [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
16330 // CHECK19-NEXT:    [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
16331 // CHECK19-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
16332 // CHECK19-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
16333 // CHECK19-NEXT:    [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4
16334 // CHECK19-NEXT:    [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
16335 // CHECK19-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false)
16336 // CHECK19-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
16337 // CHECK19-NEXT:    [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
16338 // CHECK19-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
16339 // CHECK19-NEXT:    [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8*
16340 // CHECK19-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
16341 // CHECK19-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
16342 // CHECK19-NEXT:    [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8*
16343 // CHECK19-NEXT:    [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8*
16344 // CHECK19-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false)
16345 // CHECK19-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
16346 // CHECK19-NEXT:    [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8*
16347 // CHECK19-NEXT:    [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8*
16348 // CHECK19-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false)
16349 // CHECK19-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
16350 // CHECK19-NEXT:    [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
16351 // CHECK19-NEXT:    store i16 [[TMP55]], i16* [[TMP54]], align 4
16352 // CHECK19-NEXT:    [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]])
16353 // CHECK19-NEXT:    [[TMP57:%.*]] = load i32, i32* [[A]], align 4
16354 // CHECK19-NEXT:    store i32 [[TMP57]], i32* [[A_CASTED3]], align 4
16355 // CHECK19-NEXT:    [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4
16356 // CHECK19-NEXT:    [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
16357 // CHECK19-NEXT:    [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
16358 // CHECK19-NEXT:    store i16 [[TMP59]], i16* [[CONV5]], align 2
16359 // CHECK19-NEXT:    [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
16360 // CHECK19-NEXT:    [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4
16361 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10
16362 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
16363 // CHECK19:       omp_if.then:
16364 // CHECK19-NEXT:    [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
16365 // CHECK19-NEXT:    [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32*
16366 // CHECK19-NEXT:    store i32 [[TMP58]], i32* [[TMP63]], align 4
16367 // CHECK19-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
16368 // CHECK19-NEXT:    [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32*
16369 // CHECK19-NEXT:    store i32 [[TMP58]], i32* [[TMP65]], align 4
16370 // CHECK19-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
16371 // CHECK19-NEXT:    store i8* null, i8** [[TMP66]], align 4
16372 // CHECK19-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1
16373 // CHECK19-NEXT:    [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32*
16374 // CHECK19-NEXT:    store i32 [[TMP60]], i32* [[TMP68]], align 4
16375 // CHECK19-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1
16376 // CHECK19-NEXT:    [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32*
16377 // CHECK19-NEXT:    store i32 [[TMP60]], i32* [[TMP70]], align 4
16378 // CHECK19-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1
16379 // CHECK19-NEXT:    store i8* null, i8** [[TMP71]], align 4
16380 // CHECK19-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
16381 // CHECK19-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
16382 // CHECK19-NEXT:    [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
16383 // CHECK19-NEXT:    [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0
16384 // CHECK19-NEXT:    br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
16385 // CHECK19:       omp_offload.failed9:
16386 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR3]]
16387 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT10]]
16388 // CHECK19:       omp_offload.cont10:
16389 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
16390 // CHECK19:       omp_if.else:
16391 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR3]]
16392 // CHECK19-NEXT:    br label [[OMP_IF_END]]
16393 // CHECK19:       omp_if.end:
16394 // CHECK19-NEXT:    [[TMP76:%.*]] = load i32, i32* [[A]], align 4
16395 // CHECK19-NEXT:    store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4
16396 // CHECK19-NEXT:    [[TMP77:%.*]] = load i32, i32* [[A]], align 4
16397 // CHECK19-NEXT:    store i32 [[TMP77]], i32* [[A_CASTED11]], align 4
16398 // CHECK19-NEXT:    [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4
16399 // CHECK19-NEXT:    [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
16400 // CHECK19-NEXT:    store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
16401 // CHECK19-NEXT:    [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
16402 // CHECK19-NEXT:    [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4
16403 // CHECK19-NEXT:    [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20
16404 // CHECK19-NEXT:    br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]]
16405 // CHECK19:       omp_if.then13:
16406 // CHECK19-NEXT:    [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4
16407 // CHECK19-NEXT:    [[TMP83:%.*]] = sext i32 [[TMP82]] to i64
16408 // CHECK19-NEXT:    [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]]
16409 // CHECK19-NEXT:    [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8
16410 // CHECK19-NEXT:    [[TMP86:%.*]] = sext i32 [[TMP85]] to i64
16411 // CHECK19-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
16412 // CHECK19-NEXT:    [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32*
16413 // CHECK19-NEXT:    store i32 [[TMP78]], i32* [[TMP88]], align 4
16414 // CHECK19-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
16415 // CHECK19-NEXT:    [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32*
16416 // CHECK19-NEXT:    store i32 [[TMP78]], i32* [[TMP90]], align 4
16417 // CHECK19-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
16418 // CHECK19-NEXT:    store i64 4, i64* [[TMP91]], align 4
16419 // CHECK19-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
16420 // CHECK19-NEXT:    store i8* null, i8** [[TMP92]], align 4
16421 // CHECK19-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
16422 // CHECK19-NEXT:    [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]**
16423 // CHECK19-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4
16424 // CHECK19-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
16425 // CHECK19-NEXT:    [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]**
16426 // CHECK19-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4
16427 // CHECK19-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
16428 // CHECK19-NEXT:    store i64 40, i64* [[TMP97]], align 4
16429 // CHECK19-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
16430 // CHECK19-NEXT:    store i8* null, i8** [[TMP98]], align 4
16431 // CHECK19-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
16432 // CHECK19-NEXT:    [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i32*
16433 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP100]], align 4
16434 // CHECK19-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
16435 // CHECK19-NEXT:    [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i32*
16436 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP102]], align 4
16437 // CHECK19-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
16438 // CHECK19-NEXT:    store i64 4, i64* [[TMP103]], align 4
16439 // CHECK19-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
16440 // CHECK19-NEXT:    store i8* null, i8** [[TMP104]], align 4
16441 // CHECK19-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
16442 // CHECK19-NEXT:    [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float**
16443 // CHECK19-NEXT:    store float* [[VLA]], float** [[TMP106]], align 4
16444 // CHECK19-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
16445 // CHECK19-NEXT:    [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float**
16446 // CHECK19-NEXT:    store float* [[VLA]], float** [[TMP108]], align 4
16447 // CHECK19-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
16448 // CHECK19-NEXT:    store i64 [[TMP83]], i64* [[TMP109]], align 4
16449 // CHECK19-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
16450 // CHECK19-NEXT:    store i8* null, i8** [[TMP110]], align 4
16451 // CHECK19-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
16452 // CHECK19-NEXT:    [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]**
16453 // CHECK19-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4
16454 // CHECK19-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
16455 // CHECK19-NEXT:    [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]**
16456 // CHECK19-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 4
16457 // CHECK19-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
16458 // CHECK19-NEXT:    store i64 400, i64* [[TMP115]], align 4
16459 // CHECK19-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
16460 // CHECK19-NEXT:    store i8* null, i8** [[TMP116]], align 4
16461 // CHECK19-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
16462 // CHECK19-NEXT:    [[TMP118:%.*]] = bitcast i8** [[TMP117]] to i32*
16463 // CHECK19-NEXT:    store i32 5, i32* [[TMP118]], align 4
16464 // CHECK19-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
16465 // CHECK19-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32*
16466 // CHECK19-NEXT:    store i32 5, i32* [[TMP120]], align 4
16467 // CHECK19-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
16468 // CHECK19-NEXT:    store i64 4, i64* [[TMP121]], align 4
16469 // CHECK19-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
16470 // CHECK19-NEXT:    store i8* null, i8** [[TMP122]], align 4
16471 // CHECK19-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
16472 // CHECK19-NEXT:    [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32*
16473 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[TMP124]], align 4
16474 // CHECK19-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
16475 // CHECK19-NEXT:    [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32*
16476 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[TMP126]], align 4
16477 // CHECK19-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
16478 // CHECK19-NEXT:    store i64 4, i64* [[TMP127]], align 4
16479 // CHECK19-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
16480 // CHECK19-NEXT:    store i8* null, i8** [[TMP128]], align 4
16481 // CHECK19-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
16482 // CHECK19-NEXT:    [[TMP130:%.*]] = bitcast i8** [[TMP129]] to double**
16483 // CHECK19-NEXT:    store double* [[VLA1]], double** [[TMP130]], align 4
16484 // CHECK19-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
16485 // CHECK19-NEXT:    [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double**
16486 // CHECK19-NEXT:    store double* [[VLA1]], double** [[TMP132]], align 4
16487 // CHECK19-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
16488 // CHECK19-NEXT:    store i64 [[TMP86]], i64* [[TMP133]], align 4
16489 // CHECK19-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
16490 // CHECK19-NEXT:    store i8* null, i8** [[TMP134]], align 4
16491 // CHECK19-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
16492 // CHECK19-NEXT:    [[TMP136:%.*]] = bitcast i8** [[TMP135]] to %struct.TT**
16493 // CHECK19-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP136]], align 4
16494 // CHECK19-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
16495 // CHECK19-NEXT:    [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT**
16496 // CHECK19-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 4
16497 // CHECK19-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
16498 // CHECK19-NEXT:    store i64 12, i64* [[TMP139]], align 4
16499 // CHECK19-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
16500 // CHECK19-NEXT:    store i8* null, i8** [[TMP140]], align 4
16501 // CHECK19-NEXT:    [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
16502 // CHECK19-NEXT:    [[TMP142:%.*]] = bitcast i8** [[TMP141]] to i32*
16503 // CHECK19-NEXT:    store i32 [[TMP80]], i32* [[TMP142]], align 4
16504 // CHECK19-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
16505 // CHECK19-NEXT:    [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i32*
16506 // CHECK19-NEXT:    store i32 [[TMP80]], i32* [[TMP144]], align 4
16507 // CHECK19-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
16508 // CHECK19-NEXT:    store i64 4, i64* [[TMP145]], align 4
16509 // CHECK19-NEXT:    [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
16510 // CHECK19-NEXT:    store i8* null, i8** [[TMP146]], align 4
16511 // CHECK19-NEXT:    [[TMP147:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
16512 // CHECK19-NEXT:    [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
16513 // CHECK19-NEXT:    [[TMP149:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
16514 // CHECK19-NEXT:    [[TMP150:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP147]], i8** [[TMP148]], i64* [[TMP149]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
16515 // CHECK19-NEXT:    [[TMP151:%.*]] = icmp ne i32 [[TMP150]], 0
16516 // CHECK19-NEXT:    br i1 [[TMP151]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
16517 // CHECK19:       omp_offload.failed17:
16518 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR3]]
16519 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT18]]
16520 // CHECK19:       omp_offload.cont18:
16521 // CHECK19-NEXT:    br label [[OMP_IF_END20:%.*]]
16522 // CHECK19:       omp_if.else19:
16523 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR3]]
16524 // CHECK19-NEXT:    br label [[OMP_IF_END20]]
16525 // CHECK19:       omp_if.end20:
16526 // CHECK19-NEXT:    [[TMP152:%.*]] = load i32, i32* [[A]], align 4
16527 // CHECK19-NEXT:    [[TMP153:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
16528 // CHECK19-NEXT:    call void @llvm.stackrestore(i8* [[TMP153]])
16529 // CHECK19-NEXT:    ret i32 [[TMP152]]
16530 //
16531 //
16532 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
16533 // CHECK19-SAME: () #[[ATTR2:[0-9]+]] {
16534 // CHECK19-NEXT:  entry:
16535 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
16536 // CHECK19-NEXT:    ret void
16537 //
16538 //
16539 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
16540 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
16541 // CHECK19-NEXT:  entry:
16542 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
16543 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
16544 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
16545 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16546 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
16547 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
16548 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
16549 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
16550 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
16551 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
16552 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
16553 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
16554 // CHECK19-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
16555 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
16556 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
16557 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
16558 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
16559 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
16560 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
16561 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
16562 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
16563 // CHECK19:       cond.true:
16564 // CHECK19-NEXT:    br label [[COND_END:%.*]]
16565 // CHECK19:       cond.false:
16566 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
16567 // CHECK19-NEXT:    br label [[COND_END]]
16568 // CHECK19:       cond.end:
16569 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
16570 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
16571 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16572 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
16573 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16574 // CHECK19:       omp.inner.for.cond:
16575 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16576 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
16577 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
16578 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16579 // CHECK19:       omp.inner.for.body:
16580 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16581 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
16582 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
16583 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
16584 // CHECK19-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
16585 // CHECK19-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
16586 // CHECK19-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
16587 // CHECK19:       .cancel.exit:
16588 // CHECK19-NEXT:    br label [[CANCEL_EXIT:%.*]]
16589 // CHECK19:       .cancel.continue:
16590 // CHECK19-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
16591 // CHECK19-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
16592 // CHECK19-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
16593 // CHECK19:       .cancel.exit2:
16594 // CHECK19-NEXT:    br label [[CANCEL_EXIT]]
16595 // CHECK19:       .cancel.continue3:
16596 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16597 // CHECK19:       omp.body.continue:
16598 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16599 // CHECK19:       omp.inner.for.inc:
16600 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16601 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
16602 // CHECK19-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
16603 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
16604 // CHECK19:       omp.inner.for.end:
16605 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
16606 // CHECK19:       omp.loop.exit:
16607 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
16608 // CHECK19-NEXT:    br label [[CANCEL_CONT:%.*]]
16609 // CHECK19:       cancel.cont:
16610 // CHECK19-NEXT:    ret void
16611 // CHECK19:       cancel.exit:
16612 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
16613 // CHECK19-NEXT:    br label [[CANCEL_CONT]]
16614 //
16615 //
16616 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
16617 // CHECK19-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {
16618 // CHECK19-NEXT:  entry:
16619 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
16620 // CHECK19-NEXT:    [[K_ADDR:%.*]] = alloca i64*, align 4
16621 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
16622 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
16623 // CHECK19-NEXT:    store i64* [[K]], i64** [[K_ADDR]], align 4
16624 // CHECK19-NEXT:    [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
16625 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
16626 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
16627 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
16628 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]])
16629 // CHECK19-NEXT:    ret void
16630 //
16631 //
16632 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1
16633 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {
16634 // CHECK19-NEXT:  entry:
16635 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
16636 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
16637 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
16638 // CHECK19-NEXT:    [[K_ADDR:%.*]] = alloca i64*, align 4
16639 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
16640 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16641 // CHECK19-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
16642 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
16643 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
16644 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
16645 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
16646 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
16647 // CHECK19-NEXT:    [[K1:%.*]] = alloca i64, align 8
16648 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
16649 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
16650 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
16651 // CHECK19-NEXT:    store i64* [[K]], i64** [[K_ADDR]], align 4
16652 // CHECK19-NEXT:    [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
16653 // CHECK19-NEXT:    [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8
16654 // CHECK19-NEXT:    store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8
16655 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
16656 // CHECK19-NEXT:    store i32 8, i32* [[DOTOMP_UB]], align 4
16657 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
16658 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
16659 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
16660 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
16661 // CHECK19-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
16662 // CHECK19-NEXT:    call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
16663 // CHECK19-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
16664 // CHECK19:       omp.dispatch.cond:
16665 // CHECK19-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
16666 // CHECK19-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
16667 // CHECK19-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
16668 // CHECK19:       omp.dispatch.body:
16669 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16670 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
16671 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16672 // CHECK19:       omp.inner.for.cond:
16673 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
16674 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
16675 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
16676 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16677 // CHECK19:       omp.inner.for.body:
16678 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
16679 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
16680 // CHECK19-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
16681 // CHECK19-NEXT:    store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12
16682 // CHECK19-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12
16683 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
16684 // CHECK19-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
16685 // CHECK19-NEXT:    [[CONV:%.*]] = sext i32 [[MUL2]] to i64
16686 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
16687 // CHECK19-NEXT:    store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
16688 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12
16689 // CHECK19-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
16690 // CHECK19-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !12
16691 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16692 // CHECK19:       omp.body.continue:
16693 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16694 // CHECK19:       omp.inner.for.inc:
16695 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
16696 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
16697 // CHECK19-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
16698 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
16699 // CHECK19:       omp.inner.for.end:
16700 // CHECK19-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
16701 // CHECK19:       omp.dispatch.inc:
16702 // CHECK19-NEXT:    br label [[OMP_DISPATCH_COND]]
16703 // CHECK19:       omp.dispatch.end:
16704 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
16705 // CHECK19-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
16706 // CHECK19-NEXT:    br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
16707 // CHECK19:       .omp.linear.pu:
16708 // CHECK19-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
16709 // CHECK19-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP15]], 27
16710 // CHECK19-NEXT:    store i64 [[ADD5]], i64* [[TMP0]], align 8
16711 // CHECK19-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
16712 // CHECK19:       .omp.linear.pu.done:
16713 // CHECK19-NEXT:    ret void
16714 //
16715 //
16716 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
16717 // CHECK19-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
16718 // CHECK19-NEXT:  entry:
16719 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
16720 // CHECK19-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
16721 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
16722 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
16723 // CHECK19-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
16724 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
16725 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
16726 // CHECK19-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
16727 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
16728 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
16729 // CHECK19-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
16730 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
16731 // CHECK19-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
16732 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
16733 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
16734 // CHECK19-NEXT:    store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
16735 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
16736 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
16737 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[A_CASTED]], align 4
16738 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
16739 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
16740 // CHECK19-NEXT:    ret void
16741 //
16742 //
16743 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2
16744 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
16745 // CHECK19-NEXT:  entry:
16746 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
16747 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
16748 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
16749 // CHECK19-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
16750 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
16751 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
16752 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i64, align 4
16753 // CHECK19-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
16754 // CHECK19-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
16755 // CHECK19-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
16756 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
16757 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
16758 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
16759 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
16760 // CHECK19-NEXT:    [[IT:%.*]] = alloca i64, align 8
16761 // CHECK19-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
16762 // CHECK19-NEXT:    [[A3:%.*]] = alloca i32, align 4
16763 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
16764 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
16765 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
16766 // CHECK19-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
16767 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
16768 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
16769 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
16770 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
16771 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
16772 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
16773 // CHECK19-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
16774 // CHECK19-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
16775 // CHECK19-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
16776 // CHECK19-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
16777 // CHECK19-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
16778 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
16779 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
16780 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
16781 // CHECK19-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
16782 // CHECK19-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
16783 // CHECK19-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
16784 // CHECK19-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
16785 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
16786 // CHECK19:       cond.true:
16787 // CHECK19-NEXT:    br label [[COND_END:%.*]]
16788 // CHECK19:       cond.false:
16789 // CHECK19-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
16790 // CHECK19-NEXT:    br label [[COND_END]]
16791 // CHECK19:       cond.end:
16792 // CHECK19-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
16793 // CHECK19-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
16794 // CHECK19-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
16795 // CHECK19-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
16796 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16797 // CHECK19:       omp.inner.for.cond:
16798 // CHECK19-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
16799 // CHECK19-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
16800 // CHECK19-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
16801 // CHECK19-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16802 // CHECK19:       omp.inner.for.body:
16803 // CHECK19-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
16804 // CHECK19-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
16805 // CHECK19-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
16806 // CHECK19-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
16807 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
16808 // CHECK19-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
16809 // CHECK19-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
16810 // CHECK19-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
16811 // CHECK19-NEXT:    [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
16812 // CHECK19-NEXT:    [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
16813 // CHECK19-NEXT:    [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
16814 // CHECK19-NEXT:    store i32 [[CONV7]], i32* [[LIN2]], align 4
16815 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
16816 // CHECK19-NEXT:    [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
16817 // CHECK19-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
16818 // CHECK19-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
16819 // CHECK19-NEXT:    [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
16820 // CHECK19-NEXT:    [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
16821 // CHECK19-NEXT:    [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
16822 // CHECK19-NEXT:    store i32 [[CONV11]], i32* [[A3]], align 4
16823 // CHECK19-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4
16824 // CHECK19-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
16825 // CHECK19-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
16826 // CHECK19-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
16827 // CHECK19-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4
16828 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16829 // CHECK19:       omp.body.continue:
16830 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16831 // CHECK19:       omp.inner.for.inc:
16832 // CHECK19-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
16833 // CHECK19-NEXT:    [[ADD15:%.*]] = add i64 [[TMP17]], 1
16834 // CHECK19-NEXT:    store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
16835 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
16836 // CHECK19:       omp.inner.for.end:
16837 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
16838 // CHECK19:       omp.loop.exit:
16839 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
16840 // CHECK19-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
16841 // CHECK19-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
16842 // CHECK19-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
16843 // CHECK19:       .omp.linear.pu:
16844 // CHECK19-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
16845 // CHECK19-NEXT:    [[CONV16:%.*]] = sext i32 [[TMP20]] to i64
16846 // CHECK19-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
16847 // CHECK19-NEXT:    [[MUL17:%.*]] = mul i64 4, [[TMP21]]
16848 // CHECK19-NEXT:    [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
16849 // CHECK19-NEXT:    [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
16850 // CHECK19-NEXT:    store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
16851 // CHECK19-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
16852 // CHECK19-NEXT:    [[CONV20:%.*]] = sext i32 [[TMP22]] to i64
16853 // CHECK19-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
16854 // CHECK19-NEXT:    [[MUL21:%.*]] = mul i64 4, [[TMP23]]
16855 // CHECK19-NEXT:    [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
16856 // CHECK19-NEXT:    [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
16857 // CHECK19-NEXT:    store i32 [[CONV23]], i32* [[A_ADDR]], align 4
16858 // CHECK19-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
16859 // CHECK19:       .omp.linear.pu.done:
16860 // CHECK19-NEXT:    ret void
16861 //
16862 //
16863 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map.
16864 // CHECK19-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
16865 // CHECK19-NEXT:  entry:
16866 // CHECK19-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
16867 // CHECK19-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 4
16868 // CHECK19-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
16869 // CHECK19-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
16870 // CHECK19-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
16871 // CHECK19-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
16872 // CHECK19-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
16873 // CHECK19-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
16874 // CHECK19-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
16875 // CHECK19-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
16876 // CHECK19-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
16877 // CHECK19-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
16878 // CHECK19-NEXT:    [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
16879 // CHECK19-NEXT:    store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
16880 // CHECK19-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
16881 // CHECK19-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
16882 // CHECK19-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
16883 // CHECK19-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
16884 // CHECK19-NEXT:    [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
16885 // CHECK19-NEXT:    store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
16886 // CHECK19-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
16887 // CHECK19-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
16888 // CHECK19-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 4
16889 // CHECK19-NEXT:    ret void
16890 //
16891 //
16892 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry.
16893 // CHECK19-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
16894 // CHECK19-NEXT:  entry:
16895 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
16896 // CHECK19-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
16897 // CHECK19-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
16898 // CHECK19-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
16899 // CHECK19-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
16900 // CHECK19-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
16901 // CHECK19-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
16902 // CHECK19-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
16903 // CHECK19-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
16904 // CHECK19-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
16905 // CHECK19-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
16906 // CHECK19-NEXT:    [[LIN_CASTED_I:%.*]] = alloca i32, align 4
16907 // CHECK19-NEXT:    [[A_CASTED_I:%.*]] = alloca i32, align 4
16908 // CHECK19-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
16909 // CHECK19-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
16910 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
16911 // CHECK19-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
16912 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
16913 // CHECK19-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
16914 // CHECK19-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
16915 // CHECK19-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
16916 // CHECK19-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
16917 // CHECK19-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
16918 // CHECK19-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
16919 // CHECK19-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
16920 // CHECK19-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
16921 // CHECK19-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
16922 // CHECK19-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
16923 // CHECK19-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
16924 // CHECK19-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
16925 // CHECK19-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
16926 // CHECK19-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
16927 // CHECK19-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24
16928 // CHECK19-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24
16929 // CHECK19-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24
16930 // CHECK19-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24
16931 // CHECK19-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24
16932 // CHECK19-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24
16933 // CHECK19-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24
16934 // CHECK19-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24
16935 // CHECK19-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
16936 // CHECK19-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
16937 // CHECK19-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24
16938 // CHECK19-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24
16939 // CHECK19-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24
16940 // CHECK19-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24
16941 // CHECK19-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
16942 // CHECK19-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
16943 // CHECK19-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
16944 // CHECK19-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
16945 // CHECK19-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
16946 // CHECK19-NEXT:    [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) #[[ATTR3]]
16947 // CHECK19-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
16948 // CHECK19-NEXT:    br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
16949 // CHECK19:       omp_offload.failed.i:
16950 // CHECK19-NEXT:    [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2
16951 // CHECK19-NEXT:    [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
16952 // CHECK19-NEXT:    store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24
16953 // CHECK19-NEXT:    [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !24
16954 // CHECK19-NEXT:    [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4
16955 // CHECK19-NEXT:    store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !24
16956 // CHECK19-NEXT:    [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !24
16957 // CHECK19-NEXT:    [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4
16958 // CHECK19-NEXT:    store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !24
16959 // CHECK19-NEXT:    [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !24
16960 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR3]]
16961 // CHECK19-NEXT:    br label [[DOTOMP_OUTLINED__3_EXIT]]
16962 // CHECK19:       .omp_outlined..3.exit:
16963 // CHECK19-NEXT:    ret i32 0
16964 //
16965 //
16966 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
16967 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
16968 // CHECK19-NEXT:  entry:
16969 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
16970 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
16971 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
16972 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
16973 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
16974 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
16975 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
16976 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
16977 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
16978 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
16979 // CHECK19-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
16980 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
16981 // CHECK19-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
16982 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
16983 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
16984 // CHECK19-NEXT:    ret void
16985 //
16986 //
16987 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4
16988 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
16989 // CHECK19-NEXT:  entry:
16990 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
16991 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
16992 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
16993 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
16994 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
16995 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i16, align 2
16996 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
16997 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
16998 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
16999 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
17000 // CHECK19-NEXT:    [[IT:%.*]] = alloca i16, align 2
17001 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
17002 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
17003 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
17004 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
17005 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
17006 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17007 // CHECK19-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
17008 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
17009 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
17010 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
17011 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
17012 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
17013 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17014 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
17015 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
17016 // CHECK19:       cond.true:
17017 // CHECK19-NEXT:    br label [[COND_END:%.*]]
17018 // CHECK19:       cond.false:
17019 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17020 // CHECK19-NEXT:    br label [[COND_END]]
17021 // CHECK19:       cond.end:
17022 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
17023 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
17024 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17025 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
17026 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17027 // CHECK19:       omp.inner.for.cond:
17028 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17029 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17030 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
17031 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17032 // CHECK19:       omp.inner.for.body:
17033 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17034 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
17035 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
17036 // CHECK19-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
17037 // CHECK19-NEXT:    store i16 [[CONV2]], i16* [[IT]], align 2
17038 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
17039 // CHECK19-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
17040 // CHECK19-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4
17041 // CHECK19-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
17042 // CHECK19-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
17043 // CHECK19-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
17044 // CHECK19-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
17045 // CHECK19-NEXT:    store i16 [[CONV6]], i16* [[CONV]], align 4
17046 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17047 // CHECK19:       omp.body.continue:
17048 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17049 // CHECK19:       omp.inner.for.inc:
17050 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17051 // CHECK19-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
17052 // CHECK19-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
17053 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
17054 // CHECK19:       omp.inner.for.end:
17055 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
17056 // CHECK19:       omp.loop.exit:
17057 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
17058 // CHECK19-NEXT:    ret void
17059 //
17060 //
17061 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
17062 // CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
17063 // CHECK19-NEXT:  entry:
17064 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
17065 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
17066 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
17067 // CHECK19-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
17068 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
17069 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
17070 // CHECK19-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
17071 // CHECK19-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
17072 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
17073 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
17074 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
17075 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
17076 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
17077 // CHECK19-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
17078 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
17079 // CHECK19-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
17080 // CHECK19-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
17081 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
17082 // CHECK19-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
17083 // CHECK19-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
17084 // CHECK19-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
17085 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
17086 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
17087 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
17088 // CHECK19-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
17089 // CHECK19-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
17090 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
17091 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
17092 // CHECK19-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
17093 // CHECK19-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
17094 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
17095 // CHECK19-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
17096 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
17097 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
17098 // CHECK19-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
17099 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
17100 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
17101 // CHECK19-NEXT:    ret void
17102 //
17103 //
17104 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7
17105 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
17106 // CHECK19-NEXT:  entry:
17107 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
17108 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
17109 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
17110 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
17111 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
17112 // CHECK19-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
17113 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
17114 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
17115 // CHECK19-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
17116 // CHECK19-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
17117 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
17118 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
17119 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17120 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i8, align 1
17121 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
17122 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
17123 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
17124 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
17125 // CHECK19-NEXT:    [[IT:%.*]] = alloca i8, align 1
17126 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
17127 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
17128 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
17129 // CHECK19-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
17130 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
17131 // CHECK19-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
17132 // CHECK19-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
17133 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
17134 // CHECK19-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
17135 // CHECK19-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
17136 // CHECK19-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
17137 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
17138 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
17139 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
17140 // CHECK19-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
17141 // CHECK19-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
17142 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
17143 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
17144 // CHECK19-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
17145 // CHECK19-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
17146 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17147 // CHECK19-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
17148 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
17149 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
17150 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
17151 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
17152 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
17153 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
17154 // CHECK19-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
17155 // CHECK19:       omp.dispatch.cond:
17156 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17157 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
17158 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
17159 // CHECK19:       cond.true:
17160 // CHECK19-NEXT:    br label [[COND_END:%.*]]
17161 // CHECK19:       cond.false:
17162 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17163 // CHECK19-NEXT:    br label [[COND_END]]
17164 // CHECK19:       cond.end:
17165 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
17166 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
17167 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17168 // CHECK19-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
17169 // CHECK19-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17170 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17171 // CHECK19-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
17172 // CHECK19-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
17173 // CHECK19:       omp.dispatch.body:
17174 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17175 // CHECK19:       omp.inner.for.cond:
17176 // CHECK19-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17177 // CHECK19-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17178 // CHECK19-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
17179 // CHECK19-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17180 // CHECK19:       omp.inner.for.body:
17181 // CHECK19-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17182 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
17183 // CHECK19-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
17184 // CHECK19-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
17185 // CHECK19-NEXT:    store i8 [[CONV]], i8* [[IT]], align 1
17186 // CHECK19-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
17187 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
17188 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
17189 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
17190 // CHECK19-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
17191 // CHECK19-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
17192 // CHECK19-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
17193 // CHECK19-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
17194 // CHECK19-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4
17195 // CHECK19-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
17196 // CHECK19-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
17197 // CHECK19-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
17198 // CHECK19-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
17199 // CHECK19-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
17200 // CHECK19-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4
17201 // CHECK19-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
17202 // CHECK19-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
17203 // CHECK19-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
17204 // CHECK19-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
17205 // CHECK19-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8
17206 // CHECK19-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
17207 // CHECK19-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
17208 // CHECK19-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
17209 // CHECK19-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
17210 // CHECK19-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
17211 // CHECK19-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8
17212 // CHECK19-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
17213 // CHECK19-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4
17214 // CHECK19-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
17215 // CHECK19-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4
17216 // CHECK19-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
17217 // CHECK19-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
17218 // CHECK19-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
17219 // CHECK19-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
17220 // CHECK19-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
17221 // CHECK19-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4
17222 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17223 // CHECK19:       omp.body.continue:
17224 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17225 // CHECK19:       omp.inner.for.inc:
17226 // CHECK19-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17227 // CHECK19-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
17228 // CHECK19-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
17229 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
17230 // CHECK19:       omp.inner.for.end:
17231 // CHECK19-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
17232 // CHECK19:       omp.dispatch.inc:
17233 // CHECK19-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17234 // CHECK19-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
17235 // CHECK19-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
17236 // CHECK19-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
17237 // CHECK19-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17238 // CHECK19-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
17239 // CHECK19-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
17240 // CHECK19-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
17241 // CHECK19-NEXT:    br label [[OMP_DISPATCH_COND]]
17242 // CHECK19:       omp.dispatch.end:
17243 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
17244 // CHECK19-NEXT:    ret void
17245 //
17246 //
17247 // CHECK19-LABEL: define {{[^@]+}}@_Z3bari
17248 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
17249 // CHECK19-NEXT:  entry:
17250 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17251 // CHECK19-NEXT:    [[A:%.*]] = alloca i32, align 4
17252 // CHECK19-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
17253 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17254 // CHECK19-NEXT:    store i32 0, i32* [[A]], align 4
17255 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
17256 // CHECK19-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
17257 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
17258 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
17259 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
17260 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
17261 // CHECK19-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
17262 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
17263 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
17264 // CHECK19-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
17265 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
17266 // CHECK19-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
17267 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
17268 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
17269 // CHECK19-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
17270 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
17271 // CHECK19-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
17272 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
17273 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
17274 // CHECK19-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
17275 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
17276 // CHECK19-NEXT:    ret i32 [[TMP8]]
17277 //
17278 //
17279 // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
17280 // CHECK19-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
17281 // CHECK19-NEXT:  entry:
17282 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
17283 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17284 // CHECK19-NEXT:    [[B:%.*]] = alloca i32, align 4
17285 // CHECK19-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
17286 // CHECK19-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
17287 // CHECK19-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
17288 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
17289 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
17290 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
17291 // CHECK19-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
17292 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
17293 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17294 // CHECK19-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
17295 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
17296 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
17297 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
17298 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
17299 // CHECK19-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
17300 // CHECK19-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
17301 // CHECK19-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
17302 // CHECK19-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
17303 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
17304 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
17305 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
17306 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
17307 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
17308 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
17309 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
17310 // CHECK19:       omp_if.then:
17311 // CHECK19-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
17312 // CHECK19-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
17313 // CHECK19-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
17314 // CHECK19-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
17315 // CHECK19-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
17316 // CHECK19-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
17317 // CHECK19-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
17318 // CHECK19-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
17319 // CHECK19-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
17320 // CHECK19-NEXT:    store double* [[A]], double** [[TMP13]], align 4
17321 // CHECK19-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
17322 // CHECK19-NEXT:    store i64 8, i64* [[TMP14]], align 4
17323 // CHECK19-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
17324 // CHECK19-NEXT:    store i8* null, i8** [[TMP15]], align 4
17325 // CHECK19-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
17326 // CHECK19-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
17327 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[TMP17]], align 4
17328 // CHECK19-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
17329 // CHECK19-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
17330 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[TMP19]], align 4
17331 // CHECK19-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
17332 // CHECK19-NEXT:    store i64 4, i64* [[TMP20]], align 4
17333 // CHECK19-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
17334 // CHECK19-NEXT:    store i8* null, i8** [[TMP21]], align 4
17335 // CHECK19-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
17336 // CHECK19-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
17337 // CHECK19-NEXT:    store i32 2, i32* [[TMP23]], align 4
17338 // CHECK19-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
17339 // CHECK19-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
17340 // CHECK19-NEXT:    store i32 2, i32* [[TMP25]], align 4
17341 // CHECK19-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
17342 // CHECK19-NEXT:    store i64 4, i64* [[TMP26]], align 4
17343 // CHECK19-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
17344 // CHECK19-NEXT:    store i8* null, i8** [[TMP27]], align 4
17345 // CHECK19-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
17346 // CHECK19-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
17347 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP29]], align 4
17348 // CHECK19-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
17349 // CHECK19-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
17350 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP31]], align 4
17351 // CHECK19-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
17352 // CHECK19-NEXT:    store i64 4, i64* [[TMP32]], align 4
17353 // CHECK19-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
17354 // CHECK19-NEXT:    store i8* null, i8** [[TMP33]], align 4
17355 // CHECK19-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
17356 // CHECK19-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
17357 // CHECK19-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 4
17358 // CHECK19-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
17359 // CHECK19-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
17360 // CHECK19-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 4
17361 // CHECK19-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
17362 // CHECK19-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 4
17363 // CHECK19-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
17364 // CHECK19-NEXT:    store i8* null, i8** [[TMP39]], align 4
17365 // CHECK19-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
17366 // CHECK19-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
17367 // CHECK19-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
17368 // CHECK19-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
17369 // CHECK19-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
17370 // CHECK19-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
17371 // CHECK19:       omp_offload.failed:
17372 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
17373 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
17374 // CHECK19:       omp_offload.cont:
17375 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
17376 // CHECK19:       omp_if.else:
17377 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
17378 // CHECK19-NEXT:    br label [[OMP_IF_END]]
17379 // CHECK19:       omp_if.end:
17380 // CHECK19-NEXT:    [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
17381 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
17382 // CHECK19-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
17383 // CHECK19-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
17384 // CHECK19-NEXT:    [[CONV:%.*]] = sext i16 [[TMP46]] to i32
17385 // CHECK19-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
17386 // CHECK19-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
17387 // CHECK19-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
17388 // CHECK19-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
17389 // CHECK19-NEXT:    ret i32 [[ADD3]]
17390 //
17391 //
17392 // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici
17393 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
17394 // CHECK19-NEXT:  entry:
17395 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17396 // CHECK19-NEXT:    [[A:%.*]] = alloca i32, align 4
17397 // CHECK19-NEXT:    [[AA:%.*]] = alloca i16, align 2
17398 // CHECK19-NEXT:    [[AAA:%.*]] = alloca i8, align 1
17399 // CHECK19-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
17400 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
17401 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
17402 // CHECK19-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
17403 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
17404 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
17405 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
17406 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17407 // CHECK19-NEXT:    store i32 0, i32* [[A]], align 4
17408 // CHECK19-NEXT:    store i16 0, i16* [[AA]], align 2
17409 // CHECK19-NEXT:    store i8 0, i8* [[AAA]], align 1
17410 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
17411 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
17412 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
17413 // CHECK19-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
17414 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
17415 // CHECK19-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
17416 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
17417 // CHECK19-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
17418 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
17419 // CHECK19-NEXT:    store i8 [[TMP4]], i8* [[CONV1]], align 1
17420 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
17421 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
17422 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
17423 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
17424 // CHECK19:       omp_if.then:
17425 // CHECK19-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
17426 // CHECK19-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
17427 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
17428 // CHECK19-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
17429 // CHECK19-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
17430 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
17431 // CHECK19-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
17432 // CHECK19-NEXT:    store i8* null, i8** [[TMP11]], align 4
17433 // CHECK19-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
17434 // CHECK19-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
17435 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
17436 // CHECK19-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
17437 // CHECK19-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
17438 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
17439 // CHECK19-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
17440 // CHECK19-NEXT:    store i8* null, i8** [[TMP16]], align 4
17441 // CHECK19-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
17442 // CHECK19-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
17443 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[TMP18]], align 4
17444 // CHECK19-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
17445 // CHECK19-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
17446 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
17447 // CHECK19-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
17448 // CHECK19-NEXT:    store i8* null, i8** [[TMP21]], align 4
17449 // CHECK19-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
17450 // CHECK19-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
17451 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
17452 // CHECK19-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
17453 // CHECK19-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
17454 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
17455 // CHECK19-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
17456 // CHECK19-NEXT:    store i8* null, i8** [[TMP26]], align 4
17457 // CHECK19-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
17458 // CHECK19-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
17459 // CHECK19-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
17460 // CHECK19-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
17461 // CHECK19-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
17462 // CHECK19:       omp_offload.failed:
17463 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
17464 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
17465 // CHECK19:       omp_offload.cont:
17466 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
17467 // CHECK19:       omp_if.else:
17468 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
17469 // CHECK19-NEXT:    br label [[OMP_IF_END]]
17470 // CHECK19:       omp_if.end:
17471 // CHECK19-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
17472 // CHECK19-NEXT:    ret i32 [[TMP31]]
17473 //
17474 //
17475 // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
17476 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
17477 // CHECK19-NEXT:  entry:
17478 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17479 // CHECK19-NEXT:    [[A:%.*]] = alloca i32, align 4
17480 // CHECK19-NEXT:    [[AA:%.*]] = alloca i16, align 2
17481 // CHECK19-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
17482 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
17483 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
17484 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
17485 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
17486 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
17487 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17488 // CHECK19-NEXT:    store i32 0, i32* [[A]], align 4
17489 // CHECK19-NEXT:    store i16 0, i16* [[AA]], align 2
17490 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
17491 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
17492 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
17493 // CHECK19-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
17494 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
17495 // CHECK19-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
17496 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
17497 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
17498 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
17499 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
17500 // CHECK19:       omp_if.then:
17501 // CHECK19-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
17502 // CHECK19-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
17503 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
17504 // CHECK19-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
17505 // CHECK19-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
17506 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
17507 // CHECK19-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
17508 // CHECK19-NEXT:    store i8* null, i8** [[TMP9]], align 4
17509 // CHECK19-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
17510 // CHECK19-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
17511 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
17512 // CHECK19-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
17513 // CHECK19-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
17514 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
17515 // CHECK19-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
17516 // CHECK19-NEXT:    store i8* null, i8** [[TMP14]], align 4
17517 // CHECK19-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
17518 // CHECK19-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
17519 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
17520 // CHECK19-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
17521 // CHECK19-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
17522 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
17523 // CHECK19-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
17524 // CHECK19-NEXT:    store i8* null, i8** [[TMP19]], align 4
17525 // CHECK19-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
17526 // CHECK19-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
17527 // CHECK19-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
17528 // CHECK19-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
17529 // CHECK19-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
17530 // CHECK19:       omp_offload.failed:
17531 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
17532 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
17533 // CHECK19:       omp_offload.cont:
17534 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
17535 // CHECK19:       omp_if.else:
17536 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
17537 // CHECK19-NEXT:    br label [[OMP_IF_END]]
17538 // CHECK19:       omp_if.end:
17539 // CHECK19-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
17540 // CHECK19-NEXT:    ret i32 [[TMP24]]
17541 //
17542 //
17543 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
17544 // CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
17545 // CHECK19-NEXT:  entry:
17546 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
17547 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
17548 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
17549 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
17550 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
17551 // CHECK19-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
17552 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
17553 // CHECK19-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
17554 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
17555 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
17556 // CHECK19-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
17557 // CHECK19-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
17558 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
17559 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
17560 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
17561 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
17562 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
17563 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
17564 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
17565 // CHECK19-NEXT:    ret void
17566 //
17567 //
17568 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9
17569 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
17570 // CHECK19-NEXT:  entry:
17571 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
17572 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
17573 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
17574 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
17575 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
17576 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
17577 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
17578 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
17579 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i64, align 4
17580 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
17581 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
17582 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
17583 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
17584 // CHECK19-NEXT:    [[IT:%.*]] = alloca i64, align 8
17585 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
17586 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
17587 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
17588 // CHECK19-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
17589 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
17590 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
17591 // CHECK19-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
17592 // CHECK19-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
17593 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
17594 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
17595 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
17596 // CHECK19-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
17597 // CHECK19-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
17598 // CHECK19-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
17599 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
17600 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
17601 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
17602 // CHECK19-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
17603 // CHECK19-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
17604 // CHECK19-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
17605 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
17606 // CHECK19:       cond.true:
17607 // CHECK19-NEXT:    br label [[COND_END:%.*]]
17608 // CHECK19:       cond.false:
17609 // CHECK19-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
17610 // CHECK19-NEXT:    br label [[COND_END]]
17611 // CHECK19:       cond.end:
17612 // CHECK19-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
17613 // CHECK19-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
17614 // CHECK19-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
17615 // CHECK19-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
17616 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17617 // CHECK19:       omp.inner.for.cond:
17618 // CHECK19-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
17619 // CHECK19-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
17620 // CHECK19-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
17621 // CHECK19-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17622 // CHECK19:       omp.inner.for.body:
17623 // CHECK19-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
17624 // CHECK19-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
17625 // CHECK19-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
17626 // CHECK19-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
17627 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
17628 // CHECK19-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
17629 // CHECK19-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
17630 // CHECK19-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
17631 // CHECK19-NEXT:    store double [[ADD]], double* [[A]], align 4
17632 // CHECK19-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
17633 // CHECK19-NEXT:    [[TMP13:%.*]] = load double, double* [[A4]], align 4
17634 // CHECK19-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
17635 // CHECK19-NEXT:    store double [[INC]], double* [[A4]], align 4
17636 // CHECK19-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
17637 // CHECK19-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
17638 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
17639 // CHECK19-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
17640 // CHECK19-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
17641 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17642 // CHECK19:       omp.body.continue:
17643 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17644 // CHECK19:       omp.inner.for.inc:
17645 // CHECK19-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
17646 // CHECK19-NEXT:    [[ADD7:%.*]] = add i64 [[TMP15]], 1
17647 // CHECK19-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
17648 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
17649 // CHECK19:       omp.inner.for.end:
17650 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
17651 // CHECK19:       omp.loop.exit:
17652 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
17653 // CHECK19-NEXT:    ret void
17654 //
17655 //
17656 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
17657 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
17658 // CHECK19-NEXT:  entry:
17659 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
17660 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
17661 // CHECK19-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
17662 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
17663 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
17664 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
17665 // CHECK19-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
17666 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
17667 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
17668 // CHECK19-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
17669 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
17670 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
17671 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
17672 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
17673 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
17674 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
17675 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
17676 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
17677 // CHECK19-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
17678 // CHECK19-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
17679 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
17680 // CHECK19-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
17681 // CHECK19-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
17682 // CHECK19-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
17683 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
17684 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
17685 // CHECK19-NEXT:    ret void
17686 //
17687 //
17688 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11
17689 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
17690 // CHECK19-NEXT:  entry:
17691 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
17692 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
17693 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
17694 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
17695 // CHECK19-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
17696 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
17697 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17698 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17699 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
17700 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
17701 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
17702 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
17703 // CHECK19-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
17704 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
17705 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
17706 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
17707 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
17708 // CHECK19-NEXT:    ret void
17709 //
17710 //
17711 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
17712 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
17713 // CHECK19-NEXT:  entry:
17714 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
17715 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
17716 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
17717 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
17718 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
17719 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
17720 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
17721 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
17722 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
17723 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
17724 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
17725 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
17726 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
17727 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
17728 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
17729 // CHECK19-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
17730 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
17731 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
17732 // CHECK19-NEXT:    ret void
17733 //
17734 //
17735 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..14
17736 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
17737 // CHECK19-NEXT:  entry:
17738 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
17739 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
17740 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
17741 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
17742 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
17743 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
17744 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i64, align 4
17745 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
17746 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
17747 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
17748 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
17749 // CHECK19-NEXT:    [[I:%.*]] = alloca i64, align 8
17750 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
17751 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
17752 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
17753 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
17754 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
17755 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
17756 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
17757 // CHECK19-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
17758 // CHECK19-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
17759 // CHECK19-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
17760 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
17761 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
17762 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
17763 // CHECK19-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
17764 // CHECK19-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
17765 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
17766 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
17767 // CHECK19:       cond.true:
17768 // CHECK19-NEXT:    br label [[COND_END:%.*]]
17769 // CHECK19:       cond.false:
17770 // CHECK19-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
17771 // CHECK19-NEXT:    br label [[COND_END]]
17772 // CHECK19:       cond.end:
17773 // CHECK19-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
17774 // CHECK19-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
17775 // CHECK19-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
17776 // CHECK19-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
17777 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17778 // CHECK19:       omp.inner.for.cond:
17779 // CHECK19-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
17780 // CHECK19-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
17781 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
17782 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17783 // CHECK19:       omp.inner.for.body:
17784 // CHECK19-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
17785 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
17786 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
17787 // CHECK19-NEXT:    store i64 [[ADD]], i64* [[I]], align 8
17788 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
17789 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
17790 // CHECK19-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
17791 // CHECK19-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
17792 // CHECK19-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
17793 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
17794 // CHECK19-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
17795 // CHECK19-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
17796 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
17797 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
17798 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
17799 // CHECK19-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
17800 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17801 // CHECK19:       omp.body.continue:
17802 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17803 // CHECK19:       omp.inner.for.inc:
17804 // CHECK19-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
17805 // CHECK19-NEXT:    [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
17806 // CHECK19-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
17807 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
17808 // CHECK19:       omp.inner.for.end:
17809 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
17810 // CHECK19:       omp.loop.exit:
17811 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
17812 // CHECK19-NEXT:    ret void
17813 //
17814 //
17815 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
17816 // CHECK19-SAME: () #[[ATTR5]] {
17817 // CHECK19-NEXT:  entry:
17818 // CHECK19-NEXT:    call void @__tgt_register_requires(i64 1)
17819 // CHECK19-NEXT:    ret void
17820 //
17821 //
17822 // CHECK20-LABEL: define {{[^@]+}}@_Z7get_valv
17823 // CHECK20-SAME: () #[[ATTR0:[0-9]+]] {
17824 // CHECK20-NEXT:  entry:
17825 // CHECK20-NEXT:    ret i64 0
17826 //
17827 //
17828 // CHECK20-LABEL: define {{[^@]+}}@_Z3fooi
17829 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
17830 // CHECK20-NEXT:  entry:
17831 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17832 // CHECK20-NEXT:    [[A:%.*]] = alloca i32, align 4
17833 // CHECK20-NEXT:    [[AA:%.*]] = alloca i16, align 2
17834 // CHECK20-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
17835 // CHECK20-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
17836 // CHECK20-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
17837 // CHECK20-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
17838 // CHECK20-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
17839 // CHECK20-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
17840 // CHECK20-NEXT:    [[K:%.*]] = alloca i64, align 8
17841 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
17842 // CHECK20-NEXT:    [[LIN:%.*]] = alloca i32, align 4
17843 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
17844 // CHECK20-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
17845 // CHECK20-NEXT:    [[A_CASTED2:%.*]] = alloca i32, align 4
17846 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
17847 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
17848 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
17849 // CHECK20-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
17850 // CHECK20-NEXT:    [[A_CASTED3:%.*]] = alloca i32, align 4
17851 // CHECK20-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
17852 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4
17853 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4
17854 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4
17855 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
17856 // CHECK20-NEXT:    [[A_CASTED11:%.*]] = alloca i32, align 4
17857 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
17858 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4
17859 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4
17860 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4
17861 // CHECK20-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
17862 // CHECK20-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
17863 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17864 // CHECK20-NEXT:    store i32 0, i32* [[A]], align 4
17865 // CHECK20-NEXT:    store i16 0, i16* [[AA]], align 2
17866 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
17867 // CHECK20-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
17868 // CHECK20-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
17869 // CHECK20-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
17870 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
17871 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
17872 // CHECK20-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
17873 // CHECK20-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
17874 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
17875 // CHECK20-NEXT:    [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
17876 // CHECK20-NEXT:    [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
17877 // CHECK20-NEXT:    br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
17878 // CHECK20:       omp_offload.failed:
17879 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]]
17880 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT]]
17881 // CHECK20:       omp_offload.cont:
17882 // CHECK20-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
17883 // CHECK20-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
17884 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
17885 // CHECK20-NEXT:    store i32 [[TMP7]], i32* [[A_CASTED]], align 4
17886 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4
17887 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR3]]
17888 // CHECK20-NEXT:    store i32 12, i32* [[LIN]], align 4
17889 // CHECK20-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
17890 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
17891 // CHECK20-NEXT:    store i16 [[TMP9]], i16* [[CONV]], align 2
17892 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4
17893 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4
17894 // CHECK20-NEXT:    store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4
17895 // CHECK20-NEXT:    [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
17896 // CHECK20-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4
17897 // CHECK20-NEXT:    store i32 [[TMP13]], i32* [[A_CASTED2]], align 4
17898 // CHECK20-NEXT:    [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4
17899 // CHECK20-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
17900 // CHECK20-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
17901 // CHECK20-NEXT:    store i32 [[TMP10]], i32* [[TMP16]], align 4
17902 // CHECK20-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
17903 // CHECK20-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
17904 // CHECK20-NEXT:    store i32 [[TMP10]], i32* [[TMP18]], align 4
17905 // CHECK20-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
17906 // CHECK20-NEXT:    store i8* null, i8** [[TMP19]], align 4
17907 // CHECK20-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
17908 // CHECK20-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
17909 // CHECK20-NEXT:    store i32 [[TMP12]], i32* [[TMP21]], align 4
17910 // CHECK20-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
17911 // CHECK20-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
17912 // CHECK20-NEXT:    store i32 [[TMP12]], i32* [[TMP23]], align 4
17913 // CHECK20-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
17914 // CHECK20-NEXT:    store i8* null, i8** [[TMP24]], align 4
17915 // CHECK20-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
17916 // CHECK20-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
17917 // CHECK20-NEXT:    store i32 [[TMP14]], i32* [[TMP26]], align 4
17918 // CHECK20-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
17919 // CHECK20-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
17920 // CHECK20-NEXT:    store i32 [[TMP14]], i32* [[TMP28]], align 4
17921 // CHECK20-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
17922 // CHECK20-NEXT:    store i8* null, i8** [[TMP29]], align 4
17923 // CHECK20-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
17924 // CHECK20-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
17925 // CHECK20-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
17926 // CHECK20-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
17927 // CHECK20-NEXT:    store i16 [[TMP33]], i16* [[TMP32]], align 4
17928 // CHECK20-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
17929 // CHECK20-NEXT:    [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4
17930 // CHECK20-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
17931 // CHECK20-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
17932 // CHECK20-NEXT:    [[TMP37:%.*]] = load i32, i32* [[A]], align 4
17933 // CHECK20-NEXT:    store i32 [[TMP37]], i32* [[TMP36]], align 4
17934 // CHECK20-NEXT:    [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
17935 // CHECK20-NEXT:    [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
17936 // CHECK20-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
17937 // CHECK20-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
17938 // CHECK20-NEXT:    [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4
17939 // CHECK20-NEXT:    [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
17940 // CHECK20-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false)
17941 // CHECK20-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
17942 // CHECK20-NEXT:    [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
17943 // CHECK20-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
17944 // CHECK20-NEXT:    [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8*
17945 // CHECK20-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
17946 // CHECK20-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
17947 // CHECK20-NEXT:    [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8*
17948 // CHECK20-NEXT:    [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8*
17949 // CHECK20-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false)
17950 // CHECK20-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
17951 // CHECK20-NEXT:    [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8*
17952 // CHECK20-NEXT:    [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8*
17953 // CHECK20-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false)
17954 // CHECK20-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
17955 // CHECK20-NEXT:    [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
17956 // CHECK20-NEXT:    store i16 [[TMP55]], i16* [[TMP54]], align 4
17957 // CHECK20-NEXT:    [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]])
17958 // CHECK20-NEXT:    [[TMP57:%.*]] = load i32, i32* [[A]], align 4
17959 // CHECK20-NEXT:    store i32 [[TMP57]], i32* [[A_CASTED3]], align 4
17960 // CHECK20-NEXT:    [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4
17961 // CHECK20-NEXT:    [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
17962 // CHECK20-NEXT:    [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
17963 // CHECK20-NEXT:    store i16 [[TMP59]], i16* [[CONV5]], align 2
17964 // CHECK20-NEXT:    [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
17965 // CHECK20-NEXT:    [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4
17966 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10
17967 // CHECK20-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
17968 // CHECK20:       omp_if.then:
17969 // CHECK20-NEXT:    [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
17970 // CHECK20-NEXT:    [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32*
17971 // CHECK20-NEXT:    store i32 [[TMP58]], i32* [[TMP63]], align 4
17972 // CHECK20-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
17973 // CHECK20-NEXT:    [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32*
17974 // CHECK20-NEXT:    store i32 [[TMP58]], i32* [[TMP65]], align 4
17975 // CHECK20-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
17976 // CHECK20-NEXT:    store i8* null, i8** [[TMP66]], align 4
17977 // CHECK20-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1
17978 // CHECK20-NEXT:    [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32*
17979 // CHECK20-NEXT:    store i32 [[TMP60]], i32* [[TMP68]], align 4
17980 // CHECK20-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1
17981 // CHECK20-NEXT:    [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32*
17982 // CHECK20-NEXT:    store i32 [[TMP60]], i32* [[TMP70]], align 4
17983 // CHECK20-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1
17984 // CHECK20-NEXT:    store i8* null, i8** [[TMP71]], align 4
17985 // CHECK20-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
17986 // CHECK20-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
17987 // CHECK20-NEXT:    [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
17988 // CHECK20-NEXT:    [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0
17989 // CHECK20-NEXT:    br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
17990 // CHECK20:       omp_offload.failed9:
17991 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR3]]
17992 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT10]]
17993 // CHECK20:       omp_offload.cont10:
17994 // CHECK20-NEXT:    br label [[OMP_IF_END:%.*]]
17995 // CHECK20:       omp_if.else:
17996 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR3]]
17997 // CHECK20-NEXT:    br label [[OMP_IF_END]]
17998 // CHECK20:       omp_if.end:
17999 // CHECK20-NEXT:    [[TMP76:%.*]] = load i32, i32* [[A]], align 4
18000 // CHECK20-NEXT:    store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4
18001 // CHECK20-NEXT:    [[TMP77:%.*]] = load i32, i32* [[A]], align 4
18002 // CHECK20-NEXT:    store i32 [[TMP77]], i32* [[A_CASTED11]], align 4
18003 // CHECK20-NEXT:    [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4
18004 // CHECK20-NEXT:    [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
18005 // CHECK20-NEXT:    store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
18006 // CHECK20-NEXT:    [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
18007 // CHECK20-NEXT:    [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4
18008 // CHECK20-NEXT:    [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20
18009 // CHECK20-NEXT:    br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]]
18010 // CHECK20:       omp_if.then13:
18011 // CHECK20-NEXT:    [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4
18012 // CHECK20-NEXT:    [[TMP83:%.*]] = sext i32 [[TMP82]] to i64
18013 // CHECK20-NEXT:    [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]]
18014 // CHECK20-NEXT:    [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8
18015 // CHECK20-NEXT:    [[TMP86:%.*]] = sext i32 [[TMP85]] to i64
18016 // CHECK20-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
18017 // CHECK20-NEXT:    [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32*
18018 // CHECK20-NEXT:    store i32 [[TMP78]], i32* [[TMP88]], align 4
18019 // CHECK20-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
18020 // CHECK20-NEXT:    [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32*
18021 // CHECK20-NEXT:    store i32 [[TMP78]], i32* [[TMP90]], align 4
18022 // CHECK20-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
18023 // CHECK20-NEXT:    store i64 4, i64* [[TMP91]], align 4
18024 // CHECK20-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
18025 // CHECK20-NEXT:    store i8* null, i8** [[TMP92]], align 4
18026 // CHECK20-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
18027 // CHECK20-NEXT:    [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]**
18028 // CHECK20-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4
18029 // CHECK20-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
18030 // CHECK20-NEXT:    [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]**
18031 // CHECK20-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4
18032 // CHECK20-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
18033 // CHECK20-NEXT:    store i64 40, i64* [[TMP97]], align 4
18034 // CHECK20-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
18035 // CHECK20-NEXT:    store i8* null, i8** [[TMP98]], align 4
18036 // CHECK20-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
18037 // CHECK20-NEXT:    [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i32*
18038 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP100]], align 4
18039 // CHECK20-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
18040 // CHECK20-NEXT:    [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i32*
18041 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP102]], align 4
18042 // CHECK20-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
18043 // CHECK20-NEXT:    store i64 4, i64* [[TMP103]], align 4
18044 // CHECK20-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
18045 // CHECK20-NEXT:    store i8* null, i8** [[TMP104]], align 4
18046 // CHECK20-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
18047 // CHECK20-NEXT:    [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float**
18048 // CHECK20-NEXT:    store float* [[VLA]], float** [[TMP106]], align 4
18049 // CHECK20-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
18050 // CHECK20-NEXT:    [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float**
18051 // CHECK20-NEXT:    store float* [[VLA]], float** [[TMP108]], align 4
18052 // CHECK20-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
18053 // CHECK20-NEXT:    store i64 [[TMP83]], i64* [[TMP109]], align 4
18054 // CHECK20-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
18055 // CHECK20-NEXT:    store i8* null, i8** [[TMP110]], align 4
18056 // CHECK20-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
18057 // CHECK20-NEXT:    [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]**
18058 // CHECK20-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4
18059 // CHECK20-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
18060 // CHECK20-NEXT:    [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]**
18061 // CHECK20-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 4
18062 // CHECK20-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
18063 // CHECK20-NEXT:    store i64 400, i64* [[TMP115]], align 4
18064 // CHECK20-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
18065 // CHECK20-NEXT:    store i8* null, i8** [[TMP116]], align 4
18066 // CHECK20-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
18067 // CHECK20-NEXT:    [[TMP118:%.*]] = bitcast i8** [[TMP117]] to i32*
18068 // CHECK20-NEXT:    store i32 5, i32* [[TMP118]], align 4
18069 // CHECK20-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
18070 // CHECK20-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32*
18071 // CHECK20-NEXT:    store i32 5, i32* [[TMP120]], align 4
18072 // CHECK20-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
18073 // CHECK20-NEXT:    store i64 4, i64* [[TMP121]], align 4
18074 // CHECK20-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
18075 // CHECK20-NEXT:    store i8* null, i8** [[TMP122]], align 4
18076 // CHECK20-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
18077 // CHECK20-NEXT:    [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i32*
18078 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[TMP124]], align 4
18079 // CHECK20-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
18080 // CHECK20-NEXT:    [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32*
18081 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[TMP126]], align 4
18082 // CHECK20-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
18083 // CHECK20-NEXT:    store i64 4, i64* [[TMP127]], align 4
18084 // CHECK20-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
18085 // CHECK20-NEXT:    store i8* null, i8** [[TMP128]], align 4
18086 // CHECK20-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
18087 // CHECK20-NEXT:    [[TMP130:%.*]] = bitcast i8** [[TMP129]] to double**
18088 // CHECK20-NEXT:    store double* [[VLA1]], double** [[TMP130]], align 4
18089 // CHECK20-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
18090 // CHECK20-NEXT:    [[TMP132:%.*]] = bitcast i8** [[TMP131]] to double**
18091 // CHECK20-NEXT:    store double* [[VLA1]], double** [[TMP132]], align 4
18092 // CHECK20-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
18093 // CHECK20-NEXT:    store i64 [[TMP86]], i64* [[TMP133]], align 4
18094 // CHECK20-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
18095 // CHECK20-NEXT:    store i8* null, i8** [[TMP134]], align 4
18096 // CHECK20-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
18097 // CHECK20-NEXT:    [[TMP136:%.*]] = bitcast i8** [[TMP135]] to %struct.TT**
18098 // CHECK20-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP136]], align 4
18099 // CHECK20-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
18100 // CHECK20-NEXT:    [[TMP138:%.*]] = bitcast i8** [[TMP137]] to %struct.TT**
18101 // CHECK20-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP138]], align 4
18102 // CHECK20-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
18103 // CHECK20-NEXT:    store i64 12, i64* [[TMP139]], align 4
18104 // CHECK20-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
18105 // CHECK20-NEXT:    store i8* null, i8** [[TMP140]], align 4
18106 // CHECK20-NEXT:    [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
18107 // CHECK20-NEXT:    [[TMP142:%.*]] = bitcast i8** [[TMP141]] to i32*
18108 // CHECK20-NEXT:    store i32 [[TMP80]], i32* [[TMP142]], align 4
18109 // CHECK20-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
18110 // CHECK20-NEXT:    [[TMP144:%.*]] = bitcast i8** [[TMP143]] to i32*
18111 // CHECK20-NEXT:    store i32 [[TMP80]], i32* [[TMP144]], align 4
18112 // CHECK20-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
18113 // CHECK20-NEXT:    store i64 4, i64* [[TMP145]], align 4
18114 // CHECK20-NEXT:    [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
18115 // CHECK20-NEXT:    store i8* null, i8** [[TMP146]], align 4
18116 // CHECK20-NEXT:    [[TMP147:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
18117 // CHECK20-NEXT:    [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
18118 // CHECK20-NEXT:    [[TMP149:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
18119 // CHECK20-NEXT:    [[TMP150:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP147]], i8** [[TMP148]], i64* [[TMP149]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
18120 // CHECK20-NEXT:    [[TMP151:%.*]] = icmp ne i32 [[TMP150]], 0
18121 // CHECK20-NEXT:    br i1 [[TMP151]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
18122 // CHECK20:       omp_offload.failed17:
18123 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR3]]
18124 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT18]]
18125 // CHECK20:       omp_offload.cont18:
18126 // CHECK20-NEXT:    br label [[OMP_IF_END20:%.*]]
18127 // CHECK20:       omp_if.else19:
18128 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR3]]
18129 // CHECK20-NEXT:    br label [[OMP_IF_END20]]
18130 // CHECK20:       omp_if.end20:
18131 // CHECK20-NEXT:    [[TMP152:%.*]] = load i32, i32* [[A]], align 4
18132 // CHECK20-NEXT:    [[TMP153:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
18133 // CHECK20-NEXT:    call void @llvm.stackrestore(i8* [[TMP153]])
18134 // CHECK20-NEXT:    ret i32 [[TMP152]]
18135 //
18136 //
18137 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
18138 // CHECK20-SAME: () #[[ATTR2:[0-9]+]] {
18139 // CHECK20-NEXT:  entry:
18140 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
18141 // CHECK20-NEXT:    ret void
18142 //
18143 //
18144 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined.
18145 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
18146 // CHECK20-NEXT:  entry:
18147 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
18148 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
18149 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18150 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
18151 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18152 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18153 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
18154 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18155 // CHECK20-NEXT:    [[I:%.*]] = alloca i32, align 4
18156 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
18157 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
18158 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18159 // CHECK20-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
18160 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
18161 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18162 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
18163 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
18164 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
18165 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18166 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
18167 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18168 // CHECK20:       cond.true:
18169 // CHECK20-NEXT:    br label [[COND_END:%.*]]
18170 // CHECK20:       cond.false:
18171 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18172 // CHECK20-NEXT:    br label [[COND_END]]
18173 // CHECK20:       cond.end:
18174 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
18175 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
18176 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18177 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
18178 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18179 // CHECK20:       omp.inner.for.cond:
18180 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18181 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18182 // CHECK20-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
18183 // CHECK20-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18184 // CHECK20:       omp.inner.for.body:
18185 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18186 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
18187 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
18188 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
18189 // CHECK20-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
18190 // CHECK20-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
18191 // CHECK20-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
18192 // CHECK20:       .cancel.exit:
18193 // CHECK20-NEXT:    br label [[CANCEL_EXIT:%.*]]
18194 // CHECK20:       .cancel.continue:
18195 // CHECK20-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
18196 // CHECK20-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
18197 // CHECK20-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
18198 // CHECK20:       .cancel.exit2:
18199 // CHECK20-NEXT:    br label [[CANCEL_EXIT]]
18200 // CHECK20:       .cancel.continue3:
18201 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18202 // CHECK20:       omp.body.continue:
18203 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18204 // CHECK20:       omp.inner.for.inc:
18205 // CHECK20-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18206 // CHECK20-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
18207 // CHECK20-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
18208 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]]
18209 // CHECK20:       omp.inner.for.end:
18210 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
18211 // CHECK20:       omp.loop.exit:
18212 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
18213 // CHECK20-NEXT:    br label [[CANCEL_CONT:%.*]]
18214 // CHECK20:       cancel.cont:
18215 // CHECK20-NEXT:    ret void
18216 // CHECK20:       cancel.exit:
18217 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
18218 // CHECK20-NEXT:    br label [[CANCEL_CONT]]
18219 //
18220 //
18221 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
18222 // CHECK20-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {
18223 // CHECK20-NEXT:  entry:
18224 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
18225 // CHECK20-NEXT:    [[K_ADDR:%.*]] = alloca i64*, align 4
18226 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
18227 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
18228 // CHECK20-NEXT:    store i64* [[K]], i64** [[K_ADDR]], align 4
18229 // CHECK20-NEXT:    [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
18230 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
18231 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
18232 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
18233 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]])
18234 // CHECK20-NEXT:    ret void
18235 //
18236 //
18237 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1
18238 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {
18239 // CHECK20-NEXT:  entry:
18240 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
18241 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
18242 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
18243 // CHECK20-NEXT:    [[K_ADDR:%.*]] = alloca i64*, align 4
18244 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18245 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
18246 // CHECK20-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
18247 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18248 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18249 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
18250 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18251 // CHECK20-NEXT:    [[I:%.*]] = alloca i32, align 4
18252 // CHECK20-NEXT:    [[K1:%.*]] = alloca i64, align 8
18253 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
18254 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
18255 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
18256 // CHECK20-NEXT:    store i64* [[K]], i64** [[K_ADDR]], align 4
18257 // CHECK20-NEXT:    [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
18258 // CHECK20-NEXT:    [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8
18259 // CHECK20-NEXT:    store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8
18260 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18261 // CHECK20-NEXT:    store i32 8, i32* [[DOTOMP_UB]], align 4
18262 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
18263 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18264 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
18265 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
18266 // CHECK20-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
18267 // CHECK20-NEXT:    call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
18268 // CHECK20-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
18269 // CHECK20:       omp.dispatch.cond:
18270 // CHECK20-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
18271 // CHECK20-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
18272 // CHECK20-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
18273 // CHECK20:       omp.dispatch.body:
18274 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18275 // CHECK20-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
18276 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18277 // CHECK20:       omp.inner.for.cond:
18278 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
18279 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
18280 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
18281 // CHECK20-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18282 // CHECK20:       omp.inner.for.body:
18283 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
18284 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
18285 // CHECK20-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
18286 // CHECK20-NEXT:    store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12
18287 // CHECK20-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12
18288 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
18289 // CHECK20-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
18290 // CHECK20-NEXT:    [[CONV:%.*]] = sext i32 [[MUL2]] to i64
18291 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
18292 // CHECK20-NEXT:    store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
18293 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12
18294 // CHECK20-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
18295 // CHECK20-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !12
18296 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18297 // CHECK20:       omp.body.continue:
18298 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18299 // CHECK20:       omp.inner.for.inc:
18300 // CHECK20-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
18301 // CHECK20-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
18302 // CHECK20-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
18303 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
18304 // CHECK20:       omp.inner.for.end:
18305 // CHECK20-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
18306 // CHECK20:       omp.dispatch.inc:
18307 // CHECK20-NEXT:    br label [[OMP_DISPATCH_COND]]
18308 // CHECK20:       omp.dispatch.end:
18309 // CHECK20-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
18310 // CHECK20-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
18311 // CHECK20-NEXT:    br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
18312 // CHECK20:       .omp.linear.pu:
18313 // CHECK20-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
18314 // CHECK20-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP15]], 27
18315 // CHECK20-NEXT:    store i64 [[ADD5]], i64* [[TMP0]], align 8
18316 // CHECK20-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
18317 // CHECK20:       .omp.linear.pu.done:
18318 // CHECK20-NEXT:    ret void
18319 //
18320 //
18321 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
18322 // CHECK20-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
18323 // CHECK20-NEXT:  entry:
18324 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
18325 // CHECK20-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
18326 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
18327 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
18328 // CHECK20-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
18329 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
18330 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
18331 // CHECK20-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
18332 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
18333 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
18334 // CHECK20-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
18335 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
18336 // CHECK20-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
18337 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
18338 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
18339 // CHECK20-NEXT:    store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
18340 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
18341 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
18342 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[A_CASTED]], align 4
18343 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
18344 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
18345 // CHECK20-NEXT:    ret void
18346 //
18347 //
18348 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2
18349 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
18350 // CHECK20-NEXT:  entry:
18351 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
18352 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
18353 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
18354 // CHECK20-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
18355 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
18356 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
18357 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i64, align 4
18358 // CHECK20-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
18359 // CHECK20-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
18360 // CHECK20-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
18361 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
18362 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
18363 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
18364 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18365 // CHECK20-NEXT:    [[IT:%.*]] = alloca i64, align 8
18366 // CHECK20-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
18367 // CHECK20-NEXT:    [[A3:%.*]] = alloca i32, align 4
18368 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
18369 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
18370 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
18371 // CHECK20-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
18372 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
18373 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
18374 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
18375 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
18376 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
18377 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
18378 // CHECK20-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
18379 // CHECK20-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
18380 // CHECK20-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
18381 // CHECK20-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
18382 // CHECK20-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
18383 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18384 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
18385 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
18386 // CHECK20-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
18387 // CHECK20-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
18388 // CHECK20-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
18389 // CHECK20-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
18390 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18391 // CHECK20:       cond.true:
18392 // CHECK20-NEXT:    br label [[COND_END:%.*]]
18393 // CHECK20:       cond.false:
18394 // CHECK20-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
18395 // CHECK20-NEXT:    br label [[COND_END]]
18396 // CHECK20:       cond.end:
18397 // CHECK20-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
18398 // CHECK20-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
18399 // CHECK20-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
18400 // CHECK20-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
18401 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18402 // CHECK20:       omp.inner.for.cond:
18403 // CHECK20-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
18404 // CHECK20-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
18405 // CHECK20-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
18406 // CHECK20-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18407 // CHECK20:       omp.inner.for.body:
18408 // CHECK20-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
18409 // CHECK20-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
18410 // CHECK20-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
18411 // CHECK20-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
18412 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
18413 // CHECK20-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
18414 // CHECK20-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
18415 // CHECK20-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
18416 // CHECK20-NEXT:    [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
18417 // CHECK20-NEXT:    [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
18418 // CHECK20-NEXT:    [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
18419 // CHECK20-NEXT:    store i32 [[CONV7]], i32* [[LIN2]], align 4
18420 // CHECK20-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
18421 // CHECK20-NEXT:    [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
18422 // CHECK20-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
18423 // CHECK20-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
18424 // CHECK20-NEXT:    [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
18425 // CHECK20-NEXT:    [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
18426 // CHECK20-NEXT:    [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
18427 // CHECK20-NEXT:    store i32 [[CONV11]], i32* [[A3]], align 4
18428 // CHECK20-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4
18429 // CHECK20-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
18430 // CHECK20-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
18431 // CHECK20-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
18432 // CHECK20-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4
18433 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18434 // CHECK20:       omp.body.continue:
18435 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18436 // CHECK20:       omp.inner.for.inc:
18437 // CHECK20-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
18438 // CHECK20-NEXT:    [[ADD15:%.*]] = add i64 [[TMP17]], 1
18439 // CHECK20-NEXT:    store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
18440 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]]
18441 // CHECK20:       omp.inner.for.end:
18442 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
18443 // CHECK20:       omp.loop.exit:
18444 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
18445 // CHECK20-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
18446 // CHECK20-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
18447 // CHECK20-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
18448 // CHECK20:       .omp.linear.pu:
18449 // CHECK20-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
18450 // CHECK20-NEXT:    [[CONV16:%.*]] = sext i32 [[TMP20]] to i64
18451 // CHECK20-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
18452 // CHECK20-NEXT:    [[MUL17:%.*]] = mul i64 4, [[TMP21]]
18453 // CHECK20-NEXT:    [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
18454 // CHECK20-NEXT:    [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
18455 // CHECK20-NEXT:    store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
18456 // CHECK20-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
18457 // CHECK20-NEXT:    [[CONV20:%.*]] = sext i32 [[TMP22]] to i64
18458 // CHECK20-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
18459 // CHECK20-NEXT:    [[MUL21:%.*]] = mul i64 4, [[TMP23]]
18460 // CHECK20-NEXT:    [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
18461 // CHECK20-NEXT:    [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
18462 // CHECK20-NEXT:    store i32 [[CONV23]], i32* [[A_ADDR]], align 4
18463 // CHECK20-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
18464 // CHECK20:       .omp.linear.pu.done:
18465 // CHECK20-NEXT:    ret void
18466 //
18467 //
18468 // CHECK20-LABEL: define {{[^@]+}}@.omp_task_privates_map.
18469 // CHECK20-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
18470 // CHECK20-NEXT:  entry:
18471 // CHECK20-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
18472 // CHECK20-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 4
18473 // CHECK20-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
18474 // CHECK20-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
18475 // CHECK20-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
18476 // CHECK20-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
18477 // CHECK20-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
18478 // CHECK20-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
18479 // CHECK20-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
18480 // CHECK20-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
18481 // CHECK20-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
18482 // CHECK20-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
18483 // CHECK20-NEXT:    [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
18484 // CHECK20-NEXT:    store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
18485 // CHECK20-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
18486 // CHECK20-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
18487 // CHECK20-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
18488 // CHECK20-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
18489 // CHECK20-NEXT:    [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
18490 // CHECK20-NEXT:    store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
18491 // CHECK20-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
18492 // CHECK20-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
18493 // CHECK20-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 4
18494 // CHECK20-NEXT:    ret void
18495 //
18496 //
18497 // CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry.
18498 // CHECK20-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
18499 // CHECK20-NEXT:  entry:
18500 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
18501 // CHECK20-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
18502 // CHECK20-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
18503 // CHECK20-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
18504 // CHECK20-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
18505 // CHECK20-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
18506 // CHECK20-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
18507 // CHECK20-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
18508 // CHECK20-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
18509 // CHECK20-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
18510 // CHECK20-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
18511 // CHECK20-NEXT:    [[LIN_CASTED_I:%.*]] = alloca i32, align 4
18512 // CHECK20-NEXT:    [[A_CASTED_I:%.*]] = alloca i32, align 4
18513 // CHECK20-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
18514 // CHECK20-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
18515 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
18516 // CHECK20-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
18517 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
18518 // CHECK20-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
18519 // CHECK20-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
18520 // CHECK20-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
18521 // CHECK20-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
18522 // CHECK20-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
18523 // CHECK20-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
18524 // CHECK20-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
18525 // CHECK20-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
18526 // CHECK20-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
18527 // CHECK20-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
18528 // CHECK20-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
18529 // CHECK20-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
18530 // CHECK20-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
18531 // CHECK20-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
18532 // CHECK20-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24
18533 // CHECK20-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24
18534 // CHECK20-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24
18535 // CHECK20-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24
18536 // CHECK20-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24
18537 // CHECK20-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24
18538 // CHECK20-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24
18539 // CHECK20-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24
18540 // CHECK20-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
18541 // CHECK20-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
18542 // CHECK20-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24
18543 // CHECK20-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24
18544 // CHECK20-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24
18545 // CHECK20-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24
18546 // CHECK20-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
18547 // CHECK20-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
18548 // CHECK20-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
18549 // CHECK20-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
18550 // CHECK20-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
18551 // CHECK20-NEXT:    [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) #[[ATTR3]]
18552 // CHECK20-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
18553 // CHECK20-NEXT:    br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
18554 // CHECK20:       omp_offload.failed.i:
18555 // CHECK20-NEXT:    [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2
18556 // CHECK20-NEXT:    [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
18557 // CHECK20-NEXT:    store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24
18558 // CHECK20-NEXT:    [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !24
18559 // CHECK20-NEXT:    [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4
18560 // CHECK20-NEXT:    store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !24
18561 // CHECK20-NEXT:    [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !24
18562 // CHECK20-NEXT:    [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4
18563 // CHECK20-NEXT:    store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !24
18564 // CHECK20-NEXT:    [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !24
18565 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR3]]
18566 // CHECK20-NEXT:    br label [[DOTOMP_OUTLINED__3_EXIT]]
18567 // CHECK20:       .omp_outlined..3.exit:
18568 // CHECK20-NEXT:    ret i32 0
18569 //
18570 //
18571 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
18572 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
18573 // CHECK20-NEXT:  entry:
18574 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
18575 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
18576 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
18577 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
18578 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
18579 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
18580 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
18581 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
18582 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
18583 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
18584 // CHECK20-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
18585 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
18586 // CHECK20-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
18587 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
18588 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
18589 // CHECK20-NEXT:    ret void
18590 //
18591 //
18592 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4
18593 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
18594 // CHECK20-NEXT:  entry:
18595 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
18596 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
18597 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
18598 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
18599 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18600 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i16, align 2
18601 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18602 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18603 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
18604 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18605 // CHECK20-NEXT:    [[IT:%.*]] = alloca i16, align 2
18606 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
18607 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
18608 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
18609 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
18610 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
18611 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18612 // CHECK20-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
18613 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
18614 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18615 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
18616 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
18617 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
18618 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18619 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
18620 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18621 // CHECK20:       cond.true:
18622 // CHECK20-NEXT:    br label [[COND_END:%.*]]
18623 // CHECK20:       cond.false:
18624 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18625 // CHECK20-NEXT:    br label [[COND_END]]
18626 // CHECK20:       cond.end:
18627 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
18628 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
18629 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18630 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
18631 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18632 // CHECK20:       omp.inner.for.cond:
18633 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18634 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18635 // CHECK20-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
18636 // CHECK20-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18637 // CHECK20:       omp.inner.for.body:
18638 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18639 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
18640 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
18641 // CHECK20-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
18642 // CHECK20-NEXT:    store i16 [[CONV2]], i16* [[IT]], align 2
18643 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
18644 // CHECK20-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
18645 // CHECK20-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4
18646 // CHECK20-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
18647 // CHECK20-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
18648 // CHECK20-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
18649 // CHECK20-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
18650 // CHECK20-NEXT:    store i16 [[CONV6]], i16* [[CONV]], align 4
18651 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18652 // CHECK20:       omp.body.continue:
18653 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18654 // CHECK20:       omp.inner.for.inc:
18655 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18656 // CHECK20-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
18657 // CHECK20-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
18658 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]]
18659 // CHECK20:       omp.inner.for.end:
18660 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
18661 // CHECK20:       omp.loop.exit:
18662 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
18663 // CHECK20-NEXT:    ret void
18664 //
18665 //
18666 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
18667 // CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
18668 // CHECK20-NEXT:  entry:
18669 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
18670 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
18671 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
18672 // CHECK20-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
18673 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
18674 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
18675 // CHECK20-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
18676 // CHECK20-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
18677 // CHECK20-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
18678 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
18679 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
18680 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
18681 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
18682 // CHECK20-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
18683 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
18684 // CHECK20-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
18685 // CHECK20-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
18686 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
18687 // CHECK20-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
18688 // CHECK20-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
18689 // CHECK20-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
18690 // CHECK20-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
18691 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
18692 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
18693 // CHECK20-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
18694 // CHECK20-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
18695 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
18696 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
18697 // CHECK20-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
18698 // CHECK20-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
18699 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
18700 // CHECK20-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
18701 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
18702 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
18703 // CHECK20-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
18704 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
18705 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
18706 // CHECK20-NEXT:    ret void
18707 //
18708 //
18709 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7
18710 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
18711 // CHECK20-NEXT:  entry:
18712 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
18713 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
18714 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
18715 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
18716 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
18717 // CHECK20-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
18718 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
18719 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
18720 // CHECK20-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
18721 // CHECK20-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
18722 // CHECK20-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
18723 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
18724 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18725 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i8, align 1
18726 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18727 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18728 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
18729 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18730 // CHECK20-NEXT:    [[IT:%.*]] = alloca i8, align 1
18731 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
18732 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
18733 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
18734 // CHECK20-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
18735 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
18736 // CHECK20-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
18737 // CHECK20-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
18738 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
18739 // CHECK20-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
18740 // CHECK20-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
18741 // CHECK20-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
18742 // CHECK20-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
18743 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
18744 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
18745 // CHECK20-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
18746 // CHECK20-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
18747 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
18748 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
18749 // CHECK20-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
18750 // CHECK20-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
18751 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18752 // CHECK20-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
18753 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
18754 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18755 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
18756 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
18757 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
18758 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
18759 // CHECK20-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
18760 // CHECK20:       omp.dispatch.cond:
18761 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18762 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
18763 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18764 // CHECK20:       cond.true:
18765 // CHECK20-NEXT:    br label [[COND_END:%.*]]
18766 // CHECK20:       cond.false:
18767 // CHECK20-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18768 // CHECK20-NEXT:    br label [[COND_END]]
18769 // CHECK20:       cond.end:
18770 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
18771 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
18772 // CHECK20-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18773 // CHECK20-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
18774 // CHECK20-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18775 // CHECK20-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18776 // CHECK20-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
18777 // CHECK20-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
18778 // CHECK20:       omp.dispatch.body:
18779 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18780 // CHECK20:       omp.inner.for.cond:
18781 // CHECK20-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18782 // CHECK20-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18783 // CHECK20-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
18784 // CHECK20-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18785 // CHECK20:       omp.inner.for.body:
18786 // CHECK20-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18787 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
18788 // CHECK20-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
18789 // CHECK20-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
18790 // CHECK20-NEXT:    store i8 [[CONV]], i8* [[IT]], align 1
18791 // CHECK20-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
18792 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
18793 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
18794 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
18795 // CHECK20-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
18796 // CHECK20-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
18797 // CHECK20-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
18798 // CHECK20-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
18799 // CHECK20-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4
18800 // CHECK20-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
18801 // CHECK20-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
18802 // CHECK20-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
18803 // CHECK20-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
18804 // CHECK20-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
18805 // CHECK20-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4
18806 // CHECK20-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
18807 // CHECK20-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
18808 // CHECK20-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
18809 // CHECK20-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
18810 // CHECK20-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8
18811 // CHECK20-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
18812 // CHECK20-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
18813 // CHECK20-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
18814 // CHECK20-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
18815 // CHECK20-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
18816 // CHECK20-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8
18817 // CHECK20-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
18818 // CHECK20-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4
18819 // CHECK20-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
18820 // CHECK20-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4
18821 // CHECK20-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
18822 // CHECK20-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
18823 // CHECK20-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
18824 // CHECK20-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
18825 // CHECK20-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
18826 // CHECK20-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4
18827 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18828 // CHECK20:       omp.body.continue:
18829 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18830 // CHECK20:       omp.inner.for.inc:
18831 // CHECK20-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18832 // CHECK20-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
18833 // CHECK20-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
18834 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]]
18835 // CHECK20:       omp.inner.for.end:
18836 // CHECK20-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
18837 // CHECK20:       omp.dispatch.inc:
18838 // CHECK20-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18839 // CHECK20-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
18840 // CHECK20-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
18841 // CHECK20-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
18842 // CHECK20-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18843 // CHECK20-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
18844 // CHECK20-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
18845 // CHECK20-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
18846 // CHECK20-NEXT:    br label [[OMP_DISPATCH_COND]]
18847 // CHECK20:       omp.dispatch.end:
18848 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
18849 // CHECK20-NEXT:    ret void
18850 //
18851 //
18852 // CHECK20-LABEL: define {{[^@]+}}@_Z3bari
18853 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
18854 // CHECK20-NEXT:  entry:
18855 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
18856 // CHECK20-NEXT:    [[A:%.*]] = alloca i32, align 4
18857 // CHECK20-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
18858 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
18859 // CHECK20-NEXT:    store i32 0, i32* [[A]], align 4
18860 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
18861 // CHECK20-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
18862 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
18863 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
18864 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
18865 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
18866 // CHECK20-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
18867 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
18868 // CHECK20-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
18869 // CHECK20-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
18870 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
18871 // CHECK20-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
18872 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
18873 // CHECK20-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
18874 // CHECK20-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
18875 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
18876 // CHECK20-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
18877 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
18878 // CHECK20-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
18879 // CHECK20-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
18880 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
18881 // CHECK20-NEXT:    ret i32 [[TMP8]]
18882 //
18883 //
18884 // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
18885 // CHECK20-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
18886 // CHECK20-NEXT:  entry:
18887 // CHECK20-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
18888 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
18889 // CHECK20-NEXT:    [[B:%.*]] = alloca i32, align 4
18890 // CHECK20-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
18891 // CHECK20-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
18892 // CHECK20-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
18893 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
18894 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
18895 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
18896 // CHECK20-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
18897 // CHECK20-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
18898 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
18899 // CHECK20-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
18900 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
18901 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
18902 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
18903 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
18904 // CHECK20-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
18905 // CHECK20-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
18906 // CHECK20-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
18907 // CHECK20-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
18908 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
18909 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
18910 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
18911 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
18912 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
18913 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
18914 // CHECK20-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
18915 // CHECK20:       omp_if.then:
18916 // CHECK20-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
18917 // CHECK20-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
18918 // CHECK20-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
18919 // CHECK20-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
18920 // CHECK20-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
18921 // CHECK20-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
18922 // CHECK20-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
18923 // CHECK20-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
18924 // CHECK20-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
18925 // CHECK20-NEXT:    store double* [[A]], double** [[TMP13]], align 4
18926 // CHECK20-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
18927 // CHECK20-NEXT:    store i64 8, i64* [[TMP14]], align 4
18928 // CHECK20-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
18929 // CHECK20-NEXT:    store i8* null, i8** [[TMP15]], align 4
18930 // CHECK20-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
18931 // CHECK20-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
18932 // CHECK20-NEXT:    store i32 [[TMP5]], i32* [[TMP17]], align 4
18933 // CHECK20-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
18934 // CHECK20-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
18935 // CHECK20-NEXT:    store i32 [[TMP5]], i32* [[TMP19]], align 4
18936 // CHECK20-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
18937 // CHECK20-NEXT:    store i64 4, i64* [[TMP20]], align 4
18938 // CHECK20-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
18939 // CHECK20-NEXT:    store i8* null, i8** [[TMP21]], align 4
18940 // CHECK20-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
18941 // CHECK20-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
18942 // CHECK20-NEXT:    store i32 2, i32* [[TMP23]], align 4
18943 // CHECK20-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
18944 // CHECK20-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
18945 // CHECK20-NEXT:    store i32 2, i32* [[TMP25]], align 4
18946 // CHECK20-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
18947 // CHECK20-NEXT:    store i64 4, i64* [[TMP26]], align 4
18948 // CHECK20-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
18949 // CHECK20-NEXT:    store i8* null, i8** [[TMP27]], align 4
18950 // CHECK20-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
18951 // CHECK20-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
18952 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP29]], align 4
18953 // CHECK20-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
18954 // CHECK20-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
18955 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP31]], align 4
18956 // CHECK20-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
18957 // CHECK20-NEXT:    store i64 4, i64* [[TMP32]], align 4
18958 // CHECK20-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
18959 // CHECK20-NEXT:    store i8* null, i8** [[TMP33]], align 4
18960 // CHECK20-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
18961 // CHECK20-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
18962 // CHECK20-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 4
18963 // CHECK20-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
18964 // CHECK20-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
18965 // CHECK20-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 4
18966 // CHECK20-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
18967 // CHECK20-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 4
18968 // CHECK20-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
18969 // CHECK20-NEXT:    store i8* null, i8** [[TMP39]], align 4
18970 // CHECK20-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
18971 // CHECK20-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
18972 // CHECK20-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
18973 // CHECK20-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
18974 // CHECK20-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
18975 // CHECK20-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
18976 // CHECK20:       omp_offload.failed:
18977 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
18978 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT]]
18979 // CHECK20:       omp_offload.cont:
18980 // CHECK20-NEXT:    br label [[OMP_IF_END:%.*]]
18981 // CHECK20:       omp_if.else:
18982 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
18983 // CHECK20-NEXT:    br label [[OMP_IF_END]]
18984 // CHECK20:       omp_if.end:
18985 // CHECK20-NEXT:    [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
18986 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
18987 // CHECK20-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
18988 // CHECK20-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
18989 // CHECK20-NEXT:    [[CONV:%.*]] = sext i16 [[TMP46]] to i32
18990 // CHECK20-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
18991 // CHECK20-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
18992 // CHECK20-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
18993 // CHECK20-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
18994 // CHECK20-NEXT:    ret i32 [[ADD3]]
18995 //
18996 //
18997 // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici
18998 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
18999 // CHECK20-NEXT:  entry:
19000 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
19001 // CHECK20-NEXT:    [[A:%.*]] = alloca i32, align 4
19002 // CHECK20-NEXT:    [[AA:%.*]] = alloca i16, align 2
19003 // CHECK20-NEXT:    [[AAA:%.*]] = alloca i8, align 1
19004 // CHECK20-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
19005 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
19006 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
19007 // CHECK20-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
19008 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
19009 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
19010 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
19011 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
19012 // CHECK20-NEXT:    store i32 0, i32* [[A]], align 4
19013 // CHECK20-NEXT:    store i16 0, i16* [[AA]], align 2
19014 // CHECK20-NEXT:    store i8 0, i8* [[AAA]], align 1
19015 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
19016 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
19017 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
19018 // CHECK20-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
19019 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
19020 // CHECK20-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
19021 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
19022 // CHECK20-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
19023 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
19024 // CHECK20-NEXT:    store i8 [[TMP4]], i8* [[CONV1]], align 1
19025 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
19026 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
19027 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
19028 // CHECK20-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
19029 // CHECK20:       omp_if.then:
19030 // CHECK20-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
19031 // CHECK20-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
19032 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
19033 // CHECK20-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
19034 // CHECK20-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
19035 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
19036 // CHECK20-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
19037 // CHECK20-NEXT:    store i8* null, i8** [[TMP11]], align 4
19038 // CHECK20-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
19039 // CHECK20-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
19040 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
19041 // CHECK20-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
19042 // CHECK20-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
19043 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
19044 // CHECK20-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
19045 // CHECK20-NEXT:    store i8* null, i8** [[TMP16]], align 4
19046 // CHECK20-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
19047 // CHECK20-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
19048 // CHECK20-NEXT:    store i32 [[TMP5]], i32* [[TMP18]], align 4
19049 // CHECK20-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
19050 // CHECK20-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
19051 // CHECK20-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
19052 // CHECK20-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
19053 // CHECK20-NEXT:    store i8* null, i8** [[TMP21]], align 4
19054 // CHECK20-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
19055 // CHECK20-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
19056 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
19057 // CHECK20-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
19058 // CHECK20-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
19059 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
19060 // CHECK20-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
19061 // CHECK20-NEXT:    store i8* null, i8** [[TMP26]], align 4
19062 // CHECK20-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
19063 // CHECK20-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
19064 // CHECK20-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
19065 // CHECK20-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
19066 // CHECK20-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
19067 // CHECK20:       omp_offload.failed:
19068 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
19069 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT]]
19070 // CHECK20:       omp_offload.cont:
19071 // CHECK20-NEXT:    br label [[OMP_IF_END:%.*]]
19072 // CHECK20:       omp_if.else:
19073 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
19074 // CHECK20-NEXT:    br label [[OMP_IF_END]]
19075 // CHECK20:       omp_if.end:
19076 // CHECK20-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
19077 // CHECK20-NEXT:    ret i32 [[TMP31]]
19078 //
19079 //
19080 // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
19081 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
19082 // CHECK20-NEXT:  entry:
19083 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
19084 // CHECK20-NEXT:    [[A:%.*]] = alloca i32, align 4
19085 // CHECK20-NEXT:    [[AA:%.*]] = alloca i16, align 2
19086 // CHECK20-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
19087 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
19088 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
19089 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
19090 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
19091 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
19092 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
19093 // CHECK20-NEXT:    store i32 0, i32* [[A]], align 4
19094 // CHECK20-NEXT:    store i16 0, i16* [[AA]], align 2
19095 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
19096 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
19097 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
19098 // CHECK20-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
19099 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
19100 // CHECK20-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
19101 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
19102 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
19103 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
19104 // CHECK20-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
19105 // CHECK20:       omp_if.then:
19106 // CHECK20-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
19107 // CHECK20-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
19108 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
19109 // CHECK20-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
19110 // CHECK20-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
19111 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
19112 // CHECK20-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
19113 // CHECK20-NEXT:    store i8* null, i8** [[TMP9]], align 4
19114 // CHECK20-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
19115 // CHECK20-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
19116 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
19117 // CHECK20-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
19118 // CHECK20-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
19119 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
19120 // CHECK20-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
19121 // CHECK20-NEXT:    store i8* null, i8** [[TMP14]], align 4
19122 // CHECK20-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
19123 // CHECK20-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
19124 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
19125 // CHECK20-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
19126 // CHECK20-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
19127 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
19128 // CHECK20-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
19129 // CHECK20-NEXT:    store i8* null, i8** [[TMP19]], align 4
19130 // CHECK20-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
19131 // CHECK20-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
19132 // CHECK20-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
19133 // CHECK20-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
19134 // CHECK20-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
19135 // CHECK20:       omp_offload.failed:
19136 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
19137 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT]]
19138 // CHECK20:       omp_offload.cont:
19139 // CHECK20-NEXT:    br label [[OMP_IF_END:%.*]]
19140 // CHECK20:       omp_if.else:
19141 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
19142 // CHECK20-NEXT:    br label [[OMP_IF_END]]
19143 // CHECK20:       omp_if.end:
19144 // CHECK20-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
19145 // CHECK20-NEXT:    ret i32 [[TMP24]]
19146 //
19147 //
19148 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
19149 // CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
19150 // CHECK20-NEXT:  entry:
19151 // CHECK20-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
19152 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
19153 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
19154 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
19155 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
19156 // CHECK20-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
19157 // CHECK20-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
19158 // CHECK20-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
19159 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
19160 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
19161 // CHECK20-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
19162 // CHECK20-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
19163 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
19164 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
19165 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
19166 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
19167 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
19168 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
19169 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
19170 // CHECK20-NEXT:    ret void
19171 //
19172 //
19173 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9
19174 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
19175 // CHECK20-NEXT:  entry:
19176 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
19177 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
19178 // CHECK20-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
19179 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
19180 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
19181 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
19182 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
19183 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
19184 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i64, align 4
19185 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
19186 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
19187 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
19188 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19189 // CHECK20-NEXT:    [[IT:%.*]] = alloca i64, align 8
19190 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
19191 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
19192 // CHECK20-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
19193 // CHECK20-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
19194 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
19195 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
19196 // CHECK20-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
19197 // CHECK20-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
19198 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
19199 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
19200 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
19201 // CHECK20-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
19202 // CHECK20-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
19203 // CHECK20-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
19204 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19205 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
19206 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
19207 // CHECK20-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
19208 // CHECK20-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
19209 // CHECK20-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
19210 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19211 // CHECK20:       cond.true:
19212 // CHECK20-NEXT:    br label [[COND_END:%.*]]
19213 // CHECK20:       cond.false:
19214 // CHECK20-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
19215 // CHECK20-NEXT:    br label [[COND_END]]
19216 // CHECK20:       cond.end:
19217 // CHECK20-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
19218 // CHECK20-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
19219 // CHECK20-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
19220 // CHECK20-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
19221 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19222 // CHECK20:       omp.inner.for.cond:
19223 // CHECK20-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
19224 // CHECK20-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
19225 // CHECK20-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
19226 // CHECK20-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19227 // CHECK20:       omp.inner.for.body:
19228 // CHECK20-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
19229 // CHECK20-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
19230 // CHECK20-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
19231 // CHECK20-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
19232 // CHECK20-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
19233 // CHECK20-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
19234 // CHECK20-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
19235 // CHECK20-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
19236 // CHECK20-NEXT:    store double [[ADD]], double* [[A]], align 4
19237 // CHECK20-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
19238 // CHECK20-NEXT:    [[TMP13:%.*]] = load double, double* [[A4]], align 4
19239 // CHECK20-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
19240 // CHECK20-NEXT:    store double [[INC]], double* [[A4]], align 4
19241 // CHECK20-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
19242 // CHECK20-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
19243 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
19244 // CHECK20-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
19245 // CHECK20-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
19246 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19247 // CHECK20:       omp.body.continue:
19248 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19249 // CHECK20:       omp.inner.for.inc:
19250 // CHECK20-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
19251 // CHECK20-NEXT:    [[ADD7:%.*]] = add i64 [[TMP15]], 1
19252 // CHECK20-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
19253 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]]
19254 // CHECK20:       omp.inner.for.end:
19255 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19256 // CHECK20:       omp.loop.exit:
19257 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
19258 // CHECK20-NEXT:    ret void
19259 //
19260 //
19261 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
19262 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
19263 // CHECK20-NEXT:  entry:
19264 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19265 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19266 // CHECK20-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
19267 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
19268 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
19269 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
19270 // CHECK20-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
19271 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19272 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19273 // CHECK20-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
19274 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
19275 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19276 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
19277 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
19278 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
19279 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
19280 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
19281 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
19282 // CHECK20-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
19283 // CHECK20-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
19284 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
19285 // CHECK20-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
19286 // CHECK20-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
19287 // CHECK20-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
19288 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
19289 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
19290 // CHECK20-NEXT:    ret void
19291 //
19292 //
19293 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11
19294 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
19295 // CHECK20-NEXT:  entry:
19296 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
19297 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
19298 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19299 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19300 // CHECK20-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
19301 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
19302 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19303 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19304 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
19305 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
19306 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19307 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19308 // CHECK20-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
19309 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
19310 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19311 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
19312 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
19313 // CHECK20-NEXT:    ret void
19314 //
19315 //
19316 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
19317 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
19318 // CHECK20-NEXT:  entry:
19319 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19320 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19321 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
19322 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
19323 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
19324 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19325 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19326 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
19327 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19328 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
19329 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
19330 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
19331 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
19332 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
19333 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
19334 // CHECK20-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
19335 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
19336 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
19337 // CHECK20-NEXT:    ret void
19338 //
19339 //
19340 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..14
19341 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
19342 // CHECK20-NEXT:  entry:
19343 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
19344 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
19345 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19346 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19347 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
19348 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
19349 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i64, align 4
19350 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
19351 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
19352 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
19353 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19354 // CHECK20-NEXT:    [[I:%.*]] = alloca i64, align 8
19355 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
19356 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
19357 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19358 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19359 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
19360 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19361 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
19362 // CHECK20-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
19363 // CHECK20-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
19364 // CHECK20-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
19365 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19366 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
19367 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
19368 // CHECK20-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
19369 // CHECK20-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
19370 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
19371 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19372 // CHECK20:       cond.true:
19373 // CHECK20-NEXT:    br label [[COND_END:%.*]]
19374 // CHECK20:       cond.false:
19375 // CHECK20-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
19376 // CHECK20-NEXT:    br label [[COND_END]]
19377 // CHECK20:       cond.end:
19378 // CHECK20-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
19379 // CHECK20-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
19380 // CHECK20-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
19381 // CHECK20-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
19382 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19383 // CHECK20:       omp.inner.for.cond:
19384 // CHECK20-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
19385 // CHECK20-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
19386 // CHECK20-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
19387 // CHECK20-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19388 // CHECK20:       omp.inner.for.body:
19389 // CHECK20-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
19390 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
19391 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
19392 // CHECK20-NEXT:    store i64 [[ADD]], i64* [[I]], align 8
19393 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
19394 // CHECK20-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
19395 // CHECK20-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
19396 // CHECK20-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
19397 // CHECK20-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
19398 // CHECK20-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
19399 // CHECK20-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
19400 // CHECK20-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
19401 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
19402 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
19403 // CHECK20-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
19404 // CHECK20-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
19405 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19406 // CHECK20:       omp.body.continue:
19407 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19408 // CHECK20:       omp.inner.for.inc:
19409 // CHECK20-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
19410 // CHECK20-NEXT:    [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
19411 // CHECK20-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
19412 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]]
19413 // CHECK20:       omp.inner.for.end:
19414 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19415 // CHECK20:       omp.loop.exit:
19416 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
19417 // CHECK20-NEXT:    ret void
19418 //
19419 //
19420 // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
19421 // CHECK20-SAME: () #[[ATTR5]] {
19422 // CHECK20-NEXT:  entry:
19423 // CHECK20-NEXT:    call void @__tgt_register_requires(i64 1)
19424 // CHECK20-NEXT:    ret void
19425 //
19426 //
19427 // CHECK21-LABEL: define {{[^@]+}}@_Z7get_valv
19428 // CHECK21-SAME: () #[[ATTR0:[0-9]+]] {
19429 // CHECK21-NEXT:  entry:
19430 // CHECK21-NEXT:    ret i64 0
19431 //
19432 //
19433 // CHECK21-LABEL: define {{[^@]+}}@_Z3fooi
19434 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
19435 // CHECK21-NEXT:  entry:
19436 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
19437 // CHECK21-NEXT:    [[A:%.*]] = alloca i32, align 4
19438 // CHECK21-NEXT:    [[AA:%.*]] = alloca i16, align 2
19439 // CHECK21-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
19440 // CHECK21-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
19441 // CHECK21-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
19442 // CHECK21-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
19443 // CHECK21-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
19444 // CHECK21-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
19445 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
19446 // CHECK21-NEXT:    [[K:%.*]] = alloca i64, align 8
19447 // CHECK21-NEXT:    [[I2:%.*]] = alloca i32, align 4
19448 // CHECK21-NEXT:    [[LIN:%.*]] = alloca i32, align 4
19449 // CHECK21-NEXT:    [[IT:%.*]] = alloca i64, align 8
19450 // CHECK21-NEXT:    [[IT16:%.*]] = alloca i16, align 2
19451 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
19452 // CHECK21-NEXT:    [[IT30:%.*]] = alloca i8, align 1
19453 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
19454 // CHECK21-NEXT:    store i32 0, i32* [[A]], align 4
19455 // CHECK21-NEXT:    store i16 0, i16* [[AA]], align 2
19456 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
19457 // CHECK21-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
19458 // CHECK21-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
19459 // CHECK21-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
19460 // CHECK21-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
19461 // CHECK21-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
19462 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
19463 // CHECK21-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
19464 // CHECK21-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
19465 // CHECK21-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
19466 // CHECK21-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
19467 // CHECK21-NEXT:    store i32 3, i32* [[I]], align 4
19468 // CHECK21-NEXT:    br label [[FOR_COND:%.*]]
19469 // CHECK21:       for.cond:
19470 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I]], align 4
19471 // CHECK21-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32
19472 // CHECK21-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
19473 // CHECK21:       for.body:
19474 // CHECK21-NEXT:    br label [[FOR_INC:%.*]]
19475 // CHECK21:       for.inc:
19476 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
19477 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP7]], 5
19478 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
19479 // CHECK21-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
19480 // CHECK21:       for.end:
19481 // CHECK21-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
19482 // CHECK21-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
19483 // CHECK21-NEXT:    store i32 10, i32* [[I2]], align 4
19484 // CHECK21-NEXT:    br label [[FOR_COND3:%.*]]
19485 // CHECK21:       for.cond3:
19486 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I2]], align 4
19487 // CHECK21-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1
19488 // CHECK21-NEXT:    br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]]
19489 // CHECK21:       for.body5:
19490 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
19491 // CHECK21-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1
19492 // CHECK21-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
19493 // CHECK21-NEXT:    br label [[FOR_INC7:%.*]]
19494 // CHECK21:       for.inc7:
19495 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I2]], align 4
19496 // CHECK21-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP10]], -1
19497 // CHECK21-NEXT:    store i32 [[DEC]], i32* [[I2]], align 4
19498 // CHECK21-NEXT:    br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]]
19499 // CHECK21:       for.end8:
19500 // CHECK21-NEXT:    store i32 12, i32* [[LIN]], align 4
19501 // CHECK21-NEXT:    store i64 2000, i64* [[IT]], align 8
19502 // CHECK21-NEXT:    br label [[FOR_COND9:%.*]]
19503 // CHECK21:       for.cond9:
19504 // CHECK21-NEXT:    [[TMP11:%.*]] = load i64, i64* [[IT]], align 8
19505 // CHECK21-NEXT:    [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600
19506 // CHECK21-NEXT:    br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]]
19507 // CHECK21:       for.body11:
19508 // CHECK21-NEXT:    [[TMP12:%.*]] = load i16, i16* [[AA]], align 2
19509 // CHECK21-NEXT:    [[CONV:%.*]] = sext i16 [[TMP12]] to i32
19510 // CHECK21-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV]], 1
19511 // CHECK21-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
19512 // CHECK21-NEXT:    store i16 [[CONV13]], i16* [[AA]], align 2
19513 // CHECK21-NEXT:    br label [[FOR_INC14:%.*]]
19514 // CHECK21:       for.inc14:
19515 // CHECK21-NEXT:    [[TMP13:%.*]] = load i64, i64* [[IT]], align 8
19516 // CHECK21-NEXT:    [[SUB:%.*]] = sub i64 [[TMP13]], 400
19517 // CHECK21-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
19518 // CHECK21-NEXT:    br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]]
19519 // CHECK21:       for.end15:
19520 // CHECK21-NEXT:    store i16 6, i16* [[IT16]], align 2
19521 // CHECK21-NEXT:    br label [[FOR_COND17:%.*]]
19522 // CHECK21:       for.cond17:
19523 // CHECK21-NEXT:    [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2
19524 // CHECK21-NEXT:    [[CONV18:%.*]] = sext i16 [[TMP14]] to i32
19525 // CHECK21-NEXT:    [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20
19526 // CHECK21-NEXT:    br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]]
19527 // CHECK21:       for.body20:
19528 // CHECK21-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
19529 // CHECK21-NEXT:    [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1
19530 // CHECK21-NEXT:    store i32 [[ADD21]], i32* [[A]], align 4
19531 // CHECK21-NEXT:    [[TMP16:%.*]] = load i16, i16* [[AA]], align 2
19532 // CHECK21-NEXT:    [[CONV22:%.*]] = sext i16 [[TMP16]] to i32
19533 // CHECK21-NEXT:    [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1
19534 // CHECK21-NEXT:    [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16
19535 // CHECK21-NEXT:    store i16 [[CONV24]], i16* [[AA]], align 2
19536 // CHECK21-NEXT:    br label [[FOR_INC25:%.*]]
19537 // CHECK21:       for.inc25:
19538 // CHECK21-NEXT:    [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2
19539 // CHECK21-NEXT:    [[CONV26:%.*]] = sext i16 [[TMP17]] to i32
19540 // CHECK21-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4
19541 // CHECK21-NEXT:    [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16
19542 // CHECK21-NEXT:    store i16 [[CONV28]], i16* [[IT16]], align 2
19543 // CHECK21-NEXT:    br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]]
19544 // CHECK21:       for.end29:
19545 // CHECK21-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
19546 // CHECK21-NEXT:    store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4
19547 // CHECK21-NEXT:    store i8 122, i8* [[IT30]], align 1
19548 // CHECK21-NEXT:    br label [[FOR_COND31:%.*]]
19549 // CHECK21:       for.cond31:
19550 // CHECK21-NEXT:    [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1
19551 // CHECK21-NEXT:    [[CONV32:%.*]] = zext i8 [[TMP19]] to i32
19552 // CHECK21-NEXT:    [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97
19553 // CHECK21-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]]
19554 // CHECK21:       for.body34:
19555 // CHECK21-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A]], align 4
19556 // CHECK21-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1
19557 // CHECK21-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
19558 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
19559 // CHECK21-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4
19560 // CHECK21-NEXT:    [[CONV36:%.*]] = fpext float [[TMP21]] to double
19561 // CHECK21-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
19562 // CHECK21-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
19563 // CHECK21-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
19564 // CHECK21-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
19565 // CHECK21-NEXT:    [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4
19566 // CHECK21-NEXT:    [[CONV40:%.*]] = fpext float [[TMP22]] to double
19567 // CHECK21-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
19568 // CHECK21-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
19569 // CHECK21-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
19570 // CHECK21-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
19571 // CHECK21-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2
19572 // CHECK21-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8
19573 // CHECK21-NEXT:    [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00
19574 // CHECK21-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
19575 // CHECK21-NEXT:    [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]]
19576 // CHECK21-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]]
19577 // CHECK21-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3
19578 // CHECK21-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8
19579 // CHECK21-NEXT:    [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00
19580 // CHECK21-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
19581 // CHECK21-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
19582 // CHECK21-NEXT:    [[TMP26:%.*]] = load i64, i64* [[X]], align 8
19583 // CHECK21-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1
19584 // CHECK21-NEXT:    store i64 [[ADD49]], i64* [[X]], align 8
19585 // CHECK21-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
19586 // CHECK21-NEXT:    [[TMP27:%.*]] = load i8, i8* [[Y]], align 8
19587 // CHECK21-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP27]] to i32
19588 // CHECK21-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
19589 // CHECK21-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
19590 // CHECK21-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 8
19591 // CHECK21-NEXT:    br label [[FOR_INC53:%.*]]
19592 // CHECK21:       for.inc53:
19593 // CHECK21-NEXT:    [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1
19594 // CHECK21-NEXT:    [[CONV54:%.*]] = zext i8 [[TMP28]] to i32
19595 // CHECK21-NEXT:    [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1
19596 // CHECK21-NEXT:    [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8
19597 // CHECK21-NEXT:    store i8 [[CONV56]], i8* [[IT30]], align 1
19598 // CHECK21-NEXT:    br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]]
19599 // CHECK21:       for.end57:
19600 // CHECK21-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
19601 // CHECK21-NEXT:    [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
19602 // CHECK21-NEXT:    call void @llvm.stackrestore(i8* [[TMP30]])
19603 // CHECK21-NEXT:    ret i32 [[TMP29]]
19604 //
19605 //
19606 // CHECK21-LABEL: define {{[^@]+}}@_Z3bari
19607 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
19608 // CHECK21-NEXT:  entry:
19609 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
19610 // CHECK21-NEXT:    [[A:%.*]] = alloca i32, align 4
19611 // CHECK21-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
19612 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
19613 // CHECK21-NEXT:    store i32 0, i32* [[A]], align 4
19614 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
19615 // CHECK21-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
19616 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
19617 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
19618 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
19619 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
19620 // CHECK21-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
19621 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
19622 // CHECK21-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
19623 // CHECK21-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
19624 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
19625 // CHECK21-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
19626 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
19627 // CHECK21-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
19628 // CHECK21-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
19629 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
19630 // CHECK21-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
19631 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
19632 // CHECK21-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
19633 // CHECK21-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
19634 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
19635 // CHECK21-NEXT:    ret i32 [[TMP8]]
19636 //
19637 //
19638 // CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
19639 // CHECK21-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
19640 // CHECK21-NEXT:  entry:
19641 // CHECK21-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
19642 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
19643 // CHECK21-NEXT:    [[B:%.*]] = alloca i32, align 4
19644 // CHECK21-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
19645 // CHECK21-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
19646 // CHECK21-NEXT:    [[IT:%.*]] = alloca i64, align 8
19647 // CHECK21-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
19648 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
19649 // CHECK21-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
19650 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
19651 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
19652 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
19653 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
19654 // CHECK21-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
19655 // CHECK21-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
19656 // CHECK21-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
19657 // CHECK21-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
19658 // CHECK21-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
19659 // CHECK21-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
19660 // CHECK21-NEXT:    store i64 2000, i64* [[IT]], align 8
19661 // CHECK21-NEXT:    br label [[FOR_COND:%.*]]
19662 // CHECK21:       for.cond:
19663 // CHECK21-NEXT:    [[TMP5:%.*]] = load i64, i64* [[IT]], align 8
19664 // CHECK21-NEXT:    [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600
19665 // CHECK21-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
19666 // CHECK21:       for.body:
19667 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
19668 // CHECK21-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP6]] to double
19669 // CHECK21-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
19670 // CHECK21-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
19671 // CHECK21-NEXT:    store double [[ADD2]], double* [[A]], align 8
19672 // CHECK21-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
19673 // CHECK21-NEXT:    [[TMP7:%.*]] = load double, double* [[A3]], align 8
19674 // CHECK21-NEXT:    [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
19675 // CHECK21-NEXT:    store double [[INC]], double* [[A3]], align 8
19676 // CHECK21-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
19677 // CHECK21-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
19678 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
19679 // CHECK21-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
19680 // CHECK21-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
19681 // CHECK21-NEXT:    br label [[FOR_INC:%.*]]
19682 // CHECK21:       for.inc:
19683 // CHECK21-NEXT:    [[TMP9:%.*]] = load i64, i64* [[IT]], align 8
19684 // CHECK21-NEXT:    [[SUB:%.*]] = sub i64 [[TMP9]], 400
19685 // CHECK21-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
19686 // CHECK21-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
19687 // CHECK21:       for.end:
19688 // CHECK21-NEXT:    [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
19689 // CHECK21-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]]
19690 // CHECK21-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
19691 // CHECK21-NEXT:    [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
19692 // CHECK21-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP11]] to i32
19693 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B]], align 4
19694 // CHECK21-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]]
19695 // CHECK21-NEXT:    [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
19696 // CHECK21-NEXT:    call void @llvm.stackrestore(i8* [[TMP13]])
19697 // CHECK21-NEXT:    ret i32 [[ADD9]]
19698 //
19699 //
19700 // CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici
19701 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
19702 // CHECK21-NEXT:  entry:
19703 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
19704 // CHECK21-NEXT:    [[A:%.*]] = alloca i32, align 4
19705 // CHECK21-NEXT:    [[AA:%.*]] = alloca i16, align 2
19706 // CHECK21-NEXT:    [[AAA:%.*]] = alloca i8, align 1
19707 // CHECK21-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
19708 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
19709 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
19710 // CHECK21-NEXT:    store i32 0, i32* [[A]], align 4
19711 // CHECK21-NEXT:    store i16 0, i16* [[AA]], align 2
19712 // CHECK21-NEXT:    store i8 0, i8* [[AAA]], align 1
19713 // CHECK21-NEXT:    store i32 100, i32* [[I]], align 4
19714 // CHECK21-NEXT:    br label [[FOR_COND:%.*]]
19715 // CHECK21:       for.cond:
19716 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
19717 // CHECK21-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10
19718 // CHECK21-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
19719 // CHECK21:       for.body:
19720 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
19721 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
19722 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
19723 // CHECK21-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
19724 // CHECK21-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
19725 // CHECK21-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
19726 // CHECK21-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
19727 // CHECK21-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
19728 // CHECK21-NEXT:    [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1
19729 // CHECK21-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
19730 // CHECK21-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
19731 // CHECK21-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
19732 // CHECK21-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
19733 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
19734 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
19735 // CHECK21-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
19736 // CHECK21-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
19737 // CHECK21-NEXT:    br label [[FOR_INC:%.*]]
19738 // CHECK21:       for.inc:
19739 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
19740 // CHECK21-NEXT:    [[ADD7:%.*]] = add i32 [[TMP5]], 10
19741 // CHECK21-NEXT:    store i32 [[ADD7]], i32* [[I]], align 4
19742 // CHECK21-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
19743 // CHECK21:       for.end:
19744 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
19745 // CHECK21-NEXT:    ret i32 [[TMP6]]
19746 //
19747 //
19748 // CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
19749 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
19750 // CHECK21-NEXT:  entry:
19751 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
19752 // CHECK21-NEXT:    [[A:%.*]] = alloca i32, align 4
19753 // CHECK21-NEXT:    [[AA:%.*]] = alloca i16, align 2
19754 // CHECK21-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
19755 // CHECK21-NEXT:    [[I:%.*]] = alloca i64, align 8
19756 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
19757 // CHECK21-NEXT:    store i32 0, i32* [[A]], align 4
19758 // CHECK21-NEXT:    store i16 0, i16* [[AA]], align 2
19759 // CHECK21-NEXT:    store i64 -10, i64* [[I]], align 8
19760 // CHECK21-NEXT:    br label [[FOR_COND:%.*]]
19761 // CHECK21:       for.cond:
19762 // CHECK21-NEXT:    [[TMP0:%.*]] = load i64, i64* [[I]], align 8
19763 // CHECK21-NEXT:    [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10
19764 // CHECK21-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
19765 // CHECK21:       for.body:
19766 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
19767 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
19768 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
19769 // CHECK21-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
19770 // CHECK21-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
19771 // CHECK21-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
19772 // CHECK21-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
19773 // CHECK21-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
19774 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
19775 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
19776 // CHECK21-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
19777 // CHECK21-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
19778 // CHECK21-NEXT:    br label [[FOR_INC:%.*]]
19779 // CHECK21:       for.inc:
19780 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, i64* [[I]], align 8
19781 // CHECK21-NEXT:    [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3
19782 // CHECK21-NEXT:    store i64 [[ADD4]], i64* [[I]], align 8
19783 // CHECK21-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
19784 // CHECK21:       for.end:
19785 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
19786 // CHECK21-NEXT:    ret i32 [[TMP5]]
19787 //
19788 //
19789 // CHECK22-LABEL: define {{[^@]+}}@_Z7get_valv
19790 // CHECK22-SAME: () #[[ATTR0:[0-9]+]] {
19791 // CHECK22-NEXT:  entry:
19792 // CHECK22-NEXT:    ret i64 0
19793 //
19794 //
19795 // CHECK22-LABEL: define {{[^@]+}}@_Z3fooi
19796 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
19797 // CHECK22-NEXT:  entry:
19798 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
19799 // CHECK22-NEXT:    [[A:%.*]] = alloca i32, align 4
19800 // CHECK22-NEXT:    [[AA:%.*]] = alloca i16, align 2
19801 // CHECK22-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
19802 // CHECK22-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
19803 // CHECK22-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
19804 // CHECK22-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
19805 // CHECK22-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
19806 // CHECK22-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
19807 // CHECK22-NEXT:    [[I:%.*]] = alloca i32, align 4
19808 // CHECK22-NEXT:    [[K:%.*]] = alloca i64, align 8
19809 // CHECK22-NEXT:    [[I2:%.*]] = alloca i32, align 4
19810 // CHECK22-NEXT:    [[LIN:%.*]] = alloca i32, align 4
19811 // CHECK22-NEXT:    [[IT:%.*]] = alloca i64, align 8
19812 // CHECK22-NEXT:    [[IT16:%.*]] = alloca i16, align 2
19813 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
19814 // CHECK22-NEXT:    [[IT30:%.*]] = alloca i8, align 1
19815 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
19816 // CHECK22-NEXT:    store i32 0, i32* [[A]], align 4
19817 // CHECK22-NEXT:    store i16 0, i16* [[AA]], align 2
19818 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
19819 // CHECK22-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
19820 // CHECK22-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
19821 // CHECK22-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
19822 // CHECK22-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
19823 // CHECK22-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
19824 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
19825 // CHECK22-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
19826 // CHECK22-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
19827 // CHECK22-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
19828 // CHECK22-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
19829 // CHECK22-NEXT:    store i32 3, i32* [[I]], align 4
19830 // CHECK22-NEXT:    br label [[FOR_COND:%.*]]
19831 // CHECK22:       for.cond:
19832 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I]], align 4
19833 // CHECK22-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32
19834 // CHECK22-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
19835 // CHECK22:       for.body:
19836 // CHECK22-NEXT:    br label [[FOR_INC:%.*]]
19837 // CHECK22:       for.inc:
19838 // CHECK22-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
19839 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP7]], 5
19840 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
19841 // CHECK22-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
19842 // CHECK22:       for.end:
19843 // CHECK22-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
19844 // CHECK22-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
19845 // CHECK22-NEXT:    store i32 10, i32* [[I2]], align 4
19846 // CHECK22-NEXT:    br label [[FOR_COND3:%.*]]
19847 // CHECK22:       for.cond3:
19848 // CHECK22-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I2]], align 4
19849 // CHECK22-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1
19850 // CHECK22-NEXT:    br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]]
19851 // CHECK22:       for.body5:
19852 // CHECK22-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
19853 // CHECK22-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1
19854 // CHECK22-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
19855 // CHECK22-NEXT:    br label [[FOR_INC7:%.*]]
19856 // CHECK22:       for.inc7:
19857 // CHECK22-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I2]], align 4
19858 // CHECK22-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP10]], -1
19859 // CHECK22-NEXT:    store i32 [[DEC]], i32* [[I2]], align 4
19860 // CHECK22-NEXT:    br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]]
19861 // CHECK22:       for.end8:
19862 // CHECK22-NEXT:    store i32 12, i32* [[LIN]], align 4
19863 // CHECK22-NEXT:    store i64 2000, i64* [[IT]], align 8
19864 // CHECK22-NEXT:    br label [[FOR_COND9:%.*]]
19865 // CHECK22:       for.cond9:
19866 // CHECK22-NEXT:    [[TMP11:%.*]] = load i64, i64* [[IT]], align 8
19867 // CHECK22-NEXT:    [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600
19868 // CHECK22-NEXT:    br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]]
19869 // CHECK22:       for.body11:
19870 // CHECK22-NEXT:    [[TMP12:%.*]] = load i16, i16* [[AA]], align 2
19871 // CHECK22-NEXT:    [[CONV:%.*]] = sext i16 [[TMP12]] to i32
19872 // CHECK22-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV]], 1
19873 // CHECK22-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
19874 // CHECK22-NEXT:    store i16 [[CONV13]], i16* [[AA]], align 2
19875 // CHECK22-NEXT:    br label [[FOR_INC14:%.*]]
19876 // CHECK22:       for.inc14:
19877 // CHECK22-NEXT:    [[TMP13:%.*]] = load i64, i64* [[IT]], align 8
19878 // CHECK22-NEXT:    [[SUB:%.*]] = sub i64 [[TMP13]], 400
19879 // CHECK22-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
19880 // CHECK22-NEXT:    br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]]
19881 // CHECK22:       for.end15:
19882 // CHECK22-NEXT:    store i16 6, i16* [[IT16]], align 2
19883 // CHECK22-NEXT:    br label [[FOR_COND17:%.*]]
19884 // CHECK22:       for.cond17:
19885 // CHECK22-NEXT:    [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2
19886 // CHECK22-NEXT:    [[CONV18:%.*]] = sext i16 [[TMP14]] to i32
19887 // CHECK22-NEXT:    [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20
19888 // CHECK22-NEXT:    br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]]
19889 // CHECK22:       for.body20:
19890 // CHECK22-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
19891 // CHECK22-NEXT:    [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1
19892 // CHECK22-NEXT:    store i32 [[ADD21]], i32* [[A]], align 4
19893 // CHECK22-NEXT:    [[TMP16:%.*]] = load i16, i16* [[AA]], align 2
19894 // CHECK22-NEXT:    [[CONV22:%.*]] = sext i16 [[TMP16]] to i32
19895 // CHECK22-NEXT:    [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1
19896 // CHECK22-NEXT:    [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16
19897 // CHECK22-NEXT:    store i16 [[CONV24]], i16* [[AA]], align 2
19898 // CHECK22-NEXT:    br label [[FOR_INC25:%.*]]
19899 // CHECK22:       for.inc25:
19900 // CHECK22-NEXT:    [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2
19901 // CHECK22-NEXT:    [[CONV26:%.*]] = sext i16 [[TMP17]] to i32
19902 // CHECK22-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4
19903 // CHECK22-NEXT:    [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16
19904 // CHECK22-NEXT:    store i16 [[CONV28]], i16* [[IT16]], align 2
19905 // CHECK22-NEXT:    br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]]
19906 // CHECK22:       for.end29:
19907 // CHECK22-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
19908 // CHECK22-NEXT:    store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4
19909 // CHECK22-NEXT:    store i8 122, i8* [[IT30]], align 1
19910 // CHECK22-NEXT:    br label [[FOR_COND31:%.*]]
19911 // CHECK22:       for.cond31:
19912 // CHECK22-NEXT:    [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1
19913 // CHECK22-NEXT:    [[CONV32:%.*]] = zext i8 [[TMP19]] to i32
19914 // CHECK22-NEXT:    [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97
19915 // CHECK22-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]]
19916 // CHECK22:       for.body34:
19917 // CHECK22-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A]], align 4
19918 // CHECK22-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1
19919 // CHECK22-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
19920 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
19921 // CHECK22-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4
19922 // CHECK22-NEXT:    [[CONV36:%.*]] = fpext float [[TMP21]] to double
19923 // CHECK22-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
19924 // CHECK22-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
19925 // CHECK22-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
19926 // CHECK22-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
19927 // CHECK22-NEXT:    [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4
19928 // CHECK22-NEXT:    [[CONV40:%.*]] = fpext float [[TMP22]] to double
19929 // CHECK22-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
19930 // CHECK22-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
19931 // CHECK22-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
19932 // CHECK22-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
19933 // CHECK22-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2
19934 // CHECK22-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8
19935 // CHECK22-NEXT:    [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00
19936 // CHECK22-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
19937 // CHECK22-NEXT:    [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]]
19938 // CHECK22-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]]
19939 // CHECK22-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3
19940 // CHECK22-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8
19941 // CHECK22-NEXT:    [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00
19942 // CHECK22-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
19943 // CHECK22-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
19944 // CHECK22-NEXT:    [[TMP26:%.*]] = load i64, i64* [[X]], align 8
19945 // CHECK22-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1
19946 // CHECK22-NEXT:    store i64 [[ADD49]], i64* [[X]], align 8
19947 // CHECK22-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
19948 // CHECK22-NEXT:    [[TMP27:%.*]] = load i8, i8* [[Y]], align 8
19949 // CHECK22-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP27]] to i32
19950 // CHECK22-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
19951 // CHECK22-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
19952 // CHECK22-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 8
19953 // CHECK22-NEXT:    br label [[FOR_INC53:%.*]]
19954 // CHECK22:       for.inc53:
19955 // CHECK22-NEXT:    [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1
19956 // CHECK22-NEXT:    [[CONV54:%.*]] = zext i8 [[TMP28]] to i32
19957 // CHECK22-NEXT:    [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1
19958 // CHECK22-NEXT:    [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8
19959 // CHECK22-NEXT:    store i8 [[CONV56]], i8* [[IT30]], align 1
19960 // CHECK22-NEXT:    br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]]
19961 // CHECK22:       for.end57:
19962 // CHECK22-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
19963 // CHECK22-NEXT:    [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
19964 // CHECK22-NEXT:    call void @llvm.stackrestore(i8* [[TMP30]])
19965 // CHECK22-NEXT:    ret i32 [[TMP29]]
19966 //
19967 //
19968 // CHECK22-LABEL: define {{[^@]+}}@_Z3bari
19969 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
19970 // CHECK22-NEXT:  entry:
19971 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
19972 // CHECK22-NEXT:    [[A:%.*]] = alloca i32, align 4
19973 // CHECK22-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
19974 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
19975 // CHECK22-NEXT:    store i32 0, i32* [[A]], align 4
19976 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
19977 // CHECK22-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
19978 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
19979 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
19980 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
19981 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
19982 // CHECK22-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
19983 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
19984 // CHECK22-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
19985 // CHECK22-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
19986 // CHECK22-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
19987 // CHECK22-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
19988 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
19989 // CHECK22-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
19990 // CHECK22-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
19991 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
19992 // CHECK22-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
19993 // CHECK22-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
19994 // CHECK22-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
19995 // CHECK22-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
19996 // CHECK22-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
19997 // CHECK22-NEXT:    ret i32 [[TMP8]]
19998 //
19999 //
20000 // CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
20001 // CHECK22-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
20002 // CHECK22-NEXT:  entry:
20003 // CHECK22-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
20004 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20005 // CHECK22-NEXT:    [[B:%.*]] = alloca i32, align 4
20006 // CHECK22-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
20007 // CHECK22-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
20008 // CHECK22-NEXT:    [[IT:%.*]] = alloca i64, align 8
20009 // CHECK22-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
20010 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20011 // CHECK22-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
20012 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
20013 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
20014 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
20015 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
20016 // CHECK22-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
20017 // CHECK22-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
20018 // CHECK22-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
20019 // CHECK22-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
20020 // CHECK22-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
20021 // CHECK22-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
20022 // CHECK22-NEXT:    store i64 2000, i64* [[IT]], align 8
20023 // CHECK22-NEXT:    br label [[FOR_COND:%.*]]
20024 // CHECK22:       for.cond:
20025 // CHECK22-NEXT:    [[TMP5:%.*]] = load i64, i64* [[IT]], align 8
20026 // CHECK22-NEXT:    [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600
20027 // CHECK22-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20028 // CHECK22:       for.body:
20029 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
20030 // CHECK22-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP6]] to double
20031 // CHECK22-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
20032 // CHECK22-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
20033 // CHECK22-NEXT:    store double [[ADD2]], double* [[A]], align 8
20034 // CHECK22-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
20035 // CHECK22-NEXT:    [[TMP7:%.*]] = load double, double* [[A3]], align 8
20036 // CHECK22-NEXT:    [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
20037 // CHECK22-NEXT:    store double [[INC]], double* [[A3]], align 8
20038 // CHECK22-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
20039 // CHECK22-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
20040 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
20041 // CHECK22-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
20042 // CHECK22-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
20043 // CHECK22-NEXT:    br label [[FOR_INC:%.*]]
20044 // CHECK22:       for.inc:
20045 // CHECK22-NEXT:    [[TMP9:%.*]] = load i64, i64* [[IT]], align 8
20046 // CHECK22-NEXT:    [[SUB:%.*]] = sub i64 [[TMP9]], 400
20047 // CHECK22-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
20048 // CHECK22-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
20049 // CHECK22:       for.end:
20050 // CHECK22-NEXT:    [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
20051 // CHECK22-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]]
20052 // CHECK22-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
20053 // CHECK22-NEXT:    [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
20054 // CHECK22-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP11]] to i32
20055 // CHECK22-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B]], align 4
20056 // CHECK22-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]]
20057 // CHECK22-NEXT:    [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
20058 // CHECK22-NEXT:    call void @llvm.stackrestore(i8* [[TMP13]])
20059 // CHECK22-NEXT:    ret i32 [[ADD9]]
20060 //
20061 //
20062 // CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici
20063 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
20064 // CHECK22-NEXT:  entry:
20065 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20066 // CHECK22-NEXT:    [[A:%.*]] = alloca i32, align 4
20067 // CHECK22-NEXT:    [[AA:%.*]] = alloca i16, align 2
20068 // CHECK22-NEXT:    [[AAA:%.*]] = alloca i8, align 1
20069 // CHECK22-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
20070 // CHECK22-NEXT:    [[I:%.*]] = alloca i32, align 4
20071 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20072 // CHECK22-NEXT:    store i32 0, i32* [[A]], align 4
20073 // CHECK22-NEXT:    store i16 0, i16* [[AA]], align 2
20074 // CHECK22-NEXT:    store i8 0, i8* [[AAA]], align 1
20075 // CHECK22-NEXT:    store i32 100, i32* [[I]], align 4
20076 // CHECK22-NEXT:    br label [[FOR_COND:%.*]]
20077 // CHECK22:       for.cond:
20078 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
20079 // CHECK22-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10
20080 // CHECK22-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20081 // CHECK22:       for.body:
20082 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
20083 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
20084 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
20085 // CHECK22-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
20086 // CHECK22-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
20087 // CHECK22-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
20088 // CHECK22-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
20089 // CHECK22-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
20090 // CHECK22-NEXT:    [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1
20091 // CHECK22-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
20092 // CHECK22-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
20093 // CHECK22-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
20094 // CHECK22-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
20095 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
20096 // CHECK22-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
20097 // CHECK22-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
20098 // CHECK22-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
20099 // CHECK22-NEXT:    br label [[FOR_INC:%.*]]
20100 // CHECK22:       for.inc:
20101 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
20102 // CHECK22-NEXT:    [[ADD7:%.*]] = add i32 [[TMP5]], 10
20103 // CHECK22-NEXT:    store i32 [[ADD7]], i32* [[I]], align 4
20104 // CHECK22-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
20105 // CHECK22:       for.end:
20106 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
20107 // CHECK22-NEXT:    ret i32 [[TMP6]]
20108 //
20109 //
20110 // CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
20111 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
20112 // CHECK22-NEXT:  entry:
20113 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20114 // CHECK22-NEXT:    [[A:%.*]] = alloca i32, align 4
20115 // CHECK22-NEXT:    [[AA:%.*]] = alloca i16, align 2
20116 // CHECK22-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
20117 // CHECK22-NEXT:    [[I:%.*]] = alloca i64, align 8
20118 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20119 // CHECK22-NEXT:    store i32 0, i32* [[A]], align 4
20120 // CHECK22-NEXT:    store i16 0, i16* [[AA]], align 2
20121 // CHECK22-NEXT:    store i64 -10, i64* [[I]], align 8
20122 // CHECK22-NEXT:    br label [[FOR_COND:%.*]]
20123 // CHECK22:       for.cond:
20124 // CHECK22-NEXT:    [[TMP0:%.*]] = load i64, i64* [[I]], align 8
20125 // CHECK22-NEXT:    [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10
20126 // CHECK22-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20127 // CHECK22:       for.body:
20128 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
20129 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
20130 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
20131 // CHECK22-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
20132 // CHECK22-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
20133 // CHECK22-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
20134 // CHECK22-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
20135 // CHECK22-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
20136 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
20137 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
20138 // CHECK22-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
20139 // CHECK22-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
20140 // CHECK22-NEXT:    br label [[FOR_INC:%.*]]
20141 // CHECK22:       for.inc:
20142 // CHECK22-NEXT:    [[TMP4:%.*]] = load i64, i64* [[I]], align 8
20143 // CHECK22-NEXT:    [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3
20144 // CHECK22-NEXT:    store i64 [[ADD4]], i64* [[I]], align 8
20145 // CHECK22-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
20146 // CHECK22:       for.end:
20147 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
20148 // CHECK22-NEXT:    ret i32 [[TMP5]]
20149 //
20150 //
20151 // CHECK23-LABEL: define {{[^@]+}}@_Z7get_valv
20152 // CHECK23-SAME: () #[[ATTR0:[0-9]+]] {
20153 // CHECK23-NEXT:  entry:
20154 // CHECK23-NEXT:    ret i64 0
20155 //
20156 //
20157 // CHECK23-LABEL: define {{[^@]+}}@_Z3fooi
20158 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
20159 // CHECK23-NEXT:  entry:
20160 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20161 // CHECK23-NEXT:    [[A:%.*]] = alloca i32, align 4
20162 // CHECK23-NEXT:    [[AA:%.*]] = alloca i16, align 2
20163 // CHECK23-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
20164 // CHECK23-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
20165 // CHECK23-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
20166 // CHECK23-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
20167 // CHECK23-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
20168 // CHECK23-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
20169 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
20170 // CHECK23-NEXT:    [[K:%.*]] = alloca i64, align 8
20171 // CHECK23-NEXT:    [[I2:%.*]] = alloca i32, align 4
20172 // CHECK23-NEXT:    [[LIN:%.*]] = alloca i32, align 4
20173 // CHECK23-NEXT:    [[IT:%.*]] = alloca i64, align 8
20174 // CHECK23-NEXT:    [[IT16:%.*]] = alloca i16, align 2
20175 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
20176 // CHECK23-NEXT:    [[IT30:%.*]] = alloca i8, align 1
20177 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20178 // CHECK23-NEXT:    store i32 0, i32* [[A]], align 4
20179 // CHECK23-NEXT:    store i16 0, i16* [[AA]], align 2
20180 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
20181 // CHECK23-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
20182 // CHECK23-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
20183 // CHECK23-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
20184 // CHECK23-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
20185 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
20186 // CHECK23-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
20187 // CHECK23-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
20188 // CHECK23-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
20189 // CHECK23-NEXT:    store i32 3, i32* [[I]], align 4
20190 // CHECK23-NEXT:    br label [[FOR_COND:%.*]]
20191 // CHECK23:       for.cond:
20192 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
20193 // CHECK23-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32
20194 // CHECK23-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20195 // CHECK23:       for.body:
20196 // CHECK23-NEXT:    br label [[FOR_INC:%.*]]
20197 // CHECK23:       for.inc:
20198 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
20199 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP5]], 5
20200 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
20201 // CHECK23-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
20202 // CHECK23:       for.end:
20203 // CHECK23-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
20204 // CHECK23-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
20205 // CHECK23-NEXT:    store i32 10, i32* [[I2]], align 4
20206 // CHECK23-NEXT:    br label [[FOR_COND3:%.*]]
20207 // CHECK23:       for.cond3:
20208 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I2]], align 4
20209 // CHECK23-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1
20210 // CHECK23-NEXT:    br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]]
20211 // CHECK23:       for.body5:
20212 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
20213 // CHECK23-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1
20214 // CHECK23-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
20215 // CHECK23-NEXT:    br label [[FOR_INC7:%.*]]
20216 // CHECK23:       for.inc7:
20217 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I2]], align 4
20218 // CHECK23-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP8]], -1
20219 // CHECK23-NEXT:    store i32 [[DEC]], i32* [[I2]], align 4
20220 // CHECK23-NEXT:    br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]]
20221 // CHECK23:       for.end8:
20222 // CHECK23-NEXT:    store i32 12, i32* [[LIN]], align 4
20223 // CHECK23-NEXT:    store i64 2000, i64* [[IT]], align 8
20224 // CHECK23-NEXT:    br label [[FOR_COND9:%.*]]
20225 // CHECK23:       for.cond9:
20226 // CHECK23-NEXT:    [[TMP9:%.*]] = load i64, i64* [[IT]], align 8
20227 // CHECK23-NEXT:    [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600
20228 // CHECK23-NEXT:    br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]]
20229 // CHECK23:       for.body11:
20230 // CHECK23-NEXT:    [[TMP10:%.*]] = load i16, i16* [[AA]], align 2
20231 // CHECK23-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
20232 // CHECK23-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV]], 1
20233 // CHECK23-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
20234 // CHECK23-NEXT:    store i16 [[CONV13]], i16* [[AA]], align 2
20235 // CHECK23-NEXT:    br label [[FOR_INC14:%.*]]
20236 // CHECK23:       for.inc14:
20237 // CHECK23-NEXT:    [[TMP11:%.*]] = load i64, i64* [[IT]], align 8
20238 // CHECK23-NEXT:    [[SUB:%.*]] = sub i64 [[TMP11]], 400
20239 // CHECK23-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
20240 // CHECK23-NEXT:    br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]]
20241 // CHECK23:       for.end15:
20242 // CHECK23-NEXT:    store i16 6, i16* [[IT16]], align 2
20243 // CHECK23-NEXT:    br label [[FOR_COND17:%.*]]
20244 // CHECK23:       for.cond17:
20245 // CHECK23-NEXT:    [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2
20246 // CHECK23-NEXT:    [[CONV18:%.*]] = sext i16 [[TMP12]] to i32
20247 // CHECK23-NEXT:    [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20
20248 // CHECK23-NEXT:    br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]]
20249 // CHECK23:       for.body20:
20250 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4
20251 // CHECK23-NEXT:    [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1
20252 // CHECK23-NEXT:    store i32 [[ADD21]], i32* [[A]], align 4
20253 // CHECK23-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2
20254 // CHECK23-NEXT:    [[CONV22:%.*]] = sext i16 [[TMP14]] to i32
20255 // CHECK23-NEXT:    [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1
20256 // CHECK23-NEXT:    [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16
20257 // CHECK23-NEXT:    store i16 [[CONV24]], i16* [[AA]], align 2
20258 // CHECK23-NEXT:    br label [[FOR_INC25:%.*]]
20259 // CHECK23:       for.inc25:
20260 // CHECK23-NEXT:    [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2
20261 // CHECK23-NEXT:    [[CONV26:%.*]] = sext i16 [[TMP15]] to i32
20262 // CHECK23-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4
20263 // CHECK23-NEXT:    [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16
20264 // CHECK23-NEXT:    store i16 [[CONV28]], i16* [[IT16]], align 2
20265 // CHECK23-NEXT:    br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]]
20266 // CHECK23:       for.end29:
20267 // CHECK23-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4
20268 // CHECK23-NEXT:    store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4
20269 // CHECK23-NEXT:    store i8 122, i8* [[IT30]], align 1
20270 // CHECK23-NEXT:    br label [[FOR_COND31:%.*]]
20271 // CHECK23:       for.cond31:
20272 // CHECK23-NEXT:    [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1
20273 // CHECK23-NEXT:    [[CONV32:%.*]] = zext i8 [[TMP17]] to i32
20274 // CHECK23-NEXT:    [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97
20275 // CHECK23-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]]
20276 // CHECK23:       for.body34:
20277 // CHECK23-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
20278 // CHECK23-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1
20279 // CHECK23-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
20280 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
20281 // CHECK23-NEXT:    [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4
20282 // CHECK23-NEXT:    [[CONV36:%.*]] = fpext float [[TMP19]] to double
20283 // CHECK23-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
20284 // CHECK23-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
20285 // CHECK23-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
20286 // CHECK23-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
20287 // CHECK23-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4
20288 // CHECK23-NEXT:    [[CONV40:%.*]] = fpext float [[TMP20]] to double
20289 // CHECK23-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
20290 // CHECK23-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
20291 // CHECK23-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
20292 // CHECK23-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
20293 // CHECK23-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2
20294 // CHECK23-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8
20295 // CHECK23-NEXT:    [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00
20296 // CHECK23-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
20297 // CHECK23-NEXT:    [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]]
20298 // CHECK23-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]]
20299 // CHECK23-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3
20300 // CHECK23-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8
20301 // CHECK23-NEXT:    [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00
20302 // CHECK23-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
20303 // CHECK23-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
20304 // CHECK23-NEXT:    [[TMP24:%.*]] = load i64, i64* [[X]], align 4
20305 // CHECK23-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1
20306 // CHECK23-NEXT:    store i64 [[ADD49]], i64* [[X]], align 4
20307 // CHECK23-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
20308 // CHECK23-NEXT:    [[TMP25:%.*]] = load i8, i8* [[Y]], align 4
20309 // CHECK23-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP25]] to i32
20310 // CHECK23-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
20311 // CHECK23-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
20312 // CHECK23-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 4
20313 // CHECK23-NEXT:    br label [[FOR_INC53:%.*]]
20314 // CHECK23:       for.inc53:
20315 // CHECK23-NEXT:    [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1
20316 // CHECK23-NEXT:    [[CONV54:%.*]] = zext i8 [[TMP26]] to i32
20317 // CHECK23-NEXT:    [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1
20318 // CHECK23-NEXT:    [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8
20319 // CHECK23-NEXT:    store i8 [[CONV56]], i8* [[IT30]], align 1
20320 // CHECK23-NEXT:    br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]]
20321 // CHECK23:       for.end57:
20322 // CHECK23-NEXT:    [[TMP27:%.*]] = load i32, i32* [[A]], align 4
20323 // CHECK23-NEXT:    [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
20324 // CHECK23-NEXT:    call void @llvm.stackrestore(i8* [[TMP28]])
20325 // CHECK23-NEXT:    ret i32 [[TMP27]]
20326 //
20327 //
20328 // CHECK23-LABEL: define {{[^@]+}}@_Z3bari
20329 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
20330 // CHECK23-NEXT:  entry:
20331 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20332 // CHECK23-NEXT:    [[A:%.*]] = alloca i32, align 4
20333 // CHECK23-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
20334 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20335 // CHECK23-NEXT:    store i32 0, i32* [[A]], align 4
20336 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
20337 // CHECK23-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
20338 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
20339 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
20340 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
20341 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
20342 // CHECK23-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
20343 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
20344 // CHECK23-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
20345 // CHECK23-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
20346 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
20347 // CHECK23-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
20348 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
20349 // CHECK23-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
20350 // CHECK23-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
20351 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
20352 // CHECK23-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
20353 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
20354 // CHECK23-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
20355 // CHECK23-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
20356 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
20357 // CHECK23-NEXT:    ret i32 [[TMP8]]
20358 //
20359 //
20360 // CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
20361 // CHECK23-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
20362 // CHECK23-NEXT:  entry:
20363 // CHECK23-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
20364 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20365 // CHECK23-NEXT:    [[B:%.*]] = alloca i32, align 4
20366 // CHECK23-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
20367 // CHECK23-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
20368 // CHECK23-NEXT:    [[IT:%.*]] = alloca i64, align 8
20369 // CHECK23-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
20370 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20371 // CHECK23-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
20372 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
20373 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
20374 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
20375 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
20376 // CHECK23-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
20377 // CHECK23-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
20378 // CHECK23-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
20379 // CHECK23-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
20380 // CHECK23-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
20381 // CHECK23-NEXT:    store i64 2000, i64* [[IT]], align 8
20382 // CHECK23-NEXT:    br label [[FOR_COND:%.*]]
20383 // CHECK23:       for.cond:
20384 // CHECK23-NEXT:    [[TMP4:%.*]] = load i64, i64* [[IT]], align 8
20385 // CHECK23-NEXT:    [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600
20386 // CHECK23-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20387 // CHECK23:       for.body:
20388 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
20389 // CHECK23-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
20390 // CHECK23-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
20391 // CHECK23-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
20392 // CHECK23-NEXT:    store double [[ADD2]], double* [[A]], align 4
20393 // CHECK23-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
20394 // CHECK23-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 4
20395 // CHECK23-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
20396 // CHECK23-NEXT:    store double [[INC]], double* [[A3]], align 4
20397 // CHECK23-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
20398 // CHECK23-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
20399 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
20400 // CHECK23-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
20401 // CHECK23-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
20402 // CHECK23-NEXT:    br label [[FOR_INC:%.*]]
20403 // CHECK23:       for.inc:
20404 // CHECK23-NEXT:    [[TMP8:%.*]] = load i64, i64* [[IT]], align 8
20405 // CHECK23-NEXT:    [[SUB:%.*]] = sub i64 [[TMP8]], 400
20406 // CHECK23-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
20407 // CHECK23-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
20408 // CHECK23:       for.end:
20409 // CHECK23-NEXT:    [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]]
20410 // CHECK23-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]]
20411 // CHECK23-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
20412 // CHECK23-NEXT:    [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
20413 // CHECK23-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP10]] to i32
20414 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4
20415 // CHECK23-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]]
20416 // CHECK23-NEXT:    [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
20417 // CHECK23-NEXT:    call void @llvm.stackrestore(i8* [[TMP12]])
20418 // CHECK23-NEXT:    ret i32 [[ADD9]]
20419 //
20420 //
20421 // CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici
20422 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
20423 // CHECK23-NEXT:  entry:
20424 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20425 // CHECK23-NEXT:    [[A:%.*]] = alloca i32, align 4
20426 // CHECK23-NEXT:    [[AA:%.*]] = alloca i16, align 2
20427 // CHECK23-NEXT:    [[AAA:%.*]] = alloca i8, align 1
20428 // CHECK23-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
20429 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
20430 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20431 // CHECK23-NEXT:    store i32 0, i32* [[A]], align 4
20432 // CHECK23-NEXT:    store i16 0, i16* [[AA]], align 2
20433 // CHECK23-NEXT:    store i8 0, i8* [[AAA]], align 1
20434 // CHECK23-NEXT:    store i32 100, i32* [[I]], align 4
20435 // CHECK23-NEXT:    br label [[FOR_COND:%.*]]
20436 // CHECK23:       for.cond:
20437 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
20438 // CHECK23-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10
20439 // CHECK23-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20440 // CHECK23:       for.body:
20441 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
20442 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
20443 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
20444 // CHECK23-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
20445 // CHECK23-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
20446 // CHECK23-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
20447 // CHECK23-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
20448 // CHECK23-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
20449 // CHECK23-NEXT:    [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1
20450 // CHECK23-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
20451 // CHECK23-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
20452 // CHECK23-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
20453 // CHECK23-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
20454 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
20455 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
20456 // CHECK23-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
20457 // CHECK23-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
20458 // CHECK23-NEXT:    br label [[FOR_INC:%.*]]
20459 // CHECK23:       for.inc:
20460 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
20461 // CHECK23-NEXT:    [[ADD7:%.*]] = add i32 [[TMP5]], 10
20462 // CHECK23-NEXT:    store i32 [[ADD7]], i32* [[I]], align 4
20463 // CHECK23-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
20464 // CHECK23:       for.end:
20465 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
20466 // CHECK23-NEXT:    ret i32 [[TMP6]]
20467 //
20468 //
20469 // CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
20470 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
20471 // CHECK23-NEXT:  entry:
20472 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20473 // CHECK23-NEXT:    [[A:%.*]] = alloca i32, align 4
20474 // CHECK23-NEXT:    [[AA:%.*]] = alloca i16, align 2
20475 // CHECK23-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
20476 // CHECK23-NEXT:    [[I:%.*]] = alloca i64, align 8
20477 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20478 // CHECK23-NEXT:    store i32 0, i32* [[A]], align 4
20479 // CHECK23-NEXT:    store i16 0, i16* [[AA]], align 2
20480 // CHECK23-NEXT:    store i64 -10, i64* [[I]], align 8
20481 // CHECK23-NEXT:    br label [[FOR_COND:%.*]]
20482 // CHECK23:       for.cond:
20483 // CHECK23-NEXT:    [[TMP0:%.*]] = load i64, i64* [[I]], align 8
20484 // CHECK23-NEXT:    [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10
20485 // CHECK23-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20486 // CHECK23:       for.body:
20487 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
20488 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
20489 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
20490 // CHECK23-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
20491 // CHECK23-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
20492 // CHECK23-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
20493 // CHECK23-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
20494 // CHECK23-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
20495 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
20496 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
20497 // CHECK23-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
20498 // CHECK23-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
20499 // CHECK23-NEXT:    br label [[FOR_INC:%.*]]
20500 // CHECK23:       for.inc:
20501 // CHECK23-NEXT:    [[TMP4:%.*]] = load i64, i64* [[I]], align 8
20502 // CHECK23-NEXT:    [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3
20503 // CHECK23-NEXT:    store i64 [[ADD4]], i64* [[I]], align 8
20504 // CHECK23-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
20505 // CHECK23:       for.end:
20506 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
20507 // CHECK23-NEXT:    ret i32 [[TMP5]]
20508 //
20509 //
20510 // CHECK24-LABEL: define {{[^@]+}}@_Z7get_valv
20511 // CHECK24-SAME: () #[[ATTR0:[0-9]+]] {
20512 // CHECK24-NEXT:  entry:
20513 // CHECK24-NEXT:    ret i64 0
20514 //
20515 //
20516 // CHECK24-LABEL: define {{[^@]+}}@_Z3fooi
20517 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
20518 // CHECK24-NEXT:  entry:
20519 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20520 // CHECK24-NEXT:    [[A:%.*]] = alloca i32, align 4
20521 // CHECK24-NEXT:    [[AA:%.*]] = alloca i16, align 2
20522 // CHECK24-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
20523 // CHECK24-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
20524 // CHECK24-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
20525 // CHECK24-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
20526 // CHECK24-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
20527 // CHECK24-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
20528 // CHECK24-NEXT:    [[I:%.*]] = alloca i32, align 4
20529 // CHECK24-NEXT:    [[K:%.*]] = alloca i64, align 8
20530 // CHECK24-NEXT:    [[I2:%.*]] = alloca i32, align 4
20531 // CHECK24-NEXT:    [[LIN:%.*]] = alloca i32, align 4
20532 // CHECK24-NEXT:    [[IT:%.*]] = alloca i64, align 8
20533 // CHECK24-NEXT:    [[IT16:%.*]] = alloca i16, align 2
20534 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
20535 // CHECK24-NEXT:    [[IT30:%.*]] = alloca i8, align 1
20536 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20537 // CHECK24-NEXT:    store i32 0, i32* [[A]], align 4
20538 // CHECK24-NEXT:    store i16 0, i16* [[AA]], align 2
20539 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
20540 // CHECK24-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
20541 // CHECK24-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
20542 // CHECK24-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
20543 // CHECK24-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
20544 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
20545 // CHECK24-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
20546 // CHECK24-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
20547 // CHECK24-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
20548 // CHECK24-NEXT:    store i32 3, i32* [[I]], align 4
20549 // CHECK24-NEXT:    br label [[FOR_COND:%.*]]
20550 // CHECK24:       for.cond:
20551 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
20552 // CHECK24-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32
20553 // CHECK24-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20554 // CHECK24:       for.body:
20555 // CHECK24-NEXT:    br label [[FOR_INC:%.*]]
20556 // CHECK24:       for.inc:
20557 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
20558 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP5]], 5
20559 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
20560 // CHECK24-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
20561 // CHECK24:       for.end:
20562 // CHECK24-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
20563 // CHECK24-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
20564 // CHECK24-NEXT:    store i32 10, i32* [[I2]], align 4
20565 // CHECK24-NEXT:    br label [[FOR_COND3:%.*]]
20566 // CHECK24:       for.cond3:
20567 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I2]], align 4
20568 // CHECK24-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1
20569 // CHECK24-NEXT:    br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]]
20570 // CHECK24:       for.body5:
20571 // CHECK24-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
20572 // CHECK24-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1
20573 // CHECK24-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
20574 // CHECK24-NEXT:    br label [[FOR_INC7:%.*]]
20575 // CHECK24:       for.inc7:
20576 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I2]], align 4
20577 // CHECK24-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP8]], -1
20578 // CHECK24-NEXT:    store i32 [[DEC]], i32* [[I2]], align 4
20579 // CHECK24-NEXT:    br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]]
20580 // CHECK24:       for.end8:
20581 // CHECK24-NEXT:    store i32 12, i32* [[LIN]], align 4
20582 // CHECK24-NEXT:    store i64 2000, i64* [[IT]], align 8
20583 // CHECK24-NEXT:    br label [[FOR_COND9:%.*]]
20584 // CHECK24:       for.cond9:
20585 // CHECK24-NEXT:    [[TMP9:%.*]] = load i64, i64* [[IT]], align 8
20586 // CHECK24-NEXT:    [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600
20587 // CHECK24-NEXT:    br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]]
20588 // CHECK24:       for.body11:
20589 // CHECK24-NEXT:    [[TMP10:%.*]] = load i16, i16* [[AA]], align 2
20590 // CHECK24-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
20591 // CHECK24-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV]], 1
20592 // CHECK24-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
20593 // CHECK24-NEXT:    store i16 [[CONV13]], i16* [[AA]], align 2
20594 // CHECK24-NEXT:    br label [[FOR_INC14:%.*]]
20595 // CHECK24:       for.inc14:
20596 // CHECK24-NEXT:    [[TMP11:%.*]] = load i64, i64* [[IT]], align 8
20597 // CHECK24-NEXT:    [[SUB:%.*]] = sub i64 [[TMP11]], 400
20598 // CHECK24-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
20599 // CHECK24-NEXT:    br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]]
20600 // CHECK24:       for.end15:
20601 // CHECK24-NEXT:    store i16 6, i16* [[IT16]], align 2
20602 // CHECK24-NEXT:    br label [[FOR_COND17:%.*]]
20603 // CHECK24:       for.cond17:
20604 // CHECK24-NEXT:    [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2
20605 // CHECK24-NEXT:    [[CONV18:%.*]] = sext i16 [[TMP12]] to i32
20606 // CHECK24-NEXT:    [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20
20607 // CHECK24-NEXT:    br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]]
20608 // CHECK24:       for.body20:
20609 // CHECK24-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4
20610 // CHECK24-NEXT:    [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1
20611 // CHECK24-NEXT:    store i32 [[ADD21]], i32* [[A]], align 4
20612 // CHECK24-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2
20613 // CHECK24-NEXT:    [[CONV22:%.*]] = sext i16 [[TMP14]] to i32
20614 // CHECK24-NEXT:    [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1
20615 // CHECK24-NEXT:    [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16
20616 // CHECK24-NEXT:    store i16 [[CONV24]], i16* [[AA]], align 2
20617 // CHECK24-NEXT:    br label [[FOR_INC25:%.*]]
20618 // CHECK24:       for.inc25:
20619 // CHECK24-NEXT:    [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2
20620 // CHECK24-NEXT:    [[CONV26:%.*]] = sext i16 [[TMP15]] to i32
20621 // CHECK24-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4
20622 // CHECK24-NEXT:    [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16
20623 // CHECK24-NEXT:    store i16 [[CONV28]], i16* [[IT16]], align 2
20624 // CHECK24-NEXT:    br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]]
20625 // CHECK24:       for.end29:
20626 // CHECK24-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4
20627 // CHECK24-NEXT:    store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4
20628 // CHECK24-NEXT:    store i8 122, i8* [[IT30]], align 1
20629 // CHECK24-NEXT:    br label [[FOR_COND31:%.*]]
20630 // CHECK24:       for.cond31:
20631 // CHECK24-NEXT:    [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1
20632 // CHECK24-NEXT:    [[CONV32:%.*]] = zext i8 [[TMP17]] to i32
20633 // CHECK24-NEXT:    [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97
20634 // CHECK24-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]]
20635 // CHECK24:       for.body34:
20636 // CHECK24-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
20637 // CHECK24-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1
20638 // CHECK24-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
20639 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
20640 // CHECK24-NEXT:    [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4
20641 // CHECK24-NEXT:    [[CONV36:%.*]] = fpext float [[TMP19]] to double
20642 // CHECK24-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
20643 // CHECK24-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
20644 // CHECK24-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
20645 // CHECK24-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
20646 // CHECK24-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4
20647 // CHECK24-NEXT:    [[CONV40:%.*]] = fpext float [[TMP20]] to double
20648 // CHECK24-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
20649 // CHECK24-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
20650 // CHECK24-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
20651 // CHECK24-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
20652 // CHECK24-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2
20653 // CHECK24-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8
20654 // CHECK24-NEXT:    [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00
20655 // CHECK24-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
20656 // CHECK24-NEXT:    [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]]
20657 // CHECK24-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]]
20658 // CHECK24-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3
20659 // CHECK24-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8
20660 // CHECK24-NEXT:    [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00
20661 // CHECK24-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
20662 // CHECK24-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
20663 // CHECK24-NEXT:    [[TMP24:%.*]] = load i64, i64* [[X]], align 4
20664 // CHECK24-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1
20665 // CHECK24-NEXT:    store i64 [[ADD49]], i64* [[X]], align 4
20666 // CHECK24-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
20667 // CHECK24-NEXT:    [[TMP25:%.*]] = load i8, i8* [[Y]], align 4
20668 // CHECK24-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP25]] to i32
20669 // CHECK24-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
20670 // CHECK24-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
20671 // CHECK24-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 4
20672 // CHECK24-NEXT:    br label [[FOR_INC53:%.*]]
20673 // CHECK24:       for.inc53:
20674 // CHECK24-NEXT:    [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1
20675 // CHECK24-NEXT:    [[CONV54:%.*]] = zext i8 [[TMP26]] to i32
20676 // CHECK24-NEXT:    [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1
20677 // CHECK24-NEXT:    [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8
20678 // CHECK24-NEXT:    store i8 [[CONV56]], i8* [[IT30]], align 1
20679 // CHECK24-NEXT:    br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]]
20680 // CHECK24:       for.end57:
20681 // CHECK24-NEXT:    [[TMP27:%.*]] = load i32, i32* [[A]], align 4
20682 // CHECK24-NEXT:    [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
20683 // CHECK24-NEXT:    call void @llvm.stackrestore(i8* [[TMP28]])
20684 // CHECK24-NEXT:    ret i32 [[TMP27]]
20685 //
20686 //
20687 // CHECK24-LABEL: define {{[^@]+}}@_Z3bari
20688 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
20689 // CHECK24-NEXT:  entry:
20690 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20691 // CHECK24-NEXT:    [[A:%.*]] = alloca i32, align 4
20692 // CHECK24-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
20693 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20694 // CHECK24-NEXT:    store i32 0, i32* [[A]], align 4
20695 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
20696 // CHECK24-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
20697 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
20698 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
20699 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
20700 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
20701 // CHECK24-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
20702 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
20703 // CHECK24-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
20704 // CHECK24-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
20705 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
20706 // CHECK24-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
20707 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
20708 // CHECK24-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
20709 // CHECK24-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
20710 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
20711 // CHECK24-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
20712 // CHECK24-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
20713 // CHECK24-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
20714 // CHECK24-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
20715 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
20716 // CHECK24-NEXT:    ret i32 [[TMP8]]
20717 //
20718 //
20719 // CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
20720 // CHECK24-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
20721 // CHECK24-NEXT:  entry:
20722 // CHECK24-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
20723 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20724 // CHECK24-NEXT:    [[B:%.*]] = alloca i32, align 4
20725 // CHECK24-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
20726 // CHECK24-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
20727 // CHECK24-NEXT:    [[IT:%.*]] = alloca i64, align 8
20728 // CHECK24-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
20729 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20730 // CHECK24-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
20731 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
20732 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
20733 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
20734 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
20735 // CHECK24-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
20736 // CHECK24-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
20737 // CHECK24-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
20738 // CHECK24-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
20739 // CHECK24-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
20740 // CHECK24-NEXT:    store i64 2000, i64* [[IT]], align 8
20741 // CHECK24-NEXT:    br label [[FOR_COND:%.*]]
20742 // CHECK24:       for.cond:
20743 // CHECK24-NEXT:    [[TMP4:%.*]] = load i64, i64* [[IT]], align 8
20744 // CHECK24-NEXT:    [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600
20745 // CHECK24-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20746 // CHECK24:       for.body:
20747 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
20748 // CHECK24-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
20749 // CHECK24-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
20750 // CHECK24-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
20751 // CHECK24-NEXT:    store double [[ADD2]], double* [[A]], align 4
20752 // CHECK24-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
20753 // CHECK24-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 4
20754 // CHECK24-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
20755 // CHECK24-NEXT:    store double [[INC]], double* [[A3]], align 4
20756 // CHECK24-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
20757 // CHECK24-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
20758 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
20759 // CHECK24-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
20760 // CHECK24-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
20761 // CHECK24-NEXT:    br label [[FOR_INC:%.*]]
20762 // CHECK24:       for.inc:
20763 // CHECK24-NEXT:    [[TMP8:%.*]] = load i64, i64* [[IT]], align 8
20764 // CHECK24-NEXT:    [[SUB:%.*]] = sub i64 [[TMP8]], 400
20765 // CHECK24-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
20766 // CHECK24-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
20767 // CHECK24:       for.end:
20768 // CHECK24-NEXT:    [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]]
20769 // CHECK24-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]]
20770 // CHECK24-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
20771 // CHECK24-NEXT:    [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
20772 // CHECK24-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP10]] to i32
20773 // CHECK24-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4
20774 // CHECK24-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]]
20775 // CHECK24-NEXT:    [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
20776 // CHECK24-NEXT:    call void @llvm.stackrestore(i8* [[TMP12]])
20777 // CHECK24-NEXT:    ret i32 [[ADD9]]
20778 //
20779 //
20780 // CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici
20781 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
20782 // CHECK24-NEXT:  entry:
20783 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20784 // CHECK24-NEXT:    [[A:%.*]] = alloca i32, align 4
20785 // CHECK24-NEXT:    [[AA:%.*]] = alloca i16, align 2
20786 // CHECK24-NEXT:    [[AAA:%.*]] = alloca i8, align 1
20787 // CHECK24-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
20788 // CHECK24-NEXT:    [[I:%.*]] = alloca i32, align 4
20789 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20790 // CHECK24-NEXT:    store i32 0, i32* [[A]], align 4
20791 // CHECK24-NEXT:    store i16 0, i16* [[AA]], align 2
20792 // CHECK24-NEXT:    store i8 0, i8* [[AAA]], align 1
20793 // CHECK24-NEXT:    store i32 100, i32* [[I]], align 4
20794 // CHECK24-NEXT:    br label [[FOR_COND:%.*]]
20795 // CHECK24:       for.cond:
20796 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
20797 // CHECK24-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10
20798 // CHECK24-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20799 // CHECK24:       for.body:
20800 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
20801 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
20802 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
20803 // CHECK24-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
20804 // CHECK24-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
20805 // CHECK24-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
20806 // CHECK24-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
20807 // CHECK24-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
20808 // CHECK24-NEXT:    [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1
20809 // CHECK24-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
20810 // CHECK24-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
20811 // CHECK24-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
20812 // CHECK24-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
20813 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
20814 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
20815 // CHECK24-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
20816 // CHECK24-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
20817 // CHECK24-NEXT:    br label [[FOR_INC:%.*]]
20818 // CHECK24:       for.inc:
20819 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
20820 // CHECK24-NEXT:    [[ADD7:%.*]] = add i32 [[TMP5]], 10
20821 // CHECK24-NEXT:    store i32 [[ADD7]], i32* [[I]], align 4
20822 // CHECK24-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
20823 // CHECK24:       for.end:
20824 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
20825 // CHECK24-NEXT:    ret i32 [[TMP6]]
20826 //
20827 //
20828 // CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
20829 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
20830 // CHECK24-NEXT:  entry:
20831 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20832 // CHECK24-NEXT:    [[A:%.*]] = alloca i32, align 4
20833 // CHECK24-NEXT:    [[AA:%.*]] = alloca i16, align 2
20834 // CHECK24-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
20835 // CHECK24-NEXT:    [[I:%.*]] = alloca i64, align 8
20836 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20837 // CHECK24-NEXT:    store i32 0, i32* [[A]], align 4
20838 // CHECK24-NEXT:    store i16 0, i16* [[AA]], align 2
20839 // CHECK24-NEXT:    store i64 -10, i64* [[I]], align 8
20840 // CHECK24-NEXT:    br label [[FOR_COND:%.*]]
20841 // CHECK24:       for.cond:
20842 // CHECK24-NEXT:    [[TMP0:%.*]] = load i64, i64* [[I]], align 8
20843 // CHECK24-NEXT:    [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10
20844 // CHECK24-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20845 // CHECK24:       for.body:
20846 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
20847 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
20848 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
20849 // CHECK24-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
20850 // CHECK24-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
20851 // CHECK24-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
20852 // CHECK24-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
20853 // CHECK24-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
20854 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
20855 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
20856 // CHECK24-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
20857 // CHECK24-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
20858 // CHECK24-NEXT:    br label [[FOR_INC:%.*]]
20859 // CHECK24:       for.inc:
20860 // CHECK24-NEXT:    [[TMP4:%.*]] = load i64, i64* [[I]], align 8
20861 // CHECK24-NEXT:    [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3
20862 // CHECK24-NEXT:    store i64 [[ADD4]], i64* [[I]], align 8
20863 // CHECK24-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
20864 // CHECK24:       for.end:
20865 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
20866 // CHECK24-NEXT:    ret i32 [[TMP5]]
20867 //
20868 //
20869 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
20870 // CHECK25-SAME: () #[[ATTR0:[0-9]+]] {
20871 // CHECK25-NEXT:  entry:
20872 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
20873 // CHECK25-NEXT:    ret void
20874 //
20875 //
20876 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined.
20877 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
20878 // CHECK25-NEXT:  entry:
20879 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
20880 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
20881 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
20882 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i32, align 4
20883 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
20884 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
20885 // CHECK25-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
20886 // CHECK25-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
20887 // CHECK25-NEXT:    [[I:%.*]] = alloca i32, align 4
20888 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
20889 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
20890 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
20891 // CHECK25-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
20892 // CHECK25-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
20893 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
20894 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
20895 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
20896 // CHECK25-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
20897 // CHECK25-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20898 // CHECK25-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
20899 // CHECK25-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
20900 // CHECK25:       cond.true:
20901 // CHECK25-NEXT:    br label [[COND_END:%.*]]
20902 // CHECK25:       cond.false:
20903 // CHECK25-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20904 // CHECK25-NEXT:    br label [[COND_END]]
20905 // CHECK25:       cond.end:
20906 // CHECK25-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
20907 // CHECK25-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
20908 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
20909 // CHECK25-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
20910 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
20911 // CHECK25:       omp.inner.for.cond:
20912 // CHECK25-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
20913 // CHECK25-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20914 // CHECK25-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
20915 // CHECK25-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
20916 // CHECK25:       omp.inner.for.body:
20917 // CHECK25-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
20918 // CHECK25-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
20919 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
20920 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
20921 // CHECK25-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
20922 // CHECK25-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
20923 // CHECK25-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
20924 // CHECK25:       .cancel.exit:
20925 // CHECK25-NEXT:    br label [[CANCEL_EXIT:%.*]]
20926 // CHECK25:       .cancel.continue:
20927 // CHECK25-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
20928 // CHECK25-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
20929 // CHECK25-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
20930 // CHECK25:       .cancel.exit2:
20931 // CHECK25-NEXT:    br label [[CANCEL_EXIT]]
20932 // CHECK25:       .cancel.continue3:
20933 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
20934 // CHECK25:       omp.body.continue:
20935 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
20936 // CHECK25:       omp.inner.for.inc:
20937 // CHECK25-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
20938 // CHECK25-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
20939 // CHECK25-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
20940 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]]
20941 // CHECK25:       omp.inner.for.end:
20942 // CHECK25-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
20943 // CHECK25:       omp.loop.exit:
20944 // CHECK25-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
20945 // CHECK25-NEXT:    br label [[CANCEL_CONT:%.*]]
20946 // CHECK25:       cancel.cont:
20947 // CHECK25-NEXT:    ret void
20948 // CHECK25:       cancel.exit:
20949 // CHECK25-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
20950 // CHECK25-NEXT:    br label [[CANCEL_CONT]]
20951 //
20952 //
20953 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
20954 // CHECK25-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
20955 // CHECK25-NEXT:  entry:
20956 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
20957 // CHECK25-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
20958 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
20959 // CHECK25-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
20960 // CHECK25-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
20961 // CHECK25-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
20962 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
20963 // CHECK25-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
20964 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
20965 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
20966 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
20967 // CHECK25-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
20968 // CHECK25-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
20969 // CHECK25-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
20970 // CHECK25-NEXT:    store i16 [[TMP0]], i16* [[CONV3]], align 2
20971 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
20972 // CHECK25-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
20973 // CHECK25-NEXT:    [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
20974 // CHECK25-NEXT:    store i32 [[TMP2]], i32* [[CONV4]], align 4
20975 // CHECK25-NEXT:    [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
20976 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
20977 // CHECK25-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
20978 // CHECK25-NEXT:    store i32 [[TMP4]], i32* [[CONV5]], align 4
20979 // CHECK25-NEXT:    [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
20980 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
20981 // CHECK25-NEXT:    ret void
20982 //
20983 //
20984 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1
20985 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
20986 // CHECK25-NEXT:  entry:
20987 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
20988 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
20989 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
20990 // CHECK25-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
20991 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
20992 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
20993 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i64, align 8
20994 // CHECK25-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
20995 // CHECK25-NEXT:    [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
20996 // CHECK25-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
20997 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
20998 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
20999 // CHECK25-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
21000 // CHECK25-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21001 // CHECK25-NEXT:    [[IT:%.*]] = alloca i64, align 8
21002 // CHECK25-NEXT:    [[LIN4:%.*]] = alloca i32, align 4
21003 // CHECK25-NEXT:    [[A5:%.*]] = alloca i32, align 4
21004 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21005 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21006 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21007 // CHECK25-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
21008 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21009 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21010 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
21011 // CHECK25-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21012 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
21013 // CHECK25-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
21014 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
21015 // CHECK25-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
21016 // CHECK25-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]]
21017 // CHECK25-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
21018 // CHECK25-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
21019 // CHECK25-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
21020 // CHECK25-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
21021 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21022 // CHECK25-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21023 // CHECK25-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
21024 // CHECK25-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
21025 // CHECK25-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
21026 // CHECK25-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21027 // CHECK25-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
21028 // CHECK25-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21029 // CHECK25:       cond.true:
21030 // CHECK25-NEXT:    br label [[COND_END:%.*]]
21031 // CHECK25:       cond.false:
21032 // CHECK25-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21033 // CHECK25-NEXT:    br label [[COND_END]]
21034 // CHECK25:       cond.end:
21035 // CHECK25-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
21036 // CHECK25-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
21037 // CHECK25-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
21038 // CHECK25-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
21039 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21040 // CHECK25:       omp.inner.for.cond:
21041 // CHECK25-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21042 // CHECK25-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21043 // CHECK25-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
21044 // CHECK25-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21045 // CHECK25:       omp.inner.for.body:
21046 // CHECK25-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21047 // CHECK25-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
21048 // CHECK25-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
21049 // CHECK25-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
21050 // CHECK25-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
21051 // CHECK25-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
21052 // CHECK25-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21053 // CHECK25-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
21054 // CHECK25-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
21055 // CHECK25-NEXT:    [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
21056 // CHECK25-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
21057 // CHECK25-NEXT:    store i32 [[CONV9]], i32* [[LIN4]], align 4
21058 // CHECK25-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
21059 // CHECK25-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
21060 // CHECK25-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21061 // CHECK25-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
21062 // CHECK25-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
21063 // CHECK25-NEXT:    [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
21064 // CHECK25-NEXT:    [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
21065 // CHECK25-NEXT:    store i32 [[CONV13]], i32* [[A5]], align 4
21066 // CHECK25-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8
21067 // CHECK25-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
21068 // CHECK25-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
21069 // CHECK25-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
21070 // CHECK25-NEXT:    store i16 [[CONV16]], i16* [[CONV]], align 8
21071 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21072 // CHECK25:       omp.body.continue:
21073 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21074 // CHECK25:       omp.inner.for.inc:
21075 // CHECK25-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21076 // CHECK25-NEXT:    [[ADD17:%.*]] = add i64 [[TMP17]], 1
21077 // CHECK25-NEXT:    store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
21078 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]]
21079 // CHECK25:       omp.inner.for.end:
21080 // CHECK25-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21081 // CHECK25:       omp.loop.exit:
21082 // CHECK25-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
21083 // CHECK25-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
21084 // CHECK25-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
21085 // CHECK25-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
21086 // CHECK25:       .omp.linear.pu:
21087 // CHECK25-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
21088 // CHECK25-NEXT:    [[CONV18:%.*]] = sext i32 [[TMP20]] to i64
21089 // CHECK25-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
21090 // CHECK25-NEXT:    [[MUL19:%.*]] = mul i64 4, [[TMP21]]
21091 // CHECK25-NEXT:    [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
21092 // CHECK25-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
21093 // CHECK25-NEXT:    store i32 [[CONV21]], i32* [[CONV1]], align 8
21094 // CHECK25-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
21095 // CHECK25-NEXT:    [[CONV22:%.*]] = sext i32 [[TMP22]] to i64
21096 // CHECK25-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
21097 // CHECK25-NEXT:    [[MUL23:%.*]] = mul i64 4, [[TMP23]]
21098 // CHECK25-NEXT:    [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
21099 // CHECK25-NEXT:    [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
21100 // CHECK25-NEXT:    store i32 [[CONV25]], i32* [[CONV2]], align 8
21101 // CHECK25-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
21102 // CHECK25:       .omp.linear.pu.done:
21103 // CHECK25-NEXT:    ret void
21104 //
21105 //
21106 // CHECK25-LABEL: define {{[^@]+}}@_Z7get_valv
21107 // CHECK25-SAME: () #[[ATTR2:[0-9]+]] {
21108 // CHECK25-NEXT:  entry:
21109 // CHECK25-NEXT:    ret i64 0
21110 //
21111 //
21112 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
21113 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
21114 // CHECK25-NEXT:  entry:
21115 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21116 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21117 // CHECK25-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
21118 // CHECK25-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
21119 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21120 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21121 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21122 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21123 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
21124 // CHECK25-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
21125 // CHECK25-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
21126 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
21127 // CHECK25-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
21128 // CHECK25-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
21129 // CHECK25-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
21130 // CHECK25-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
21131 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
21132 // CHECK25-NEXT:    ret void
21133 //
21134 //
21135 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2
21136 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
21137 // CHECK25-NEXT:  entry:
21138 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21139 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21140 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21141 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21142 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21143 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i16, align 2
21144 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21145 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21146 // CHECK25-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21147 // CHECK25-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21148 // CHECK25-NEXT:    [[IT:%.*]] = alloca i16, align 2
21149 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21150 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21151 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21152 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21153 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21154 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21155 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21156 // CHECK25-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
21157 // CHECK25-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21158 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21159 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21160 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
21161 // CHECK25-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
21162 // CHECK25-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21163 // CHECK25-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
21164 // CHECK25-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21165 // CHECK25:       cond.true:
21166 // CHECK25-NEXT:    br label [[COND_END:%.*]]
21167 // CHECK25:       cond.false:
21168 // CHECK25-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21169 // CHECK25-NEXT:    br label [[COND_END]]
21170 // CHECK25:       cond.end:
21171 // CHECK25-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
21172 // CHECK25-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21173 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21174 // CHECK25-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
21175 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21176 // CHECK25:       omp.inner.for.cond:
21177 // CHECK25-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21178 // CHECK25-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21179 // CHECK25-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
21180 // CHECK25-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21181 // CHECK25:       omp.inner.for.body:
21182 // CHECK25-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21183 // CHECK25-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
21184 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
21185 // CHECK25-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
21186 // CHECK25-NEXT:    store i16 [[CONV3]], i16* [[IT]], align 2
21187 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
21188 // CHECK25-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
21189 // CHECK25-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8
21190 // CHECK25-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
21191 // CHECK25-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
21192 // CHECK25-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
21193 // CHECK25-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
21194 // CHECK25-NEXT:    store i16 [[CONV7]], i16* [[CONV1]], align 8
21195 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21196 // CHECK25:       omp.body.continue:
21197 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21198 // CHECK25:       omp.inner.for.inc:
21199 // CHECK25-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21200 // CHECK25-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
21201 // CHECK25-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
21202 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]]
21203 // CHECK25:       omp.inner.for.end:
21204 // CHECK25-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21205 // CHECK25:       omp.loop.exit:
21206 // CHECK25-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
21207 // CHECK25-NEXT:    ret void
21208 //
21209 //
21210 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
21211 // CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
21212 // CHECK25-NEXT:  entry:
21213 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21214 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
21215 // CHECK25-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
21216 // CHECK25-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
21217 // CHECK25-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
21218 // CHECK25-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
21219 // CHECK25-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
21220 // CHECK25-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
21221 // CHECK25-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
21222 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
21223 // CHECK25-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
21224 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
21225 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21226 // CHECK25-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
21227 // CHECK25-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
21228 // CHECK25-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
21229 // CHECK25-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
21230 // CHECK25-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
21231 // CHECK25-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
21232 // CHECK25-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
21233 // CHECK25-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
21234 // CHECK25-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
21235 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21236 // CHECK25-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
21237 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
21238 // CHECK25-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
21239 // CHECK25-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
21240 // CHECK25-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
21241 // CHECK25-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
21242 // CHECK25-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
21243 // CHECK25-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
21244 // CHECK25-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
21245 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
21246 // CHECK25-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
21247 // CHECK25-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
21248 // CHECK25-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
21249 // CHECK25-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
21250 // CHECK25-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
21251 // CHECK25-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
21252 // CHECK25-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
21253 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
21254 // CHECK25-NEXT:    ret void
21255 //
21256 //
21257 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3
21258 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
21259 // CHECK25-NEXT:  entry:
21260 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21261 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21262 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21263 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
21264 // CHECK25-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
21265 // CHECK25-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
21266 // CHECK25-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
21267 // CHECK25-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
21268 // CHECK25-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
21269 // CHECK25-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
21270 // CHECK25-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
21271 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
21272 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21273 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i8, align 1
21274 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21275 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21276 // CHECK25-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21277 // CHECK25-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21278 // CHECK25-NEXT:    [[IT:%.*]] = alloca i8, align 1
21279 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21280 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21281 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21282 // CHECK25-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
21283 // CHECK25-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
21284 // CHECK25-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
21285 // CHECK25-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
21286 // CHECK25-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
21287 // CHECK25-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
21288 // CHECK25-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
21289 // CHECK25-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
21290 // CHECK25-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
21291 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21292 // CHECK25-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
21293 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
21294 // CHECK25-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
21295 // CHECK25-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
21296 // CHECK25-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
21297 // CHECK25-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
21298 // CHECK25-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
21299 // CHECK25-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
21300 // CHECK25-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
21301 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21302 // CHECK25-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
21303 // CHECK25-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21304 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21305 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
21306 // CHECK25-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21307 // CHECK25-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
21308 // CHECK25-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
21309 // CHECK25-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
21310 // CHECK25:       omp.dispatch.cond:
21311 // CHECK25-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21312 // CHECK25-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
21313 // CHECK25-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21314 // CHECK25:       cond.true:
21315 // CHECK25-NEXT:    br label [[COND_END:%.*]]
21316 // CHECK25:       cond.false:
21317 // CHECK25-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21318 // CHECK25-NEXT:    br label [[COND_END]]
21319 // CHECK25:       cond.end:
21320 // CHECK25-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
21321 // CHECK25-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21322 // CHECK25-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21323 // CHECK25-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
21324 // CHECK25-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21325 // CHECK25-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21326 // CHECK25-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
21327 // CHECK25-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
21328 // CHECK25:       omp.dispatch.body:
21329 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21330 // CHECK25:       omp.inner.for.cond:
21331 // CHECK25-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21332 // CHECK25-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21333 // CHECK25-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
21334 // CHECK25-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21335 // CHECK25:       omp.inner.for.body:
21336 // CHECK25-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21337 // CHECK25-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
21338 // CHECK25-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
21339 // CHECK25-NEXT:    [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
21340 // CHECK25-NEXT:    store i8 [[CONV8]], i8* [[IT]], align 1
21341 // CHECK25-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
21342 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
21343 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
21344 // CHECK25-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
21345 // CHECK25-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
21346 // CHECK25-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
21347 // CHECK25-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
21348 // CHECK25-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
21349 // CHECK25-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
21350 // CHECK25-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
21351 // CHECK25-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
21352 // CHECK25-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
21353 // CHECK25-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
21354 // CHECK25-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
21355 // CHECK25-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
21356 // CHECK25-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
21357 // CHECK25-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
21358 // CHECK25-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
21359 // CHECK25-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
21360 // CHECK25-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
21361 // CHECK25-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
21362 // CHECK25-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
21363 // CHECK25-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
21364 // CHECK25-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
21365 // CHECK25-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
21366 // CHECK25-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
21367 // CHECK25-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
21368 // CHECK25-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8
21369 // CHECK25-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
21370 // CHECK25-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8
21371 // CHECK25-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
21372 // CHECK25-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
21373 // CHECK25-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
21374 // CHECK25-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
21375 // CHECK25-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
21376 // CHECK25-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8
21377 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21378 // CHECK25:       omp.body.continue:
21379 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21380 // CHECK25:       omp.inner.for.inc:
21381 // CHECK25-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21382 // CHECK25-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
21383 // CHECK25-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
21384 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]]
21385 // CHECK25:       omp.inner.for.end:
21386 // CHECK25-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
21387 // CHECK25:       omp.dispatch.inc:
21388 // CHECK25-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21389 // CHECK25-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
21390 // CHECK25-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
21391 // CHECK25-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
21392 // CHECK25-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21393 // CHECK25-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
21394 // CHECK25-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
21395 // CHECK25-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
21396 // CHECK25-NEXT:    br label [[OMP_DISPATCH_COND]]
21397 // CHECK25:       omp.dispatch.end:
21398 // CHECK25-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
21399 // CHECK25-NEXT:    ret void
21400 //
21401 //
21402 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
21403 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
21404 // CHECK25-NEXT:  entry:
21405 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21406 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21407 // CHECK25-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
21408 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
21409 // CHECK25-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
21410 // CHECK25-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
21411 // CHECK25-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
21412 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21413 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21414 // CHECK25-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
21415 // CHECK25-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
21416 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21417 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21418 // CHECK25-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
21419 // CHECK25-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
21420 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
21421 // CHECK25-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
21422 // CHECK25-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
21423 // CHECK25-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
21424 // CHECK25-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
21425 // CHECK25-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
21426 // CHECK25-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
21427 // CHECK25-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
21428 // CHECK25-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
21429 // CHECK25-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
21430 // CHECK25-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
21431 // CHECK25-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
21432 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
21433 // CHECK25-NEXT:    ret void
21434 //
21435 //
21436 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4
21437 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
21438 // CHECK25-NEXT:  entry:
21439 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21440 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21441 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21442 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21443 // CHECK25-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
21444 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
21445 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21446 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i32, align 4
21447 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21448 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21449 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21450 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21451 // CHECK25-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
21452 // CHECK25-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
21453 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21454 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21455 // CHECK25-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
21456 // CHECK25-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
21457 // CHECK25-NEXT:    ret void
21458 //
21459 //
21460 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
21461 // CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
21462 // CHECK25-NEXT:  entry:
21463 // CHECK25-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
21464 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
21465 // CHECK25-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
21466 // CHECK25-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
21467 // CHECK25-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
21468 // CHECK25-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
21469 // CHECK25-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
21470 // CHECK25-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
21471 // CHECK25-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
21472 // CHECK25-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
21473 // CHECK25-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
21474 // CHECK25-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
21475 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
21476 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
21477 // CHECK25-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
21478 // CHECK25-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
21479 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
21480 // CHECK25-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
21481 // CHECK25-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
21482 // CHECK25-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
21483 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
21484 // CHECK25-NEXT:    ret void
21485 //
21486 //
21487 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5
21488 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
21489 // CHECK25-NEXT:  entry:
21490 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21491 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21492 // CHECK25-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
21493 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
21494 // CHECK25-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
21495 // CHECK25-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
21496 // CHECK25-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
21497 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
21498 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i64, align 8
21499 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
21500 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
21501 // CHECK25-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
21502 // CHECK25-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21503 // CHECK25-NEXT:    [[IT:%.*]] = alloca i64, align 8
21504 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21505 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21506 // CHECK25-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
21507 // CHECK25-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
21508 // CHECK25-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
21509 // CHECK25-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
21510 // CHECK25-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
21511 // CHECK25-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
21512 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
21513 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
21514 // CHECK25-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
21515 // CHECK25-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
21516 // CHECK25-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
21517 // CHECK25-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
21518 // CHECK25-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
21519 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21520 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21521 // CHECK25-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
21522 // CHECK25-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
21523 // CHECK25-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21524 // CHECK25-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
21525 // CHECK25-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21526 // CHECK25:       cond.true:
21527 // CHECK25-NEXT:    br label [[COND_END:%.*]]
21528 // CHECK25:       cond.false:
21529 // CHECK25-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21530 // CHECK25-NEXT:    br label [[COND_END]]
21531 // CHECK25:       cond.end:
21532 // CHECK25-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
21533 // CHECK25-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
21534 // CHECK25-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
21535 // CHECK25-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
21536 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21537 // CHECK25:       omp.inner.for.cond:
21538 // CHECK25-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21539 // CHECK25-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21540 // CHECK25-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
21541 // CHECK25-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21542 // CHECK25:       omp.inner.for.body:
21543 // CHECK25-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21544 // CHECK25-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
21545 // CHECK25-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
21546 // CHECK25-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
21547 // CHECK25-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
21548 // CHECK25-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
21549 // CHECK25-NEXT:    [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
21550 // CHECK25-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
21551 // CHECK25-NEXT:    store double [[ADD]], double* [[A]], align 8
21552 // CHECK25-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
21553 // CHECK25-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 8
21554 // CHECK25-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
21555 // CHECK25-NEXT:    store double [[INC]], double* [[A5]], align 8
21556 // CHECK25-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
21557 // CHECK25-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
21558 // CHECK25-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
21559 // CHECK25-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
21560 // CHECK25-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
21561 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21562 // CHECK25:       omp.body.continue:
21563 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21564 // CHECK25:       omp.inner.for.inc:
21565 // CHECK25-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21566 // CHECK25-NEXT:    [[ADD8:%.*]] = add i64 [[TMP15]], 1
21567 // CHECK25-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
21568 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]]
21569 // CHECK25:       omp.inner.for.end:
21570 // CHECK25-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21571 // CHECK25:       omp.loop.exit:
21572 // CHECK25-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
21573 // CHECK25-NEXT:    ret void
21574 //
21575 //
21576 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
21577 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
21578 // CHECK25-NEXT:  entry:
21579 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21580 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21581 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
21582 // CHECK25-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
21583 // CHECK25-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
21584 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21585 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21586 // CHECK25-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
21587 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21588 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21589 // CHECK25-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
21590 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
21591 // CHECK25-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
21592 // CHECK25-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
21593 // CHECK25-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
21594 // CHECK25-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
21595 // CHECK25-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
21596 // CHECK25-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
21597 // CHECK25-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
21598 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
21599 // CHECK25-NEXT:    ret void
21600 //
21601 //
21602 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6
21603 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
21604 // CHECK25-NEXT:  entry:
21605 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21606 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21607 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21608 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21609 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
21610 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
21611 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i64, align 8
21612 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
21613 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
21614 // CHECK25-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
21615 // CHECK25-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21616 // CHECK25-NEXT:    [[I:%.*]] = alloca i64, align 8
21617 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21618 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21619 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21620 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21621 // CHECK25-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
21622 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21623 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21624 // CHECK25-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
21625 // CHECK25-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
21626 // CHECK25-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
21627 // CHECK25-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
21628 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21629 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21630 // CHECK25-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
21631 // CHECK25-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
21632 // CHECK25-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21633 // CHECK25-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
21634 // CHECK25-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21635 // CHECK25:       cond.true:
21636 // CHECK25-NEXT:    br label [[COND_END:%.*]]
21637 // CHECK25:       cond.false:
21638 // CHECK25-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21639 // CHECK25-NEXT:    br label [[COND_END]]
21640 // CHECK25:       cond.end:
21641 // CHECK25-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
21642 // CHECK25-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
21643 // CHECK25-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
21644 // CHECK25-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
21645 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21646 // CHECK25:       omp.inner.for.cond:
21647 // CHECK25-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21648 // CHECK25-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21649 // CHECK25-NEXT:    [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
21650 // CHECK25-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21651 // CHECK25:       omp.inner.for.body:
21652 // CHECK25-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21653 // CHECK25-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
21654 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
21655 // CHECK25-NEXT:    store i64 [[ADD]], i64* [[I]], align 8
21656 // CHECK25-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
21657 // CHECK25-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
21658 // CHECK25-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
21659 // CHECK25-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
21660 // CHECK25-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
21661 // CHECK25-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
21662 // CHECK25-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
21663 // CHECK25-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
21664 // CHECK25-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
21665 // CHECK25-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
21666 // CHECK25-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
21667 // CHECK25-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
21668 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21669 // CHECK25:       omp.body.continue:
21670 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21671 // CHECK25:       omp.inner.for.inc:
21672 // CHECK25-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21673 // CHECK25-NEXT:    [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
21674 // CHECK25-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
21675 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]]
21676 // CHECK25:       omp.inner.for.end:
21677 // CHECK25-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21678 // CHECK25:       omp.loop.exit:
21679 // CHECK25-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
21680 // CHECK25-NEXT:    ret void
21681 //
21682 //
21683 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
21684 // CHECK26-SAME: () #[[ATTR0:[0-9]+]] {
21685 // CHECK26-NEXT:  entry:
21686 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
21687 // CHECK26-NEXT:    ret void
21688 //
21689 //
21690 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined.
21691 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
21692 // CHECK26-NEXT:  entry:
21693 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21694 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21695 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21696 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i32, align 4
21697 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21698 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21699 // CHECK26-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21700 // CHECK26-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21701 // CHECK26-NEXT:    [[I:%.*]] = alloca i32, align 4
21702 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21703 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21704 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21705 // CHECK26-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
21706 // CHECK26-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21707 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21708 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21709 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
21710 // CHECK26-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
21711 // CHECK26-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21712 // CHECK26-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
21713 // CHECK26-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21714 // CHECK26:       cond.true:
21715 // CHECK26-NEXT:    br label [[COND_END:%.*]]
21716 // CHECK26:       cond.false:
21717 // CHECK26-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21718 // CHECK26-NEXT:    br label [[COND_END]]
21719 // CHECK26:       cond.end:
21720 // CHECK26-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
21721 // CHECK26-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21722 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21723 // CHECK26-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
21724 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21725 // CHECK26:       omp.inner.for.cond:
21726 // CHECK26-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21727 // CHECK26-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21728 // CHECK26-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
21729 // CHECK26-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21730 // CHECK26:       omp.inner.for.body:
21731 // CHECK26-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21732 // CHECK26-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
21733 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
21734 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
21735 // CHECK26-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
21736 // CHECK26-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
21737 // CHECK26-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
21738 // CHECK26:       .cancel.exit:
21739 // CHECK26-NEXT:    br label [[CANCEL_EXIT:%.*]]
21740 // CHECK26:       .cancel.continue:
21741 // CHECK26-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
21742 // CHECK26-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
21743 // CHECK26-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
21744 // CHECK26:       .cancel.exit2:
21745 // CHECK26-NEXT:    br label [[CANCEL_EXIT]]
21746 // CHECK26:       .cancel.continue3:
21747 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21748 // CHECK26:       omp.body.continue:
21749 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21750 // CHECK26:       omp.inner.for.inc:
21751 // CHECK26-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21752 // CHECK26-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
21753 // CHECK26-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
21754 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]]
21755 // CHECK26:       omp.inner.for.end:
21756 // CHECK26-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21757 // CHECK26:       omp.loop.exit:
21758 // CHECK26-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
21759 // CHECK26-NEXT:    br label [[CANCEL_CONT:%.*]]
21760 // CHECK26:       cancel.cont:
21761 // CHECK26-NEXT:    ret void
21762 // CHECK26:       cancel.exit:
21763 // CHECK26-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
21764 // CHECK26-NEXT:    br label [[CANCEL_CONT]]
21765 //
21766 //
21767 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
21768 // CHECK26-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
21769 // CHECK26-NEXT:  entry:
21770 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21771 // CHECK26-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
21772 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21773 // CHECK26-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
21774 // CHECK26-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
21775 // CHECK26-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
21776 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21777 // CHECK26-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
21778 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21779 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21780 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
21781 // CHECK26-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21782 // CHECK26-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
21783 // CHECK26-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
21784 // CHECK26-NEXT:    store i16 [[TMP0]], i16* [[CONV3]], align 2
21785 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
21786 // CHECK26-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
21787 // CHECK26-NEXT:    [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
21788 // CHECK26-NEXT:    store i32 [[TMP2]], i32* [[CONV4]], align 4
21789 // CHECK26-NEXT:    [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
21790 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
21791 // CHECK26-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
21792 // CHECK26-NEXT:    store i32 [[TMP4]], i32* [[CONV5]], align 4
21793 // CHECK26-NEXT:    [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
21794 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
21795 // CHECK26-NEXT:    ret void
21796 //
21797 //
21798 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1
21799 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
21800 // CHECK26-NEXT:  entry:
21801 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21802 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21803 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21804 // CHECK26-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
21805 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21806 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
21807 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i64, align 8
21808 // CHECK26-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
21809 // CHECK26-NEXT:    [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
21810 // CHECK26-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
21811 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
21812 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
21813 // CHECK26-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
21814 // CHECK26-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21815 // CHECK26-NEXT:    [[IT:%.*]] = alloca i64, align 8
21816 // CHECK26-NEXT:    [[LIN4:%.*]] = alloca i32, align 4
21817 // CHECK26-NEXT:    [[A5:%.*]] = alloca i32, align 4
21818 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21819 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21820 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21821 // CHECK26-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
21822 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21823 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21824 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
21825 // CHECK26-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21826 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
21827 // CHECK26-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
21828 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
21829 // CHECK26-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
21830 // CHECK26-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]]
21831 // CHECK26-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
21832 // CHECK26-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
21833 // CHECK26-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
21834 // CHECK26-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
21835 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21836 // CHECK26-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21837 // CHECK26-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
21838 // CHECK26-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
21839 // CHECK26-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
21840 // CHECK26-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21841 // CHECK26-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
21842 // CHECK26-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21843 // CHECK26:       cond.true:
21844 // CHECK26-NEXT:    br label [[COND_END:%.*]]
21845 // CHECK26:       cond.false:
21846 // CHECK26-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21847 // CHECK26-NEXT:    br label [[COND_END]]
21848 // CHECK26:       cond.end:
21849 // CHECK26-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
21850 // CHECK26-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
21851 // CHECK26-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
21852 // CHECK26-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
21853 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21854 // CHECK26:       omp.inner.for.cond:
21855 // CHECK26-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21856 // CHECK26-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21857 // CHECK26-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
21858 // CHECK26-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21859 // CHECK26:       omp.inner.for.body:
21860 // CHECK26-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21861 // CHECK26-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
21862 // CHECK26-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
21863 // CHECK26-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
21864 // CHECK26-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
21865 // CHECK26-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
21866 // CHECK26-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21867 // CHECK26-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
21868 // CHECK26-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
21869 // CHECK26-NEXT:    [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
21870 // CHECK26-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
21871 // CHECK26-NEXT:    store i32 [[CONV9]], i32* [[LIN4]], align 4
21872 // CHECK26-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
21873 // CHECK26-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
21874 // CHECK26-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21875 // CHECK26-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
21876 // CHECK26-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
21877 // CHECK26-NEXT:    [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
21878 // CHECK26-NEXT:    [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
21879 // CHECK26-NEXT:    store i32 [[CONV13]], i32* [[A5]], align 4
21880 // CHECK26-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8
21881 // CHECK26-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
21882 // CHECK26-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
21883 // CHECK26-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
21884 // CHECK26-NEXT:    store i16 [[CONV16]], i16* [[CONV]], align 8
21885 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21886 // CHECK26:       omp.body.continue:
21887 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21888 // CHECK26:       omp.inner.for.inc:
21889 // CHECK26-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21890 // CHECK26-NEXT:    [[ADD17:%.*]] = add i64 [[TMP17]], 1
21891 // CHECK26-NEXT:    store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
21892 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]]
21893 // CHECK26:       omp.inner.for.end:
21894 // CHECK26-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21895 // CHECK26:       omp.loop.exit:
21896 // CHECK26-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
21897 // CHECK26-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
21898 // CHECK26-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
21899 // CHECK26-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
21900 // CHECK26:       .omp.linear.pu:
21901 // CHECK26-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
21902 // CHECK26-NEXT:    [[CONV18:%.*]] = sext i32 [[TMP20]] to i64
21903 // CHECK26-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
21904 // CHECK26-NEXT:    [[MUL19:%.*]] = mul i64 4, [[TMP21]]
21905 // CHECK26-NEXT:    [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
21906 // CHECK26-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
21907 // CHECK26-NEXT:    store i32 [[CONV21]], i32* [[CONV1]], align 8
21908 // CHECK26-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
21909 // CHECK26-NEXT:    [[CONV22:%.*]] = sext i32 [[TMP22]] to i64
21910 // CHECK26-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
21911 // CHECK26-NEXT:    [[MUL23:%.*]] = mul i64 4, [[TMP23]]
21912 // CHECK26-NEXT:    [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
21913 // CHECK26-NEXT:    [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
21914 // CHECK26-NEXT:    store i32 [[CONV25]], i32* [[CONV2]], align 8
21915 // CHECK26-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
21916 // CHECK26:       .omp.linear.pu.done:
21917 // CHECK26-NEXT:    ret void
21918 //
21919 //
21920 // CHECK26-LABEL: define {{[^@]+}}@_Z7get_valv
21921 // CHECK26-SAME: () #[[ATTR2:[0-9]+]] {
21922 // CHECK26-NEXT:  entry:
21923 // CHECK26-NEXT:    ret i64 0
21924 //
21925 //
21926 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
21927 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
21928 // CHECK26-NEXT:  entry:
21929 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21930 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21931 // CHECK26-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
21932 // CHECK26-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
21933 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21934 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21935 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21936 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21937 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
21938 // CHECK26-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
21939 // CHECK26-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
21940 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
21941 // CHECK26-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
21942 // CHECK26-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
21943 // CHECK26-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
21944 // CHECK26-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
21945 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
21946 // CHECK26-NEXT:    ret void
21947 //
21948 //
21949 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2
21950 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
21951 // CHECK26-NEXT:  entry:
21952 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21953 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21954 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21955 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21956 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21957 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i16, align 2
21958 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21959 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21960 // CHECK26-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21961 // CHECK26-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21962 // CHECK26-NEXT:    [[IT:%.*]] = alloca i16, align 2
21963 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21964 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21965 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21966 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21967 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21968 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21969 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21970 // CHECK26-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
21971 // CHECK26-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21972 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21973 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21974 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
21975 // CHECK26-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
21976 // CHECK26-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21977 // CHECK26-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
21978 // CHECK26-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21979 // CHECK26:       cond.true:
21980 // CHECK26-NEXT:    br label [[COND_END:%.*]]
21981 // CHECK26:       cond.false:
21982 // CHECK26-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21983 // CHECK26-NEXT:    br label [[COND_END]]
21984 // CHECK26:       cond.end:
21985 // CHECK26-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
21986 // CHECK26-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21987 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21988 // CHECK26-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
21989 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21990 // CHECK26:       omp.inner.for.cond:
21991 // CHECK26-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21992 // CHECK26-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21993 // CHECK26-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
21994 // CHECK26-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21995 // CHECK26:       omp.inner.for.body:
21996 // CHECK26-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21997 // CHECK26-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
21998 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
21999 // CHECK26-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
22000 // CHECK26-NEXT:    store i16 [[CONV3]], i16* [[IT]], align 2
22001 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
22002 // CHECK26-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
22003 // CHECK26-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8
22004 // CHECK26-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
22005 // CHECK26-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
22006 // CHECK26-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
22007 // CHECK26-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
22008 // CHECK26-NEXT:    store i16 [[CONV7]], i16* [[CONV1]], align 8
22009 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22010 // CHECK26:       omp.body.continue:
22011 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22012 // CHECK26:       omp.inner.for.inc:
22013 // CHECK26-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22014 // CHECK26-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
22015 // CHECK26-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
22016 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]]
22017 // CHECK26:       omp.inner.for.end:
22018 // CHECK26-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22019 // CHECK26:       omp.loop.exit:
22020 // CHECK26-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
22021 // CHECK26-NEXT:    ret void
22022 //
22023 //
22024 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
22025 // CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
22026 // CHECK26-NEXT:  entry:
22027 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22028 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
22029 // CHECK26-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
22030 // CHECK26-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
22031 // CHECK26-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
22032 // CHECK26-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
22033 // CHECK26-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
22034 // CHECK26-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
22035 // CHECK26-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
22036 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
22037 // CHECK26-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
22038 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
22039 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22040 // CHECK26-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
22041 // CHECK26-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
22042 // CHECK26-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
22043 // CHECK26-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
22044 // CHECK26-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
22045 // CHECK26-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
22046 // CHECK26-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
22047 // CHECK26-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
22048 // CHECK26-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
22049 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22050 // CHECK26-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
22051 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
22052 // CHECK26-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
22053 // CHECK26-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
22054 // CHECK26-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
22055 // CHECK26-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
22056 // CHECK26-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
22057 // CHECK26-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
22058 // CHECK26-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
22059 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
22060 // CHECK26-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
22061 // CHECK26-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
22062 // CHECK26-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
22063 // CHECK26-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
22064 // CHECK26-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
22065 // CHECK26-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
22066 // CHECK26-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
22067 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
22068 // CHECK26-NEXT:    ret void
22069 //
22070 //
22071 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3
22072 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
22073 // CHECK26-NEXT:  entry:
22074 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22075 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22076 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22077 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
22078 // CHECK26-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
22079 // CHECK26-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
22080 // CHECK26-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
22081 // CHECK26-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
22082 // CHECK26-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
22083 // CHECK26-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
22084 // CHECK26-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
22085 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
22086 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22087 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i8, align 1
22088 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22089 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22090 // CHECK26-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22091 // CHECK26-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22092 // CHECK26-NEXT:    [[IT:%.*]] = alloca i8, align 1
22093 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22094 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22095 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22096 // CHECK26-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
22097 // CHECK26-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
22098 // CHECK26-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
22099 // CHECK26-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
22100 // CHECK26-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
22101 // CHECK26-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
22102 // CHECK26-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
22103 // CHECK26-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
22104 // CHECK26-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
22105 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22106 // CHECK26-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
22107 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
22108 // CHECK26-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
22109 // CHECK26-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
22110 // CHECK26-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
22111 // CHECK26-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
22112 // CHECK26-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
22113 // CHECK26-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
22114 // CHECK26-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
22115 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22116 // CHECK26-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
22117 // CHECK26-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22118 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22119 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
22120 // CHECK26-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22121 // CHECK26-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
22122 // CHECK26-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
22123 // CHECK26-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
22124 // CHECK26:       omp.dispatch.cond:
22125 // CHECK26-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22126 // CHECK26-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
22127 // CHECK26-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22128 // CHECK26:       cond.true:
22129 // CHECK26-NEXT:    br label [[COND_END:%.*]]
22130 // CHECK26:       cond.false:
22131 // CHECK26-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22132 // CHECK26-NEXT:    br label [[COND_END]]
22133 // CHECK26:       cond.end:
22134 // CHECK26-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
22135 // CHECK26-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22136 // CHECK26-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22137 // CHECK26-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
22138 // CHECK26-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22139 // CHECK26-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22140 // CHECK26-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
22141 // CHECK26-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
22142 // CHECK26:       omp.dispatch.body:
22143 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22144 // CHECK26:       omp.inner.for.cond:
22145 // CHECK26-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22146 // CHECK26-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22147 // CHECK26-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
22148 // CHECK26-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22149 // CHECK26:       omp.inner.for.body:
22150 // CHECK26-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22151 // CHECK26-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
22152 // CHECK26-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
22153 // CHECK26-NEXT:    [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
22154 // CHECK26-NEXT:    store i8 [[CONV8]], i8* [[IT]], align 1
22155 // CHECK26-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
22156 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
22157 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
22158 // CHECK26-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
22159 // CHECK26-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
22160 // CHECK26-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
22161 // CHECK26-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
22162 // CHECK26-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
22163 // CHECK26-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
22164 // CHECK26-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
22165 // CHECK26-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
22166 // CHECK26-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
22167 // CHECK26-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
22168 // CHECK26-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
22169 // CHECK26-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
22170 // CHECK26-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
22171 // CHECK26-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
22172 // CHECK26-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
22173 // CHECK26-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
22174 // CHECK26-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
22175 // CHECK26-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
22176 // CHECK26-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
22177 // CHECK26-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
22178 // CHECK26-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
22179 // CHECK26-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
22180 // CHECK26-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
22181 // CHECK26-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
22182 // CHECK26-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8
22183 // CHECK26-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
22184 // CHECK26-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8
22185 // CHECK26-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
22186 // CHECK26-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
22187 // CHECK26-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
22188 // CHECK26-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
22189 // CHECK26-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
22190 // CHECK26-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8
22191 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22192 // CHECK26:       omp.body.continue:
22193 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22194 // CHECK26:       omp.inner.for.inc:
22195 // CHECK26-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22196 // CHECK26-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
22197 // CHECK26-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
22198 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]]
22199 // CHECK26:       omp.inner.for.end:
22200 // CHECK26-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
22201 // CHECK26:       omp.dispatch.inc:
22202 // CHECK26-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22203 // CHECK26-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
22204 // CHECK26-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
22205 // CHECK26-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
22206 // CHECK26-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22207 // CHECK26-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
22208 // CHECK26-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
22209 // CHECK26-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
22210 // CHECK26-NEXT:    br label [[OMP_DISPATCH_COND]]
22211 // CHECK26:       omp.dispatch.end:
22212 // CHECK26-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
22213 // CHECK26-NEXT:    ret void
22214 //
22215 //
22216 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
22217 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
22218 // CHECK26-NEXT:  entry:
22219 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22220 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22221 // CHECK26-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
22222 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
22223 // CHECK26-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
22224 // CHECK26-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
22225 // CHECK26-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
22226 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22227 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22228 // CHECK26-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
22229 // CHECK26-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
22230 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22231 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22232 // CHECK26-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
22233 // CHECK26-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
22234 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
22235 // CHECK26-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
22236 // CHECK26-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
22237 // CHECK26-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
22238 // CHECK26-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
22239 // CHECK26-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
22240 // CHECK26-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
22241 // CHECK26-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
22242 // CHECK26-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
22243 // CHECK26-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
22244 // CHECK26-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
22245 // CHECK26-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
22246 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
22247 // CHECK26-NEXT:    ret void
22248 //
22249 //
22250 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4
22251 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
22252 // CHECK26-NEXT:  entry:
22253 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22254 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22255 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22256 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22257 // CHECK26-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
22258 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
22259 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22260 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22261 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22262 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22263 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22264 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22265 // CHECK26-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
22266 // CHECK26-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
22267 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22268 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22269 // CHECK26-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
22270 // CHECK26-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
22271 // CHECK26-NEXT:    ret void
22272 //
22273 //
22274 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
22275 // CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
22276 // CHECK26-NEXT:  entry:
22277 // CHECK26-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
22278 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
22279 // CHECK26-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
22280 // CHECK26-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
22281 // CHECK26-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
22282 // CHECK26-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
22283 // CHECK26-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
22284 // CHECK26-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
22285 // CHECK26-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
22286 // CHECK26-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
22287 // CHECK26-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
22288 // CHECK26-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
22289 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
22290 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
22291 // CHECK26-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
22292 // CHECK26-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
22293 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
22294 // CHECK26-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
22295 // CHECK26-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
22296 // CHECK26-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
22297 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
22298 // CHECK26-NEXT:    ret void
22299 //
22300 //
22301 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5
22302 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
22303 // CHECK26-NEXT:  entry:
22304 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22305 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22306 // CHECK26-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
22307 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
22308 // CHECK26-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
22309 // CHECK26-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
22310 // CHECK26-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
22311 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
22312 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i64, align 8
22313 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
22314 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
22315 // CHECK26-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
22316 // CHECK26-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22317 // CHECK26-NEXT:    [[IT:%.*]] = alloca i64, align 8
22318 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22319 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22320 // CHECK26-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
22321 // CHECK26-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
22322 // CHECK26-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
22323 // CHECK26-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
22324 // CHECK26-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
22325 // CHECK26-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
22326 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
22327 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
22328 // CHECK26-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
22329 // CHECK26-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
22330 // CHECK26-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
22331 // CHECK26-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
22332 // CHECK26-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
22333 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22334 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22335 // CHECK26-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
22336 // CHECK26-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
22337 // CHECK26-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
22338 // CHECK26-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
22339 // CHECK26-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22340 // CHECK26:       cond.true:
22341 // CHECK26-NEXT:    br label [[COND_END:%.*]]
22342 // CHECK26:       cond.false:
22343 // CHECK26-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
22344 // CHECK26-NEXT:    br label [[COND_END]]
22345 // CHECK26:       cond.end:
22346 // CHECK26-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
22347 // CHECK26-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
22348 // CHECK26-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
22349 // CHECK26-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
22350 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22351 // CHECK26:       omp.inner.for.cond:
22352 // CHECK26-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
22353 // CHECK26-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
22354 // CHECK26-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
22355 // CHECK26-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22356 // CHECK26:       omp.inner.for.body:
22357 // CHECK26-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
22358 // CHECK26-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
22359 // CHECK26-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
22360 // CHECK26-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
22361 // CHECK26-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
22362 // CHECK26-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
22363 // CHECK26-NEXT:    [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
22364 // CHECK26-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
22365 // CHECK26-NEXT:    store double [[ADD]], double* [[A]], align 8
22366 // CHECK26-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
22367 // CHECK26-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 8
22368 // CHECK26-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
22369 // CHECK26-NEXT:    store double [[INC]], double* [[A5]], align 8
22370 // CHECK26-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
22371 // CHECK26-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
22372 // CHECK26-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
22373 // CHECK26-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
22374 // CHECK26-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
22375 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22376 // CHECK26:       omp.body.continue:
22377 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22378 // CHECK26:       omp.inner.for.inc:
22379 // CHECK26-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
22380 // CHECK26-NEXT:    [[ADD8:%.*]] = add i64 [[TMP15]], 1
22381 // CHECK26-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
22382 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]]
22383 // CHECK26:       omp.inner.for.end:
22384 // CHECK26-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22385 // CHECK26:       omp.loop.exit:
22386 // CHECK26-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
22387 // CHECK26-NEXT:    ret void
22388 //
22389 //
22390 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
22391 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
22392 // CHECK26-NEXT:  entry:
22393 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22394 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22395 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
22396 // CHECK26-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
22397 // CHECK26-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
22398 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22399 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22400 // CHECK26-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
22401 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22402 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22403 // CHECK26-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
22404 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
22405 // CHECK26-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
22406 // CHECK26-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
22407 // CHECK26-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
22408 // CHECK26-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
22409 // CHECK26-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
22410 // CHECK26-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
22411 // CHECK26-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
22412 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
22413 // CHECK26-NEXT:    ret void
22414 //
22415 //
22416 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6
22417 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
22418 // CHECK26-NEXT:  entry:
22419 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22420 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22421 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22422 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22423 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
22424 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
22425 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i64, align 8
22426 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
22427 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
22428 // CHECK26-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
22429 // CHECK26-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22430 // CHECK26-NEXT:    [[I:%.*]] = alloca i64, align 8
22431 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22432 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22433 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22434 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22435 // CHECK26-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
22436 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22437 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22438 // CHECK26-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
22439 // CHECK26-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
22440 // CHECK26-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
22441 // CHECK26-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
22442 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22443 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22444 // CHECK26-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
22445 // CHECK26-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
22446 // CHECK26-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
22447 // CHECK26-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
22448 // CHECK26-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22449 // CHECK26:       cond.true:
22450 // CHECK26-NEXT:    br label [[COND_END:%.*]]
22451 // CHECK26:       cond.false:
22452 // CHECK26-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
22453 // CHECK26-NEXT:    br label [[COND_END]]
22454 // CHECK26:       cond.end:
22455 // CHECK26-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
22456 // CHECK26-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
22457 // CHECK26-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
22458 // CHECK26-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
22459 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22460 // CHECK26:       omp.inner.for.cond:
22461 // CHECK26-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
22462 // CHECK26-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
22463 // CHECK26-NEXT:    [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
22464 // CHECK26-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22465 // CHECK26:       omp.inner.for.body:
22466 // CHECK26-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
22467 // CHECK26-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
22468 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
22469 // CHECK26-NEXT:    store i64 [[ADD]], i64* [[I]], align 8
22470 // CHECK26-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
22471 // CHECK26-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
22472 // CHECK26-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
22473 // CHECK26-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
22474 // CHECK26-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
22475 // CHECK26-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
22476 // CHECK26-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
22477 // CHECK26-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
22478 // CHECK26-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
22479 // CHECK26-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
22480 // CHECK26-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
22481 // CHECK26-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
22482 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22483 // CHECK26:       omp.body.continue:
22484 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22485 // CHECK26:       omp.inner.for.inc:
22486 // CHECK26-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
22487 // CHECK26-NEXT:    [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
22488 // CHECK26-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
22489 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]]
22490 // CHECK26:       omp.inner.for.end:
22491 // CHECK26-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22492 // CHECK26:       omp.loop.exit:
22493 // CHECK26-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
22494 // CHECK26-NEXT:    ret void
22495 //
22496 //
22497 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
22498 // CHECK27-SAME: () #[[ATTR0:[0-9]+]] {
22499 // CHECK27-NEXT:  entry:
22500 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
22501 // CHECK27-NEXT:    ret void
22502 //
22503 //
22504 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined.
22505 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
22506 // CHECK27-NEXT:  entry:
22507 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
22508 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
22509 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22510 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22511 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22512 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22513 // CHECK27-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22514 // CHECK27-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22515 // CHECK27-NEXT:    [[I:%.*]] = alloca i32, align 4
22516 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
22517 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
22518 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22519 // CHECK27-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
22520 // CHECK27-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22521 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22522 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
22523 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
22524 // CHECK27-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22525 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22526 // CHECK27-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
22527 // CHECK27-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22528 // CHECK27:       cond.true:
22529 // CHECK27-NEXT:    br label [[COND_END:%.*]]
22530 // CHECK27:       cond.false:
22531 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22532 // CHECK27-NEXT:    br label [[COND_END]]
22533 // CHECK27:       cond.end:
22534 // CHECK27-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
22535 // CHECK27-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22536 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22537 // CHECK27-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
22538 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22539 // CHECK27:       omp.inner.for.cond:
22540 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22541 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22542 // CHECK27-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
22543 // CHECK27-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22544 // CHECK27:       omp.inner.for.body:
22545 // CHECK27-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22546 // CHECK27-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
22547 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
22548 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
22549 // CHECK27-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
22550 // CHECK27-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
22551 // CHECK27-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
22552 // CHECK27:       .cancel.exit:
22553 // CHECK27-NEXT:    br label [[CANCEL_EXIT:%.*]]
22554 // CHECK27:       .cancel.continue:
22555 // CHECK27-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
22556 // CHECK27-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
22557 // CHECK27-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
22558 // CHECK27:       .cancel.exit2:
22559 // CHECK27-NEXT:    br label [[CANCEL_EXIT]]
22560 // CHECK27:       .cancel.continue3:
22561 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22562 // CHECK27:       omp.body.continue:
22563 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22564 // CHECK27:       omp.inner.for.inc:
22565 // CHECK27-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22566 // CHECK27-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
22567 // CHECK27-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
22568 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]]
22569 // CHECK27:       omp.inner.for.end:
22570 // CHECK27-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22571 // CHECK27:       omp.loop.exit:
22572 // CHECK27-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
22573 // CHECK27-NEXT:    br label [[CANCEL_CONT:%.*]]
22574 // CHECK27:       cancel.cont:
22575 // CHECK27-NEXT:    ret void
22576 // CHECK27:       cancel.exit:
22577 // CHECK27-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
22578 // CHECK27-NEXT:    br label [[CANCEL_CONT]]
22579 //
22580 //
22581 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
22582 // CHECK27-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
22583 // CHECK27-NEXT:  entry:
22584 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
22585 // CHECK27-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
22586 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
22587 // CHECK27-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
22588 // CHECK27-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
22589 // CHECK27-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
22590 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
22591 // CHECK27-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
22592 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
22593 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
22594 // CHECK27-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
22595 // CHECK27-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
22596 // CHECK27-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
22597 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
22598 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
22599 // CHECK27-NEXT:    store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
22600 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
22601 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
22602 // CHECK27-NEXT:    store i32 [[TMP4]], i32* [[A_CASTED]], align 4
22603 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
22604 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
22605 // CHECK27-NEXT:    ret void
22606 //
22607 //
22608 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1
22609 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
22610 // CHECK27-NEXT:  entry:
22611 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
22612 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
22613 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
22614 // CHECK27-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
22615 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
22616 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
22617 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i64, align 4
22618 // CHECK27-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
22619 // CHECK27-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
22620 // CHECK27-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
22621 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
22622 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
22623 // CHECK27-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
22624 // CHECK27-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22625 // CHECK27-NEXT:    [[IT:%.*]] = alloca i64, align 8
22626 // CHECK27-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
22627 // CHECK27-NEXT:    [[A3:%.*]] = alloca i32, align 4
22628 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
22629 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
22630 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
22631 // CHECK27-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
22632 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
22633 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
22634 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
22635 // CHECK27-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
22636 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
22637 // CHECK27-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
22638 // CHECK27-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]]
22639 // CHECK27-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
22640 // CHECK27-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
22641 // CHECK27-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
22642 // CHECK27-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
22643 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22644 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
22645 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
22646 // CHECK27-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
22647 // CHECK27-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
22648 // CHECK27-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
22649 // CHECK27-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
22650 // CHECK27-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22651 // CHECK27:       cond.true:
22652 // CHECK27-NEXT:    br label [[COND_END:%.*]]
22653 // CHECK27:       cond.false:
22654 // CHECK27-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
22655 // CHECK27-NEXT:    br label [[COND_END]]
22656 // CHECK27:       cond.end:
22657 // CHECK27-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
22658 // CHECK27-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
22659 // CHECK27-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
22660 // CHECK27-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
22661 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22662 // CHECK27:       omp.inner.for.cond:
22663 // CHECK27-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
22664 // CHECK27-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
22665 // CHECK27-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
22666 // CHECK27-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22667 // CHECK27:       omp.inner.for.body:
22668 // CHECK27-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
22669 // CHECK27-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
22670 // CHECK27-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
22671 // CHECK27-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
22672 // CHECK27-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
22673 // CHECK27-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
22674 // CHECK27-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
22675 // CHECK27-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
22676 // CHECK27-NEXT:    [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
22677 // CHECK27-NEXT:    [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
22678 // CHECK27-NEXT:    [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
22679 // CHECK27-NEXT:    store i32 [[CONV7]], i32* [[LIN2]], align 4
22680 // CHECK27-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
22681 // CHECK27-NEXT:    [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
22682 // CHECK27-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
22683 // CHECK27-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
22684 // CHECK27-NEXT:    [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
22685 // CHECK27-NEXT:    [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
22686 // CHECK27-NEXT:    [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
22687 // CHECK27-NEXT:    store i32 [[CONV11]], i32* [[A3]], align 4
22688 // CHECK27-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4
22689 // CHECK27-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
22690 // CHECK27-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
22691 // CHECK27-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
22692 // CHECK27-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4
22693 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22694 // CHECK27:       omp.body.continue:
22695 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22696 // CHECK27:       omp.inner.for.inc:
22697 // CHECK27-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
22698 // CHECK27-NEXT:    [[ADD15:%.*]] = add i64 [[TMP17]], 1
22699 // CHECK27-NEXT:    store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
22700 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]]
22701 // CHECK27:       omp.inner.for.end:
22702 // CHECK27-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22703 // CHECK27:       omp.loop.exit:
22704 // CHECK27-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
22705 // CHECK27-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
22706 // CHECK27-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
22707 // CHECK27-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
22708 // CHECK27:       .omp.linear.pu:
22709 // CHECK27-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
22710 // CHECK27-NEXT:    [[CONV16:%.*]] = sext i32 [[TMP20]] to i64
22711 // CHECK27-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
22712 // CHECK27-NEXT:    [[MUL17:%.*]] = mul i64 4, [[TMP21]]
22713 // CHECK27-NEXT:    [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
22714 // CHECK27-NEXT:    [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
22715 // CHECK27-NEXT:    store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
22716 // CHECK27-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
22717 // CHECK27-NEXT:    [[CONV20:%.*]] = sext i32 [[TMP22]] to i64
22718 // CHECK27-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
22719 // CHECK27-NEXT:    [[MUL21:%.*]] = mul i64 4, [[TMP23]]
22720 // CHECK27-NEXT:    [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
22721 // CHECK27-NEXT:    [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
22722 // CHECK27-NEXT:    store i32 [[CONV23]], i32* [[A_ADDR]], align 4
22723 // CHECK27-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
22724 // CHECK27:       .omp.linear.pu.done:
22725 // CHECK27-NEXT:    ret void
22726 //
22727 //
22728 // CHECK27-LABEL: define {{[^@]+}}@_Z7get_valv
22729 // CHECK27-SAME: () #[[ATTR2:[0-9]+]] {
22730 // CHECK27-NEXT:  entry:
22731 // CHECK27-NEXT:    ret i64 0
22732 //
22733 //
22734 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
22735 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
22736 // CHECK27-NEXT:  entry:
22737 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
22738 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
22739 // CHECK27-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
22740 // CHECK27-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
22741 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
22742 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
22743 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
22744 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
22745 // CHECK27-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
22746 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
22747 // CHECK27-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
22748 // CHECK27-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
22749 // CHECK27-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
22750 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
22751 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
22752 // CHECK27-NEXT:    ret void
22753 //
22754 //
22755 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2
22756 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
22757 // CHECK27-NEXT:  entry:
22758 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
22759 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
22760 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
22761 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
22762 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22763 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i16, align 2
22764 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22765 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22766 // CHECK27-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22767 // CHECK27-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22768 // CHECK27-NEXT:    [[IT:%.*]] = alloca i16, align 2
22769 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
22770 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
22771 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
22772 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
22773 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
22774 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22775 // CHECK27-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
22776 // CHECK27-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22777 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22778 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
22779 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
22780 // CHECK27-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22781 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22782 // CHECK27-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
22783 // CHECK27-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22784 // CHECK27:       cond.true:
22785 // CHECK27-NEXT:    br label [[COND_END:%.*]]
22786 // CHECK27:       cond.false:
22787 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22788 // CHECK27-NEXT:    br label [[COND_END]]
22789 // CHECK27:       cond.end:
22790 // CHECK27-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
22791 // CHECK27-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22792 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22793 // CHECK27-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
22794 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22795 // CHECK27:       omp.inner.for.cond:
22796 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22797 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22798 // CHECK27-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
22799 // CHECK27-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22800 // CHECK27:       omp.inner.for.body:
22801 // CHECK27-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22802 // CHECK27-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
22803 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
22804 // CHECK27-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
22805 // CHECK27-NEXT:    store i16 [[CONV2]], i16* [[IT]], align 2
22806 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
22807 // CHECK27-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
22808 // CHECK27-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4
22809 // CHECK27-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
22810 // CHECK27-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
22811 // CHECK27-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
22812 // CHECK27-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
22813 // CHECK27-NEXT:    store i16 [[CONV6]], i16* [[CONV]], align 4
22814 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22815 // CHECK27:       omp.body.continue:
22816 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22817 // CHECK27:       omp.inner.for.inc:
22818 // CHECK27-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22819 // CHECK27-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
22820 // CHECK27-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
22821 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]]
22822 // CHECK27:       omp.inner.for.end:
22823 // CHECK27-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22824 // CHECK27:       omp.loop.exit:
22825 // CHECK27-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
22826 // CHECK27-NEXT:    ret void
22827 //
22828 //
22829 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
22830 // CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
22831 // CHECK27-NEXT:  entry:
22832 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
22833 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
22834 // CHECK27-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
22835 // CHECK27-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
22836 // CHECK27-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
22837 // CHECK27-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
22838 // CHECK27-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
22839 // CHECK27-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
22840 // CHECK27-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
22841 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
22842 // CHECK27-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
22843 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
22844 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
22845 // CHECK27-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
22846 // CHECK27-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
22847 // CHECK27-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
22848 // CHECK27-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
22849 // CHECK27-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
22850 // CHECK27-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
22851 // CHECK27-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
22852 // CHECK27-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
22853 // CHECK27-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
22854 // CHECK27-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
22855 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
22856 // CHECK27-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
22857 // CHECK27-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
22858 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
22859 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
22860 // CHECK27-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
22861 // CHECK27-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
22862 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
22863 // CHECK27-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
22864 // CHECK27-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
22865 // CHECK27-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
22866 // CHECK27-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
22867 // CHECK27-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
22868 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
22869 // CHECK27-NEXT:    ret void
22870 //
22871 //
22872 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3
22873 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
22874 // CHECK27-NEXT:  entry:
22875 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
22876 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
22877 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
22878 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
22879 // CHECK27-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
22880 // CHECK27-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
22881 // CHECK27-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
22882 // CHECK27-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
22883 // CHECK27-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
22884 // CHECK27-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
22885 // CHECK27-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
22886 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
22887 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22888 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i8, align 1
22889 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22890 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22891 // CHECK27-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22892 // CHECK27-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22893 // CHECK27-NEXT:    [[IT:%.*]] = alloca i8, align 1
22894 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
22895 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
22896 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
22897 // CHECK27-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
22898 // CHECK27-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
22899 // CHECK27-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
22900 // CHECK27-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
22901 // CHECK27-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
22902 // CHECK27-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
22903 // CHECK27-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
22904 // CHECK27-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
22905 // CHECK27-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
22906 // CHECK27-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
22907 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
22908 // CHECK27-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
22909 // CHECK27-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
22910 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
22911 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
22912 // CHECK27-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
22913 // CHECK27-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
22914 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22915 // CHECK27-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
22916 // CHECK27-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22917 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22918 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
22919 // CHECK27-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
22920 // CHECK27-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
22921 // CHECK27-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
22922 // CHECK27-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
22923 // CHECK27:       omp.dispatch.cond:
22924 // CHECK27-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22925 // CHECK27-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
22926 // CHECK27-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22927 // CHECK27:       cond.true:
22928 // CHECK27-NEXT:    br label [[COND_END:%.*]]
22929 // CHECK27:       cond.false:
22930 // CHECK27-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22931 // CHECK27-NEXT:    br label [[COND_END]]
22932 // CHECK27:       cond.end:
22933 // CHECK27-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
22934 // CHECK27-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22935 // CHECK27-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22936 // CHECK27-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
22937 // CHECK27-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22938 // CHECK27-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22939 // CHECK27-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
22940 // CHECK27-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
22941 // CHECK27:       omp.dispatch.body:
22942 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22943 // CHECK27:       omp.inner.for.cond:
22944 // CHECK27-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22945 // CHECK27-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22946 // CHECK27-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
22947 // CHECK27-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22948 // CHECK27:       omp.inner.for.body:
22949 // CHECK27-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22950 // CHECK27-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
22951 // CHECK27-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
22952 // CHECK27-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
22953 // CHECK27-NEXT:    store i8 [[CONV]], i8* [[IT]], align 1
22954 // CHECK27-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
22955 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
22956 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
22957 // CHECK27-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
22958 // CHECK27-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
22959 // CHECK27-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
22960 // CHECK27-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
22961 // CHECK27-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
22962 // CHECK27-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4
22963 // CHECK27-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
22964 // CHECK27-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
22965 // CHECK27-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
22966 // CHECK27-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
22967 // CHECK27-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
22968 // CHECK27-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4
22969 // CHECK27-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
22970 // CHECK27-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
22971 // CHECK27-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
22972 // CHECK27-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
22973 // CHECK27-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8
22974 // CHECK27-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
22975 // CHECK27-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
22976 // CHECK27-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
22977 // CHECK27-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
22978 // CHECK27-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
22979 // CHECK27-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8
22980 // CHECK27-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
22981 // CHECK27-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4
22982 // CHECK27-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
22983 // CHECK27-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4
22984 // CHECK27-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
22985 // CHECK27-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
22986 // CHECK27-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
22987 // CHECK27-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
22988 // CHECK27-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
22989 // CHECK27-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4
22990 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22991 // CHECK27:       omp.body.continue:
22992 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22993 // CHECK27:       omp.inner.for.inc:
22994 // CHECK27-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22995 // CHECK27-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
22996 // CHECK27-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
22997 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]]
22998 // CHECK27:       omp.inner.for.end:
22999 // CHECK27-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
23000 // CHECK27:       omp.dispatch.inc:
23001 // CHECK27-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23002 // CHECK27-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
23003 // CHECK27-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
23004 // CHECK27-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
23005 // CHECK27-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23006 // CHECK27-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
23007 // CHECK27-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
23008 // CHECK27-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
23009 // CHECK27-NEXT:    br label [[OMP_DISPATCH_COND]]
23010 // CHECK27:       omp.dispatch.end:
23011 // CHECK27-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
23012 // CHECK27-NEXT:    ret void
23013 //
23014 //
23015 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
23016 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23017 // CHECK27-NEXT:  entry:
23018 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23019 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23020 // CHECK27-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
23021 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
23022 // CHECK27-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
23023 // CHECK27-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23024 // CHECK27-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
23025 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23026 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23027 // CHECK27-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
23028 // CHECK27-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
23029 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23030 // CHECK27-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
23031 // CHECK27-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
23032 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
23033 // CHECK27-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
23034 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
23035 // CHECK27-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
23036 // CHECK27-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
23037 // CHECK27-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
23038 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
23039 // CHECK27-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
23040 // CHECK27-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
23041 // CHECK27-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
23042 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
23043 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
23044 // CHECK27-NEXT:    ret void
23045 //
23046 //
23047 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4
23048 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23049 // CHECK27-NEXT:  entry:
23050 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23051 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23052 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23053 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23054 // CHECK27-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
23055 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
23056 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23057 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23058 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23059 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23060 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23061 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23062 // CHECK27-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
23063 // CHECK27-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
23064 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23065 // CHECK27-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
23066 // CHECK27-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
23067 // CHECK27-NEXT:    ret void
23068 //
23069 //
23070 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
23071 // CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
23072 // CHECK27-NEXT:  entry:
23073 // CHECK27-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
23074 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
23075 // CHECK27-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
23076 // CHECK27-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
23077 // CHECK27-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
23078 // CHECK27-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
23079 // CHECK27-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
23080 // CHECK27-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
23081 // CHECK27-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
23082 // CHECK27-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
23083 // CHECK27-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
23084 // CHECK27-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
23085 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
23086 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
23087 // CHECK27-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
23088 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
23089 // CHECK27-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
23090 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
23091 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
23092 // CHECK27-NEXT:    ret void
23093 //
23094 //
23095 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5
23096 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
23097 // CHECK27-NEXT:  entry:
23098 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23099 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23100 // CHECK27-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
23101 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
23102 // CHECK27-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
23103 // CHECK27-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
23104 // CHECK27-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
23105 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
23106 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i64, align 4
23107 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
23108 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
23109 // CHECK27-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
23110 // CHECK27-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23111 // CHECK27-NEXT:    [[IT:%.*]] = alloca i64, align 8
23112 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23113 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23114 // CHECK27-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
23115 // CHECK27-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
23116 // CHECK27-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
23117 // CHECK27-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
23118 // CHECK27-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
23119 // CHECK27-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
23120 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
23121 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
23122 // CHECK27-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
23123 // CHECK27-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
23124 // CHECK27-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
23125 // CHECK27-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
23126 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23127 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23128 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
23129 // CHECK27-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
23130 // CHECK27-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23131 // CHECK27-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
23132 // CHECK27-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23133 // CHECK27:       cond.true:
23134 // CHECK27-NEXT:    br label [[COND_END:%.*]]
23135 // CHECK27:       cond.false:
23136 // CHECK27-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23137 // CHECK27-NEXT:    br label [[COND_END]]
23138 // CHECK27:       cond.end:
23139 // CHECK27-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
23140 // CHECK27-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
23141 // CHECK27-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
23142 // CHECK27-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
23143 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23144 // CHECK27:       omp.inner.for.cond:
23145 // CHECK27-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
23146 // CHECK27-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23147 // CHECK27-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
23148 // CHECK27-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23149 // CHECK27:       omp.inner.for.body:
23150 // CHECK27-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
23151 // CHECK27-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
23152 // CHECK27-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
23153 // CHECK27-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
23154 // CHECK27-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
23155 // CHECK27-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
23156 // CHECK27-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
23157 // CHECK27-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
23158 // CHECK27-NEXT:    store double [[ADD]], double* [[A]], align 4
23159 // CHECK27-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
23160 // CHECK27-NEXT:    [[TMP13:%.*]] = load double, double* [[A4]], align 4
23161 // CHECK27-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
23162 // CHECK27-NEXT:    store double [[INC]], double* [[A4]], align 4
23163 // CHECK27-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
23164 // CHECK27-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
23165 // CHECK27-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
23166 // CHECK27-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
23167 // CHECK27-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
23168 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23169 // CHECK27:       omp.body.continue:
23170 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23171 // CHECK27:       omp.inner.for.inc:
23172 // CHECK27-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
23173 // CHECK27-NEXT:    [[ADD7:%.*]] = add i64 [[TMP15]], 1
23174 // CHECK27-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
23175 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]]
23176 // CHECK27:       omp.inner.for.end:
23177 // CHECK27-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23178 // CHECK27:       omp.loop.exit:
23179 // CHECK27-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
23180 // CHECK27-NEXT:    ret void
23181 //
23182 //
23183 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
23184 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23185 // CHECK27-NEXT:  entry:
23186 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23187 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23188 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
23189 // CHECK27-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
23190 // CHECK27-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23191 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23192 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23193 // CHECK27-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
23194 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23195 // CHECK27-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
23196 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
23197 // CHECK27-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
23198 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
23199 // CHECK27-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
23200 // CHECK27-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
23201 // CHECK27-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
23202 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
23203 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
23204 // CHECK27-NEXT:    ret void
23205 //
23206 //
23207 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6
23208 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23209 // CHECK27-NEXT:  entry:
23210 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23211 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23212 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23213 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23214 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
23215 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
23216 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i64, align 4
23217 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
23218 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
23219 // CHECK27-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
23220 // CHECK27-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23221 // CHECK27-NEXT:    [[I:%.*]] = alloca i64, align 8
23222 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23223 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23224 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23225 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23226 // CHECK27-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
23227 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23228 // CHECK27-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
23229 // CHECK27-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
23230 // CHECK27-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
23231 // CHECK27-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
23232 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23233 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23234 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
23235 // CHECK27-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
23236 // CHECK27-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23237 // CHECK27-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
23238 // CHECK27-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23239 // CHECK27:       cond.true:
23240 // CHECK27-NEXT:    br label [[COND_END:%.*]]
23241 // CHECK27:       cond.false:
23242 // CHECK27-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23243 // CHECK27-NEXT:    br label [[COND_END]]
23244 // CHECK27:       cond.end:
23245 // CHECK27-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
23246 // CHECK27-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
23247 // CHECK27-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
23248 // CHECK27-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
23249 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23250 // CHECK27:       omp.inner.for.cond:
23251 // CHECK27-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
23252 // CHECK27-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23253 // CHECK27-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
23254 // CHECK27-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23255 // CHECK27:       omp.inner.for.body:
23256 // CHECK27-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
23257 // CHECK27-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
23258 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
23259 // CHECK27-NEXT:    store i64 [[ADD]], i64* [[I]], align 8
23260 // CHECK27-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
23261 // CHECK27-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
23262 // CHECK27-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
23263 // CHECK27-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
23264 // CHECK27-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
23265 // CHECK27-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
23266 // CHECK27-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
23267 // CHECK27-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
23268 // CHECK27-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
23269 // CHECK27-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
23270 // CHECK27-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
23271 // CHECK27-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
23272 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23273 // CHECK27:       omp.body.continue:
23274 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23275 // CHECK27:       omp.inner.for.inc:
23276 // CHECK27-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
23277 // CHECK27-NEXT:    [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
23278 // CHECK27-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
23279 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]]
23280 // CHECK27:       omp.inner.for.end:
23281 // CHECK27-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23282 // CHECK27:       omp.loop.exit:
23283 // CHECK27-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
23284 // CHECK27-NEXT:    ret void
23285 //
23286 //
23287 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
23288 // CHECK28-SAME: () #[[ATTR0:[0-9]+]] {
23289 // CHECK28-NEXT:  entry:
23290 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
23291 // CHECK28-NEXT:    ret void
23292 //
23293 //
23294 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined.
23295 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
23296 // CHECK28-NEXT:  entry:
23297 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23298 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23299 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23300 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23301 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23302 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23303 // CHECK28-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23304 // CHECK28-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23305 // CHECK28-NEXT:    [[I:%.*]] = alloca i32, align 4
23306 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23307 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23308 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23309 // CHECK28-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
23310 // CHECK28-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23311 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23312 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23313 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
23314 // CHECK28-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23315 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23316 // CHECK28-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
23317 // CHECK28-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23318 // CHECK28:       cond.true:
23319 // CHECK28-NEXT:    br label [[COND_END:%.*]]
23320 // CHECK28:       cond.false:
23321 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23322 // CHECK28-NEXT:    br label [[COND_END]]
23323 // CHECK28:       cond.end:
23324 // CHECK28-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
23325 // CHECK28-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23326 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23327 // CHECK28-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
23328 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23329 // CHECK28:       omp.inner.for.cond:
23330 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23331 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23332 // CHECK28-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
23333 // CHECK28-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23334 // CHECK28:       omp.inner.for.body:
23335 // CHECK28-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23336 // CHECK28-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
23337 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
23338 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
23339 // CHECK28-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
23340 // CHECK28-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
23341 // CHECK28-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
23342 // CHECK28:       .cancel.exit:
23343 // CHECK28-NEXT:    br label [[CANCEL_EXIT:%.*]]
23344 // CHECK28:       .cancel.continue:
23345 // CHECK28-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
23346 // CHECK28-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
23347 // CHECK28-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
23348 // CHECK28:       .cancel.exit2:
23349 // CHECK28-NEXT:    br label [[CANCEL_EXIT]]
23350 // CHECK28:       .cancel.continue3:
23351 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23352 // CHECK28:       omp.body.continue:
23353 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23354 // CHECK28:       omp.inner.for.inc:
23355 // CHECK28-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23356 // CHECK28-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
23357 // CHECK28-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
23358 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]]
23359 // CHECK28:       omp.inner.for.end:
23360 // CHECK28-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23361 // CHECK28:       omp.loop.exit:
23362 // CHECK28-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
23363 // CHECK28-NEXT:    br label [[CANCEL_CONT:%.*]]
23364 // CHECK28:       cancel.cont:
23365 // CHECK28-NEXT:    ret void
23366 // CHECK28:       cancel.exit:
23367 // CHECK28-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
23368 // CHECK28-NEXT:    br label [[CANCEL_CONT]]
23369 //
23370 //
23371 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
23372 // CHECK28-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
23373 // CHECK28-NEXT:  entry:
23374 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23375 // CHECK28-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
23376 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23377 // CHECK28-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23378 // CHECK28-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
23379 // CHECK28-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
23380 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23381 // CHECK28-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
23382 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23383 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23384 // CHECK28-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
23385 // CHECK28-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
23386 // CHECK28-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
23387 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
23388 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
23389 // CHECK28-NEXT:    store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
23390 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
23391 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
23392 // CHECK28-NEXT:    store i32 [[TMP4]], i32* [[A_CASTED]], align 4
23393 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
23394 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
23395 // CHECK28-NEXT:    ret void
23396 //
23397 //
23398 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1
23399 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
23400 // CHECK28-NEXT:  entry:
23401 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23402 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23403 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23404 // CHECK28-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
23405 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23406 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
23407 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i64, align 4
23408 // CHECK28-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
23409 // CHECK28-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
23410 // CHECK28-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
23411 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
23412 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
23413 // CHECK28-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
23414 // CHECK28-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23415 // CHECK28-NEXT:    [[IT:%.*]] = alloca i64, align 8
23416 // CHECK28-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
23417 // CHECK28-NEXT:    [[A3:%.*]] = alloca i32, align 4
23418 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23419 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23420 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23421 // CHECK28-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
23422 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23423 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23424 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
23425 // CHECK28-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
23426 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
23427 // CHECK28-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
23428 // CHECK28-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR4:[0-9]+]]
23429 // CHECK28-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
23430 // CHECK28-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
23431 // CHECK28-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
23432 // CHECK28-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
23433 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23434 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23435 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
23436 // CHECK28-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
23437 // CHECK28-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
23438 // CHECK28-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23439 // CHECK28-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
23440 // CHECK28-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23441 // CHECK28:       cond.true:
23442 // CHECK28-NEXT:    br label [[COND_END:%.*]]
23443 // CHECK28:       cond.false:
23444 // CHECK28-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23445 // CHECK28-NEXT:    br label [[COND_END]]
23446 // CHECK28:       cond.end:
23447 // CHECK28-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
23448 // CHECK28-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
23449 // CHECK28-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
23450 // CHECK28-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
23451 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23452 // CHECK28:       omp.inner.for.cond:
23453 // CHECK28-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
23454 // CHECK28-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23455 // CHECK28-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
23456 // CHECK28-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23457 // CHECK28:       omp.inner.for.body:
23458 // CHECK28-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
23459 // CHECK28-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
23460 // CHECK28-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
23461 // CHECK28-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
23462 // CHECK28-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
23463 // CHECK28-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
23464 // CHECK28-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
23465 // CHECK28-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
23466 // CHECK28-NEXT:    [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
23467 // CHECK28-NEXT:    [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
23468 // CHECK28-NEXT:    [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
23469 // CHECK28-NEXT:    store i32 [[CONV7]], i32* [[LIN2]], align 4
23470 // CHECK28-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
23471 // CHECK28-NEXT:    [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
23472 // CHECK28-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
23473 // CHECK28-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
23474 // CHECK28-NEXT:    [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
23475 // CHECK28-NEXT:    [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
23476 // CHECK28-NEXT:    [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
23477 // CHECK28-NEXT:    store i32 [[CONV11]], i32* [[A3]], align 4
23478 // CHECK28-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4
23479 // CHECK28-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
23480 // CHECK28-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
23481 // CHECK28-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
23482 // CHECK28-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4
23483 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23484 // CHECK28:       omp.body.continue:
23485 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23486 // CHECK28:       omp.inner.for.inc:
23487 // CHECK28-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
23488 // CHECK28-NEXT:    [[ADD15:%.*]] = add i64 [[TMP17]], 1
23489 // CHECK28-NEXT:    store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
23490 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]]
23491 // CHECK28:       omp.inner.for.end:
23492 // CHECK28-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23493 // CHECK28:       omp.loop.exit:
23494 // CHECK28-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
23495 // CHECK28-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
23496 // CHECK28-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
23497 // CHECK28-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
23498 // CHECK28:       .omp.linear.pu:
23499 // CHECK28-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
23500 // CHECK28-NEXT:    [[CONV16:%.*]] = sext i32 [[TMP20]] to i64
23501 // CHECK28-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
23502 // CHECK28-NEXT:    [[MUL17:%.*]] = mul i64 4, [[TMP21]]
23503 // CHECK28-NEXT:    [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
23504 // CHECK28-NEXT:    [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
23505 // CHECK28-NEXT:    store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
23506 // CHECK28-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
23507 // CHECK28-NEXT:    [[CONV20:%.*]] = sext i32 [[TMP22]] to i64
23508 // CHECK28-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
23509 // CHECK28-NEXT:    [[MUL21:%.*]] = mul i64 4, [[TMP23]]
23510 // CHECK28-NEXT:    [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
23511 // CHECK28-NEXT:    [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
23512 // CHECK28-NEXT:    store i32 [[CONV23]], i32* [[A_ADDR]], align 4
23513 // CHECK28-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
23514 // CHECK28:       .omp.linear.pu.done:
23515 // CHECK28-NEXT:    ret void
23516 //
23517 //
23518 // CHECK28-LABEL: define {{[^@]+}}@_Z7get_valv
23519 // CHECK28-SAME: () #[[ATTR2:[0-9]+]] {
23520 // CHECK28-NEXT:  entry:
23521 // CHECK28-NEXT:    ret i64 0
23522 //
23523 //
23524 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
23525 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
23526 // CHECK28-NEXT:  entry:
23527 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23528 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23529 // CHECK28-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
23530 // CHECK28-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23531 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23532 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23533 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23534 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
23535 // CHECK28-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
23536 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
23537 // CHECK28-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
23538 // CHECK28-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
23539 // CHECK28-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
23540 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
23541 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
23542 // CHECK28-NEXT:    ret void
23543 //
23544 //
23545 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2
23546 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
23547 // CHECK28-NEXT:  entry:
23548 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23549 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23550 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23551 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23552 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23553 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i16, align 2
23554 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23555 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23556 // CHECK28-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23557 // CHECK28-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23558 // CHECK28-NEXT:    [[IT:%.*]] = alloca i16, align 2
23559 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23560 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23561 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23562 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23563 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23564 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23565 // CHECK28-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
23566 // CHECK28-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23567 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23568 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23569 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
23570 // CHECK28-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23571 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23572 // CHECK28-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
23573 // CHECK28-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23574 // CHECK28:       cond.true:
23575 // CHECK28-NEXT:    br label [[COND_END:%.*]]
23576 // CHECK28:       cond.false:
23577 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23578 // CHECK28-NEXT:    br label [[COND_END]]
23579 // CHECK28:       cond.end:
23580 // CHECK28-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
23581 // CHECK28-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23582 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23583 // CHECK28-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
23584 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23585 // CHECK28:       omp.inner.for.cond:
23586 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23587 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23588 // CHECK28-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
23589 // CHECK28-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23590 // CHECK28:       omp.inner.for.body:
23591 // CHECK28-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23592 // CHECK28-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
23593 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
23594 // CHECK28-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
23595 // CHECK28-NEXT:    store i16 [[CONV2]], i16* [[IT]], align 2
23596 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
23597 // CHECK28-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
23598 // CHECK28-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4
23599 // CHECK28-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
23600 // CHECK28-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
23601 // CHECK28-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
23602 // CHECK28-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
23603 // CHECK28-NEXT:    store i16 [[CONV6]], i16* [[CONV]], align 4
23604 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23605 // CHECK28:       omp.body.continue:
23606 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23607 // CHECK28:       omp.inner.for.inc:
23608 // CHECK28-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23609 // CHECK28-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
23610 // CHECK28-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
23611 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]]
23612 // CHECK28:       omp.inner.for.end:
23613 // CHECK28-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23614 // CHECK28:       omp.loop.exit:
23615 // CHECK28-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
23616 // CHECK28-NEXT:    ret void
23617 //
23618 //
23619 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
23620 // CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
23621 // CHECK28-NEXT:  entry:
23622 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23623 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
23624 // CHECK28-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
23625 // CHECK28-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
23626 // CHECK28-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
23627 // CHECK28-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
23628 // CHECK28-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
23629 // CHECK28-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
23630 // CHECK28-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
23631 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
23632 // CHECK28-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
23633 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
23634 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23635 // CHECK28-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
23636 // CHECK28-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
23637 // CHECK28-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
23638 // CHECK28-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
23639 // CHECK28-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
23640 // CHECK28-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
23641 // CHECK28-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
23642 // CHECK28-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
23643 // CHECK28-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
23644 // CHECK28-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
23645 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
23646 // CHECK28-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
23647 // CHECK28-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
23648 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
23649 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
23650 // CHECK28-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
23651 // CHECK28-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
23652 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
23653 // CHECK28-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
23654 // CHECK28-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
23655 // CHECK28-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
23656 // CHECK28-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
23657 // CHECK28-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
23658 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
23659 // CHECK28-NEXT:    ret void
23660 //
23661 //
23662 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3
23663 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
23664 // CHECK28-NEXT:  entry:
23665 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23666 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23667 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23668 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
23669 // CHECK28-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
23670 // CHECK28-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
23671 // CHECK28-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
23672 // CHECK28-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
23673 // CHECK28-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
23674 // CHECK28-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
23675 // CHECK28-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
23676 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
23677 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23678 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i8, align 1
23679 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23680 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23681 // CHECK28-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23682 // CHECK28-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23683 // CHECK28-NEXT:    [[IT:%.*]] = alloca i8, align 1
23684 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23685 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23686 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23687 // CHECK28-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
23688 // CHECK28-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
23689 // CHECK28-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
23690 // CHECK28-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
23691 // CHECK28-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
23692 // CHECK28-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
23693 // CHECK28-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
23694 // CHECK28-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
23695 // CHECK28-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
23696 // CHECK28-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
23697 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
23698 // CHECK28-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
23699 // CHECK28-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
23700 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
23701 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
23702 // CHECK28-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
23703 // CHECK28-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
23704 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23705 // CHECK28-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
23706 // CHECK28-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23707 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23708 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
23709 // CHECK28-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23710 // CHECK28-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
23711 // CHECK28-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
23712 // CHECK28-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
23713 // CHECK28:       omp.dispatch.cond:
23714 // CHECK28-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23715 // CHECK28-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
23716 // CHECK28-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23717 // CHECK28:       cond.true:
23718 // CHECK28-NEXT:    br label [[COND_END:%.*]]
23719 // CHECK28:       cond.false:
23720 // CHECK28-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23721 // CHECK28-NEXT:    br label [[COND_END]]
23722 // CHECK28:       cond.end:
23723 // CHECK28-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
23724 // CHECK28-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23725 // CHECK28-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23726 // CHECK28-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
23727 // CHECK28-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23728 // CHECK28-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23729 // CHECK28-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
23730 // CHECK28-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
23731 // CHECK28:       omp.dispatch.body:
23732 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23733 // CHECK28:       omp.inner.for.cond:
23734 // CHECK28-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23735 // CHECK28-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23736 // CHECK28-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
23737 // CHECK28-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23738 // CHECK28:       omp.inner.for.body:
23739 // CHECK28-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23740 // CHECK28-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
23741 // CHECK28-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
23742 // CHECK28-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
23743 // CHECK28-NEXT:    store i8 [[CONV]], i8* [[IT]], align 1
23744 // CHECK28-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
23745 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
23746 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
23747 // CHECK28-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
23748 // CHECK28-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
23749 // CHECK28-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
23750 // CHECK28-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
23751 // CHECK28-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
23752 // CHECK28-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4
23753 // CHECK28-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
23754 // CHECK28-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
23755 // CHECK28-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
23756 // CHECK28-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
23757 // CHECK28-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
23758 // CHECK28-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4
23759 // CHECK28-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
23760 // CHECK28-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
23761 // CHECK28-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
23762 // CHECK28-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
23763 // CHECK28-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8
23764 // CHECK28-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
23765 // CHECK28-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
23766 // CHECK28-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
23767 // CHECK28-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
23768 // CHECK28-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
23769 // CHECK28-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8
23770 // CHECK28-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
23771 // CHECK28-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4
23772 // CHECK28-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
23773 // CHECK28-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4
23774 // CHECK28-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
23775 // CHECK28-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
23776 // CHECK28-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
23777 // CHECK28-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
23778 // CHECK28-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
23779 // CHECK28-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4
23780 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23781 // CHECK28:       omp.body.continue:
23782 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23783 // CHECK28:       omp.inner.for.inc:
23784 // CHECK28-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23785 // CHECK28-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
23786 // CHECK28-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
23787 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]]
23788 // CHECK28:       omp.inner.for.end:
23789 // CHECK28-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
23790 // CHECK28:       omp.dispatch.inc:
23791 // CHECK28-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23792 // CHECK28-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
23793 // CHECK28-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
23794 // CHECK28-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
23795 // CHECK28-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23796 // CHECK28-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
23797 // CHECK28-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
23798 // CHECK28-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
23799 // CHECK28-NEXT:    br label [[OMP_DISPATCH_COND]]
23800 // CHECK28:       omp.dispatch.end:
23801 // CHECK28-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
23802 // CHECK28-NEXT:    ret void
23803 //
23804 //
23805 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
23806 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23807 // CHECK28-NEXT:  entry:
23808 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23809 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23810 // CHECK28-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
23811 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
23812 // CHECK28-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
23813 // CHECK28-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23814 // CHECK28-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
23815 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23816 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23817 // CHECK28-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
23818 // CHECK28-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
23819 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23820 // CHECK28-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
23821 // CHECK28-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
23822 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
23823 // CHECK28-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
23824 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
23825 // CHECK28-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
23826 // CHECK28-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
23827 // CHECK28-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
23828 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
23829 // CHECK28-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
23830 // CHECK28-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
23831 // CHECK28-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
23832 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
23833 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
23834 // CHECK28-NEXT:    ret void
23835 //
23836 //
23837 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4
23838 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23839 // CHECK28-NEXT:  entry:
23840 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23841 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23842 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23843 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23844 // CHECK28-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
23845 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
23846 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23847 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23848 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23849 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23850 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23851 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23852 // CHECK28-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
23853 // CHECK28-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
23854 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23855 // CHECK28-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
23856 // CHECK28-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
23857 // CHECK28-NEXT:    ret void
23858 //
23859 //
23860 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
23861 // CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
23862 // CHECK28-NEXT:  entry:
23863 // CHECK28-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
23864 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
23865 // CHECK28-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
23866 // CHECK28-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
23867 // CHECK28-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
23868 // CHECK28-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
23869 // CHECK28-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
23870 // CHECK28-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
23871 // CHECK28-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
23872 // CHECK28-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
23873 // CHECK28-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
23874 // CHECK28-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
23875 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
23876 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
23877 // CHECK28-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
23878 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
23879 // CHECK28-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
23880 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
23881 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
23882 // CHECK28-NEXT:    ret void
23883 //
23884 //
23885 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5
23886 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
23887 // CHECK28-NEXT:  entry:
23888 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23889 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23890 // CHECK28-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
23891 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
23892 // CHECK28-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
23893 // CHECK28-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
23894 // CHECK28-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
23895 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
23896 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i64, align 4
23897 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
23898 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
23899 // CHECK28-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
23900 // CHECK28-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23901 // CHECK28-NEXT:    [[IT:%.*]] = alloca i64, align 8
23902 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23903 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23904 // CHECK28-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
23905 // CHECK28-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
23906 // CHECK28-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
23907 // CHECK28-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
23908 // CHECK28-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
23909 // CHECK28-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
23910 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
23911 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
23912 // CHECK28-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
23913 // CHECK28-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
23914 // CHECK28-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
23915 // CHECK28-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
23916 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23917 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23918 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
23919 // CHECK28-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
23920 // CHECK28-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23921 // CHECK28-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
23922 // CHECK28-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23923 // CHECK28:       cond.true:
23924 // CHECK28-NEXT:    br label [[COND_END:%.*]]
23925 // CHECK28:       cond.false:
23926 // CHECK28-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23927 // CHECK28-NEXT:    br label [[COND_END]]
23928 // CHECK28:       cond.end:
23929 // CHECK28-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
23930 // CHECK28-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
23931 // CHECK28-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
23932 // CHECK28-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
23933 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23934 // CHECK28:       omp.inner.for.cond:
23935 // CHECK28-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
23936 // CHECK28-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23937 // CHECK28-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
23938 // CHECK28-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23939 // CHECK28:       omp.inner.for.body:
23940 // CHECK28-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
23941 // CHECK28-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
23942 // CHECK28-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
23943 // CHECK28-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
23944 // CHECK28-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
23945 // CHECK28-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
23946 // CHECK28-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
23947 // CHECK28-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
23948 // CHECK28-NEXT:    store double [[ADD]], double* [[A]], align 4
23949 // CHECK28-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
23950 // CHECK28-NEXT:    [[TMP13:%.*]] = load double, double* [[A4]], align 4
23951 // CHECK28-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
23952 // CHECK28-NEXT:    store double [[INC]], double* [[A4]], align 4
23953 // CHECK28-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
23954 // CHECK28-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
23955 // CHECK28-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
23956 // CHECK28-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
23957 // CHECK28-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
23958 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23959 // CHECK28:       omp.body.continue:
23960 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23961 // CHECK28:       omp.inner.for.inc:
23962 // CHECK28-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
23963 // CHECK28-NEXT:    [[ADD7:%.*]] = add i64 [[TMP15]], 1
23964 // CHECK28-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
23965 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]]
23966 // CHECK28:       omp.inner.for.end:
23967 // CHECK28-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23968 // CHECK28:       omp.loop.exit:
23969 // CHECK28-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
23970 // CHECK28-NEXT:    ret void
23971 //
23972 //
23973 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
23974 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23975 // CHECK28-NEXT:  entry:
23976 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23977 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23978 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
23979 // CHECK28-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
23980 // CHECK28-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23981 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23982 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23983 // CHECK28-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
23984 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23985 // CHECK28-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
23986 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
23987 // CHECK28-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
23988 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
23989 // CHECK28-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
23990 // CHECK28-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
23991 // CHECK28-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
23992 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
23993 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
23994 // CHECK28-NEXT:    ret void
23995 //
23996 //
23997 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6
23998 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23999 // CHECK28-NEXT:  entry:
24000 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24001 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24002 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24003 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24004 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
24005 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
24006 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i64, align 4
24007 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
24008 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
24009 // CHECK28-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
24010 // CHECK28-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
24011 // CHECK28-NEXT:    [[I:%.*]] = alloca i64, align 8
24012 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24013 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24014 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24015 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24016 // CHECK28-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
24017 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24018 // CHECK28-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
24019 // CHECK28-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
24020 // CHECK28-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
24021 // CHECK28-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
24022 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
24023 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24024 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
24025 // CHECK28-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
24026 // CHECK28-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
24027 // CHECK28-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
24028 // CHECK28-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
24029 // CHECK28:       cond.true:
24030 // CHECK28-NEXT:    br label [[COND_END:%.*]]
24031 // CHECK28:       cond.false:
24032 // CHECK28-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
24033 // CHECK28-NEXT:    br label [[COND_END]]
24034 // CHECK28:       cond.end:
24035 // CHECK28-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
24036 // CHECK28-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
24037 // CHECK28-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
24038 // CHECK28-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
24039 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24040 // CHECK28:       omp.inner.for.cond:
24041 // CHECK28-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
24042 // CHECK28-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
24043 // CHECK28-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
24044 // CHECK28-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24045 // CHECK28:       omp.inner.for.body:
24046 // CHECK28-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
24047 // CHECK28-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
24048 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
24049 // CHECK28-NEXT:    store i64 [[ADD]], i64* [[I]], align 8
24050 // CHECK28-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
24051 // CHECK28-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
24052 // CHECK28-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
24053 // CHECK28-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
24054 // CHECK28-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
24055 // CHECK28-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
24056 // CHECK28-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
24057 // CHECK28-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
24058 // CHECK28-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
24059 // CHECK28-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
24060 // CHECK28-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
24061 // CHECK28-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
24062 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24063 // CHECK28:       omp.body.continue:
24064 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24065 // CHECK28:       omp.inner.for.inc:
24066 // CHECK28-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
24067 // CHECK28-NEXT:    [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
24068 // CHECK28-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
24069 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]]
24070 // CHECK28:       omp.inner.for.end:
24071 // CHECK28-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
24072 // CHECK28:       omp.loop.exit:
24073 // CHECK28-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
24074 // CHECK28-NEXT:    ret void
24075 //
24076 //
24077 // CHECK29-LABEL: define {{[^@]+}}@_Z7get_valv
24078 // CHECK29-SAME: () #[[ATTR0:[0-9]+]] {
24079 // CHECK29-NEXT:  entry:
24080 // CHECK29-NEXT:    ret i64 0
24081 //
24082 //
24083 // CHECK29-LABEL: define {{[^@]+}}@_Z3fooi
24084 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
24085 // CHECK29-NEXT:  entry:
24086 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24087 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
24088 // CHECK29-NEXT:    [[AA:%.*]] = alloca i16, align 2
24089 // CHECK29-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
24090 // CHECK29-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
24091 // CHECK29-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
24092 // CHECK29-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
24093 // CHECK29-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
24094 // CHECK29-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
24095 // CHECK29-NEXT:    [[I:%.*]] = alloca i32, align 4
24096 // CHECK29-NEXT:    [[K:%.*]] = alloca i64, align 8
24097 // CHECK29-NEXT:    [[I2:%.*]] = alloca i32, align 4
24098 // CHECK29-NEXT:    [[LIN:%.*]] = alloca i32, align 4
24099 // CHECK29-NEXT:    [[IT:%.*]] = alloca i64, align 8
24100 // CHECK29-NEXT:    [[IT16:%.*]] = alloca i16, align 2
24101 // CHECK29-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
24102 // CHECK29-NEXT:    [[IT30:%.*]] = alloca i8, align 1
24103 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24104 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
24105 // CHECK29-NEXT:    store i16 0, i16* [[AA]], align 2
24106 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
24107 // CHECK29-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
24108 // CHECK29-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
24109 // CHECK29-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
24110 // CHECK29-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
24111 // CHECK29-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
24112 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
24113 // CHECK29-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
24114 // CHECK29-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
24115 // CHECK29-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
24116 // CHECK29-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
24117 // CHECK29-NEXT:    store i32 3, i32* [[I]], align 4
24118 // CHECK29-NEXT:    br label [[FOR_COND:%.*]]
24119 // CHECK29:       for.cond:
24120 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I]], align 4
24121 // CHECK29-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32
24122 // CHECK29-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
24123 // CHECK29:       for.body:
24124 // CHECK29-NEXT:    br label [[FOR_INC:%.*]]
24125 // CHECK29:       for.inc:
24126 // CHECK29-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
24127 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP7]], 5
24128 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
24129 // CHECK29-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
24130 // CHECK29:       for.end:
24131 // CHECK29-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
24132 // CHECK29-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
24133 // CHECK29-NEXT:    store i32 10, i32* [[I2]], align 4
24134 // CHECK29-NEXT:    br label [[FOR_COND3:%.*]]
24135 // CHECK29:       for.cond3:
24136 // CHECK29-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I2]], align 4
24137 // CHECK29-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1
24138 // CHECK29-NEXT:    br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]]
24139 // CHECK29:       for.body5:
24140 // CHECK29-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
24141 // CHECK29-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1
24142 // CHECK29-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
24143 // CHECK29-NEXT:    br label [[FOR_INC7:%.*]]
24144 // CHECK29:       for.inc7:
24145 // CHECK29-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I2]], align 4
24146 // CHECK29-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP10]], -1
24147 // CHECK29-NEXT:    store i32 [[DEC]], i32* [[I2]], align 4
24148 // CHECK29-NEXT:    br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]]
24149 // CHECK29:       for.end8:
24150 // CHECK29-NEXT:    store i32 12, i32* [[LIN]], align 4
24151 // CHECK29-NEXT:    store i64 2000, i64* [[IT]], align 8
24152 // CHECK29-NEXT:    br label [[FOR_COND9:%.*]]
24153 // CHECK29:       for.cond9:
24154 // CHECK29-NEXT:    [[TMP11:%.*]] = load i64, i64* [[IT]], align 8
24155 // CHECK29-NEXT:    [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600
24156 // CHECK29-NEXT:    br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]]
24157 // CHECK29:       for.body11:
24158 // CHECK29-NEXT:    [[TMP12:%.*]] = load i16, i16* [[AA]], align 2
24159 // CHECK29-NEXT:    [[CONV:%.*]] = sext i16 [[TMP12]] to i32
24160 // CHECK29-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV]], 1
24161 // CHECK29-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
24162 // CHECK29-NEXT:    store i16 [[CONV13]], i16* [[AA]], align 2
24163 // CHECK29-NEXT:    br label [[FOR_INC14:%.*]]
24164 // CHECK29:       for.inc14:
24165 // CHECK29-NEXT:    [[TMP13:%.*]] = load i64, i64* [[IT]], align 8
24166 // CHECK29-NEXT:    [[SUB:%.*]] = sub i64 [[TMP13]], 400
24167 // CHECK29-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
24168 // CHECK29-NEXT:    br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]]
24169 // CHECK29:       for.end15:
24170 // CHECK29-NEXT:    store i16 6, i16* [[IT16]], align 2
24171 // CHECK29-NEXT:    br label [[FOR_COND17:%.*]]
24172 // CHECK29:       for.cond17:
24173 // CHECK29-NEXT:    [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2
24174 // CHECK29-NEXT:    [[CONV18:%.*]] = sext i16 [[TMP14]] to i32
24175 // CHECK29-NEXT:    [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20
24176 // CHECK29-NEXT:    br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]]
24177 // CHECK29:       for.body20:
24178 // CHECK29-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
24179 // CHECK29-NEXT:    [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1
24180 // CHECK29-NEXT:    store i32 [[ADD21]], i32* [[A]], align 4
24181 // CHECK29-NEXT:    [[TMP16:%.*]] = load i16, i16* [[AA]], align 2
24182 // CHECK29-NEXT:    [[CONV22:%.*]] = sext i16 [[TMP16]] to i32
24183 // CHECK29-NEXT:    [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1
24184 // CHECK29-NEXT:    [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16
24185 // CHECK29-NEXT:    store i16 [[CONV24]], i16* [[AA]], align 2
24186 // CHECK29-NEXT:    br label [[FOR_INC25:%.*]]
24187 // CHECK29:       for.inc25:
24188 // CHECK29-NEXT:    [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2
24189 // CHECK29-NEXT:    [[CONV26:%.*]] = sext i16 [[TMP17]] to i32
24190 // CHECK29-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4
24191 // CHECK29-NEXT:    [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16
24192 // CHECK29-NEXT:    store i16 [[CONV28]], i16* [[IT16]], align 2
24193 // CHECK29-NEXT:    br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]]
24194 // CHECK29:       for.end29:
24195 // CHECK29-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
24196 // CHECK29-NEXT:    store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4
24197 // CHECK29-NEXT:    store i8 122, i8* [[IT30]], align 1
24198 // CHECK29-NEXT:    br label [[FOR_COND31:%.*]]
24199 // CHECK29:       for.cond31:
24200 // CHECK29-NEXT:    [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1
24201 // CHECK29-NEXT:    [[CONV32:%.*]] = zext i8 [[TMP19]] to i32
24202 // CHECK29-NEXT:    [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97
24203 // CHECK29-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]]
24204 // CHECK29:       for.body34:
24205 // CHECK29-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A]], align 4
24206 // CHECK29-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1
24207 // CHECK29-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
24208 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
24209 // CHECK29-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4
24210 // CHECK29-NEXT:    [[CONV36:%.*]] = fpext float [[TMP21]] to double
24211 // CHECK29-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
24212 // CHECK29-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
24213 // CHECK29-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
24214 // CHECK29-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
24215 // CHECK29-NEXT:    [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4
24216 // CHECK29-NEXT:    [[CONV40:%.*]] = fpext float [[TMP22]] to double
24217 // CHECK29-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
24218 // CHECK29-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
24219 // CHECK29-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
24220 // CHECK29-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
24221 // CHECK29-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2
24222 // CHECK29-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8
24223 // CHECK29-NEXT:    [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00
24224 // CHECK29-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
24225 // CHECK29-NEXT:    [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]]
24226 // CHECK29-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]]
24227 // CHECK29-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3
24228 // CHECK29-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8
24229 // CHECK29-NEXT:    [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00
24230 // CHECK29-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
24231 // CHECK29-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
24232 // CHECK29-NEXT:    [[TMP26:%.*]] = load i64, i64* [[X]], align 8
24233 // CHECK29-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1
24234 // CHECK29-NEXT:    store i64 [[ADD49]], i64* [[X]], align 8
24235 // CHECK29-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
24236 // CHECK29-NEXT:    [[TMP27:%.*]] = load i8, i8* [[Y]], align 8
24237 // CHECK29-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP27]] to i32
24238 // CHECK29-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
24239 // CHECK29-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
24240 // CHECK29-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 8
24241 // CHECK29-NEXT:    br label [[FOR_INC53:%.*]]
24242 // CHECK29:       for.inc53:
24243 // CHECK29-NEXT:    [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1
24244 // CHECK29-NEXT:    [[CONV54:%.*]] = zext i8 [[TMP28]] to i32
24245 // CHECK29-NEXT:    [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1
24246 // CHECK29-NEXT:    [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8
24247 // CHECK29-NEXT:    store i8 [[CONV56]], i8* [[IT30]], align 1
24248 // CHECK29-NEXT:    br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]]
24249 // CHECK29:       for.end57:
24250 // CHECK29-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
24251 // CHECK29-NEXT:    [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
24252 // CHECK29-NEXT:    call void @llvm.stackrestore(i8* [[TMP30]])
24253 // CHECK29-NEXT:    ret i32 [[TMP29]]
24254 //
24255 //
24256 // CHECK29-LABEL: define {{[^@]+}}@_Z3bari
24257 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
24258 // CHECK29-NEXT:  entry:
24259 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24260 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
24261 // CHECK29-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
24262 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24263 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
24264 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
24265 // CHECK29-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
24266 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
24267 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
24268 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
24269 // CHECK29-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
24270 // CHECK29-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
24271 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
24272 // CHECK29-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
24273 // CHECK29-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
24274 // CHECK29-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
24275 // CHECK29-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
24276 // CHECK29-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
24277 // CHECK29-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
24278 // CHECK29-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
24279 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
24280 // CHECK29-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
24281 // CHECK29-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
24282 // CHECK29-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
24283 // CHECK29-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
24284 // CHECK29-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
24285 // CHECK29-NEXT:    ret i32 [[TMP8]]
24286 //
24287 //
24288 // CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
24289 // CHECK29-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
24290 // CHECK29-NEXT:  entry:
24291 // CHECK29-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
24292 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24293 // CHECK29-NEXT:    [[B:%.*]] = alloca i32, align 4
24294 // CHECK29-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
24295 // CHECK29-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
24296 // CHECK29-NEXT:    [[IT:%.*]] = alloca i64, align 8
24297 // CHECK29-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
24298 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24299 // CHECK29-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
24300 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
24301 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
24302 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
24303 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
24304 // CHECK29-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
24305 // CHECK29-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
24306 // CHECK29-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
24307 // CHECK29-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
24308 // CHECK29-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
24309 // CHECK29-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
24310 // CHECK29-NEXT:    store i64 2000, i64* [[IT]], align 8
24311 // CHECK29-NEXT:    br label [[FOR_COND:%.*]]
24312 // CHECK29:       for.cond:
24313 // CHECK29-NEXT:    [[TMP5:%.*]] = load i64, i64* [[IT]], align 8
24314 // CHECK29-NEXT:    [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600
24315 // CHECK29-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
24316 // CHECK29:       for.body:
24317 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
24318 // CHECK29-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP6]] to double
24319 // CHECK29-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
24320 // CHECK29-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
24321 // CHECK29-NEXT:    store double [[ADD2]], double* [[A]], align 8
24322 // CHECK29-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
24323 // CHECK29-NEXT:    [[TMP7:%.*]] = load double, double* [[A3]], align 8
24324 // CHECK29-NEXT:    [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
24325 // CHECK29-NEXT:    store double [[INC]], double* [[A3]], align 8
24326 // CHECK29-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
24327 // CHECK29-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
24328 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
24329 // CHECK29-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
24330 // CHECK29-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
24331 // CHECK29-NEXT:    br label [[FOR_INC:%.*]]
24332 // CHECK29:       for.inc:
24333 // CHECK29-NEXT:    [[TMP9:%.*]] = load i64, i64* [[IT]], align 8
24334 // CHECK29-NEXT:    [[SUB:%.*]] = sub i64 [[TMP9]], 400
24335 // CHECK29-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
24336 // CHECK29-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
24337 // CHECK29:       for.end:
24338 // CHECK29-NEXT:    [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
24339 // CHECK29-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]]
24340 // CHECK29-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
24341 // CHECK29-NEXT:    [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
24342 // CHECK29-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP11]] to i32
24343 // CHECK29-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B]], align 4
24344 // CHECK29-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]]
24345 // CHECK29-NEXT:    [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
24346 // CHECK29-NEXT:    call void @llvm.stackrestore(i8* [[TMP13]])
24347 // CHECK29-NEXT:    ret i32 [[ADD9]]
24348 //
24349 //
24350 // CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici
24351 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
24352 // CHECK29-NEXT:  entry:
24353 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24354 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
24355 // CHECK29-NEXT:    [[AA:%.*]] = alloca i16, align 2
24356 // CHECK29-NEXT:    [[AAA:%.*]] = alloca i8, align 1
24357 // CHECK29-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
24358 // CHECK29-NEXT:    [[I:%.*]] = alloca i32, align 4
24359 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24360 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
24361 // CHECK29-NEXT:    store i16 0, i16* [[AA]], align 2
24362 // CHECK29-NEXT:    store i8 0, i8* [[AAA]], align 1
24363 // CHECK29-NEXT:    store i32 100, i32* [[I]], align 4
24364 // CHECK29-NEXT:    br label [[FOR_COND:%.*]]
24365 // CHECK29:       for.cond:
24366 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
24367 // CHECK29-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10
24368 // CHECK29-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
24369 // CHECK29:       for.body:
24370 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
24371 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
24372 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
24373 // CHECK29-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
24374 // CHECK29-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
24375 // CHECK29-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
24376 // CHECK29-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
24377 // CHECK29-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
24378 // CHECK29-NEXT:    [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1
24379 // CHECK29-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
24380 // CHECK29-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
24381 // CHECK29-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
24382 // CHECK29-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
24383 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
24384 // CHECK29-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
24385 // CHECK29-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
24386 // CHECK29-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
24387 // CHECK29-NEXT:    br label [[FOR_INC:%.*]]
24388 // CHECK29:       for.inc:
24389 // CHECK29-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
24390 // CHECK29-NEXT:    [[ADD7:%.*]] = add i32 [[TMP5]], 10
24391 // CHECK29-NEXT:    store i32 [[ADD7]], i32* [[I]], align 4
24392 // CHECK29-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
24393 // CHECK29:       for.end:
24394 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
24395 // CHECK29-NEXT:    ret i32 [[TMP6]]
24396 //
24397 //
24398 // CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
24399 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
24400 // CHECK29-NEXT:  entry:
24401 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24402 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
24403 // CHECK29-NEXT:    [[AA:%.*]] = alloca i16, align 2
24404 // CHECK29-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
24405 // CHECK29-NEXT:    [[I:%.*]] = alloca i64, align 8
24406 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24407 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
24408 // CHECK29-NEXT:    store i16 0, i16* [[AA]], align 2
24409 // CHECK29-NEXT:    store i64 -10, i64* [[I]], align 8
24410 // CHECK29-NEXT:    br label [[FOR_COND:%.*]]
24411 // CHECK29:       for.cond:
24412 // CHECK29-NEXT:    [[TMP0:%.*]] = load i64, i64* [[I]], align 8
24413 // CHECK29-NEXT:    [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10
24414 // CHECK29-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
24415 // CHECK29:       for.body:
24416 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
24417 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
24418 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
24419 // CHECK29-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
24420 // CHECK29-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
24421 // CHECK29-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
24422 // CHECK29-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
24423 // CHECK29-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
24424 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
24425 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
24426 // CHECK29-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
24427 // CHECK29-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
24428 // CHECK29-NEXT:    br label [[FOR_INC:%.*]]
24429 // CHECK29:       for.inc:
24430 // CHECK29-NEXT:    [[TMP4:%.*]] = load i64, i64* [[I]], align 8
24431 // CHECK29-NEXT:    [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3
24432 // CHECK29-NEXT:    store i64 [[ADD4]], i64* [[I]], align 8
24433 // CHECK29-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
24434 // CHECK29:       for.end:
24435 // CHECK29-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
24436 // CHECK29-NEXT:    ret i32 [[TMP5]]
24437 //
24438 //
24439 // CHECK30-LABEL: define {{[^@]+}}@_Z7get_valv
24440 // CHECK30-SAME: () #[[ATTR0:[0-9]+]] {
24441 // CHECK30-NEXT:  entry:
24442 // CHECK30-NEXT:    ret i64 0
24443 //
24444 //
24445 // CHECK30-LABEL: define {{[^@]+}}@_Z3fooi
24446 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
24447 // CHECK30-NEXT:  entry:
24448 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24449 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
24450 // CHECK30-NEXT:    [[AA:%.*]] = alloca i16, align 2
24451 // CHECK30-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
24452 // CHECK30-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
24453 // CHECK30-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
24454 // CHECK30-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
24455 // CHECK30-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
24456 // CHECK30-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
24457 // CHECK30-NEXT:    [[I:%.*]] = alloca i32, align 4
24458 // CHECK30-NEXT:    [[K:%.*]] = alloca i64, align 8
24459 // CHECK30-NEXT:    [[I2:%.*]] = alloca i32, align 4
24460 // CHECK30-NEXT:    [[LIN:%.*]] = alloca i32, align 4
24461 // CHECK30-NEXT:    [[IT:%.*]] = alloca i64, align 8
24462 // CHECK30-NEXT:    [[IT16:%.*]] = alloca i16, align 2
24463 // CHECK30-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
24464 // CHECK30-NEXT:    [[IT30:%.*]] = alloca i8, align 1
24465 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24466 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
24467 // CHECK30-NEXT:    store i16 0, i16* [[AA]], align 2
24468 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
24469 // CHECK30-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
24470 // CHECK30-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
24471 // CHECK30-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
24472 // CHECK30-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
24473 // CHECK30-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
24474 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
24475 // CHECK30-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
24476 // CHECK30-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
24477 // CHECK30-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
24478 // CHECK30-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
24479 // CHECK30-NEXT:    store i32 3, i32* [[I]], align 4
24480 // CHECK30-NEXT:    br label [[FOR_COND:%.*]]
24481 // CHECK30:       for.cond:
24482 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I]], align 4
24483 // CHECK30-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32
24484 // CHECK30-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
24485 // CHECK30:       for.body:
24486 // CHECK30-NEXT:    br label [[FOR_INC:%.*]]
24487 // CHECK30:       for.inc:
24488 // CHECK30-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
24489 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP7]], 5
24490 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
24491 // CHECK30-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
24492 // CHECK30:       for.end:
24493 // CHECK30-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
24494 // CHECK30-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
24495 // CHECK30-NEXT:    store i32 10, i32* [[I2]], align 4
24496 // CHECK30-NEXT:    br label [[FOR_COND3:%.*]]
24497 // CHECK30:       for.cond3:
24498 // CHECK30-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I2]], align 4
24499 // CHECK30-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1
24500 // CHECK30-NEXT:    br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]]
24501 // CHECK30:       for.body5:
24502 // CHECK30-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
24503 // CHECK30-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1
24504 // CHECK30-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
24505 // CHECK30-NEXT:    br label [[FOR_INC7:%.*]]
24506 // CHECK30:       for.inc7:
24507 // CHECK30-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I2]], align 4
24508 // CHECK30-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP10]], -1
24509 // CHECK30-NEXT:    store i32 [[DEC]], i32* [[I2]], align 4
24510 // CHECK30-NEXT:    br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]]
24511 // CHECK30:       for.end8:
24512 // CHECK30-NEXT:    store i32 12, i32* [[LIN]], align 4
24513 // CHECK30-NEXT:    store i64 2000, i64* [[IT]], align 8
24514 // CHECK30-NEXT:    br label [[FOR_COND9:%.*]]
24515 // CHECK30:       for.cond9:
24516 // CHECK30-NEXT:    [[TMP11:%.*]] = load i64, i64* [[IT]], align 8
24517 // CHECK30-NEXT:    [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600
24518 // CHECK30-NEXT:    br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]]
24519 // CHECK30:       for.body11:
24520 // CHECK30-NEXT:    [[TMP12:%.*]] = load i16, i16* [[AA]], align 2
24521 // CHECK30-NEXT:    [[CONV:%.*]] = sext i16 [[TMP12]] to i32
24522 // CHECK30-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV]], 1
24523 // CHECK30-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
24524 // CHECK30-NEXT:    store i16 [[CONV13]], i16* [[AA]], align 2
24525 // CHECK30-NEXT:    br label [[FOR_INC14:%.*]]
24526 // CHECK30:       for.inc14:
24527 // CHECK30-NEXT:    [[TMP13:%.*]] = load i64, i64* [[IT]], align 8
24528 // CHECK30-NEXT:    [[SUB:%.*]] = sub i64 [[TMP13]], 400
24529 // CHECK30-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
24530 // CHECK30-NEXT:    br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]]
24531 // CHECK30:       for.end15:
24532 // CHECK30-NEXT:    store i16 6, i16* [[IT16]], align 2
24533 // CHECK30-NEXT:    br label [[FOR_COND17:%.*]]
24534 // CHECK30:       for.cond17:
24535 // CHECK30-NEXT:    [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2
24536 // CHECK30-NEXT:    [[CONV18:%.*]] = sext i16 [[TMP14]] to i32
24537 // CHECK30-NEXT:    [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20
24538 // CHECK30-NEXT:    br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]]
24539 // CHECK30:       for.body20:
24540 // CHECK30-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
24541 // CHECK30-NEXT:    [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1
24542 // CHECK30-NEXT:    store i32 [[ADD21]], i32* [[A]], align 4
24543 // CHECK30-NEXT:    [[TMP16:%.*]] = load i16, i16* [[AA]], align 2
24544 // CHECK30-NEXT:    [[CONV22:%.*]] = sext i16 [[TMP16]] to i32
24545 // CHECK30-NEXT:    [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1
24546 // CHECK30-NEXT:    [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16
24547 // CHECK30-NEXT:    store i16 [[CONV24]], i16* [[AA]], align 2
24548 // CHECK30-NEXT:    br label [[FOR_INC25:%.*]]
24549 // CHECK30:       for.inc25:
24550 // CHECK30-NEXT:    [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2
24551 // CHECK30-NEXT:    [[CONV26:%.*]] = sext i16 [[TMP17]] to i32
24552 // CHECK30-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4
24553 // CHECK30-NEXT:    [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16
24554 // CHECK30-NEXT:    store i16 [[CONV28]], i16* [[IT16]], align 2
24555 // CHECK30-NEXT:    br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]]
24556 // CHECK30:       for.end29:
24557 // CHECK30-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
24558 // CHECK30-NEXT:    store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4
24559 // CHECK30-NEXT:    store i8 122, i8* [[IT30]], align 1
24560 // CHECK30-NEXT:    br label [[FOR_COND31:%.*]]
24561 // CHECK30:       for.cond31:
24562 // CHECK30-NEXT:    [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1
24563 // CHECK30-NEXT:    [[CONV32:%.*]] = zext i8 [[TMP19]] to i32
24564 // CHECK30-NEXT:    [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97
24565 // CHECK30-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]]
24566 // CHECK30:       for.body34:
24567 // CHECK30-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A]], align 4
24568 // CHECK30-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1
24569 // CHECK30-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
24570 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
24571 // CHECK30-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4
24572 // CHECK30-NEXT:    [[CONV36:%.*]] = fpext float [[TMP21]] to double
24573 // CHECK30-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
24574 // CHECK30-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
24575 // CHECK30-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
24576 // CHECK30-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
24577 // CHECK30-NEXT:    [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4
24578 // CHECK30-NEXT:    [[CONV40:%.*]] = fpext float [[TMP22]] to double
24579 // CHECK30-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
24580 // CHECK30-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
24581 // CHECK30-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
24582 // CHECK30-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
24583 // CHECK30-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2
24584 // CHECK30-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8
24585 // CHECK30-NEXT:    [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00
24586 // CHECK30-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
24587 // CHECK30-NEXT:    [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]]
24588 // CHECK30-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]]
24589 // CHECK30-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3
24590 // CHECK30-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8
24591 // CHECK30-NEXT:    [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00
24592 // CHECK30-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
24593 // CHECK30-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
24594 // CHECK30-NEXT:    [[TMP26:%.*]] = load i64, i64* [[X]], align 8
24595 // CHECK30-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1
24596 // CHECK30-NEXT:    store i64 [[ADD49]], i64* [[X]], align 8
24597 // CHECK30-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
24598 // CHECK30-NEXT:    [[TMP27:%.*]] = load i8, i8* [[Y]], align 8
24599 // CHECK30-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP27]] to i32
24600 // CHECK30-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
24601 // CHECK30-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
24602 // CHECK30-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 8
24603 // CHECK30-NEXT:    br label [[FOR_INC53:%.*]]
24604 // CHECK30:       for.inc53:
24605 // CHECK30-NEXT:    [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1
24606 // CHECK30-NEXT:    [[CONV54:%.*]] = zext i8 [[TMP28]] to i32
24607 // CHECK30-NEXT:    [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1
24608 // CHECK30-NEXT:    [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8
24609 // CHECK30-NEXT:    store i8 [[CONV56]], i8* [[IT30]], align 1
24610 // CHECK30-NEXT:    br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]]
24611 // CHECK30:       for.end57:
24612 // CHECK30-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
24613 // CHECK30-NEXT:    [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
24614 // CHECK30-NEXT:    call void @llvm.stackrestore(i8* [[TMP30]])
24615 // CHECK30-NEXT:    ret i32 [[TMP29]]
24616 //
24617 //
24618 // CHECK30-LABEL: define {{[^@]+}}@_Z3bari
24619 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
24620 // CHECK30-NEXT:  entry:
24621 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24622 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
24623 // CHECK30-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
24624 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24625 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
24626 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
24627 // CHECK30-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
24628 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
24629 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
24630 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
24631 // CHECK30-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
24632 // CHECK30-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
24633 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
24634 // CHECK30-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
24635 // CHECK30-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
24636 // CHECK30-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
24637 // CHECK30-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
24638 // CHECK30-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
24639 // CHECK30-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
24640 // CHECK30-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
24641 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
24642 // CHECK30-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
24643 // CHECK30-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
24644 // CHECK30-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
24645 // CHECK30-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
24646 // CHECK30-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
24647 // CHECK30-NEXT:    ret i32 [[TMP8]]
24648 //
24649 //
24650 // CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
24651 // CHECK30-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
24652 // CHECK30-NEXT:  entry:
24653 // CHECK30-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
24654 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24655 // CHECK30-NEXT:    [[B:%.*]] = alloca i32, align 4
24656 // CHECK30-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
24657 // CHECK30-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
24658 // CHECK30-NEXT:    [[IT:%.*]] = alloca i64, align 8
24659 // CHECK30-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
24660 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24661 // CHECK30-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
24662 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
24663 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
24664 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
24665 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
24666 // CHECK30-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
24667 // CHECK30-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
24668 // CHECK30-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
24669 // CHECK30-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
24670 // CHECK30-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
24671 // CHECK30-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
24672 // CHECK30-NEXT:    store i64 2000, i64* [[IT]], align 8
24673 // CHECK30-NEXT:    br label [[FOR_COND:%.*]]
24674 // CHECK30:       for.cond:
24675 // CHECK30-NEXT:    [[TMP5:%.*]] = load i64, i64* [[IT]], align 8
24676 // CHECK30-NEXT:    [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600
24677 // CHECK30-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
24678 // CHECK30:       for.body:
24679 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
24680 // CHECK30-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP6]] to double
24681 // CHECK30-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
24682 // CHECK30-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
24683 // CHECK30-NEXT:    store double [[ADD2]], double* [[A]], align 8
24684 // CHECK30-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
24685 // CHECK30-NEXT:    [[TMP7:%.*]] = load double, double* [[A3]], align 8
24686 // CHECK30-NEXT:    [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
24687 // CHECK30-NEXT:    store double [[INC]], double* [[A3]], align 8
24688 // CHECK30-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
24689 // CHECK30-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
24690 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
24691 // CHECK30-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
24692 // CHECK30-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
24693 // CHECK30-NEXT:    br label [[FOR_INC:%.*]]
24694 // CHECK30:       for.inc:
24695 // CHECK30-NEXT:    [[TMP9:%.*]] = load i64, i64* [[IT]], align 8
24696 // CHECK30-NEXT:    [[SUB:%.*]] = sub i64 [[TMP9]], 400
24697 // CHECK30-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
24698 // CHECK30-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
24699 // CHECK30:       for.end:
24700 // CHECK30-NEXT:    [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
24701 // CHECK30-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]]
24702 // CHECK30-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
24703 // CHECK30-NEXT:    [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
24704 // CHECK30-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP11]] to i32
24705 // CHECK30-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B]], align 4
24706 // CHECK30-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]]
24707 // CHECK30-NEXT:    [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
24708 // CHECK30-NEXT:    call void @llvm.stackrestore(i8* [[TMP13]])
24709 // CHECK30-NEXT:    ret i32 [[ADD9]]
24710 //
24711 //
24712 // CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici
24713 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
24714 // CHECK30-NEXT:  entry:
24715 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24716 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
24717 // CHECK30-NEXT:    [[AA:%.*]] = alloca i16, align 2
24718 // CHECK30-NEXT:    [[AAA:%.*]] = alloca i8, align 1
24719 // CHECK30-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
24720 // CHECK30-NEXT:    [[I:%.*]] = alloca i32, align 4
24721 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24722 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
24723 // CHECK30-NEXT:    store i16 0, i16* [[AA]], align 2
24724 // CHECK30-NEXT:    store i8 0, i8* [[AAA]], align 1
24725 // CHECK30-NEXT:    store i32 100, i32* [[I]], align 4
24726 // CHECK30-NEXT:    br label [[FOR_COND:%.*]]
24727 // CHECK30:       for.cond:
24728 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
24729 // CHECK30-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10
24730 // CHECK30-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
24731 // CHECK30:       for.body:
24732 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
24733 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
24734 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
24735 // CHECK30-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
24736 // CHECK30-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
24737 // CHECK30-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
24738 // CHECK30-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
24739 // CHECK30-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
24740 // CHECK30-NEXT:    [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1
24741 // CHECK30-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
24742 // CHECK30-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
24743 // CHECK30-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
24744 // CHECK30-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
24745 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
24746 // CHECK30-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
24747 // CHECK30-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
24748 // CHECK30-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
24749 // CHECK30-NEXT:    br label [[FOR_INC:%.*]]
24750 // CHECK30:       for.inc:
24751 // CHECK30-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
24752 // CHECK30-NEXT:    [[ADD7:%.*]] = add i32 [[TMP5]], 10
24753 // CHECK30-NEXT:    store i32 [[ADD7]], i32* [[I]], align 4
24754 // CHECK30-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
24755 // CHECK30:       for.end:
24756 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
24757 // CHECK30-NEXT:    ret i32 [[TMP6]]
24758 //
24759 //
24760 // CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
24761 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
24762 // CHECK30-NEXT:  entry:
24763 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24764 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
24765 // CHECK30-NEXT:    [[AA:%.*]] = alloca i16, align 2
24766 // CHECK30-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
24767 // CHECK30-NEXT:    [[I:%.*]] = alloca i64, align 8
24768 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24769 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
24770 // CHECK30-NEXT:    store i16 0, i16* [[AA]], align 2
24771 // CHECK30-NEXT:    store i64 -10, i64* [[I]], align 8
24772 // CHECK30-NEXT:    br label [[FOR_COND:%.*]]
24773 // CHECK30:       for.cond:
24774 // CHECK30-NEXT:    [[TMP0:%.*]] = load i64, i64* [[I]], align 8
24775 // CHECK30-NEXT:    [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10
24776 // CHECK30-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
24777 // CHECK30:       for.body:
24778 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
24779 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
24780 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
24781 // CHECK30-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
24782 // CHECK30-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
24783 // CHECK30-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
24784 // CHECK30-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
24785 // CHECK30-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
24786 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
24787 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
24788 // CHECK30-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
24789 // CHECK30-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
24790 // CHECK30-NEXT:    br label [[FOR_INC:%.*]]
24791 // CHECK30:       for.inc:
24792 // CHECK30-NEXT:    [[TMP4:%.*]] = load i64, i64* [[I]], align 8
24793 // CHECK30-NEXT:    [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3
24794 // CHECK30-NEXT:    store i64 [[ADD4]], i64* [[I]], align 8
24795 // CHECK30-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
24796 // CHECK30:       for.end:
24797 // CHECK30-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
24798 // CHECK30-NEXT:    ret i32 [[TMP5]]
24799 //
24800 //
24801 // CHECK31-LABEL: define {{[^@]+}}@_Z7get_valv
24802 // CHECK31-SAME: () #[[ATTR0:[0-9]+]] {
24803 // CHECK31-NEXT:  entry:
24804 // CHECK31-NEXT:    ret i64 0
24805 //
24806 //
24807 // CHECK31-LABEL: define {{[^@]+}}@_Z3fooi
24808 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
24809 // CHECK31-NEXT:  entry:
24810 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24811 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
24812 // CHECK31-NEXT:    [[AA:%.*]] = alloca i16, align 2
24813 // CHECK31-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
24814 // CHECK31-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
24815 // CHECK31-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
24816 // CHECK31-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
24817 // CHECK31-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
24818 // CHECK31-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
24819 // CHECK31-NEXT:    [[I:%.*]] = alloca i32, align 4
24820 // CHECK31-NEXT:    [[K:%.*]] = alloca i64, align 8
24821 // CHECK31-NEXT:    [[I2:%.*]] = alloca i32, align 4
24822 // CHECK31-NEXT:    [[LIN:%.*]] = alloca i32, align 4
24823 // CHECK31-NEXT:    [[IT:%.*]] = alloca i64, align 8
24824 // CHECK31-NEXT:    [[IT16:%.*]] = alloca i16, align 2
24825 // CHECK31-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
24826 // CHECK31-NEXT:    [[IT30:%.*]] = alloca i8, align 1
24827 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24828 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
24829 // CHECK31-NEXT:    store i16 0, i16* [[AA]], align 2
24830 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
24831 // CHECK31-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
24832 // CHECK31-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
24833 // CHECK31-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
24834 // CHECK31-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
24835 // CHECK31-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
24836 // CHECK31-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
24837 // CHECK31-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
24838 // CHECK31-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
24839 // CHECK31-NEXT:    store i32 3, i32* [[I]], align 4
24840 // CHECK31-NEXT:    br label [[FOR_COND:%.*]]
24841 // CHECK31:       for.cond:
24842 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
24843 // CHECK31-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32
24844 // CHECK31-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
24845 // CHECK31:       for.body:
24846 // CHECK31-NEXT:    br label [[FOR_INC:%.*]]
24847 // CHECK31:       for.inc:
24848 // CHECK31-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
24849 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP5]], 5
24850 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
24851 // CHECK31-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
24852 // CHECK31:       for.end:
24853 // CHECK31-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
24854 // CHECK31-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
24855 // CHECK31-NEXT:    store i32 10, i32* [[I2]], align 4
24856 // CHECK31-NEXT:    br label [[FOR_COND3:%.*]]
24857 // CHECK31:       for.cond3:
24858 // CHECK31-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I2]], align 4
24859 // CHECK31-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1
24860 // CHECK31-NEXT:    br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]]
24861 // CHECK31:       for.body5:
24862 // CHECK31-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
24863 // CHECK31-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1
24864 // CHECK31-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
24865 // CHECK31-NEXT:    br label [[FOR_INC7:%.*]]
24866 // CHECK31:       for.inc7:
24867 // CHECK31-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I2]], align 4
24868 // CHECK31-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP8]], -1
24869 // CHECK31-NEXT:    store i32 [[DEC]], i32* [[I2]], align 4
24870 // CHECK31-NEXT:    br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]]
24871 // CHECK31:       for.end8:
24872 // CHECK31-NEXT:    store i32 12, i32* [[LIN]], align 4
24873 // CHECK31-NEXT:    store i64 2000, i64* [[IT]], align 8
24874 // CHECK31-NEXT:    br label [[FOR_COND9:%.*]]
24875 // CHECK31:       for.cond9:
24876 // CHECK31-NEXT:    [[TMP9:%.*]] = load i64, i64* [[IT]], align 8
24877 // CHECK31-NEXT:    [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600
24878 // CHECK31-NEXT:    br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]]
24879 // CHECK31:       for.body11:
24880 // CHECK31-NEXT:    [[TMP10:%.*]] = load i16, i16* [[AA]], align 2
24881 // CHECK31-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
24882 // CHECK31-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV]], 1
24883 // CHECK31-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
24884 // CHECK31-NEXT:    store i16 [[CONV13]], i16* [[AA]], align 2
24885 // CHECK31-NEXT:    br label [[FOR_INC14:%.*]]
24886 // CHECK31:       for.inc14:
24887 // CHECK31-NEXT:    [[TMP11:%.*]] = load i64, i64* [[IT]], align 8
24888 // CHECK31-NEXT:    [[SUB:%.*]] = sub i64 [[TMP11]], 400
24889 // CHECK31-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
24890 // CHECK31-NEXT:    br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]]
24891 // CHECK31:       for.end15:
24892 // CHECK31-NEXT:    store i16 6, i16* [[IT16]], align 2
24893 // CHECK31-NEXT:    br label [[FOR_COND17:%.*]]
24894 // CHECK31:       for.cond17:
24895 // CHECK31-NEXT:    [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2
24896 // CHECK31-NEXT:    [[CONV18:%.*]] = sext i16 [[TMP12]] to i32
24897 // CHECK31-NEXT:    [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20
24898 // CHECK31-NEXT:    br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]]
24899 // CHECK31:       for.body20:
24900 // CHECK31-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4
24901 // CHECK31-NEXT:    [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1
24902 // CHECK31-NEXT:    store i32 [[ADD21]], i32* [[A]], align 4
24903 // CHECK31-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2
24904 // CHECK31-NEXT:    [[CONV22:%.*]] = sext i16 [[TMP14]] to i32
24905 // CHECK31-NEXT:    [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1
24906 // CHECK31-NEXT:    [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16
24907 // CHECK31-NEXT:    store i16 [[CONV24]], i16* [[AA]], align 2
24908 // CHECK31-NEXT:    br label [[FOR_INC25:%.*]]
24909 // CHECK31:       for.inc25:
24910 // CHECK31-NEXT:    [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2
24911 // CHECK31-NEXT:    [[CONV26:%.*]] = sext i16 [[TMP15]] to i32
24912 // CHECK31-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4
24913 // CHECK31-NEXT:    [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16
24914 // CHECK31-NEXT:    store i16 [[CONV28]], i16* [[IT16]], align 2
24915 // CHECK31-NEXT:    br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]]
24916 // CHECK31:       for.end29:
24917 // CHECK31-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4
24918 // CHECK31-NEXT:    store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4
24919 // CHECK31-NEXT:    store i8 122, i8* [[IT30]], align 1
24920 // CHECK31-NEXT:    br label [[FOR_COND31:%.*]]
24921 // CHECK31:       for.cond31:
24922 // CHECK31-NEXT:    [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1
24923 // CHECK31-NEXT:    [[CONV32:%.*]] = zext i8 [[TMP17]] to i32
24924 // CHECK31-NEXT:    [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97
24925 // CHECK31-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]]
24926 // CHECK31:       for.body34:
24927 // CHECK31-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
24928 // CHECK31-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1
24929 // CHECK31-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
24930 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
24931 // CHECK31-NEXT:    [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4
24932 // CHECK31-NEXT:    [[CONV36:%.*]] = fpext float [[TMP19]] to double
24933 // CHECK31-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
24934 // CHECK31-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
24935 // CHECK31-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
24936 // CHECK31-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
24937 // CHECK31-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4
24938 // CHECK31-NEXT:    [[CONV40:%.*]] = fpext float [[TMP20]] to double
24939 // CHECK31-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
24940 // CHECK31-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
24941 // CHECK31-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
24942 // CHECK31-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
24943 // CHECK31-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2
24944 // CHECK31-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8
24945 // CHECK31-NEXT:    [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00
24946 // CHECK31-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
24947 // CHECK31-NEXT:    [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]]
24948 // CHECK31-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]]
24949 // CHECK31-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3
24950 // CHECK31-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8
24951 // CHECK31-NEXT:    [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00
24952 // CHECK31-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
24953 // CHECK31-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
24954 // CHECK31-NEXT:    [[TMP24:%.*]] = load i64, i64* [[X]], align 4
24955 // CHECK31-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1
24956 // CHECK31-NEXT:    store i64 [[ADD49]], i64* [[X]], align 4
24957 // CHECK31-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
24958 // CHECK31-NEXT:    [[TMP25:%.*]] = load i8, i8* [[Y]], align 4
24959 // CHECK31-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP25]] to i32
24960 // CHECK31-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
24961 // CHECK31-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
24962 // CHECK31-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 4
24963 // CHECK31-NEXT:    br label [[FOR_INC53:%.*]]
24964 // CHECK31:       for.inc53:
24965 // CHECK31-NEXT:    [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1
24966 // CHECK31-NEXT:    [[CONV54:%.*]] = zext i8 [[TMP26]] to i32
24967 // CHECK31-NEXT:    [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1
24968 // CHECK31-NEXT:    [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8
24969 // CHECK31-NEXT:    store i8 [[CONV56]], i8* [[IT30]], align 1
24970 // CHECK31-NEXT:    br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]]
24971 // CHECK31:       for.end57:
24972 // CHECK31-NEXT:    [[TMP27:%.*]] = load i32, i32* [[A]], align 4
24973 // CHECK31-NEXT:    [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
24974 // CHECK31-NEXT:    call void @llvm.stackrestore(i8* [[TMP28]])
24975 // CHECK31-NEXT:    ret i32 [[TMP27]]
24976 //
24977 //
24978 // CHECK31-LABEL: define {{[^@]+}}@_Z3bari
24979 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
24980 // CHECK31-NEXT:  entry:
24981 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24982 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
24983 // CHECK31-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
24984 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24985 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
24986 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
24987 // CHECK31-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
24988 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
24989 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
24990 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
24991 // CHECK31-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
24992 // CHECK31-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
24993 // CHECK31-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
24994 // CHECK31-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
24995 // CHECK31-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
24996 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
24997 // CHECK31-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
24998 // CHECK31-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
24999 // CHECK31-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
25000 // CHECK31-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
25001 // CHECK31-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
25002 // CHECK31-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
25003 // CHECK31-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
25004 // CHECK31-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
25005 // CHECK31-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
25006 // CHECK31-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
25007 // CHECK31-NEXT:    ret i32 [[TMP8]]
25008 //
25009 //
25010 // CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
25011 // CHECK31-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
25012 // CHECK31-NEXT:  entry:
25013 // CHECK31-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
25014 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25015 // CHECK31-NEXT:    [[B:%.*]] = alloca i32, align 4
25016 // CHECK31-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
25017 // CHECK31-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
25018 // CHECK31-NEXT:    [[IT:%.*]] = alloca i64, align 8
25019 // CHECK31-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
25020 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25021 // CHECK31-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
25022 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25023 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
25024 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
25025 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
25026 // CHECK31-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
25027 // CHECK31-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
25028 // CHECK31-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
25029 // CHECK31-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
25030 // CHECK31-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
25031 // CHECK31-NEXT:    store i64 2000, i64* [[IT]], align 8
25032 // CHECK31-NEXT:    br label [[FOR_COND:%.*]]
25033 // CHECK31:       for.cond:
25034 // CHECK31-NEXT:    [[TMP4:%.*]] = load i64, i64* [[IT]], align 8
25035 // CHECK31-NEXT:    [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600
25036 // CHECK31-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25037 // CHECK31:       for.body:
25038 // CHECK31-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
25039 // CHECK31-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
25040 // CHECK31-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
25041 // CHECK31-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
25042 // CHECK31-NEXT:    store double [[ADD2]], double* [[A]], align 4
25043 // CHECK31-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
25044 // CHECK31-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 4
25045 // CHECK31-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
25046 // CHECK31-NEXT:    store double [[INC]], double* [[A3]], align 4
25047 // CHECK31-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
25048 // CHECK31-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
25049 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
25050 // CHECK31-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
25051 // CHECK31-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
25052 // CHECK31-NEXT:    br label [[FOR_INC:%.*]]
25053 // CHECK31:       for.inc:
25054 // CHECK31-NEXT:    [[TMP8:%.*]] = load i64, i64* [[IT]], align 8
25055 // CHECK31-NEXT:    [[SUB:%.*]] = sub i64 [[TMP8]], 400
25056 // CHECK31-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
25057 // CHECK31-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
25058 // CHECK31:       for.end:
25059 // CHECK31-NEXT:    [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]]
25060 // CHECK31-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]]
25061 // CHECK31-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
25062 // CHECK31-NEXT:    [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
25063 // CHECK31-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP10]] to i32
25064 // CHECK31-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4
25065 // CHECK31-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]]
25066 // CHECK31-NEXT:    [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
25067 // CHECK31-NEXT:    call void @llvm.stackrestore(i8* [[TMP12]])
25068 // CHECK31-NEXT:    ret i32 [[ADD9]]
25069 //
25070 //
25071 // CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici
25072 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
25073 // CHECK31-NEXT:  entry:
25074 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25075 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
25076 // CHECK31-NEXT:    [[AA:%.*]] = alloca i16, align 2
25077 // CHECK31-NEXT:    [[AAA:%.*]] = alloca i8, align 1
25078 // CHECK31-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
25079 // CHECK31-NEXT:    [[I:%.*]] = alloca i32, align 4
25080 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25081 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
25082 // CHECK31-NEXT:    store i16 0, i16* [[AA]], align 2
25083 // CHECK31-NEXT:    store i8 0, i8* [[AAA]], align 1
25084 // CHECK31-NEXT:    store i32 100, i32* [[I]], align 4
25085 // CHECK31-NEXT:    br label [[FOR_COND:%.*]]
25086 // CHECK31:       for.cond:
25087 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
25088 // CHECK31-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10
25089 // CHECK31-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25090 // CHECK31:       for.body:
25091 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
25092 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
25093 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25094 // CHECK31-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
25095 // CHECK31-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
25096 // CHECK31-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
25097 // CHECK31-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
25098 // CHECK31-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
25099 // CHECK31-NEXT:    [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1
25100 // CHECK31-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
25101 // CHECK31-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
25102 // CHECK31-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
25103 // CHECK31-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
25104 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
25105 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
25106 // CHECK31-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
25107 // CHECK31-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
25108 // CHECK31-NEXT:    br label [[FOR_INC:%.*]]
25109 // CHECK31:       for.inc:
25110 // CHECK31-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
25111 // CHECK31-NEXT:    [[ADD7:%.*]] = add i32 [[TMP5]], 10
25112 // CHECK31-NEXT:    store i32 [[ADD7]], i32* [[I]], align 4
25113 // CHECK31-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
25114 // CHECK31:       for.end:
25115 // CHECK31-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
25116 // CHECK31-NEXT:    ret i32 [[TMP6]]
25117 //
25118 //
25119 // CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
25120 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
25121 // CHECK31-NEXT:  entry:
25122 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25123 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
25124 // CHECK31-NEXT:    [[AA:%.*]] = alloca i16, align 2
25125 // CHECK31-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
25126 // CHECK31-NEXT:    [[I:%.*]] = alloca i64, align 8
25127 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25128 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
25129 // CHECK31-NEXT:    store i16 0, i16* [[AA]], align 2
25130 // CHECK31-NEXT:    store i64 -10, i64* [[I]], align 8
25131 // CHECK31-NEXT:    br label [[FOR_COND:%.*]]
25132 // CHECK31:       for.cond:
25133 // CHECK31-NEXT:    [[TMP0:%.*]] = load i64, i64* [[I]], align 8
25134 // CHECK31-NEXT:    [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10
25135 // CHECK31-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25136 // CHECK31:       for.body:
25137 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
25138 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
25139 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25140 // CHECK31-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
25141 // CHECK31-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
25142 // CHECK31-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
25143 // CHECK31-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
25144 // CHECK31-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
25145 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
25146 // CHECK31-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
25147 // CHECK31-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
25148 // CHECK31-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
25149 // CHECK31-NEXT:    br label [[FOR_INC:%.*]]
25150 // CHECK31:       for.inc:
25151 // CHECK31-NEXT:    [[TMP4:%.*]] = load i64, i64* [[I]], align 8
25152 // CHECK31-NEXT:    [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3
25153 // CHECK31-NEXT:    store i64 [[ADD4]], i64* [[I]], align 8
25154 // CHECK31-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
25155 // CHECK31:       for.end:
25156 // CHECK31-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
25157 // CHECK31-NEXT:    ret i32 [[TMP5]]
25158 //
25159 //
25160 // CHECK32-LABEL: define {{[^@]+}}@_Z7get_valv
25161 // CHECK32-SAME: () #[[ATTR0:[0-9]+]] {
25162 // CHECK32-NEXT:  entry:
25163 // CHECK32-NEXT:    ret i64 0
25164 //
25165 //
25166 // CHECK32-LABEL: define {{[^@]+}}@_Z3fooi
25167 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
25168 // CHECK32-NEXT:  entry:
25169 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25170 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
25171 // CHECK32-NEXT:    [[AA:%.*]] = alloca i16, align 2
25172 // CHECK32-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
25173 // CHECK32-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
25174 // CHECK32-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
25175 // CHECK32-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
25176 // CHECK32-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
25177 // CHECK32-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
25178 // CHECK32-NEXT:    [[I:%.*]] = alloca i32, align 4
25179 // CHECK32-NEXT:    [[K:%.*]] = alloca i64, align 8
25180 // CHECK32-NEXT:    [[I2:%.*]] = alloca i32, align 4
25181 // CHECK32-NEXT:    [[LIN:%.*]] = alloca i32, align 4
25182 // CHECK32-NEXT:    [[IT:%.*]] = alloca i64, align 8
25183 // CHECK32-NEXT:    [[IT16:%.*]] = alloca i16, align 2
25184 // CHECK32-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
25185 // CHECK32-NEXT:    [[IT30:%.*]] = alloca i8, align 1
25186 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25187 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
25188 // CHECK32-NEXT:    store i16 0, i16* [[AA]], align 2
25189 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25190 // CHECK32-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
25191 // CHECK32-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
25192 // CHECK32-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
25193 // CHECK32-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
25194 // CHECK32-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
25195 // CHECK32-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
25196 // CHECK32-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
25197 // CHECK32-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
25198 // CHECK32-NEXT:    store i32 3, i32* [[I]], align 4
25199 // CHECK32-NEXT:    br label [[FOR_COND:%.*]]
25200 // CHECK32:       for.cond:
25201 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
25202 // CHECK32-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32
25203 // CHECK32-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25204 // CHECK32:       for.body:
25205 // CHECK32-NEXT:    br label [[FOR_INC:%.*]]
25206 // CHECK32:       for.inc:
25207 // CHECK32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
25208 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP5]], 5
25209 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
25210 // CHECK32-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
25211 // CHECK32:       for.end:
25212 // CHECK32-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
25213 // CHECK32-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
25214 // CHECK32-NEXT:    store i32 10, i32* [[I2]], align 4
25215 // CHECK32-NEXT:    br label [[FOR_COND3:%.*]]
25216 // CHECK32:       for.cond3:
25217 // CHECK32-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I2]], align 4
25218 // CHECK32-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1
25219 // CHECK32-NEXT:    br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]]
25220 // CHECK32:       for.body5:
25221 // CHECK32-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
25222 // CHECK32-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1
25223 // CHECK32-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
25224 // CHECK32-NEXT:    br label [[FOR_INC7:%.*]]
25225 // CHECK32:       for.inc7:
25226 // CHECK32-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I2]], align 4
25227 // CHECK32-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP8]], -1
25228 // CHECK32-NEXT:    store i32 [[DEC]], i32* [[I2]], align 4
25229 // CHECK32-NEXT:    br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]]
25230 // CHECK32:       for.end8:
25231 // CHECK32-NEXT:    store i32 12, i32* [[LIN]], align 4
25232 // CHECK32-NEXT:    store i64 2000, i64* [[IT]], align 8
25233 // CHECK32-NEXT:    br label [[FOR_COND9:%.*]]
25234 // CHECK32:       for.cond9:
25235 // CHECK32-NEXT:    [[TMP9:%.*]] = load i64, i64* [[IT]], align 8
25236 // CHECK32-NEXT:    [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600
25237 // CHECK32-NEXT:    br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]]
25238 // CHECK32:       for.body11:
25239 // CHECK32-NEXT:    [[TMP10:%.*]] = load i16, i16* [[AA]], align 2
25240 // CHECK32-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
25241 // CHECK32-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV]], 1
25242 // CHECK32-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
25243 // CHECK32-NEXT:    store i16 [[CONV13]], i16* [[AA]], align 2
25244 // CHECK32-NEXT:    br label [[FOR_INC14:%.*]]
25245 // CHECK32:       for.inc14:
25246 // CHECK32-NEXT:    [[TMP11:%.*]] = load i64, i64* [[IT]], align 8
25247 // CHECK32-NEXT:    [[SUB:%.*]] = sub i64 [[TMP11]], 400
25248 // CHECK32-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
25249 // CHECK32-NEXT:    br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]]
25250 // CHECK32:       for.end15:
25251 // CHECK32-NEXT:    store i16 6, i16* [[IT16]], align 2
25252 // CHECK32-NEXT:    br label [[FOR_COND17:%.*]]
25253 // CHECK32:       for.cond17:
25254 // CHECK32-NEXT:    [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2
25255 // CHECK32-NEXT:    [[CONV18:%.*]] = sext i16 [[TMP12]] to i32
25256 // CHECK32-NEXT:    [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20
25257 // CHECK32-NEXT:    br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]]
25258 // CHECK32:       for.body20:
25259 // CHECK32-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4
25260 // CHECK32-NEXT:    [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1
25261 // CHECK32-NEXT:    store i32 [[ADD21]], i32* [[A]], align 4
25262 // CHECK32-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2
25263 // CHECK32-NEXT:    [[CONV22:%.*]] = sext i16 [[TMP14]] to i32
25264 // CHECK32-NEXT:    [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1
25265 // CHECK32-NEXT:    [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16
25266 // CHECK32-NEXT:    store i16 [[CONV24]], i16* [[AA]], align 2
25267 // CHECK32-NEXT:    br label [[FOR_INC25:%.*]]
25268 // CHECK32:       for.inc25:
25269 // CHECK32-NEXT:    [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2
25270 // CHECK32-NEXT:    [[CONV26:%.*]] = sext i16 [[TMP15]] to i32
25271 // CHECK32-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4
25272 // CHECK32-NEXT:    [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16
25273 // CHECK32-NEXT:    store i16 [[CONV28]], i16* [[IT16]], align 2
25274 // CHECK32-NEXT:    br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]]
25275 // CHECK32:       for.end29:
25276 // CHECK32-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4
25277 // CHECK32-NEXT:    store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4
25278 // CHECK32-NEXT:    store i8 122, i8* [[IT30]], align 1
25279 // CHECK32-NEXT:    br label [[FOR_COND31:%.*]]
25280 // CHECK32:       for.cond31:
25281 // CHECK32-NEXT:    [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1
25282 // CHECK32-NEXT:    [[CONV32:%.*]] = zext i8 [[TMP17]] to i32
25283 // CHECK32-NEXT:    [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97
25284 // CHECK32-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]]
25285 // CHECK32:       for.body34:
25286 // CHECK32-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
25287 // CHECK32-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1
25288 // CHECK32-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
25289 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
25290 // CHECK32-NEXT:    [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4
25291 // CHECK32-NEXT:    [[CONV36:%.*]] = fpext float [[TMP19]] to double
25292 // CHECK32-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
25293 // CHECK32-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
25294 // CHECK32-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
25295 // CHECK32-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
25296 // CHECK32-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4
25297 // CHECK32-NEXT:    [[CONV40:%.*]] = fpext float [[TMP20]] to double
25298 // CHECK32-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
25299 // CHECK32-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
25300 // CHECK32-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
25301 // CHECK32-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
25302 // CHECK32-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2
25303 // CHECK32-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8
25304 // CHECK32-NEXT:    [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00
25305 // CHECK32-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
25306 // CHECK32-NEXT:    [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]]
25307 // CHECK32-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]]
25308 // CHECK32-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3
25309 // CHECK32-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8
25310 // CHECK32-NEXT:    [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00
25311 // CHECK32-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
25312 // CHECK32-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
25313 // CHECK32-NEXT:    [[TMP24:%.*]] = load i64, i64* [[X]], align 4
25314 // CHECK32-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1
25315 // CHECK32-NEXT:    store i64 [[ADD49]], i64* [[X]], align 4
25316 // CHECK32-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
25317 // CHECK32-NEXT:    [[TMP25:%.*]] = load i8, i8* [[Y]], align 4
25318 // CHECK32-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP25]] to i32
25319 // CHECK32-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
25320 // CHECK32-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
25321 // CHECK32-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 4
25322 // CHECK32-NEXT:    br label [[FOR_INC53:%.*]]
25323 // CHECK32:       for.inc53:
25324 // CHECK32-NEXT:    [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1
25325 // CHECK32-NEXT:    [[CONV54:%.*]] = zext i8 [[TMP26]] to i32
25326 // CHECK32-NEXT:    [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1
25327 // CHECK32-NEXT:    [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8
25328 // CHECK32-NEXT:    store i8 [[CONV56]], i8* [[IT30]], align 1
25329 // CHECK32-NEXT:    br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]]
25330 // CHECK32:       for.end57:
25331 // CHECK32-NEXT:    [[TMP27:%.*]] = load i32, i32* [[A]], align 4
25332 // CHECK32-NEXT:    [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
25333 // CHECK32-NEXT:    call void @llvm.stackrestore(i8* [[TMP28]])
25334 // CHECK32-NEXT:    ret i32 [[TMP27]]
25335 //
25336 //
25337 // CHECK32-LABEL: define {{[^@]+}}@_Z3bari
25338 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
25339 // CHECK32-NEXT:  entry:
25340 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25341 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
25342 // CHECK32-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
25343 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25344 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
25345 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25346 // CHECK32-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
25347 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
25348 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
25349 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25350 // CHECK32-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
25351 // CHECK32-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
25352 // CHECK32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
25353 // CHECK32-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
25354 // CHECK32-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
25355 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
25356 // CHECK32-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
25357 // CHECK32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
25358 // CHECK32-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
25359 // CHECK32-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
25360 // CHECK32-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
25361 // CHECK32-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
25362 // CHECK32-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
25363 // CHECK32-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
25364 // CHECK32-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
25365 // CHECK32-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
25366 // CHECK32-NEXT:    ret i32 [[TMP8]]
25367 //
25368 //
25369 // CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
25370 // CHECK32-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
25371 // CHECK32-NEXT:  entry:
25372 // CHECK32-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
25373 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25374 // CHECK32-NEXT:    [[B:%.*]] = alloca i32, align 4
25375 // CHECK32-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
25376 // CHECK32-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
25377 // CHECK32-NEXT:    [[IT:%.*]] = alloca i64, align 8
25378 // CHECK32-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
25379 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25380 // CHECK32-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
25381 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25382 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
25383 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
25384 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
25385 // CHECK32-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
25386 // CHECK32-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
25387 // CHECK32-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
25388 // CHECK32-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
25389 // CHECK32-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
25390 // CHECK32-NEXT:    store i64 2000, i64* [[IT]], align 8
25391 // CHECK32-NEXT:    br label [[FOR_COND:%.*]]
25392 // CHECK32:       for.cond:
25393 // CHECK32-NEXT:    [[TMP4:%.*]] = load i64, i64* [[IT]], align 8
25394 // CHECK32-NEXT:    [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600
25395 // CHECK32-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25396 // CHECK32:       for.body:
25397 // CHECK32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
25398 // CHECK32-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
25399 // CHECK32-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
25400 // CHECK32-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
25401 // CHECK32-NEXT:    store double [[ADD2]], double* [[A]], align 4
25402 // CHECK32-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
25403 // CHECK32-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 4
25404 // CHECK32-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
25405 // CHECK32-NEXT:    store double [[INC]], double* [[A3]], align 4
25406 // CHECK32-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
25407 // CHECK32-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
25408 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
25409 // CHECK32-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
25410 // CHECK32-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
25411 // CHECK32-NEXT:    br label [[FOR_INC:%.*]]
25412 // CHECK32:       for.inc:
25413 // CHECK32-NEXT:    [[TMP8:%.*]] = load i64, i64* [[IT]], align 8
25414 // CHECK32-NEXT:    [[SUB:%.*]] = sub i64 [[TMP8]], 400
25415 // CHECK32-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8
25416 // CHECK32-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
25417 // CHECK32:       for.end:
25418 // CHECK32-NEXT:    [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]]
25419 // CHECK32-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]]
25420 // CHECK32-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
25421 // CHECK32-NEXT:    [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
25422 // CHECK32-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP10]] to i32
25423 // CHECK32-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4
25424 // CHECK32-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]]
25425 // CHECK32-NEXT:    [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
25426 // CHECK32-NEXT:    call void @llvm.stackrestore(i8* [[TMP12]])
25427 // CHECK32-NEXT:    ret i32 [[ADD9]]
25428 //
25429 //
25430 // CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici
25431 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
25432 // CHECK32-NEXT:  entry:
25433 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25434 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
25435 // CHECK32-NEXT:    [[AA:%.*]] = alloca i16, align 2
25436 // CHECK32-NEXT:    [[AAA:%.*]] = alloca i8, align 1
25437 // CHECK32-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
25438 // CHECK32-NEXT:    [[I:%.*]] = alloca i32, align 4
25439 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25440 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
25441 // CHECK32-NEXT:    store i16 0, i16* [[AA]], align 2
25442 // CHECK32-NEXT:    store i8 0, i8* [[AAA]], align 1
25443 // CHECK32-NEXT:    store i32 100, i32* [[I]], align 4
25444 // CHECK32-NEXT:    br label [[FOR_COND:%.*]]
25445 // CHECK32:       for.cond:
25446 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
25447 // CHECK32-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10
25448 // CHECK32-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25449 // CHECK32:       for.body:
25450 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
25451 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
25452 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25453 // CHECK32-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
25454 // CHECK32-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
25455 // CHECK32-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
25456 // CHECK32-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
25457 // CHECK32-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
25458 // CHECK32-NEXT:    [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1
25459 // CHECK32-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
25460 // CHECK32-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
25461 // CHECK32-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
25462 // CHECK32-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
25463 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
25464 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
25465 // CHECK32-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
25466 // CHECK32-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
25467 // CHECK32-NEXT:    br label [[FOR_INC:%.*]]
25468 // CHECK32:       for.inc:
25469 // CHECK32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
25470 // CHECK32-NEXT:    [[ADD7:%.*]] = add i32 [[TMP5]], 10
25471 // CHECK32-NEXT:    store i32 [[ADD7]], i32* [[I]], align 4
25472 // CHECK32-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
25473 // CHECK32:       for.end:
25474 // CHECK32-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
25475 // CHECK32-NEXT:    ret i32 [[TMP6]]
25476 //
25477 //
25478 // CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
25479 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
25480 // CHECK32-NEXT:  entry:
25481 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25482 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
25483 // CHECK32-NEXT:    [[AA:%.*]] = alloca i16, align 2
25484 // CHECK32-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
25485 // CHECK32-NEXT:    [[I:%.*]] = alloca i64, align 8
25486 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25487 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
25488 // CHECK32-NEXT:    store i16 0, i16* [[AA]], align 2
25489 // CHECK32-NEXT:    store i64 -10, i64* [[I]], align 8
25490 // CHECK32-NEXT:    br label [[FOR_COND:%.*]]
25491 // CHECK32:       for.cond:
25492 // CHECK32-NEXT:    [[TMP0:%.*]] = load i64, i64* [[I]], align 8
25493 // CHECK32-NEXT:    [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10
25494 // CHECK32-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25495 // CHECK32:       for.body:
25496 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
25497 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
25498 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25499 // CHECK32-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
25500 // CHECK32-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
25501 // CHECK32-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
25502 // CHECK32-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
25503 // CHECK32-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
25504 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
25505 // CHECK32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
25506 // CHECK32-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
25507 // CHECK32-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
25508 // CHECK32-NEXT:    br label [[FOR_INC:%.*]]
25509 // CHECK32:       for.inc:
25510 // CHECK32-NEXT:    [[TMP4:%.*]] = load i64, i64* [[I]], align 8
25511 // CHECK32-NEXT:    [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3
25512 // CHECK32-NEXT:    store i64 [[ADD4]], i64* [[I]], align 8
25513 // CHECK32-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
25514 // CHECK32:       for.end:
25515 // CHECK32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
25516 // CHECK32-NEXT:    ret i32 [[TMP5]]
25517 //
25518