1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 10 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 15 // expected-no-diagnostics 16 #ifndef HEADER 17 #define HEADER 18 19 20 21 double Ga = 1.0; 22 double Gb = 2.0; 23 double Gc = 3.0; 24 double Gd = 4.0; 25 26 int foo(short a, short b, short c, short d){ 27 static float Sa = 5.0; 28 static float Sb = 6.0; 29 static float Sc = 7.0; 30 static float Sd = 8.0; 31 32 33 // 3 local vars being captured. 34 35 36 37 38 // 3 static vars being captured. 39 40 41 42 43 // 3 static global vars being captured. 44 45 46 47 48 // Capture b, Gb, Sb, Gc, c, Sc, d, Gd, Sd 49 #pragma omp target if(Ga>0.0 && a>0 && Sa>0.0) 50 { 51 b += 1; 52 Gb += 1.0; 53 Sb += 1.0; 54 55 // The parallel region only uses 3 captures. 56 // Capture d, Gd, Sd, 57 58 #pragma omp parallel if(Gc>0.0 && c>0 && Sc>0.0) 59 { 60 d += 1; 61 Gd += 1.0; 62 Sd += 1.0; 63 } 64 } 65 return a + b + c + d + (int)Sa + (int)Sb + (int)Sc + (int)Sd; 66 } 67 68 int bar(short a, short b, short c, short d){ 69 static float Sa = 9.0; 70 static float Sb = 10.0; 71 static float Sc = 11.0; 72 static float Sd = 12.0; 73 74 // Capture a, b, c, d 75 #pragma omp parallel 76 { 77 78 // 3 local vars being captured. 79 80 81 82 83 // 3 static vars being captured. 84 85 86 87 88 // 3 static global vars being captured. 89 90 91 92 93 // Capture b, Gb, Sb, Gc, c, Sc, d, Gd, Sd 94 #pragma omp target if(Ga>0.0 && a>0 && Sa>0.0) 95 { 96 b += 1; 97 Gb += 1.0; 98 Sb += 1.0; 99 100 101 // Capture d, Gd, Sd 102 #pragma omp parallel if(Gc>0.0 && c>0 && Sc>0.0) 103 { 104 d += 1; 105 Gd += 1.0; 106 Sd += 1.0; 107 } 108 } 109 } 110 return a + b + c + d + (int)Sa + (int)Sb + (int)Sc + (int)Sd; 111 } 112 113 /// 114 /// Tests with template functions. 115 /// 116 117 118 template<typename T> 119 int tbar(T a, T b, T c, T d){ 120 static float Sa = 17.0; 121 static float Sb = 18.0; 122 static float Sc = 19.0; 123 static float Sd = 20.0; 124 125 // Capture a, b, c, d 126 #pragma omp parallel 127 { 128 129 // 3 local vars being captured. 130 131 132 133 134 // 3 static vars being captured. 135 136 137 138 139 // 3 static global vars being captured. 140 141 142 143 144 // Capture b, Gb, Sb, Gc, c, Sc, d, Gd, Sd 145 #pragma omp target if(Ga>0.0 && a>0 && Sa>0.0) 146 { 147 b += 1; 148 Gb += 1.0; 149 Sb += 1.0; 150 151 152 // Capture d, Gd, Sd 153 #pragma omp parallel if(Gc>0.0 && c>0 && Sc>0.0) 154 { 155 d += 1; 156 Gd += 1.0; 157 Sd += 1.0; 158 } 159 } 160 } 161 return a + b + c + d + (int)Sa + (int)Sb + (int)Sc + (int)Sd; 162 } 163 164 int tbar2(short a, short b, short c, short d){ 165 return tbar(a, b, c, d); 166 } 167 168 #endif 169 // CHECK1-LABEL: define {{[^@]+}}@_Z3foossss 170 // CHECK1-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0:[0-9]+]] { 171 // CHECK1-NEXT: entry: 172 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 173 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 174 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 175 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 176 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 177 // CHECK1-NEXT: [[GB_CASTED:%.*]] = alloca i64, align 8 178 // CHECK1-NEXT: [[SB_CASTED:%.*]] = alloca i64, align 8 179 // CHECK1-NEXT: [[GC_CASTED:%.*]] = alloca i64, align 8 180 // CHECK1-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 181 // CHECK1-NEXT: [[SC_CASTED:%.*]] = alloca i64, align 8 182 // CHECK1-NEXT: [[D_CASTED:%.*]] = alloca i64, align 8 183 // CHECK1-NEXT: [[GD_CASTED:%.*]] = alloca i64, align 8 184 // CHECK1-NEXT: [[SD_CASTED:%.*]] = alloca i64, align 8 185 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 8 186 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 8 187 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 8 188 // CHECK1-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 189 // CHECK1-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 190 // CHECK1-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 191 // CHECK1-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 192 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 193 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i16* 194 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2 195 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_CASTED]], align 8 196 // CHECK1-NEXT: [[TMP2:%.*]] = load double, double* @Gb, align 8 197 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_CASTED]] to double* 198 // CHECK1-NEXT: store double [[TMP2]], double* [[CONV1]], align 8 199 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[GB_CASTED]], align 8 200 // CHECK1-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 201 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_CASTED]] to float* 202 // CHECK1-NEXT: store float [[TMP4]], float* [[CONV2]], align 4 203 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[SB_CASTED]], align 8 204 // CHECK1-NEXT: [[TMP6:%.*]] = load double, double* @Gc, align 8 205 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_CASTED]] to double* 206 // CHECK1-NEXT: store double [[TMP6]], double* [[CONV3]], align 8 207 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[GC_CASTED]], align 8 208 // CHECK1-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 209 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_CASTED]] to i16* 210 // CHECK1-NEXT: store i16 [[TMP8]], i16* [[CONV4]], align 2 211 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8 212 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4 213 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_CASTED]] to float* 214 // CHECK1-NEXT: store float [[TMP10]], float* [[CONV5]], align 4 215 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[SC_CASTED]], align 8 216 // CHECK1-NEXT: [[TMP12:%.*]] = load i16, i16* [[D_ADDR]], align 2 217 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_CASTED]] to i16* 218 // CHECK1-NEXT: store i16 [[TMP12]], i16* [[CONV6]], align 2 219 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[D_CASTED]], align 8 220 // CHECK1-NEXT: [[TMP14:%.*]] = load double, double* @Gd, align 8 221 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_CASTED]] to double* 222 // CHECK1-NEXT: store double [[TMP14]], double* [[CONV7]], align 8 223 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[GD_CASTED]], align 8 224 // CHECK1-NEXT: [[TMP16:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 225 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_CASTED]] to float* 226 // CHECK1-NEXT: store float [[TMP16]], float* [[CONV8]], align 4 227 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[SD_CASTED]], align 8 228 // CHECK1-NEXT: [[TMP18:%.*]] = load double, double* @Ga, align 8 229 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP18]], 0.000000e+00 230 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] 231 // CHECK1: land.lhs.true: 232 // CHECK1-NEXT: [[TMP19:%.*]] = load i16, i16* [[A_ADDR]], align 2 233 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP19]] to i32 234 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[CONV9]], 0 235 // CHECK1-NEXT: br i1 [[CMP10]], label [[LAND_LHS_TRUE11:%.*]], label [[OMP_IF_ELSE]] 236 // CHECK1: land.lhs.true11: 237 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4 238 // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP20]] to double 239 // CHECK1-NEXT: [[CMP13:%.*]] = fcmp ogt double [[CONV12]], 0.000000e+00 240 // CHECK1-NEXT: br i1 [[CMP13]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] 241 // CHECK1: omp_if.then: 242 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 243 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 244 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP22]], align 8 245 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 246 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 247 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP24]], align 8 248 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 249 // CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8 250 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 251 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 252 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8 253 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 254 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 255 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP29]], align 8 256 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 257 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8 258 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 259 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 260 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP32]], align 8 261 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 262 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64* 263 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP34]], align 8 264 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 265 // CHECK1-NEXT: store i8* null, i8** [[TMP35]], align 8 266 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 267 // CHECK1-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* 268 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP37]], align 8 269 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 270 // CHECK1-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* 271 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP39]], align 8 272 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 273 // CHECK1-NEXT: store i8* null, i8** [[TMP40]], align 8 274 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 275 // CHECK1-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i64* 276 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP42]], align 8 277 // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 278 // CHECK1-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i64* 279 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP44]], align 8 280 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 281 // CHECK1-NEXT: store i8* null, i8** [[TMP45]], align 8 282 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 283 // CHECK1-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i64* 284 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[TMP47]], align 8 285 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 286 // CHECK1-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i64* 287 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[TMP49]], align 8 288 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 289 // CHECK1-NEXT: store i8* null, i8** [[TMP50]], align 8 290 // CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 291 // CHECK1-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64* 292 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[TMP52]], align 8 293 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 294 // CHECK1-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i64* 295 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[TMP54]], align 8 296 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 297 // CHECK1-NEXT: store i8* null, i8** [[TMP55]], align 8 298 // CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 299 // CHECK1-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to i64* 300 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP57]], align 8 301 // CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 302 // CHECK1-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to i64* 303 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP59]], align 8 304 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 305 // CHECK1-NEXT: store i8* null, i8** [[TMP60]], align 8 306 // CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 307 // CHECK1-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 308 // CHECK1-NEXT: store i64 [[TMP17]], i64* [[TMP62]], align 8 309 // CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 310 // CHECK1-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* 311 // CHECK1-NEXT: store i64 [[TMP17]], i64* [[TMP64]], align 8 312 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8 313 // CHECK1-NEXT: store i8* null, i8** [[TMP65]], align 8 314 // CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 315 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 316 // CHECK1-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49.region_id, i32 9, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null) 317 // CHECK1-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 318 // CHECK1-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 319 // CHECK1: omp_offload.failed: 320 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]]) #[[ATTR2:[0-9]+]] 321 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 322 // CHECK1: omp_offload.cont: 323 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 324 // CHECK1: omp_if.else: 325 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]]) #[[ATTR2]] 326 // CHECK1-NEXT: br label [[OMP_IF_END]] 327 // CHECK1: omp_if.end: 328 // CHECK1-NEXT: [[TMP70:%.*]] = load i16, i16* [[A_ADDR]], align 2 329 // CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP70]] to i32 330 // CHECK1-NEXT: [[TMP71:%.*]] = load i16, i16* [[B_ADDR]], align 2 331 // CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP71]] to i32 332 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV14]], [[CONV15]] 333 // CHECK1-NEXT: [[TMP72:%.*]] = load i16, i16* [[C_ADDR]], align 2 334 // CHECK1-NEXT: [[CONV16:%.*]] = sext i16 [[TMP72]] to i32 335 // CHECK1-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD]], [[CONV16]] 336 // CHECK1-NEXT: [[TMP73:%.*]] = load i16, i16* [[D_ADDR]], align 2 337 // CHECK1-NEXT: [[CONV18:%.*]] = sext i16 [[TMP73]] to i32 338 // CHECK1-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] 339 // CHECK1-NEXT: [[TMP74:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4 340 // CHECK1-NEXT: [[CONV20:%.*]] = fptosi float [[TMP74]] to i32 341 // CHECK1-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] 342 // CHECK1-NEXT: [[TMP75:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 343 // CHECK1-NEXT: [[CONV22:%.*]] = fptosi float [[TMP75]] to i32 344 // CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] 345 // CHECK1-NEXT: [[TMP76:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4 346 // CHECK1-NEXT: [[CONV24:%.*]] = fptosi float [[TMP76]] to i32 347 // CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] 348 // CHECK1-NEXT: [[TMP77:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 349 // CHECK1-NEXT: [[CONV26:%.*]] = fptosi float [[TMP77]] to i32 350 // CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] 351 // CHECK1-NEXT: ret i32 [[ADD27]] 352 // 353 // 354 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49 355 // CHECK1-SAME: (i64 noundef [[B:%.*]], i64 noundef [[GB:%.*]], i64 noundef [[SB:%.*]], i64 noundef [[GC:%.*]], i64 noundef [[C:%.*]], i64 noundef [[SC:%.*]], i64 noundef [[D:%.*]], i64 noundef [[GD:%.*]], i64 noundef [[SD:%.*]]) #[[ATTR1:[0-9]+]] { 356 // CHECK1-NEXT: entry: 357 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 358 // CHECK1-NEXT: [[GB_ADDR:%.*]] = alloca i64, align 8 359 // CHECK1-NEXT: [[SB_ADDR:%.*]] = alloca i64, align 8 360 // CHECK1-NEXT: [[GC_ADDR:%.*]] = alloca i64, align 8 361 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 362 // CHECK1-NEXT: [[SC_ADDR:%.*]] = alloca i64, align 8 363 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i64, align 8 364 // CHECK1-NEXT: [[GD_ADDR:%.*]] = alloca i64, align 8 365 // CHECK1-NEXT: [[SD_ADDR:%.*]] = alloca i64, align 8 366 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 367 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 368 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 369 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 370 // CHECK1-NEXT: store i64 [[GB]], i64* [[GB_ADDR]], align 8 371 // CHECK1-NEXT: store i64 [[SB]], i64* [[SB_ADDR]], align 8 372 // CHECK1-NEXT: store i64 [[GC]], i64* [[GC_ADDR]], align 8 373 // CHECK1-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 374 // CHECK1-NEXT: store i64 [[SC]], i64* [[SC_ADDR]], align 8 375 // CHECK1-NEXT: store i64 [[D]], i64* [[D_ADDR]], align 8 376 // CHECK1-NEXT: store i64 [[GD]], i64* [[GD_ADDR]], align 8 377 // CHECK1-NEXT: store i64 [[SD]], i64* [[SD_ADDR]], align 8 378 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i16* 379 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double* 380 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float* 381 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double* 382 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16* 383 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float* 384 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16* 385 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double* 386 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float* 387 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 388 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32 389 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1 390 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 391 // CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2 392 // CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8 393 // CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00 394 // CHECK1-NEXT: store double [[ADD11]], double* [[CONV1]], align 8 395 // CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 4 396 // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double 397 // CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00 398 // CHECK1-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float 399 // CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 4 400 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8 401 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00 402 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] 403 // CHECK1: land.lhs.true: 404 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 2 405 // CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32 406 // CHECK1-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0 407 // CHECK1-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]] 408 // CHECK1: land.lhs.true17: 409 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 4 410 // CHECK1-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double 411 // CHECK1-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00 412 // CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] 413 // CHECK1: omp_if.then: 414 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined. to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) 415 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 416 // CHECK1: omp_if.else: 417 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 418 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 419 // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 420 // CHECK1-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) #[[ATTR2]] 421 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 422 // CHECK1-NEXT: br label [[OMP_IF_END]] 423 // CHECK1: omp_if.end: 424 // CHECK1-NEXT: ret void 425 // 426 // 427 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 428 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { 429 // CHECK1-NEXT: entry: 430 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 431 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 432 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8 433 // CHECK1-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 8 434 // CHECK1-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 8 435 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 436 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 437 // CHECK1-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8 438 // CHECK1-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 8 439 // CHECK1-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 8 440 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 8 441 // CHECK1-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 8 442 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 8 443 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2 444 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32 445 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 446 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 447 // CHECK1-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2 448 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8 449 // CHECK1-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00 450 // CHECK1-NEXT: store double [[ADD2]], double* [[TMP1]], align 8 451 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4 452 // CHECK1-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double 453 // CHECK1-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 454 // CHECK1-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float 455 // CHECK1-NEXT: store float [[CONV5]], float* [[TMP2]], align 4 456 // CHECK1-NEXT: ret void 457 // 458 // 459 // CHECK1-LABEL: define {{[^@]+}}@_Z3barssss 460 // CHECK1-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] { 461 // CHECK1-NEXT: entry: 462 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 463 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 464 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 465 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 466 // CHECK1-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 467 // CHECK1-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 468 // CHECK1-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 469 // CHECK1-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 470 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, i16*, i16*, i16*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i16* [[A_ADDR]], i16* [[B_ADDR]], i16* [[C_ADDR]], i16* [[D_ADDR]]) 471 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2 472 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 473 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2 474 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 475 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]] 476 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2 477 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 478 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]] 479 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 480 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP3]] to i32 481 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]] 482 // CHECK1-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4 483 // CHECK1-NEXT: [[CONV6:%.*]] = fptosi float [[TMP4]] to i32 484 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]] 485 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 486 // CHECK1-NEXT: [[CONV8:%.*]] = fptosi float [[TMP5]] to i32 487 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]] 488 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4 489 // CHECK1-NEXT: [[CONV10:%.*]] = fptosi float [[TMP6]] to i32 490 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]] 491 // CHECK1-NEXT: [[TMP7:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 492 // CHECK1-NEXT: [[CONV12:%.*]] = fptosi float [[TMP7]] to i32 493 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]] 494 // CHECK1-NEXT: ret i32 [[ADD13]] 495 // 496 // 497 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 498 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { 499 // CHECK1-NEXT: entry: 500 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 501 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 502 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16*, align 8 503 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16*, align 8 504 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 505 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8 506 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 507 // CHECK1-NEXT: [[GB_CASTED:%.*]] = alloca i64, align 8 508 // CHECK1-NEXT: [[SB_CASTED:%.*]] = alloca i64, align 8 509 // CHECK1-NEXT: [[GC_CASTED:%.*]] = alloca i64, align 8 510 // CHECK1-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 511 // CHECK1-NEXT: [[SC_CASTED:%.*]] = alloca i64, align 8 512 // CHECK1-NEXT: [[D_CASTED:%.*]] = alloca i64, align 8 513 // CHECK1-NEXT: [[GD_CASTED:%.*]] = alloca i64, align 8 514 // CHECK1-NEXT: [[SD_CASTED:%.*]] = alloca i64, align 8 515 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 8 516 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 8 517 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 8 518 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 519 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 520 // CHECK1-NEXT: store i16* [[A]], i16** [[A_ADDR]], align 8 521 // CHECK1-NEXT: store i16* [[B]], i16** [[B_ADDR]], align 8 522 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 523 // CHECK1-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8 524 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[A_ADDR]], align 8 525 // CHECK1-NEXT: [[TMP1:%.*]] = load i16*, i16** [[B_ADDR]], align 8 526 // CHECK1-NEXT: [[TMP2:%.*]] = load i16*, i16** [[C_ADDR]], align 8 527 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[D_ADDR]], align 8 528 // CHECK1-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2 529 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i16* 530 // CHECK1-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2 531 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 532 // CHECK1-NEXT: [[TMP6:%.*]] = load double, double* @Gb, align 8 533 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_CASTED]] to double* 534 // CHECK1-NEXT: store double [[TMP6]], double* [[CONV1]], align 8 535 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[GB_CASTED]], align 8 536 // CHECK1-NEXT: [[TMP8:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 537 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_CASTED]] to float* 538 // CHECK1-NEXT: store float [[TMP8]], float* [[CONV2]], align 4 539 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[SB_CASTED]], align 8 540 // CHECK1-NEXT: [[TMP10:%.*]] = load double, double* @Gc, align 8 541 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_CASTED]] to double* 542 // CHECK1-NEXT: store double [[TMP10]], double* [[CONV3]], align 8 543 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[GC_CASTED]], align 8 544 // CHECK1-NEXT: [[TMP12:%.*]] = load i16, i16* [[TMP2]], align 2 545 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_CASTED]] to i16* 546 // CHECK1-NEXT: store i16 [[TMP12]], i16* [[CONV4]], align 2 547 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[C_CASTED]], align 8 548 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4 549 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_CASTED]] to float* 550 // CHECK1-NEXT: store float [[TMP14]], float* [[CONV5]], align 4 551 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[SC_CASTED]], align 8 552 // CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[TMP3]], align 2 553 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_CASTED]] to i16* 554 // CHECK1-NEXT: store i16 [[TMP16]], i16* [[CONV6]], align 2 555 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[D_CASTED]], align 8 556 // CHECK1-NEXT: [[TMP18:%.*]] = load double, double* @Gd, align 8 557 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_CASTED]] to double* 558 // CHECK1-NEXT: store double [[TMP18]], double* [[CONV7]], align 8 559 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[GD_CASTED]], align 8 560 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 561 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_CASTED]] to float* 562 // CHECK1-NEXT: store float [[TMP20]], float* [[CONV8]], align 4 563 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SD_CASTED]], align 8 564 // CHECK1-NEXT: [[TMP22:%.*]] = load double, double* @Ga, align 8 565 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP22]], 0.000000e+00 566 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] 567 // CHECK1: land.lhs.true: 568 // CHECK1-NEXT: [[TMP23:%.*]] = load i16, i16* [[TMP0]], align 2 569 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP23]] to i32 570 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[CONV9]], 0 571 // CHECK1-NEXT: br i1 [[CMP10]], label [[LAND_LHS_TRUE11:%.*]], label [[OMP_IF_ELSE]] 572 // CHECK1: land.lhs.true11: 573 // CHECK1-NEXT: [[TMP24:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4 574 // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP24]] to double 575 // CHECK1-NEXT: [[CMP13:%.*]] = fcmp ogt double [[CONV12]], 0.000000e+00 576 // CHECK1-NEXT: br i1 [[CMP13]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] 577 // CHECK1: omp_if.then: 578 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 579 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 580 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP26]], align 8 581 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 582 // CHECK1-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 583 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP28]], align 8 584 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 585 // CHECK1-NEXT: store i8* null, i8** [[TMP29]], align 8 586 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 587 // CHECK1-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 588 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP31]], align 8 589 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 590 // CHECK1-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* 591 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP33]], align 8 592 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 593 // CHECK1-NEXT: store i8* null, i8** [[TMP34]], align 8 594 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 595 // CHECK1-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64* 596 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP36]], align 8 597 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 598 // CHECK1-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64* 599 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 600 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 601 // CHECK1-NEXT: store i8* null, i8** [[TMP39]], align 8 602 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 603 // CHECK1-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* 604 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[TMP41]], align 8 605 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 606 // CHECK1-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* 607 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[TMP43]], align 8 608 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 609 // CHECK1-NEXT: store i8* null, i8** [[TMP44]], align 8 610 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 611 // CHECK1-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* 612 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[TMP46]], align 8 613 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 614 // CHECK1-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64* 615 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[TMP48]], align 8 616 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 617 // CHECK1-NEXT: store i8* null, i8** [[TMP49]], align 8 618 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 619 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64* 620 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP51]], align 8 621 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 622 // CHECK1-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64* 623 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP53]], align 8 624 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 625 // CHECK1-NEXT: store i8* null, i8** [[TMP54]], align 8 626 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 627 // CHECK1-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i64* 628 // CHECK1-NEXT: store i64 [[TMP17]], i64* [[TMP56]], align 8 629 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 630 // CHECK1-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i64* 631 // CHECK1-NEXT: store i64 [[TMP17]], i64* [[TMP58]], align 8 632 // CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 633 // CHECK1-NEXT: store i8* null, i8** [[TMP59]], align 8 634 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 635 // CHECK1-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i64* 636 // CHECK1-NEXT: store i64 [[TMP19]], i64* [[TMP61]], align 8 637 // CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 638 // CHECK1-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i64* 639 // CHECK1-NEXT: store i64 [[TMP19]], i64* [[TMP63]], align 8 640 // CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 641 // CHECK1-NEXT: store i8* null, i8** [[TMP64]], align 8 642 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 643 // CHECK1-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to i64* 644 // CHECK1-NEXT: store i64 [[TMP21]], i64* [[TMP66]], align 8 645 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 646 // CHECK1-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i64* 647 // CHECK1-NEXT: store i64 [[TMP21]], i64* [[TMP68]], align 8 648 // CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8 649 // CHECK1-NEXT: store i8* null, i8** [[TMP69]], align 8 650 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 651 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 652 // CHECK1-NEXT: [[TMP72:%.*]] = call i32 @__tgt_target_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94.region_id, i32 9, i8** [[TMP70]], i8** [[TMP71]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes.3, i32 0, i32 0), i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null) 653 // CHECK1-NEXT: [[TMP73:%.*]] = icmp ne i32 [[TMP72]], 0 654 // CHECK1-NEXT: br i1 [[TMP73]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 655 // CHECK1: omp_offload.failed: 656 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]] 657 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 658 // CHECK1: omp_offload.cont: 659 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 660 // CHECK1: omp_if.else: 661 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]] 662 // CHECK1-NEXT: br label [[OMP_IF_END]] 663 // CHECK1: omp_if.end: 664 // CHECK1-NEXT: ret void 665 // 666 // 667 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94 668 // CHECK1-SAME: (i64 noundef [[B:%.*]], i64 noundef [[GB:%.*]], i64 noundef [[SB:%.*]], i64 noundef [[GC:%.*]], i64 noundef [[C:%.*]], i64 noundef [[SC:%.*]], i64 noundef [[D:%.*]], i64 noundef [[GD:%.*]], i64 noundef [[SD:%.*]]) #[[ATTR1]] { 669 // CHECK1-NEXT: entry: 670 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 671 // CHECK1-NEXT: [[GB_ADDR:%.*]] = alloca i64, align 8 672 // CHECK1-NEXT: [[SB_ADDR:%.*]] = alloca i64, align 8 673 // CHECK1-NEXT: [[GC_ADDR:%.*]] = alloca i64, align 8 674 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 675 // CHECK1-NEXT: [[SC_ADDR:%.*]] = alloca i64, align 8 676 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i64, align 8 677 // CHECK1-NEXT: [[GD_ADDR:%.*]] = alloca i64, align 8 678 // CHECK1-NEXT: [[SD_ADDR:%.*]] = alloca i64, align 8 679 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 680 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 681 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 682 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 683 // CHECK1-NEXT: store i64 [[GB]], i64* [[GB_ADDR]], align 8 684 // CHECK1-NEXT: store i64 [[SB]], i64* [[SB_ADDR]], align 8 685 // CHECK1-NEXT: store i64 [[GC]], i64* [[GC_ADDR]], align 8 686 // CHECK1-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 687 // CHECK1-NEXT: store i64 [[SC]], i64* [[SC_ADDR]], align 8 688 // CHECK1-NEXT: store i64 [[D]], i64* [[D_ADDR]], align 8 689 // CHECK1-NEXT: store i64 [[GD]], i64* [[GD_ADDR]], align 8 690 // CHECK1-NEXT: store i64 [[SD]], i64* [[SD_ADDR]], align 8 691 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i16* 692 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double* 693 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float* 694 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double* 695 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16* 696 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float* 697 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16* 698 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double* 699 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float* 700 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 701 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32 702 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1 703 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 704 // CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2 705 // CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8 706 // CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00 707 // CHECK1-NEXT: store double [[ADD11]], double* [[CONV1]], align 8 708 // CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 4 709 // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double 710 // CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00 711 // CHECK1-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float 712 // CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 4 713 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8 714 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00 715 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] 716 // CHECK1: land.lhs.true: 717 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 2 718 // CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32 719 // CHECK1-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0 720 // CHECK1-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]] 721 // CHECK1: land.lhs.true17: 722 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 4 723 // CHECK1-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double 724 // CHECK1-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00 725 // CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] 726 // CHECK1: omp_if.then: 727 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) 728 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 729 // CHECK1: omp_if.else: 730 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 731 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 732 // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 733 // CHECK1-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) #[[ATTR2]] 734 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 735 // CHECK1-NEXT: br label [[OMP_IF_END]] 736 // CHECK1: omp_if.end: 737 // CHECK1-NEXT: ret void 738 // 739 // 740 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 741 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { 742 // CHECK1-NEXT: entry: 743 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 744 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 745 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8 746 // CHECK1-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 8 747 // CHECK1-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 8 748 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 749 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 750 // CHECK1-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8 751 // CHECK1-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 8 752 // CHECK1-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 8 753 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 8 754 // CHECK1-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 8 755 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 8 756 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2 757 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32 758 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 759 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 760 // CHECK1-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2 761 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8 762 // CHECK1-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00 763 // CHECK1-NEXT: store double [[ADD2]], double* [[TMP1]], align 8 764 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4 765 // CHECK1-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double 766 // CHECK1-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 767 // CHECK1-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float 768 // CHECK1-NEXT: store float [[CONV5]], float* [[TMP2]], align 4 769 // CHECK1-NEXT: ret void 770 // 771 // 772 // CHECK1-LABEL: define {{[^@]+}}@_Z5tbar2ssss 773 // CHECK1-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] { 774 // CHECK1-NEXT: entry: 775 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 776 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 777 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 778 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 779 // CHECK1-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 780 // CHECK1-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 781 // CHECK1-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 782 // CHECK1-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 783 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2 784 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2 785 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2 786 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 787 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 noundef signext [[TMP0]], i16 noundef signext [[TMP1]], i16 noundef signext [[TMP2]], i16 noundef signext [[TMP3]]) 788 // CHECK1-NEXT: ret i32 [[CALL]] 789 // 790 // 791 // CHECK1-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_ 792 // CHECK1-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] comdat { 793 // CHECK1-NEXT: entry: 794 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 795 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 796 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 797 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 798 // CHECK1-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 799 // CHECK1-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 800 // CHECK1-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 801 // CHECK1-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 802 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, i16*, i16*, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i16* [[A_ADDR]], i16* [[B_ADDR]], i16* [[C_ADDR]], i16* [[D_ADDR]]) 803 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2 804 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 805 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2 806 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 807 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]] 808 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2 809 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 810 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]] 811 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 812 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP3]] to i32 813 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]] 814 // CHECK1-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4 815 // CHECK1-NEXT: [[CONV6:%.*]] = fptosi float [[TMP4]] to i32 816 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]] 817 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 818 // CHECK1-NEXT: [[CONV8:%.*]] = fptosi float [[TMP5]] to i32 819 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]] 820 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4 821 // CHECK1-NEXT: [[CONV10:%.*]] = fptosi float [[TMP6]] to i32 822 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]] 823 // CHECK1-NEXT: [[TMP7:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 824 // CHECK1-NEXT: [[CONV12:%.*]] = fptosi float [[TMP7]] to i32 825 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]] 826 // CHECK1-NEXT: ret i32 [[ADD13]] 827 // 828 // 829 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 830 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { 831 // CHECK1-NEXT: entry: 832 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 833 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 834 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16*, align 8 835 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16*, align 8 836 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 837 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8 838 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 839 // CHECK1-NEXT: [[GB_CASTED:%.*]] = alloca i64, align 8 840 // CHECK1-NEXT: [[SB_CASTED:%.*]] = alloca i64, align 8 841 // CHECK1-NEXT: [[GC_CASTED:%.*]] = alloca i64, align 8 842 // CHECK1-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 843 // CHECK1-NEXT: [[SC_CASTED:%.*]] = alloca i64, align 8 844 // CHECK1-NEXT: [[D_CASTED:%.*]] = alloca i64, align 8 845 // CHECK1-NEXT: [[GD_CASTED:%.*]] = alloca i64, align 8 846 // CHECK1-NEXT: [[SD_CASTED:%.*]] = alloca i64, align 8 847 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 8 848 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 8 849 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 8 850 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 851 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 852 // CHECK1-NEXT: store i16* [[A]], i16** [[A_ADDR]], align 8 853 // CHECK1-NEXT: store i16* [[B]], i16** [[B_ADDR]], align 8 854 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 855 // CHECK1-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8 856 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[A_ADDR]], align 8 857 // CHECK1-NEXT: [[TMP1:%.*]] = load i16*, i16** [[B_ADDR]], align 8 858 // CHECK1-NEXT: [[TMP2:%.*]] = load i16*, i16** [[C_ADDR]], align 8 859 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[D_ADDR]], align 8 860 // CHECK1-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2 861 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i16* 862 // CHECK1-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2 863 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 864 // CHECK1-NEXT: [[TMP6:%.*]] = load double, double* @Gb, align 8 865 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_CASTED]] to double* 866 // CHECK1-NEXT: store double [[TMP6]], double* [[CONV1]], align 8 867 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[GB_CASTED]], align 8 868 // CHECK1-NEXT: [[TMP8:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 869 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_CASTED]] to float* 870 // CHECK1-NEXT: store float [[TMP8]], float* [[CONV2]], align 4 871 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[SB_CASTED]], align 8 872 // CHECK1-NEXT: [[TMP10:%.*]] = load double, double* @Gc, align 8 873 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_CASTED]] to double* 874 // CHECK1-NEXT: store double [[TMP10]], double* [[CONV3]], align 8 875 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[GC_CASTED]], align 8 876 // CHECK1-NEXT: [[TMP12:%.*]] = load i16, i16* [[TMP2]], align 2 877 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_CASTED]] to i16* 878 // CHECK1-NEXT: store i16 [[TMP12]], i16* [[CONV4]], align 2 879 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[C_CASTED]], align 8 880 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4 881 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_CASTED]] to float* 882 // CHECK1-NEXT: store float [[TMP14]], float* [[CONV5]], align 4 883 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[SC_CASTED]], align 8 884 // CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[TMP3]], align 2 885 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_CASTED]] to i16* 886 // CHECK1-NEXT: store i16 [[TMP16]], i16* [[CONV6]], align 2 887 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[D_CASTED]], align 8 888 // CHECK1-NEXT: [[TMP18:%.*]] = load double, double* @Gd, align 8 889 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_CASTED]] to double* 890 // CHECK1-NEXT: store double [[TMP18]], double* [[CONV7]], align 8 891 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[GD_CASTED]], align 8 892 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 893 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_CASTED]] to float* 894 // CHECK1-NEXT: store float [[TMP20]], float* [[CONV8]], align 4 895 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SD_CASTED]], align 8 896 // CHECK1-NEXT: [[TMP22:%.*]] = load double, double* @Ga, align 8 897 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP22]], 0.000000e+00 898 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] 899 // CHECK1: land.lhs.true: 900 // CHECK1-NEXT: [[TMP23:%.*]] = load i16, i16* [[TMP0]], align 2 901 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP23]] to i32 902 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[CONV9]], 0 903 // CHECK1-NEXT: br i1 [[CMP10]], label [[LAND_LHS_TRUE11:%.*]], label [[OMP_IF_ELSE]] 904 // CHECK1: land.lhs.true11: 905 // CHECK1-NEXT: [[TMP24:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4 906 // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP24]] to double 907 // CHECK1-NEXT: [[CMP13:%.*]] = fcmp ogt double [[CONV12]], 0.000000e+00 908 // CHECK1-NEXT: br i1 [[CMP13]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] 909 // CHECK1: omp_if.then: 910 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 911 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 912 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP26]], align 8 913 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 914 // CHECK1-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 915 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP28]], align 8 916 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 917 // CHECK1-NEXT: store i8* null, i8** [[TMP29]], align 8 918 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 919 // CHECK1-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 920 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP31]], align 8 921 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 922 // CHECK1-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* 923 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP33]], align 8 924 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 925 // CHECK1-NEXT: store i8* null, i8** [[TMP34]], align 8 926 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 927 // CHECK1-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64* 928 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP36]], align 8 929 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 930 // CHECK1-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64* 931 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 932 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 933 // CHECK1-NEXT: store i8* null, i8** [[TMP39]], align 8 934 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 935 // CHECK1-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* 936 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[TMP41]], align 8 937 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 938 // CHECK1-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* 939 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[TMP43]], align 8 940 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 941 // CHECK1-NEXT: store i8* null, i8** [[TMP44]], align 8 942 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 943 // CHECK1-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* 944 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[TMP46]], align 8 945 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 946 // CHECK1-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64* 947 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[TMP48]], align 8 948 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 949 // CHECK1-NEXT: store i8* null, i8** [[TMP49]], align 8 950 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 951 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64* 952 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP51]], align 8 953 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 954 // CHECK1-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64* 955 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP53]], align 8 956 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 957 // CHECK1-NEXT: store i8* null, i8** [[TMP54]], align 8 958 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 959 // CHECK1-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i64* 960 // CHECK1-NEXT: store i64 [[TMP17]], i64* [[TMP56]], align 8 961 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 962 // CHECK1-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i64* 963 // CHECK1-NEXT: store i64 [[TMP17]], i64* [[TMP58]], align 8 964 // CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 965 // CHECK1-NEXT: store i8* null, i8** [[TMP59]], align 8 966 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 967 // CHECK1-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i64* 968 // CHECK1-NEXT: store i64 [[TMP19]], i64* [[TMP61]], align 8 969 // CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 970 // CHECK1-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i64* 971 // CHECK1-NEXT: store i64 [[TMP19]], i64* [[TMP63]], align 8 972 // CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 973 // CHECK1-NEXT: store i8* null, i8** [[TMP64]], align 8 974 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 975 // CHECK1-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to i64* 976 // CHECK1-NEXT: store i64 [[TMP21]], i64* [[TMP66]], align 8 977 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 978 // CHECK1-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i64* 979 // CHECK1-NEXT: store i64 [[TMP21]], i64* [[TMP68]], align 8 980 // CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8 981 // CHECK1-NEXT: store i8* null, i8** [[TMP69]], align 8 982 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 983 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 984 // CHECK1-NEXT: [[TMP72:%.*]] = call i32 @__tgt_target_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145.region_id, i32 9, i8** [[TMP70]], i8** [[TMP71]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null) 985 // CHECK1-NEXT: [[TMP73:%.*]] = icmp ne i32 [[TMP72]], 0 986 // CHECK1-NEXT: br i1 [[TMP73]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 987 // CHECK1: omp_offload.failed: 988 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]] 989 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 990 // CHECK1: omp_offload.cont: 991 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 992 // CHECK1: omp_if.else: 993 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]] 994 // CHECK1-NEXT: br label [[OMP_IF_END]] 995 // CHECK1: omp_if.end: 996 // CHECK1-NEXT: ret void 997 // 998 // 999 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145 1000 // CHECK1-SAME: (i64 noundef [[B:%.*]], i64 noundef [[GB:%.*]], i64 noundef [[SB:%.*]], i64 noundef [[GC:%.*]], i64 noundef [[C:%.*]], i64 noundef [[SC:%.*]], i64 noundef [[D:%.*]], i64 noundef [[GD:%.*]], i64 noundef [[SD:%.*]]) #[[ATTR1]] { 1001 // CHECK1-NEXT: entry: 1002 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1003 // CHECK1-NEXT: [[GB_ADDR:%.*]] = alloca i64, align 8 1004 // CHECK1-NEXT: [[SB_ADDR:%.*]] = alloca i64, align 8 1005 // CHECK1-NEXT: [[GC_ADDR:%.*]] = alloca i64, align 8 1006 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 1007 // CHECK1-NEXT: [[SC_ADDR:%.*]] = alloca i64, align 8 1008 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i64, align 8 1009 // CHECK1-NEXT: [[GD_ADDR:%.*]] = alloca i64, align 8 1010 // CHECK1-NEXT: [[SD_ADDR:%.*]] = alloca i64, align 8 1011 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 1012 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 1013 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1014 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1015 // CHECK1-NEXT: store i64 [[GB]], i64* [[GB_ADDR]], align 8 1016 // CHECK1-NEXT: store i64 [[SB]], i64* [[SB_ADDR]], align 8 1017 // CHECK1-NEXT: store i64 [[GC]], i64* [[GC_ADDR]], align 8 1018 // CHECK1-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 1019 // CHECK1-NEXT: store i64 [[SC]], i64* [[SC_ADDR]], align 8 1020 // CHECK1-NEXT: store i64 [[D]], i64* [[D_ADDR]], align 8 1021 // CHECK1-NEXT: store i64 [[GD]], i64* [[GD_ADDR]], align 8 1022 // CHECK1-NEXT: store i64 [[SD]], i64* [[SD_ADDR]], align 8 1023 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i16* 1024 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double* 1025 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float* 1026 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double* 1027 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16* 1028 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float* 1029 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16* 1030 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double* 1031 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float* 1032 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 1033 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32 1034 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1 1035 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 1036 // CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2 1037 // CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8 1038 // CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00 1039 // CHECK1-NEXT: store double [[ADD11]], double* [[CONV1]], align 8 1040 // CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 4 1041 // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double 1042 // CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00 1043 // CHECK1-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float 1044 // CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 4 1045 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8 1046 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00 1047 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] 1048 // CHECK1: land.lhs.true: 1049 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 2 1050 // CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32 1051 // CHECK1-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0 1052 // CHECK1-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]] 1053 // CHECK1: land.lhs.true17: 1054 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 4 1055 // CHECK1-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double 1056 // CHECK1-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00 1057 // CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] 1058 // CHECK1: omp_if.then: 1059 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) 1060 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1061 // CHECK1: omp_if.else: 1062 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1063 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 1064 // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 1065 // CHECK1-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) #[[ATTR2]] 1066 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1067 // CHECK1-NEXT: br label [[OMP_IF_END]] 1068 // CHECK1: omp_if.end: 1069 // CHECK1-NEXT: ret void 1070 // 1071 // 1072 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 1073 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { 1074 // CHECK1-NEXT: entry: 1075 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1076 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1077 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8 1078 // CHECK1-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 8 1079 // CHECK1-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 8 1080 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1081 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1082 // CHECK1-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8 1083 // CHECK1-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 8 1084 // CHECK1-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 8 1085 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 8 1086 // CHECK1-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 8 1087 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 8 1088 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2 1089 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32 1090 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 1091 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 1092 // CHECK1-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2 1093 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8 1094 // CHECK1-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00 1095 // CHECK1-NEXT: store double [[ADD2]], double* [[TMP1]], align 8 1096 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4 1097 // CHECK1-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double 1098 // CHECK1-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 1099 // CHECK1-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float 1100 // CHECK1-NEXT: store float [[CONV5]], float* [[TMP2]], align 4 1101 // CHECK1-NEXT: ret void 1102 // 1103 // 1104 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1105 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 1106 // CHECK1-NEXT: entry: 1107 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1108 // CHECK1-NEXT: ret void 1109 // 1110 // 1111 // CHECK3-LABEL: define {{[^@]+}}@_Z3foossss 1112 // CHECK3-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0:[0-9]+]] { 1113 // CHECK3-NEXT: entry: 1114 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 1115 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 1116 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 1117 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 1118 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1119 // CHECK3-NEXT: [[SB_CASTED:%.*]] = alloca i32, align 4 1120 // CHECK3-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4 1121 // CHECK3-NEXT: [[SC_CASTED:%.*]] = alloca i32, align 4 1122 // CHECK3-NEXT: [[D_CASTED:%.*]] = alloca i32, align 4 1123 // CHECK3-NEXT: [[SD_CASTED:%.*]] = alloca i32, align 4 1124 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 4 1125 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 4 1126 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 4 1127 // CHECK3-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 1128 // CHECK3-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 1129 // CHECK3-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 1130 // CHECK3-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 1131 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 1132 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* 1133 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2 1134 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_CASTED]], align 4 1135 // CHECK3-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 1136 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_CASTED]] to float* 1137 // CHECK3-NEXT: store float [[TMP2]], float* [[CONV1]], align 4 1138 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[SB_CASTED]], align 4 1139 // CHECK3-NEXT: [[TMP4:%.*]] = load i16, i16* [[C_ADDR]], align 2 1140 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_CASTED]] to i16* 1141 // CHECK3-NEXT: store i16 [[TMP4]], i16* [[CONV2]], align 2 1142 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[C_CASTED]], align 4 1143 // CHECK3-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4 1144 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_CASTED]] to float* 1145 // CHECK3-NEXT: store float [[TMP6]], float* [[CONV3]], align 4 1146 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[SC_CASTED]], align 4 1147 // CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[D_ADDR]], align 2 1148 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_CASTED]] to i16* 1149 // CHECK3-NEXT: store i16 [[TMP8]], i16* [[CONV4]], align 2 1150 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[D_CASTED]], align 4 1151 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 1152 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_CASTED]] to float* 1153 // CHECK3-NEXT: store float [[TMP10]], float* [[CONV5]], align 4 1154 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[SD_CASTED]], align 4 1155 // CHECK3-NEXT: [[TMP12:%.*]] = load double, double* @Ga, align 8 1156 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP12]], 0.000000e+00 1157 // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] 1158 // CHECK3: land.lhs.true: 1159 // CHECK3-NEXT: [[TMP13:%.*]] = load i16, i16* [[A_ADDR]], align 2 1160 // CHECK3-NEXT: [[CONV6:%.*]] = sext i16 [[TMP13]] to i32 1161 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[CONV6]], 0 1162 // CHECK3-NEXT: br i1 [[CMP7]], label [[LAND_LHS_TRUE8:%.*]], label [[OMP_IF_ELSE]] 1163 // CHECK3: land.lhs.true8: 1164 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4 1165 // CHECK3-NEXT: [[CONV9:%.*]] = fpext float [[TMP14]] to double 1166 // CHECK3-NEXT: [[CMP10:%.*]] = fcmp ogt double [[CONV9]], 0.000000e+00 1167 // CHECK3-NEXT: br i1 [[CMP10]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] 1168 // CHECK3: omp_if.then: 1169 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1170 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 1171 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP16]], align 4 1172 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1173 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 1174 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP18]], align 4 1175 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1176 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 1177 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1178 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to double** 1179 // CHECK3-NEXT: store double* @Gb, double** [[TMP21]], align 4 1180 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1181 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to double** 1182 // CHECK3-NEXT: store double* @Gb, double** [[TMP23]], align 4 1183 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1184 // CHECK3-NEXT: store i8* null, i8** [[TMP24]], align 4 1185 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1186 // CHECK3-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 1187 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP26]], align 4 1188 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1189 // CHECK3-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 1190 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP28]], align 4 1191 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1192 // CHECK3-NEXT: store i8* null, i8** [[TMP29]], align 4 1193 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1194 // CHECK3-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to double** 1195 // CHECK3-NEXT: store double* @Gc, double** [[TMP31]], align 4 1196 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1197 // CHECK3-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** 1198 // CHECK3-NEXT: store double* @Gc, double** [[TMP33]], align 4 1199 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1200 // CHECK3-NEXT: store i8* null, i8** [[TMP34]], align 4 1201 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1202 // CHECK3-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32* 1203 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP36]], align 4 1204 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1205 // CHECK3-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* 1206 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP38]], align 4 1207 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1208 // CHECK3-NEXT: store i8* null, i8** [[TMP39]], align 4 1209 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 1210 // CHECK3-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* 1211 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP41]], align 4 1212 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 1213 // CHECK3-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i32* 1214 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP43]], align 4 1215 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 1216 // CHECK3-NEXT: store i8* null, i8** [[TMP44]], align 4 1217 // CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 1218 // CHECK3-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* 1219 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[TMP46]], align 4 1220 // CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 1221 // CHECK3-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i32* 1222 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[TMP48]], align 4 1223 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 1224 // CHECK3-NEXT: store i8* null, i8** [[TMP49]], align 4 1225 // CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 1226 // CHECK3-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double** 1227 // CHECK3-NEXT: store double* @Gd, double** [[TMP51]], align 4 1228 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 1229 // CHECK3-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double** 1230 // CHECK3-NEXT: store double* @Gd, double** [[TMP53]], align 4 1231 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 1232 // CHECK3-NEXT: store i8* null, i8** [[TMP54]], align 4 1233 // CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 1234 // CHECK3-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32* 1235 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[TMP56]], align 4 1236 // CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 1237 // CHECK3-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i32* 1238 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[TMP58]], align 4 1239 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8 1240 // CHECK3-NEXT: store i8* null, i8** [[TMP59]], align 4 1241 // CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1242 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1243 // CHECK3-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49.region_id, i32 9, i8** [[TMP60]], i8** [[TMP61]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null) 1244 // CHECK3-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 1245 // CHECK3-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1246 // CHECK3: omp_offload.failed: 1247 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i32 [[TMP1]], double* @Gb, i32 [[TMP3]], double* @Gc, i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP9]], double* @Gd, i32 [[TMP11]]) #[[ATTR2:[0-9]+]] 1248 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1249 // CHECK3: omp_offload.cont: 1250 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 1251 // CHECK3: omp_if.else: 1252 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i32 [[TMP1]], double* @Gb, i32 [[TMP3]], double* @Gc, i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP9]], double* @Gd, i32 [[TMP11]]) #[[ATTR2]] 1253 // CHECK3-NEXT: br label [[OMP_IF_END]] 1254 // CHECK3: omp_if.end: 1255 // CHECK3-NEXT: [[TMP64:%.*]] = load i16, i16* [[A_ADDR]], align 2 1256 // CHECK3-NEXT: [[CONV11:%.*]] = sext i16 [[TMP64]] to i32 1257 // CHECK3-NEXT: [[TMP65:%.*]] = load i16, i16* [[B_ADDR]], align 2 1258 // CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP65]] to i32 1259 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV11]], [[CONV12]] 1260 // CHECK3-NEXT: [[TMP66:%.*]] = load i16, i16* [[C_ADDR]], align 2 1261 // CHECK3-NEXT: [[CONV13:%.*]] = sext i16 [[TMP66]] to i32 1262 // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CONV13]] 1263 // CHECK3-NEXT: [[TMP67:%.*]] = load i16, i16* [[D_ADDR]], align 2 1264 // CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP67]] to i32 1265 // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD14]], [[CONV15]] 1266 // CHECK3-NEXT: [[TMP68:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4 1267 // CHECK3-NEXT: [[CONV17:%.*]] = fptosi float [[TMP68]] to i32 1268 // CHECK3-NEXT: [[ADD18:%.*]] = add nsw i32 [[ADD16]], [[CONV17]] 1269 // CHECK3-NEXT: [[TMP69:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 1270 // CHECK3-NEXT: [[CONV19:%.*]] = fptosi float [[TMP69]] to i32 1271 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i32 [[ADD18]], [[CONV19]] 1272 // CHECK3-NEXT: [[TMP70:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4 1273 // CHECK3-NEXT: [[CONV21:%.*]] = fptosi float [[TMP70]] to i32 1274 // CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[ADD20]], [[CONV21]] 1275 // CHECK3-NEXT: [[TMP71:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 1276 // CHECK3-NEXT: [[CONV23:%.*]] = fptosi float [[TMP71]] to i32 1277 // CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[ADD22]], [[CONV23]] 1278 // CHECK3-NEXT: ret i32 [[ADD24]] 1279 // 1280 // 1281 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49 1282 // CHECK3-SAME: (i32 noundef [[B:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 noundef [[SB:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 noundef [[C:%.*]], i32 noundef [[SC:%.*]], i32 noundef [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 noundef [[SD:%.*]]) #[[ATTR1:[0-9]+]] { 1283 // CHECK3-NEXT: entry: 1284 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1285 // CHECK3-NEXT: [[GB_ADDR:%.*]] = alloca double*, align 4 1286 // CHECK3-NEXT: [[SB_ADDR:%.*]] = alloca i32, align 4 1287 // CHECK3-NEXT: [[GC_ADDR:%.*]] = alloca double*, align 4 1288 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 1289 // CHECK3-NEXT: [[SC_ADDR:%.*]] = alloca i32, align 4 1290 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32, align 4 1291 // CHECK3-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4 1292 // CHECK3-NEXT: [[SD_ADDR:%.*]] = alloca i32, align 4 1293 // CHECK3-NEXT: [[GB6:%.*]] = alloca double, align 8 1294 // CHECK3-NEXT: [[GC7:%.*]] = alloca double, align 8 1295 // CHECK3-NEXT: [[GD8:%.*]] = alloca double, align 8 1296 // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 1297 // CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 1298 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1299 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1300 // CHECK3-NEXT: store double* [[GB]], double** [[GB_ADDR]], align 4 1301 // CHECK3-NEXT: store i32 [[SB]], i32* [[SB_ADDR]], align 4 1302 // CHECK3-NEXT: store double* [[GC]], double** [[GC_ADDR]], align 4 1303 // CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 1304 // CHECK3-NEXT: store i32 [[SC]], i32* [[SC_ADDR]], align 4 1305 // CHECK3-NEXT: store i32 [[D]], i32* [[D_ADDR]], align 4 1306 // CHECK3-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4 1307 // CHECK3-NEXT: store i32 [[SD]], i32* [[SD_ADDR]], align 4 1308 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 1309 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[GB_ADDR]], align 4 1310 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_ADDR]] to float* 1311 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[GC_ADDR]], align 4 1312 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_ADDR]] to i16* 1313 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_ADDR]] to float* 1314 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_ADDR]] to i16* 1315 // CHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4 1316 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float* 1317 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8 1318 // CHECK3-NEXT: store double [[TMP4]], double* [[GB6]], align 8 1319 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8 1320 // CHECK3-NEXT: store double [[TMP5]], double* [[GC7]], align 8 1321 // CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8 1322 // CHECK3-NEXT: store double [[TMP6]], double* [[GD8]], align 8 1323 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2 1324 // CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32 1325 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1 1326 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 1327 // CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2 1328 // CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8 1329 // CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00 1330 // CHECK3-NEXT: store double [[ADD11]], double* [[GB6]], align 8 1331 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4 1332 // CHECK3-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double 1333 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00 1334 // CHECK3-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float 1335 // CHECK3-NEXT: store float [[CONV14]], float* [[CONV1]], align 4 1336 // CHECK3-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8 1337 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00 1338 // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] 1339 // CHECK3: land.lhs.true: 1340 // CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 2 1341 // CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32 1342 // CHECK3-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0 1343 // CHECK3-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]] 1344 // CHECK3: land.lhs.true17: 1345 // CHECK3-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4 1346 // CHECK3-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double 1347 // CHECK3-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00 1348 // CHECK3-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] 1349 // CHECK3: omp_if.then: 1350 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined. to void (i32*, i32*, ...)*), i16* [[CONV4]], double* [[GD8]], float* [[CONV5]]) 1351 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 1352 // CHECK3: omp_if.else: 1353 // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1354 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 1355 // CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 1356 // CHECK3-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV4]], double* [[GD8]], float* [[CONV5]]) #[[ATTR2]] 1357 // CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1358 // CHECK3-NEXT: br label [[OMP_IF_END]] 1359 // CHECK3: omp_if.end: 1360 // CHECK3-NEXT: ret void 1361 // 1362 // 1363 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1364 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { 1365 // CHECK3-NEXT: entry: 1366 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1367 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1368 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4 1369 // CHECK3-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4 1370 // CHECK3-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 4 1371 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1372 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1373 // CHECK3-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4 1374 // CHECK3-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4 1375 // CHECK3-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 4 1376 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 4 1377 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 4 1378 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 4 1379 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2 1380 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32 1381 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 1382 // CHECK3-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 1383 // CHECK3-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2 1384 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8 1385 // CHECK3-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00 1386 // CHECK3-NEXT: store double [[ADD2]], double* [[TMP1]], align 8 1387 // CHECK3-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4 1388 // CHECK3-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double 1389 // CHECK3-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 1390 // CHECK3-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float 1391 // CHECK3-NEXT: store float [[CONV5]], float* [[TMP2]], align 4 1392 // CHECK3-NEXT: ret void 1393 // 1394 // 1395 // CHECK3-LABEL: define {{[^@]+}}@_Z3barssss 1396 // CHECK3-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] { 1397 // CHECK3-NEXT: entry: 1398 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 1399 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 1400 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 1401 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 1402 // CHECK3-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 1403 // CHECK3-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 1404 // CHECK3-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 1405 // CHECK3-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 1406 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, i16*, i16*, i16*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i16* [[A_ADDR]], i16* [[B_ADDR]], i16* [[C_ADDR]], i16* [[D_ADDR]]) 1407 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2 1408 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 1409 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2 1410 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 1411 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]] 1412 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2 1413 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 1414 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]] 1415 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 1416 // CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP3]] to i32 1417 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]] 1418 // CHECK3-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4 1419 // CHECK3-NEXT: [[CONV6:%.*]] = fptosi float [[TMP4]] to i32 1420 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]] 1421 // CHECK3-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 1422 // CHECK3-NEXT: [[CONV8:%.*]] = fptosi float [[TMP5]] to i32 1423 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]] 1424 // CHECK3-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4 1425 // CHECK3-NEXT: [[CONV10:%.*]] = fptosi float [[TMP6]] to i32 1426 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]] 1427 // CHECK3-NEXT: [[TMP7:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 1428 // CHECK3-NEXT: [[CONV12:%.*]] = fptosi float [[TMP7]] to i32 1429 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]] 1430 // CHECK3-NEXT: ret i32 [[ADD13]] 1431 // 1432 // 1433 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 1434 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { 1435 // CHECK3-NEXT: entry: 1436 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1437 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1438 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16*, align 4 1439 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16*, align 4 1440 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 1441 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4 1442 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1443 // CHECK3-NEXT: [[SB_CASTED:%.*]] = alloca i32, align 4 1444 // CHECK3-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4 1445 // CHECK3-NEXT: [[SC_CASTED:%.*]] = alloca i32, align 4 1446 // CHECK3-NEXT: [[D_CASTED:%.*]] = alloca i32, align 4 1447 // CHECK3-NEXT: [[SD_CASTED:%.*]] = alloca i32, align 4 1448 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 4 1449 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 4 1450 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 4 1451 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1452 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1453 // CHECK3-NEXT: store i16* [[A]], i16** [[A_ADDR]], align 4 1454 // CHECK3-NEXT: store i16* [[B]], i16** [[B_ADDR]], align 4 1455 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 1456 // CHECK3-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4 1457 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[A_ADDR]], align 4 1458 // CHECK3-NEXT: [[TMP1:%.*]] = load i16*, i16** [[B_ADDR]], align 4 1459 // CHECK3-NEXT: [[TMP2:%.*]] = load i16*, i16** [[C_ADDR]], align 4 1460 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[D_ADDR]], align 4 1461 // CHECK3-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2 1462 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* 1463 // CHECK3-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2 1464 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 1465 // CHECK3-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 1466 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_CASTED]] to float* 1467 // CHECK3-NEXT: store float [[TMP6]], float* [[CONV1]], align 4 1468 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[SB_CASTED]], align 4 1469 // CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[TMP2]], align 2 1470 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_CASTED]] to i16* 1471 // CHECK3-NEXT: store i16 [[TMP8]], i16* [[CONV2]], align 2 1472 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[C_CASTED]], align 4 1473 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4 1474 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_CASTED]] to float* 1475 // CHECK3-NEXT: store float [[TMP10]], float* [[CONV3]], align 4 1476 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[SC_CASTED]], align 4 1477 // CHECK3-NEXT: [[TMP12:%.*]] = load i16, i16* [[TMP3]], align 2 1478 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_CASTED]] to i16* 1479 // CHECK3-NEXT: store i16 [[TMP12]], i16* [[CONV4]], align 2 1480 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[D_CASTED]], align 4 1481 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 1482 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_CASTED]] to float* 1483 // CHECK3-NEXT: store float [[TMP14]], float* [[CONV5]], align 4 1484 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[SD_CASTED]], align 4 1485 // CHECK3-NEXT: [[TMP16:%.*]] = load double, double* @Ga, align 8 1486 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP16]], 0.000000e+00 1487 // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] 1488 // CHECK3: land.lhs.true: 1489 // CHECK3-NEXT: [[TMP17:%.*]] = load i16, i16* [[TMP0]], align 2 1490 // CHECK3-NEXT: [[CONV6:%.*]] = sext i16 [[TMP17]] to i32 1491 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[CONV6]], 0 1492 // CHECK3-NEXT: br i1 [[CMP7]], label [[LAND_LHS_TRUE8:%.*]], label [[OMP_IF_ELSE]] 1493 // CHECK3: land.lhs.true8: 1494 // CHECK3-NEXT: [[TMP18:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4 1495 // CHECK3-NEXT: [[CONV9:%.*]] = fpext float [[TMP18]] to double 1496 // CHECK3-NEXT: [[CMP10:%.*]] = fcmp ogt double [[CONV9]], 0.000000e+00 1497 // CHECK3-NEXT: br i1 [[CMP10]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] 1498 // CHECK3: omp_if.then: 1499 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1500 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 1501 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 1502 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1503 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 1504 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP22]], align 4 1505 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1506 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1507 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1508 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to double** 1509 // CHECK3-NEXT: store double* @Gb, double** [[TMP25]], align 4 1510 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1511 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to double** 1512 // CHECK3-NEXT: store double* @Gb, double** [[TMP27]], align 4 1513 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1514 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4 1515 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1516 // CHECK3-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 1517 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP30]], align 4 1518 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1519 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* 1520 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP32]], align 4 1521 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1522 // CHECK3-NEXT: store i8* null, i8** [[TMP33]], align 4 1523 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1524 // CHECK3-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to double** 1525 // CHECK3-NEXT: store double* @Gc, double** [[TMP35]], align 4 1526 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1527 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to double** 1528 // CHECK3-NEXT: store double* @Gc, double** [[TMP37]], align 4 1529 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1530 // CHECK3-NEXT: store i8* null, i8** [[TMP38]], align 4 1531 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1532 // CHECK3-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* 1533 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[TMP40]], align 4 1534 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1535 // CHECK3-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32* 1536 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[TMP42]], align 4 1537 // CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1538 // CHECK3-NEXT: store i8* null, i8** [[TMP43]], align 4 1539 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 1540 // CHECK3-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i32* 1541 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[TMP45]], align 4 1542 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 1543 // CHECK3-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32* 1544 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[TMP47]], align 4 1545 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 1546 // CHECK3-NEXT: store i8* null, i8** [[TMP48]], align 4 1547 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 1548 // CHECK3-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32* 1549 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[TMP50]], align 4 1550 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 1551 // CHECK3-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32* 1552 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[TMP52]], align 4 1553 // CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 1554 // CHECK3-NEXT: store i8* null, i8** [[TMP53]], align 4 1555 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 1556 // CHECK3-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to double** 1557 // CHECK3-NEXT: store double* @Gd, double** [[TMP55]], align 4 1558 // CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 1559 // CHECK3-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to double** 1560 // CHECK3-NEXT: store double* @Gd, double** [[TMP57]], align 4 1561 // CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 1562 // CHECK3-NEXT: store i8* null, i8** [[TMP58]], align 4 1563 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 1564 // CHECK3-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* 1565 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[TMP60]], align 4 1566 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 1567 // CHECK3-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 1568 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[TMP62]], align 4 1569 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8 1570 // CHECK3-NEXT: store i8* null, i8** [[TMP63]], align 4 1571 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1572 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1573 // CHECK3-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94.region_id, i32 9, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes.3, i32 0, i32 0), i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null) 1574 // CHECK3-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 1575 // CHECK3-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1576 // CHECK3: omp_offload.failed: 1577 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i32 [[TMP5]], double* @Gb, i32 [[TMP7]], double* @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], double* @Gd, i32 [[TMP15]]) #[[ATTR2]] 1578 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1579 // CHECK3: omp_offload.cont: 1580 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 1581 // CHECK3: omp_if.else: 1582 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i32 [[TMP5]], double* @Gb, i32 [[TMP7]], double* @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], double* @Gd, i32 [[TMP15]]) #[[ATTR2]] 1583 // CHECK3-NEXT: br label [[OMP_IF_END]] 1584 // CHECK3: omp_if.end: 1585 // CHECK3-NEXT: ret void 1586 // 1587 // 1588 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94 1589 // CHECK3-SAME: (i32 noundef [[B:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 noundef [[SB:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 noundef [[C:%.*]], i32 noundef [[SC:%.*]], i32 noundef [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 noundef [[SD:%.*]]) #[[ATTR1]] { 1590 // CHECK3-NEXT: entry: 1591 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1592 // CHECK3-NEXT: [[GB_ADDR:%.*]] = alloca double*, align 4 1593 // CHECK3-NEXT: [[SB_ADDR:%.*]] = alloca i32, align 4 1594 // CHECK3-NEXT: [[GC_ADDR:%.*]] = alloca double*, align 4 1595 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 1596 // CHECK3-NEXT: [[SC_ADDR:%.*]] = alloca i32, align 4 1597 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32, align 4 1598 // CHECK3-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4 1599 // CHECK3-NEXT: [[SD_ADDR:%.*]] = alloca i32, align 4 1600 // CHECK3-NEXT: [[GB6:%.*]] = alloca double, align 8 1601 // CHECK3-NEXT: [[GC7:%.*]] = alloca double, align 8 1602 // CHECK3-NEXT: [[GD8:%.*]] = alloca double, align 8 1603 // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 1604 // CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 1605 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1606 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1607 // CHECK3-NEXT: store double* [[GB]], double** [[GB_ADDR]], align 4 1608 // CHECK3-NEXT: store i32 [[SB]], i32* [[SB_ADDR]], align 4 1609 // CHECK3-NEXT: store double* [[GC]], double** [[GC_ADDR]], align 4 1610 // CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 1611 // CHECK3-NEXT: store i32 [[SC]], i32* [[SC_ADDR]], align 4 1612 // CHECK3-NEXT: store i32 [[D]], i32* [[D_ADDR]], align 4 1613 // CHECK3-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4 1614 // CHECK3-NEXT: store i32 [[SD]], i32* [[SD_ADDR]], align 4 1615 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 1616 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[GB_ADDR]], align 4 1617 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_ADDR]] to float* 1618 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[GC_ADDR]], align 4 1619 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_ADDR]] to i16* 1620 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_ADDR]] to float* 1621 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_ADDR]] to i16* 1622 // CHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4 1623 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float* 1624 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8 1625 // CHECK3-NEXT: store double [[TMP4]], double* [[GB6]], align 8 1626 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8 1627 // CHECK3-NEXT: store double [[TMP5]], double* [[GC7]], align 8 1628 // CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8 1629 // CHECK3-NEXT: store double [[TMP6]], double* [[GD8]], align 8 1630 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2 1631 // CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32 1632 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1 1633 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 1634 // CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2 1635 // CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8 1636 // CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00 1637 // CHECK3-NEXT: store double [[ADD11]], double* [[GB6]], align 8 1638 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4 1639 // CHECK3-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double 1640 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00 1641 // CHECK3-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float 1642 // CHECK3-NEXT: store float [[CONV14]], float* [[CONV1]], align 4 1643 // CHECK3-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8 1644 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00 1645 // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] 1646 // CHECK3: land.lhs.true: 1647 // CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 2 1648 // CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32 1649 // CHECK3-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0 1650 // CHECK3-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]] 1651 // CHECK3: land.lhs.true17: 1652 // CHECK3-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4 1653 // CHECK3-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double 1654 // CHECK3-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00 1655 // CHECK3-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] 1656 // CHECK3: omp_if.then: 1657 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i16* [[CONV4]], double* [[GD8]], float* [[CONV5]]) 1658 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 1659 // CHECK3: omp_if.else: 1660 // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1661 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 1662 // CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 1663 // CHECK3-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV4]], double* [[GD8]], float* [[CONV5]]) #[[ATTR2]] 1664 // CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1665 // CHECK3-NEXT: br label [[OMP_IF_END]] 1666 // CHECK3: omp_if.end: 1667 // CHECK3-NEXT: ret void 1668 // 1669 // 1670 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 1671 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { 1672 // CHECK3-NEXT: entry: 1673 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1674 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1675 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4 1676 // CHECK3-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4 1677 // CHECK3-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 4 1678 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1679 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1680 // CHECK3-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4 1681 // CHECK3-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4 1682 // CHECK3-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 4 1683 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 4 1684 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 4 1685 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 4 1686 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2 1687 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32 1688 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 1689 // CHECK3-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 1690 // CHECK3-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2 1691 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8 1692 // CHECK3-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00 1693 // CHECK3-NEXT: store double [[ADD2]], double* [[TMP1]], align 8 1694 // CHECK3-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4 1695 // CHECK3-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double 1696 // CHECK3-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 1697 // CHECK3-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float 1698 // CHECK3-NEXT: store float [[CONV5]], float* [[TMP2]], align 4 1699 // CHECK3-NEXT: ret void 1700 // 1701 // 1702 // CHECK3-LABEL: define {{[^@]+}}@_Z5tbar2ssss 1703 // CHECK3-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] { 1704 // CHECK3-NEXT: entry: 1705 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 1706 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 1707 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 1708 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 1709 // CHECK3-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 1710 // CHECK3-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 1711 // CHECK3-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 1712 // CHECK3-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 1713 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2 1714 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2 1715 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2 1716 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 1717 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 noundef signext [[TMP0]], i16 noundef signext [[TMP1]], i16 noundef signext [[TMP2]], i16 noundef signext [[TMP3]]) 1718 // CHECK3-NEXT: ret i32 [[CALL]] 1719 // 1720 // 1721 // CHECK3-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_ 1722 // CHECK3-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] comdat { 1723 // CHECK3-NEXT: entry: 1724 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 1725 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 1726 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 1727 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 1728 // CHECK3-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 1729 // CHECK3-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 1730 // CHECK3-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 1731 // CHECK3-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 1732 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, i16*, i16*, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i16* [[A_ADDR]], i16* [[B_ADDR]], i16* [[C_ADDR]], i16* [[D_ADDR]]) 1733 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2 1734 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 1735 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2 1736 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 1737 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]] 1738 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2 1739 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 1740 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]] 1741 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 1742 // CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP3]] to i32 1743 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]] 1744 // CHECK3-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4 1745 // CHECK3-NEXT: [[CONV6:%.*]] = fptosi float [[TMP4]] to i32 1746 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]] 1747 // CHECK3-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 1748 // CHECK3-NEXT: [[CONV8:%.*]] = fptosi float [[TMP5]] to i32 1749 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]] 1750 // CHECK3-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4 1751 // CHECK3-NEXT: [[CONV10:%.*]] = fptosi float [[TMP6]] to i32 1752 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]] 1753 // CHECK3-NEXT: [[TMP7:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 1754 // CHECK3-NEXT: [[CONV12:%.*]] = fptosi float [[TMP7]] to i32 1755 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]] 1756 // CHECK3-NEXT: ret i32 [[ADD13]] 1757 // 1758 // 1759 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 1760 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { 1761 // CHECK3-NEXT: entry: 1762 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1763 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1764 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16*, align 4 1765 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16*, align 4 1766 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 1767 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4 1768 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1769 // CHECK3-NEXT: [[SB_CASTED:%.*]] = alloca i32, align 4 1770 // CHECK3-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4 1771 // CHECK3-NEXT: [[SC_CASTED:%.*]] = alloca i32, align 4 1772 // CHECK3-NEXT: [[D_CASTED:%.*]] = alloca i32, align 4 1773 // CHECK3-NEXT: [[SD_CASTED:%.*]] = alloca i32, align 4 1774 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 4 1775 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 4 1776 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 4 1777 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1778 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1779 // CHECK3-NEXT: store i16* [[A]], i16** [[A_ADDR]], align 4 1780 // CHECK3-NEXT: store i16* [[B]], i16** [[B_ADDR]], align 4 1781 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 1782 // CHECK3-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4 1783 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[A_ADDR]], align 4 1784 // CHECK3-NEXT: [[TMP1:%.*]] = load i16*, i16** [[B_ADDR]], align 4 1785 // CHECK3-NEXT: [[TMP2:%.*]] = load i16*, i16** [[C_ADDR]], align 4 1786 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[D_ADDR]], align 4 1787 // CHECK3-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2 1788 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* 1789 // CHECK3-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2 1790 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 1791 // CHECK3-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 1792 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_CASTED]] to float* 1793 // CHECK3-NEXT: store float [[TMP6]], float* [[CONV1]], align 4 1794 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[SB_CASTED]], align 4 1795 // CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[TMP2]], align 2 1796 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_CASTED]] to i16* 1797 // CHECK3-NEXT: store i16 [[TMP8]], i16* [[CONV2]], align 2 1798 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[C_CASTED]], align 4 1799 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4 1800 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_CASTED]] to float* 1801 // CHECK3-NEXT: store float [[TMP10]], float* [[CONV3]], align 4 1802 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[SC_CASTED]], align 4 1803 // CHECK3-NEXT: [[TMP12:%.*]] = load i16, i16* [[TMP3]], align 2 1804 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_CASTED]] to i16* 1805 // CHECK3-NEXT: store i16 [[TMP12]], i16* [[CONV4]], align 2 1806 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[D_CASTED]], align 4 1807 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 1808 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_CASTED]] to float* 1809 // CHECK3-NEXT: store float [[TMP14]], float* [[CONV5]], align 4 1810 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[SD_CASTED]], align 4 1811 // CHECK3-NEXT: [[TMP16:%.*]] = load double, double* @Ga, align 8 1812 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP16]], 0.000000e+00 1813 // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] 1814 // CHECK3: land.lhs.true: 1815 // CHECK3-NEXT: [[TMP17:%.*]] = load i16, i16* [[TMP0]], align 2 1816 // CHECK3-NEXT: [[CONV6:%.*]] = sext i16 [[TMP17]] to i32 1817 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[CONV6]], 0 1818 // CHECK3-NEXT: br i1 [[CMP7]], label [[LAND_LHS_TRUE8:%.*]], label [[OMP_IF_ELSE]] 1819 // CHECK3: land.lhs.true8: 1820 // CHECK3-NEXT: [[TMP18:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4 1821 // CHECK3-NEXT: [[CONV9:%.*]] = fpext float [[TMP18]] to double 1822 // CHECK3-NEXT: [[CMP10:%.*]] = fcmp ogt double [[CONV9]], 0.000000e+00 1823 // CHECK3-NEXT: br i1 [[CMP10]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] 1824 // CHECK3: omp_if.then: 1825 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1826 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 1827 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 1828 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1829 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 1830 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP22]], align 4 1831 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1832 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1833 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1834 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to double** 1835 // CHECK3-NEXT: store double* @Gb, double** [[TMP25]], align 4 1836 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1837 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to double** 1838 // CHECK3-NEXT: store double* @Gb, double** [[TMP27]], align 4 1839 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1840 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4 1841 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1842 // CHECK3-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 1843 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP30]], align 4 1844 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1845 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* 1846 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP32]], align 4 1847 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1848 // CHECK3-NEXT: store i8* null, i8** [[TMP33]], align 4 1849 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1850 // CHECK3-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to double** 1851 // CHECK3-NEXT: store double* @Gc, double** [[TMP35]], align 4 1852 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1853 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to double** 1854 // CHECK3-NEXT: store double* @Gc, double** [[TMP37]], align 4 1855 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1856 // CHECK3-NEXT: store i8* null, i8** [[TMP38]], align 4 1857 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1858 // CHECK3-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* 1859 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[TMP40]], align 4 1860 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1861 // CHECK3-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32* 1862 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[TMP42]], align 4 1863 // CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1864 // CHECK3-NEXT: store i8* null, i8** [[TMP43]], align 4 1865 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 1866 // CHECK3-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i32* 1867 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[TMP45]], align 4 1868 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 1869 // CHECK3-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32* 1870 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[TMP47]], align 4 1871 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 1872 // CHECK3-NEXT: store i8* null, i8** [[TMP48]], align 4 1873 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 1874 // CHECK3-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32* 1875 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[TMP50]], align 4 1876 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 1877 // CHECK3-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32* 1878 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[TMP52]], align 4 1879 // CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 1880 // CHECK3-NEXT: store i8* null, i8** [[TMP53]], align 4 1881 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 1882 // CHECK3-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to double** 1883 // CHECK3-NEXT: store double* @Gd, double** [[TMP55]], align 4 1884 // CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 1885 // CHECK3-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to double** 1886 // CHECK3-NEXT: store double* @Gd, double** [[TMP57]], align 4 1887 // CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 1888 // CHECK3-NEXT: store i8* null, i8** [[TMP58]], align 4 1889 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 1890 // CHECK3-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* 1891 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[TMP60]], align 4 1892 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 1893 // CHECK3-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 1894 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[TMP62]], align 4 1895 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8 1896 // CHECK3-NEXT: store i8* null, i8** [[TMP63]], align 4 1897 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1898 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1899 // CHECK3-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145.region_id, i32 9, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null) 1900 // CHECK3-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 1901 // CHECK3-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1902 // CHECK3: omp_offload.failed: 1903 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i32 [[TMP5]], double* @Gb, i32 [[TMP7]], double* @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], double* @Gd, i32 [[TMP15]]) #[[ATTR2]] 1904 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1905 // CHECK3: omp_offload.cont: 1906 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 1907 // CHECK3: omp_if.else: 1908 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i32 [[TMP5]], double* @Gb, i32 [[TMP7]], double* @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], double* @Gd, i32 [[TMP15]]) #[[ATTR2]] 1909 // CHECK3-NEXT: br label [[OMP_IF_END]] 1910 // CHECK3: omp_if.end: 1911 // CHECK3-NEXT: ret void 1912 // 1913 // 1914 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145 1915 // CHECK3-SAME: (i32 noundef [[B:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 noundef [[SB:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 noundef [[C:%.*]], i32 noundef [[SC:%.*]], i32 noundef [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 noundef [[SD:%.*]]) #[[ATTR1]] { 1916 // CHECK3-NEXT: entry: 1917 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1918 // CHECK3-NEXT: [[GB_ADDR:%.*]] = alloca double*, align 4 1919 // CHECK3-NEXT: [[SB_ADDR:%.*]] = alloca i32, align 4 1920 // CHECK3-NEXT: [[GC_ADDR:%.*]] = alloca double*, align 4 1921 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 1922 // CHECK3-NEXT: [[SC_ADDR:%.*]] = alloca i32, align 4 1923 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32, align 4 1924 // CHECK3-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4 1925 // CHECK3-NEXT: [[SD_ADDR:%.*]] = alloca i32, align 4 1926 // CHECK3-NEXT: [[GB6:%.*]] = alloca double, align 8 1927 // CHECK3-NEXT: [[GC7:%.*]] = alloca double, align 8 1928 // CHECK3-NEXT: [[GD8:%.*]] = alloca double, align 8 1929 // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 1930 // CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 1931 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1932 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1933 // CHECK3-NEXT: store double* [[GB]], double** [[GB_ADDR]], align 4 1934 // CHECK3-NEXT: store i32 [[SB]], i32* [[SB_ADDR]], align 4 1935 // CHECK3-NEXT: store double* [[GC]], double** [[GC_ADDR]], align 4 1936 // CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 1937 // CHECK3-NEXT: store i32 [[SC]], i32* [[SC_ADDR]], align 4 1938 // CHECK3-NEXT: store i32 [[D]], i32* [[D_ADDR]], align 4 1939 // CHECK3-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4 1940 // CHECK3-NEXT: store i32 [[SD]], i32* [[SD_ADDR]], align 4 1941 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 1942 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[GB_ADDR]], align 4 1943 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_ADDR]] to float* 1944 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[GC_ADDR]], align 4 1945 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_ADDR]] to i16* 1946 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_ADDR]] to float* 1947 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_ADDR]] to i16* 1948 // CHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4 1949 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float* 1950 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8 1951 // CHECK3-NEXT: store double [[TMP4]], double* [[GB6]], align 8 1952 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8 1953 // CHECK3-NEXT: store double [[TMP5]], double* [[GC7]], align 8 1954 // CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8 1955 // CHECK3-NEXT: store double [[TMP6]], double* [[GD8]], align 8 1956 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2 1957 // CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32 1958 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1 1959 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 1960 // CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2 1961 // CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8 1962 // CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00 1963 // CHECK3-NEXT: store double [[ADD11]], double* [[GB6]], align 8 1964 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4 1965 // CHECK3-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double 1966 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00 1967 // CHECK3-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float 1968 // CHECK3-NEXT: store float [[CONV14]], float* [[CONV1]], align 4 1969 // CHECK3-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8 1970 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00 1971 // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] 1972 // CHECK3: land.lhs.true: 1973 // CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 2 1974 // CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32 1975 // CHECK3-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0 1976 // CHECK3-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]] 1977 // CHECK3: land.lhs.true17: 1978 // CHECK3-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4 1979 // CHECK3-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double 1980 // CHECK3-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00 1981 // CHECK3-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] 1982 // CHECK3: omp_if.then: 1983 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i16* [[CONV4]], double* [[GD8]], float* [[CONV5]]) 1984 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 1985 // CHECK3: omp_if.else: 1986 // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1987 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 1988 // CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 1989 // CHECK3-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV4]], double* [[GD8]], float* [[CONV5]]) #[[ATTR2]] 1990 // CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1991 // CHECK3-NEXT: br label [[OMP_IF_END]] 1992 // CHECK3: omp_if.end: 1993 // CHECK3-NEXT: ret void 1994 // 1995 // 1996 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 1997 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { 1998 // CHECK3-NEXT: entry: 1999 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2000 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2001 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4 2002 // CHECK3-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4 2003 // CHECK3-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 4 2004 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2005 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2006 // CHECK3-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4 2007 // CHECK3-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4 2008 // CHECK3-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 4 2009 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 4 2010 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 4 2011 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 4 2012 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2 2013 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32 2014 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 2015 // CHECK3-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 2016 // CHECK3-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2 2017 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8 2018 // CHECK3-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00 2019 // CHECK3-NEXT: store double [[ADD2]], double* [[TMP1]], align 8 2020 // CHECK3-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4 2021 // CHECK3-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double 2022 // CHECK3-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 2023 // CHECK3-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float 2024 // CHECK3-NEXT: store float [[CONV5]], float* [[TMP2]], align 4 2025 // CHECK3-NEXT: ret void 2026 // 2027 // 2028 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2029 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 2030 // CHECK3-NEXT: entry: 2031 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 2032 // CHECK3-NEXT: ret void 2033 // 2034