1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
8
9 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
10 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
12 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
13 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
15 // expected-no-diagnostics
16 #ifndef HEADER
17 #define HEADER
18
19
20
21 double Ga = 1.0;
22 double Gb = 2.0;
23 double Gc = 3.0;
24 double Gd = 4.0;
25
foo(short a,short b,short c,short d)26 int foo(short a, short b, short c, short d){
27 static float Sa = 5.0;
28 static float Sb = 6.0;
29 static float Sc = 7.0;
30 static float Sd = 8.0;
31
32
33 // 3 local vars being captured.
34
35
36
37
38 // 3 static vars being captured.
39
40
41
42
43 // 3 static global vars being captured.
44
45
46
47
48 // Capture b, Gb, Sb, Gc, c, Sc, d, Gd, Sd
49 #pragma omp target if(Ga>0.0 && a>0 && Sa>0.0)
50 {
51 b += 1;
52 Gb += 1.0;
53 Sb += 1.0;
54
55 // The parallel region only uses 3 captures.
56 // Capture d, Gd, Sd,
57
58 #pragma omp parallel if(Gc>0.0 && c>0 && Sc>0.0)
59 {
60 d += 1;
61 Gd += 1.0;
62 Sd += 1.0;
63 }
64 }
65 return a + b + c + d + (int)Sa + (int)Sb + (int)Sc + (int)Sd;
66 }
67
bar(short a,short b,short c,short d)68 int bar(short a, short b, short c, short d){
69 static float Sa = 9.0;
70 static float Sb = 10.0;
71 static float Sc = 11.0;
72 static float Sd = 12.0;
73
74 // Capture a, b, c, d
75 #pragma omp parallel
76 {
77
78 // 3 local vars being captured.
79
80
81
82
83 // 3 static vars being captured.
84
85
86
87
88 // 3 static global vars being captured.
89
90
91
92
93 // Capture b, Gb, Sb, Gc, c, Sc, d, Gd, Sd
94 #pragma omp target if(Ga>0.0 && a>0 && Sa>0.0)
95 {
96 b += 1;
97 Gb += 1.0;
98 Sb += 1.0;
99
100
101 // Capture d, Gd, Sd
102 #pragma omp parallel if(Gc>0.0 && c>0 && Sc>0.0)
103 {
104 d += 1;
105 Gd += 1.0;
106 Sd += 1.0;
107 }
108 }
109 }
110 return a + b + c + d + (int)Sa + (int)Sb + (int)Sc + (int)Sd;
111 }
112
113 ///
114 /// Tests with template functions.
115 ///
116
117
118 template<typename T>
tbar(T a,T b,T c,T d)119 int tbar(T a, T b, T c, T d){
120 static float Sa = 17.0;
121 static float Sb = 18.0;
122 static float Sc = 19.0;
123 static float Sd = 20.0;
124
125 // Capture a, b, c, d
126 #pragma omp parallel
127 {
128
129 // 3 local vars being captured.
130
131
132
133
134 // 3 static vars being captured.
135
136
137
138
139 // 3 static global vars being captured.
140
141
142
143
144 // Capture b, Gb, Sb, Gc, c, Sc, d, Gd, Sd
145 #pragma omp target if(Ga>0.0 && a>0 && Sa>0.0)
146 {
147 b += 1;
148 Gb += 1.0;
149 Sb += 1.0;
150
151
152 // Capture d, Gd, Sd
153 #pragma omp parallel if(Gc>0.0 && c>0 && Sc>0.0)
154 {
155 d += 1;
156 Gd += 1.0;
157 Sd += 1.0;
158 }
159 }
160 }
161 return a + b + c + d + (int)Sa + (int)Sb + (int)Sc + (int)Sd;
162 }
163
tbar2(short a,short b,short c,short d)164 int tbar2(short a, short b, short c, short d){
165 return tbar(a, b, c, d);
166 }
167
168 #endif
169 // CHECK1-LABEL: define {{[^@]+}}@_Z3foossss
170 // CHECK1-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0:[0-9]+]] {
171 // CHECK1-NEXT: entry:
172 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
173 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
174 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
175 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
176 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
177 // CHECK1-NEXT: [[GB_CASTED:%.*]] = alloca i64, align 8
178 // CHECK1-NEXT: [[SB_CASTED:%.*]] = alloca i64, align 8
179 // CHECK1-NEXT: [[GC_CASTED:%.*]] = alloca i64, align 8
180 // CHECK1-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8
181 // CHECK1-NEXT: [[SC_CASTED:%.*]] = alloca i64, align 8
182 // CHECK1-NEXT: [[D_CASTED:%.*]] = alloca i64, align 8
183 // CHECK1-NEXT: [[GD_CASTED:%.*]] = alloca i64, align 8
184 // CHECK1-NEXT: [[SD_CASTED:%.*]] = alloca i64, align 8
185 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 8
186 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 8
187 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 8
188 // CHECK1-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
189 // CHECK1-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
190 // CHECK1-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
191 // CHECK1-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
192 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2
193 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i16*
194 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2
195 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_CASTED]], align 8
196 // CHECK1-NEXT: [[TMP2:%.*]] = load double, double* @Gb, align 8
197 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_CASTED]] to double*
198 // CHECK1-NEXT: store double [[TMP2]], double* [[CONV1]], align 8
199 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[GB_CASTED]], align 8
200 // CHECK1-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4
201 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_CASTED]] to float*
202 // CHECK1-NEXT: store float [[TMP4]], float* [[CONV2]], align 4
203 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[SB_CASTED]], align 8
204 // CHECK1-NEXT: [[TMP6:%.*]] = load double, double* @Gc, align 8
205 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_CASTED]] to double*
206 // CHECK1-NEXT: store double [[TMP6]], double* [[CONV3]], align 8
207 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[GC_CASTED]], align 8
208 // CHECK1-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2
209 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_CASTED]] to i16*
210 // CHECK1-NEXT: store i16 [[TMP8]], i16* [[CONV4]], align 2
211 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8
212 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4
213 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_CASTED]] to float*
214 // CHECK1-NEXT: store float [[TMP10]], float* [[CONV5]], align 4
215 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[SC_CASTED]], align 8
216 // CHECK1-NEXT: [[TMP12:%.*]] = load i16, i16* [[D_ADDR]], align 2
217 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_CASTED]] to i16*
218 // CHECK1-NEXT: store i16 [[TMP12]], i16* [[CONV6]], align 2
219 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[D_CASTED]], align 8
220 // CHECK1-NEXT: [[TMP14:%.*]] = load double, double* @Gd, align 8
221 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_CASTED]] to double*
222 // CHECK1-NEXT: store double [[TMP14]], double* [[CONV7]], align 8
223 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[GD_CASTED]], align 8
224 // CHECK1-NEXT: [[TMP16:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4
225 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_CASTED]] to float*
226 // CHECK1-NEXT: store float [[TMP16]], float* [[CONV8]], align 4
227 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[SD_CASTED]], align 8
228 // CHECK1-NEXT: [[TMP18:%.*]] = load double, double* @Ga, align 8
229 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP18]], 0.000000e+00
230 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
231 // CHECK1: land.lhs.true:
232 // CHECK1-NEXT: [[TMP19:%.*]] = load i16, i16* [[A_ADDR]], align 2
233 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP19]] to i32
234 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[CONV9]], 0
235 // CHECK1-NEXT: br i1 [[CMP10]], label [[LAND_LHS_TRUE11:%.*]], label [[OMP_IF_ELSE]]
236 // CHECK1: land.lhs.true11:
237 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4
238 // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP20]] to double
239 // CHECK1-NEXT: [[CMP13:%.*]] = fcmp ogt double [[CONV12]], 0.000000e+00
240 // CHECK1-NEXT: br i1 [[CMP13]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
241 // CHECK1: omp_if.then:
242 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
243 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
244 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP22]], align 8
245 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
246 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
247 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP24]], align 8
248 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
249 // CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8
250 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
251 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
252 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8
253 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
254 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
255 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP29]], align 8
256 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
257 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8
258 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
259 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
260 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP32]], align 8
261 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
262 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
263 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP34]], align 8
264 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
265 // CHECK1-NEXT: store i8* null, i8** [[TMP35]], align 8
266 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
267 // CHECK1-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64*
268 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP37]], align 8
269 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
270 // CHECK1-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64*
271 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP39]], align 8
272 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
273 // CHECK1-NEXT: store i8* null, i8** [[TMP40]], align 8
274 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
275 // CHECK1-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i64*
276 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP42]], align 8
277 // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
278 // CHECK1-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i64*
279 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP44]], align 8
280 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
281 // CHECK1-NEXT: store i8* null, i8** [[TMP45]], align 8
282 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
283 // CHECK1-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i64*
284 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[TMP47]], align 8
285 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
286 // CHECK1-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i64*
287 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[TMP49]], align 8
288 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
289 // CHECK1-NEXT: store i8* null, i8** [[TMP50]], align 8
290 // CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
291 // CHECK1-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64*
292 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[TMP52]], align 8
293 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6
294 // CHECK1-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i64*
295 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[TMP54]], align 8
296 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6
297 // CHECK1-NEXT: store i8* null, i8** [[TMP55]], align 8
298 // CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
299 // CHECK1-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to i64*
300 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP57]], align 8
301 // CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7
302 // CHECK1-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to i64*
303 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP59]], align 8
304 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7
305 // CHECK1-NEXT: store i8* null, i8** [[TMP60]], align 8
306 // CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
307 // CHECK1-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
308 // CHECK1-NEXT: store i64 [[TMP17]], i64* [[TMP62]], align 8
309 // CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8
310 // CHECK1-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
311 // CHECK1-NEXT: store i64 [[TMP17]], i64* [[TMP64]], align 8
312 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8
313 // CHECK1-NEXT: store i8* null, i8** [[TMP65]], align 8
314 // CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
315 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
316 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
317 // CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
318 // CHECK1-NEXT: store i32 1, i32* [[TMP68]], align 4
319 // CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
320 // CHECK1-NEXT: store i32 9, i32* [[TMP69]], align 4
321 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
322 // CHECK1-NEXT: store i8** [[TMP66]], i8*** [[TMP70]], align 8
323 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
324 // CHECK1-NEXT: store i8** [[TMP67]], i8*** [[TMP71]], align 8
325 // CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
326 // CHECK1-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP72]], align 8
327 // CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
328 // CHECK1-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP73]], align 8
329 // CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
330 // CHECK1-NEXT: store i8** null, i8*** [[TMP74]], align 8
331 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
332 // CHECK1-NEXT: store i8** null, i8*** [[TMP75]], align 8
333 // CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
334 // CHECK1-NEXT: store i64 0, i64* [[TMP76]], align 8
335 // CHECK1-NEXT: [[TMP77:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
336 // CHECK1-NEXT: [[TMP78:%.*]] = icmp ne i32 [[TMP77]], 0
337 // CHECK1-NEXT: br i1 [[TMP78]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
338 // CHECK1: omp_offload.failed:
339 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]]) #[[ATTR2:[0-9]+]]
340 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
341 // CHECK1: omp_offload.cont:
342 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
343 // CHECK1: omp_if.else:
344 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]]) #[[ATTR2]]
345 // CHECK1-NEXT: br label [[OMP_IF_END]]
346 // CHECK1: omp_if.end:
347 // CHECK1-NEXT: [[TMP79:%.*]] = load i16, i16* [[A_ADDR]], align 2
348 // CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP79]] to i32
349 // CHECK1-NEXT: [[TMP80:%.*]] = load i16, i16* [[B_ADDR]], align 2
350 // CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP80]] to i32
351 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV14]], [[CONV15]]
352 // CHECK1-NEXT: [[TMP81:%.*]] = load i16, i16* [[C_ADDR]], align 2
353 // CHECK1-NEXT: [[CONV16:%.*]] = sext i16 [[TMP81]] to i32
354 // CHECK1-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD]], [[CONV16]]
355 // CHECK1-NEXT: [[TMP82:%.*]] = load i16, i16* [[D_ADDR]], align 2
356 // CHECK1-NEXT: [[CONV18:%.*]] = sext i16 [[TMP82]] to i32
357 // CHECK1-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]]
358 // CHECK1-NEXT: [[TMP83:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4
359 // CHECK1-NEXT: [[CONV20:%.*]] = fptosi float [[TMP83]] to i32
360 // CHECK1-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]]
361 // CHECK1-NEXT: [[TMP84:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4
362 // CHECK1-NEXT: [[CONV22:%.*]] = fptosi float [[TMP84]] to i32
363 // CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]]
364 // CHECK1-NEXT: [[TMP85:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4
365 // CHECK1-NEXT: [[CONV24:%.*]] = fptosi float [[TMP85]] to i32
366 // CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]]
367 // CHECK1-NEXT: [[TMP86:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4
368 // CHECK1-NEXT: [[CONV26:%.*]] = fptosi float [[TMP86]] to i32
369 // CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]]
370 // CHECK1-NEXT: ret i32 [[ADD27]]
371 //
372 //
373 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49
374 // CHECK1-SAME: (i64 noundef [[B:%.*]], i64 noundef [[GB:%.*]], i64 noundef [[SB:%.*]], i64 noundef [[GC:%.*]], i64 noundef [[C:%.*]], i64 noundef [[SC:%.*]], i64 noundef [[D:%.*]], i64 noundef [[GD:%.*]], i64 noundef [[SD:%.*]]) #[[ATTR1:[0-9]+]] {
375 // CHECK1-NEXT: entry:
376 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
377 // CHECK1-NEXT: [[GB_ADDR:%.*]] = alloca i64, align 8
378 // CHECK1-NEXT: [[SB_ADDR:%.*]] = alloca i64, align 8
379 // CHECK1-NEXT: [[GC_ADDR:%.*]] = alloca i64, align 8
380 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8
381 // CHECK1-NEXT: [[SC_ADDR:%.*]] = alloca i64, align 8
382 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i64, align 8
383 // CHECK1-NEXT: [[GD_ADDR:%.*]] = alloca i64, align 8
384 // CHECK1-NEXT: [[SD_ADDR:%.*]] = alloca i64, align 8
385 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
386 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
387 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
388 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
389 // CHECK1-NEXT: store i64 [[GB]], i64* [[GB_ADDR]], align 8
390 // CHECK1-NEXT: store i64 [[SB]], i64* [[SB_ADDR]], align 8
391 // CHECK1-NEXT: store i64 [[GC]], i64* [[GC_ADDR]], align 8
392 // CHECK1-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8
393 // CHECK1-NEXT: store i64 [[SC]], i64* [[SC_ADDR]], align 8
394 // CHECK1-NEXT: store i64 [[D]], i64* [[D_ADDR]], align 8
395 // CHECK1-NEXT: store i64 [[GD]], i64* [[GD_ADDR]], align 8
396 // CHECK1-NEXT: store i64 [[SD]], i64* [[SD_ADDR]], align 8
397 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i16*
398 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double*
399 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float*
400 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double*
401 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16*
402 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float*
403 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
404 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
405 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
406 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
407 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
408 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
409 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
410 // CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
411 // CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
412 // CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
413 // CHECK1-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
414 // CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 4
415 // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
416 // CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
417 // CHECK1-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
418 // CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 4
419 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
420 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
421 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
422 // CHECK1: land.lhs.true:
423 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 2
424 // CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
425 // CHECK1-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
426 // CHECK1-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
427 // CHECK1: land.lhs.true17:
428 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 4
429 // CHECK1-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
430 // CHECK1-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
431 // CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
432 // CHECK1: omp_if.then:
433 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined. to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]])
434 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
435 // CHECK1: omp_if.else:
436 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
437 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
438 // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
439 // CHECK1-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) #[[ATTR2]]
440 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
441 // CHECK1-NEXT: br label [[OMP_IF_END]]
442 // CHECK1: omp_if.end:
443 // CHECK1-NEXT: ret void
444 //
445 //
446 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
447 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
448 // CHECK1-NEXT: entry:
449 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
450 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
451 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8
452 // CHECK1-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 8
453 // CHECK1-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 8
454 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
455 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
456 // CHECK1-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8
457 // CHECK1-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 8
458 // CHECK1-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 8
459 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 8
460 // CHECK1-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 8
461 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 8
462 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2
463 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32
464 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
465 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
466 // CHECK1-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2
467 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
468 // CHECK1-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
469 // CHECK1-NEXT: store double [[ADD2]], double* [[TMP1]], align 8
470 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4
471 // CHECK1-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double
472 // CHECK1-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
473 // CHECK1-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
474 // CHECK1-NEXT: store float [[CONV5]], float* [[TMP2]], align 4
475 // CHECK1-NEXT: ret void
476 //
477 //
478 // CHECK1-LABEL: define {{[^@]+}}@_Z3barssss
479 // CHECK1-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] {
480 // CHECK1-NEXT: entry:
481 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
482 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
483 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
484 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
485 // CHECK1-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
486 // CHECK1-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
487 // CHECK1-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
488 // CHECK1-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
489 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, i16*, i16*, i16*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i16* [[A_ADDR]], i16* [[B_ADDR]], i16* [[C_ADDR]], i16* [[D_ADDR]])
490 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2
491 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32
492 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2
493 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
494 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]]
495 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2
496 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
497 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]]
498 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2
499 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP3]] to i32
500 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]]
501 // CHECK1-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4
502 // CHECK1-NEXT: [[CONV6:%.*]] = fptosi float [[TMP4]] to i32
503 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]]
504 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4
505 // CHECK1-NEXT: [[CONV8:%.*]] = fptosi float [[TMP5]] to i32
506 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]]
507 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4
508 // CHECK1-NEXT: [[CONV10:%.*]] = fptosi float [[TMP6]] to i32
509 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]]
510 // CHECK1-NEXT: [[TMP7:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4
511 // CHECK1-NEXT: [[CONV12:%.*]] = fptosi float [[TMP7]] to i32
512 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
513 // CHECK1-NEXT: ret i32 [[ADD13]]
514 //
515 //
516 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
517 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] {
518 // CHECK1-NEXT: entry:
519 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
520 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
521 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16*, align 8
522 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16*, align 8
523 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
524 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8
525 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
526 // CHECK1-NEXT: [[GB_CASTED:%.*]] = alloca i64, align 8
527 // CHECK1-NEXT: [[SB_CASTED:%.*]] = alloca i64, align 8
528 // CHECK1-NEXT: [[GC_CASTED:%.*]] = alloca i64, align 8
529 // CHECK1-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8
530 // CHECK1-NEXT: [[SC_CASTED:%.*]] = alloca i64, align 8
531 // CHECK1-NEXT: [[D_CASTED:%.*]] = alloca i64, align 8
532 // CHECK1-NEXT: [[GD_CASTED:%.*]] = alloca i64, align 8
533 // CHECK1-NEXT: [[SD_CASTED:%.*]] = alloca i64, align 8
534 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 8
535 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 8
536 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 8
537 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
538 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
539 // CHECK1-NEXT: store i16* [[A]], i16** [[A_ADDR]], align 8
540 // CHECK1-NEXT: store i16* [[B]], i16** [[B_ADDR]], align 8
541 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
542 // CHECK1-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8
543 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[A_ADDR]], align 8
544 // CHECK1-NEXT: [[TMP1:%.*]] = load i16*, i16** [[B_ADDR]], align 8
545 // CHECK1-NEXT: [[TMP2:%.*]] = load i16*, i16** [[C_ADDR]], align 8
546 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[D_ADDR]], align 8
547 // CHECK1-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
548 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i16*
549 // CHECK1-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2
550 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
551 // CHECK1-NEXT: [[TMP6:%.*]] = load double, double* @Gb, align 8
552 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_CASTED]] to double*
553 // CHECK1-NEXT: store double [[TMP6]], double* [[CONV1]], align 8
554 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[GB_CASTED]], align 8
555 // CHECK1-NEXT: [[TMP8:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4
556 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_CASTED]] to float*
557 // CHECK1-NEXT: store float [[TMP8]], float* [[CONV2]], align 4
558 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[SB_CASTED]], align 8
559 // CHECK1-NEXT: [[TMP10:%.*]] = load double, double* @Gc, align 8
560 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_CASTED]] to double*
561 // CHECK1-NEXT: store double [[TMP10]], double* [[CONV3]], align 8
562 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[GC_CASTED]], align 8
563 // CHECK1-NEXT: [[TMP12:%.*]] = load i16, i16* [[TMP2]], align 2
564 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_CASTED]] to i16*
565 // CHECK1-NEXT: store i16 [[TMP12]], i16* [[CONV4]], align 2
566 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[C_CASTED]], align 8
567 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4
568 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_CASTED]] to float*
569 // CHECK1-NEXT: store float [[TMP14]], float* [[CONV5]], align 4
570 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[SC_CASTED]], align 8
571 // CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[TMP3]], align 2
572 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_CASTED]] to i16*
573 // CHECK1-NEXT: store i16 [[TMP16]], i16* [[CONV6]], align 2
574 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[D_CASTED]], align 8
575 // CHECK1-NEXT: [[TMP18:%.*]] = load double, double* @Gd, align 8
576 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_CASTED]] to double*
577 // CHECK1-NEXT: store double [[TMP18]], double* [[CONV7]], align 8
578 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[GD_CASTED]], align 8
579 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4
580 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_CASTED]] to float*
581 // CHECK1-NEXT: store float [[TMP20]], float* [[CONV8]], align 4
582 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SD_CASTED]], align 8
583 // CHECK1-NEXT: [[TMP22:%.*]] = load double, double* @Ga, align 8
584 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP22]], 0.000000e+00
585 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
586 // CHECK1: land.lhs.true:
587 // CHECK1-NEXT: [[TMP23:%.*]] = load i16, i16* [[TMP0]], align 2
588 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP23]] to i32
589 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[CONV9]], 0
590 // CHECK1-NEXT: br i1 [[CMP10]], label [[LAND_LHS_TRUE11:%.*]], label [[OMP_IF_ELSE]]
591 // CHECK1: land.lhs.true11:
592 // CHECK1-NEXT: [[TMP24:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4
593 // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP24]] to double
594 // CHECK1-NEXT: [[CMP13:%.*]] = fcmp ogt double [[CONV12]], 0.000000e+00
595 // CHECK1-NEXT: br i1 [[CMP13]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
596 // CHECK1: omp_if.then:
597 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
598 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
599 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP26]], align 8
600 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
601 // CHECK1-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
602 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP28]], align 8
603 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
604 // CHECK1-NEXT: store i8* null, i8** [[TMP29]], align 8
605 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
606 // CHECK1-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
607 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP31]], align 8
608 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
609 // CHECK1-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64*
610 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP33]], align 8
611 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
612 // CHECK1-NEXT: store i8* null, i8** [[TMP34]], align 8
613 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
614 // CHECK1-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64*
615 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP36]], align 8
616 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
617 // CHECK1-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64*
618 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8
619 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
620 // CHECK1-NEXT: store i8* null, i8** [[TMP39]], align 8
621 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
622 // CHECK1-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64*
623 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[TMP41]], align 8
624 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
625 // CHECK1-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64*
626 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[TMP43]], align 8
627 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
628 // CHECK1-NEXT: store i8* null, i8** [[TMP44]], align 8
629 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
630 // CHECK1-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
631 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[TMP46]], align 8
632 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
633 // CHECK1-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64*
634 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[TMP48]], align 8
635 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
636 // CHECK1-NEXT: store i8* null, i8** [[TMP49]], align 8
637 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
638 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64*
639 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP51]], align 8
640 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
641 // CHECK1-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64*
642 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP53]], align 8
643 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
644 // CHECK1-NEXT: store i8* null, i8** [[TMP54]], align 8
645 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
646 // CHECK1-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i64*
647 // CHECK1-NEXT: store i64 [[TMP17]], i64* [[TMP56]], align 8
648 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6
649 // CHECK1-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i64*
650 // CHECK1-NEXT: store i64 [[TMP17]], i64* [[TMP58]], align 8
651 // CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6
652 // CHECK1-NEXT: store i8* null, i8** [[TMP59]], align 8
653 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
654 // CHECK1-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i64*
655 // CHECK1-NEXT: store i64 [[TMP19]], i64* [[TMP61]], align 8
656 // CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7
657 // CHECK1-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i64*
658 // CHECK1-NEXT: store i64 [[TMP19]], i64* [[TMP63]], align 8
659 // CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7
660 // CHECK1-NEXT: store i8* null, i8** [[TMP64]], align 8
661 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
662 // CHECK1-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to i64*
663 // CHECK1-NEXT: store i64 [[TMP21]], i64* [[TMP66]], align 8
664 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8
665 // CHECK1-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i64*
666 // CHECK1-NEXT: store i64 [[TMP21]], i64* [[TMP68]], align 8
667 // CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8
668 // CHECK1-NEXT: store i8* null, i8** [[TMP69]], align 8
669 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
670 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
671 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
672 // CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
673 // CHECK1-NEXT: store i32 1, i32* [[TMP72]], align 4
674 // CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
675 // CHECK1-NEXT: store i32 9, i32* [[TMP73]], align 4
676 // CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
677 // CHECK1-NEXT: store i8** [[TMP70]], i8*** [[TMP74]], align 8
678 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
679 // CHECK1-NEXT: store i8** [[TMP71]], i8*** [[TMP75]], align 8
680 // CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
681 // CHECK1-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP76]], align 8
682 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
683 // CHECK1-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP77]], align 8
684 // CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
685 // CHECK1-NEXT: store i8** null, i8*** [[TMP78]], align 8
686 // CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
687 // CHECK1-NEXT: store i8** null, i8*** [[TMP79]], align 8
688 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
689 // CHECK1-NEXT: store i64 0, i64* [[TMP80]], align 8
690 // CHECK1-NEXT: [[TMP81:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
691 // CHECK1-NEXT: [[TMP82:%.*]] = icmp ne i32 [[TMP81]], 0
692 // CHECK1-NEXT: br i1 [[TMP82]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
693 // CHECK1: omp_offload.failed:
694 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]]
695 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
696 // CHECK1: omp_offload.cont:
697 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
698 // CHECK1: omp_if.else:
699 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]]
700 // CHECK1-NEXT: br label [[OMP_IF_END]]
701 // CHECK1: omp_if.end:
702 // CHECK1-NEXT: ret void
703 //
704 //
705 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94
706 // CHECK1-SAME: (i64 noundef [[B:%.*]], i64 noundef [[GB:%.*]], i64 noundef [[SB:%.*]], i64 noundef [[GC:%.*]], i64 noundef [[C:%.*]], i64 noundef [[SC:%.*]], i64 noundef [[D:%.*]], i64 noundef [[GD:%.*]], i64 noundef [[SD:%.*]]) #[[ATTR1]] {
707 // CHECK1-NEXT: entry:
708 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
709 // CHECK1-NEXT: [[GB_ADDR:%.*]] = alloca i64, align 8
710 // CHECK1-NEXT: [[SB_ADDR:%.*]] = alloca i64, align 8
711 // CHECK1-NEXT: [[GC_ADDR:%.*]] = alloca i64, align 8
712 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8
713 // CHECK1-NEXT: [[SC_ADDR:%.*]] = alloca i64, align 8
714 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i64, align 8
715 // CHECK1-NEXT: [[GD_ADDR:%.*]] = alloca i64, align 8
716 // CHECK1-NEXT: [[SD_ADDR:%.*]] = alloca i64, align 8
717 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
718 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
719 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
720 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
721 // CHECK1-NEXT: store i64 [[GB]], i64* [[GB_ADDR]], align 8
722 // CHECK1-NEXT: store i64 [[SB]], i64* [[SB_ADDR]], align 8
723 // CHECK1-NEXT: store i64 [[GC]], i64* [[GC_ADDR]], align 8
724 // CHECK1-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8
725 // CHECK1-NEXT: store i64 [[SC]], i64* [[SC_ADDR]], align 8
726 // CHECK1-NEXT: store i64 [[D]], i64* [[D_ADDR]], align 8
727 // CHECK1-NEXT: store i64 [[GD]], i64* [[GD_ADDR]], align 8
728 // CHECK1-NEXT: store i64 [[SD]], i64* [[SD_ADDR]], align 8
729 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i16*
730 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double*
731 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float*
732 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double*
733 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16*
734 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float*
735 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
736 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
737 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
738 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
739 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
740 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
741 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
742 // CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
743 // CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
744 // CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
745 // CHECK1-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
746 // CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 4
747 // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
748 // CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
749 // CHECK1-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
750 // CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 4
751 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
752 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
753 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
754 // CHECK1: land.lhs.true:
755 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 2
756 // CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
757 // CHECK1-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
758 // CHECK1-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
759 // CHECK1: land.lhs.true17:
760 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 4
761 // CHECK1-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
762 // CHECK1-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
763 // CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
764 // CHECK1: omp_if.then:
765 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]])
766 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
767 // CHECK1: omp_if.else:
768 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
769 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
770 // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
771 // CHECK1-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) #[[ATTR2]]
772 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
773 // CHECK1-NEXT: br label [[OMP_IF_END]]
774 // CHECK1: omp_if.end:
775 // CHECK1-NEXT: ret void
776 //
777 //
778 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
779 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
780 // CHECK1-NEXT: entry:
781 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
782 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
783 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8
784 // CHECK1-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 8
785 // CHECK1-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 8
786 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
787 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
788 // CHECK1-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8
789 // CHECK1-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 8
790 // CHECK1-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 8
791 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 8
792 // CHECK1-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 8
793 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 8
794 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2
795 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32
796 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
797 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
798 // CHECK1-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2
799 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
800 // CHECK1-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
801 // CHECK1-NEXT: store double [[ADD2]], double* [[TMP1]], align 8
802 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4
803 // CHECK1-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double
804 // CHECK1-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
805 // CHECK1-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
806 // CHECK1-NEXT: store float [[CONV5]], float* [[TMP2]], align 4
807 // CHECK1-NEXT: ret void
808 //
809 //
810 // CHECK1-LABEL: define {{[^@]+}}@_Z5tbar2ssss
811 // CHECK1-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] {
812 // CHECK1-NEXT: entry:
813 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
814 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
815 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
816 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
817 // CHECK1-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
818 // CHECK1-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
819 // CHECK1-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
820 // CHECK1-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
821 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2
822 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2
823 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2
824 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2
825 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 noundef signext [[TMP0]], i16 noundef signext [[TMP1]], i16 noundef signext [[TMP2]], i16 noundef signext [[TMP3]])
826 // CHECK1-NEXT: ret i32 [[CALL]]
827 //
828 //
829 // CHECK1-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_
830 // CHECK1-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] comdat {
831 // CHECK1-NEXT: entry:
832 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
833 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
834 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
835 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
836 // CHECK1-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
837 // CHECK1-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
838 // CHECK1-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
839 // CHECK1-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
840 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, i16*, i16*, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i16* [[A_ADDR]], i16* [[B_ADDR]], i16* [[C_ADDR]], i16* [[D_ADDR]])
841 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2
842 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32
843 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2
844 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
845 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]]
846 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2
847 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
848 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]]
849 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2
850 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP3]] to i32
851 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]]
852 // CHECK1-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4
853 // CHECK1-NEXT: [[CONV6:%.*]] = fptosi float [[TMP4]] to i32
854 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]]
855 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4
856 // CHECK1-NEXT: [[CONV8:%.*]] = fptosi float [[TMP5]] to i32
857 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]]
858 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4
859 // CHECK1-NEXT: [[CONV10:%.*]] = fptosi float [[TMP6]] to i32
860 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]]
861 // CHECK1-NEXT: [[TMP7:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4
862 // CHECK1-NEXT: [[CONV12:%.*]] = fptosi float [[TMP7]] to i32
863 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
864 // CHECK1-NEXT: ret i32 [[ADD13]]
865 //
866 //
867 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5
868 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] {
869 // CHECK1-NEXT: entry:
870 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
871 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
872 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16*, align 8
873 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16*, align 8
874 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
875 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8
876 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
877 // CHECK1-NEXT: [[GB_CASTED:%.*]] = alloca i64, align 8
878 // CHECK1-NEXT: [[SB_CASTED:%.*]] = alloca i64, align 8
879 // CHECK1-NEXT: [[GC_CASTED:%.*]] = alloca i64, align 8
880 // CHECK1-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8
881 // CHECK1-NEXT: [[SC_CASTED:%.*]] = alloca i64, align 8
882 // CHECK1-NEXT: [[D_CASTED:%.*]] = alloca i64, align 8
883 // CHECK1-NEXT: [[GD_CASTED:%.*]] = alloca i64, align 8
884 // CHECK1-NEXT: [[SD_CASTED:%.*]] = alloca i64, align 8
885 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 8
886 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 8
887 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 8
888 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
889 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
890 // CHECK1-NEXT: store i16* [[A]], i16** [[A_ADDR]], align 8
891 // CHECK1-NEXT: store i16* [[B]], i16** [[B_ADDR]], align 8
892 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
893 // CHECK1-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8
894 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[A_ADDR]], align 8
895 // CHECK1-NEXT: [[TMP1:%.*]] = load i16*, i16** [[B_ADDR]], align 8
896 // CHECK1-NEXT: [[TMP2:%.*]] = load i16*, i16** [[C_ADDR]], align 8
897 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[D_ADDR]], align 8
898 // CHECK1-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
899 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i16*
900 // CHECK1-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2
901 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
902 // CHECK1-NEXT: [[TMP6:%.*]] = load double, double* @Gb, align 8
903 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_CASTED]] to double*
904 // CHECK1-NEXT: store double [[TMP6]], double* [[CONV1]], align 8
905 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[GB_CASTED]], align 8
906 // CHECK1-NEXT: [[TMP8:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4
907 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_CASTED]] to float*
908 // CHECK1-NEXT: store float [[TMP8]], float* [[CONV2]], align 4
909 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[SB_CASTED]], align 8
910 // CHECK1-NEXT: [[TMP10:%.*]] = load double, double* @Gc, align 8
911 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_CASTED]] to double*
912 // CHECK1-NEXT: store double [[TMP10]], double* [[CONV3]], align 8
913 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[GC_CASTED]], align 8
914 // CHECK1-NEXT: [[TMP12:%.*]] = load i16, i16* [[TMP2]], align 2
915 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_CASTED]] to i16*
916 // CHECK1-NEXT: store i16 [[TMP12]], i16* [[CONV4]], align 2
917 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[C_CASTED]], align 8
918 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4
919 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_CASTED]] to float*
920 // CHECK1-NEXT: store float [[TMP14]], float* [[CONV5]], align 4
921 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[SC_CASTED]], align 8
922 // CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[TMP3]], align 2
923 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_CASTED]] to i16*
924 // CHECK1-NEXT: store i16 [[TMP16]], i16* [[CONV6]], align 2
925 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[D_CASTED]], align 8
926 // CHECK1-NEXT: [[TMP18:%.*]] = load double, double* @Gd, align 8
927 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_CASTED]] to double*
928 // CHECK1-NEXT: store double [[TMP18]], double* [[CONV7]], align 8
929 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[GD_CASTED]], align 8
930 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4
931 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_CASTED]] to float*
932 // CHECK1-NEXT: store float [[TMP20]], float* [[CONV8]], align 4
933 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SD_CASTED]], align 8
934 // CHECK1-NEXT: [[TMP22:%.*]] = load double, double* @Ga, align 8
935 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP22]], 0.000000e+00
936 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
937 // CHECK1: land.lhs.true:
938 // CHECK1-NEXT: [[TMP23:%.*]] = load i16, i16* [[TMP0]], align 2
939 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP23]] to i32
940 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[CONV9]], 0
941 // CHECK1-NEXT: br i1 [[CMP10]], label [[LAND_LHS_TRUE11:%.*]], label [[OMP_IF_ELSE]]
942 // CHECK1: land.lhs.true11:
943 // CHECK1-NEXT: [[TMP24:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4
944 // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP24]] to double
945 // CHECK1-NEXT: [[CMP13:%.*]] = fcmp ogt double [[CONV12]], 0.000000e+00
946 // CHECK1-NEXT: br i1 [[CMP13]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
947 // CHECK1: omp_if.then:
948 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
949 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
950 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP26]], align 8
951 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
952 // CHECK1-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
953 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP28]], align 8
954 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
955 // CHECK1-NEXT: store i8* null, i8** [[TMP29]], align 8
956 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
957 // CHECK1-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
958 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP31]], align 8
959 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
960 // CHECK1-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64*
961 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP33]], align 8
962 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
963 // CHECK1-NEXT: store i8* null, i8** [[TMP34]], align 8
964 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
965 // CHECK1-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64*
966 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP36]], align 8
967 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
968 // CHECK1-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64*
969 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8
970 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
971 // CHECK1-NEXT: store i8* null, i8** [[TMP39]], align 8
972 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
973 // CHECK1-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64*
974 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[TMP41]], align 8
975 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
976 // CHECK1-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64*
977 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[TMP43]], align 8
978 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
979 // CHECK1-NEXT: store i8* null, i8** [[TMP44]], align 8
980 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
981 // CHECK1-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
982 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[TMP46]], align 8
983 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
984 // CHECK1-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64*
985 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[TMP48]], align 8
986 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
987 // CHECK1-NEXT: store i8* null, i8** [[TMP49]], align 8
988 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
989 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64*
990 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP51]], align 8
991 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
992 // CHECK1-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64*
993 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP53]], align 8
994 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
995 // CHECK1-NEXT: store i8* null, i8** [[TMP54]], align 8
996 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
997 // CHECK1-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i64*
998 // CHECK1-NEXT: store i64 [[TMP17]], i64* [[TMP56]], align 8
999 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6
1000 // CHECK1-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i64*
1001 // CHECK1-NEXT: store i64 [[TMP17]], i64* [[TMP58]], align 8
1002 // CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6
1003 // CHECK1-NEXT: store i8* null, i8** [[TMP59]], align 8
1004 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
1005 // CHECK1-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i64*
1006 // CHECK1-NEXT: store i64 [[TMP19]], i64* [[TMP61]], align 8
1007 // CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7
1008 // CHECK1-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i64*
1009 // CHECK1-NEXT: store i64 [[TMP19]], i64* [[TMP63]], align 8
1010 // CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7
1011 // CHECK1-NEXT: store i8* null, i8** [[TMP64]], align 8
1012 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
1013 // CHECK1-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to i64*
1014 // CHECK1-NEXT: store i64 [[TMP21]], i64* [[TMP66]], align 8
1015 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8
1016 // CHECK1-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i64*
1017 // CHECK1-NEXT: store i64 [[TMP21]], i64* [[TMP68]], align 8
1018 // CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8
1019 // CHECK1-NEXT: store i8* null, i8** [[TMP69]], align 8
1020 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1021 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1022 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1023 // CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1024 // CHECK1-NEXT: store i32 1, i32* [[TMP72]], align 4
1025 // CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1026 // CHECK1-NEXT: store i32 9, i32* [[TMP73]], align 4
1027 // CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1028 // CHECK1-NEXT: store i8** [[TMP70]], i8*** [[TMP74]], align 8
1029 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1030 // CHECK1-NEXT: store i8** [[TMP71]], i8*** [[TMP75]], align 8
1031 // CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1032 // CHECK1-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP76]], align 8
1033 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1034 // CHECK1-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP77]], align 8
1035 // CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1036 // CHECK1-NEXT: store i8** null, i8*** [[TMP78]], align 8
1037 // CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1038 // CHECK1-NEXT: store i8** null, i8*** [[TMP79]], align 8
1039 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1040 // CHECK1-NEXT: store i64 0, i64* [[TMP80]], align 8
1041 // CHECK1-NEXT: [[TMP81:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1042 // CHECK1-NEXT: [[TMP82:%.*]] = icmp ne i32 [[TMP81]], 0
1043 // CHECK1-NEXT: br i1 [[TMP82]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1044 // CHECK1: omp_offload.failed:
1045 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]]
1046 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
1047 // CHECK1: omp_offload.cont:
1048 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
1049 // CHECK1: omp_if.else:
1050 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]]
1051 // CHECK1-NEXT: br label [[OMP_IF_END]]
1052 // CHECK1: omp_if.end:
1053 // CHECK1-NEXT: ret void
1054 //
1055 //
1056 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145
1057 // CHECK1-SAME: (i64 noundef [[B:%.*]], i64 noundef [[GB:%.*]], i64 noundef [[SB:%.*]], i64 noundef [[GC:%.*]], i64 noundef [[C:%.*]], i64 noundef [[SC:%.*]], i64 noundef [[D:%.*]], i64 noundef [[GD:%.*]], i64 noundef [[SD:%.*]]) #[[ATTR1]] {
1058 // CHECK1-NEXT: entry:
1059 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
1060 // CHECK1-NEXT: [[GB_ADDR:%.*]] = alloca i64, align 8
1061 // CHECK1-NEXT: [[SB_ADDR:%.*]] = alloca i64, align 8
1062 // CHECK1-NEXT: [[GC_ADDR:%.*]] = alloca i64, align 8
1063 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8
1064 // CHECK1-NEXT: [[SC_ADDR:%.*]] = alloca i64, align 8
1065 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i64, align 8
1066 // CHECK1-NEXT: [[GD_ADDR:%.*]] = alloca i64, align 8
1067 // CHECK1-NEXT: [[SD_ADDR:%.*]] = alloca i64, align 8
1068 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1069 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1070 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1071 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
1072 // CHECK1-NEXT: store i64 [[GB]], i64* [[GB_ADDR]], align 8
1073 // CHECK1-NEXT: store i64 [[SB]], i64* [[SB_ADDR]], align 8
1074 // CHECK1-NEXT: store i64 [[GC]], i64* [[GC_ADDR]], align 8
1075 // CHECK1-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8
1076 // CHECK1-NEXT: store i64 [[SC]], i64* [[SC_ADDR]], align 8
1077 // CHECK1-NEXT: store i64 [[D]], i64* [[D_ADDR]], align 8
1078 // CHECK1-NEXT: store i64 [[GD]], i64* [[GD_ADDR]], align 8
1079 // CHECK1-NEXT: store i64 [[SD]], i64* [[SD_ADDR]], align 8
1080 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i16*
1081 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double*
1082 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float*
1083 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double*
1084 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16*
1085 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float*
1086 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
1087 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
1088 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
1089 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
1090 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
1091 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
1092 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
1093 // CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
1094 // CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
1095 // CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
1096 // CHECK1-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
1097 // CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 4
1098 // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
1099 // CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
1100 // CHECK1-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
1101 // CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 4
1102 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
1103 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
1104 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1105 // CHECK1: land.lhs.true:
1106 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 2
1107 // CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
1108 // CHECK1-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
1109 // CHECK1-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
1110 // CHECK1: land.lhs.true17:
1111 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 4
1112 // CHECK1-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
1113 // CHECK1-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
1114 // CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1115 // CHECK1: omp_if.then:
1116 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]])
1117 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
1118 // CHECK1: omp_if.else:
1119 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1120 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
1121 // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
1122 // CHECK1-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) #[[ATTR2]]
1123 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1124 // CHECK1-NEXT: br label [[OMP_IF_END]]
1125 // CHECK1: omp_if.end:
1126 // CHECK1-NEXT: ret void
1127 //
1128 //
1129 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6
1130 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
1131 // CHECK1-NEXT: entry:
1132 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1133 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1134 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8
1135 // CHECK1-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 8
1136 // CHECK1-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 8
1137 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1138 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1139 // CHECK1-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8
1140 // CHECK1-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 8
1141 // CHECK1-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 8
1142 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 8
1143 // CHECK1-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 8
1144 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 8
1145 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2
1146 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32
1147 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
1148 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
1149 // CHECK1-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2
1150 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
1151 // CHECK1-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
1152 // CHECK1-NEXT: store double [[ADD2]], double* [[TMP1]], align 8
1153 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4
1154 // CHECK1-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double
1155 // CHECK1-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
1156 // CHECK1-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
1157 // CHECK1-NEXT: store float [[CONV5]], float* [[TMP2]], align 4
1158 // CHECK1-NEXT: ret void
1159 //
1160 //
1161 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1162 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
1163 // CHECK1-NEXT: entry:
1164 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
1165 // CHECK1-NEXT: ret void
1166 //
1167 //
1168 // CHECK3-LABEL: define {{[^@]+}}@_Z3foossss
1169 // CHECK3-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0:[0-9]+]] {
1170 // CHECK3-NEXT: entry:
1171 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
1172 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
1173 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
1174 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
1175 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
1176 // CHECK3-NEXT: [[SB_CASTED:%.*]] = alloca i32, align 4
1177 // CHECK3-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4
1178 // CHECK3-NEXT: [[SC_CASTED:%.*]] = alloca i32, align 4
1179 // CHECK3-NEXT: [[D_CASTED:%.*]] = alloca i32, align 4
1180 // CHECK3-NEXT: [[SD_CASTED:%.*]] = alloca i32, align 4
1181 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 4
1182 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 4
1183 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 4
1184 // CHECK3-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
1185 // CHECK3-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
1186 // CHECK3-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
1187 // CHECK3-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
1188 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2
1189 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16*
1190 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2
1191 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_CASTED]], align 4
1192 // CHECK3-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4
1193 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_CASTED]] to float*
1194 // CHECK3-NEXT: store float [[TMP2]], float* [[CONV1]], align 4
1195 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[SB_CASTED]], align 4
1196 // CHECK3-NEXT: [[TMP4:%.*]] = load i16, i16* [[C_ADDR]], align 2
1197 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_CASTED]] to i16*
1198 // CHECK3-NEXT: store i16 [[TMP4]], i16* [[CONV2]], align 2
1199 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[C_CASTED]], align 4
1200 // CHECK3-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4
1201 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_CASTED]] to float*
1202 // CHECK3-NEXT: store float [[TMP6]], float* [[CONV3]], align 4
1203 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[SC_CASTED]], align 4
1204 // CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[D_ADDR]], align 2
1205 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_CASTED]] to i16*
1206 // CHECK3-NEXT: store i16 [[TMP8]], i16* [[CONV4]], align 2
1207 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[D_CASTED]], align 4
1208 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4
1209 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_CASTED]] to float*
1210 // CHECK3-NEXT: store float [[TMP10]], float* [[CONV5]], align 4
1211 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[SD_CASTED]], align 4
1212 // CHECK3-NEXT: [[TMP12:%.*]] = load double, double* @Ga, align 8
1213 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP12]], 0.000000e+00
1214 // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1215 // CHECK3: land.lhs.true:
1216 // CHECK3-NEXT: [[TMP13:%.*]] = load i16, i16* [[A_ADDR]], align 2
1217 // CHECK3-NEXT: [[CONV6:%.*]] = sext i16 [[TMP13]] to i32
1218 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[CONV6]], 0
1219 // CHECK3-NEXT: br i1 [[CMP7]], label [[LAND_LHS_TRUE8:%.*]], label [[OMP_IF_ELSE]]
1220 // CHECK3: land.lhs.true8:
1221 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4
1222 // CHECK3-NEXT: [[CONV9:%.*]] = fpext float [[TMP14]] to double
1223 // CHECK3-NEXT: [[CMP10:%.*]] = fcmp ogt double [[CONV9]], 0.000000e+00
1224 // CHECK3-NEXT: br i1 [[CMP10]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1225 // CHECK3: omp_if.then:
1226 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1227 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
1228 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP16]], align 4
1229 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1230 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
1231 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP18]], align 4
1232 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1233 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4
1234 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1235 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to double**
1236 // CHECK3-NEXT: store double* @Gb, double** [[TMP21]], align 4
1237 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1238 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to double**
1239 // CHECK3-NEXT: store double* @Gb, double** [[TMP23]], align 4
1240 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1241 // CHECK3-NEXT: store i8* null, i8** [[TMP24]], align 4
1242 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1243 // CHECK3-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
1244 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP26]], align 4
1245 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1246 // CHECK3-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
1247 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP28]], align 4
1248 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1249 // CHECK3-NEXT: store i8* null, i8** [[TMP29]], align 4
1250 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1251 // CHECK3-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to double**
1252 // CHECK3-NEXT: store double* @Gc, double** [[TMP31]], align 4
1253 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1254 // CHECK3-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double**
1255 // CHECK3-NEXT: store double* @Gc, double** [[TMP33]], align 4
1256 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1257 // CHECK3-NEXT: store i8* null, i8** [[TMP34]], align 4
1258 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1259 // CHECK3-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32*
1260 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP36]], align 4
1261 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1262 // CHECK3-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32*
1263 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP38]], align 4
1264 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1265 // CHECK3-NEXT: store i8* null, i8** [[TMP39]], align 4
1266 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
1267 // CHECK3-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32*
1268 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP41]], align 4
1269 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
1270 // CHECK3-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i32*
1271 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP43]], align 4
1272 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
1273 // CHECK3-NEXT: store i8* null, i8** [[TMP44]], align 4
1274 // CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
1275 // CHECK3-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32*
1276 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[TMP46]], align 4
1277 // CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6
1278 // CHECK3-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i32*
1279 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[TMP48]], align 4
1280 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6
1281 // CHECK3-NEXT: store i8* null, i8** [[TMP49]], align 4
1282 // CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
1283 // CHECK3-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double**
1284 // CHECK3-NEXT: store double* @Gd, double** [[TMP51]], align 4
1285 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7
1286 // CHECK3-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double**
1287 // CHECK3-NEXT: store double* @Gd, double** [[TMP53]], align 4
1288 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7
1289 // CHECK3-NEXT: store i8* null, i8** [[TMP54]], align 4
1290 // CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
1291 // CHECK3-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32*
1292 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[TMP56]], align 4
1293 // CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8
1294 // CHECK3-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i32*
1295 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[TMP58]], align 4
1296 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8
1297 // CHECK3-NEXT: store i8* null, i8** [[TMP59]], align 4
1298 // CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1299 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1300 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1301 // CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1302 // CHECK3-NEXT: store i32 1, i32* [[TMP62]], align 4
1303 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1304 // CHECK3-NEXT: store i32 9, i32* [[TMP63]], align 4
1305 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1306 // CHECK3-NEXT: store i8** [[TMP60]], i8*** [[TMP64]], align 4
1307 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1308 // CHECK3-NEXT: store i8** [[TMP61]], i8*** [[TMP65]], align 4
1309 // CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1310 // CHECK3-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP66]], align 4
1311 // CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1312 // CHECK3-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP67]], align 4
1313 // CHECK3-NEXT: [[TMP68:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1314 // CHECK3-NEXT: store i8** null, i8*** [[TMP68]], align 4
1315 // CHECK3-NEXT: [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1316 // CHECK3-NEXT: store i8** null, i8*** [[TMP69]], align 4
1317 // CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1318 // CHECK3-NEXT: store i64 0, i64* [[TMP70]], align 8
1319 // CHECK3-NEXT: [[TMP71:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1320 // CHECK3-NEXT: [[TMP72:%.*]] = icmp ne i32 [[TMP71]], 0
1321 // CHECK3-NEXT: br i1 [[TMP72]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1322 // CHECK3: omp_offload.failed:
1323 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i32 [[TMP1]], double* @Gb, i32 [[TMP3]], double* @Gc, i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP9]], double* @Gd, i32 [[TMP11]]) #[[ATTR2:[0-9]+]]
1324 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1325 // CHECK3: omp_offload.cont:
1326 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
1327 // CHECK3: omp_if.else:
1328 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i32 [[TMP1]], double* @Gb, i32 [[TMP3]], double* @Gc, i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP9]], double* @Gd, i32 [[TMP11]]) #[[ATTR2]]
1329 // CHECK3-NEXT: br label [[OMP_IF_END]]
1330 // CHECK3: omp_if.end:
1331 // CHECK3-NEXT: [[TMP73:%.*]] = load i16, i16* [[A_ADDR]], align 2
1332 // CHECK3-NEXT: [[CONV11:%.*]] = sext i16 [[TMP73]] to i32
1333 // CHECK3-NEXT: [[TMP74:%.*]] = load i16, i16* [[B_ADDR]], align 2
1334 // CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP74]] to i32
1335 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV11]], [[CONV12]]
1336 // CHECK3-NEXT: [[TMP75:%.*]] = load i16, i16* [[C_ADDR]], align 2
1337 // CHECK3-NEXT: [[CONV13:%.*]] = sext i16 [[TMP75]] to i32
1338 // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CONV13]]
1339 // CHECK3-NEXT: [[TMP76:%.*]] = load i16, i16* [[D_ADDR]], align 2
1340 // CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP76]] to i32
1341 // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD14]], [[CONV15]]
1342 // CHECK3-NEXT: [[TMP77:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4
1343 // CHECK3-NEXT: [[CONV17:%.*]] = fptosi float [[TMP77]] to i32
1344 // CHECK3-NEXT: [[ADD18:%.*]] = add nsw i32 [[ADD16]], [[CONV17]]
1345 // CHECK3-NEXT: [[TMP78:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4
1346 // CHECK3-NEXT: [[CONV19:%.*]] = fptosi float [[TMP78]] to i32
1347 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i32 [[ADD18]], [[CONV19]]
1348 // CHECK3-NEXT: [[TMP79:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4
1349 // CHECK3-NEXT: [[CONV21:%.*]] = fptosi float [[TMP79]] to i32
1350 // CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[ADD20]], [[CONV21]]
1351 // CHECK3-NEXT: [[TMP80:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4
1352 // CHECK3-NEXT: [[CONV23:%.*]] = fptosi float [[TMP80]] to i32
1353 // CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[ADD22]], [[CONV23]]
1354 // CHECK3-NEXT: ret i32 [[ADD24]]
1355 //
1356 //
1357 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49
1358 // CHECK3-SAME: (i32 noundef [[B:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 noundef [[SB:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 noundef [[C:%.*]], i32 noundef [[SC:%.*]], i32 noundef [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 noundef [[SD:%.*]]) #[[ATTR1:[0-9]+]] {
1359 // CHECK3-NEXT: entry:
1360 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
1361 // CHECK3-NEXT: [[GB_ADDR:%.*]] = alloca double*, align 4
1362 // CHECK3-NEXT: [[SB_ADDR:%.*]] = alloca i32, align 4
1363 // CHECK3-NEXT: [[GC_ADDR:%.*]] = alloca double*, align 4
1364 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
1365 // CHECK3-NEXT: [[SC_ADDR:%.*]] = alloca i32, align 4
1366 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32, align 4
1367 // CHECK3-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4
1368 // CHECK3-NEXT: [[SD_ADDR:%.*]] = alloca i32, align 4
1369 // CHECK3-NEXT: [[GB6:%.*]] = alloca double, align 8
1370 // CHECK3-NEXT: [[GC7:%.*]] = alloca double, align 8
1371 // CHECK3-NEXT: [[GD8:%.*]] = alloca double, align 8
1372 // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1373 // CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1374 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1375 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
1376 // CHECK3-NEXT: store double* [[GB]], double** [[GB_ADDR]], align 4
1377 // CHECK3-NEXT: store i32 [[SB]], i32* [[SB_ADDR]], align 4
1378 // CHECK3-NEXT: store double* [[GC]], double** [[GC_ADDR]], align 4
1379 // CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4
1380 // CHECK3-NEXT: store i32 [[SC]], i32* [[SC_ADDR]], align 4
1381 // CHECK3-NEXT: store i32 [[D]], i32* [[D_ADDR]], align 4
1382 // CHECK3-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4
1383 // CHECK3-NEXT: store i32 [[SD]], i32* [[SD_ADDR]], align 4
1384 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
1385 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[GB_ADDR]], align 4
1386 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_ADDR]] to float*
1387 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[GC_ADDR]], align 4
1388 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_ADDR]] to i16*
1389 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_ADDR]] to float*
1390 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_ADDR]] to i16*
1391 // CHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4
1392 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float*
1393 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
1394 // CHECK3-NEXT: store double [[TMP4]], double* [[GB6]], align 8
1395 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8
1396 // CHECK3-NEXT: store double [[TMP5]], double* [[GC7]], align 8
1397 // CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
1398 // CHECK3-NEXT: store double [[TMP6]], double* [[GD8]], align 8
1399 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2
1400 // CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
1401 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
1402 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
1403 // CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
1404 // CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
1405 // CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
1406 // CHECK3-NEXT: store double [[ADD11]], double* [[GB6]], align 8
1407 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4
1408 // CHECK3-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double
1409 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
1410 // CHECK3-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
1411 // CHECK3-NEXT: store float [[CONV14]], float* [[CONV1]], align 4
1412 // CHECK3-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8
1413 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
1414 // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1415 // CHECK3: land.lhs.true:
1416 // CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 2
1417 // CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
1418 // CHECK3-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
1419 // CHECK3-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
1420 // CHECK3: land.lhs.true17:
1421 // CHECK3-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4
1422 // CHECK3-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double
1423 // CHECK3-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
1424 // CHECK3-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1425 // CHECK3: omp_if.then:
1426 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined. to void (i32*, i32*, ...)*), i16* [[CONV4]], double* [[GD8]], float* [[CONV5]])
1427 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
1428 // CHECK3: omp_if.else:
1429 // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1430 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
1431 // CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
1432 // CHECK3-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV4]], double* [[GD8]], float* [[CONV5]]) #[[ATTR2]]
1433 // CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1434 // CHECK3-NEXT: br label [[OMP_IF_END]]
1435 // CHECK3: omp_if.end:
1436 // CHECK3-NEXT: ret void
1437 //
1438 //
1439 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
1440 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
1441 // CHECK3-NEXT: entry:
1442 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1443 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1444 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4
1445 // CHECK3-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4
1446 // CHECK3-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 4
1447 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1448 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1449 // CHECK3-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4
1450 // CHECK3-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4
1451 // CHECK3-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 4
1452 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 4
1453 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 4
1454 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 4
1455 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2
1456 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32
1457 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
1458 // CHECK3-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
1459 // CHECK3-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2
1460 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
1461 // CHECK3-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
1462 // CHECK3-NEXT: store double [[ADD2]], double* [[TMP1]], align 8
1463 // CHECK3-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4
1464 // CHECK3-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double
1465 // CHECK3-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
1466 // CHECK3-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
1467 // CHECK3-NEXT: store float [[CONV5]], float* [[TMP2]], align 4
1468 // CHECK3-NEXT: ret void
1469 //
1470 //
1471 // CHECK3-LABEL: define {{[^@]+}}@_Z3barssss
1472 // CHECK3-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] {
1473 // CHECK3-NEXT: entry:
1474 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
1475 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
1476 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
1477 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
1478 // CHECK3-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
1479 // CHECK3-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
1480 // CHECK3-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
1481 // CHECK3-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
1482 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, i16*, i16*, i16*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i16* [[A_ADDR]], i16* [[B_ADDR]], i16* [[C_ADDR]], i16* [[D_ADDR]])
1483 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2
1484 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32
1485 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2
1486 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
1487 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]]
1488 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2
1489 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
1490 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]]
1491 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2
1492 // CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP3]] to i32
1493 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]]
1494 // CHECK3-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4
1495 // CHECK3-NEXT: [[CONV6:%.*]] = fptosi float [[TMP4]] to i32
1496 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]]
1497 // CHECK3-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4
1498 // CHECK3-NEXT: [[CONV8:%.*]] = fptosi float [[TMP5]] to i32
1499 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]]
1500 // CHECK3-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4
1501 // CHECK3-NEXT: [[CONV10:%.*]] = fptosi float [[TMP6]] to i32
1502 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]]
1503 // CHECK3-NEXT: [[TMP7:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4
1504 // CHECK3-NEXT: [[CONV12:%.*]] = fptosi float [[TMP7]] to i32
1505 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
1506 // CHECK3-NEXT: ret i32 [[ADD13]]
1507 //
1508 //
1509 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
1510 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] {
1511 // CHECK3-NEXT: entry:
1512 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1513 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1514 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16*, align 4
1515 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16*, align 4
1516 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
1517 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4
1518 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
1519 // CHECK3-NEXT: [[SB_CASTED:%.*]] = alloca i32, align 4
1520 // CHECK3-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4
1521 // CHECK3-NEXT: [[SC_CASTED:%.*]] = alloca i32, align 4
1522 // CHECK3-NEXT: [[D_CASTED:%.*]] = alloca i32, align 4
1523 // CHECK3-NEXT: [[SD_CASTED:%.*]] = alloca i32, align 4
1524 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 4
1525 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 4
1526 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 4
1527 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1528 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1529 // CHECK3-NEXT: store i16* [[A]], i16** [[A_ADDR]], align 4
1530 // CHECK3-NEXT: store i16* [[B]], i16** [[B_ADDR]], align 4
1531 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
1532 // CHECK3-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4
1533 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[A_ADDR]], align 4
1534 // CHECK3-NEXT: [[TMP1:%.*]] = load i16*, i16** [[B_ADDR]], align 4
1535 // CHECK3-NEXT: [[TMP2:%.*]] = load i16*, i16** [[C_ADDR]], align 4
1536 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[D_ADDR]], align 4
1537 // CHECK3-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
1538 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16*
1539 // CHECK3-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2
1540 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
1541 // CHECK3-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4
1542 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_CASTED]] to float*
1543 // CHECK3-NEXT: store float [[TMP6]], float* [[CONV1]], align 4
1544 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[SB_CASTED]], align 4
1545 // CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[TMP2]], align 2
1546 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_CASTED]] to i16*
1547 // CHECK3-NEXT: store i16 [[TMP8]], i16* [[CONV2]], align 2
1548 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[C_CASTED]], align 4
1549 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4
1550 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_CASTED]] to float*
1551 // CHECK3-NEXT: store float [[TMP10]], float* [[CONV3]], align 4
1552 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[SC_CASTED]], align 4
1553 // CHECK3-NEXT: [[TMP12:%.*]] = load i16, i16* [[TMP3]], align 2
1554 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_CASTED]] to i16*
1555 // CHECK3-NEXT: store i16 [[TMP12]], i16* [[CONV4]], align 2
1556 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[D_CASTED]], align 4
1557 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4
1558 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_CASTED]] to float*
1559 // CHECK3-NEXT: store float [[TMP14]], float* [[CONV5]], align 4
1560 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[SD_CASTED]], align 4
1561 // CHECK3-NEXT: [[TMP16:%.*]] = load double, double* @Ga, align 8
1562 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP16]], 0.000000e+00
1563 // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1564 // CHECK3: land.lhs.true:
1565 // CHECK3-NEXT: [[TMP17:%.*]] = load i16, i16* [[TMP0]], align 2
1566 // CHECK3-NEXT: [[CONV6:%.*]] = sext i16 [[TMP17]] to i32
1567 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[CONV6]], 0
1568 // CHECK3-NEXT: br i1 [[CMP7]], label [[LAND_LHS_TRUE8:%.*]], label [[OMP_IF_ELSE]]
1569 // CHECK3: land.lhs.true8:
1570 // CHECK3-NEXT: [[TMP18:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4
1571 // CHECK3-NEXT: [[CONV9:%.*]] = fpext float [[TMP18]] to double
1572 // CHECK3-NEXT: [[CMP10:%.*]] = fcmp ogt double [[CONV9]], 0.000000e+00
1573 // CHECK3-NEXT: br i1 [[CMP10]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1574 // CHECK3: omp_if.then:
1575 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1576 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
1577 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
1578 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1579 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
1580 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP22]], align 4
1581 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1582 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4
1583 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1584 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to double**
1585 // CHECK3-NEXT: store double* @Gb, double** [[TMP25]], align 4
1586 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1587 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to double**
1588 // CHECK3-NEXT: store double* @Gb, double** [[TMP27]], align 4
1589 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1590 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4
1591 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1592 // CHECK3-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
1593 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP30]], align 4
1594 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1595 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
1596 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP32]], align 4
1597 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1598 // CHECK3-NEXT: store i8* null, i8** [[TMP33]], align 4
1599 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1600 // CHECK3-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to double**
1601 // CHECK3-NEXT: store double* @Gc, double** [[TMP35]], align 4
1602 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1603 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to double**
1604 // CHECK3-NEXT: store double* @Gc, double** [[TMP37]], align 4
1605 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1606 // CHECK3-NEXT: store i8* null, i8** [[TMP38]], align 4
1607 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1608 // CHECK3-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32*
1609 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[TMP40]], align 4
1610 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1611 // CHECK3-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32*
1612 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[TMP42]], align 4
1613 // CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1614 // CHECK3-NEXT: store i8* null, i8** [[TMP43]], align 4
1615 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
1616 // CHECK3-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i32*
1617 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[TMP45]], align 4
1618 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
1619 // CHECK3-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32*
1620 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[TMP47]], align 4
1621 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
1622 // CHECK3-NEXT: store i8* null, i8** [[TMP48]], align 4
1623 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
1624 // CHECK3-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32*
1625 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[TMP50]], align 4
1626 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6
1627 // CHECK3-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32*
1628 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[TMP52]], align 4
1629 // CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6
1630 // CHECK3-NEXT: store i8* null, i8** [[TMP53]], align 4
1631 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
1632 // CHECK3-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to double**
1633 // CHECK3-NEXT: store double* @Gd, double** [[TMP55]], align 4
1634 // CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7
1635 // CHECK3-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to double**
1636 // CHECK3-NEXT: store double* @Gd, double** [[TMP57]], align 4
1637 // CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7
1638 // CHECK3-NEXT: store i8* null, i8** [[TMP58]], align 4
1639 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
1640 // CHECK3-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
1641 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[TMP60]], align 4
1642 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8
1643 // CHECK3-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
1644 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[TMP62]], align 4
1645 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8
1646 // CHECK3-NEXT: store i8* null, i8** [[TMP63]], align 4
1647 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1648 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1649 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1650 // CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1651 // CHECK3-NEXT: store i32 1, i32* [[TMP66]], align 4
1652 // CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1653 // CHECK3-NEXT: store i32 9, i32* [[TMP67]], align 4
1654 // CHECK3-NEXT: [[TMP68:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1655 // CHECK3-NEXT: store i8** [[TMP64]], i8*** [[TMP68]], align 4
1656 // CHECK3-NEXT: [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1657 // CHECK3-NEXT: store i8** [[TMP65]], i8*** [[TMP69]], align 4
1658 // CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1659 // CHECK3-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP70]], align 4
1660 // CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1661 // CHECK3-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP71]], align 4
1662 // CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1663 // CHECK3-NEXT: store i8** null, i8*** [[TMP72]], align 4
1664 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1665 // CHECK3-NEXT: store i8** null, i8*** [[TMP73]], align 4
1666 // CHECK3-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1667 // CHECK3-NEXT: store i64 0, i64* [[TMP74]], align 8
1668 // CHECK3-NEXT: [[TMP75:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1669 // CHECK3-NEXT: [[TMP76:%.*]] = icmp ne i32 [[TMP75]], 0
1670 // CHECK3-NEXT: br i1 [[TMP76]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1671 // CHECK3: omp_offload.failed:
1672 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i32 [[TMP5]], double* @Gb, i32 [[TMP7]], double* @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], double* @Gd, i32 [[TMP15]]) #[[ATTR2]]
1673 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1674 // CHECK3: omp_offload.cont:
1675 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
1676 // CHECK3: omp_if.else:
1677 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i32 [[TMP5]], double* @Gb, i32 [[TMP7]], double* @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], double* @Gd, i32 [[TMP15]]) #[[ATTR2]]
1678 // CHECK3-NEXT: br label [[OMP_IF_END]]
1679 // CHECK3: omp_if.end:
1680 // CHECK3-NEXT: ret void
1681 //
1682 //
1683 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94
1684 // CHECK3-SAME: (i32 noundef [[B:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 noundef [[SB:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 noundef [[C:%.*]], i32 noundef [[SC:%.*]], i32 noundef [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 noundef [[SD:%.*]]) #[[ATTR1]] {
1685 // CHECK3-NEXT: entry:
1686 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
1687 // CHECK3-NEXT: [[GB_ADDR:%.*]] = alloca double*, align 4
1688 // CHECK3-NEXT: [[SB_ADDR:%.*]] = alloca i32, align 4
1689 // CHECK3-NEXT: [[GC_ADDR:%.*]] = alloca double*, align 4
1690 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
1691 // CHECK3-NEXT: [[SC_ADDR:%.*]] = alloca i32, align 4
1692 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32, align 4
1693 // CHECK3-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4
1694 // CHECK3-NEXT: [[SD_ADDR:%.*]] = alloca i32, align 4
1695 // CHECK3-NEXT: [[GB6:%.*]] = alloca double, align 8
1696 // CHECK3-NEXT: [[GC7:%.*]] = alloca double, align 8
1697 // CHECK3-NEXT: [[GD8:%.*]] = alloca double, align 8
1698 // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1699 // CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1700 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1701 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
1702 // CHECK3-NEXT: store double* [[GB]], double** [[GB_ADDR]], align 4
1703 // CHECK3-NEXT: store i32 [[SB]], i32* [[SB_ADDR]], align 4
1704 // CHECK3-NEXT: store double* [[GC]], double** [[GC_ADDR]], align 4
1705 // CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4
1706 // CHECK3-NEXT: store i32 [[SC]], i32* [[SC_ADDR]], align 4
1707 // CHECK3-NEXT: store i32 [[D]], i32* [[D_ADDR]], align 4
1708 // CHECK3-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4
1709 // CHECK3-NEXT: store i32 [[SD]], i32* [[SD_ADDR]], align 4
1710 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
1711 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[GB_ADDR]], align 4
1712 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_ADDR]] to float*
1713 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[GC_ADDR]], align 4
1714 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_ADDR]] to i16*
1715 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_ADDR]] to float*
1716 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_ADDR]] to i16*
1717 // CHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4
1718 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float*
1719 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
1720 // CHECK3-NEXT: store double [[TMP4]], double* [[GB6]], align 8
1721 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8
1722 // CHECK3-NEXT: store double [[TMP5]], double* [[GC7]], align 8
1723 // CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
1724 // CHECK3-NEXT: store double [[TMP6]], double* [[GD8]], align 8
1725 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2
1726 // CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
1727 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
1728 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
1729 // CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
1730 // CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
1731 // CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
1732 // CHECK3-NEXT: store double [[ADD11]], double* [[GB6]], align 8
1733 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4
1734 // CHECK3-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double
1735 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
1736 // CHECK3-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
1737 // CHECK3-NEXT: store float [[CONV14]], float* [[CONV1]], align 4
1738 // CHECK3-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8
1739 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
1740 // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1741 // CHECK3: land.lhs.true:
1742 // CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 2
1743 // CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
1744 // CHECK3-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
1745 // CHECK3-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
1746 // CHECK3: land.lhs.true17:
1747 // CHECK3-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4
1748 // CHECK3-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double
1749 // CHECK3-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
1750 // CHECK3-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1751 // CHECK3: omp_if.then:
1752 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i16* [[CONV4]], double* [[GD8]], float* [[CONV5]])
1753 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
1754 // CHECK3: omp_if.else:
1755 // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1756 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
1757 // CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
1758 // CHECK3-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV4]], double* [[GD8]], float* [[CONV5]]) #[[ATTR2]]
1759 // CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1760 // CHECK3-NEXT: br label [[OMP_IF_END]]
1761 // CHECK3: omp_if.end:
1762 // CHECK3-NEXT: ret void
1763 //
1764 //
1765 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2
1766 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
1767 // CHECK3-NEXT: entry:
1768 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1769 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1770 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4
1771 // CHECK3-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4
1772 // CHECK3-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 4
1773 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1774 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1775 // CHECK3-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4
1776 // CHECK3-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4
1777 // CHECK3-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 4
1778 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 4
1779 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 4
1780 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 4
1781 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2
1782 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32
1783 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
1784 // CHECK3-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
1785 // CHECK3-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2
1786 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
1787 // CHECK3-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
1788 // CHECK3-NEXT: store double [[ADD2]], double* [[TMP1]], align 8
1789 // CHECK3-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4
1790 // CHECK3-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double
1791 // CHECK3-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
1792 // CHECK3-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
1793 // CHECK3-NEXT: store float [[CONV5]], float* [[TMP2]], align 4
1794 // CHECK3-NEXT: ret void
1795 //
1796 //
1797 // CHECK3-LABEL: define {{[^@]+}}@_Z5tbar2ssss
1798 // CHECK3-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] {
1799 // CHECK3-NEXT: entry:
1800 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
1801 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
1802 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
1803 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
1804 // CHECK3-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
1805 // CHECK3-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
1806 // CHECK3-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
1807 // CHECK3-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
1808 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2
1809 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2
1810 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2
1811 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2
1812 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 noundef signext [[TMP0]], i16 noundef signext [[TMP1]], i16 noundef signext [[TMP2]], i16 noundef signext [[TMP3]])
1813 // CHECK3-NEXT: ret i32 [[CALL]]
1814 //
1815 //
1816 // CHECK3-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_
1817 // CHECK3-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] comdat {
1818 // CHECK3-NEXT: entry:
1819 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
1820 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
1821 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
1822 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
1823 // CHECK3-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
1824 // CHECK3-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
1825 // CHECK3-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
1826 // CHECK3-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
1827 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, i16*, i16*, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i16* [[A_ADDR]], i16* [[B_ADDR]], i16* [[C_ADDR]], i16* [[D_ADDR]])
1828 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2
1829 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32
1830 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2
1831 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
1832 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]]
1833 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2
1834 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
1835 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]]
1836 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2
1837 // CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP3]] to i32
1838 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]]
1839 // CHECK3-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4
1840 // CHECK3-NEXT: [[CONV6:%.*]] = fptosi float [[TMP4]] to i32
1841 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]]
1842 // CHECK3-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4
1843 // CHECK3-NEXT: [[CONV8:%.*]] = fptosi float [[TMP5]] to i32
1844 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]]
1845 // CHECK3-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4
1846 // CHECK3-NEXT: [[CONV10:%.*]] = fptosi float [[TMP6]] to i32
1847 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]]
1848 // CHECK3-NEXT: [[TMP7:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4
1849 // CHECK3-NEXT: [[CONV12:%.*]] = fptosi float [[TMP7]] to i32
1850 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
1851 // CHECK3-NEXT: ret i32 [[ADD13]]
1852 //
1853 //
1854 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5
1855 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] {
1856 // CHECK3-NEXT: entry:
1857 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1858 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1859 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16*, align 4
1860 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16*, align 4
1861 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
1862 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4
1863 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
1864 // CHECK3-NEXT: [[SB_CASTED:%.*]] = alloca i32, align 4
1865 // CHECK3-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4
1866 // CHECK3-NEXT: [[SC_CASTED:%.*]] = alloca i32, align 4
1867 // CHECK3-NEXT: [[D_CASTED:%.*]] = alloca i32, align 4
1868 // CHECK3-NEXT: [[SD_CASTED:%.*]] = alloca i32, align 4
1869 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 4
1870 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 4
1871 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 4
1872 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1873 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1874 // CHECK3-NEXT: store i16* [[A]], i16** [[A_ADDR]], align 4
1875 // CHECK3-NEXT: store i16* [[B]], i16** [[B_ADDR]], align 4
1876 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
1877 // CHECK3-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4
1878 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[A_ADDR]], align 4
1879 // CHECK3-NEXT: [[TMP1:%.*]] = load i16*, i16** [[B_ADDR]], align 4
1880 // CHECK3-NEXT: [[TMP2:%.*]] = load i16*, i16** [[C_ADDR]], align 4
1881 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[D_ADDR]], align 4
1882 // CHECK3-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
1883 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16*
1884 // CHECK3-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2
1885 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
1886 // CHECK3-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4
1887 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_CASTED]] to float*
1888 // CHECK3-NEXT: store float [[TMP6]], float* [[CONV1]], align 4
1889 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[SB_CASTED]], align 4
1890 // CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[TMP2]], align 2
1891 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_CASTED]] to i16*
1892 // CHECK3-NEXT: store i16 [[TMP8]], i16* [[CONV2]], align 2
1893 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[C_CASTED]], align 4
1894 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4
1895 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_CASTED]] to float*
1896 // CHECK3-NEXT: store float [[TMP10]], float* [[CONV3]], align 4
1897 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[SC_CASTED]], align 4
1898 // CHECK3-NEXT: [[TMP12:%.*]] = load i16, i16* [[TMP3]], align 2
1899 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_CASTED]] to i16*
1900 // CHECK3-NEXT: store i16 [[TMP12]], i16* [[CONV4]], align 2
1901 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[D_CASTED]], align 4
1902 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4
1903 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_CASTED]] to float*
1904 // CHECK3-NEXT: store float [[TMP14]], float* [[CONV5]], align 4
1905 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[SD_CASTED]], align 4
1906 // CHECK3-NEXT: [[TMP16:%.*]] = load double, double* @Ga, align 8
1907 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP16]], 0.000000e+00
1908 // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1909 // CHECK3: land.lhs.true:
1910 // CHECK3-NEXT: [[TMP17:%.*]] = load i16, i16* [[TMP0]], align 2
1911 // CHECK3-NEXT: [[CONV6:%.*]] = sext i16 [[TMP17]] to i32
1912 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[CONV6]], 0
1913 // CHECK3-NEXT: br i1 [[CMP7]], label [[LAND_LHS_TRUE8:%.*]], label [[OMP_IF_ELSE]]
1914 // CHECK3: land.lhs.true8:
1915 // CHECK3-NEXT: [[TMP18:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4
1916 // CHECK3-NEXT: [[CONV9:%.*]] = fpext float [[TMP18]] to double
1917 // CHECK3-NEXT: [[CMP10:%.*]] = fcmp ogt double [[CONV9]], 0.000000e+00
1918 // CHECK3-NEXT: br i1 [[CMP10]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1919 // CHECK3: omp_if.then:
1920 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1921 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
1922 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
1923 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1924 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
1925 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP22]], align 4
1926 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1927 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4
1928 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1929 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to double**
1930 // CHECK3-NEXT: store double* @Gb, double** [[TMP25]], align 4
1931 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1932 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to double**
1933 // CHECK3-NEXT: store double* @Gb, double** [[TMP27]], align 4
1934 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1935 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4
1936 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1937 // CHECK3-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
1938 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP30]], align 4
1939 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1940 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
1941 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP32]], align 4
1942 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1943 // CHECK3-NEXT: store i8* null, i8** [[TMP33]], align 4
1944 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1945 // CHECK3-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to double**
1946 // CHECK3-NEXT: store double* @Gc, double** [[TMP35]], align 4
1947 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1948 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to double**
1949 // CHECK3-NEXT: store double* @Gc, double** [[TMP37]], align 4
1950 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1951 // CHECK3-NEXT: store i8* null, i8** [[TMP38]], align 4
1952 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1953 // CHECK3-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32*
1954 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[TMP40]], align 4
1955 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1956 // CHECK3-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32*
1957 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[TMP42]], align 4
1958 // CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1959 // CHECK3-NEXT: store i8* null, i8** [[TMP43]], align 4
1960 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
1961 // CHECK3-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i32*
1962 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[TMP45]], align 4
1963 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
1964 // CHECK3-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32*
1965 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[TMP47]], align 4
1966 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
1967 // CHECK3-NEXT: store i8* null, i8** [[TMP48]], align 4
1968 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
1969 // CHECK3-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32*
1970 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[TMP50]], align 4
1971 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6
1972 // CHECK3-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32*
1973 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[TMP52]], align 4
1974 // CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6
1975 // CHECK3-NEXT: store i8* null, i8** [[TMP53]], align 4
1976 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
1977 // CHECK3-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to double**
1978 // CHECK3-NEXT: store double* @Gd, double** [[TMP55]], align 4
1979 // CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7
1980 // CHECK3-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to double**
1981 // CHECK3-NEXT: store double* @Gd, double** [[TMP57]], align 4
1982 // CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7
1983 // CHECK3-NEXT: store i8* null, i8** [[TMP58]], align 4
1984 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
1985 // CHECK3-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
1986 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[TMP60]], align 4
1987 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8
1988 // CHECK3-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
1989 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[TMP62]], align 4
1990 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8
1991 // CHECK3-NEXT: store i8* null, i8** [[TMP63]], align 4
1992 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1993 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1994 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1995 // CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1996 // CHECK3-NEXT: store i32 1, i32* [[TMP66]], align 4
1997 // CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1998 // CHECK3-NEXT: store i32 9, i32* [[TMP67]], align 4
1999 // CHECK3-NEXT: [[TMP68:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
2000 // CHECK3-NEXT: store i8** [[TMP64]], i8*** [[TMP68]], align 4
2001 // CHECK3-NEXT: [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
2002 // CHECK3-NEXT: store i8** [[TMP65]], i8*** [[TMP69]], align 4
2003 // CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
2004 // CHECK3-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP70]], align 4
2005 // CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
2006 // CHECK3-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP71]], align 4
2007 // CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
2008 // CHECK3-NEXT: store i8** null, i8*** [[TMP72]], align 4
2009 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
2010 // CHECK3-NEXT: store i8** null, i8*** [[TMP73]], align 4
2011 // CHECK3-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
2012 // CHECK3-NEXT: store i64 0, i64* [[TMP74]], align 8
2013 // CHECK3-NEXT: [[TMP75:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
2014 // CHECK3-NEXT: [[TMP76:%.*]] = icmp ne i32 [[TMP75]], 0
2015 // CHECK3-NEXT: br i1 [[TMP76]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2016 // CHECK3: omp_offload.failed:
2017 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i32 [[TMP5]], double* @Gb, i32 [[TMP7]], double* @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], double* @Gd, i32 [[TMP15]]) #[[ATTR2]]
2018 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
2019 // CHECK3: omp_offload.cont:
2020 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
2021 // CHECK3: omp_if.else:
2022 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i32 [[TMP5]], double* @Gb, i32 [[TMP7]], double* @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], double* @Gd, i32 [[TMP15]]) #[[ATTR2]]
2023 // CHECK3-NEXT: br label [[OMP_IF_END]]
2024 // CHECK3: omp_if.end:
2025 // CHECK3-NEXT: ret void
2026 //
2027 //
2028 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145
2029 // CHECK3-SAME: (i32 noundef [[B:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 noundef [[SB:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 noundef [[C:%.*]], i32 noundef [[SC:%.*]], i32 noundef [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 noundef [[SD:%.*]]) #[[ATTR1]] {
2030 // CHECK3-NEXT: entry:
2031 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
2032 // CHECK3-NEXT: [[GB_ADDR:%.*]] = alloca double*, align 4
2033 // CHECK3-NEXT: [[SB_ADDR:%.*]] = alloca i32, align 4
2034 // CHECK3-NEXT: [[GC_ADDR:%.*]] = alloca double*, align 4
2035 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
2036 // CHECK3-NEXT: [[SC_ADDR:%.*]] = alloca i32, align 4
2037 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32, align 4
2038 // CHECK3-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4
2039 // CHECK3-NEXT: [[SD_ADDR:%.*]] = alloca i32, align 4
2040 // CHECK3-NEXT: [[GB6:%.*]] = alloca double, align 8
2041 // CHECK3-NEXT: [[GC7:%.*]] = alloca double, align 8
2042 // CHECK3-NEXT: [[GD8:%.*]] = alloca double, align 8
2043 // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2044 // CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
2045 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
2046 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
2047 // CHECK3-NEXT: store double* [[GB]], double** [[GB_ADDR]], align 4
2048 // CHECK3-NEXT: store i32 [[SB]], i32* [[SB_ADDR]], align 4
2049 // CHECK3-NEXT: store double* [[GC]], double** [[GC_ADDR]], align 4
2050 // CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4
2051 // CHECK3-NEXT: store i32 [[SC]], i32* [[SC_ADDR]], align 4
2052 // CHECK3-NEXT: store i32 [[D]], i32* [[D_ADDR]], align 4
2053 // CHECK3-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4
2054 // CHECK3-NEXT: store i32 [[SD]], i32* [[SD_ADDR]], align 4
2055 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
2056 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[GB_ADDR]], align 4
2057 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_ADDR]] to float*
2058 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[GC_ADDR]], align 4
2059 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_ADDR]] to i16*
2060 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_ADDR]] to float*
2061 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_ADDR]] to i16*
2062 // CHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4
2063 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float*
2064 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
2065 // CHECK3-NEXT: store double [[TMP4]], double* [[GB6]], align 8
2066 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8
2067 // CHECK3-NEXT: store double [[TMP5]], double* [[GC7]], align 8
2068 // CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
2069 // CHECK3-NEXT: store double [[TMP6]], double* [[GD8]], align 8
2070 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2
2071 // CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
2072 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
2073 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
2074 // CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
2075 // CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
2076 // CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
2077 // CHECK3-NEXT: store double [[ADD11]], double* [[GB6]], align 8
2078 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4
2079 // CHECK3-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double
2080 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
2081 // CHECK3-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
2082 // CHECK3-NEXT: store float [[CONV14]], float* [[CONV1]], align 4
2083 // CHECK3-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8
2084 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
2085 // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
2086 // CHECK3: land.lhs.true:
2087 // CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 2
2088 // CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
2089 // CHECK3-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
2090 // CHECK3-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
2091 // CHECK3: land.lhs.true17:
2092 // CHECK3-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4
2093 // CHECK3-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double
2094 // CHECK3-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
2095 // CHECK3-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
2096 // CHECK3: omp_if.then:
2097 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i16* [[CONV4]], double* [[GD8]], float* [[CONV5]])
2098 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
2099 // CHECK3: omp_if.else:
2100 // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2101 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
2102 // CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
2103 // CHECK3-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV4]], double* [[GD8]], float* [[CONV5]]) #[[ATTR2]]
2104 // CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2105 // CHECK3-NEXT: br label [[OMP_IF_END]]
2106 // CHECK3: omp_if.end:
2107 // CHECK3-NEXT: ret void
2108 //
2109 //
2110 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6
2111 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
2112 // CHECK3-NEXT: entry:
2113 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2114 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2115 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4
2116 // CHECK3-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4
2117 // CHECK3-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 4
2118 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2119 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2120 // CHECK3-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4
2121 // CHECK3-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4
2122 // CHECK3-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 4
2123 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 4
2124 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 4
2125 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 4
2126 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2
2127 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32
2128 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
2129 // CHECK3-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
2130 // CHECK3-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2
2131 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
2132 // CHECK3-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
2133 // CHECK3-NEXT: store double [[ADD2]], double* [[TMP1]], align 8
2134 // CHECK3-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4
2135 // CHECK3-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double
2136 // CHECK3-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
2137 // CHECK3-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
2138 // CHECK3-NEXT: store float [[CONV5]], float* [[TMP2]], align 4
2139 // CHECK3-NEXT: ret void
2140 //
2141 //
2142 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2143 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
2144 // CHECK3-NEXT: entry:
2145 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
2146 // CHECK3-NEXT: ret void
2147 //
2148