1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s 4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 5 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 7 8 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 9 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s 10 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 11 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 12 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 13 // expected-no-diagnostics 14 #ifndef HEADER 15 #define HEADER 16 17 volatile int g __attribute__((aligned(128))) = 1212; 18 19 template <class T> 20 struct S { 21 T f; 22 S(T a) : f(a + g) {} 23 S() : f(g) {} 24 operator T() { return T(); } 25 S &operator&(const S &) { return *this; } 26 ~S() {} 27 }; 28 29 struct SS { 30 int a; 31 int b : 4; 32 int &c; 33 SS(int &d) : a(0), b(0), c(d) { 34 #pragma omp parallel reduction(default, +: a, b, c) 35 #ifdef LAMBDA 36 [&]() { 37 ++this->a, --b, (this)->c /= 1; 38 #pragma omp parallel reduction(&: a, b, c) 39 ++(this)->a, --b, this->c /= 1; 40 }(); 41 #elif defined(BLOCKS) 42 ^{ 43 ++a; 44 --this->b; 45 (this)->c /= 1; 46 #pragma omp parallel reduction(-: a, b, c) 47 ++(this)->a, --b, this->c /= 1; 48 }(); 49 #else 50 ++this->a, --b, c /= 1; 51 #endif 52 } 53 }; 54 55 template<typename T> 56 struct SST { 57 T a; 58 SST() : a(T()) { 59 #pragma omp parallel reduction(*: a) 60 #ifdef LAMBDA 61 [&]() { 62 [&]() { 63 ++this->a; 64 #pragma omp parallel reduction(&& :a) 65 ++(this)->a; 66 }(); 67 }(); 68 #elif defined(BLOCKS) 69 ^{ 70 ^{ 71 ++a; 72 #pragma omp parallel reduction(|: a) 73 ++(this)->a; 74 }(); 75 }(); 76 #else 77 ++(this)->a; 78 #endif 79 } 80 }; 81 82 83 //CHECK: foo_array_sect 84 //CHECK: call void {{.+}}@__kmpc_fork_call( 85 //CHECK: ret void 86 void foo_array_sect(short x[1]) { 87 #pragma omp parallel reduction(default, + : x[:]) 88 {} 89 } 90 91 template <typename T> 92 T tmain() { 93 T t; 94 S<T> test; 95 SST<T> sst; 96 T t_var __attribute__((aligned(128))) = T(), t_var1 __attribute__((aligned(128))); 97 T vec[] = {1, 2}; 98 S<T> s_arr[] = {1, 2}; 99 S<T> var __attribute__((aligned(128))) (3), var1 __attribute__((aligned(128))); 100 #pragma omp parallel reduction(+:t_var) reduction(&:var) reduction(&& : var1) reduction(min: t_var1) 101 { 102 vec[0] = t_var; 103 s_arr[0] = var; 104 } 105 return T(); 106 } 107 108 int sivar; 109 int main() { 110 SS ss(sivar); 111 #ifdef LAMBDA 112 [&]() { 113 #pragma omp parallel reduction(+:g) 114 { 115 116 117 118 119 // Reduction list for runtime. 120 121 g = 1; 122 123 [&]() { 124 g = 2; 125 }(); 126 } 127 }(); 128 return 0; 129 #elif defined(BLOCKS) 130 ^{ 131 #pragma omp parallel reduction(-:g) 132 { 133 134 // Reduction list for runtime. 135 136 g = 1; 137 138 ^{ 139 g = 2; 140 }(); 141 } 142 }(); 143 return 0; 144 145 146 #else 147 S<float> test; 148 float t_var = 0, t_var1; 149 int vec[] = {1, 2}; 150 S<float> s_arr[] = {1, 2}; 151 S<float> var(3), var1; 152 float _Complex cf; 153 #pragma omp parallel reduction(+:t_var) reduction(&:var) reduction(&& : var1) reduction(min: t_var1) 154 { 155 vec[0] = t_var; 156 s_arr[0] = var; 157 } 158 if (var1) 159 #pragma omp parallel reduction(+ : t_var) reduction(& : var) reduction(&& : var1) reduction(min : t_var1) 160 while (1) { 161 vec[0] = t_var; 162 s_arr[0] = var; 163 } 164 #pragma omp parallel reduction(+ : cf) 165 ; 166 return tmain<int>(); 167 #endif 168 } 169 170 171 // Reduction list for runtime. 172 173 174 175 // For + reduction operation initial value of private variable is 0. 176 177 // For & reduction operation initial value of private variable is ones in all bits. 178 179 // For && reduction operation initial value of private variable is 1.0. 180 181 // For min reduction operation initial value of private variable is largest repesentable value. 182 183 // Skip checks for internal operations. 184 185 // void *RedList[<n>] = {<ReductionVars>[0], ..., <ReductionVars>[<n>-1]}; 186 187 188 // res = __kmpc_reduce_nowait(<loc>, <gtid>, <n>, sizeof(RedList), RedList, reduce_func, &<lock>); 189 190 191 // switch(res) 192 193 // case 1: 194 // t_var += t_var_reduction; 195 196 // var = var.operator &(var_reduction); 197 198 // var1 = var1.operator &&(var1_reduction); 199 200 // t_var1 = min(t_var1, t_var1_reduction); 201 202 // __kmpc_end_reduce_nowait(<loc>, <gtid>, &<lock>); 203 204 // break; 205 206 // case 2: 207 // t_var += t_var_reduction; 208 209 // var = var.operator &(var_reduction); 210 211 // var1 = var1.operator &&(var1_reduction); 212 213 // t_var1 = min(t_var1, t_var1_reduction); 214 215 // break; 216 217 218 // void reduce_func(void *lhs[<n>], void *rhs[<n>]) { 219 // *(Type0*)lhs[0] = ReductionOperation0(*(Type0*)lhs[0], *(Type0*)rhs[0]); 220 // ... 221 // *(Type<n>-1*)lhs[<n>-1] = ReductionOperation<n>-1(*(Type<n>-1*)lhs[<n>-1], 222 // *(Type<n>-1*)rhs[<n>-1]); 223 // } 224 // t_var_lhs = (float*)lhs[0]; 225 // t_var_rhs = (float*)rhs[0]; 226 227 // var_lhs = (S<float>*)lhs[1]; 228 // var_rhs = (S<float>*)rhs[1]; 229 230 // var1_lhs = (S<float>*)lhs[2]; 231 // var1_rhs = (S<float>*)rhs[2]; 232 233 // t_var1_lhs = (float*)lhs[3]; 234 // t_var1_rhs = (float*)rhs[3]; 235 236 // t_var_lhs += t_var_rhs; 237 238 // var_lhs = var_lhs.operator &(var_rhs); 239 240 // var1_lhs = var1_lhs.operator &&(var1_rhs); 241 242 // t_var1_lhs = min(t_var1_lhs, t_var1_rhs); 243 244 245 246 247 // For + reduction operation initial value of private variable is 0. 248 249 // For & reduction operation initial value of private variable is ones in all bits. 250 251 // For && reduction operation initial value of private variable is 1.0. 252 253 // For min reduction operation initial value of private variable is largest repesentable value. 254 255 256 257 258 259 260 // Reduction list for runtime. 261 262 263 264 // For + reduction operation initial value of private variable is 0. 265 266 // For & reduction operation initial value of private variable is ones in all bits. 267 268 // For && reduction operation initial value of private variable is 1.0. 269 270 // For min reduction operation initial value of private variable is largest repesentable value. 271 272 // Skip checks for internal operations. 273 274 // void *RedList[<n>] = {<ReductionVars>[0], ..., <ReductionVars>[<n>-1]}; 275 276 277 // res = __kmpc_reduce_nowait(<loc>, <gtid>, <n>, sizeof(RedList), RedList, reduce_func, &<lock>); 278 279 280 // switch(res) 281 282 // case 1: 283 // t_var += t_var_reduction; 284 285 // var = var.operator &(var_reduction); 286 287 // var1 = var1.operator &&(var1_reduction); 288 289 // t_var1 = min(t_var1, t_var1_reduction); 290 291 // __kmpc_end_reduce_nowait(<loc>, <gtid>, &<lock>); 292 293 // break; 294 295 // case 2: 296 // t_var += t_var_reduction; 297 298 // var = var.operator &(var_reduction); 299 300 // var1 = var1.operator &&(var1_reduction); 301 302 // t_var1 = min(t_var1, t_var1_reduction); 303 304 // break; 305 306 307 // void reduce_func(void *lhs[<n>], void *rhs[<n>]) { 308 // *(Type0*)lhs[0] = ReductionOperation0(*(Type0*)lhs[0], *(Type0*)rhs[0]); 309 // ... 310 // *(Type<n>-1*)lhs[<n>-1] = ReductionOperation<n>-1(*(Type<n>-1*)lhs[<n>-1], 311 // *(Type<n>-1*)rhs[<n>-1]); 312 // } 313 // t_var_lhs = (i{{[0-9]+}}*)lhs[0]; 314 // t_var_rhs = (i{{[0-9]+}}*)rhs[0]; 315 316 // var_lhs = (S<i{{[0-9]+}}>*)lhs[1]; 317 // var_rhs = (S<i{{[0-9]+}}>*)rhs[1]; 318 319 // var1_lhs = (S<i{{[0-9]+}}>*)lhs[2]; 320 // var1_rhs = (S<i{{[0-9]+}}>*)rhs[2]; 321 322 // t_var1_lhs = (i{{[0-9]+}}*)lhs[3]; 323 // t_var1_rhs = (i{{[0-9]+}}*)rhs[3]; 324 325 // t_var_lhs += t_var_rhs; 326 327 // var_lhs = var_lhs.operator &(var_rhs); 328 329 // var1_lhs = var1_lhs.operator &&(var1_rhs); 330 331 // t_var1_lhs = min(t_var1_lhs, t_var1_rhs); 332 333 #endif 334 // CHECK1-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs 335 // CHECK1-SAME: (i16* [[X:%.*]]) #[[ATTR0:[0-9]+]] { 336 // CHECK1-NEXT: entry: 337 // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 338 // CHECK1-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 339 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[X_ADDR]], align 8 340 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined. to void (i32*, i32*, ...)*), i16* [[TMP0]]) 341 // CHECK1-NEXT: ret void 342 // 343 // 344 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 345 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* [[X:%.*]]) #[[ATTR1:[0-9]+]] { 346 // CHECK1-NEXT: entry: 347 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 348 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 349 // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 350 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 351 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 352 // CHECK1-NEXT: [[TMP:%.*]] = alloca i16*, align 8 353 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [2 x i8*], align 8 354 // CHECK1-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i16, align 2 355 // CHECK1-NEXT: [[_TMP13:%.*]] = alloca i16, align 2 356 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 357 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 358 // CHECK1-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 359 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[X_ADDR]], align 8 360 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP0]], i64 0 361 // CHECK1-NEXT: [[TMP1:%.*]] = load i16*, i16** [[X_ADDR]], align 8 362 // CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i16, i16* [[TMP1]], i64 0 363 // CHECK1-NEXT: [[TMP2:%.*]] = ptrtoint i16* [[ARRAYIDX1]] to i64 364 // CHECK1-NEXT: [[TMP3:%.*]] = ptrtoint i16* [[ARRAYIDX]] to i64 365 // CHECK1-NEXT: [[TMP4:%.*]] = sub i64 [[TMP2]], [[TMP3]] 366 // CHECK1-NEXT: [[TMP5:%.*]] = sdiv exact i64 [[TMP4]], ptrtoint (i16* getelementptr (i16, i16* null, i32 1) to i64) 367 // CHECK1-NEXT: [[TMP6:%.*]] = add nuw i64 [[TMP5]], 1 368 // CHECK1-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], ptrtoint (i16* getelementptr (i16, i16* null, i32 1) to i64) 369 // CHECK1-NEXT: [[TMP8:%.*]] = call i8* @llvm.stacksave() 370 // CHECK1-NEXT: store i8* [[TMP8]], i8** [[SAVED_STACK]], align 8 371 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP6]], align 16 372 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[__VLA_EXPR0]], align 8 373 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr i16, i16* [[VLA]], i64 [[TMP6]] 374 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq i16* [[VLA]], [[TMP9]] 375 // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] 376 // CHECK1: omp.arrayinit.body: 377 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i16* [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] 378 // CHECK1-NEXT: store i16 0, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 2 379 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 380 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i16* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] 381 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] 382 // CHECK1: omp.arrayinit.done: 383 // CHECK1-NEXT: [[TMP10:%.*]] = load i16*, i16** [[X_ADDR]], align 8 384 // CHECK1-NEXT: [[TMP11:%.*]] = ptrtoint i16* [[TMP10]] to i64 385 // CHECK1-NEXT: [[TMP12:%.*]] = ptrtoint i16* [[ARRAYIDX]] to i64 386 // CHECK1-NEXT: [[TMP13:%.*]] = sub i64 [[TMP11]], [[TMP12]] 387 // CHECK1-NEXT: [[TMP14:%.*]] = sdiv exact i64 [[TMP13]], ptrtoint (i16* getelementptr (i16, i16* null, i32 1) to i64) 388 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr i16, i16* [[VLA]], i64 [[TMP14]] 389 // CHECK1-NEXT: store i16* [[TMP15]], i16** [[TMP]], align 8 390 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 391 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i16* [[VLA]] to i8* 392 // CHECK1-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8 393 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1 394 // CHECK1-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP6]] to i8* 395 // CHECK1-NEXT: store i8* [[TMP19]], i8** [[TMP18]], align 8 396 // CHECK1-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 397 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 398 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast [2 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 399 // CHECK1-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP21]], i32 1, i64 16, i8* [[TMP22]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 400 // CHECK1-NEXT: switch i32 [[TMP23]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 401 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 402 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 403 // CHECK1-NEXT: ] 404 // CHECK1: .omp.reduction.case1: 405 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr i16, i16* [[ARRAYIDX]], i64 [[TMP6]] 406 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq i16* [[ARRAYIDX]], [[TMP24]] 407 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE7:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 408 // CHECK1: omp.arraycpy.body: 409 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i16* [ [[VLA]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 410 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST2:%.*]] = phi i16* [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT5:%.*]], [[OMP_ARRAYCPY_BODY]] ] 411 // CHECK1-NEXT: [[TMP25:%.*]] = load i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST2]], align 2 412 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP25]] to i32 413 // CHECK1-NEXT: [[TMP26:%.*]] = load i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 2 414 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP26]] to i32 415 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV3]] 416 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD]] to i16 417 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[OMP_ARRAYCPY_DESTELEMENTPAST2]], align 2 418 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT5]] = getelementptr i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST2]], i32 1 419 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 420 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE6:%.*]] = icmp eq i16* [[OMP_ARRAYCPY_DEST_ELEMENT5]], [[TMP24]] 421 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_DONE7]], label [[OMP_ARRAYCPY_BODY]] 422 // CHECK1: omp.arraycpy.done7: 423 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]], [8 x i32]* @.gomp_critical_user_.reduction.var) 424 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 425 // CHECK1: .omp.reduction.case2: 426 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr i16, i16* [[ARRAYIDX]], i64 [[TMP6]] 427 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY8:%.*]] = icmp eq i16* [[ARRAYIDX]], [[TMP27]] 428 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY8]], label [[OMP_ARRAYCPY_DONE21:%.*]], label [[OMP_ARRAYCPY_BODY9:%.*]] 429 // CHECK1: omp.arraycpy.body9: 430 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST10:%.*]] = phi i16* [ [[VLA]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT19:%.*]], [[ATOMIC_EXIT:%.*]] ] 431 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST11:%.*]] = phi i16* [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT18:%.*]], [[ATOMIC_EXIT]] ] 432 // CHECK1-NEXT: [[TMP28:%.*]] = load i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST10]], align 2 433 // CHECK1-NEXT: [[CONV12:%.*]] = sext i16 [[TMP28]] to i32 434 // CHECK1-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST11]] monotonic, align 2 435 // CHECK1-NEXT: br label [[ATOMIC_CONT:%.*]] 436 // CHECK1: atomic_cont: 437 // CHECK1-NEXT: [[TMP29:%.*]] = phi i16 [ [[ATOMIC_LOAD]], [[OMP_ARRAYCPY_BODY9]] ], [ [[TMP34:%.*]], [[ATOMIC_CONT]] ] 438 // CHECK1-NEXT: store i16 [[TMP29]], i16* [[_TMP13]], align 2 439 // CHECK1-NEXT: [[TMP30:%.*]] = load i16, i16* [[_TMP13]], align 2 440 // CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP30]] to i32 441 // CHECK1-NEXT: [[TMP31:%.*]] = load i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST10]], align 2 442 // CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP31]] to i32 443 // CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV14]], [[CONV15]] 444 // CHECK1-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i16 445 // CHECK1-NEXT: store i16 [[CONV17]], i16* [[ATOMIC_TEMP]], align 2 446 // CHECK1-NEXT: [[TMP32:%.*]] = load i16, i16* [[ATOMIC_TEMP]], align 2 447 // CHECK1-NEXT: [[TMP33:%.*]] = cmpxchg i16* [[OMP_ARRAYCPY_DESTELEMENTPAST11]], i16 [[TMP29]], i16 [[TMP32]] monotonic monotonic, align 2 448 // CHECK1-NEXT: [[TMP34]] = extractvalue { i16, i1 } [[TMP33]], 0 449 // CHECK1-NEXT: [[TMP35:%.*]] = extractvalue { i16, i1 } [[TMP33]], 1 450 // CHECK1-NEXT: br i1 [[TMP35]], label [[ATOMIC_EXIT]], label [[ATOMIC_CONT]] 451 // CHECK1: atomic_exit: 452 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT18]] = getelementptr i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST11]], i32 1 453 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT19]] = getelementptr i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST10]], i32 1 454 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE20:%.*]] = icmp eq i16* [[OMP_ARRAYCPY_DEST_ELEMENT18]], [[TMP27]] 455 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE20]], label [[OMP_ARRAYCPY_DONE21]], label [[OMP_ARRAYCPY_BODY9]] 456 // CHECK1: omp.arraycpy.done21: 457 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 458 // CHECK1: .omp.reduction.default: 459 // CHECK1-NEXT: [[TMP36:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 460 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP36]]) 461 // CHECK1-NEXT: ret void 462 // 463 // 464 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 465 // CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { 466 // CHECK1-NEXT: entry: 467 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 468 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 469 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 470 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 471 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 472 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [2 x i8*]* 473 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 474 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [2 x i8*]* 475 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP5]], i64 0, i64 0 476 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 477 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i16* 478 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP3]], i64 0, i64 0 479 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 480 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i16* 481 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP3]], i64 0, i64 1 482 // CHECK1-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8 483 // CHECK1-NEXT: [[TMP14:%.*]] = ptrtoint i8* [[TMP13]] to i64 484 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr i16, i16* [[TMP11]], i64 [[TMP14]] 485 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq i16* [[TMP11]], [[TMP15]] 486 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 487 // CHECK1: omp.arraycpy.body: 488 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i16* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 489 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i16* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 490 // CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 2 491 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP16]] to i32 492 // CHECK1-NEXT: [[TMP17:%.*]] = load i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 2 493 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP17]] to i32 494 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV2]] 495 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 496 // CHECK1-NEXT: store i16 [[CONV3]], i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 2 497 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 498 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 499 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i16* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP15]] 500 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 501 // CHECK1: omp.arraycpy.done4: 502 // CHECK1-NEXT: ret void 503 // 504 // 505 // CHECK1-LABEL: define {{[^@]+}}@main 506 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] { 507 // CHECK1-NEXT: entry: 508 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 509 // CHECK1-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 510 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 511 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca float, align 4 512 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 513 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 514 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 515 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 516 // CHECK1-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 517 // CHECK1-NEXT: [[CF:%.*]] = alloca { float, float }, align 4 518 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 519 // CHECK1-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) 520 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 521 // CHECK1-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 522 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 523 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) 524 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 525 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 526 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 527 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 528 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 529 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) 530 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, float*, [2 x %struct.S]*, %struct.S*, %struct.S*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], float* [[T_VAR]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], %struct.S* [[VAR1]], float* [[T_VAR1]]) 531 // CHECK1-NEXT: [[CALL:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) 532 // CHECK1-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL]], 0.000000e+00 533 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] 534 // CHECK1: if.then: 535 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, float*, [2 x %struct.S]*, %struct.S*, %struct.S*, float*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], float* [[T_VAR]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], %struct.S* [[VAR1]], float* [[T_VAR1]]) 536 // CHECK1-NEXT: br label [[IF_END]] 537 // CHECK1: if.end: 538 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, { float, float }*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), { float, float }* [[CF]]) 539 // CHECK1-NEXT: [[CALL1:%.*]] = call i32 @_Z5tmainIiET_v() 540 // CHECK1-NEXT: store i32 [[CALL1]], i32* [[RETVAL]], align 4 541 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR5:[0-9]+]] 542 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] 543 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 544 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 545 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 546 // CHECK1: arraydestroy.body: 547 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[IF_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 548 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 549 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] 550 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 551 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 552 // CHECK1: arraydestroy.done2: 553 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] 554 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 555 // CHECK1-NEXT: ret i32 [[TMP2]] 556 // 557 // 558 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 559 // CHECK1-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] align 2 { 560 // CHECK1-NEXT: entry: 561 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 562 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 563 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 564 // CHECK1-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 565 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 566 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 567 // CHECK1-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) 568 // CHECK1-NEXT: ret void 569 // 570 // 571 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 572 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 573 // CHECK1-NEXT: entry: 574 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 575 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 576 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 577 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 578 // CHECK1-NEXT: ret void 579 // 580 // 581 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 582 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 583 // CHECK1-NEXT: entry: 584 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 585 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 586 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 587 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 588 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 589 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 590 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 591 // CHECK1-NEXT: ret void 592 // 593 // 594 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 595 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]]) #[[ATTR1]] { 596 // CHECK1-NEXT: entry: 597 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 598 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 599 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 600 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca float*, align 8 601 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 602 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 603 // CHECK1-NEXT: [[VAR1_ADDR:%.*]] = alloca %struct.S*, align 8 604 // CHECK1-NEXT: [[T_VAR1_ADDR:%.*]] = alloca float*, align 8 605 // CHECK1-NEXT: [[T_VAR2:%.*]] = alloca float, align 4 606 // CHECK1-NEXT: [[VAR3:%.*]] = alloca [[STRUCT_S:%.*]], align 4 607 // CHECK1-NEXT: [[VAR14:%.*]] = alloca [[STRUCT_S]], align 4 608 // CHECK1-NEXT: [[T_VAR15:%.*]] = alloca float, align 4 609 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [4 x i8*], align 8 610 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4 611 // CHECK1-NEXT: [[ATOMIC_TEMP:%.*]] = alloca float, align 4 612 // CHECK1-NEXT: [[TMP:%.*]] = alloca float, align 4 613 // CHECK1-NEXT: [[REF_TMP13:%.*]] = alloca [[STRUCT_S]], align 4 614 // CHECK1-NEXT: [[ATOMIC_TEMP23:%.*]] = alloca float, align 4 615 // CHECK1-NEXT: [[_TMP24:%.*]] = alloca float, align 4 616 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 617 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 618 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 619 // CHECK1-NEXT: store float* [[T_VAR]], float** [[T_VAR_ADDR]], align 8 620 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 621 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 622 // CHECK1-NEXT: store %struct.S* [[VAR1]], %struct.S** [[VAR1_ADDR]], align 8 623 // CHECK1-NEXT: store float* [[T_VAR1]], float** [[T_VAR1_ADDR]], align 8 624 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 625 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[T_VAR_ADDR]], align 8 626 // CHECK1-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 627 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 628 // CHECK1-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[VAR1_ADDR]], align 8 629 // CHECK1-NEXT: [[TMP5:%.*]] = load float*, float** [[T_VAR1_ADDR]], align 8 630 // CHECK1-NEXT: store float 0.000000e+00, float* [[T_VAR2]], align 4 631 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) 632 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) 633 // CHECK1-NEXT: store float 0x47EFFFFFE0000000, float* [[T_VAR15]], align 4 634 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[T_VAR2]], align 4 635 // CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32 636 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP0]], i64 0, i64 0 637 // CHECK1-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4 638 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i64 0, i64 0 639 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* 640 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR3]] to i8* 641 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false) 642 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 643 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast float* [[T_VAR2]] to i8* 644 // CHECK1-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 8 645 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1 646 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR3]] to i8* 647 // CHECK1-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 8 648 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 2 649 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR14]] to i8* 650 // CHECK1-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 651 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 3 652 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast float* [[T_VAR15]] to i8* 653 // CHECK1-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 654 // CHECK1-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 655 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 656 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 657 // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 4, i64 32, i8* [[TMP19]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) 658 // CHECK1-NEXT: switch i32 [[TMP20]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 659 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 660 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 661 // CHECK1-NEXT: ] 662 // CHECK1: .omp.reduction.case1: 663 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[TMP1]], align 4 664 // CHECK1-NEXT: [[TMP22:%.*]] = load float, float* [[T_VAR2]], align 4 665 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP21]], [[TMP22]] 666 // CHECK1-NEXT: store float [[ADD]], float* [[TMP1]], align 4 667 // CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) 668 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast %struct.S* [[TMP3]] to i8* 669 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast %struct.S* [[CALL]] to i8* 670 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i64 4, i1 false) 671 // CHECK1-NEXT: [[CALL7:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP4]]) 672 // CHECK1-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL7]], 0.000000e+00 673 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] 674 // CHECK1: land.rhs: 675 // CHECK1-NEXT: [[CALL8:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) 676 // CHECK1-NEXT: [[TOBOOL9:%.*]] = fcmp une float [[CALL8]], 0.000000e+00 677 // CHECK1-NEXT: br label [[LAND_END]] 678 // CHECK1: land.end: 679 // CHECK1-NEXT: [[TMP25:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL9]], [[LAND_RHS]] ] 680 // CHECK1-NEXT: [[CONV10:%.*]] = uitofp i1 [[TMP25]] to float 681 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]], float [[CONV10]]) 682 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[TMP4]] to i8* 683 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* 684 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) 685 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] 686 // CHECK1-NEXT: [[TMP28:%.*]] = load float, float* [[TMP5]], align 4 687 // CHECK1-NEXT: [[TMP29:%.*]] = load float, float* [[T_VAR15]], align 4 688 // CHECK1-NEXT: [[CMP:%.*]] = fcmp olt float [[TMP28]], [[TMP29]] 689 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 690 // CHECK1: cond.true: 691 // CHECK1-NEXT: [[TMP30:%.*]] = load float, float* [[TMP5]], align 4 692 // CHECK1-NEXT: br label [[COND_END:%.*]] 693 // CHECK1: cond.false: 694 // CHECK1-NEXT: [[TMP31:%.*]] = load float, float* [[T_VAR15]], align 4 695 // CHECK1-NEXT: br label [[COND_END]] 696 // CHECK1: cond.end: 697 // CHECK1-NEXT: [[COND:%.*]] = phi float [ [[TMP30]], [[COND_TRUE]] ], [ [[TMP31]], [[COND_FALSE]] ] 698 // CHECK1-NEXT: store float [[COND]], float* [[TMP5]], align 4 699 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.reduction.var) 700 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 701 // CHECK1: .omp.reduction.case2: 702 // CHECK1-NEXT: [[TMP32:%.*]] = load float, float* [[T_VAR2]], align 4 703 // CHECK1-NEXT: [[TMP33:%.*]] = bitcast float* [[TMP1]] to i32* 704 // CHECK1-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i32, i32* [[TMP33]] monotonic, align 4 705 // CHECK1-NEXT: br label [[ATOMIC_CONT:%.*]] 706 // CHECK1: atomic_cont: 707 // CHECK1-NEXT: [[TMP34:%.*]] = phi i32 [ [[ATOMIC_LOAD]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[TMP42:%.*]], [[ATOMIC_CONT]] ] 708 // CHECK1-NEXT: [[TMP35:%.*]] = bitcast float* [[ATOMIC_TEMP]] to i32* 709 // CHECK1-NEXT: [[TMP36:%.*]] = bitcast i32 [[TMP34]] to float 710 // CHECK1-NEXT: store float [[TMP36]], float* [[TMP]], align 4 711 // CHECK1-NEXT: [[TMP37:%.*]] = load float, float* [[TMP]], align 4 712 // CHECK1-NEXT: [[TMP38:%.*]] = load float, float* [[T_VAR2]], align 4 713 // CHECK1-NEXT: [[ADD11:%.*]] = fadd float [[TMP37]], [[TMP38]] 714 // CHECK1-NEXT: store float [[ADD11]], float* [[ATOMIC_TEMP]], align 4 715 // CHECK1-NEXT: [[TMP39:%.*]] = load i32, i32* [[TMP35]], align 4 716 // CHECK1-NEXT: [[TMP40:%.*]] = bitcast float* [[TMP1]] to i32* 717 // CHECK1-NEXT: [[TMP41:%.*]] = cmpxchg i32* [[TMP40]], i32 [[TMP34]], i32 [[TMP39]] monotonic monotonic, align 4 718 // CHECK1-NEXT: [[TMP42]] = extractvalue { i32, i1 } [[TMP41]], 0 719 // CHECK1-NEXT: [[TMP43:%.*]] = extractvalue { i32, i1 } [[TMP41]], 1 720 // CHECK1-NEXT: br i1 [[TMP43]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] 721 // CHECK1: atomic_exit: 722 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) 723 // CHECK1-NEXT: [[CALL12:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) 724 // CHECK1-NEXT: [[TMP44:%.*]] = bitcast %struct.S* [[TMP3]] to i8* 725 // CHECK1-NEXT: [[TMP45:%.*]] = bitcast %struct.S* [[CALL12]] to i8* 726 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP44]], i8* align 4 [[TMP45]], i64 4, i1 false) 727 // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) 728 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) 729 // CHECK1-NEXT: [[CALL14:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP4]]) 730 // CHECK1-NEXT: [[TOBOOL15:%.*]] = fcmp une float [[CALL14]], 0.000000e+00 731 // CHECK1-NEXT: br i1 [[TOBOOL15]], label [[LAND_RHS16:%.*]], label [[LAND_END19:%.*]] 732 // CHECK1: land.rhs16: 733 // CHECK1-NEXT: [[CALL17:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) 734 // CHECK1-NEXT: [[TOBOOL18:%.*]] = fcmp une float [[CALL17]], 0.000000e+00 735 // CHECK1-NEXT: br label [[LAND_END19]] 736 // CHECK1: land.end19: 737 // CHECK1-NEXT: [[TMP46:%.*]] = phi i1 [ false, [[ATOMIC_EXIT]] ], [ [[TOBOOL18]], [[LAND_RHS16]] ] 738 // CHECK1-NEXT: [[CONV20:%.*]] = uitofp i1 [[TMP46]] to float 739 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP13]], float [[CONV20]]) 740 // CHECK1-NEXT: [[TMP47:%.*]] = bitcast %struct.S* [[TMP4]] to i8* 741 // CHECK1-NEXT: [[TMP48:%.*]] = bitcast %struct.S* [[REF_TMP13]] to i8* 742 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i64 4, i1 false) 743 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP13]]) #[[ATTR5]] 744 // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) 745 // CHECK1-NEXT: [[TMP49:%.*]] = load float, float* [[T_VAR15]], align 4 746 // CHECK1-NEXT: [[TMP50:%.*]] = bitcast float* [[TMP5]] to i32* 747 // CHECK1-NEXT: [[ATOMIC_LOAD21:%.*]] = load atomic i32, i32* [[TMP50]] monotonic, align 4 748 // CHECK1-NEXT: br label [[ATOMIC_CONT22:%.*]] 749 // CHECK1: atomic_cont22: 750 // CHECK1-NEXT: [[TMP51:%.*]] = phi i32 [ [[ATOMIC_LOAD21]], [[LAND_END19]] ], [ [[TMP61:%.*]], [[COND_END28:%.*]] ] 751 // CHECK1-NEXT: [[TMP52:%.*]] = bitcast float* [[ATOMIC_TEMP23]] to i32* 752 // CHECK1-NEXT: [[TMP53:%.*]] = bitcast i32 [[TMP51]] to float 753 // CHECK1-NEXT: store float [[TMP53]], float* [[_TMP24]], align 4 754 // CHECK1-NEXT: [[TMP54:%.*]] = load float, float* [[_TMP24]], align 4 755 // CHECK1-NEXT: [[TMP55:%.*]] = load float, float* [[T_VAR15]], align 4 756 // CHECK1-NEXT: [[CMP25:%.*]] = fcmp olt float [[TMP54]], [[TMP55]] 757 // CHECK1-NEXT: br i1 [[CMP25]], label [[COND_TRUE26:%.*]], label [[COND_FALSE27:%.*]] 758 // CHECK1: cond.true26: 759 // CHECK1-NEXT: [[TMP56:%.*]] = load float, float* [[_TMP24]], align 4 760 // CHECK1-NEXT: br label [[COND_END28]] 761 // CHECK1: cond.false27: 762 // CHECK1-NEXT: [[TMP57:%.*]] = load float, float* [[T_VAR15]], align 4 763 // CHECK1-NEXT: br label [[COND_END28]] 764 // CHECK1: cond.end28: 765 // CHECK1-NEXT: [[COND29:%.*]] = phi float [ [[TMP56]], [[COND_TRUE26]] ], [ [[TMP57]], [[COND_FALSE27]] ] 766 // CHECK1-NEXT: store float [[COND29]], float* [[ATOMIC_TEMP23]], align 4 767 // CHECK1-NEXT: [[TMP58:%.*]] = load i32, i32* [[TMP52]], align 4 768 // CHECK1-NEXT: [[TMP59:%.*]] = bitcast float* [[TMP5]] to i32* 769 // CHECK1-NEXT: [[TMP60:%.*]] = cmpxchg i32* [[TMP59]], i32 [[TMP51]], i32 [[TMP58]] monotonic monotonic, align 4 770 // CHECK1-NEXT: [[TMP61]] = extractvalue { i32, i1 } [[TMP60]], 0 771 // CHECK1-NEXT: [[TMP62:%.*]] = extractvalue { i32, i1 } [[TMP60]], 1 772 // CHECK1-NEXT: br i1 [[TMP62]], label [[ATOMIC_EXIT30:%.*]], label [[ATOMIC_CONT22]] 773 // CHECK1: atomic_exit30: 774 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 775 // CHECK1: .omp.reduction.default: 776 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR5]] 777 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR5]] 778 // CHECK1-NEXT: ret void 779 // 780 // 781 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 782 // CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { 783 // CHECK1-NEXT: entry: 784 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 785 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 786 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 4 787 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 788 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 789 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 790 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [4 x i8*]* 791 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 792 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [4 x i8*]* 793 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP5]], i64 0, i64 0 794 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 795 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to float* 796 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 0 797 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 798 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to float* 799 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP5]], i64 0, i64 1 800 // CHECK1-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8 801 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to %struct.S* 802 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 1 803 // CHECK1-NEXT: [[TMP16:%.*]] = load i8*, i8** [[TMP15]], align 8 804 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8* [[TMP16]] to %struct.S* 805 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP5]], i64 0, i64 2 806 // CHECK1-NEXT: [[TMP19:%.*]] = load i8*, i8** [[TMP18]], align 8 807 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8* [[TMP19]] to %struct.S* 808 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 2 809 // CHECK1-NEXT: [[TMP22:%.*]] = load i8*, i8** [[TMP21]], align 8 810 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8* [[TMP22]] to %struct.S* 811 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP5]], i64 0, i64 3 812 // CHECK1-NEXT: [[TMP25:%.*]] = load i8*, i8** [[TMP24]], align 8 813 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8* [[TMP25]] to float* 814 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 3 815 // CHECK1-NEXT: [[TMP28:%.*]] = load i8*, i8** [[TMP27]], align 8 816 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8* [[TMP28]] to float* 817 // CHECK1-NEXT: [[TMP30:%.*]] = load float, float* [[TMP11]], align 4 818 // CHECK1-NEXT: [[TMP31:%.*]] = load float, float* [[TMP8]], align 4 819 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP30]], [[TMP31]] 820 // CHECK1-NEXT: store float [[ADD]], float* [[TMP11]], align 4 821 // CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP14]]) 822 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP17]] to i8* 823 // CHECK1-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[CALL]] to i8* 824 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) 825 // CHECK1-NEXT: [[CALL2:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP23]]) 826 // CHECK1-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL2]], 0.000000e+00 827 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] 828 // CHECK1: land.rhs: 829 // CHECK1-NEXT: [[CALL3:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP20]]) 830 // CHECK1-NEXT: [[TOBOOL4:%.*]] = fcmp une float [[CALL3]], 0.000000e+00 831 // CHECK1-NEXT: br label [[LAND_END]] 832 // CHECK1: land.end: 833 // CHECK1-NEXT: [[TMP34:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ] 834 // CHECK1-NEXT: [[CONV:%.*]] = uitofp i1 [[TMP34]] to float 835 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]], float [[CONV]]) 836 // CHECK1-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP23]] to i8* 837 // CHECK1-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* 838 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) 839 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] 840 // CHECK1-NEXT: [[TMP37:%.*]] = load float, float* [[TMP29]], align 4 841 // CHECK1-NEXT: [[TMP38:%.*]] = load float, float* [[TMP26]], align 4 842 // CHECK1-NEXT: [[CMP:%.*]] = fcmp olt float [[TMP37]], [[TMP38]] 843 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 844 // CHECK1: cond.true: 845 // CHECK1-NEXT: [[TMP39:%.*]] = load float, float* [[TMP29]], align 4 846 // CHECK1-NEXT: br label [[COND_END:%.*]] 847 // CHECK1: cond.false: 848 // CHECK1-NEXT: [[TMP40:%.*]] = load float, float* [[TMP26]], align 4 849 // CHECK1-NEXT: br label [[COND_END]] 850 // CHECK1: cond.end: 851 // CHECK1-NEXT: [[COND:%.*]] = phi float [ [[TMP39]], [[COND_TRUE]] ], [ [[TMP40]], [[COND_FALSE]] ] 852 // CHECK1-NEXT: store float [[COND]], float* [[TMP29]], align 4 853 // CHECK1-NEXT: ret void 854 // 855 // 856 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEanERKS0_ 857 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR0]] align 2 { 858 // CHECK1-NEXT: entry: 859 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 860 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 861 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 862 // CHECK1-NEXT: store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8 863 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 864 // CHECK1-NEXT: ret %struct.S* [[THIS1]] 865 // 866 // 867 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEcvfEv 868 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR0]] align 2 { 869 // CHECK1-NEXT: entry: 870 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 871 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 872 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 873 // CHECK1-NEXT: ret float 0.000000e+00 874 // 875 // 876 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 877 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 878 // CHECK1-NEXT: entry: 879 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 880 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 881 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 882 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] 883 // CHECK1-NEXT: ret void 884 // 885 // 886 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 887 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]]) #[[ATTR1]] { 888 // CHECK1-NEXT: entry: 889 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 890 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 891 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 892 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca float*, align 8 893 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 894 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 895 // CHECK1-NEXT: [[VAR1_ADDR:%.*]] = alloca %struct.S*, align 8 896 // CHECK1-NEXT: [[T_VAR1_ADDR:%.*]] = alloca float*, align 8 897 // CHECK1-NEXT: [[T_VAR2:%.*]] = alloca float, align 4 898 // CHECK1-NEXT: [[VAR3:%.*]] = alloca [[STRUCT_S:%.*]], align 4 899 // CHECK1-NEXT: [[VAR14:%.*]] = alloca [[STRUCT_S]], align 4 900 // CHECK1-NEXT: [[T_VAR15:%.*]] = alloca float, align 4 901 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 902 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 903 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 904 // CHECK1-NEXT: store float* [[T_VAR]], float** [[T_VAR_ADDR]], align 8 905 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 906 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 907 // CHECK1-NEXT: store %struct.S* [[VAR1]], %struct.S** [[VAR1_ADDR]], align 8 908 // CHECK1-NEXT: store float* [[T_VAR1]], float** [[T_VAR1_ADDR]], align 8 909 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 910 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[T_VAR_ADDR]], align 8 911 // CHECK1-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 912 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 913 // CHECK1-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[VAR1_ADDR]], align 8 914 // CHECK1-NEXT: [[TMP5:%.*]] = load float*, float** [[T_VAR1_ADDR]], align 8 915 // CHECK1-NEXT: store float 0.000000e+00, float* [[T_VAR2]], align 4 916 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) 917 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) 918 // CHECK1-NEXT: store float 0x47EFFFFFE0000000, float* [[T_VAR15]], align 4 919 // CHECK1-NEXT: br label [[WHILE_COND:%.*]] 920 // CHECK1: while.cond: 921 // CHECK1-NEXT: br label [[WHILE_BODY:%.*]] 922 // CHECK1: while.body: 923 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[T_VAR2]], align 4 924 // CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32 925 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP0]], i64 0, i64 0 926 // CHECK1-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4 927 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i64 0, i64 0 928 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* 929 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR3]] to i8* 930 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false) 931 // CHECK1-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP4:![0-9]+]] 932 // 933 // 934 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 935 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], { float, float }* nonnull align 4 dereferenceable(8) [[CF:%.*]]) #[[ATTR1]] { 936 // CHECK1-NEXT: entry: 937 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 938 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 939 // CHECK1-NEXT: [[CF_ADDR:%.*]] = alloca { float, float }*, align 8 940 // CHECK1-NEXT: [[CF1:%.*]] = alloca { float, float }, align 4 941 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 942 // CHECK1-NEXT: [[ATOMIC_TEMP:%.*]] = alloca { float, float }, align 4 943 // CHECK1-NEXT: [[ATOMIC_TEMP10:%.*]] = alloca { float, float }, align 4 944 // CHECK1-NEXT: [[TMP:%.*]] = alloca { float, float }, align 4 945 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 946 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 947 // CHECK1-NEXT: store { float, float }* [[CF]], { float, float }** [[CF_ADDR]], align 8 948 // CHECK1-NEXT: [[TMP0:%.*]] = load { float, float }*, { float, float }** [[CF_ADDR]], align 8 949 // CHECK1-NEXT: [[CF1_REALP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[CF1]], i32 0, i32 0 950 // CHECK1-NEXT: [[CF1_IMAGP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[CF1]], i32 0, i32 1 951 // CHECK1-NEXT: store float 0.000000e+00, float* [[CF1_REALP]], align 4 952 // CHECK1-NEXT: store float 0.000000e+00, float* [[CF1_IMAGP]], align 4 953 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 954 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast { float, float }* [[CF1]] to i8* 955 // CHECK1-NEXT: store i8* [[TMP2]], i8** [[TMP1]], align 8 956 // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 957 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 958 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 959 // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 1, i64 8, i8* [[TMP5]], void (i8*, i8*)* @.omp.reduction.reduction_func.5, [8 x i32]* @.gomp_critical_user_.reduction.var) 960 // CHECK1-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 961 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 962 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 963 // CHECK1-NEXT: ] 964 // CHECK1: .omp.reduction.case1: 965 // CHECK1-NEXT: [[DOTREALP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP0]], i32 0, i32 0 966 // CHECK1-NEXT: [[DOTREAL:%.*]] = load float, float* [[DOTREALP]], align 4 967 // CHECK1-NEXT: [[DOTIMAGP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP0]], i32 0, i32 1 968 // CHECK1-NEXT: [[DOTIMAG:%.*]] = load float, float* [[DOTIMAGP]], align 4 969 // CHECK1-NEXT: [[CF1_REALP2:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[CF1]], i32 0, i32 0 970 // CHECK1-NEXT: [[CF1_REAL:%.*]] = load float, float* [[CF1_REALP2]], align 4 971 // CHECK1-NEXT: [[CF1_IMAGP3:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[CF1]], i32 0, i32 1 972 // CHECK1-NEXT: [[CF1_IMAG:%.*]] = load float, float* [[CF1_IMAGP3]], align 4 973 // CHECK1-NEXT: [[ADD_R:%.*]] = fadd float [[DOTREAL]], [[CF1_REAL]] 974 // CHECK1-NEXT: [[ADD_I:%.*]] = fadd float [[DOTIMAG]], [[CF1_IMAG]] 975 // CHECK1-NEXT: [[DOTREALP4:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP0]], i32 0, i32 0 976 // CHECK1-NEXT: [[DOTIMAGP5:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP0]], i32 0, i32 1 977 // CHECK1-NEXT: store float [[ADD_R]], float* [[DOTREALP4]], align 4 978 // CHECK1-NEXT: store float [[ADD_I]], float* [[DOTIMAGP5]], align 4 979 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], [8 x i32]* @.gomp_critical_user_.reduction.var) 980 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 981 // CHECK1: .omp.reduction.case2: 982 // CHECK1-NEXT: [[CF1_REALP6:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[CF1]], i32 0, i32 0 983 // CHECK1-NEXT: [[CF1_REAL7:%.*]] = load float, float* [[CF1_REALP6]], align 4 984 // CHECK1-NEXT: [[CF1_IMAGP8:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[CF1]], i32 0, i32 1 985 // CHECK1-NEXT: [[CF1_IMAG9:%.*]] = load float, float* [[CF1_IMAGP8]], align 4 986 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast { float, float }* [[TMP0]] to i8* 987 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast { float, float }* [[ATOMIC_TEMP]] to i8* 988 // CHECK1-NEXT: call void @__atomic_load(i64 8, i8* [[TMP7]], i8* [[TMP8]], i32 0) 989 // CHECK1-NEXT: br label [[ATOMIC_CONT:%.*]] 990 // CHECK1: atomic_cont: 991 // CHECK1-NEXT: [[ATOMIC_TEMP_REALP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[ATOMIC_TEMP]], i32 0, i32 0 992 // CHECK1-NEXT: [[ATOMIC_TEMP_REAL:%.*]] = load float, float* [[ATOMIC_TEMP_REALP]], align 4 993 // CHECK1-NEXT: [[ATOMIC_TEMP_IMAGP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[ATOMIC_TEMP]], i32 0, i32 1 994 // CHECK1-NEXT: [[ATOMIC_TEMP_IMAG:%.*]] = load float, float* [[ATOMIC_TEMP_IMAGP]], align 4 995 // CHECK1-NEXT: [[TMP_REALP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP]], i32 0, i32 0 996 // CHECK1-NEXT: [[TMP_IMAGP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP]], i32 0, i32 1 997 // CHECK1-NEXT: store float [[ATOMIC_TEMP_REAL]], float* [[TMP_REALP]], align 4 998 // CHECK1-NEXT: store float [[ATOMIC_TEMP_IMAG]], float* [[TMP_IMAGP]], align 4 999 // CHECK1-NEXT: [[TMP_REALP11:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP]], i32 0, i32 0 1000 // CHECK1-NEXT: [[TMP_REAL:%.*]] = load float, float* [[TMP_REALP11]], align 4 1001 // CHECK1-NEXT: [[TMP_IMAGP12:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP]], i32 0, i32 1 1002 // CHECK1-NEXT: [[TMP_IMAG:%.*]] = load float, float* [[TMP_IMAGP12]], align 4 1003 // CHECK1-NEXT: [[CF1_REALP13:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[CF1]], i32 0, i32 0 1004 // CHECK1-NEXT: [[CF1_REAL14:%.*]] = load float, float* [[CF1_REALP13]], align 4 1005 // CHECK1-NEXT: [[CF1_IMAGP15:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[CF1]], i32 0, i32 1 1006 // CHECK1-NEXT: [[CF1_IMAG16:%.*]] = load float, float* [[CF1_IMAGP15]], align 4 1007 // CHECK1-NEXT: [[ADD_R17:%.*]] = fadd float [[TMP_REAL]], [[CF1_REAL14]] 1008 // CHECK1-NEXT: [[ADD_I18:%.*]] = fadd float [[TMP_IMAG]], [[CF1_IMAG16]] 1009 // CHECK1-NEXT: [[ATOMIC_TEMP10_REALP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[ATOMIC_TEMP10]], i32 0, i32 0 1010 // CHECK1-NEXT: [[ATOMIC_TEMP10_IMAGP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[ATOMIC_TEMP10]], i32 0, i32 1 1011 // CHECK1-NEXT: store float [[ADD_R17]], float* [[ATOMIC_TEMP10_REALP]], align 4 1012 // CHECK1-NEXT: store float [[ADD_I18]], float* [[ATOMIC_TEMP10_IMAGP]], align 4 1013 // CHECK1-NEXT: [[TMP9:%.*]] = bitcast { float, float }* [[TMP0]] to i8* 1014 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast { float, float }* [[ATOMIC_TEMP]] to i8* 1015 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast { float, float }* [[ATOMIC_TEMP10]] to i8* 1016 // CHECK1-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, i8* [[TMP9]], i8* [[TMP10]], i8* [[TMP11]], i32 0, i32 0) 1017 // CHECK1-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] 1018 // CHECK1: atomic_exit: 1019 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1020 // CHECK1: .omp.reduction.default: 1021 // CHECK1-NEXT: ret void 1022 // 1023 // 1024 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 1025 // CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { 1026 // CHECK1-NEXT: entry: 1027 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1028 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 1029 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1030 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 1031 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 1032 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 1033 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 1034 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 1035 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 1036 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 1037 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to { float, float }* 1038 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 1039 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 1040 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to { float, float }* 1041 // CHECK1-NEXT: [[DOTREALP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP11]], i32 0, i32 0 1042 // CHECK1-NEXT: [[DOTREAL:%.*]] = load float, float* [[DOTREALP]], align 4 1043 // CHECK1-NEXT: [[DOTIMAGP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP11]], i32 0, i32 1 1044 // CHECK1-NEXT: [[DOTIMAG:%.*]] = load float, float* [[DOTIMAGP]], align 4 1045 // CHECK1-NEXT: [[DOTREALP2:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP8]], i32 0, i32 0 1046 // CHECK1-NEXT: [[DOTREAL3:%.*]] = load float, float* [[DOTREALP2]], align 4 1047 // CHECK1-NEXT: [[DOTIMAGP4:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP8]], i32 0, i32 1 1048 // CHECK1-NEXT: [[DOTIMAG5:%.*]] = load float, float* [[DOTIMAGP4]], align 4 1049 // CHECK1-NEXT: [[ADD_R:%.*]] = fadd float [[DOTREAL]], [[DOTREAL3]] 1050 // CHECK1-NEXT: [[ADD_I:%.*]] = fadd float [[DOTIMAG]], [[DOTIMAG5]] 1051 // CHECK1-NEXT: [[DOTREALP6:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP11]], i32 0, i32 0 1052 // CHECK1-NEXT: [[DOTIMAGP7:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP11]], i32 0, i32 1 1053 // CHECK1-NEXT: store float [[ADD_R]], float* [[DOTREALP6]], align 4 1054 // CHECK1-NEXT: store float [[ADD_I]], float* [[DOTIMAGP7]], align 4 1055 // CHECK1-NEXT: ret void 1056 // 1057 // 1058 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1059 // CHECK1-SAME: () #[[ATTR0]] { 1060 // CHECK1-NEXT: entry: 1061 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1062 // CHECK1-NEXT: [[T:%.*]] = alloca i32, align 4 1063 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1064 // CHECK1-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 1065 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 1066 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1067 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1068 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1069 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 1070 // CHECK1-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 128 1071 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 1072 // CHECK1-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) 1073 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 128 1074 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1075 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 1076 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 1077 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 1078 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 1079 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 1080 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 1081 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) 1082 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*, %struct.S.0*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]], %struct.S.0* [[VAR1]], i32* [[T_VAR1]]) 1083 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 1084 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR5]] 1085 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] 1086 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1087 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1088 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1089 // CHECK1: arraydestroy.body: 1090 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1091 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1092 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] 1093 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1094 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1095 // CHECK1: arraydestroy.done1: 1096 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] 1097 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 1098 // CHECK1-NEXT: ret i32 [[TMP2]] 1099 // 1100 // 1101 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 1102 // CHECK1-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 1103 // CHECK1-NEXT: entry: 1104 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 1105 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 1106 // CHECK1-NEXT: [[A2:%.*]] = alloca i32*, align 8 1107 // CHECK1-NEXT: [[B4:%.*]] = alloca i32, align 4 1108 // CHECK1-NEXT: [[C5:%.*]] = alloca i32*, align 8 1109 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 1110 // CHECK1-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 1111 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 1112 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 1113 // CHECK1-NEXT: store i32 0, i32* [[A]], align 8 1114 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 1115 // CHECK1-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 1116 // CHECK1-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 1117 // CHECK1-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 1118 // CHECK1-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 1119 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 1120 // CHECK1-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 1121 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 1122 // CHECK1-NEXT: store i32* [[A3]], i32** [[A2]], align 8 1123 // CHECK1-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 1124 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 1125 // CHECK1-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 1126 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 1127 // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 1128 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i32*, i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i32* [[TMP2]], i32* [[B4]], i32* [[TMP3]]) 1129 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[B4]], align 4 1130 // CHECK1-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 1131 // CHECK1-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8 1132 // CHECK1-NEXT: [[BF_LOAD8:%.*]] = load i8, i8* [[B7]], align 4 1133 // CHECK1-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP5]], 15 1134 // CHECK1-NEXT: [[BF_CLEAR9:%.*]] = and i8 [[BF_LOAD8]], -16 1135 // CHECK1-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR9]], [[BF_VALUE]] 1136 // CHECK1-NEXT: store i8 [[BF_SET]], i8* [[B7]], align 4 1137 // CHECK1-NEXT: ret void 1138 // 1139 // 1140 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 1141 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { 1142 // CHECK1-NEXT: entry: 1143 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1144 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1145 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 1146 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 1147 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 1148 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 1149 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32*, align 8 1150 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 1151 // CHECK1-NEXT: [[A2:%.*]] = alloca i32, align 4 1152 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 1153 // CHECK1-NEXT: [[B4:%.*]] = alloca i32, align 4 1154 // CHECK1-NEXT: [[C5:%.*]] = alloca i32, align 4 1155 // CHECK1-NEXT: [[_TMP6:%.*]] = alloca i32*, align 8 1156 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [3 x i8*], align 8 1157 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1158 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1159 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 1160 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 1161 // CHECK1-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 1162 // CHECK1-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 1163 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 1164 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 1165 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[B_ADDR]], align 8 1166 // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C_ADDR]], align 8 1167 // CHECK1-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8 1168 // CHECK1-NEXT: store i32* [[TMP3]], i32** [[_TMP1]], align 8 1169 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 1170 // CHECK1-NEXT: store i32 0, i32* [[A2]], align 4 1171 // CHECK1-NEXT: store i32* [[A2]], i32** [[_TMP3]], align 8 1172 // CHECK1-NEXT: store i32 0, i32* [[B4]], align 4 1173 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[_TMP1]], align 8 1174 // CHECK1-NEXT: store i32 0, i32* [[C5]], align 4 1175 // CHECK1-NEXT: store i32* [[C5]], i32** [[_TMP6]], align 8 1176 // CHECK1-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP3]], align 8 1177 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 1178 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 1179 // CHECK1-NEXT: store i32 [[INC]], i32* [[TMP6]], align 4 1180 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[B4]], align 4 1181 // CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 1182 // CHECK1-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 1183 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[_TMP6]], align 8 1184 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 1185 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 1186 // CHECK1-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 1187 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 1188 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i32* [[A2]] to i8* 1189 // CHECK1-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 8 1190 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1 1191 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i32* [[B4]] to i8* 1192 // CHECK1-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 1193 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 2 1194 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i32* [[C5]] to i8* 1195 // CHECK1-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 1196 // CHECK1-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1197 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 1198 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 1199 // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 3, i64 24, i8* [[TMP19]], void (i8*, i8*)* @.omp.reduction.reduction_func.7, [8 x i32]* @.gomp_critical_user_.reduction.var) 1200 // CHECK1-NEXT: switch i32 [[TMP20]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1201 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1202 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1203 // CHECK1-NEXT: ] 1204 // CHECK1: .omp.reduction.case1: 1205 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP4]], align 4 1206 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[A2]], align 4 1207 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] 1208 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP4]], align 4 1209 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP2]], align 4 1210 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[B4]], align 4 1211 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] 1212 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[TMP2]], align 4 1213 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP5]], align 4 1214 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[C5]], align 4 1215 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] 1216 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[TMP5]], align 4 1217 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1218 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1219 // CHECK1: .omp.reduction.case2: 1220 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[A2]], align 4 1221 // CHECK1-NEXT: [[TMP28:%.*]] = atomicrmw add i32* [[TMP4]], i32 [[TMP27]] monotonic, align 4 1222 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[B4]], align 4 1223 // CHECK1-NEXT: [[TMP30:%.*]] = atomicrmw add i32* [[TMP2]], i32 [[TMP29]] monotonic, align 4 1224 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[C5]], align 4 1225 // CHECK1-NEXT: [[TMP32:%.*]] = atomicrmw add i32* [[TMP5]], i32 [[TMP31]] monotonic, align 4 1226 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1227 // CHECK1: .omp.reduction.default: 1228 // CHECK1-NEXT: ret void 1229 // 1230 // 1231 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.7 1232 // CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { 1233 // CHECK1-NEXT: entry: 1234 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1235 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 1236 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1237 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 1238 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 1239 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [3 x i8*]* 1240 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 1241 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [3 x i8*]* 1242 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP5]], i64 0, i64 0 1243 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 1244 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 1245 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP3]], i64 0, i64 0 1246 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 1247 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 1248 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP5]], i64 0, i64 1 1249 // CHECK1-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8 1250 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to i32* 1251 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP3]], i64 0, i64 1 1252 // CHECK1-NEXT: [[TMP16:%.*]] = load i8*, i8** [[TMP15]], align 8 1253 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8* [[TMP16]] to i32* 1254 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP5]], i64 0, i64 2 1255 // CHECK1-NEXT: [[TMP19:%.*]] = load i8*, i8** [[TMP18]], align 8 1256 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8* [[TMP19]] to i32* 1257 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP3]], i64 0, i64 2 1258 // CHECK1-NEXT: [[TMP22:%.*]] = load i8*, i8** [[TMP21]], align 8 1259 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8* [[TMP22]] to i32* 1260 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP11]], align 4 1261 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP8]], align 4 1262 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] 1263 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 1264 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP17]], align 4 1265 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP14]], align 4 1266 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] 1267 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[TMP17]], align 4 1268 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP23]], align 4 1269 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP20]], align 4 1270 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 1271 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[TMP23]], align 4 1272 // CHECK1-NEXT: ret void 1273 // 1274 // 1275 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1276 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 1277 // CHECK1-NEXT: entry: 1278 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1279 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1280 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1281 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1282 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 1283 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1284 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4 1285 // CHECK1-NEXT: ret void 1286 // 1287 // 1288 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1289 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 1290 // CHECK1-NEXT: entry: 1291 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1292 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1293 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1294 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1295 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1296 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1297 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1298 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 1299 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1300 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1301 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 1302 // CHECK1-NEXT: ret void 1303 // 1304 // 1305 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1306 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 1307 // CHECK1-NEXT: entry: 1308 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1309 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1310 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1311 // CHECK1-NEXT: ret void 1312 // 1313 // 1314 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1315 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 1316 // CHECK1-NEXT: entry: 1317 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1318 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1319 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1320 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 1321 // CHECK1-NEXT: ret void 1322 // 1323 // 1324 // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev 1325 // CHECK1-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 1326 // CHECK1-NEXT: entry: 1327 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 1328 // CHECK1-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 1329 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 1330 // CHECK1-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) 1331 // CHECK1-NEXT: ret void 1332 // 1333 // 1334 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1335 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 1336 // CHECK1-NEXT: entry: 1337 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1338 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1339 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1340 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1341 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1342 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1343 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 1344 // CHECK1-NEXT: ret void 1345 // 1346 // 1347 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 1348 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]]) #[[ATTR1]] { 1349 // CHECK1-NEXT: entry: 1350 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1351 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1352 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1353 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 1354 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 1355 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 1356 // CHECK1-NEXT: [[VAR1_ADDR:%.*]] = alloca %struct.S.0*, align 8 1357 // CHECK1-NEXT: [[T_VAR1_ADDR:%.*]] = alloca i32*, align 8 1358 // CHECK1-NEXT: [[T_VAR2:%.*]] = alloca i32, align 128 1359 // CHECK1-NEXT: [[VAR3:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 1360 // CHECK1-NEXT: [[VAR14:%.*]] = alloca [[STRUCT_S_0]], align 128 1361 // CHECK1-NEXT: [[T_VAR15:%.*]] = alloca i32, align 128 1362 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [4 x i8*], align 8 1363 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4 1364 // CHECK1-NEXT: [[REF_TMP11:%.*]] = alloca [[STRUCT_S_0]], align 4 1365 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1366 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1367 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1368 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 1369 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1370 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 1371 // CHECK1-NEXT: store %struct.S.0* [[VAR1]], %struct.S.0** [[VAR1_ADDR]], align 8 1372 // CHECK1-NEXT: store i32* [[T_VAR1]], i32** [[T_VAR1_ADDR]], align 8 1373 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1374 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 1375 // CHECK1-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1376 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 1377 // CHECK1-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR1_ADDR]], align 8 1378 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[T_VAR1_ADDR]], align 8 1379 // CHECK1-NEXT: store i32 0, i32* [[T_VAR2]], align 128 1380 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) 1381 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) 1382 // CHECK1-NEXT: store i32 2147483647, i32* [[T_VAR15]], align 128 1383 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR2]], align 128 1384 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP0]], i64 0, i64 0 1385 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 1386 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i64 0, i64 0 1387 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* 1388 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast %struct.S.0* [[VAR3]] to i8* 1389 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 128 [[TMP8]], i64 4, i1 false) 1390 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 1391 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i32* [[T_VAR2]] to i8* 1392 // CHECK1-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 8 1393 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1 1394 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[VAR3]] to i8* 1395 // CHECK1-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 8 1396 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 2 1397 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[VAR14]] to i8* 1398 // CHECK1-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 1399 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 3 1400 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i32* [[T_VAR15]] to i8* 1401 // CHECK1-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 1402 // CHECK1-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1403 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 1404 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 1405 // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 4, i64 32, i8* [[TMP19]], void (i8*, i8*)* @.omp.reduction.reduction_func.9, [8 x i32]* @.gomp_critical_user_.reduction.var) 1406 // CHECK1-NEXT: switch i32 [[TMP20]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1407 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1408 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1409 // CHECK1-NEXT: ] 1410 // CHECK1: .omp.reduction.case1: 1411 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP1]], align 128 1412 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR2]], align 128 1413 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] 1414 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP1]], align 128 1415 // CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) 1416 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8* 1417 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast %struct.S.0* [[CALL]] to i8* 1418 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP23]], i8* align 4 [[TMP24]], i64 4, i1 false) 1419 // CHECK1-NEXT: [[CALL7:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP4]]) 1420 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL7]], 0 1421 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] 1422 // CHECK1: land.rhs: 1423 // CHECK1-NEXT: [[CALL8:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) 1424 // CHECK1-NEXT: [[TOBOOL9:%.*]] = icmp ne i32 [[CALL8]], 0 1425 // CHECK1-NEXT: br label [[LAND_END]] 1426 // CHECK1: land.end: 1427 // CHECK1-NEXT: [[TMP25:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL9]], [[LAND_RHS]] ] 1428 // CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TMP25]] to i32 1429 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[CONV]]) 1430 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* 1431 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* 1432 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) 1433 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] 1434 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP5]], align 128 1435 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[T_VAR15]], align 128 1436 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP28]], [[TMP29]] 1437 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1438 // CHECK1: cond.true: 1439 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP5]], align 128 1440 // CHECK1-NEXT: br label [[COND_END:%.*]] 1441 // CHECK1: cond.false: 1442 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[T_VAR15]], align 128 1443 // CHECK1-NEXT: br label [[COND_END]] 1444 // CHECK1: cond.end: 1445 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP30]], [[COND_TRUE]] ], [ [[TMP31]], [[COND_FALSE]] ] 1446 // CHECK1-NEXT: store i32 [[COND]], i32* [[TMP5]], align 128 1447 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1448 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1449 // CHECK1: .omp.reduction.case2: 1450 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[T_VAR2]], align 128 1451 // CHECK1-NEXT: [[TMP33:%.*]] = atomicrmw add i32* [[TMP1]], i32 [[TMP32]] monotonic, align 4 1452 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) 1453 // CHECK1-NEXT: [[CALL10:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) 1454 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8* 1455 // CHECK1-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[CALL10]] to i8* 1456 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) 1457 // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) 1458 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) 1459 // CHECK1-NEXT: [[CALL12:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP4]]) 1460 // CHECK1-NEXT: [[TOBOOL13:%.*]] = icmp ne i32 [[CALL12]], 0 1461 // CHECK1-NEXT: br i1 [[TOBOOL13]], label [[LAND_RHS14:%.*]], label [[LAND_END17:%.*]] 1462 // CHECK1: land.rhs14: 1463 // CHECK1-NEXT: [[CALL15:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) 1464 // CHECK1-NEXT: [[TOBOOL16:%.*]] = icmp ne i32 [[CALL15]], 0 1465 // CHECK1-NEXT: br label [[LAND_END17]] 1466 // CHECK1: land.end17: 1467 // CHECK1-NEXT: [[TMP36:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE2]] ], [ [[TOBOOL16]], [[LAND_RHS14]] ] 1468 // CHECK1-NEXT: [[CONV18:%.*]] = zext i1 [[TMP36]] to i32 1469 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP11]], i32 [[CONV18]]) 1470 // CHECK1-NEXT: [[TMP37:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* 1471 // CHECK1-NEXT: [[TMP38:%.*]] = bitcast %struct.S.0* [[REF_TMP11]] to i8* 1472 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP37]], i8* align 4 [[TMP38]], i64 4, i1 false) 1473 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP11]]) #[[ATTR5]] 1474 // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) 1475 // CHECK1-NEXT: [[TMP39:%.*]] = load i32, i32* [[T_VAR15]], align 128 1476 // CHECK1-NEXT: [[TMP40:%.*]] = atomicrmw min i32* [[TMP5]], i32 [[TMP39]] monotonic, align 4 1477 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1478 // CHECK1: .omp.reduction.default: 1479 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR5]] 1480 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR5]] 1481 // CHECK1-NEXT: ret void 1482 // 1483 // 1484 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.9 1485 // CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { 1486 // CHECK1-NEXT: entry: 1487 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1488 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 1489 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1490 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1491 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 1492 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 1493 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [4 x i8*]* 1494 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 1495 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [4 x i8*]* 1496 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP5]], i64 0, i64 0 1497 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 1498 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 1499 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 0 1500 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 1501 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 1502 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP5]], i64 0, i64 1 1503 // CHECK1-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8 1504 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to %struct.S.0* 1505 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 1 1506 // CHECK1-NEXT: [[TMP16:%.*]] = load i8*, i8** [[TMP15]], align 8 1507 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8* [[TMP16]] to %struct.S.0* 1508 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP5]], i64 0, i64 2 1509 // CHECK1-NEXT: [[TMP19:%.*]] = load i8*, i8** [[TMP18]], align 8 1510 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8* [[TMP19]] to %struct.S.0* 1511 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 2 1512 // CHECK1-NEXT: [[TMP22:%.*]] = load i8*, i8** [[TMP21]], align 8 1513 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8* [[TMP22]] to %struct.S.0* 1514 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP5]], i64 0, i64 3 1515 // CHECK1-NEXT: [[TMP25:%.*]] = load i8*, i8** [[TMP24]], align 8 1516 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8* [[TMP25]] to i32* 1517 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 3 1518 // CHECK1-NEXT: [[TMP28:%.*]] = load i8*, i8** [[TMP27]], align 8 1519 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8* [[TMP28]] to i32* 1520 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP11]], align 128 1521 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP8]], align 128 1522 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 1523 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 128 1524 // CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP17]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP14]]) 1525 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* 1526 // CHECK1-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[CALL]] to i8* 1527 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) 1528 // CHECK1-NEXT: [[CALL2:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP23]]) 1529 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL2]], 0 1530 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] 1531 // CHECK1: land.rhs: 1532 // CHECK1-NEXT: [[CALL3:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP20]]) 1533 // CHECK1-NEXT: [[TOBOOL4:%.*]] = icmp ne i32 [[CALL3]], 0 1534 // CHECK1-NEXT: br label [[LAND_END]] 1535 // CHECK1: land.end: 1536 // CHECK1-NEXT: [[TMP34:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ] 1537 // CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TMP34]] to i32 1538 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[CONV]]) 1539 // CHECK1-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP23]] to i8* 1540 // CHECK1-NEXT: [[TMP36:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* 1541 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) 1542 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] 1543 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP29]], align 128 1544 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, i32* [[TMP26]], align 128 1545 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]] 1546 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1547 // CHECK1: cond.true: 1548 // CHECK1-NEXT: [[TMP39:%.*]] = load i32, i32* [[TMP29]], align 128 1549 // CHECK1-NEXT: br label [[COND_END:%.*]] 1550 // CHECK1: cond.false: 1551 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, i32* [[TMP26]], align 128 1552 // CHECK1-NEXT: br label [[COND_END]] 1553 // CHECK1: cond.end: 1554 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP39]], [[COND_TRUE]] ], [ [[TMP40]], [[COND_FALSE]] ] 1555 // CHECK1-NEXT: store i32 [[COND]], i32* [[TMP29]], align 128 1556 // CHECK1-NEXT: ret void 1557 // 1558 // 1559 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEanERKS0_ 1560 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR0]] align 2 { 1561 // CHECK1-NEXT: entry: 1562 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1563 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 1564 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1565 // CHECK1-NEXT: store %struct.S.0* [[TMP0]], %struct.S.0** [[DOTADDR]], align 8 1566 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1567 // CHECK1-NEXT: ret %struct.S.0* [[THIS1]] 1568 // 1569 // 1570 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEcviEv 1571 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR0]] align 2 { 1572 // CHECK1-NEXT: entry: 1573 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1574 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1575 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1576 // CHECK1-NEXT: ret i32 0 1577 // 1578 // 1579 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1580 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 1581 // CHECK1-NEXT: entry: 1582 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1583 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1584 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1585 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] 1586 // CHECK1-NEXT: ret void 1587 // 1588 // 1589 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1590 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 1591 // CHECK1-NEXT: entry: 1592 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1593 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1594 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1595 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1596 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 1597 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1598 // CHECK1-NEXT: ret void 1599 // 1600 // 1601 // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev 1602 // CHECK1-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 1603 // CHECK1-NEXT: entry: 1604 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 1605 // CHECK1-NEXT: [[A2:%.*]] = alloca i32*, align 8 1606 // CHECK1-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 1607 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 1608 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 1609 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1610 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 1611 // CHECK1-NEXT: store i32* [[A3]], i32** [[A2]], align 8 1612 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 1613 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.SST* [[THIS1]], i32* [[TMP0]]) 1614 // CHECK1-NEXT: ret void 1615 // 1616 // 1617 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 1618 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1]] { 1619 // CHECK1-NEXT: entry: 1620 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1621 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1622 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 1623 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 1624 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32*, align 8 1625 // CHECK1-NEXT: [[A1:%.*]] = alloca i32, align 4 1626 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 1627 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 1628 // CHECK1-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4 1629 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 1630 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1631 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1632 // CHECK1-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 1633 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 1634 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 1635 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 1636 // CHECK1-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8 1637 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 1638 // CHECK1-NEXT: store i32 1, i32* [[A1]], align 4 1639 // CHECK1-NEXT: store i32* [[A1]], i32** [[_TMP2]], align 8 1640 // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[_TMP2]], align 8 1641 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 1642 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 1643 // CHECK1-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 1644 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 1645 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i32* [[A1]] to i8* 1646 // CHECK1-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8 1647 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1648 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 1649 // CHECK1-NEXT: [[TMP9:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 1650 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 1, i64 8, i8* [[TMP9]], void (i8*, i8*)* @.omp.reduction.reduction_func.11, [8 x i32]* @.gomp_critical_user_.reduction.var) 1651 // CHECK1-NEXT: switch i32 [[TMP10]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1652 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1653 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1654 // CHECK1-NEXT: ] 1655 // CHECK1: .omp.reduction.case1: 1656 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP2]], align 4 1657 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[A1]], align 4 1658 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], [[TMP12]] 1659 // CHECK1-NEXT: store i32 [[MUL]], i32* [[TMP2]], align 4 1660 // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1661 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1662 // CHECK1: .omp.reduction.case2: 1663 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[A1]], align 4 1664 // CHECK1-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i32, i32* [[TMP2]] monotonic, align 4 1665 // CHECK1-NEXT: br label [[ATOMIC_CONT:%.*]] 1666 // CHECK1: atomic_cont: 1667 // CHECK1-NEXT: [[TMP14:%.*]] = phi i32 [ [[ATOMIC_LOAD]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[TMP19:%.*]], [[ATOMIC_CONT]] ] 1668 // CHECK1-NEXT: store i32 [[TMP14]], i32* [[_TMP3]], align 4 1669 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[_TMP3]], align 4 1670 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[A1]], align 4 1671 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[TMP15]], [[TMP16]] 1672 // CHECK1-NEXT: store i32 [[MUL4]], i32* [[ATOMIC_TEMP]], align 4 1673 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[ATOMIC_TEMP]], align 4 1674 // CHECK1-NEXT: [[TMP18:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP14]], i32 [[TMP17]] monotonic monotonic, align 4 1675 // CHECK1-NEXT: [[TMP19]] = extractvalue { i32, i1 } [[TMP18]], 0 1676 // CHECK1-NEXT: [[TMP20:%.*]] = extractvalue { i32, i1 } [[TMP18]], 1 1677 // CHECK1-NEXT: br i1 [[TMP20]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] 1678 // CHECK1: atomic_exit: 1679 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1680 // CHECK1: .omp.reduction.default: 1681 // CHECK1-NEXT: ret void 1682 // 1683 // 1684 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.11 1685 // CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { 1686 // CHECK1-NEXT: entry: 1687 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1688 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 1689 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1690 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 1691 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 1692 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 1693 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 1694 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 1695 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 1696 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 1697 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 1698 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 1699 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 1700 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 1701 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 1702 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 1703 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]] 1704 // CHECK1-NEXT: store i32 [[MUL]], i32* [[TMP11]], align 4 1705 // CHECK1-NEXT: ret void 1706 // 1707 // 1708 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1709 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 1710 // CHECK1-NEXT: entry: 1711 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1712 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1713 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1714 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1715 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1716 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1717 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1718 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 1719 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1720 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1721 // CHECK1-NEXT: ret void 1722 // 1723 // 1724 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1725 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 1726 // CHECK1-NEXT: entry: 1727 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1728 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1729 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1730 // CHECK1-NEXT: ret void 1731 // 1732 // 1733 // CHECK2-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs 1734 // CHECK2-SAME: (i16* [[X:%.*]]) #[[ATTR0:[0-9]+]] { 1735 // CHECK2-NEXT: entry: 1736 // CHECK2-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 1737 // CHECK2-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 1738 // CHECK2-NEXT: [[TMP0:%.*]] = load i16*, i16** [[X_ADDR]], align 8 1739 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined. to void (i32*, i32*, ...)*), i16* [[TMP0]]) 1740 // CHECK2-NEXT: ret void 1741 // 1742 // 1743 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 1744 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* [[X:%.*]]) #[[ATTR1:[0-9]+]] { 1745 // CHECK2-NEXT: entry: 1746 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1747 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1748 // CHECK2-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 1749 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1750 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1751 // CHECK2-NEXT: [[TMP:%.*]] = alloca i16*, align 8 1752 // CHECK2-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [2 x i8*], align 8 1753 // CHECK2-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i16, align 2 1754 // CHECK2-NEXT: [[_TMP13:%.*]] = alloca i16, align 2 1755 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1756 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1757 // CHECK2-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 1758 // CHECK2-NEXT: [[TMP0:%.*]] = load i16*, i16** [[X_ADDR]], align 8 1759 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP0]], i64 0 1760 // CHECK2-NEXT: [[TMP1:%.*]] = load i16*, i16** [[X_ADDR]], align 8 1761 // CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i16, i16* [[TMP1]], i64 0 1762 // CHECK2-NEXT: [[TMP2:%.*]] = ptrtoint i16* [[ARRAYIDX1]] to i64 1763 // CHECK2-NEXT: [[TMP3:%.*]] = ptrtoint i16* [[ARRAYIDX]] to i64 1764 // CHECK2-NEXT: [[TMP4:%.*]] = sub i64 [[TMP2]], [[TMP3]] 1765 // CHECK2-NEXT: [[TMP5:%.*]] = sdiv exact i64 [[TMP4]], ptrtoint (i16* getelementptr (i16, i16* null, i32 1) to i64) 1766 // CHECK2-NEXT: [[TMP6:%.*]] = add nuw i64 [[TMP5]], 1 1767 // CHECK2-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], ptrtoint (i16* getelementptr (i16, i16* null, i32 1) to i64) 1768 // CHECK2-NEXT: [[TMP8:%.*]] = call i8* @llvm.stacksave() 1769 // CHECK2-NEXT: store i8* [[TMP8]], i8** [[SAVED_STACK]], align 8 1770 // CHECK2-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP6]], align 16 1771 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[__VLA_EXPR0]], align 8 1772 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr i16, i16* [[VLA]], i64 [[TMP6]] 1773 // CHECK2-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq i16* [[VLA]], [[TMP9]] 1774 // CHECK2-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] 1775 // CHECK2: omp.arrayinit.body: 1776 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i16* [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] 1777 // CHECK2-NEXT: store i16 0, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 2 1778 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1779 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i16* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] 1780 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] 1781 // CHECK2: omp.arrayinit.done: 1782 // CHECK2-NEXT: [[TMP10:%.*]] = load i16*, i16** [[X_ADDR]], align 8 1783 // CHECK2-NEXT: [[TMP11:%.*]] = ptrtoint i16* [[TMP10]] to i64 1784 // CHECK2-NEXT: [[TMP12:%.*]] = ptrtoint i16* [[ARRAYIDX]] to i64 1785 // CHECK2-NEXT: [[TMP13:%.*]] = sub i64 [[TMP11]], [[TMP12]] 1786 // CHECK2-NEXT: [[TMP14:%.*]] = sdiv exact i64 [[TMP13]], ptrtoint (i16* getelementptr (i16, i16* null, i32 1) to i64) 1787 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr i16, i16* [[VLA]], i64 [[TMP14]] 1788 // CHECK2-NEXT: store i16* [[TMP15]], i16** [[TMP]], align 8 1789 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 1790 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i16* [[VLA]] to i8* 1791 // CHECK2-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8 1792 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1 1793 // CHECK2-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP6]] to i8* 1794 // CHECK2-NEXT: store i8* [[TMP19]], i8** [[TMP18]], align 8 1795 // CHECK2-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1796 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 1797 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast [2 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 1798 // CHECK2-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP21]], i32 1, i64 16, i8* [[TMP22]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 1799 // CHECK2-NEXT: switch i32 [[TMP23]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1800 // CHECK2-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1801 // CHECK2-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1802 // CHECK2-NEXT: ] 1803 // CHECK2: .omp.reduction.case1: 1804 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr i16, i16* [[ARRAYIDX]], i64 [[TMP6]] 1805 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq i16* [[ARRAYIDX]], [[TMP24]] 1806 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE7:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1807 // CHECK2: omp.arraycpy.body: 1808 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i16* [ [[VLA]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1809 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST2:%.*]] = phi i16* [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT5:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1810 // CHECK2-NEXT: [[TMP25:%.*]] = load i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST2]], align 2 1811 // CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP25]] to i32 1812 // CHECK2-NEXT: [[TMP26:%.*]] = load i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 2 1813 // CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP26]] to i32 1814 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV3]] 1815 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD]] to i16 1816 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[OMP_ARRAYCPY_DESTELEMENTPAST2]], align 2 1817 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT5]] = getelementptr i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST2]], i32 1 1818 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1819 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE6:%.*]] = icmp eq i16* [[OMP_ARRAYCPY_DEST_ELEMENT5]], [[TMP24]] 1820 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_DONE7]], label [[OMP_ARRAYCPY_BODY]] 1821 // CHECK2: omp.arraycpy.done7: 1822 // CHECK2-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1823 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1824 // CHECK2: .omp.reduction.case2: 1825 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr i16, i16* [[ARRAYIDX]], i64 [[TMP6]] 1826 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY8:%.*]] = icmp eq i16* [[ARRAYIDX]], [[TMP27]] 1827 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY8]], label [[OMP_ARRAYCPY_DONE21:%.*]], label [[OMP_ARRAYCPY_BODY9:%.*]] 1828 // CHECK2: omp.arraycpy.body9: 1829 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST10:%.*]] = phi i16* [ [[VLA]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT19:%.*]], [[ATOMIC_EXIT:%.*]] ] 1830 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST11:%.*]] = phi i16* [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT18:%.*]], [[ATOMIC_EXIT]] ] 1831 // CHECK2-NEXT: [[TMP28:%.*]] = load i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST10]], align 2 1832 // CHECK2-NEXT: [[CONV12:%.*]] = sext i16 [[TMP28]] to i32 1833 // CHECK2-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST11]] monotonic, align 2 1834 // CHECK2-NEXT: br label [[ATOMIC_CONT:%.*]] 1835 // CHECK2: atomic_cont: 1836 // CHECK2-NEXT: [[TMP29:%.*]] = phi i16 [ [[ATOMIC_LOAD]], [[OMP_ARRAYCPY_BODY9]] ], [ [[TMP34:%.*]], [[ATOMIC_CONT]] ] 1837 // CHECK2-NEXT: store i16 [[TMP29]], i16* [[_TMP13]], align 2 1838 // CHECK2-NEXT: [[TMP30:%.*]] = load i16, i16* [[_TMP13]], align 2 1839 // CHECK2-NEXT: [[CONV14:%.*]] = sext i16 [[TMP30]] to i32 1840 // CHECK2-NEXT: [[TMP31:%.*]] = load i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST10]], align 2 1841 // CHECK2-NEXT: [[CONV15:%.*]] = sext i16 [[TMP31]] to i32 1842 // CHECK2-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV14]], [[CONV15]] 1843 // CHECK2-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i16 1844 // CHECK2-NEXT: store i16 [[CONV17]], i16* [[ATOMIC_TEMP]], align 2 1845 // CHECK2-NEXT: [[TMP32:%.*]] = load i16, i16* [[ATOMIC_TEMP]], align 2 1846 // CHECK2-NEXT: [[TMP33:%.*]] = cmpxchg i16* [[OMP_ARRAYCPY_DESTELEMENTPAST11]], i16 [[TMP29]], i16 [[TMP32]] monotonic monotonic, align 2 1847 // CHECK2-NEXT: [[TMP34]] = extractvalue { i16, i1 } [[TMP33]], 0 1848 // CHECK2-NEXT: [[TMP35:%.*]] = extractvalue { i16, i1 } [[TMP33]], 1 1849 // CHECK2-NEXT: br i1 [[TMP35]], label [[ATOMIC_EXIT]], label [[ATOMIC_CONT]] 1850 // CHECK2: atomic_exit: 1851 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT18]] = getelementptr i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST11]], i32 1 1852 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT19]] = getelementptr i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST10]], i32 1 1853 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE20:%.*]] = icmp eq i16* [[OMP_ARRAYCPY_DEST_ELEMENT18]], [[TMP27]] 1854 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE20]], label [[OMP_ARRAYCPY_DONE21]], label [[OMP_ARRAYCPY_BODY9]] 1855 // CHECK2: omp.arraycpy.done21: 1856 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1857 // CHECK2: .omp.reduction.default: 1858 // CHECK2-NEXT: [[TMP36:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1859 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP36]]) 1860 // CHECK2-NEXT: ret void 1861 // 1862 // 1863 // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 1864 // CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { 1865 // CHECK2-NEXT: entry: 1866 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1867 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 1868 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1869 // CHECK2-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 1870 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 1871 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [2 x i8*]* 1872 // CHECK2-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 1873 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [2 x i8*]* 1874 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP5]], i64 0, i64 0 1875 // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 1876 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i16* 1877 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP3]], i64 0, i64 0 1878 // CHECK2-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 1879 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i16* 1880 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP3]], i64 0, i64 1 1881 // CHECK2-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8 1882 // CHECK2-NEXT: [[TMP14:%.*]] = ptrtoint i8* [[TMP13]] to i64 1883 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr i16, i16* [[TMP11]], i64 [[TMP14]] 1884 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq i16* [[TMP11]], [[TMP15]] 1885 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1886 // CHECK2: omp.arraycpy.body: 1887 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i16* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1888 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i16* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1889 // CHECK2-NEXT: [[TMP16:%.*]] = load i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 2 1890 // CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP16]] to i32 1891 // CHECK2-NEXT: [[TMP17:%.*]] = load i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 2 1892 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP17]] to i32 1893 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV2]] 1894 // CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 1895 // CHECK2-NEXT: store i16 [[CONV3]], i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 2 1896 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1897 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1898 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i16* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP15]] 1899 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1900 // CHECK2: omp.arraycpy.done4: 1901 // CHECK2-NEXT: ret void 1902 // 1903 // 1904 // CHECK2-LABEL: define {{[^@]+}}@main 1905 // CHECK2-SAME: () #[[ATTR6:[0-9]+]] { 1906 // CHECK2-NEXT: entry: 1907 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1908 // CHECK2-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 1909 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1910 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca float, align 4 1911 // CHECK2-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 1912 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1913 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1914 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 1915 // CHECK2-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 1916 // CHECK2-NEXT: [[CF:%.*]] = alloca { float, float }, align 4 1917 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 1918 // CHECK2-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) 1919 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 1920 // CHECK2-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 1921 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1922 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) 1923 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 1924 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 1925 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 1926 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 1927 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 1928 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) 1929 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, float*, [2 x %struct.S]*, %struct.S*, %struct.S*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], float* [[T_VAR]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], %struct.S* [[VAR1]], float* [[T_VAR1]]) 1930 // CHECK2-NEXT: [[CALL:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) 1931 // CHECK2-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL]], 0.000000e+00 1932 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] 1933 // CHECK2: if.then: 1934 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, float*, [2 x %struct.S]*, %struct.S*, %struct.S*, float*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], float* [[T_VAR]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], %struct.S* [[VAR1]], float* [[T_VAR1]]) 1935 // CHECK2-NEXT: br label [[IF_END]] 1936 // CHECK2: if.end: 1937 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, { float, float }*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), { float, float }* [[CF]]) 1938 // CHECK2-NEXT: [[CALL1:%.*]] = call i32 @_Z5tmainIiET_v() 1939 // CHECK2-NEXT: store i32 [[CALL1]], i32* [[RETVAL]], align 4 1940 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR5:[0-9]+]] 1941 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] 1942 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1943 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 1944 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1945 // CHECK2: arraydestroy.body: 1946 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[IF_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1947 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1948 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] 1949 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1950 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1951 // CHECK2: arraydestroy.done2: 1952 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] 1953 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 1954 // CHECK2-NEXT: ret i32 [[TMP2]] 1955 // 1956 // 1957 // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 1958 // CHECK2-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] align 2 { 1959 // CHECK2-NEXT: entry: 1960 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 1961 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 1962 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 1963 // CHECK2-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 1964 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 1965 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 1966 // CHECK2-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) 1967 // CHECK2-NEXT: ret void 1968 // 1969 // 1970 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1971 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 1972 // CHECK2-NEXT: entry: 1973 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1974 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1975 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1976 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 1977 // CHECK2-NEXT: ret void 1978 // 1979 // 1980 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1981 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 1982 // CHECK2-NEXT: entry: 1983 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1984 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1985 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1986 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1987 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1988 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1989 // CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 1990 // CHECK2-NEXT: ret void 1991 // 1992 // 1993 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 1994 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]]) #[[ATTR1]] { 1995 // CHECK2-NEXT: entry: 1996 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1997 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1998 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1999 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca float*, align 8 2000 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 2001 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 2002 // CHECK2-NEXT: [[VAR1_ADDR:%.*]] = alloca %struct.S*, align 8 2003 // CHECK2-NEXT: [[T_VAR1_ADDR:%.*]] = alloca float*, align 8 2004 // CHECK2-NEXT: [[T_VAR2:%.*]] = alloca float, align 4 2005 // CHECK2-NEXT: [[VAR3:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2006 // CHECK2-NEXT: [[VAR14:%.*]] = alloca [[STRUCT_S]], align 4 2007 // CHECK2-NEXT: [[T_VAR15:%.*]] = alloca float, align 4 2008 // CHECK2-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [4 x i8*], align 8 2009 // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4 2010 // CHECK2-NEXT: [[ATOMIC_TEMP:%.*]] = alloca float, align 4 2011 // CHECK2-NEXT: [[TMP:%.*]] = alloca float, align 4 2012 // CHECK2-NEXT: [[REF_TMP13:%.*]] = alloca [[STRUCT_S]], align 4 2013 // CHECK2-NEXT: [[ATOMIC_TEMP23:%.*]] = alloca float, align 4 2014 // CHECK2-NEXT: [[_TMP24:%.*]] = alloca float, align 4 2015 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2016 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2017 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 2018 // CHECK2-NEXT: store float* [[T_VAR]], float** [[T_VAR_ADDR]], align 8 2019 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 2020 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 2021 // CHECK2-NEXT: store %struct.S* [[VAR1]], %struct.S** [[VAR1_ADDR]], align 8 2022 // CHECK2-NEXT: store float* [[T_VAR1]], float** [[T_VAR1_ADDR]], align 8 2023 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 2024 // CHECK2-NEXT: [[TMP1:%.*]] = load float*, float** [[T_VAR_ADDR]], align 8 2025 // CHECK2-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 2026 // CHECK2-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 2027 // CHECK2-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[VAR1_ADDR]], align 8 2028 // CHECK2-NEXT: [[TMP5:%.*]] = load float*, float** [[T_VAR1_ADDR]], align 8 2029 // CHECK2-NEXT: store float 0.000000e+00, float* [[T_VAR2]], align 4 2030 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) 2031 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) 2032 // CHECK2-NEXT: store float 0x47EFFFFFE0000000, float* [[T_VAR15]], align 4 2033 // CHECK2-NEXT: [[TMP6:%.*]] = load float, float* [[T_VAR2]], align 4 2034 // CHECK2-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32 2035 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP0]], i64 0, i64 0 2036 // CHECK2-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4 2037 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i64 0, i64 0 2038 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* 2039 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR3]] to i8* 2040 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false) 2041 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 2042 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast float* [[T_VAR2]] to i8* 2043 // CHECK2-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 8 2044 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1 2045 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR3]] to i8* 2046 // CHECK2-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 8 2047 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 2 2048 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR14]] to i8* 2049 // CHECK2-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 2050 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 3 2051 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast float* [[T_VAR15]] to i8* 2052 // CHECK2-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 2053 // CHECK2-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2054 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 2055 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 2056 // CHECK2-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 4, i64 32, i8* [[TMP19]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) 2057 // CHECK2-NEXT: switch i32 [[TMP20]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 2058 // CHECK2-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 2059 // CHECK2-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 2060 // CHECK2-NEXT: ] 2061 // CHECK2: .omp.reduction.case1: 2062 // CHECK2-NEXT: [[TMP21:%.*]] = load float, float* [[TMP1]], align 4 2063 // CHECK2-NEXT: [[TMP22:%.*]] = load float, float* [[T_VAR2]], align 4 2064 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP21]], [[TMP22]] 2065 // CHECK2-NEXT: store float [[ADD]], float* [[TMP1]], align 4 2066 // CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) 2067 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast %struct.S* [[TMP3]] to i8* 2068 // CHECK2-NEXT: [[TMP24:%.*]] = bitcast %struct.S* [[CALL]] to i8* 2069 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i64 4, i1 false) 2070 // CHECK2-NEXT: [[CALL7:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP4]]) 2071 // CHECK2-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL7]], 0.000000e+00 2072 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] 2073 // CHECK2: land.rhs: 2074 // CHECK2-NEXT: [[CALL8:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) 2075 // CHECK2-NEXT: [[TOBOOL9:%.*]] = fcmp une float [[CALL8]], 0.000000e+00 2076 // CHECK2-NEXT: br label [[LAND_END]] 2077 // CHECK2: land.end: 2078 // CHECK2-NEXT: [[TMP25:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL9]], [[LAND_RHS]] ] 2079 // CHECK2-NEXT: [[CONV10:%.*]] = uitofp i1 [[TMP25]] to float 2080 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]], float [[CONV10]]) 2081 // CHECK2-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[TMP4]] to i8* 2082 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* 2083 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) 2084 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] 2085 // CHECK2-NEXT: [[TMP28:%.*]] = load float, float* [[TMP5]], align 4 2086 // CHECK2-NEXT: [[TMP29:%.*]] = load float, float* [[T_VAR15]], align 4 2087 // CHECK2-NEXT: [[CMP:%.*]] = fcmp olt float [[TMP28]], [[TMP29]] 2088 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2089 // CHECK2: cond.true: 2090 // CHECK2-NEXT: [[TMP30:%.*]] = load float, float* [[TMP5]], align 4 2091 // CHECK2-NEXT: br label [[COND_END:%.*]] 2092 // CHECK2: cond.false: 2093 // CHECK2-NEXT: [[TMP31:%.*]] = load float, float* [[T_VAR15]], align 4 2094 // CHECK2-NEXT: br label [[COND_END]] 2095 // CHECK2: cond.end: 2096 // CHECK2-NEXT: [[COND:%.*]] = phi float [ [[TMP30]], [[COND_TRUE]] ], [ [[TMP31]], [[COND_FALSE]] ] 2097 // CHECK2-NEXT: store float [[COND]], float* [[TMP5]], align 4 2098 // CHECK2-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.reduction.var) 2099 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 2100 // CHECK2: .omp.reduction.case2: 2101 // CHECK2-NEXT: [[TMP32:%.*]] = load float, float* [[T_VAR2]], align 4 2102 // CHECK2-NEXT: [[TMP33:%.*]] = bitcast float* [[TMP1]] to i32* 2103 // CHECK2-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i32, i32* [[TMP33]] monotonic, align 4 2104 // CHECK2-NEXT: br label [[ATOMIC_CONT:%.*]] 2105 // CHECK2: atomic_cont: 2106 // CHECK2-NEXT: [[TMP34:%.*]] = phi i32 [ [[ATOMIC_LOAD]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[TMP42:%.*]], [[ATOMIC_CONT]] ] 2107 // CHECK2-NEXT: [[TMP35:%.*]] = bitcast float* [[ATOMIC_TEMP]] to i32* 2108 // CHECK2-NEXT: [[TMP36:%.*]] = bitcast i32 [[TMP34]] to float 2109 // CHECK2-NEXT: store float [[TMP36]], float* [[TMP]], align 4 2110 // CHECK2-NEXT: [[TMP37:%.*]] = load float, float* [[TMP]], align 4 2111 // CHECK2-NEXT: [[TMP38:%.*]] = load float, float* [[T_VAR2]], align 4 2112 // CHECK2-NEXT: [[ADD11:%.*]] = fadd float [[TMP37]], [[TMP38]] 2113 // CHECK2-NEXT: store float [[ADD11]], float* [[ATOMIC_TEMP]], align 4 2114 // CHECK2-NEXT: [[TMP39:%.*]] = load i32, i32* [[TMP35]], align 4 2115 // CHECK2-NEXT: [[TMP40:%.*]] = bitcast float* [[TMP1]] to i32* 2116 // CHECK2-NEXT: [[TMP41:%.*]] = cmpxchg i32* [[TMP40]], i32 [[TMP34]], i32 [[TMP39]] monotonic monotonic, align 4 2117 // CHECK2-NEXT: [[TMP42]] = extractvalue { i32, i1 } [[TMP41]], 0 2118 // CHECK2-NEXT: [[TMP43:%.*]] = extractvalue { i32, i1 } [[TMP41]], 1 2119 // CHECK2-NEXT: br i1 [[TMP43]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] 2120 // CHECK2: atomic_exit: 2121 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) 2122 // CHECK2-NEXT: [[CALL12:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) 2123 // CHECK2-NEXT: [[TMP44:%.*]] = bitcast %struct.S* [[TMP3]] to i8* 2124 // CHECK2-NEXT: [[TMP45:%.*]] = bitcast %struct.S* [[CALL12]] to i8* 2125 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP44]], i8* align 4 [[TMP45]], i64 4, i1 false) 2126 // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) 2127 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) 2128 // CHECK2-NEXT: [[CALL14:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP4]]) 2129 // CHECK2-NEXT: [[TOBOOL15:%.*]] = fcmp une float [[CALL14]], 0.000000e+00 2130 // CHECK2-NEXT: br i1 [[TOBOOL15]], label [[LAND_RHS16:%.*]], label [[LAND_END19:%.*]] 2131 // CHECK2: land.rhs16: 2132 // CHECK2-NEXT: [[CALL17:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) 2133 // CHECK2-NEXT: [[TOBOOL18:%.*]] = fcmp une float [[CALL17]], 0.000000e+00 2134 // CHECK2-NEXT: br label [[LAND_END19]] 2135 // CHECK2: land.end19: 2136 // CHECK2-NEXT: [[TMP46:%.*]] = phi i1 [ false, [[ATOMIC_EXIT]] ], [ [[TOBOOL18]], [[LAND_RHS16]] ] 2137 // CHECK2-NEXT: [[CONV20:%.*]] = uitofp i1 [[TMP46]] to float 2138 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP13]], float [[CONV20]]) 2139 // CHECK2-NEXT: [[TMP47:%.*]] = bitcast %struct.S* [[TMP4]] to i8* 2140 // CHECK2-NEXT: [[TMP48:%.*]] = bitcast %struct.S* [[REF_TMP13]] to i8* 2141 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i64 4, i1 false) 2142 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP13]]) #[[ATTR5]] 2143 // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) 2144 // CHECK2-NEXT: [[TMP49:%.*]] = load float, float* [[T_VAR15]], align 4 2145 // CHECK2-NEXT: [[TMP50:%.*]] = bitcast float* [[TMP5]] to i32* 2146 // CHECK2-NEXT: [[ATOMIC_LOAD21:%.*]] = load atomic i32, i32* [[TMP50]] monotonic, align 4 2147 // CHECK2-NEXT: br label [[ATOMIC_CONT22:%.*]] 2148 // CHECK2: atomic_cont22: 2149 // CHECK2-NEXT: [[TMP51:%.*]] = phi i32 [ [[ATOMIC_LOAD21]], [[LAND_END19]] ], [ [[TMP61:%.*]], [[COND_END28:%.*]] ] 2150 // CHECK2-NEXT: [[TMP52:%.*]] = bitcast float* [[ATOMIC_TEMP23]] to i32* 2151 // CHECK2-NEXT: [[TMP53:%.*]] = bitcast i32 [[TMP51]] to float 2152 // CHECK2-NEXT: store float [[TMP53]], float* [[_TMP24]], align 4 2153 // CHECK2-NEXT: [[TMP54:%.*]] = load float, float* [[_TMP24]], align 4 2154 // CHECK2-NEXT: [[TMP55:%.*]] = load float, float* [[T_VAR15]], align 4 2155 // CHECK2-NEXT: [[CMP25:%.*]] = fcmp olt float [[TMP54]], [[TMP55]] 2156 // CHECK2-NEXT: br i1 [[CMP25]], label [[COND_TRUE26:%.*]], label [[COND_FALSE27:%.*]] 2157 // CHECK2: cond.true26: 2158 // CHECK2-NEXT: [[TMP56:%.*]] = load float, float* [[_TMP24]], align 4 2159 // CHECK2-NEXT: br label [[COND_END28]] 2160 // CHECK2: cond.false27: 2161 // CHECK2-NEXT: [[TMP57:%.*]] = load float, float* [[T_VAR15]], align 4 2162 // CHECK2-NEXT: br label [[COND_END28]] 2163 // CHECK2: cond.end28: 2164 // CHECK2-NEXT: [[COND29:%.*]] = phi float [ [[TMP56]], [[COND_TRUE26]] ], [ [[TMP57]], [[COND_FALSE27]] ] 2165 // CHECK2-NEXT: store float [[COND29]], float* [[ATOMIC_TEMP23]], align 4 2166 // CHECK2-NEXT: [[TMP58:%.*]] = load i32, i32* [[TMP52]], align 4 2167 // CHECK2-NEXT: [[TMP59:%.*]] = bitcast float* [[TMP5]] to i32* 2168 // CHECK2-NEXT: [[TMP60:%.*]] = cmpxchg i32* [[TMP59]], i32 [[TMP51]], i32 [[TMP58]] monotonic monotonic, align 4 2169 // CHECK2-NEXT: [[TMP61]] = extractvalue { i32, i1 } [[TMP60]], 0 2170 // CHECK2-NEXT: [[TMP62:%.*]] = extractvalue { i32, i1 } [[TMP60]], 1 2171 // CHECK2-NEXT: br i1 [[TMP62]], label [[ATOMIC_EXIT30:%.*]], label [[ATOMIC_CONT22]] 2172 // CHECK2: atomic_exit30: 2173 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 2174 // CHECK2: .omp.reduction.default: 2175 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR5]] 2176 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR5]] 2177 // CHECK2-NEXT: ret void 2178 // 2179 // 2180 // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 2181 // CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { 2182 // CHECK2-NEXT: entry: 2183 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2184 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 2185 // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2186 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2187 // CHECK2-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 2188 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 2189 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [4 x i8*]* 2190 // CHECK2-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 2191 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [4 x i8*]* 2192 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP5]], i64 0, i64 0 2193 // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 2194 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to float* 2195 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 0 2196 // CHECK2-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 2197 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to float* 2198 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP5]], i64 0, i64 1 2199 // CHECK2-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8 2200 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to %struct.S* 2201 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 1 2202 // CHECK2-NEXT: [[TMP16:%.*]] = load i8*, i8** [[TMP15]], align 8 2203 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8* [[TMP16]] to %struct.S* 2204 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP5]], i64 0, i64 2 2205 // CHECK2-NEXT: [[TMP19:%.*]] = load i8*, i8** [[TMP18]], align 8 2206 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8* [[TMP19]] to %struct.S* 2207 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 2 2208 // CHECK2-NEXT: [[TMP22:%.*]] = load i8*, i8** [[TMP21]], align 8 2209 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8* [[TMP22]] to %struct.S* 2210 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP5]], i64 0, i64 3 2211 // CHECK2-NEXT: [[TMP25:%.*]] = load i8*, i8** [[TMP24]], align 8 2212 // CHECK2-NEXT: [[TMP26:%.*]] = bitcast i8* [[TMP25]] to float* 2213 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 3 2214 // CHECK2-NEXT: [[TMP28:%.*]] = load i8*, i8** [[TMP27]], align 8 2215 // CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8* [[TMP28]] to float* 2216 // CHECK2-NEXT: [[TMP30:%.*]] = load float, float* [[TMP11]], align 4 2217 // CHECK2-NEXT: [[TMP31:%.*]] = load float, float* [[TMP8]], align 4 2218 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP30]], [[TMP31]] 2219 // CHECK2-NEXT: store float [[ADD]], float* [[TMP11]], align 4 2220 // CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP14]]) 2221 // CHECK2-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP17]] to i8* 2222 // CHECK2-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[CALL]] to i8* 2223 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) 2224 // CHECK2-NEXT: [[CALL2:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP23]]) 2225 // CHECK2-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL2]], 0.000000e+00 2226 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] 2227 // CHECK2: land.rhs: 2228 // CHECK2-NEXT: [[CALL3:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP20]]) 2229 // CHECK2-NEXT: [[TOBOOL4:%.*]] = fcmp une float [[CALL3]], 0.000000e+00 2230 // CHECK2-NEXT: br label [[LAND_END]] 2231 // CHECK2: land.end: 2232 // CHECK2-NEXT: [[TMP34:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ] 2233 // CHECK2-NEXT: [[CONV:%.*]] = uitofp i1 [[TMP34]] to float 2234 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]], float [[CONV]]) 2235 // CHECK2-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP23]] to i8* 2236 // CHECK2-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* 2237 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) 2238 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] 2239 // CHECK2-NEXT: [[TMP37:%.*]] = load float, float* [[TMP29]], align 4 2240 // CHECK2-NEXT: [[TMP38:%.*]] = load float, float* [[TMP26]], align 4 2241 // CHECK2-NEXT: [[CMP:%.*]] = fcmp olt float [[TMP37]], [[TMP38]] 2242 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2243 // CHECK2: cond.true: 2244 // CHECK2-NEXT: [[TMP39:%.*]] = load float, float* [[TMP29]], align 4 2245 // CHECK2-NEXT: br label [[COND_END:%.*]] 2246 // CHECK2: cond.false: 2247 // CHECK2-NEXT: [[TMP40:%.*]] = load float, float* [[TMP26]], align 4 2248 // CHECK2-NEXT: br label [[COND_END]] 2249 // CHECK2: cond.end: 2250 // CHECK2-NEXT: [[COND:%.*]] = phi float [ [[TMP39]], [[COND_TRUE]] ], [ [[TMP40]], [[COND_FALSE]] ] 2251 // CHECK2-NEXT: store float [[COND]], float* [[TMP29]], align 4 2252 // CHECK2-NEXT: ret void 2253 // 2254 // 2255 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEanERKS0_ 2256 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR0]] align 2 { 2257 // CHECK2-NEXT: entry: 2258 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2259 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 2260 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2261 // CHECK2-NEXT: store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8 2262 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2263 // CHECK2-NEXT: ret %struct.S* [[THIS1]] 2264 // 2265 // 2266 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEcvfEv 2267 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR0]] align 2 { 2268 // CHECK2-NEXT: entry: 2269 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2270 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2271 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2272 // CHECK2-NEXT: ret float 0.000000e+00 2273 // 2274 // 2275 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2276 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 2277 // CHECK2-NEXT: entry: 2278 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2279 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2280 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2281 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] 2282 // CHECK2-NEXT: ret void 2283 // 2284 // 2285 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 2286 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]]) #[[ATTR1]] { 2287 // CHECK2-NEXT: entry: 2288 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2289 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2290 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 2291 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca float*, align 8 2292 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 2293 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 2294 // CHECK2-NEXT: [[VAR1_ADDR:%.*]] = alloca %struct.S*, align 8 2295 // CHECK2-NEXT: [[T_VAR1_ADDR:%.*]] = alloca float*, align 8 2296 // CHECK2-NEXT: [[T_VAR2:%.*]] = alloca float, align 4 2297 // CHECK2-NEXT: [[VAR3:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2298 // CHECK2-NEXT: [[VAR14:%.*]] = alloca [[STRUCT_S]], align 4 2299 // CHECK2-NEXT: [[T_VAR15:%.*]] = alloca float, align 4 2300 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2301 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2302 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 2303 // CHECK2-NEXT: store float* [[T_VAR]], float** [[T_VAR_ADDR]], align 8 2304 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 2305 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 2306 // CHECK2-NEXT: store %struct.S* [[VAR1]], %struct.S** [[VAR1_ADDR]], align 8 2307 // CHECK2-NEXT: store float* [[T_VAR1]], float** [[T_VAR1_ADDR]], align 8 2308 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 2309 // CHECK2-NEXT: [[TMP1:%.*]] = load float*, float** [[T_VAR_ADDR]], align 8 2310 // CHECK2-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 2311 // CHECK2-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 2312 // CHECK2-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[VAR1_ADDR]], align 8 2313 // CHECK2-NEXT: [[TMP5:%.*]] = load float*, float** [[T_VAR1_ADDR]], align 8 2314 // CHECK2-NEXT: store float 0.000000e+00, float* [[T_VAR2]], align 4 2315 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) 2316 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) 2317 // CHECK2-NEXT: store float 0x47EFFFFFE0000000, float* [[T_VAR15]], align 4 2318 // CHECK2-NEXT: br label [[WHILE_COND:%.*]] 2319 // CHECK2: while.cond: 2320 // CHECK2-NEXT: br label [[WHILE_BODY:%.*]] 2321 // CHECK2: while.body: 2322 // CHECK2-NEXT: [[TMP6:%.*]] = load float, float* [[T_VAR2]], align 4 2323 // CHECK2-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32 2324 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP0]], i64 0, i64 0 2325 // CHECK2-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4 2326 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i64 0, i64 0 2327 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* 2328 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR3]] to i8* 2329 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false) 2330 // CHECK2-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP4:![0-9]+]] 2331 // 2332 // 2333 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 2334 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], { float, float }* nonnull align 4 dereferenceable(8) [[CF:%.*]]) #[[ATTR1]] { 2335 // CHECK2-NEXT: entry: 2336 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2337 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2338 // CHECK2-NEXT: [[CF_ADDR:%.*]] = alloca { float, float }*, align 8 2339 // CHECK2-NEXT: [[CF1:%.*]] = alloca { float, float }, align 4 2340 // CHECK2-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 2341 // CHECK2-NEXT: [[ATOMIC_TEMP:%.*]] = alloca { float, float }, align 4 2342 // CHECK2-NEXT: [[ATOMIC_TEMP10:%.*]] = alloca { float, float }, align 4 2343 // CHECK2-NEXT: [[TMP:%.*]] = alloca { float, float }, align 4 2344 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2345 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2346 // CHECK2-NEXT: store { float, float }* [[CF]], { float, float }** [[CF_ADDR]], align 8 2347 // CHECK2-NEXT: [[TMP0:%.*]] = load { float, float }*, { float, float }** [[CF_ADDR]], align 8 2348 // CHECK2-NEXT: [[CF1_REALP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[CF1]], i32 0, i32 0 2349 // CHECK2-NEXT: [[CF1_IMAGP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[CF1]], i32 0, i32 1 2350 // CHECK2-NEXT: store float 0.000000e+00, float* [[CF1_REALP]], align 4 2351 // CHECK2-NEXT: store float 0.000000e+00, float* [[CF1_IMAGP]], align 4 2352 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 2353 // CHECK2-NEXT: [[TMP2:%.*]] = bitcast { float, float }* [[CF1]] to i8* 2354 // CHECK2-NEXT: store i8* [[TMP2]], i8** [[TMP1]], align 8 2355 // CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2356 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 2357 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 2358 // CHECK2-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 1, i64 8, i8* [[TMP5]], void (i8*, i8*)* @.omp.reduction.reduction_func.5, [8 x i32]* @.gomp_critical_user_.reduction.var) 2359 // CHECK2-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 2360 // CHECK2-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 2361 // CHECK2-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 2362 // CHECK2-NEXT: ] 2363 // CHECK2: .omp.reduction.case1: 2364 // CHECK2-NEXT: [[DOTREALP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP0]], i32 0, i32 0 2365 // CHECK2-NEXT: [[DOTREAL:%.*]] = load float, float* [[DOTREALP]], align 4 2366 // CHECK2-NEXT: [[DOTIMAGP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP0]], i32 0, i32 1 2367 // CHECK2-NEXT: [[DOTIMAG:%.*]] = load float, float* [[DOTIMAGP]], align 4 2368 // CHECK2-NEXT: [[CF1_REALP2:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[CF1]], i32 0, i32 0 2369 // CHECK2-NEXT: [[CF1_REAL:%.*]] = load float, float* [[CF1_REALP2]], align 4 2370 // CHECK2-NEXT: [[CF1_IMAGP3:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[CF1]], i32 0, i32 1 2371 // CHECK2-NEXT: [[CF1_IMAG:%.*]] = load float, float* [[CF1_IMAGP3]], align 4 2372 // CHECK2-NEXT: [[ADD_R:%.*]] = fadd float [[DOTREAL]], [[CF1_REAL]] 2373 // CHECK2-NEXT: [[ADD_I:%.*]] = fadd float [[DOTIMAG]], [[CF1_IMAG]] 2374 // CHECK2-NEXT: [[DOTREALP4:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP0]], i32 0, i32 0 2375 // CHECK2-NEXT: [[DOTIMAGP5:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP0]], i32 0, i32 1 2376 // CHECK2-NEXT: store float [[ADD_R]], float* [[DOTREALP4]], align 4 2377 // CHECK2-NEXT: store float [[ADD_I]], float* [[DOTIMAGP5]], align 4 2378 // CHECK2-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], [8 x i32]* @.gomp_critical_user_.reduction.var) 2379 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 2380 // CHECK2: .omp.reduction.case2: 2381 // CHECK2-NEXT: [[CF1_REALP6:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[CF1]], i32 0, i32 0 2382 // CHECK2-NEXT: [[CF1_REAL7:%.*]] = load float, float* [[CF1_REALP6]], align 4 2383 // CHECK2-NEXT: [[CF1_IMAGP8:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[CF1]], i32 0, i32 1 2384 // CHECK2-NEXT: [[CF1_IMAG9:%.*]] = load float, float* [[CF1_IMAGP8]], align 4 2385 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast { float, float }* [[TMP0]] to i8* 2386 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast { float, float }* [[ATOMIC_TEMP]] to i8* 2387 // CHECK2-NEXT: call void @__atomic_load(i64 8, i8* [[TMP7]], i8* [[TMP8]], i32 0) 2388 // CHECK2-NEXT: br label [[ATOMIC_CONT:%.*]] 2389 // CHECK2: atomic_cont: 2390 // CHECK2-NEXT: [[ATOMIC_TEMP_REALP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[ATOMIC_TEMP]], i32 0, i32 0 2391 // CHECK2-NEXT: [[ATOMIC_TEMP_REAL:%.*]] = load float, float* [[ATOMIC_TEMP_REALP]], align 4 2392 // CHECK2-NEXT: [[ATOMIC_TEMP_IMAGP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[ATOMIC_TEMP]], i32 0, i32 1 2393 // CHECK2-NEXT: [[ATOMIC_TEMP_IMAG:%.*]] = load float, float* [[ATOMIC_TEMP_IMAGP]], align 4 2394 // CHECK2-NEXT: [[TMP_REALP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP]], i32 0, i32 0 2395 // CHECK2-NEXT: [[TMP_IMAGP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP]], i32 0, i32 1 2396 // CHECK2-NEXT: store float [[ATOMIC_TEMP_REAL]], float* [[TMP_REALP]], align 4 2397 // CHECK2-NEXT: store float [[ATOMIC_TEMP_IMAG]], float* [[TMP_IMAGP]], align 4 2398 // CHECK2-NEXT: [[TMP_REALP11:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP]], i32 0, i32 0 2399 // CHECK2-NEXT: [[TMP_REAL:%.*]] = load float, float* [[TMP_REALP11]], align 4 2400 // CHECK2-NEXT: [[TMP_IMAGP12:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP]], i32 0, i32 1 2401 // CHECK2-NEXT: [[TMP_IMAG:%.*]] = load float, float* [[TMP_IMAGP12]], align 4 2402 // CHECK2-NEXT: [[CF1_REALP13:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[CF1]], i32 0, i32 0 2403 // CHECK2-NEXT: [[CF1_REAL14:%.*]] = load float, float* [[CF1_REALP13]], align 4 2404 // CHECK2-NEXT: [[CF1_IMAGP15:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[CF1]], i32 0, i32 1 2405 // CHECK2-NEXT: [[CF1_IMAG16:%.*]] = load float, float* [[CF1_IMAGP15]], align 4 2406 // CHECK2-NEXT: [[ADD_R17:%.*]] = fadd float [[TMP_REAL]], [[CF1_REAL14]] 2407 // CHECK2-NEXT: [[ADD_I18:%.*]] = fadd float [[TMP_IMAG]], [[CF1_IMAG16]] 2408 // CHECK2-NEXT: [[ATOMIC_TEMP10_REALP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[ATOMIC_TEMP10]], i32 0, i32 0 2409 // CHECK2-NEXT: [[ATOMIC_TEMP10_IMAGP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[ATOMIC_TEMP10]], i32 0, i32 1 2410 // CHECK2-NEXT: store float [[ADD_R17]], float* [[ATOMIC_TEMP10_REALP]], align 4 2411 // CHECK2-NEXT: store float [[ADD_I18]], float* [[ATOMIC_TEMP10_IMAGP]], align 4 2412 // CHECK2-NEXT: [[TMP9:%.*]] = bitcast { float, float }* [[TMP0]] to i8* 2413 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast { float, float }* [[ATOMIC_TEMP]] to i8* 2414 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast { float, float }* [[ATOMIC_TEMP10]] to i8* 2415 // CHECK2-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, i8* [[TMP9]], i8* [[TMP10]], i8* [[TMP11]], i32 0, i32 0) 2416 // CHECK2-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] 2417 // CHECK2: atomic_exit: 2418 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 2419 // CHECK2: .omp.reduction.default: 2420 // CHECK2-NEXT: ret void 2421 // 2422 // 2423 // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 2424 // CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { 2425 // CHECK2-NEXT: entry: 2426 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2427 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 2428 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2429 // CHECK2-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 2430 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 2431 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 2432 // CHECK2-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 2433 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 2434 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 2435 // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 2436 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to { float, float }* 2437 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 2438 // CHECK2-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 2439 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to { float, float }* 2440 // CHECK2-NEXT: [[DOTREALP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP11]], i32 0, i32 0 2441 // CHECK2-NEXT: [[DOTREAL:%.*]] = load float, float* [[DOTREALP]], align 4 2442 // CHECK2-NEXT: [[DOTIMAGP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP11]], i32 0, i32 1 2443 // CHECK2-NEXT: [[DOTIMAG:%.*]] = load float, float* [[DOTIMAGP]], align 4 2444 // CHECK2-NEXT: [[DOTREALP2:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP8]], i32 0, i32 0 2445 // CHECK2-NEXT: [[DOTREAL3:%.*]] = load float, float* [[DOTREALP2]], align 4 2446 // CHECK2-NEXT: [[DOTIMAGP4:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP8]], i32 0, i32 1 2447 // CHECK2-NEXT: [[DOTIMAG5:%.*]] = load float, float* [[DOTIMAGP4]], align 4 2448 // CHECK2-NEXT: [[ADD_R:%.*]] = fadd float [[DOTREAL]], [[DOTREAL3]] 2449 // CHECK2-NEXT: [[ADD_I:%.*]] = fadd float [[DOTIMAG]], [[DOTIMAG5]] 2450 // CHECK2-NEXT: [[DOTREALP6:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP11]], i32 0, i32 0 2451 // CHECK2-NEXT: [[DOTIMAGP7:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[TMP11]], i32 0, i32 1 2452 // CHECK2-NEXT: store float [[ADD_R]], float* [[DOTREALP6]], align 4 2453 // CHECK2-NEXT: store float [[ADD_I]], float* [[DOTIMAGP7]], align 4 2454 // CHECK2-NEXT: ret void 2455 // 2456 // 2457 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2458 // CHECK2-SAME: () #[[ATTR0]] { 2459 // CHECK2-NEXT: entry: 2460 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2461 // CHECK2-NEXT: [[T:%.*]] = alloca i32, align 4 2462 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2463 // CHECK2-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 2464 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 2465 // CHECK2-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 2466 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2467 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2468 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 2469 // CHECK2-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 128 2470 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 2471 // CHECK2-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) 2472 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 128 2473 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2474 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 2475 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 2476 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 2477 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 2478 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 2479 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 2480 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) 2481 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*, %struct.S.0*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]], %struct.S.0* [[VAR1]], i32* [[T_VAR1]]) 2482 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 2483 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR5]] 2484 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] 2485 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2486 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 2487 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2488 // CHECK2: arraydestroy.body: 2489 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2490 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2491 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] 2492 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2493 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2494 // CHECK2: arraydestroy.done1: 2495 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] 2496 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 2497 // CHECK2-NEXT: ret i32 [[TMP2]] 2498 // 2499 // 2500 // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 2501 // CHECK2-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 2502 // CHECK2-NEXT: entry: 2503 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 2504 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 2505 // CHECK2-NEXT: [[A2:%.*]] = alloca i32*, align 8 2506 // CHECK2-NEXT: [[B4:%.*]] = alloca i32, align 4 2507 // CHECK2-NEXT: [[C5:%.*]] = alloca i32*, align 8 2508 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 2509 // CHECK2-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 2510 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 2511 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 2512 // CHECK2-NEXT: store i32 0, i32* [[A]], align 8 2513 // CHECK2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 2514 // CHECK2-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 2515 // CHECK2-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 2516 // CHECK2-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 2517 // CHECK2-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 2518 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 2519 // CHECK2-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 2520 // CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 2521 // CHECK2-NEXT: store i32* [[A3]], i32** [[A2]], align 8 2522 // CHECK2-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 2523 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 2524 // CHECK2-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 2525 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 2526 // CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 2527 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i32*, i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i32* [[TMP2]], i32* [[B4]], i32* [[TMP3]]) 2528 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[B4]], align 4 2529 // CHECK2-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 2530 // CHECK2-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8 2531 // CHECK2-NEXT: [[BF_LOAD8:%.*]] = load i8, i8* [[B7]], align 4 2532 // CHECK2-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP5]], 15 2533 // CHECK2-NEXT: [[BF_CLEAR9:%.*]] = and i8 [[BF_LOAD8]], -16 2534 // CHECK2-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR9]], [[BF_VALUE]] 2535 // CHECK2-NEXT: store i8 [[BF_SET]], i8* [[B7]], align 4 2536 // CHECK2-NEXT: ret void 2537 // 2538 // 2539 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 2540 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { 2541 // CHECK2-NEXT: entry: 2542 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2543 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2544 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 2545 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 2546 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 2547 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 2548 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32*, align 8 2549 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 2550 // CHECK2-NEXT: [[A2:%.*]] = alloca i32, align 4 2551 // CHECK2-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 2552 // CHECK2-NEXT: [[B4:%.*]] = alloca i32, align 4 2553 // CHECK2-NEXT: [[C5:%.*]] = alloca i32, align 4 2554 // CHECK2-NEXT: [[_TMP6:%.*]] = alloca i32*, align 8 2555 // CHECK2-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [3 x i8*], align 8 2556 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2557 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2558 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 2559 // CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 2560 // CHECK2-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 2561 // CHECK2-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 2562 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 2563 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 2564 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[B_ADDR]], align 8 2565 // CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C_ADDR]], align 8 2566 // CHECK2-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8 2567 // CHECK2-NEXT: store i32* [[TMP3]], i32** [[_TMP1]], align 8 2568 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 2569 // CHECK2-NEXT: store i32 0, i32* [[A2]], align 4 2570 // CHECK2-NEXT: store i32* [[A2]], i32** [[_TMP3]], align 8 2571 // CHECK2-NEXT: store i32 0, i32* [[B4]], align 4 2572 // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[_TMP1]], align 8 2573 // CHECK2-NEXT: store i32 0, i32* [[C5]], align 4 2574 // CHECK2-NEXT: store i32* [[C5]], i32** [[_TMP6]], align 8 2575 // CHECK2-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP3]], align 8 2576 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 2577 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 2578 // CHECK2-NEXT: store i32 [[INC]], i32* [[TMP6]], align 4 2579 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[B4]], align 4 2580 // CHECK2-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 2581 // CHECK2-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 2582 // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[_TMP6]], align 8 2583 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 2584 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 2585 // CHECK2-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 2586 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 2587 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i32* [[A2]] to i8* 2588 // CHECK2-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 8 2589 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1 2590 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast i32* [[B4]] to i8* 2591 // CHECK2-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 2592 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 2 2593 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i32* [[C5]] to i8* 2594 // CHECK2-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 2595 // CHECK2-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2596 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 2597 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 2598 // CHECK2-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 3, i64 24, i8* [[TMP19]], void (i8*, i8*)* @.omp.reduction.reduction_func.7, [8 x i32]* @.gomp_critical_user_.reduction.var) 2599 // CHECK2-NEXT: switch i32 [[TMP20]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 2600 // CHECK2-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 2601 // CHECK2-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 2602 // CHECK2-NEXT: ] 2603 // CHECK2: .omp.reduction.case1: 2604 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP4]], align 4 2605 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[A2]], align 4 2606 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] 2607 // CHECK2-NEXT: store i32 [[ADD]], i32* [[TMP4]], align 4 2608 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP2]], align 4 2609 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[B4]], align 4 2610 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] 2611 // CHECK2-NEXT: store i32 [[ADD7]], i32* [[TMP2]], align 4 2612 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP5]], align 4 2613 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[C5]], align 4 2614 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] 2615 // CHECK2-NEXT: store i32 [[ADD8]], i32* [[TMP5]], align 4 2616 // CHECK2-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.reduction.var) 2617 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 2618 // CHECK2: .omp.reduction.case2: 2619 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[A2]], align 4 2620 // CHECK2-NEXT: [[TMP28:%.*]] = atomicrmw add i32* [[TMP4]], i32 [[TMP27]] monotonic, align 4 2621 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[B4]], align 4 2622 // CHECK2-NEXT: [[TMP30:%.*]] = atomicrmw add i32* [[TMP2]], i32 [[TMP29]] monotonic, align 4 2623 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[C5]], align 4 2624 // CHECK2-NEXT: [[TMP32:%.*]] = atomicrmw add i32* [[TMP5]], i32 [[TMP31]] monotonic, align 4 2625 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 2626 // CHECK2: .omp.reduction.default: 2627 // CHECK2-NEXT: ret void 2628 // 2629 // 2630 // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.7 2631 // CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { 2632 // CHECK2-NEXT: entry: 2633 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2634 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 2635 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2636 // CHECK2-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 2637 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 2638 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [3 x i8*]* 2639 // CHECK2-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 2640 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [3 x i8*]* 2641 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP5]], i64 0, i64 0 2642 // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 2643 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 2644 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP3]], i64 0, i64 0 2645 // CHECK2-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 2646 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 2647 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP5]], i64 0, i64 1 2648 // CHECK2-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8 2649 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to i32* 2650 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP3]], i64 0, i64 1 2651 // CHECK2-NEXT: [[TMP16:%.*]] = load i8*, i8** [[TMP15]], align 8 2652 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8* [[TMP16]] to i32* 2653 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP5]], i64 0, i64 2 2654 // CHECK2-NEXT: [[TMP19:%.*]] = load i8*, i8** [[TMP18]], align 8 2655 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8* [[TMP19]] to i32* 2656 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP3]], i64 0, i64 2 2657 // CHECK2-NEXT: [[TMP22:%.*]] = load i8*, i8** [[TMP21]], align 8 2658 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8* [[TMP22]] to i32* 2659 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP11]], align 4 2660 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP8]], align 4 2661 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] 2662 // CHECK2-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 2663 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP17]], align 4 2664 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP14]], align 4 2665 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] 2666 // CHECK2-NEXT: store i32 [[ADD2]], i32* [[TMP17]], align 4 2667 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP23]], align 4 2668 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP20]], align 4 2669 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 2670 // CHECK2-NEXT: store i32 [[ADD3]], i32* [[TMP23]], align 4 2671 // CHECK2-NEXT: ret void 2672 // 2673 // 2674 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2675 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 2676 // CHECK2-NEXT: entry: 2677 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2678 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2679 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2680 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2681 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 2682 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2683 // CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4 2684 // CHECK2-NEXT: ret void 2685 // 2686 // 2687 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2688 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 2689 // CHECK2-NEXT: entry: 2690 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2691 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2692 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2693 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2694 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2695 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2696 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2697 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 2698 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2699 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2700 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4 2701 // CHECK2-NEXT: ret void 2702 // 2703 // 2704 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2705 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 2706 // CHECK2-NEXT: entry: 2707 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2708 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2709 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2710 // CHECK2-NEXT: ret void 2711 // 2712 // 2713 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2714 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 2715 // CHECK2-NEXT: entry: 2716 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2717 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2718 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2719 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 2720 // CHECK2-NEXT: ret void 2721 // 2722 // 2723 // CHECK2-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev 2724 // CHECK2-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 2725 // CHECK2-NEXT: entry: 2726 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 2727 // CHECK2-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 2728 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 2729 // CHECK2-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) 2730 // CHECK2-NEXT: ret void 2731 // 2732 // 2733 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2734 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 2735 // CHECK2-NEXT: entry: 2736 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2737 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2738 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2739 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2740 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2741 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2742 // CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 2743 // CHECK2-NEXT: ret void 2744 // 2745 // 2746 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 2747 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]]) #[[ATTR1]] { 2748 // CHECK2-NEXT: entry: 2749 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2750 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2751 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 2752 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 2753 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 2754 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 2755 // CHECK2-NEXT: [[VAR1_ADDR:%.*]] = alloca %struct.S.0*, align 8 2756 // CHECK2-NEXT: [[T_VAR1_ADDR:%.*]] = alloca i32*, align 8 2757 // CHECK2-NEXT: [[T_VAR2:%.*]] = alloca i32, align 128 2758 // CHECK2-NEXT: [[VAR3:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 2759 // CHECK2-NEXT: [[VAR14:%.*]] = alloca [[STRUCT_S_0]], align 128 2760 // CHECK2-NEXT: [[T_VAR15:%.*]] = alloca i32, align 128 2761 // CHECK2-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [4 x i8*], align 8 2762 // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4 2763 // CHECK2-NEXT: [[REF_TMP11:%.*]] = alloca [[STRUCT_S_0]], align 4 2764 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2765 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2766 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 2767 // CHECK2-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 2768 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 2769 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 2770 // CHECK2-NEXT: store %struct.S.0* [[VAR1]], %struct.S.0** [[VAR1_ADDR]], align 8 2771 // CHECK2-NEXT: store i32* [[T_VAR1]], i32** [[T_VAR1_ADDR]], align 8 2772 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 2773 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 2774 // CHECK2-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 2775 // CHECK2-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 2776 // CHECK2-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR1_ADDR]], align 8 2777 // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[T_VAR1_ADDR]], align 8 2778 // CHECK2-NEXT: store i32 0, i32* [[T_VAR2]], align 128 2779 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) 2780 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) 2781 // CHECK2-NEXT: store i32 2147483647, i32* [[T_VAR15]], align 128 2782 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR2]], align 128 2783 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP0]], i64 0, i64 0 2784 // CHECK2-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 2785 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i64 0, i64 0 2786 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* 2787 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast %struct.S.0* [[VAR3]] to i8* 2788 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 128 [[TMP8]], i64 4, i1 false) 2789 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 2790 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i32* [[T_VAR2]] to i8* 2791 // CHECK2-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 8 2792 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1 2793 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[VAR3]] to i8* 2794 // CHECK2-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 8 2795 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 2 2796 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[VAR14]] to i8* 2797 // CHECK2-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 2798 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 3 2799 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i32* [[T_VAR15]] to i8* 2800 // CHECK2-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 2801 // CHECK2-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2802 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 2803 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast [4 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 2804 // CHECK2-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 4, i64 32, i8* [[TMP19]], void (i8*, i8*)* @.omp.reduction.reduction_func.9, [8 x i32]* @.gomp_critical_user_.reduction.var) 2805 // CHECK2-NEXT: switch i32 [[TMP20]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 2806 // CHECK2-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 2807 // CHECK2-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 2808 // CHECK2-NEXT: ] 2809 // CHECK2: .omp.reduction.case1: 2810 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP1]], align 128 2811 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR2]], align 128 2812 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] 2813 // CHECK2-NEXT: store i32 [[ADD]], i32* [[TMP1]], align 128 2814 // CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) 2815 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8* 2816 // CHECK2-NEXT: [[TMP24:%.*]] = bitcast %struct.S.0* [[CALL]] to i8* 2817 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP23]], i8* align 4 [[TMP24]], i64 4, i1 false) 2818 // CHECK2-NEXT: [[CALL7:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP4]]) 2819 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL7]], 0 2820 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] 2821 // CHECK2: land.rhs: 2822 // CHECK2-NEXT: [[CALL8:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) 2823 // CHECK2-NEXT: [[TOBOOL9:%.*]] = icmp ne i32 [[CALL8]], 0 2824 // CHECK2-NEXT: br label [[LAND_END]] 2825 // CHECK2: land.end: 2826 // CHECK2-NEXT: [[TMP25:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL9]], [[LAND_RHS]] ] 2827 // CHECK2-NEXT: [[CONV:%.*]] = zext i1 [[TMP25]] to i32 2828 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[CONV]]) 2829 // CHECK2-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* 2830 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* 2831 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) 2832 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] 2833 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP5]], align 128 2834 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[T_VAR15]], align 128 2835 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP28]], [[TMP29]] 2836 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2837 // CHECK2: cond.true: 2838 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP5]], align 128 2839 // CHECK2-NEXT: br label [[COND_END:%.*]] 2840 // CHECK2: cond.false: 2841 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[T_VAR15]], align 128 2842 // CHECK2-NEXT: br label [[COND_END]] 2843 // CHECK2: cond.end: 2844 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP30]], [[COND_TRUE]] ], [ [[TMP31]], [[COND_FALSE]] ] 2845 // CHECK2-NEXT: store i32 [[COND]], i32* [[TMP5]], align 128 2846 // CHECK2-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.reduction.var) 2847 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 2848 // CHECK2: .omp.reduction.case2: 2849 // CHECK2-NEXT: [[TMP32:%.*]] = load i32, i32* [[T_VAR2]], align 128 2850 // CHECK2-NEXT: [[TMP33:%.*]] = atomicrmw add i32* [[TMP1]], i32 [[TMP32]] monotonic, align 4 2851 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) 2852 // CHECK2-NEXT: [[CALL10:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) 2853 // CHECK2-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8* 2854 // CHECK2-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[CALL10]] to i8* 2855 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) 2856 // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) 2857 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) 2858 // CHECK2-NEXT: [[CALL12:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP4]]) 2859 // CHECK2-NEXT: [[TOBOOL13:%.*]] = icmp ne i32 [[CALL12]], 0 2860 // CHECK2-NEXT: br i1 [[TOBOOL13]], label [[LAND_RHS14:%.*]], label [[LAND_END17:%.*]] 2861 // CHECK2: land.rhs14: 2862 // CHECK2-NEXT: [[CALL15:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) 2863 // CHECK2-NEXT: [[TOBOOL16:%.*]] = icmp ne i32 [[CALL15]], 0 2864 // CHECK2-NEXT: br label [[LAND_END17]] 2865 // CHECK2: land.end17: 2866 // CHECK2-NEXT: [[TMP36:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE2]] ], [ [[TOBOOL16]], [[LAND_RHS14]] ] 2867 // CHECK2-NEXT: [[CONV18:%.*]] = zext i1 [[TMP36]] to i32 2868 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP11]], i32 [[CONV18]]) 2869 // CHECK2-NEXT: [[TMP37:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* 2870 // CHECK2-NEXT: [[TMP38:%.*]] = bitcast %struct.S.0* [[REF_TMP11]] to i8* 2871 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP37]], i8* align 4 [[TMP38]], i64 4, i1 false) 2872 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP11]]) #[[ATTR5]] 2873 // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) 2874 // CHECK2-NEXT: [[TMP39:%.*]] = load i32, i32* [[T_VAR15]], align 128 2875 // CHECK2-NEXT: [[TMP40:%.*]] = atomicrmw min i32* [[TMP5]], i32 [[TMP39]] monotonic, align 4 2876 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 2877 // CHECK2: .omp.reduction.default: 2878 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR5]] 2879 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR5]] 2880 // CHECK2-NEXT: ret void 2881 // 2882 // 2883 // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.9 2884 // CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { 2885 // CHECK2-NEXT: entry: 2886 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2887 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 2888 // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2889 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2890 // CHECK2-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 2891 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 2892 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [4 x i8*]* 2893 // CHECK2-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 2894 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [4 x i8*]* 2895 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP5]], i64 0, i64 0 2896 // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 2897 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 2898 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 0 2899 // CHECK2-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 2900 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 2901 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP5]], i64 0, i64 1 2902 // CHECK2-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8 2903 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to %struct.S.0* 2904 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 1 2905 // CHECK2-NEXT: [[TMP16:%.*]] = load i8*, i8** [[TMP15]], align 8 2906 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8* [[TMP16]] to %struct.S.0* 2907 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP5]], i64 0, i64 2 2908 // CHECK2-NEXT: [[TMP19:%.*]] = load i8*, i8** [[TMP18]], align 8 2909 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8* [[TMP19]] to %struct.S.0* 2910 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 2 2911 // CHECK2-NEXT: [[TMP22:%.*]] = load i8*, i8** [[TMP21]], align 8 2912 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8* [[TMP22]] to %struct.S.0* 2913 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP5]], i64 0, i64 3 2914 // CHECK2-NEXT: [[TMP25:%.*]] = load i8*, i8** [[TMP24]], align 8 2915 // CHECK2-NEXT: [[TMP26:%.*]] = bitcast i8* [[TMP25]] to i32* 2916 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 3 2917 // CHECK2-NEXT: [[TMP28:%.*]] = load i8*, i8** [[TMP27]], align 8 2918 // CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8* [[TMP28]] to i32* 2919 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP11]], align 128 2920 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP8]], align 128 2921 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 2922 // CHECK2-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 128 2923 // CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP17]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP14]]) 2924 // CHECK2-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* 2925 // CHECK2-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[CALL]] to i8* 2926 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) 2927 // CHECK2-NEXT: [[CALL2:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP23]]) 2928 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL2]], 0 2929 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] 2930 // CHECK2: land.rhs: 2931 // CHECK2-NEXT: [[CALL3:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP20]]) 2932 // CHECK2-NEXT: [[TOBOOL4:%.*]] = icmp ne i32 [[CALL3]], 0 2933 // CHECK2-NEXT: br label [[LAND_END]] 2934 // CHECK2: land.end: 2935 // CHECK2-NEXT: [[TMP34:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ] 2936 // CHECK2-NEXT: [[CONV:%.*]] = zext i1 [[TMP34]] to i32 2937 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[CONV]]) 2938 // CHECK2-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP23]] to i8* 2939 // CHECK2-NEXT: [[TMP36:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* 2940 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) 2941 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] 2942 // CHECK2-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP29]], align 128 2943 // CHECK2-NEXT: [[TMP38:%.*]] = load i32, i32* [[TMP26]], align 128 2944 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]] 2945 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2946 // CHECK2: cond.true: 2947 // CHECK2-NEXT: [[TMP39:%.*]] = load i32, i32* [[TMP29]], align 128 2948 // CHECK2-NEXT: br label [[COND_END:%.*]] 2949 // CHECK2: cond.false: 2950 // CHECK2-NEXT: [[TMP40:%.*]] = load i32, i32* [[TMP26]], align 128 2951 // CHECK2-NEXT: br label [[COND_END]] 2952 // CHECK2: cond.end: 2953 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP39]], [[COND_TRUE]] ], [ [[TMP40]], [[COND_FALSE]] ] 2954 // CHECK2-NEXT: store i32 [[COND]], i32* [[TMP29]], align 128 2955 // CHECK2-NEXT: ret void 2956 // 2957 // 2958 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEanERKS0_ 2959 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR0]] align 2 { 2960 // CHECK2-NEXT: entry: 2961 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2962 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 2963 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2964 // CHECK2-NEXT: store %struct.S.0* [[TMP0]], %struct.S.0** [[DOTADDR]], align 8 2965 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2966 // CHECK2-NEXT: ret %struct.S.0* [[THIS1]] 2967 // 2968 // 2969 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEcviEv 2970 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR0]] align 2 { 2971 // CHECK2-NEXT: entry: 2972 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2973 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2974 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2975 // CHECK2-NEXT: ret i32 0 2976 // 2977 // 2978 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2979 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 2980 // CHECK2-NEXT: entry: 2981 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2982 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2983 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2984 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] 2985 // CHECK2-NEXT: ret void 2986 // 2987 // 2988 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2989 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 2990 // CHECK2-NEXT: entry: 2991 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2992 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2993 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2994 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2995 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 2996 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2997 // CHECK2-NEXT: ret void 2998 // 2999 // 3000 // CHECK2-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev 3001 // CHECK2-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 3002 // CHECK2-NEXT: entry: 3003 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 3004 // CHECK2-NEXT: [[A2:%.*]] = alloca i32*, align 8 3005 // CHECK2-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 3006 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 3007 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 3008 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 3009 // CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 3010 // CHECK2-NEXT: store i32* [[A3]], i32** [[A2]], align 8 3011 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 3012 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.SST* [[THIS1]], i32* [[TMP0]]) 3013 // CHECK2-NEXT: ret void 3014 // 3015 // 3016 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 3017 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1]] { 3018 // CHECK2-NEXT: entry: 3019 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3020 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3021 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 3022 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 3023 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32*, align 8 3024 // CHECK2-NEXT: [[A1:%.*]] = alloca i32, align 4 3025 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 3026 // CHECK2-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 3027 // CHECK2-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4 3028 // CHECK2-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 3029 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3030 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3031 // CHECK2-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 3032 // CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 3033 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 3034 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 3035 // CHECK2-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8 3036 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 3037 // CHECK2-NEXT: store i32 1, i32* [[A1]], align 4 3038 // CHECK2-NEXT: store i32* [[A1]], i32** [[_TMP2]], align 8 3039 // CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[_TMP2]], align 8 3040 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 3041 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 3042 // CHECK2-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 3043 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 3044 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i32* [[A1]] to i8* 3045 // CHECK2-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8 3046 // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3047 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 3048 // CHECK2-NEXT: [[TMP9:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 3049 // CHECK2-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 1, i64 8, i8* [[TMP9]], void (i8*, i8*)* @.omp.reduction.reduction_func.11, [8 x i32]* @.gomp_critical_user_.reduction.var) 3050 // CHECK2-NEXT: switch i32 [[TMP10]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 3051 // CHECK2-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 3052 // CHECK2-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 3053 // CHECK2-NEXT: ] 3054 // CHECK2: .omp.reduction.case1: 3055 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP2]], align 4 3056 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[A1]], align 4 3057 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], [[TMP12]] 3058 // CHECK2-NEXT: store i32 [[MUL]], i32* [[TMP2]], align 4 3059 // CHECK2-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], [8 x i32]* @.gomp_critical_user_.reduction.var) 3060 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 3061 // CHECK2: .omp.reduction.case2: 3062 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[A1]], align 4 3063 // CHECK2-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i32, i32* [[TMP2]] monotonic, align 4 3064 // CHECK2-NEXT: br label [[ATOMIC_CONT:%.*]] 3065 // CHECK2: atomic_cont: 3066 // CHECK2-NEXT: [[TMP14:%.*]] = phi i32 [ [[ATOMIC_LOAD]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[TMP19:%.*]], [[ATOMIC_CONT]] ] 3067 // CHECK2-NEXT: store i32 [[TMP14]], i32* [[_TMP3]], align 4 3068 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[_TMP3]], align 4 3069 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[A1]], align 4 3070 // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[TMP15]], [[TMP16]] 3071 // CHECK2-NEXT: store i32 [[MUL4]], i32* [[ATOMIC_TEMP]], align 4 3072 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[ATOMIC_TEMP]], align 4 3073 // CHECK2-NEXT: [[TMP18:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP14]], i32 [[TMP17]] monotonic monotonic, align 4 3074 // CHECK2-NEXT: [[TMP19]] = extractvalue { i32, i1 } [[TMP18]], 0 3075 // CHECK2-NEXT: [[TMP20:%.*]] = extractvalue { i32, i1 } [[TMP18]], 1 3076 // CHECK2-NEXT: br i1 [[TMP20]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] 3077 // CHECK2: atomic_exit: 3078 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 3079 // CHECK2: .omp.reduction.default: 3080 // CHECK2-NEXT: ret void 3081 // 3082 // 3083 // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.11 3084 // CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { 3085 // CHECK2-NEXT: entry: 3086 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 3087 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 3088 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 3089 // CHECK2-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 3090 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 3091 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 3092 // CHECK2-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 3093 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 3094 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 3095 // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 3096 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 3097 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 3098 // CHECK2-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 3099 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 3100 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 3101 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 3102 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]] 3103 // CHECK2-NEXT: store i32 [[MUL]], i32* [[TMP11]], align 4 3104 // CHECK2-NEXT: ret void 3105 // 3106 // 3107 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3108 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 3109 // CHECK2-NEXT: entry: 3110 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3111 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3112 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3113 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3114 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3115 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3116 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3117 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 3118 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3119 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3120 // CHECK2-NEXT: ret void 3121 // 3122 // 3123 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3124 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 3125 // CHECK2-NEXT: entry: 3126 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3127 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3128 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3129 // CHECK2-NEXT: ret void 3130 // 3131 // 3132 // CHECK3-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs 3133 // CHECK3-SAME: (i16* [[X:%.*]]) #[[ATTR0:[0-9]+]] { 3134 // CHECK3-NEXT: entry: 3135 // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 3136 // CHECK3-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 3137 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[X_ADDR]], align 8 3138 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined. to void (i32*, i32*, ...)*), i16* [[TMP0]]) 3139 // CHECK3-NEXT: ret void 3140 // 3141 // 3142 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 3143 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* [[X:%.*]]) #[[ATTR1:[0-9]+]] { 3144 // CHECK3-NEXT: entry: 3145 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3146 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3147 // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 3148 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3149 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3150 // CHECK3-NEXT: [[TMP:%.*]] = alloca i16*, align 8 3151 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [2 x i8*], align 8 3152 // CHECK3-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i16, align 2 3153 // CHECK3-NEXT: [[_TMP13:%.*]] = alloca i16, align 2 3154 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3155 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3156 // CHECK3-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 3157 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[X_ADDR]], align 8 3158 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP0]], i64 0 3159 // CHECK3-NEXT: [[TMP1:%.*]] = load i16*, i16** [[X_ADDR]], align 8 3160 // CHECK3-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i16, i16* [[TMP1]], i64 0 3161 // CHECK3-NEXT: [[TMP2:%.*]] = ptrtoint i16* [[ARRAYIDX1]] to i64 3162 // CHECK3-NEXT: [[TMP3:%.*]] = ptrtoint i16* [[ARRAYIDX]] to i64 3163 // CHECK3-NEXT: [[TMP4:%.*]] = sub i64 [[TMP2]], [[TMP3]] 3164 // CHECK3-NEXT: [[TMP5:%.*]] = sdiv exact i64 [[TMP4]], ptrtoint (i16* getelementptr (i16, i16* null, i32 1) to i64) 3165 // CHECK3-NEXT: [[TMP6:%.*]] = add nuw i64 [[TMP5]], 1 3166 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], ptrtoint (i16* getelementptr (i16, i16* null, i32 1) to i64) 3167 // CHECK3-NEXT: [[TMP8:%.*]] = call i8* @llvm.stacksave() 3168 // CHECK3-NEXT: store i8* [[TMP8]], i8** [[SAVED_STACK]], align 8 3169 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP6]], align 16 3170 // CHECK3-NEXT: store i64 [[TMP6]], i64* [[__VLA_EXPR0]], align 8 3171 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr i16, i16* [[VLA]], i64 [[TMP6]] 3172 // CHECK3-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq i16* [[VLA]], [[TMP9]] 3173 // CHECK3-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] 3174 // CHECK3: omp.arrayinit.body: 3175 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i16* [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] 3176 // CHECK3-NEXT: store i16 0, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 2 3177 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3178 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i16* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] 3179 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] 3180 // CHECK3: omp.arrayinit.done: 3181 // CHECK3-NEXT: [[TMP10:%.*]] = load i16*, i16** [[X_ADDR]], align 8 3182 // CHECK3-NEXT: [[TMP11:%.*]] = ptrtoint i16* [[TMP10]] to i64 3183 // CHECK3-NEXT: [[TMP12:%.*]] = ptrtoint i16* [[ARRAYIDX]] to i64 3184 // CHECK3-NEXT: [[TMP13:%.*]] = sub i64 [[TMP11]], [[TMP12]] 3185 // CHECK3-NEXT: [[TMP14:%.*]] = sdiv exact i64 [[TMP13]], ptrtoint (i16* getelementptr (i16, i16* null, i32 1) to i64) 3186 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr i16, i16* [[VLA]], i64 [[TMP14]] 3187 // CHECK3-NEXT: store i16* [[TMP15]], i16** [[TMP]], align 8 3188 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 3189 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i16* [[VLA]] to i8* 3190 // CHECK3-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8 3191 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1 3192 // CHECK3-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP6]] to i8* 3193 // CHECK3-NEXT: store i8* [[TMP19]], i8** [[TMP18]], align 8 3194 // CHECK3-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3195 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 3196 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast [2 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 3197 // CHECK3-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP21]], i32 1, i64 16, i8* [[TMP22]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 3198 // CHECK3-NEXT: switch i32 [[TMP23]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 3199 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 3200 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 3201 // CHECK3-NEXT: ] 3202 // CHECK3: .omp.reduction.case1: 3203 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr i16, i16* [[ARRAYIDX]], i64 [[TMP6]] 3204 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq i16* [[ARRAYIDX]], [[TMP24]] 3205 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE7:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3206 // CHECK3: omp.arraycpy.body: 3207 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i16* [ [[VLA]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3208 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST2:%.*]] = phi i16* [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT5:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3209 // CHECK3-NEXT: [[TMP25:%.*]] = load i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST2]], align 2 3210 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP25]] to i32 3211 // CHECK3-NEXT: [[TMP26:%.*]] = load i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 2 3212 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP26]] to i32 3213 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV3]] 3214 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD]] to i16 3215 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[OMP_ARRAYCPY_DESTELEMENTPAST2]], align 2 3216 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT5]] = getelementptr i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST2]], i32 1 3217 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3218 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE6:%.*]] = icmp eq i16* [[OMP_ARRAYCPY_DEST_ELEMENT5]], [[TMP24]] 3219 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_DONE7]], label [[OMP_ARRAYCPY_BODY]] 3220 // CHECK3: omp.arraycpy.done7: 3221 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]], [8 x i32]* @.gomp_critical_user_.reduction.var) 3222 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 3223 // CHECK3: .omp.reduction.case2: 3224 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr i16, i16* [[ARRAYIDX]], i64 [[TMP6]] 3225 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY8:%.*]] = icmp eq i16* [[ARRAYIDX]], [[TMP27]] 3226 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY8]], label [[OMP_ARRAYCPY_DONE21:%.*]], label [[OMP_ARRAYCPY_BODY9:%.*]] 3227 // CHECK3: omp.arraycpy.body9: 3228 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST10:%.*]] = phi i16* [ [[VLA]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT19:%.*]], [[ATOMIC_EXIT:%.*]] ] 3229 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST11:%.*]] = phi i16* [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT18:%.*]], [[ATOMIC_EXIT]] ] 3230 // CHECK3-NEXT: [[TMP28:%.*]] = load i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST10]], align 2 3231 // CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP28]] to i32 3232 // CHECK3-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST11]] monotonic, align 2 3233 // CHECK3-NEXT: br label [[ATOMIC_CONT:%.*]] 3234 // CHECK3: atomic_cont: 3235 // CHECK3-NEXT: [[TMP29:%.*]] = phi i16 [ [[ATOMIC_LOAD]], [[OMP_ARRAYCPY_BODY9]] ], [ [[TMP34:%.*]], [[ATOMIC_CONT]] ] 3236 // CHECK3-NEXT: store i16 [[TMP29]], i16* [[_TMP13]], align 2 3237 // CHECK3-NEXT: [[TMP30:%.*]] = load i16, i16* [[_TMP13]], align 2 3238 // CHECK3-NEXT: [[CONV14:%.*]] = sext i16 [[TMP30]] to i32 3239 // CHECK3-NEXT: [[TMP31:%.*]] = load i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST10]], align 2 3240 // CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP31]] to i32 3241 // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV14]], [[CONV15]] 3242 // CHECK3-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i16 3243 // CHECK3-NEXT: store i16 [[CONV17]], i16* [[ATOMIC_TEMP]], align 2 3244 // CHECK3-NEXT: [[TMP32:%.*]] = load i16, i16* [[ATOMIC_TEMP]], align 2 3245 // CHECK3-NEXT: [[TMP33:%.*]] = cmpxchg i16* [[OMP_ARRAYCPY_DESTELEMENTPAST11]], i16 [[TMP29]], i16 [[TMP32]] monotonic monotonic, align 2 3246 // CHECK3-NEXT: [[TMP34]] = extractvalue { i16, i1 } [[TMP33]], 0 3247 // CHECK3-NEXT: [[TMP35:%.*]] = extractvalue { i16, i1 } [[TMP33]], 1 3248 // CHECK3-NEXT: br i1 [[TMP35]], label [[ATOMIC_EXIT]], label [[ATOMIC_CONT]] 3249 // CHECK3: atomic_exit: 3250 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT18]] = getelementptr i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST11]], i32 1 3251 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT19]] = getelementptr i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST10]], i32 1 3252 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE20:%.*]] = icmp eq i16* [[OMP_ARRAYCPY_DEST_ELEMENT18]], [[TMP27]] 3253 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE20]], label [[OMP_ARRAYCPY_DONE21]], label [[OMP_ARRAYCPY_BODY9]] 3254 // CHECK3: omp.arraycpy.done21: 3255 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 3256 // CHECK3: .omp.reduction.default: 3257 // CHECK3-NEXT: [[TMP36:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 3258 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP36]]) 3259 // CHECK3-NEXT: ret void 3260 // 3261 // 3262 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 3263 // CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { 3264 // CHECK3-NEXT: entry: 3265 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 3266 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 3267 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 3268 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 3269 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 3270 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [2 x i8*]* 3271 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 3272 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [2 x i8*]* 3273 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP5]], i64 0, i64 0 3274 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 3275 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i16* 3276 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP3]], i64 0, i64 0 3277 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 3278 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i16* 3279 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP3]], i64 0, i64 1 3280 // CHECK3-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8 3281 // CHECK3-NEXT: [[TMP14:%.*]] = ptrtoint i8* [[TMP13]] to i64 3282 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr i16, i16* [[TMP11]], i64 [[TMP14]] 3283 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq i16* [[TMP11]], [[TMP15]] 3284 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3285 // CHECK3: omp.arraycpy.body: 3286 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i16* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3287 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i16* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3288 // CHECK3-NEXT: [[TMP16:%.*]] = load i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 2 3289 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP16]] to i32 3290 // CHECK3-NEXT: [[TMP17:%.*]] = load i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 2 3291 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP17]] to i32 3292 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV2]] 3293 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 3294 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 2 3295 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3296 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3297 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i16* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP15]] 3298 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 3299 // CHECK3: omp.arraycpy.done4: 3300 // CHECK3-NEXT: ret void 3301 // 3302 // 3303 // CHECK3-LABEL: define {{[^@]+}}@main 3304 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] { 3305 // CHECK3-NEXT: entry: 3306 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3307 // CHECK3-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 3308 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 3309 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 3310 // CHECK3-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) 3311 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 3312 // CHECK3-NEXT: ret i32 0 3313 // 3314 // 3315 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 3316 // CHECK3-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] align 2 { 3317 // CHECK3-NEXT: entry: 3318 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3319 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 3320 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3321 // CHECK3-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 3322 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3323 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 3324 // CHECK3-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) 3325 // CHECK3-NEXT: ret void 3326 // 3327 // 3328 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 3329 // CHECK3-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR7]] align 2 { 3330 // CHECK3-NEXT: entry: 3331 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3332 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 3333 // CHECK3-NEXT: [[A2:%.*]] = alloca i32*, align 8 3334 // CHECK3-NEXT: [[B4:%.*]] = alloca i32, align 4 3335 // CHECK3-NEXT: [[C5:%.*]] = alloca i32*, align 8 3336 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3337 // CHECK3-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 3338 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3339 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 3340 // CHECK3-NEXT: store i32 0, i32* [[A]], align 8 3341 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 3342 // CHECK3-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 3343 // CHECK3-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 3344 // CHECK3-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 3345 // CHECK3-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 3346 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 3347 // CHECK3-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 3348 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 3349 // CHECK3-NEXT: store i32* [[A3]], i32** [[A2]], align 8 3350 // CHECK3-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 3351 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 3352 // CHECK3-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 3353 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 3354 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 3355 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i32* [[TMP2]], i32* [[B4]], i32* [[TMP3]]) 3356 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B4]], align 4 3357 // CHECK3-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 3358 // CHECK3-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8 3359 // CHECK3-NEXT: [[BF_LOAD8:%.*]] = load i8, i8* [[B7]], align 4 3360 // CHECK3-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP5]], 15 3361 // CHECK3-NEXT: [[BF_CLEAR9:%.*]] = and i8 [[BF_LOAD8]], -16 3362 // CHECK3-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR9]], [[BF_VALUE]] 3363 // CHECK3-NEXT: store i8 [[BF_SET]], i8* [[B7]], align 4 3364 // CHECK3-NEXT: ret void 3365 // 3366 // 3367 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 3368 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { 3369 // CHECK3-NEXT: entry: 3370 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3371 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3372 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3373 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 3374 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 3375 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 3376 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32*, align 8 3377 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 3378 // CHECK3-NEXT: [[A2:%.*]] = alloca i32, align 4 3379 // CHECK3-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 3380 // CHECK3-NEXT: [[B4:%.*]] = alloca i32, align 4 3381 // CHECK3-NEXT: [[C5:%.*]] = alloca i32, align 4 3382 // CHECK3-NEXT: [[_TMP6:%.*]] = alloca i32*, align 8 3383 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 3384 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [3 x i8*], align 8 3385 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3386 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3387 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3388 // CHECK3-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 3389 // CHECK3-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 3390 // CHECK3-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 3391 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3392 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 3393 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[B_ADDR]], align 8 3394 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C_ADDR]], align 8 3395 // CHECK3-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8 3396 // CHECK3-NEXT: store i32* [[TMP3]], i32** [[_TMP1]], align 8 3397 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 3398 // CHECK3-NEXT: store i32 0, i32* [[A2]], align 4 3399 // CHECK3-NEXT: store i32* [[A2]], i32** [[_TMP3]], align 8 3400 // CHECK3-NEXT: store i32 0, i32* [[B4]], align 4 3401 // CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[_TMP1]], align 8 3402 // CHECK3-NEXT: store i32 0, i32* [[C5]], align 4 3403 // CHECK3-NEXT: store i32* [[C5]], i32** [[_TMP6]], align 8 3404 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 3405 // CHECK3-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[TMP6]], align 8 3406 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 3407 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP3]], align 8 3408 // CHECK3-NEXT: store i32* [[TMP8]], i32** [[TMP7]], align 8 3409 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 3410 // CHECK3-NEXT: store i32* [[B4]], i32** [[TMP9]], align 8 3411 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 3412 // CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP6]], align 8 3413 // CHECK3-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 3414 // CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) 3415 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 3416 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i32* [[A2]] to i8* 3417 // CHECK3-NEXT: store i8* [[TMP13]], i8** [[TMP12]], align 8 3418 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1 3419 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i32* [[B4]] to i8* 3420 // CHECK3-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 3421 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 2 3422 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i32* [[C5]] to i8* 3423 // CHECK3-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8 3424 // CHECK3-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3425 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 3426 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 3427 // CHECK3-NEXT: [[TMP21:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]], i32 3, i64 24, i8* [[TMP20]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) 3428 // CHECK3-NEXT: switch i32 [[TMP21]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 3429 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 3430 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 3431 // CHECK3-NEXT: ] 3432 // CHECK3: .omp.reduction.case1: 3433 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP4]], align 4 3434 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[A2]], align 4 3435 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] 3436 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP4]], align 4 3437 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP2]], align 4 3438 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[B4]], align 4 3439 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] 3440 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[TMP2]], align 4 3441 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP5]], align 4 3442 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[C5]], align 4 3443 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] 3444 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[TMP5]], align 4 3445 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]], [8 x i32]* @.gomp_critical_user_.reduction.var) 3446 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 3447 // CHECK3: .omp.reduction.case2: 3448 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[A2]], align 4 3449 // CHECK3-NEXT: [[TMP29:%.*]] = atomicrmw add i32* [[TMP4]], i32 [[TMP28]] monotonic, align 4 3450 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[B4]], align 4 3451 // CHECK3-NEXT: [[TMP31:%.*]] = atomicrmw add i32* [[TMP2]], i32 [[TMP30]] monotonic, align 4 3452 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[C5]], align 4 3453 // CHECK3-NEXT: [[TMP33:%.*]] = atomicrmw add i32* [[TMP5]], i32 [[TMP32]] monotonic, align 4 3454 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 3455 // CHECK3: .omp.reduction.default: 3456 // CHECK3-NEXT: ret void 3457 // 3458 // 3459 // CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv 3460 // CHECK3-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR0]] align 2 { 3461 // CHECK3-NEXT: entry: 3462 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 3463 // CHECK3-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 3464 // CHECK3-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 3465 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 3466 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 3467 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 3468 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 3469 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 3470 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 3471 // CHECK3-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 3472 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 3473 // CHECK3-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 3474 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 3475 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 3476 // CHECK3-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 3477 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 3478 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 3479 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 3480 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 3481 // CHECK3-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 3482 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 3483 // CHECK3-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 3484 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 3485 // CHECK3-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 8 3486 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 3487 // CHECK3-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 3488 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i32*, i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SS* [[TMP1]], i32* [[TMP12]], i32* [[TMP14]], i32* [[TMP16]]) 3489 // CHECK3-NEXT: ret void 3490 // 3491 // 3492 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 3493 // CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { 3494 // CHECK3-NEXT: entry: 3495 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 3496 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 3497 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 3498 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 3499 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 3500 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [3 x i8*]* 3501 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 3502 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [3 x i8*]* 3503 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP5]], i64 0, i64 0 3504 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 3505 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 3506 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP3]], i64 0, i64 0 3507 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 3508 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 3509 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP5]], i64 0, i64 1 3510 // CHECK3-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8 3511 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to i32* 3512 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP3]], i64 0, i64 1 3513 // CHECK3-NEXT: [[TMP16:%.*]] = load i8*, i8** [[TMP15]], align 8 3514 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8* [[TMP16]] to i32* 3515 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP5]], i64 0, i64 2 3516 // CHECK3-NEXT: [[TMP19:%.*]] = load i8*, i8** [[TMP18]], align 8 3517 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8* [[TMP19]] to i32* 3518 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP3]], i64 0, i64 2 3519 // CHECK3-NEXT: [[TMP22:%.*]] = load i8*, i8** [[TMP21]], align 8 3520 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8* [[TMP22]] to i32* 3521 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP11]], align 4 3522 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP8]], align 4 3523 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] 3524 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 3525 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP17]], align 4 3526 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP14]], align 4 3527 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] 3528 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[TMP17]], align 4 3529 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP23]], align 4 3530 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP20]], align 4 3531 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 3532 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[TMP23]], align 4 3533 // CHECK3-NEXT: ret void 3534 // 3535 // 3536 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 3537 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { 3538 // CHECK3-NEXT: entry: 3539 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3540 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3541 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3542 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 3543 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 3544 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 3545 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32*, align 8 3546 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 3547 // CHECK3-NEXT: [[A2:%.*]] = alloca i32, align 4 3548 // CHECK3-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 3549 // CHECK3-NEXT: [[B4:%.*]] = alloca i32, align 4 3550 // CHECK3-NEXT: [[C5:%.*]] = alloca i32, align 4 3551 // CHECK3-NEXT: [[_TMP6:%.*]] = alloca i32*, align 8 3552 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [3 x i8*], align 8 3553 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3554 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3555 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3556 // CHECK3-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 3557 // CHECK3-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 3558 // CHECK3-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 3559 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3560 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 3561 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[B_ADDR]], align 8 3562 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C_ADDR]], align 8 3563 // CHECK3-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8 3564 // CHECK3-NEXT: store i32* [[TMP3]], i32** [[_TMP1]], align 8 3565 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 3566 // CHECK3-NEXT: store i32 -1, i32* [[A2]], align 4 3567 // CHECK3-NEXT: store i32* [[A2]], i32** [[_TMP3]], align 8 3568 // CHECK3-NEXT: store i32 -1, i32* [[B4]], align 4 3569 // CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[_TMP1]], align 8 3570 // CHECK3-NEXT: store i32 -1, i32* [[C5]], align 4 3571 // CHECK3-NEXT: store i32* [[C5]], i32** [[_TMP6]], align 8 3572 // CHECK3-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP3]], align 8 3573 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 3574 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 3575 // CHECK3-NEXT: store i32 [[INC]], i32* [[TMP6]], align 4 3576 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[B4]], align 4 3577 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 3578 // CHECK3-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 3579 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[_TMP6]], align 8 3580 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 3581 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 3582 // CHECK3-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 3583 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 3584 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i32* [[A2]] to i8* 3585 // CHECK3-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 8 3586 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1 3587 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i32* [[B4]] to i8* 3588 // CHECK3-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 3589 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 2 3590 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i32* [[C5]] to i8* 3591 // CHECK3-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 3592 // CHECK3-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3593 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 3594 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 3595 // CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 3, i64 24, i8* [[TMP19]], void (i8*, i8*)* @.omp.reduction.reduction_func.4, [8 x i32]* @.gomp_critical_user_.reduction.var) 3596 // CHECK3-NEXT: switch i32 [[TMP20]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 3597 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 3598 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 3599 // CHECK3-NEXT: ] 3600 // CHECK3: .omp.reduction.case1: 3601 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP4]], align 4 3602 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[A2]], align 4 3603 // CHECK3-NEXT: [[AND:%.*]] = and i32 [[TMP21]], [[TMP22]] 3604 // CHECK3-NEXT: store i32 [[AND]], i32* [[TMP4]], align 4 3605 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP2]], align 4 3606 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[B4]], align 4 3607 // CHECK3-NEXT: [[AND7:%.*]] = and i32 [[TMP23]], [[TMP24]] 3608 // CHECK3-NEXT: store i32 [[AND7]], i32* [[TMP2]], align 4 3609 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP5]], align 4 3610 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[C5]], align 4 3611 // CHECK3-NEXT: [[AND8:%.*]] = and i32 [[TMP25]], [[TMP26]] 3612 // CHECK3-NEXT: store i32 [[AND8]], i32* [[TMP5]], align 4 3613 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.reduction.var) 3614 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 3615 // CHECK3: .omp.reduction.case2: 3616 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[A2]], align 4 3617 // CHECK3-NEXT: [[TMP28:%.*]] = atomicrmw and i32* [[TMP4]], i32 [[TMP27]] monotonic, align 4 3618 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[B4]], align 4 3619 // CHECK3-NEXT: [[TMP30:%.*]] = atomicrmw and i32* [[TMP2]], i32 [[TMP29]] monotonic, align 4 3620 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[C5]], align 4 3621 // CHECK3-NEXT: [[TMP32:%.*]] = atomicrmw and i32* [[TMP5]], i32 [[TMP31]] monotonic, align 4 3622 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 3623 // CHECK3: .omp.reduction.default: 3624 // CHECK3-NEXT: ret void 3625 // 3626 // 3627 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.4 3628 // CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { 3629 // CHECK3-NEXT: entry: 3630 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 3631 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 3632 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 3633 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 3634 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 3635 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [3 x i8*]* 3636 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 3637 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [3 x i8*]* 3638 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP5]], i64 0, i64 0 3639 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 3640 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 3641 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP3]], i64 0, i64 0 3642 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 3643 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 3644 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP5]], i64 0, i64 1 3645 // CHECK3-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8 3646 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to i32* 3647 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP3]], i64 0, i64 1 3648 // CHECK3-NEXT: [[TMP16:%.*]] = load i8*, i8** [[TMP15]], align 8 3649 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8* [[TMP16]] to i32* 3650 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP5]], i64 0, i64 2 3651 // CHECK3-NEXT: [[TMP19:%.*]] = load i8*, i8** [[TMP18]], align 8 3652 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8* [[TMP19]] to i32* 3653 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP3]], i64 0, i64 2 3654 // CHECK3-NEXT: [[TMP22:%.*]] = load i8*, i8** [[TMP21]], align 8 3655 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8* [[TMP22]] to i32* 3656 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP11]], align 4 3657 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP8]], align 4 3658 // CHECK3-NEXT: [[AND:%.*]] = and i32 [[TMP24]], [[TMP25]] 3659 // CHECK3-NEXT: store i32 [[AND]], i32* [[TMP11]], align 4 3660 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP17]], align 4 3661 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP14]], align 4 3662 // CHECK3-NEXT: [[AND2:%.*]] = and i32 [[TMP26]], [[TMP27]] 3663 // CHECK3-NEXT: store i32 [[AND2]], i32* [[TMP17]], align 4 3664 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP23]], align 4 3665 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP20]], align 4 3666 // CHECK3-NEXT: [[AND3:%.*]] = and i32 [[TMP28]], [[TMP29]] 3667 // CHECK3-NEXT: store i32 [[AND3]], i32* [[TMP23]], align 4 3668 // CHECK3-NEXT: ret void 3669 // 3670 // 3671 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 3672 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR1]] { 3673 // CHECK3-NEXT: entry: 3674 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3675 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3676 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 3677 // CHECK3-NEXT: [[G1:%.*]] = alloca i32, align 128 3678 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 3679 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 3680 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3681 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3682 // CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 3683 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 3684 // CHECK3-NEXT: store i32 0, i32* [[G1]], align 128 3685 // CHECK3-NEXT: store i32 1, i32* [[G1]], align 128 3686 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0 3687 // CHECK3-NEXT: store i32* [[G1]], i32** [[TMP1]], align 8 3688 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* nonnull align 8 dereferenceable(8) [[REF_TMP]]) 3689 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 3690 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i32* [[G1]] to i8* 3691 // CHECK3-NEXT: store i8* [[TMP3]], i8** [[TMP2]], align 8 3692 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3693 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3694 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 3695 // CHECK3-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 1, i64 8, i8* [[TMP6]], void (i8*, i8*)* @.omp.reduction.reduction_func.6, [8 x i32]* @.gomp_critical_user_.reduction.var) 3696 // CHECK3-NEXT: switch i32 [[TMP7]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 3697 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 3698 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 3699 // CHECK3-NEXT: ] 3700 // CHECK3: .omp.reduction.case1: 3701 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP0]], align 128 3702 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[G1]], align 128 3703 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 3704 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 128 3705 // CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], [8 x i32]* @.gomp_critical_user_.reduction.var) 3706 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 3707 // CHECK3: .omp.reduction.case2: 3708 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[G1]], align 128 3709 // CHECK3-NEXT: [[TMP11:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP10]] monotonic, align 4 3710 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 3711 // CHECK3: .omp.reduction.default: 3712 // CHECK3-NEXT: ret void 3713 // 3714 // 3715 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 3716 // CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { 3717 // CHECK3-NEXT: entry: 3718 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 3719 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 3720 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 3721 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 3722 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 3723 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 3724 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 3725 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 3726 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 3727 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 3728 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 3729 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 3730 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 3731 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 3732 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 128 3733 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 128 3734 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 3735 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 128 3736 // CHECK3-NEXT: ret void 3737 // 3738 // 3739 // CHECK4-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs 3740 // CHECK4-SAME: (i16* [[X:%.*]]) #[[ATTR1:[0-9]+]] { 3741 // CHECK4-NEXT: entry: 3742 // CHECK4-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 3743 // CHECK4-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 3744 // CHECK4-NEXT: [[TMP0:%.*]] = load i16*, i16** [[X_ADDR]], align 8 3745 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined. to void (i32*, i32*, ...)*), i16* [[TMP0]]) 3746 // CHECK4-NEXT: ret void 3747 // 3748 // 3749 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 3750 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* [[X:%.*]]) #[[ATTR2:[0-9]+]] { 3751 // CHECK4-NEXT: entry: 3752 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3753 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3754 // CHECK4-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 3755 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3756 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3757 // CHECK4-NEXT: [[TMP:%.*]] = alloca i16*, align 8 3758 // CHECK4-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [2 x i8*], align 8 3759 // CHECK4-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i16, align 2 3760 // CHECK4-NEXT: [[_TMP13:%.*]] = alloca i16, align 2 3761 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3762 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3763 // CHECK4-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 3764 // CHECK4-NEXT: [[TMP0:%.*]] = load i16*, i16** [[X_ADDR]], align 8 3765 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP0]], i64 0 3766 // CHECK4-NEXT: [[TMP1:%.*]] = load i16*, i16** [[X_ADDR]], align 8 3767 // CHECK4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i16, i16* [[TMP1]], i64 0 3768 // CHECK4-NEXT: [[TMP2:%.*]] = ptrtoint i16* [[ARRAYIDX1]] to i64 3769 // CHECK4-NEXT: [[TMP3:%.*]] = ptrtoint i16* [[ARRAYIDX]] to i64 3770 // CHECK4-NEXT: [[TMP4:%.*]] = sub i64 [[TMP2]], [[TMP3]] 3771 // CHECK4-NEXT: [[TMP5:%.*]] = sdiv exact i64 [[TMP4]], ptrtoint (i16* getelementptr (i16, i16* null, i32 1) to i64) 3772 // CHECK4-NEXT: [[TMP6:%.*]] = add nuw i64 [[TMP5]], 1 3773 // CHECK4-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], ptrtoint (i16* getelementptr (i16, i16* null, i32 1) to i64) 3774 // CHECK4-NEXT: [[TMP8:%.*]] = call i8* @llvm.stacksave() 3775 // CHECK4-NEXT: store i8* [[TMP8]], i8** [[SAVED_STACK]], align 8 3776 // CHECK4-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP6]], align 16 3777 // CHECK4-NEXT: store i64 [[TMP6]], i64* [[__VLA_EXPR0]], align 8 3778 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr i16, i16* [[VLA]], i64 [[TMP6]] 3779 // CHECK4-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq i16* [[VLA]], [[TMP9]] 3780 // CHECK4-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] 3781 // CHECK4: omp.arrayinit.body: 3782 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i16* [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] 3783 // CHECK4-NEXT: store i16 0, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 2 3784 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3785 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i16* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] 3786 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] 3787 // CHECK4: omp.arrayinit.done: 3788 // CHECK4-NEXT: [[TMP10:%.*]] = load i16*, i16** [[X_ADDR]], align 8 3789 // CHECK4-NEXT: [[TMP11:%.*]] = ptrtoint i16* [[TMP10]] to i64 3790 // CHECK4-NEXT: [[TMP12:%.*]] = ptrtoint i16* [[ARRAYIDX]] to i64 3791 // CHECK4-NEXT: [[TMP13:%.*]] = sub i64 [[TMP11]], [[TMP12]] 3792 // CHECK4-NEXT: [[TMP14:%.*]] = sdiv exact i64 [[TMP13]], ptrtoint (i16* getelementptr (i16, i16* null, i32 1) to i64) 3793 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr i16, i16* [[VLA]], i64 [[TMP14]] 3794 // CHECK4-NEXT: store i16* [[TMP15]], i16** [[TMP]], align 8 3795 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 3796 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i16* [[VLA]] to i8* 3797 // CHECK4-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8 3798 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1 3799 // CHECK4-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP6]] to i8* 3800 // CHECK4-NEXT: store i8* [[TMP19]], i8** [[TMP18]], align 8 3801 // CHECK4-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3802 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 3803 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast [2 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 3804 // CHECK4-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP21]], i32 1, i64 16, i8* [[TMP22]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 3805 // CHECK4-NEXT: switch i32 [[TMP23]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 3806 // CHECK4-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 3807 // CHECK4-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 3808 // CHECK4-NEXT: ] 3809 // CHECK4: .omp.reduction.case1: 3810 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr i16, i16* [[ARRAYIDX]], i64 [[TMP6]] 3811 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq i16* [[ARRAYIDX]], [[TMP24]] 3812 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE7:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3813 // CHECK4: omp.arraycpy.body: 3814 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i16* [ [[VLA]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3815 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST2:%.*]] = phi i16* [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT5:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3816 // CHECK4-NEXT: [[TMP25:%.*]] = load i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST2]], align 2 3817 // CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP25]] to i32 3818 // CHECK4-NEXT: [[TMP26:%.*]] = load i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 2 3819 // CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP26]] to i32 3820 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV3]] 3821 // CHECK4-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD]] to i16 3822 // CHECK4-NEXT: store i16 [[CONV4]], i16* [[OMP_ARRAYCPY_DESTELEMENTPAST2]], align 2 3823 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT5]] = getelementptr i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST2]], i32 1 3824 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3825 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE6:%.*]] = icmp eq i16* [[OMP_ARRAYCPY_DEST_ELEMENT5]], [[TMP24]] 3826 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_DONE7]], label [[OMP_ARRAYCPY_BODY]] 3827 // CHECK4: omp.arraycpy.done7: 3828 // CHECK4-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]], [8 x i32]* @.gomp_critical_user_.reduction.var) 3829 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 3830 // CHECK4: .omp.reduction.case2: 3831 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr i16, i16* [[ARRAYIDX]], i64 [[TMP6]] 3832 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY8:%.*]] = icmp eq i16* [[ARRAYIDX]], [[TMP27]] 3833 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY8]], label [[OMP_ARRAYCPY_DONE21:%.*]], label [[OMP_ARRAYCPY_BODY9:%.*]] 3834 // CHECK4: omp.arraycpy.body9: 3835 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST10:%.*]] = phi i16* [ [[VLA]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT19:%.*]], [[ATOMIC_EXIT:%.*]] ] 3836 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST11:%.*]] = phi i16* [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT18:%.*]], [[ATOMIC_EXIT]] ] 3837 // CHECK4-NEXT: [[TMP28:%.*]] = load i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST10]], align 2 3838 // CHECK4-NEXT: [[CONV12:%.*]] = sext i16 [[TMP28]] to i32 3839 // CHECK4-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST11]] monotonic, align 2 3840 // CHECK4-NEXT: br label [[ATOMIC_CONT:%.*]] 3841 // CHECK4: atomic_cont: 3842 // CHECK4-NEXT: [[TMP29:%.*]] = phi i16 [ [[ATOMIC_LOAD]], [[OMP_ARRAYCPY_BODY9]] ], [ [[TMP34:%.*]], [[ATOMIC_CONT]] ] 3843 // CHECK4-NEXT: store i16 [[TMP29]], i16* [[_TMP13]], align 2 3844 // CHECK4-NEXT: [[TMP30:%.*]] = load i16, i16* [[_TMP13]], align 2 3845 // CHECK4-NEXT: [[CONV14:%.*]] = sext i16 [[TMP30]] to i32 3846 // CHECK4-NEXT: [[TMP31:%.*]] = load i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST10]], align 2 3847 // CHECK4-NEXT: [[CONV15:%.*]] = sext i16 [[TMP31]] to i32 3848 // CHECK4-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV14]], [[CONV15]] 3849 // CHECK4-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i16 3850 // CHECK4-NEXT: store i16 [[CONV17]], i16* [[ATOMIC_TEMP]], align 2 3851 // CHECK4-NEXT: [[TMP32:%.*]] = load i16, i16* [[ATOMIC_TEMP]], align 2 3852 // CHECK4-NEXT: [[TMP33:%.*]] = cmpxchg i16* [[OMP_ARRAYCPY_DESTELEMENTPAST11]], i16 [[TMP29]], i16 [[TMP32]] monotonic monotonic, align 2 3853 // CHECK4-NEXT: [[TMP34]] = extractvalue { i16, i1 } [[TMP33]], 0 3854 // CHECK4-NEXT: [[TMP35:%.*]] = extractvalue { i16, i1 } [[TMP33]], 1 3855 // CHECK4-NEXT: br i1 [[TMP35]], label [[ATOMIC_EXIT]], label [[ATOMIC_CONT]] 3856 // CHECK4: atomic_exit: 3857 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT18]] = getelementptr i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST11]], i32 1 3858 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT19]] = getelementptr i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST10]], i32 1 3859 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE20:%.*]] = icmp eq i16* [[OMP_ARRAYCPY_DEST_ELEMENT18]], [[TMP27]] 3860 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE20]], label [[OMP_ARRAYCPY_DONE21]], label [[OMP_ARRAYCPY_BODY9]] 3861 // CHECK4: omp.arraycpy.done21: 3862 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 3863 // CHECK4: .omp.reduction.default: 3864 // CHECK4-NEXT: [[TMP36:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 3865 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP36]]) 3866 // CHECK4-NEXT: ret void 3867 // 3868 // 3869 // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 3870 // CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { 3871 // CHECK4-NEXT: entry: 3872 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 3873 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 3874 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 3875 // CHECK4-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 3876 // CHECK4-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 3877 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [2 x i8*]* 3878 // CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 3879 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [2 x i8*]* 3880 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP5]], i64 0, i64 0 3881 // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 3882 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i16* 3883 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP3]], i64 0, i64 0 3884 // CHECK4-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 3885 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i16* 3886 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[TMP3]], i64 0, i64 1 3887 // CHECK4-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8 3888 // CHECK4-NEXT: [[TMP14:%.*]] = ptrtoint i8* [[TMP13]] to i64 3889 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr i16, i16* [[TMP11]], i64 [[TMP14]] 3890 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq i16* [[TMP11]], [[TMP15]] 3891 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3892 // CHECK4: omp.arraycpy.body: 3893 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i16* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3894 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i16* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3895 // CHECK4-NEXT: [[TMP16:%.*]] = load i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 2 3896 // CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP16]] to i32 3897 // CHECK4-NEXT: [[TMP17:%.*]] = load i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 2 3898 // CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP17]] to i32 3899 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV2]] 3900 // CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 3901 // CHECK4-NEXT: store i16 [[CONV3]], i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 2 3902 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i16, i16* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3903 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i16, i16* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3904 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i16* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP15]] 3905 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 3906 // CHECK4: omp.arraycpy.done4: 3907 // CHECK4-NEXT: ret void 3908 // 3909 // 3910 // CHECK4-LABEL: define {{[^@]+}}@main 3911 // CHECK4-SAME: () #[[ATTR7:[0-9]+]] { 3912 // CHECK4-NEXT: entry: 3913 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3914 // CHECK4-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 3915 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 3916 // CHECK4-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) 3917 // CHECK4-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 3918 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* 3919 // CHECK4-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) 3920 // CHECK4-NEXT: ret i32 0 3921 // 3922 // 3923 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 3924 // CHECK4-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 { 3925 // CHECK4-NEXT: entry: 3926 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3927 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 3928 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3929 // CHECK4-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 3930 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3931 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 3932 // CHECK4-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) 3933 // CHECK4-NEXT: ret void 3934 // 3935 // 3936 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke 3937 // CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR8]] { 3938 // CHECK4-NEXT: entry: 3939 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 3940 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 3941 // CHECK4-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 3942 // CHECK4-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* 3943 // CHECK4-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 3944 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* @g) 3945 // CHECK4-NEXT: ret void 3946 // 3947 // 3948 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 3949 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR2]] { 3950 // CHECK4-NEXT: entry: 3951 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3952 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3953 // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 3954 // CHECK4-NEXT: [[G1:%.*]] = alloca i32, align 128 3955 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, align 128 3956 // CHECK4-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 3957 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3958 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3959 // CHECK4-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 3960 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 3961 // CHECK4-NEXT: store i32 0, i32* [[G1]], align 128 3962 // CHECK4-NEXT: store i32 1, i32* [[G1]], align 128 3963 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK]], i32 0, i32 0 3964 // CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128 3965 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK]], i32 0, i32 1 3966 // CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 3967 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK]], i32 0, i32 2 3968 // CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 3969 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK]], i32 0, i32 3 3970 // CHECK4-NEXT: store i8* bitcast (void (i8*)* @g_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 16 3971 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK]], i32 0, i32 4 3972 // CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.2 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 3973 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK]], i32 0, i32 6 3974 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[G1]], align 128 3975 // CHECK4-NEXT: store volatile i32 [[TMP1]], i32* [[BLOCK_CAPTURED]], align 128 3976 // CHECK4-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK]] to void ()* 3977 // CHECK4-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* 3978 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 3979 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* 3980 // CHECK4-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 3981 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* 3982 // CHECK4-NEXT: call void [[TMP6]](i8* [[TMP4]]) 3983 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 3984 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i32* [[G1]] to i8* 3985 // CHECK4-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 8 3986 // CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3987 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 3988 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 3989 // CHECK4-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 1, i64 8, i8* [[TMP11]], void (i8*, i8*)* @.omp.reduction.reduction_func.3, [8 x i32]* @.gomp_critical_user_.reduction.var) 3990 // CHECK4-NEXT: switch i32 [[TMP12]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 3991 // CHECK4-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 3992 // CHECK4-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 3993 // CHECK4-NEXT: ] 3994 // CHECK4: .omp.reduction.case1: 3995 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 128 3996 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[G1]], align 128 3997 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 3998 // CHECK4-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 128 3999 // CHECK4-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], [8 x i32]* @.gomp_critical_user_.reduction.var) 4000 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 4001 // CHECK4: .omp.reduction.case2: 4002 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[G1]], align 128 4003 // CHECK4-NEXT: [[TMP16:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP15]] monotonic, align 4 4004 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 4005 // CHECK4: .omp.reduction.default: 4006 // CHECK4-NEXT: ret void 4007 // 4008 // 4009 // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke 4010 // CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR8]] { 4011 // CHECK4-NEXT: entry: 4012 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 4013 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>*, align 8 4014 // CHECK4-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 4015 // CHECK4-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* 4016 // CHECK4-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>** [[BLOCK_ADDR]], align 8 4017 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK]], i32 0, i32 6 4018 // CHECK4-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128 4019 // CHECK4-NEXT: ret void 4020 // 4021 // 4022 // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.3 4023 // CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { 4024 // CHECK4-NEXT: entry: 4025 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 4026 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 4027 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 4028 // CHECK4-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 4029 // CHECK4-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 4030 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 4031 // CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 4032 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 4033 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 4034 // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 4035 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 4036 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 4037 // CHECK4-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 4038 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 4039 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 128 4040 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 128 4041 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 4042 // CHECK4-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 128 4043 // CHECK4-NEXT: ret void 4044 // 4045 // 4046 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 4047 // CHECK4-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR8]] align 2 { 4048 // CHECK4-NEXT: entry: 4049 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 4050 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 4051 // CHECK4-NEXT: [[A2:%.*]] = alloca i32*, align 8 4052 // CHECK4-NEXT: [[B4:%.*]] = alloca i32, align 4 4053 // CHECK4-NEXT: [[C5:%.*]] = alloca i32*, align 8 4054 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 4055 // CHECK4-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 4056 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 4057 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 4058 // CHECK4-NEXT: store i32 0, i32* [[A]], align 8 4059 // CHECK4-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 4060 // CHECK4-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 4061 // CHECK4-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 4062 // CHECK4-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 4063 // CHECK4-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 4064 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 4065 // CHECK4-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 4066 // CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 4067 // CHECK4-NEXT: store i32* [[A3]], i32** [[A2]], align 8 4068 // CHECK4-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 4069 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 4070 // CHECK4-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 4071 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 4072 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 4073 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i32* [[TMP2]], i32* [[B4]], i32* [[TMP3]]) 4074 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B4]], align 4 4075 // CHECK4-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 4076 // CHECK4-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8 4077 // CHECK4-NEXT: [[BF_LOAD8:%.*]] = load i8, i8* [[B7]], align 4 4078 // CHECK4-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP5]], 15 4079 // CHECK4-NEXT: [[BF_CLEAR9:%.*]] = and i8 [[BF_LOAD8]], -16 4080 // CHECK4-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR9]], [[BF_VALUE]] 4081 // CHECK4-NEXT: store i8 [[BF_SET]], i8* [[B7]], align 4 4082 // CHECK4-NEXT: ret void 4083 // 4084 // 4085 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 4086 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { 4087 // CHECK4-NEXT: entry: 4088 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4089 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4090 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 4091 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 4092 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 4093 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 4094 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4095 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 4096 // CHECK4-NEXT: [[A2:%.*]] = alloca i32, align 4 4097 // CHECK4-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 4098 // CHECK4-NEXT: [[B4:%.*]] = alloca i32, align 4 4099 // CHECK4-NEXT: [[C5:%.*]] = alloca i32, align 4 4100 // CHECK4-NEXT: [[_TMP6:%.*]] = alloca i32*, align 8 4101 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, align 8 4102 // CHECK4-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [3 x i8*], align 8 4103 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4104 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4105 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 4106 // CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 4107 // CHECK4-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 4108 // CHECK4-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 4109 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 4110 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 4111 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[B_ADDR]], align 8 4112 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C_ADDR]], align 8 4113 // CHECK4-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8 4114 // CHECK4-NEXT: store i32* [[TMP3]], i32** [[_TMP1]], align 8 4115 // CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 4116 // CHECK4-NEXT: store i32 0, i32* [[A2]], align 4 4117 // CHECK4-NEXT: store i32* [[A2]], i32** [[_TMP3]], align 8 4118 // CHECK4-NEXT: store i32 0, i32* [[B4]], align 4 4119 // CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[_TMP1]], align 8 4120 // CHECK4-NEXT: store i32 0, i32* [[C5]], align 4 4121 // CHECK4-NEXT: store i32* [[C5]], i32** [[_TMP6]], align 8 4122 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 0 4123 // CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 4124 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 1 4125 // CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 4126 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 2 4127 // CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 4128 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 3 4129 // CHECK4-NEXT: store i8* bitcast (void (i8*)* @g_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 4130 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4 4131 // CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.7 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 4132 // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 4133 // CHECK4-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8 4134 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 4135 // CHECK4-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP3]], align 8 4136 // CHECK4-NEXT: store i32* [[TMP6]], i32** [[BLOCK_CAPTURED]], align 8 4137 // CHECK4-NEXT: [[BLOCK_CAPTURED7:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 4138 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[B4]], align 4 4139 // CHECK4-NEXT: store i32 [[TMP7]], i32* [[BLOCK_CAPTURED7]], align 8 4140 // CHECK4-NEXT: [[BLOCK_CAPTURED8:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 4141 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP6]], align 8 4142 // CHECK4-NEXT: store i32* [[TMP8]], i32** [[BLOCK_CAPTURED8]], align 8 4143 // CHECK4-NEXT: [[TMP9:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()* 4144 // CHECK4-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP9]] to %struct.__block_literal_generic* 4145 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 4146 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* 4147 // CHECK4-NEXT: [[TMP12:%.*]] = load i8*, i8** [[TMP10]], align 8 4148 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8* [[TMP12]] to void (i8*)* 4149 // CHECK4-NEXT: call void [[TMP13]](i8* [[TMP11]]) 4150 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 4151 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i32* [[A2]] to i8* 4152 // CHECK4-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 4153 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1 4154 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i32* [[B4]] to i8* 4155 // CHECK4-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8 4156 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 2 4157 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast i32* [[C5]] to i8* 4158 // CHECK4-NEXT: store i8* [[TMP19]], i8** [[TMP18]], align 8 4159 // CHECK4-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4160 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 4161 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 4162 // CHECK4-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]], i32 3, i64 24, i8* [[TMP22]], void (i8*, i8*)* @.omp.reduction.reduction_func.8, [8 x i32]* @.gomp_critical_user_.reduction.var) 4163 // CHECK4-NEXT: switch i32 [[TMP23]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 4164 // CHECK4-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 4165 // CHECK4-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 4166 // CHECK4-NEXT: ] 4167 // CHECK4: .omp.reduction.case1: 4168 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP4]], align 4 4169 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[A2]], align 4 4170 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] 4171 // CHECK4-NEXT: store i32 [[ADD]], i32* [[TMP4]], align 4 4172 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP2]], align 4 4173 // CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[B4]], align 4 4174 // CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] 4175 // CHECK4-NEXT: store i32 [[ADD9]], i32* [[TMP2]], align 4 4176 // CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP5]], align 4 4177 // CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[C5]], align 4 4178 // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 4179 // CHECK4-NEXT: store i32 [[ADD10]], i32* [[TMP5]], align 4 4180 // CHECK4-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]], [8 x i32]* @.gomp_critical_user_.reduction.var) 4181 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 4182 // CHECK4: .omp.reduction.case2: 4183 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[A2]], align 4 4184 // CHECK4-NEXT: [[TMP31:%.*]] = atomicrmw add i32* [[TMP4]], i32 [[TMP30]] monotonic, align 4 4185 // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[B4]], align 4 4186 // CHECK4-NEXT: [[TMP33:%.*]] = atomicrmw add i32* [[TMP2]], i32 [[TMP32]] monotonic, align 4 4187 // CHECK4-NEXT: [[TMP34:%.*]] = load i32, i32* [[C5]], align 4 4188 // CHECK4-NEXT: [[TMP35:%.*]] = atomicrmw add i32* [[TMP5]], i32 [[TMP34]] monotonic, align 4 4189 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 4190 // CHECK4: .omp.reduction.default: 4191 // CHECK4-NEXT: ret void 4192 // 4193 // 4194 // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke_2 4195 // CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR8]] { 4196 // CHECK4-NEXT: entry: 4197 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 4198 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 4199 // CHECK4-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 4200 // CHECK4-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* 4201 // CHECK4-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 4202 // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 4203 // CHECK4-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 4204 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 4205 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 4206 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4207 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 4208 // CHECK4-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 4209 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 4210 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 4211 // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 4212 // CHECK4-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 8 4213 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 4214 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 4215 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 4216 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 4217 // CHECK4-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 4218 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 4219 // CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 8 4220 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 4221 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 4222 // CHECK4-NEXT: [[TMP6:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR5]], align 8 4223 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i32*, i32*, i32*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.SS* [[THIS]], i32* [[TMP5]], i32* [[BLOCK_CAPTURE_ADDR4]], i32* [[TMP6]]) 4224 // CHECK4-NEXT: ret void 4225 // 4226 // 4227 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 4228 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { 4229 // CHECK4-NEXT: entry: 4230 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4231 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4232 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 4233 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 4234 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 4235 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 4236 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4237 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 4238 // CHECK4-NEXT: [[A2:%.*]] = alloca i32, align 4 4239 // CHECK4-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 4240 // CHECK4-NEXT: [[B4:%.*]] = alloca i32, align 4 4241 // CHECK4-NEXT: [[C5:%.*]] = alloca i32, align 4 4242 // CHECK4-NEXT: [[_TMP6:%.*]] = alloca i32*, align 8 4243 // CHECK4-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [3 x i8*], align 8 4244 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4245 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4246 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 4247 // CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 4248 // CHECK4-NEXT: store i32* [[B]], i32** [[B_ADDR]], align 8 4249 // CHECK4-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 4250 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 4251 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 4252 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[B_ADDR]], align 8 4253 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C_ADDR]], align 8 4254 // CHECK4-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8 4255 // CHECK4-NEXT: store i32* [[TMP3]], i32** [[_TMP1]], align 8 4256 // CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 4257 // CHECK4-NEXT: store i32 0, i32* [[A2]], align 4 4258 // CHECK4-NEXT: store i32* [[A2]], i32** [[_TMP3]], align 8 4259 // CHECK4-NEXT: store i32 0, i32* [[B4]], align 4 4260 // CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[_TMP1]], align 8 4261 // CHECK4-NEXT: store i32 0, i32* [[C5]], align 4 4262 // CHECK4-NEXT: store i32* [[C5]], i32** [[_TMP6]], align 8 4263 // CHECK4-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP3]], align 8 4264 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 4265 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 4266 // CHECK4-NEXT: store i32 [[INC]], i32* [[TMP6]], align 4 4267 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[B4]], align 4 4268 // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 4269 // CHECK4-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 4270 // CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[_TMP6]], align 8 4271 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 4272 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 4273 // CHECK4-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 4274 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 4275 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i32* [[A2]] to i8* 4276 // CHECK4-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 8 4277 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1 4278 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast i32* [[B4]] to i8* 4279 // CHECK4-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 4280 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 2 4281 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i32* [[C5]] to i8* 4282 // CHECK4-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 4283 // CHECK4-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4284 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 4285 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 4286 // CHECK4-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 3, i64 24, i8* [[TMP19]], void (i8*, i8*)* @.omp.reduction.reduction_func.6, [8 x i32]* @.gomp_critical_user_.reduction.var) 4287 // CHECK4-NEXT: switch i32 [[TMP20]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 4288 // CHECK4-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 4289 // CHECK4-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 4290 // CHECK4-NEXT: ] 4291 // CHECK4: .omp.reduction.case1: 4292 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP4]], align 4 4293 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[A2]], align 4 4294 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] 4295 // CHECK4-NEXT: store i32 [[ADD]], i32* [[TMP4]], align 4 4296 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP2]], align 4 4297 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[B4]], align 4 4298 // CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] 4299 // CHECK4-NEXT: store i32 [[ADD7]], i32* [[TMP2]], align 4 4300 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP5]], align 4 4301 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[C5]], align 4 4302 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] 4303 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[TMP5]], align 4 4304 // CHECK4-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.reduction.var) 4305 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 4306 // CHECK4: .omp.reduction.case2: 4307 // CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[A2]], align 4 4308 // CHECK4-NEXT: [[TMP28:%.*]] = atomicrmw add i32* [[TMP4]], i32 [[TMP27]] monotonic, align 4 4309 // CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[B4]], align 4 4310 // CHECK4-NEXT: [[TMP30:%.*]] = atomicrmw add i32* [[TMP2]], i32 [[TMP29]] monotonic, align 4 4311 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[C5]], align 4 4312 // CHECK4-NEXT: [[TMP32:%.*]] = atomicrmw add i32* [[TMP5]], i32 [[TMP31]] monotonic, align 4 4313 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 4314 // CHECK4: .omp.reduction.default: 4315 // CHECK4-NEXT: ret void 4316 // 4317 // 4318 // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 4319 // CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { 4320 // CHECK4-NEXT: entry: 4321 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 4322 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 4323 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 4324 // CHECK4-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 4325 // CHECK4-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 4326 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [3 x i8*]* 4327 // CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 4328 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [3 x i8*]* 4329 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP5]], i64 0, i64 0 4330 // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 4331 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 4332 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP3]], i64 0, i64 0 4333 // CHECK4-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 4334 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 4335 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP5]], i64 0, i64 1 4336 // CHECK4-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8 4337 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to i32* 4338 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP3]], i64 0, i64 1 4339 // CHECK4-NEXT: [[TMP16:%.*]] = load i8*, i8** [[TMP15]], align 8 4340 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8* [[TMP16]] to i32* 4341 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP5]], i64 0, i64 2 4342 // CHECK4-NEXT: [[TMP19:%.*]] = load i8*, i8** [[TMP18]], align 8 4343 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8* [[TMP19]] to i32* 4344 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP3]], i64 0, i64 2 4345 // CHECK4-NEXT: [[TMP22:%.*]] = load i8*, i8** [[TMP21]], align 8 4346 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8* [[TMP22]] to i32* 4347 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP11]], align 4 4348 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP8]], align 4 4349 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] 4350 // CHECK4-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 4351 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP17]], align 4 4352 // CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP14]], align 4 4353 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] 4354 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[TMP17]], align 4 4355 // CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP23]], align 4 4356 // CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP20]], align 4 4357 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 4358 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[TMP23]], align 4 4359 // CHECK4-NEXT: ret void 4360 // 4361 // 4362 // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.8 4363 // CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { 4364 // CHECK4-NEXT: entry: 4365 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 4366 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 4367 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 4368 // CHECK4-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 4369 // CHECK4-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 4370 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [3 x i8*]* 4371 // CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 4372 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [3 x i8*]* 4373 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP5]], i64 0, i64 0 4374 // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 4375 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 4376 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP3]], i64 0, i64 0 4377 // CHECK4-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 4378 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 4379 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP5]], i64 0, i64 1 4380 // CHECK4-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8 4381 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to i32* 4382 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP3]], i64 0, i64 1 4383 // CHECK4-NEXT: [[TMP16:%.*]] = load i8*, i8** [[TMP15]], align 8 4384 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8* [[TMP16]] to i32* 4385 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP5]], i64 0, i64 2 4386 // CHECK4-NEXT: [[TMP19:%.*]] = load i8*, i8** [[TMP18]], align 8 4387 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8* [[TMP19]] to i32* 4388 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP3]], i64 0, i64 2 4389 // CHECK4-NEXT: [[TMP22:%.*]] = load i8*, i8** [[TMP21]], align 8 4390 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8* [[TMP22]] to i32* 4391 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP11]], align 4 4392 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP8]], align 4 4393 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] 4394 // CHECK4-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 4395 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP17]], align 4 4396 // CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP14]], align 4 4397 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] 4398 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[TMP17]], align 4 4399 // CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP23]], align 4 4400 // CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP20]], align 4 4401 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 4402 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[TMP23]], align 4 4403 // CHECK4-NEXT: ret void 4404 // 4405 // 4406 // CHECK5-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs 4407 // CHECK5-SAME: (i16* [[X:%.*]]) #[[ATTR0:[0-9]+]] { 4408 // CHECK5-NEXT: entry: 4409 // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 4410 // CHECK5-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 4411 // CHECK5-NEXT: ret void 4412 // 4413 // 4414 // CHECK5-LABEL: define {{[^@]+}}@main 4415 // CHECK5-SAME: () #[[ATTR1:[0-9]+]] { 4416 // CHECK5-NEXT: entry: 4417 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4418 // CHECK5-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 4419 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 4420 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca float, align 4 4421 // CHECK5-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 4422 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 4423 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 4424 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 4425 // CHECK5-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 4426 // CHECK5-NEXT: [[CF:%.*]] = alloca { float, float }, align 4 4427 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 4428 // CHECK5-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) 4429 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 4430 // CHECK5-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 4431 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 4432 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) 4433 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 4434 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 4435 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 4436 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 4437 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 4438 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) 4439 // CHECK5-NEXT: [[TMP1:%.*]] = load float, float* [[T_VAR]], align 4 4440 // CHECK5-NEXT: [[CONV:%.*]] = fptosi float [[TMP1]] to i32 4441 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 4442 // CHECK5-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4 4443 // CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 4444 // CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 4445 // CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* 4446 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) 4447 // CHECK5-NEXT: [[CALL:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) 4448 // CHECK5-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL]], 0.000000e+00 4449 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] 4450 // CHECK5: if.then: 4451 // CHECK5-NEXT: br label [[WHILE_COND:%.*]] 4452 // CHECK5: while.cond: 4453 // CHECK5-NEXT: br label [[WHILE_BODY:%.*]] 4454 // CHECK5: while.body: 4455 // CHECK5-NEXT: [[TMP4:%.*]] = load float, float* [[T_VAR]], align 4 4456 // CHECK5-NEXT: [[CONV2:%.*]] = fptosi float [[TMP4]] to i32 4457 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 4458 // CHECK5-NEXT: store i32 [[CONV2]], i32* [[ARRAYIDX3]], align 4 4459 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 4460 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* 4461 // CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[VAR]] to i8* 4462 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 4, i1 false) 4463 // CHECK5-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP2:![0-9]+]] 4464 // CHECK5: if.end: 4465 // CHECK5-NEXT: [[CALL5:%.*]] = call i32 @_Z5tmainIiET_v() 4466 // CHECK5-NEXT: store i32 [[CALL5]], i32* [[RETVAL]], align 4 4467 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4:[0-9]+]] 4468 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 4469 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 4470 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 4471 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4472 // CHECK5: arraydestroy.body: 4473 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[IF_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4474 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4475 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 4476 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 4477 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 4478 // CHECK5: arraydestroy.done6: 4479 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 4480 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 4481 // CHECK5-NEXT: ret i32 [[TMP8]] 4482 // 4483 // 4484 // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 4485 // CHECK5-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { 4486 // CHECK5-NEXT: entry: 4487 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 4488 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 4489 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 4490 // CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 4491 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 4492 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 4493 // CHECK5-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) 4494 // CHECK5-NEXT: ret void 4495 // 4496 // 4497 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4498 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4499 // CHECK5-NEXT: entry: 4500 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4501 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4502 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4503 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 4504 // CHECK5-NEXT: ret void 4505 // 4506 // 4507 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4508 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4509 // CHECK5-NEXT: entry: 4510 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4511 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4512 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4513 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4514 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4515 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4516 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 4517 // CHECK5-NEXT: ret void 4518 // 4519 // 4520 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEcvfEv 4521 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR0]] align 2 { 4522 // CHECK5-NEXT: entry: 4523 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4524 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4525 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4526 // CHECK5-NEXT: ret float 0.000000e+00 4527 // 4528 // 4529 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 4530 // CHECK5-SAME: () #[[ATTR0]] { 4531 // CHECK5-NEXT: entry: 4532 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4533 // CHECK5-NEXT: [[T:%.*]] = alloca i32, align 4 4534 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 4535 // CHECK5-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 4536 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 4537 // CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 4538 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 4539 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 4540 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 4541 // CHECK5-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 128 4542 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 4543 // CHECK5-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) 4544 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 128 4545 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 4546 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 4547 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 4548 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 4549 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 4550 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 4551 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 4552 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) 4553 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 4554 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 4555 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 4556 // CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 4557 // CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* 4558 // CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* 4559 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) 4560 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 4561 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4]] 4562 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 4563 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4564 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 4565 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4566 // CHECK5: arraydestroy.body: 4567 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4568 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4569 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 4570 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 4571 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 4572 // CHECK5: arraydestroy.done2: 4573 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 4574 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 4575 // CHECK5-NEXT: ret i32 [[TMP5]] 4576 // 4577 // 4578 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4579 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4580 // CHECK5-NEXT: entry: 4581 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4582 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4583 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4584 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 4585 // CHECK5-NEXT: ret void 4586 // 4587 // 4588 // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 4589 // CHECK5-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4590 // CHECK5-NEXT: entry: 4591 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 4592 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 4593 // CHECK5-NEXT: [[A2:%.*]] = alloca i32*, align 8 4594 // CHECK5-NEXT: [[B4:%.*]] = alloca i32, align 4 4595 // CHECK5-NEXT: [[C5:%.*]] = alloca i32*, align 8 4596 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4597 // CHECK5-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 4598 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 4599 // CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 4600 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 4601 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 4602 // CHECK5-NEXT: store i32 0, i32* [[A]], align 8 4603 // CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 4604 // CHECK5-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 4605 // CHECK5-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 4606 // CHECK5-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 4607 // CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 4608 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 4609 // CHECK5-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 4610 // CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 4611 // CHECK5-NEXT: store i32* [[A3]], i32** [[A2]], align 8 4612 // CHECK5-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 4613 // CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 4614 // CHECK5-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 4615 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 4616 // CHECK5-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 4617 // CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 4618 // CHECK5-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 4619 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 4620 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 4621 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 4622 // CHECK5-NEXT: store i32 [[INC]], i32* [[TMP4]], align 4 4623 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[B4]], align 4 4624 // CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP6]], -1 4625 // CHECK5-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 4626 // CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP7]], align 8 4627 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 4628 // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 1 4629 // CHECK5-NEXT: store i32 [[DIV]], i32* [[TMP7]], align 4 4630 // CHECK5-NEXT: ret void 4631 // 4632 // 4633 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4634 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4635 // CHECK5-NEXT: entry: 4636 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4637 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4638 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4639 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4640 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 4641 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4642 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 4643 // CHECK5-NEXT: ret void 4644 // 4645 // 4646 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4647 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4648 // CHECK5-NEXT: entry: 4649 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4650 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4651 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4652 // CHECK5-NEXT: ret void 4653 // 4654 // 4655 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4656 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4657 // CHECK5-NEXT: entry: 4658 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4659 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4660 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4661 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4662 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4663 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4664 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4665 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 4666 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4667 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4668 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 4669 // CHECK5-NEXT: ret void 4670 // 4671 // 4672 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 4673 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4674 // CHECK5-NEXT: entry: 4675 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 4676 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 4677 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 4678 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 4679 // CHECK5-NEXT: ret void 4680 // 4681 // 4682 // CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev 4683 // CHECK5-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4684 // CHECK5-NEXT: entry: 4685 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 4686 // CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 4687 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 4688 // CHECK5-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) 4689 // CHECK5-NEXT: ret void 4690 // 4691 // 4692 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 4693 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4694 // CHECK5-NEXT: entry: 4695 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 4696 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4697 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 4698 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4699 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 4700 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4701 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 4702 // CHECK5-NEXT: ret void 4703 // 4704 // 4705 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 4706 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4707 // CHECK5-NEXT: entry: 4708 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 4709 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 4710 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 4711 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 4712 // CHECK5-NEXT: ret void 4713 // 4714 // 4715 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 4716 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4717 // CHECK5-NEXT: entry: 4718 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 4719 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 4720 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 4721 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4722 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 4723 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 4724 // CHECK5-NEXT: ret void 4725 // 4726 // 4727 // CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev 4728 // CHECK5-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4729 // CHECK5-NEXT: entry: 4730 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 4731 // CHECK5-NEXT: [[A2:%.*]] = alloca i32*, align 8 4732 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4733 // CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 4734 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 4735 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 4736 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 4737 // CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 4738 // CHECK5-NEXT: store i32* [[A3]], i32** [[A2]], align 8 4739 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 4740 // CHECK5-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 4741 // CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 4742 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 4743 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 4744 // CHECK5-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 4745 // CHECK5-NEXT: ret void 4746 // 4747 // 4748 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 4749 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4750 // CHECK5-NEXT: entry: 4751 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 4752 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4753 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 4754 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4755 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 4756 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4757 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4758 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 4759 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 4760 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 4761 // CHECK5-NEXT: ret void 4762 // 4763 // 4764 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 4765 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4766 // CHECK5-NEXT: entry: 4767 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 4768 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 4769 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 4770 // CHECK5-NEXT: ret void 4771 // 4772 // 4773 // CHECK6-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs 4774 // CHECK6-SAME: (i16* [[X:%.*]]) #[[ATTR0:[0-9]+]] { 4775 // CHECK6-NEXT: entry: 4776 // CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 4777 // CHECK6-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 4778 // CHECK6-NEXT: ret void 4779 // 4780 // 4781 // CHECK6-LABEL: define {{[^@]+}}@main 4782 // CHECK6-SAME: () #[[ATTR1:[0-9]+]] { 4783 // CHECK6-NEXT: entry: 4784 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4785 // CHECK6-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 4786 // CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 4787 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca float, align 4 4788 // CHECK6-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 4789 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 4790 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 4791 // CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 4792 // CHECK6-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 4793 // CHECK6-NEXT: [[CF:%.*]] = alloca { float, float }, align 4 4794 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 4795 // CHECK6-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) 4796 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 4797 // CHECK6-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 4798 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 4799 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) 4800 // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 4801 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 4802 // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 4803 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 4804 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 4805 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) 4806 // CHECK6-NEXT: [[TMP1:%.*]] = load float, float* [[T_VAR]], align 4 4807 // CHECK6-NEXT: [[CONV:%.*]] = fptosi float [[TMP1]] to i32 4808 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 4809 // CHECK6-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4 4810 // CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 4811 // CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 4812 // CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* 4813 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) 4814 // CHECK6-NEXT: [[CALL:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) 4815 // CHECK6-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL]], 0.000000e+00 4816 // CHECK6-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] 4817 // CHECK6: if.then: 4818 // CHECK6-NEXT: br label [[WHILE_COND:%.*]] 4819 // CHECK6: while.cond: 4820 // CHECK6-NEXT: br label [[WHILE_BODY:%.*]] 4821 // CHECK6: while.body: 4822 // CHECK6-NEXT: [[TMP4:%.*]] = load float, float* [[T_VAR]], align 4 4823 // CHECK6-NEXT: [[CONV2:%.*]] = fptosi float [[TMP4]] to i32 4824 // CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 4825 // CHECK6-NEXT: store i32 [[CONV2]], i32* [[ARRAYIDX3]], align 4 4826 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 4827 // CHECK6-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* 4828 // CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[VAR]] to i8* 4829 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 4, i1 false) 4830 // CHECK6-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP2:![0-9]+]] 4831 // CHECK6: if.end: 4832 // CHECK6-NEXT: [[CALL5:%.*]] = call i32 @_Z5tmainIiET_v() 4833 // CHECK6-NEXT: store i32 [[CALL5]], i32* [[RETVAL]], align 4 4834 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4:[0-9]+]] 4835 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 4836 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 4837 // CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 4838 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4839 // CHECK6: arraydestroy.body: 4840 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[IF_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4841 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4842 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 4843 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 4844 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 4845 // CHECK6: arraydestroy.done6: 4846 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 4847 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 4848 // CHECK6-NEXT: ret i32 [[TMP8]] 4849 // 4850 // 4851 // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 4852 // CHECK6-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { 4853 // CHECK6-NEXT: entry: 4854 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 4855 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 4856 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 4857 // CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 4858 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 4859 // CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 4860 // CHECK6-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) 4861 // CHECK6-NEXT: ret void 4862 // 4863 // 4864 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4865 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4866 // CHECK6-NEXT: entry: 4867 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4868 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4869 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4870 // CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 4871 // CHECK6-NEXT: ret void 4872 // 4873 // 4874 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4875 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4876 // CHECK6-NEXT: entry: 4877 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4878 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4879 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4880 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4881 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4882 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4883 // CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 4884 // CHECK6-NEXT: ret void 4885 // 4886 // 4887 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEcvfEv 4888 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR0]] align 2 { 4889 // CHECK6-NEXT: entry: 4890 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4891 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4892 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4893 // CHECK6-NEXT: ret float 0.000000e+00 4894 // 4895 // 4896 // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 4897 // CHECK6-SAME: () #[[ATTR0]] { 4898 // CHECK6-NEXT: entry: 4899 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4900 // CHECK6-NEXT: [[T:%.*]] = alloca i32, align 4 4901 // CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 4902 // CHECK6-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 4903 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 4904 // CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 4905 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 4906 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 4907 // CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 4908 // CHECK6-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 128 4909 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 4910 // CHECK6-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) 4911 // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 128 4912 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 4913 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 4914 // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 4915 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 4916 // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 4917 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 4918 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 4919 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) 4920 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 4921 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 4922 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 4923 // CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 4924 // CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* 4925 // CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* 4926 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) 4927 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 4928 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4]] 4929 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 4930 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4931 // CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 4932 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4933 // CHECK6: arraydestroy.body: 4934 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4935 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4936 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 4937 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 4938 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 4939 // CHECK6: arraydestroy.done2: 4940 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 4941 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 4942 // CHECK6-NEXT: ret i32 [[TMP5]] 4943 // 4944 // 4945 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4946 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4947 // CHECK6-NEXT: entry: 4948 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4949 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4950 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4951 // CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 4952 // CHECK6-NEXT: ret void 4953 // 4954 // 4955 // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 4956 // CHECK6-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 4957 // CHECK6-NEXT: entry: 4958 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 4959 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 4960 // CHECK6-NEXT: [[A2:%.*]] = alloca i32*, align 8 4961 // CHECK6-NEXT: [[B4:%.*]] = alloca i32, align 4 4962 // CHECK6-NEXT: [[C5:%.*]] = alloca i32*, align 8 4963 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4964 // CHECK6-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 4965 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 4966 // CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 4967 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 4968 // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 4969 // CHECK6-NEXT: store i32 0, i32* [[A]], align 8 4970 // CHECK6-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 4971 // CHECK6-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 4972 // CHECK6-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 4973 // CHECK6-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 4974 // CHECK6-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 4975 // CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 4976 // CHECK6-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 4977 // CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 4978 // CHECK6-NEXT: store i32* [[A3]], i32** [[A2]], align 8 4979 // CHECK6-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 4980 // CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 4981 // CHECK6-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 4982 // CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 4983 // CHECK6-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 4984 // CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 4985 // CHECK6-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 4986 // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 4987 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 4988 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 4989 // CHECK6-NEXT: store i32 [[INC]], i32* [[TMP4]], align 4 4990 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[B4]], align 4 4991 // CHECK6-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP6]], -1 4992 // CHECK6-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 4993 // CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP7]], align 8 4994 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 4995 // CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 1 4996 // CHECK6-NEXT: store i32 [[DIV]], i32* [[TMP7]], align 4 4997 // CHECK6-NEXT: ret void 4998 // 4999 // 5000 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 5001 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 5002 // CHECK6-NEXT: entry: 5003 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5004 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5005 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5006 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5007 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 5008 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 5009 // CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 5010 // CHECK6-NEXT: ret void 5011 // 5012 // 5013 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 5014 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 5015 // CHECK6-NEXT: entry: 5016 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5017 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5018 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5019 // CHECK6-NEXT: ret void 5020 // 5021 // 5022 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 5023 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 5024 // CHECK6-NEXT: entry: 5025 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5026 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5027 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5028 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5029 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5030 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5031 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5032 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 5033 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 5034 // CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 5035 // CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 5036 // CHECK6-NEXT: ret void 5037 // 5038 // 5039 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 5040 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 5041 // CHECK6-NEXT: entry: 5042 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 5043 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 5044 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 5045 // CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 5046 // CHECK6-NEXT: ret void 5047 // 5048 // 5049 // CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev 5050 // CHECK6-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 5051 // CHECK6-NEXT: entry: 5052 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 5053 // CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 5054 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 5055 // CHECK6-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) 5056 // CHECK6-NEXT: ret void 5057 // 5058 // 5059 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 5060 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 5061 // CHECK6-NEXT: entry: 5062 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 5063 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5064 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 5065 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5066 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 5067 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 5068 // CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 5069 // CHECK6-NEXT: ret void 5070 // 5071 // 5072 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 5073 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 5074 // CHECK6-NEXT: entry: 5075 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 5076 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 5077 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 5078 // CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 5079 // CHECK6-NEXT: ret void 5080 // 5081 // 5082 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 5083 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 5084 // CHECK6-NEXT: entry: 5085 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 5086 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 5087 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 5088 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 5089 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 5090 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 5091 // CHECK6-NEXT: ret void 5092 // 5093 // 5094 // CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev 5095 // CHECK6-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 5096 // CHECK6-NEXT: entry: 5097 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 5098 // CHECK6-NEXT: [[A2:%.*]] = alloca i32*, align 8 5099 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 5100 // CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 5101 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 5102 // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 5103 // CHECK6-NEXT: store i32 0, i32* [[A]], align 4 5104 // CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 5105 // CHECK6-NEXT: store i32* [[A3]], i32** [[A2]], align 8 5106 // CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 5107 // CHECK6-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 5108 // CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 5109 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 5110 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 5111 // CHECK6-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 5112 // CHECK6-NEXT: ret void 5113 // 5114 // 5115 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 5116 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 5117 // CHECK6-NEXT: entry: 5118 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 5119 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5120 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 5121 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5122 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 5123 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 5124 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 5125 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 5126 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 5127 // CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 5128 // CHECK6-NEXT: ret void 5129 // 5130 // 5131 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 5132 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 5133 // CHECK6-NEXT: entry: 5134 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 5135 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 5136 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 5137 // CHECK6-NEXT: ret void 5138 // 5139 // 5140 // CHECK7-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs 5141 // CHECK7-SAME: (i16* [[X:%.*]]) #[[ATTR0:[0-9]+]] { 5142 // CHECK7-NEXT: entry: 5143 // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 5144 // CHECK7-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 5145 // CHECK7-NEXT: ret void 5146 // 5147 // 5148 // CHECK7-LABEL: define {{[^@]+}}@main 5149 // CHECK7-SAME: () #[[ATTR1:[0-9]+]] { 5150 // CHECK7-NEXT: entry: 5151 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 5152 // CHECK7-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 5153 // CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 5154 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 5155 // CHECK7-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) 5156 // CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 5157 // CHECK7-NEXT: ret i32 0 5158 // 5159 // 5160 // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 5161 // CHECK7-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { 5162 // CHECK7-NEXT: entry: 5163 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 5164 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 5165 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 5166 // CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 5167 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 5168 // CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 5169 // CHECK7-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) 5170 // CHECK7-NEXT: ret void 5171 // 5172 // 5173 // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 5174 // CHECK7-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 { 5175 // CHECK7-NEXT: entry: 5176 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 5177 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 5178 // CHECK7-NEXT: [[A2:%.*]] = alloca i32*, align 8 5179 // CHECK7-NEXT: [[B4:%.*]] = alloca i32, align 4 5180 // CHECK7-NEXT: [[C5:%.*]] = alloca i32*, align 8 5181 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 5182 // CHECK7-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 5183 // CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 5184 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 5185 // CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 5186 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 5187 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 5188 // CHECK7-NEXT: store i32 0, i32* [[A]], align 8 5189 // CHECK7-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 5190 // CHECK7-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 5191 // CHECK7-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 5192 // CHECK7-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 5193 // CHECK7-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 5194 // CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 5195 // CHECK7-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 5196 // CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 5197 // CHECK7-NEXT: store i32* [[A3]], i32** [[A2]], align 8 5198 // CHECK7-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 5199 // CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 5200 // CHECK7-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 5201 // CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 5202 // CHECK7-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 5203 // CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 5204 // CHECK7-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 5205 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 5206 // CHECK7-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 8 5207 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 5208 // CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 5209 // CHECK7-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 8 5210 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 5211 // CHECK7-NEXT: store i32* [[B4]], i32** [[TMP7]], align 8 5212 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 5213 // CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[_TMP7]], align 8 5214 // CHECK7-NEXT: store i32* [[TMP9]], i32** [[TMP8]], align 8 5215 // CHECK7-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) 5216 // CHECK7-NEXT: ret void 5217 // 5218 // 5219 // CHECK7-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv 5220 // CHECK7-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR0]] align 2 { 5221 // CHECK7-NEXT: entry: 5222 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 5223 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 5224 // CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 5225 // CHECK7-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 5226 // CHECK7-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 5227 // CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 5228 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 5229 // CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 5230 // CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 5231 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 5232 // CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 5233 // CHECK7-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 5234 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 5235 // CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 5236 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 5237 // CHECK7-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 5238 // CHECK7-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 5239 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 5240 // CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 5241 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 5242 // CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 5243 // CHECK7-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 5244 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 5245 // CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 5246 // CHECK7-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 8 5247 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 5248 // CHECK7-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 8 5249 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 5250 // CHECK7-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 5251 // CHECK7-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 8 5252 // CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 8 5253 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 5254 // CHECK7-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP18]], 1 5255 // CHECK7-NEXT: store i32 [[INC3]], i32* [[TMP17]], align 4 5256 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP14]], align 4 5257 // CHECK7-NEXT: [[DEC4:%.*]] = add nsw i32 [[TMP19]], -1 5258 // CHECK7-NEXT: store i32 [[DEC4]], i32* [[TMP14]], align 4 5259 // CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[_TMP2]], align 8 5260 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 5261 // CHECK7-NEXT: [[DIV5:%.*]] = sdiv i32 [[TMP21]], 1 5262 // CHECK7-NEXT: store i32 [[DIV5]], i32* [[TMP20]], align 4 5263 // CHECK7-NEXT: ret void 5264 // 5265 // 5266 // CHECK8-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs 5267 // CHECK8-SAME: (i16* [[X:%.*]]) #[[ATTR1:[0-9]+]] { 5268 // CHECK8-NEXT: entry: 5269 // CHECK8-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 5270 // CHECK8-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 5271 // CHECK8-NEXT: ret void 5272 // 5273 // 5274 // CHECK8-LABEL: define {{[^@]+}}@main 5275 // CHECK8-SAME: () #[[ATTR2:[0-9]+]] { 5276 // CHECK8-NEXT: entry: 5277 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 5278 // CHECK8-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 5279 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 5280 // CHECK8-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) 5281 // CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 5282 // CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* 5283 // CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) 5284 // CHECK8-NEXT: ret i32 0 5285 // 5286 // 5287 // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 5288 // CHECK8-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 { 5289 // CHECK8-NEXT: entry: 5290 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 5291 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 5292 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 5293 // CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 5294 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 5295 // CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 5296 // CHECK8-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) 5297 // CHECK8-NEXT: ret void 5298 // 5299 // 5300 // CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke 5301 // CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR3]] { 5302 // CHECK8-NEXT: entry: 5303 // CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 5304 // CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 5305 // CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, align 128 5306 // CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 5307 // CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* 5308 // CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 5309 // CHECK8-NEXT: store i32 1, i32* @g, align 128 5310 // CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]], i32 0, i32 0 5311 // CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128 5312 // CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]], i32 0, i32 1 5313 // CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 5314 // CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]], i32 0, i32 2 5315 // CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 5316 // CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]], i32 0, i32 3 5317 // CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 16 5318 // CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]], i32 0, i32 4 5319 // CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 5320 // CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]], i32 0, i32 6 5321 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 5322 // CHECK8-NEXT: store volatile i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 128 5323 // CHECK8-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]] to void ()* 5324 // CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* 5325 // CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 5326 // CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* 5327 // CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 5328 // CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* 5329 // CHECK8-NEXT: call void [[TMP5]](i8* [[TMP3]]) 5330 // CHECK8-NEXT: ret void 5331 // 5332 // 5333 // CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 5334 // CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR3]] { 5335 // CHECK8-NEXT: entry: 5336 // CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 5337 // CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>*, align 8 5338 // CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 5339 // CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* 5340 // CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>** [[BLOCK_ADDR]], align 8 5341 // CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK]], i32 0, i32 6 5342 // CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128 5343 // CHECK8-NEXT: ret void 5344 // 5345 // 5346 // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 5347 // CHECK8-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR3]] align 2 { 5348 // CHECK8-NEXT: entry: 5349 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 5350 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 5351 // CHECK8-NEXT: [[A2:%.*]] = alloca i32*, align 8 5352 // CHECK8-NEXT: [[B4:%.*]] = alloca i32, align 4 5353 // CHECK8-NEXT: [[C5:%.*]] = alloca i32*, align 8 5354 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 5355 // CHECK8-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 5356 // CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, align 8 5357 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 5358 // CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 5359 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 5360 // CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 5361 // CHECK8-NEXT: store i32 0, i32* [[A]], align 8 5362 // CHECK8-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 5363 // CHECK8-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 5364 // CHECK8-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 5365 // CHECK8-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 5366 // CHECK8-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 5367 // CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 5368 // CHECK8-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 5369 // CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 5370 // CHECK8-NEXT: store i32* [[A3]], i32** [[A2]], align 8 5371 // CHECK8-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 5372 // CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 5373 // CHECK8-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 5374 // CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 5375 // CHECK8-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 5376 // CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 5377 // CHECK8-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 5378 // CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 0 5379 // CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 5380 // CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 1 5381 // CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 5382 // CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 2 5383 // CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 5384 // CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 3 5385 // CHECK8-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 5386 // CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4 5387 // CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.2 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 5388 // CHECK8-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 5389 // CHECK8-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8 5390 // CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 5391 // CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 5392 // CHECK8-NEXT: store i32* [[TMP4]], i32** [[BLOCK_CAPTURED]], align 8 5393 // CHECK8-NEXT: [[BLOCK_CAPTURED8:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 5394 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 5395 // CHECK8-NEXT: store i32 [[TMP5]], i32* [[BLOCK_CAPTURED8]], align 8 5396 // CHECK8-NEXT: [[BLOCK_CAPTURED9:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 5397 // CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP7]], align 8 5398 // CHECK8-NEXT: store i32* [[TMP6]], i32** [[BLOCK_CAPTURED9]], align 8 5399 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()* 5400 // CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP7]] to %struct.__block_literal_generic* 5401 // CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 5402 // CHECK8-NEXT: [[TMP9:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* 5403 // CHECK8-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP8]], align 8 5404 // CHECK8-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to void (i8*)* 5405 // CHECK8-NEXT: call void [[TMP11]](i8* [[TMP9]]) 5406 // CHECK8-NEXT: ret void 5407 // 5408 // 5409 // CHECK8-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke 5410 // CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR3]] { 5411 // CHECK8-NEXT: entry: 5412 // CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 5413 // CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 5414 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 5415 // CHECK8-NEXT: [[_TMP6:%.*]] = alloca i32*, align 8 5416 // CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 5417 // CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* 5418 // CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 5419 // CHECK8-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 5420 // CHECK8-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 5421 // CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 5422 // CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 5423 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 5424 // CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 5425 // CHECK8-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 5426 // CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 5427 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 5428 // CHECK8-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 5429 // CHECK8-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 8 5430 // CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 5431 // CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 5432 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 5433 // CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 5434 // CHECK8-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 5435 // CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 5436 // CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 8 5437 // CHECK8-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 5438 // CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 5439 // CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 5440 // CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR5]], align 8 5441 // CHECK8-NEXT: store i32* [[TMP6]], i32** [[_TMP6]], align 8 5442 // CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 5443 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 5444 // CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 5445 // CHECK8-NEXT: store i32 [[INC7]], i32* [[TMP7]], align 4 5446 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 8 5447 // CHECK8-NEXT: [[DEC8:%.*]] = add nsw i32 [[TMP9]], -1 5448 // CHECK8-NEXT: store i32 [[DEC8]], i32* [[BLOCK_CAPTURE_ADDR4]], align 8 5449 // CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP6]], align 8 5450 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 5451 // CHECK8-NEXT: [[DIV9:%.*]] = sdiv i32 [[TMP11]], 1 5452 // CHECK8-NEXT: store i32 [[DIV9]], i32* [[TMP10]], align 4 5453 // CHECK8-NEXT: ret void 5454 // 5455