1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple i386-pc-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -fopenmp -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4
7
8 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
9 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple i386-pc-linux-gnu -emit-pch -o %t %s
10 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
11 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
12 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
13
14 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9
15 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s
16 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
18 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12
19
20 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
21 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s
22 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
23 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
24 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
25
26 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17
27
28 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
29 // expected-no-diagnostics
30 #ifndef ARRAY
31 #ifndef HEADER
32 #define HEADER
33
34 enum omp_allocator_handle_t {
35 omp_null_allocator = 0,
36 omp_default_mem_alloc = 1,
37 omp_large_cap_mem_alloc = 2,
38 omp_const_mem_alloc = 3,
39 omp_high_bw_mem_alloc = 4,
40 omp_low_lat_mem_alloc = 5,
41 omp_cgroup_mem_alloc = 6,
42 omp_pteam_mem_alloc = 7,
43 omp_thread_mem_alloc = 8,
44 KMP_ALLOCATOR_MAX_HANDLE = __UINTPTR_MAX__
45 };
46
47 struct St {
48 int a, b;
StSt49 St() : a(0), b(0) {}
StSt50 St(const St &st) : a(st.a + st.b), b(0) {}
~StSt51 ~St() {}
52 };
53
54 volatile int g __attribute__((aligned(128))) = 1212;
55
56 struct SS {
57 int a;
58 int b : 4;
59 int &c;
60 int e[4];
SSSS61 SS(int &d) : a(0), b(0), c(d) {
62 #pragma omp parallel firstprivate(a, b, c, e)
63 #ifdef LAMBDA
64 [&]() {
65 ++this->a, --b, (this)->c /= 1;
66 #pragma omp parallel firstprivate(a, b, c)
67 ++(this)->a, --b, this->c /= 1;
68 }();
69 #elif defined(BLOCKS)
70 ^{
71 ++a;
72 --this->b;
73 (this)->c /= 1;
74 #pragma omp parallel firstprivate(a, b, c)
75 ++(this)->a, --b, this->c /= 1;
76 }();
77 #else
78 ++this->a, --b, c /= 1, e[2] = 1111;
79 #endif
80 }
81 };
82
83 template<typename T>
84 struct SST {
85 T a;
SSTSST86 SST() : a(T()) {
87 #pragma omp parallel firstprivate(a)
88 #ifdef LAMBDA
89 [&]() {
90 [&]() {
91 ++this->a;
92 #pragma omp parallel firstprivate(a)
93 ++(this)->a;
94 }();
95 }();
96 #elif defined(BLOCKS)
97 ^{
98 ^{
99 ++a;
100 #pragma omp parallel firstprivate(a)
101 ++(this)->a;
102 }();
103 }();
104 #else
105 ++(this)->a;
106 #endif
107 }
108 };
109
110 template <class T>
111 struct S {
112 T f;
SS113 S(T a) : f(a + g) {}
SS114 S() : f(g) {}
SS115 S(const S &s, St t = St()) : f(s.f + t.a) {}
operator TS116 operator T() { return T(); }
~SS117 ~S() {}
118 };
119
120
121 template <typename T>
tmain()122 T tmain() {
123 S<T> test;
124 SST<T> sst;
125 T t_var __attribute__((aligned(128))) = T();
126 T vec[] __attribute__((aligned(128))) = {1, 2};
127 S<T> s_arr[] __attribute__((aligned(128))) = {1, 2};
128 S<T> var __attribute__((aligned(128))) (3);
129 #pragma omp parallel firstprivate(t_var, vec, s_arr, var)
130 {
131 vec[0] = t_var;
132 s_arr[0] = var;
133 }
134 #pragma omp parallel firstprivate(t_var)
135 {}
136 return T();
137 }
138
main()139 int main() {
140 static int sivar;
141 SS ss(sivar);
142 #ifdef LAMBDA
143 [&]() {
144 #pragma omp parallel firstprivate(g, sivar)
145 {
146
147
148
149 g = 1;
150 sivar = 2;
151 [&]() {
152 g = 2;
153 sivar = 4;
154 }();
155 }
156 }();
157 return 0;
158 #elif defined(BLOCKS)
159 ^{
160 #pragma omp parallel firstprivate(g, sivar)
161 {
162 g = 1;
163 sivar = 2;
164 ^{
165 g = 2;
166 sivar = 4;
167 }();
168 }
169 }();
170 return 0;
171
172
173 #else
174 S<float> test;
175 int t_var = 0;
176 int vec[] = {1, 2};
177 S<float> s_arr[] = {1, 2};
178 S<float> var(3);
179 #pragma omp parallel firstprivate(t_var, vec, s_arr, var, sivar)
180 {
181 vec[0] = t_var;
182 s_arr[0] = var;
183 sivar = 2;
184 }
185 const int a = 0;
186 #pragma omp parallel allocate(omp_default_mem_alloc: t_var) firstprivate(t_var, a)
187 { t_var = a; }
188 return tmain<int>();
189 #endif
190 }
191
192
193
194
195
196
197
198
199
200
201
202
203
204 #endif
205 #else
206
207 enum omp_allocator_handle_t {
208 omp_null_allocator = 0,
209 omp_default_mem_alloc = 1,
210 omp_large_cap_mem_alloc = 2,
211 omp_const_mem_alloc = 3,
212 omp_high_bw_mem_alloc = 4,
213 omp_low_lat_mem_alloc = 5,
214 omp_cgroup_mem_alloc = 6,
215 omp_pteam_mem_alloc = 7,
216 omp_thread_mem_alloc = 8,
217 KMP_ALLOCATOR_MAX_HANDLE = __UINTPTR_MAX__
218 };
219
220 struct St {
221 int a, b;
StSt222 St() : a(0), b(0) {}
StSt223 St(const St &) { }
~StSt224 ~St() {}
St_funcSt225 void St_func(St s[2], int n, long double vla1[n]) {
226 double vla2[n][n] __attribute__((aligned(128)));
227 a = b;
228 #pragma omp parallel allocate(omp_thread_mem_alloc:vla2) firstprivate(s, vla1, vla2)
229 vla1[b] = vla2[1][n - 1] = a = b;
230 }
231 };
232
array_func(float a[3],St s[2],int n,long double vla1[n])233 void array_func(float a[3], St s[2], int n, long double vla1[n]) {
234 double vla2[n][n] __attribute__((aligned(128)));
235 #pragma omp parallel firstprivate(a, s, vla1, vla2)
236 s[0].St_func(s, n, vla1);
237 ;
238 }
239
240 #endif
241
242 // CHECK1-LABEL: define {{[^@]+}}@main
243 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
244 // CHECK1-NEXT: entry:
245 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
246 // CHECK1-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
247 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
248 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
249 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
250 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
251 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4
252 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
253 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
254 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
255 // CHECK1-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4
256 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
257 // CHECK1-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)
258 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]])
259 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4
260 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
261 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false)
262 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
263 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00)
264 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1
265 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00)
266 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00)
267 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4
268 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[T_VAR_CASTED]], align 4
269 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
270 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
271 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[SIVAR_CASTED]], align 4
272 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
273 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32 [[TMP2]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32 [[TMP4]])
274 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4
275 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4
276 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[T_VAR_CASTED1]], align 4
277 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR_CASTED1]], align 4
278 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP6]])
279 // CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
280 // CHECK1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
281 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]]
282 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
283 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
284 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
285 // CHECK1: arraydestroy.body:
286 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
287 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
288 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
289 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
290 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
291 // CHECK1: arraydestroy.done2:
292 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
293 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4
294 // CHECK1-NEXT: ret i32 [[TMP8]]
295 //
296 //
297 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi
298 // CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
299 // CHECK1-NEXT: entry:
300 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
301 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4
302 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
303 // CHECK1-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4
304 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
305 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4
306 // CHECK1-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]])
307 // CHECK1-NEXT: ret void
308 //
309 //
310 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
311 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
312 // CHECK1-NEXT: entry:
313 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
314 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
315 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
316 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
317 // CHECK1-NEXT: ret void
318 //
319 //
320 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
321 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
322 // CHECK1-NEXT: entry:
323 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
324 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
325 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
326 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
327 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
328 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
329 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
330 // CHECK1-NEXT: ret void
331 //
332 //
333 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
334 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] {
335 // CHECK1-NEXT: entry:
336 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
337 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
338 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
339 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
340 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
341 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
342 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
343 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
344 // CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
345 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
346 // CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
347 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
348 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
349 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
350 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
351 // CHECK1-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
352 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
353 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
354 // CHECK1-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
355 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
356 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
357 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
358 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
359 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
360 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
361 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
362 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
363 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
364 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
365 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
366 // CHECK1: omp.arraycpy.body:
367 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
368 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
369 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
370 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
371 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
372 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
373 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
374 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
375 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
376 // CHECK1: omp.arraycpy.done3:
377 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
378 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]])
379 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]
380 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
381 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 0
382 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4
383 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
384 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8*
385 // CHECK1-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR4]] to i8*
386 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 4, i1 false)
387 // CHECK1-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4
388 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]]
389 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
390 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2
391 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
392 // CHECK1: arraydestroy.body:
393 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
394 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
395 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
396 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
397 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
398 // CHECK1: arraydestroy.done8:
399 // CHECK1-NEXT: ret void
400 //
401 //
402 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
403 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
404 // CHECK1-NEXT: entry:
405 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
406 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
407 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
408 // CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
409 // CHECK1-NEXT: ret void
410 //
411 //
412 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
413 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
414 // CHECK1-NEXT: entry:
415 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
416 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
417 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
418 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
419 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
420 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
421 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
422 // CHECK1-NEXT: ret void
423 //
424 //
425 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
426 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
427 // CHECK1-NEXT: entry:
428 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
429 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
430 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
431 // CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
432 // CHECK1-NEXT: ret void
433 //
434 //
435 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
436 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
437 // CHECK1-NEXT: entry:
438 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
439 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
440 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
441 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
442 // CHECK1-NEXT: ret void
443 //
444 //
445 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
446 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] {
447 // CHECK1-NEXT: entry:
448 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
449 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
450 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
451 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
452 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
453 // CHECK1-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
454 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
455 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
456 // CHECK1-NEXT: [[DOTT_VAR__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP1]], i32 4, i8* inttoptr (i32 1 to i8*))
457 // CHECK1-NEXT: [[DOTT_VAR__ADDR:%.*]] = bitcast i8* [[DOTT_VAR__VOID_ADDR]] to i32*
458 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
459 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTT_VAR__ADDR]], align 4
460 // CHECK1-NEXT: store i32 0, i32* [[DOTT_VAR__ADDR]], align 4
461 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTT_VAR__ADDR]] to i8*
462 // CHECK1-NEXT: call void @__kmpc_free(i32 [[TMP1]], i8* [[TMP3]], i8* inttoptr (i32 1 to i8*))
463 // CHECK1-NEXT: ret void
464 //
465 //
466 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
467 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] comdat {
468 // CHECK1-NEXT: entry:
469 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
470 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
471 // CHECK1-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4
472 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128
473 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128
474 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128
475 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128
476 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
477 // CHECK1-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]])
478 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 128
479 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
480 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
481 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
482 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
483 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
484 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
485 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3)
486 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]])
487 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[T_VAR]])
488 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
489 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
490 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
491 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
492 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
493 // CHECK1: arraydestroy.body:
494 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
495 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
496 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
497 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
498 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
499 // CHECK1: arraydestroy.done1:
500 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
501 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4
502 // CHECK1-NEXT: ret i32 [[TMP2]]
503 //
504 //
505 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi
506 // CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
507 // CHECK1-NEXT: entry:
508 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
509 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4
510 // CHECK1-NEXT: [[A2:%.*]] = alloca i32*, align 4
511 // CHECK1-NEXT: [[B4:%.*]] = alloca i32, align 4
512 // CHECK1-NEXT: [[C7:%.*]] = alloca i32*, align 4
513 // CHECK1-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 4
514 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
515 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
516 // CHECK1-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4
517 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
518 // CHECK1-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4
519 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
520 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
521 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4
522 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
523 // CHECK1-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4
524 // CHECK1-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16
525 // CHECK1-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0
526 // CHECK1-NEXT: store i8 [[BF_SET]], i8* [[B]], align 4
527 // CHECK1-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2
528 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4
529 // CHECK1-NEXT: store i32* [[TMP0]], i32** [[C]], align 4
530 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
531 // CHECK1-NEXT: store i32* [[A3]], i32** [[A2]], align 4
532 // CHECK1-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
533 // CHECK1-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4
534 // CHECK1-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4
535 // CHECK1-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4
536 // CHECK1-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32
537 // CHECK1-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4
538 // CHECK1-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2
539 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 4
540 // CHECK1-NEXT: store i32* [[TMP1]], i32** [[C7]], align 4
541 // CHECK1-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3
542 // CHECK1-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 4
543 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 4
544 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
545 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
546 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
547 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4
548 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4
549 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
550 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 4
551 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
552 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[C_CASTED]], align 4
553 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[C_CASTED]], align 4
554 // CHECK1-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 4
555 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i32, i32, i32, [4 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP9]], [4 x i32]* [[TMP10]])
556 // CHECK1-NEXT: ret void
557 //
558 //
559 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
560 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] {
561 // CHECK1-NEXT: entry:
562 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
563 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
564 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
565 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
566 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
567 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
568 // CHECK1-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 4
569 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32*, align 4
570 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4
571 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca [4 x i32]*, align 4
572 // CHECK1-NEXT: [[E3:%.*]] = alloca [4 x i32], align 4
573 // CHECK1-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 4
574 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
575 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
576 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
577 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
578 // CHECK1-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
579 // CHECK1-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4
580 // CHECK1-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 4
581 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
582 // CHECK1-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 4
583 // CHECK1-NEXT: store i32* [[A_ADDR]], i32** [[TMP]], align 4
584 // CHECK1-NEXT: store i32* [[C_ADDR]], i32** [[_TMP1]], align 4
585 // CHECK1-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP2]], align 4
586 // CHECK1-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP2]], align 4
587 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E3]] to i8*
588 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8*
589 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 16, i1 false)
590 // CHECK1-NEXT: store [4 x i32]* [[E3]], [4 x i32]** [[_TMP4]], align 4
591 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 4
592 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
593 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
594 // CHECK1-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4
595 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[B_ADDR]], align 4
596 // CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1
597 // CHECK1-NEXT: store i32 [[DEC]], i32* [[B_ADDR]], align 4
598 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP1]], align 4
599 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
600 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1
601 // CHECK1-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4
602 // CHECK1-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP4]], align 4
603 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i32 0, i32 2
604 // CHECK1-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4
605 // CHECK1-NEXT: ret void
606 //
607 //
608 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
609 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
610 // CHECK1-NEXT: entry:
611 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
612 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
613 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
614 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
615 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128
616 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
617 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4
618 // CHECK1-NEXT: ret void
619 //
620 //
621 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
622 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
623 // CHECK1-NEXT: entry:
624 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
625 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
626 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
627 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
628 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
629 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
630 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
631 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128
632 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
633 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
634 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
635 // CHECK1-NEXT: ret void
636 //
637 //
638 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
639 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
640 // CHECK1-NEXT: entry:
641 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
642 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
643 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
644 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
645 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4
646 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
647 // CHECK1-NEXT: store i32 0, i32* [[B]], align 4
648 // CHECK1-NEXT: ret void
649 //
650 //
651 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
652 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
653 // CHECK1-NEXT: entry:
654 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
655 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
656 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
657 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
658 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
659 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
660 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
661 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
662 // CHECK1-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
663 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
664 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
665 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
666 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
667 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
668 // CHECK1-NEXT: ret void
669 //
670 //
671 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
672 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
673 // CHECK1-NEXT: entry:
674 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
675 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
676 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
677 // CHECK1-NEXT: ret void
678 //
679 //
680 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
681 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
682 // CHECK1-NEXT: entry:
683 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
684 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
685 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
686 // CHECK1-NEXT: ret void
687 //
688 //
689 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
690 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
691 // CHECK1-NEXT: entry:
692 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
693 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
694 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
695 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
696 // CHECK1-NEXT: ret void
697 //
698 //
699 // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev
700 // CHECK1-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
701 // CHECK1-NEXT: entry:
702 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4
703 // CHECK1-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4
704 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4
705 // CHECK1-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]])
706 // CHECK1-NEXT: ret void
707 //
708 //
709 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
710 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
711 // CHECK1-NEXT: entry:
712 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
713 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
714 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
715 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
716 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
717 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
718 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
719 // CHECK1-NEXT: ret void
720 //
721 //
722 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
723 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
724 // CHECK1-NEXT: entry:
725 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
726 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
727 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
728 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4
729 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
730 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
731 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128
732 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128
733 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128
734 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
735 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128
736 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
737 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
738 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
739 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
740 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4
741 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
742 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
743 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
744 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4
745 // CHECK1-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
746 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
747 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128
748 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128
749 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
750 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
751 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i32 8, i1 false)
752 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
753 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0*
754 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
755 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
756 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
757 // CHECK1: omp.arraycpy.body:
758 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
759 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
760 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
761 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
762 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
763 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
764 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
765 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
766 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
767 // CHECK1: omp.arraycpy.done4:
768 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
769 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]])
770 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
771 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128
772 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0
773 // CHECK1-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128
774 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
775 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8*
776 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8*
777 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 4, i1 false)
778 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
779 // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
780 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2
781 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
782 // CHECK1: arraydestroy.body:
783 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
784 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
785 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
786 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
787 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
788 // CHECK1: arraydestroy.done9:
789 // CHECK1-NEXT: ret void
790 //
791 //
792 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
793 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
794 // CHECK1-NEXT: entry:
795 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
796 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
797 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
798 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
799 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
800 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
801 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
802 // CHECK1-NEXT: ret void
803 //
804 //
805 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
806 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
807 // CHECK1-NEXT: entry:
808 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
809 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
810 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
811 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
812 // CHECK1-NEXT: ret void
813 //
814 //
815 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
816 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] {
817 // CHECK1-NEXT: entry:
818 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
819 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
820 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4
821 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128
822 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
823 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
824 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4
825 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4
826 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128
827 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128
828 // CHECK1-NEXT: ret void
829 //
830 //
831 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
832 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
833 // CHECK1-NEXT: entry:
834 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
835 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
836 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
837 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
838 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128
839 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
840 // CHECK1-NEXT: ret void
841 //
842 //
843 // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev
844 // CHECK1-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
845 // CHECK1-NEXT: entry:
846 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4
847 // CHECK1-NEXT: [[A2:%.*]] = alloca i32*, align 4
848 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
849 // CHECK1-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4
850 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4
851 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0
852 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4
853 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0
854 // CHECK1-NEXT: store i32* [[A3]], i32** [[A2]], align 4
855 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 4
856 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
857 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
858 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
859 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.SST* [[THIS1]], i32 [[TMP2]])
860 // CHECK1-NEXT: ret void
861 //
862 //
863 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5
864 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i32 [[A:%.*]]) #[[ATTR3]] {
865 // CHECK1-NEXT: entry:
866 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
867 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
868 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4
869 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
870 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32*, align 4
871 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
872 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
873 // CHECK1-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4
874 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
875 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4
876 // CHECK1-NEXT: store i32* [[A_ADDR]], i32** [[TMP]], align 4
877 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4
878 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
879 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
880 // CHECK1-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4
881 // CHECK1-NEXT: ret void
882 //
883 //
884 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
885 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
886 // CHECK1-NEXT: entry:
887 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
888 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
889 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
890 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
891 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
892 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
893 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
894 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128
895 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
896 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
897 // CHECK1-NEXT: ret void
898 //
899 //
900 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
901 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
902 // CHECK1-NEXT: entry:
903 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
904 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
905 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
906 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
907 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
908 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
909 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
910 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
911 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
912 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
913 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
914 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
915 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
916 // CHECK1-NEXT: ret void
917 //
918 //
919 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
920 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
921 // CHECK1-NEXT: entry:
922 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
923 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
924 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
925 // CHECK1-NEXT: ret void
926 //
927 //
928 // CHECK3-LABEL: define {{[^@]+}}@main
929 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
930 // CHECK3-NEXT: entry:
931 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
932 // CHECK3-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
933 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4
934 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
935 // CHECK3-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)
936 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0
937 // CHECK3-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 4
938 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(4) [[REF_TMP]])
939 // CHECK3-NEXT: ret i32 0
940 //
941 //
942 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC1ERi
943 // CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
944 // CHECK3-NEXT: entry:
945 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
946 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4
947 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
948 // CHECK3-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4
949 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
950 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4
951 // CHECK3-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]])
952 // CHECK3-NEXT: ret void
953 //
954 //
955 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi
956 // CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
957 // CHECK3-NEXT: entry:
958 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
959 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4
960 // CHECK3-NEXT: [[A2:%.*]] = alloca i32*, align 4
961 // CHECK3-NEXT: [[B4:%.*]] = alloca i32, align 4
962 // CHECK3-NEXT: [[C7:%.*]] = alloca i32*, align 4
963 // CHECK3-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 4
964 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
965 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
966 // CHECK3-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4
967 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
968 // CHECK3-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4
969 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
970 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
971 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4
972 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
973 // CHECK3-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4
974 // CHECK3-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16
975 // CHECK3-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0
976 // CHECK3-NEXT: store i8 [[BF_SET]], i8* [[B]], align 4
977 // CHECK3-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2
978 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4
979 // CHECK3-NEXT: store i32* [[TMP0]], i32** [[C]], align 4
980 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
981 // CHECK3-NEXT: store i32* [[A3]], i32** [[A2]], align 4
982 // CHECK3-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
983 // CHECK3-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4
984 // CHECK3-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4
985 // CHECK3-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4
986 // CHECK3-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32
987 // CHECK3-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4
988 // CHECK3-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2
989 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 4
990 // CHECK3-NEXT: store i32* [[TMP1]], i32** [[C7]], align 4
991 // CHECK3-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3
992 // CHECK3-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 4
993 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 4
994 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
995 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
996 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
997 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4
998 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4
999 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
1000 // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 4
1001 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
1002 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[C_CASTED]], align 4
1003 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[C_CASTED]], align 4
1004 // CHECK3-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 4
1005 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i32, i32, i32, [4 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP9]], [4 x i32]* [[TMP10]])
1006 // CHECK3-NEXT: ret void
1007 //
1008 //
1009 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
1010 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3:[0-9]+]] {
1011 // CHECK3-NEXT: entry:
1012 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1013 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1014 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
1015 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1016 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
1017 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
1018 // CHECK3-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 4
1019 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32*, align 4
1020 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4
1021 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca [4 x i32]*, align 4
1022 // CHECK3-NEXT: [[E3:%.*]] = alloca [4 x i32], align 4
1023 // CHECK3-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 4
1024 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4
1025 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1026 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1027 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
1028 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1029 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
1030 // CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4
1031 // CHECK3-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 4
1032 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
1033 // CHECK3-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 4
1034 // CHECK3-NEXT: store i32* [[A_ADDR]], i32** [[TMP]], align 4
1035 // CHECK3-NEXT: store i32* [[C_ADDR]], i32** [[_TMP1]], align 4
1036 // CHECK3-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP2]], align 4
1037 // CHECK3-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP2]], align 4
1038 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E3]] to i8*
1039 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8*
1040 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 16, i1 false)
1041 // CHECK3-NEXT: store [4 x i32]* [[E3]], [4 x i32]** [[_TMP4]], align 4
1042 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
1043 // CHECK3-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[TMP5]], align 4
1044 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
1045 // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 4
1046 // CHECK3-NEXT: store i32* [[TMP7]], i32** [[TMP6]], align 4
1047 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
1048 // CHECK3-NEXT: store i32* [[B_ADDR]], i32** [[TMP8]], align 4
1049 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3
1050 // CHECK3-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP1]], align 4
1051 // CHECK3-NEXT: store i32* [[TMP10]], i32** [[TMP9]], align 4
1052 // CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]])
1053 // CHECK3-NEXT: ret void
1054 //
1055 //
1056 // CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv
1057 // CHECK3-SAME: (%class.anon.0* nonnull align 4 dereferenceable(16) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 {
1058 // CHECK3-NEXT: entry:
1059 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 4
1060 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
1061 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
1062 // CHECK3-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4
1063 // CHECK3-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 4
1064 // CHECK3-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 4
1065 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0
1066 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 4
1067 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1
1068 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 4
1069 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
1070 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
1071 // CHECK3-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4
1072 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2
1073 // CHECK3-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 4
1074 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
1075 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1
1076 // CHECK3-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4
1077 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3
1078 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 4
1079 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
1080 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1
1081 // CHECK3-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4
1082 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1
1083 // CHECK3-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 4
1084 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
1085 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[A_CASTED]], align 4
1086 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED]], align 4
1087 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2
1088 // CHECK3-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 4
1089 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
1090 // CHECK3-NEXT: store i32 [[TMP17]], i32* [[B_CASTED]], align 4
1091 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[B_CASTED]], align 4
1092 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3
1093 // CHECK3-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP19]], align 4
1094 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4
1095 // CHECK3-NEXT: store i32 [[TMP21]], i32* [[C_CASTED]], align 4
1096 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[C_CASTED]], align 4
1097 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP1]], i32 [[TMP14]], i32 [[TMP18]], i32 [[TMP22]])
1098 // CHECK3-NEXT: ret void
1099 //
1100 //
1101 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
1102 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) #[[ATTR3]] {
1103 // CHECK3-NEXT: entry:
1104 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1105 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1106 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
1107 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1108 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
1109 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
1110 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32*, align 4
1111 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4
1112 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1113 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1114 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
1115 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1116 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
1117 // CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4
1118 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
1119 // CHECK3-NEXT: store i32* [[A_ADDR]], i32** [[TMP]], align 4
1120 // CHECK3-NEXT: store i32* [[C_ADDR]], i32** [[_TMP1]], align 4
1121 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4
1122 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
1123 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
1124 // CHECK3-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4
1125 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4
1126 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1
1127 // CHECK3-NEXT: store i32 [[DEC]], i32* [[B_ADDR]], align 4
1128 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP1]], align 4
1129 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
1130 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1
1131 // CHECK3-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4
1132 // CHECK3-NEXT: ret void
1133 //
1134 //
1135 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2
1136 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3]] {
1137 // CHECK3-NEXT: entry:
1138 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1139 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1140 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4
1141 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
1142 // CHECK3-NEXT: [[G1:%.*]] = alloca i32, align 128
1143 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 4
1144 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1145 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1146 // CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4
1147 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
1148 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 4
1149 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[TMP0]], align 128
1150 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128
1151 // CHECK3-NEXT: store i32 1, i32* [[G1]], align 128
1152 // CHECK3-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4
1153 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0
1154 // CHECK3-NEXT: store i32* [[G1]], i32** [[TMP2]], align 4
1155 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1
1156 // CHECK3-NEXT: store i32* [[SIVAR_ADDR]], i32** [[TMP3]], align 4
1157 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* nonnull align 4 dereferenceable(8) [[REF_TMP]])
1158 // CHECK3-NEXT: ret void
1159 //
1160 //
1161 // CHECK4-LABEL: define {{[^@]+}}@main
1162 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] {
1163 // CHECK4-NEXT: entry:
1164 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1165 // CHECK4-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
1166 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 4
1167 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4
1168 // CHECK4-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)
1169 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0
1170 // CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 4
1171 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1
1172 // CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 4
1173 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2
1174 // CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4
1175 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3
1176 // CHECK4-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 4
1177 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4
1178 // CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i32, i32, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 4
1179 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5
1180 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
1181 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 4
1182 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()*
1183 // CHECK4-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic*
1184 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3
1185 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8*
1186 // CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 4
1187 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)*
1188 // CHECK4-NEXT: call void [[TMP5]](i8* [[TMP3]])
1189 // CHECK4-NEXT: ret i32 0
1190 //
1191 //
1192 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC1ERi
1193 // CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1194 // CHECK4-NEXT: entry:
1195 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
1196 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4
1197 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
1198 // CHECK4-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4
1199 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
1200 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4
1201 // CHECK4-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]])
1202 // CHECK4-NEXT: ret void
1203 //
1204 //
1205 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke
1206 // CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] {
1207 // CHECK4-NEXT: entry:
1208 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 4
1209 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 4
1210 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
1211 // CHECK4-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4
1212 // CHECK4-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*
1213 // CHECK4-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 4
1214 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
1215 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[SIVAR_CASTED]], align 4
1216 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
1217 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @g, i32 [[TMP1]])
1218 // CHECK4-NEXT: ret void
1219 //
1220 //
1221 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
1222 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] {
1223 // CHECK4-NEXT: entry:
1224 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1225 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1226 // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4
1227 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
1228 // CHECK4-NEXT: [[G1:%.*]] = alloca i32, align 128
1229 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, align 128
1230 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1231 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1232 // CHECK4-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4
1233 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
1234 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 4
1235 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[TMP0]], align 128
1236 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128
1237 // CHECK4-NEXT: store i32 1, i32* [[G1]], align 128
1238 // CHECK4-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4
1239 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 0
1240 // CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128
1241 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 1
1242 // CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 4
1243 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 2
1244 // CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 8
1245 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 3
1246 // CHECK4-NEXT: store i8* bitcast (void (i8*)* @g_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 4
1247 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 4
1248 // CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i32, i32, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 16
1249 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 7
1250 // CHECK4-NEXT: [[TMP2:%.*]] = load volatile i32, i32* [[G1]], align 128
1251 // CHECK4-NEXT: store volatile i32 [[TMP2]], i32* [[BLOCK_CAPTURED]], align 128
1252 // CHECK4-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 5
1253 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
1254 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[BLOCK_CAPTURED2]], align 4
1255 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]] to void ()*
1256 // CHECK4-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP4]] to %struct.__block_literal_generic*
1257 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3
1258 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8*
1259 // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP5]], align 4
1260 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to void (i8*)*
1261 // CHECK4-NEXT: call void [[TMP8]](i8* [[TMP6]])
1262 // CHECK4-NEXT: ret void
1263 //
1264 //
1265 // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke
1266 // CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] {
1267 // CHECK4-NEXT: entry:
1268 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 4
1269 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>*, align 4
1270 // CHECK4-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4
1271 // CHECK4-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>*
1272 // CHECK4-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>** [[BLOCK_ADDR]], align 4
1273 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 7
1274 // CHECK4-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128
1275 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 5
1276 // CHECK4-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR1]], align 4
1277 // CHECK4-NEXT: ret void
1278 //
1279 //
1280 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi
1281 // CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1282 // CHECK4-NEXT: entry:
1283 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
1284 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4
1285 // CHECK4-NEXT: [[A2:%.*]] = alloca i32*, align 4
1286 // CHECK4-NEXT: [[B4:%.*]] = alloca i32, align 4
1287 // CHECK4-NEXT: [[C7:%.*]] = alloca i32*, align 4
1288 // CHECK4-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 4
1289 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
1290 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
1291 // CHECK4-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4
1292 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
1293 // CHECK4-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4
1294 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
1295 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
1296 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4
1297 // CHECK4-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
1298 // CHECK4-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4
1299 // CHECK4-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16
1300 // CHECK4-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0
1301 // CHECK4-NEXT: store i8 [[BF_SET]], i8* [[B]], align 4
1302 // CHECK4-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2
1303 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4
1304 // CHECK4-NEXT: store i32* [[TMP0]], i32** [[C]], align 4
1305 // CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
1306 // CHECK4-NEXT: store i32* [[A3]], i32** [[A2]], align 4
1307 // CHECK4-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
1308 // CHECK4-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4
1309 // CHECK4-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4
1310 // CHECK4-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4
1311 // CHECK4-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32
1312 // CHECK4-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4
1313 // CHECK4-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2
1314 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 4
1315 // CHECK4-NEXT: store i32* [[TMP1]], i32** [[C7]], align 4
1316 // CHECK4-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3
1317 // CHECK4-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 4
1318 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 4
1319 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1320 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
1321 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
1322 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4
1323 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4
1324 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
1325 // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 4
1326 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
1327 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[C_CASTED]], align 4
1328 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[C_CASTED]], align 4
1329 // CHECK4-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 4
1330 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i32, i32, i32, [4 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP9]], [4 x i32]* [[TMP10]])
1331 // CHECK4-NEXT: ret void
1332 //
1333 //
1334 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2
1335 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR2]] {
1336 // CHECK4-NEXT: entry:
1337 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1338 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1339 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
1340 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1341 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
1342 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
1343 // CHECK4-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 4
1344 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32*, align 4
1345 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4
1346 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca [4 x i32]*, align 4
1347 // CHECK4-NEXT: [[E3:%.*]] = alloca [4 x i32], align 4
1348 // CHECK4-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 4
1349 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, align 4
1350 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1351 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1352 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
1353 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1354 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
1355 // CHECK4-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4
1356 // CHECK4-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 4
1357 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
1358 // CHECK4-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 4
1359 // CHECK4-NEXT: store i32* [[A_ADDR]], i32** [[TMP]], align 4
1360 // CHECK4-NEXT: store i32* [[C_ADDR]], i32** [[_TMP1]], align 4
1361 // CHECK4-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP2]], align 4
1362 // CHECK4-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP2]], align 4
1363 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E3]] to i8*
1364 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8*
1365 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 16, i1 false)
1366 // CHECK4-NEXT: store [4 x i32]* [[E3]], [4 x i32]** [[_TMP4]], align 4
1367 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 0
1368 // CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 4
1369 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 1
1370 // CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 4
1371 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 2
1372 // CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4
1373 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 3
1374 // CHECK4-NEXT: store i8* bitcast (void (i8*)* @g_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 4
1375 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 4
1376 // CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i32, i32, i8*, i8* }* @__block_descriptor_tmp.4 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 4
1377 // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 5
1378 // CHECK4-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 4
1379 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 6
1380 // CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 4
1381 // CHECK4-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED]], align 4
1382 // CHECK4-NEXT: [[BLOCK_CAPTURED5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 7
1383 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_ADDR]], align 4
1384 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED5]], align 4
1385 // CHECK4-NEXT: [[BLOCK_CAPTURED6:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 8
1386 // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP1]], align 4
1387 // CHECK4-NEXT: store i32* [[TMP7]], i32** [[BLOCK_CAPTURED6]], align 4
1388 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]] to void ()*
1389 // CHECK4-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP8]] to %struct.__block_literal_generic*
1390 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3
1391 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8*
1392 // CHECK4-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP9]], align 4
1393 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8* [[TMP11]] to void (i8*)*
1394 // CHECK4-NEXT: call void [[TMP12]](i8* [[TMP10]])
1395 // CHECK4-NEXT: ret void
1396 //
1397 //
1398 // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke_2
1399 // CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] {
1400 // CHECK4-NEXT: entry:
1401 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 4
1402 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>*, align 4
1403 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
1404 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
1405 // CHECK4-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4
1406 // CHECK4-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4
1407 // CHECK4-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>*
1408 // CHECK4-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>** [[BLOCK_ADDR]], align 4
1409 // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 5
1410 // CHECK4-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 4
1411 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 6
1412 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 4
1413 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1414 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
1415 // CHECK4-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
1416 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 7
1417 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 4
1418 // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1
1419 // CHECK4-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 4
1420 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 8
1421 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 4
1422 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
1423 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1
1424 // CHECK4-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4
1425 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 6
1426 // CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 4
1427 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
1428 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[A_CASTED]], align 4
1429 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A_CASTED]], align 4
1430 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 7
1431 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 4
1432 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[B_CASTED]], align 4
1433 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[B_CASTED]], align 4
1434 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 8
1435 // CHECK4-NEXT: [[TMP10:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR5]], align 4
1436 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
1437 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[C_CASTED]], align 4
1438 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[C_CASTED]], align 4
1439 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SS* [[THIS]], i32 [[TMP7]], i32 [[TMP9]], i32 [[TMP12]])
1440 // CHECK4-NEXT: ret void
1441 //
1442 //
1443 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3
1444 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) #[[ATTR2]] {
1445 // CHECK4-NEXT: entry:
1446 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1447 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1448 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
1449 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1450 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
1451 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
1452 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32*, align 4
1453 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4
1454 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1455 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1456 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
1457 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1458 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
1459 // CHECK4-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4
1460 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
1461 // CHECK4-NEXT: store i32* [[A_ADDR]], i32** [[TMP]], align 4
1462 // CHECK4-NEXT: store i32* [[C_ADDR]], i32** [[_TMP1]], align 4
1463 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4
1464 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
1465 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
1466 // CHECK4-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4
1467 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4
1468 // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1
1469 // CHECK4-NEXT: store i32 [[DEC]], i32* [[B_ADDR]], align 4
1470 // CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP1]], align 4
1471 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
1472 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1
1473 // CHECK4-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4
1474 // CHECK4-NEXT: ret void
1475 //
1476 //
1477 // CHECK9-LABEL: define {{[^@]+}}@main
1478 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
1479 // CHECK9-NEXT: entry:
1480 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1481 // CHECK9-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8
1482 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1483 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1484 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1485 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1486 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4
1487 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1488 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
1489 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
1490 // CHECK9-NEXT: [[T_VAR_CASTED2:%.*]] = alloca i64, align 8
1491 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4
1492 // CHECK9-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)
1493 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]])
1494 // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4
1495 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1496 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false)
1497 // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0
1498 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00)
1499 // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1
1500 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00)
1501 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00)
1502 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4
1503 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1504 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4
1505 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1506 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
1507 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
1508 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
1509 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
1510 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i64 [[TMP2]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i64 [[TMP4]])
1511 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4
1512 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4
1513 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[T_VAR_CASTED2]] to i32*
1514 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
1515 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[T_VAR_CASTED2]], align 8
1516 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP6]])
1517 // CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
1518 // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
1519 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]]
1520 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1521 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
1522 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1523 // CHECK9: arraydestroy.body:
1524 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1525 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1526 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1527 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1528 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]]
1529 // CHECK9: arraydestroy.done4:
1530 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1531 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4
1532 // CHECK9-NEXT: ret i32 [[TMP8]]
1533 //
1534 //
1535 // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC1ERi
1536 // CHECK9-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1537 // CHECK9-NEXT: entry:
1538 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
1539 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8
1540 // CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
1541 // CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8
1542 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
1543 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8
1544 // CHECK9-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]])
1545 // CHECK9-NEXT: ret void
1546 //
1547 //
1548 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1549 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1550 // CHECK9-NEXT: entry:
1551 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1552 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1553 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1554 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
1555 // CHECK9-NEXT: ret void
1556 //
1557 //
1558 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1559 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1560 // CHECK9-NEXT: entry:
1561 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1562 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1563 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1564 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1565 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1566 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1567 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
1568 // CHECK9-NEXT: ret void
1569 //
1570 //
1571 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
1572 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] {
1573 // CHECK9-NEXT: entry:
1574 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1575 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1576 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1577 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1578 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
1579 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
1580 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
1581 // CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
1582 // CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4
1583 // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1584 // CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1585 // CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
1586 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1587 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1588 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1589 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1590 // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1591 // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
1592 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
1593 // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1594 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1595 // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1596 // CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
1597 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
1598 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
1599 // CHECK9-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1600 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
1601 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
1602 // CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
1603 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
1604 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
1605 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1606 // CHECK9: omp.arraycpy.body:
1607 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1608 // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1609 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1610 // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
1611 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
1612 // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1613 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1614 // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
1615 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
1616 // CHECK9: omp.arraycpy.done4:
1617 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
1618 // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]])
1619 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
1620 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
1621 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0
1622 // CHECK9-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4
1623 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0
1624 // CHECK9-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
1625 // CHECK9-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
1626 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false)
1627 // CHECK9-NEXT: store i32 2, i32* [[CONV1]], align 4
1628 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
1629 // CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
1630 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2
1631 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1632 // CHECK9: arraydestroy.body:
1633 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1634 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1635 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1636 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
1637 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
1638 // CHECK9: arraydestroy.done9:
1639 // CHECK9-NEXT: ret void
1640 //
1641 //
1642 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC1Ev
1643 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1644 // CHECK9-NEXT: entry:
1645 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1646 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1647 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1648 // CHECK9-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
1649 // CHECK9-NEXT: ret void
1650 //
1651 //
1652 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
1653 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1654 // CHECK9-NEXT: entry:
1655 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1656 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
1657 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1658 // CHECK9-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
1659 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1660 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
1661 // CHECK9-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
1662 // CHECK9-NEXT: ret void
1663 //
1664 //
1665 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD1Ev
1666 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1667 // CHECK9-NEXT: entry:
1668 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1669 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1670 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1671 // CHECK9-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
1672 // CHECK9-NEXT: ret void
1673 //
1674 //
1675 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1676 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1677 // CHECK9-NEXT: entry:
1678 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1679 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1680 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1681 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
1682 // CHECK9-NEXT: ret void
1683 //
1684 //
1685 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
1686 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] {
1687 // CHECK9-NEXT: entry:
1688 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1689 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1690 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1691 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1692 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1693 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1694 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1695 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1696 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1697 // CHECK9-NEXT: [[DOTT_VAR__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP1]], i64 4, i8* inttoptr (i64 1 to i8*))
1698 // CHECK9-NEXT: [[DOTT_VAR__ADDR:%.*]] = bitcast i8* [[DOTT_VAR__VOID_ADDR]] to i32*
1699 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
1700 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTT_VAR__ADDR]], align 4
1701 // CHECK9-NEXT: store i32 0, i32* [[DOTT_VAR__ADDR]], align 4
1702 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTT_VAR__ADDR]] to i8*
1703 // CHECK9-NEXT: call void @__kmpc_free(i32 [[TMP1]], i8* [[TMP3]], i8* inttoptr (i64 1 to i8*))
1704 // CHECK9-NEXT: ret void
1705 //
1706 //
1707 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1708 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat {
1709 // CHECK9-NEXT: entry:
1710 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1711 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1712 // CHECK9-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4
1713 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128
1714 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128
1715 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128
1716 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128
1717 // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
1718 // CHECK9-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]])
1719 // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 128
1720 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1721 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
1722 // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
1723 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
1724 // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
1725 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
1726 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3)
1727 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]])
1728 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[T_VAR]])
1729 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4
1730 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
1731 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1732 // CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1733 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1734 // CHECK9: arraydestroy.body:
1735 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1736 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1737 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1738 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1739 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1740 // CHECK9: arraydestroy.done1:
1741 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1742 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4
1743 // CHECK9-NEXT: ret i32 [[TMP2]]
1744 //
1745 //
1746 // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi
1747 // CHECK9-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1748 // CHECK9-NEXT: entry:
1749 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
1750 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8
1751 // CHECK9-NEXT: [[A2:%.*]] = alloca i32*, align 8
1752 // CHECK9-NEXT: [[B4:%.*]] = alloca i32, align 4
1753 // CHECK9-NEXT: [[C7:%.*]] = alloca i32*, align 8
1754 // CHECK9-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8
1755 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1756 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
1757 // CHECK9-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8
1758 // CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
1759 // CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8
1760 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
1761 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
1762 // CHECK9-NEXT: store i32 0, i32* [[A]], align 8
1763 // CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
1764 // CHECK9-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4
1765 // CHECK9-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16
1766 // CHECK9-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0
1767 // CHECK9-NEXT: store i8 [[BF_SET]], i8* [[B]], align 4
1768 // CHECK9-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2
1769 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8
1770 // CHECK9-NEXT: store i32* [[TMP0]], i32** [[C]], align 8
1771 // CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
1772 // CHECK9-NEXT: store i32* [[A3]], i32** [[A2]], align 8
1773 // CHECK9-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
1774 // CHECK9-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4
1775 // CHECK9-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4
1776 // CHECK9-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4
1777 // CHECK9-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32
1778 // CHECK9-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4
1779 // CHECK9-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2
1780 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8
1781 // CHECK9-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8
1782 // CHECK9-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3
1783 // CHECK9-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8
1784 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8
1785 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1786 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1787 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4
1788 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
1789 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4
1790 // CHECK9-NEXT: [[CONV10:%.*]] = bitcast i64* [[B_CASTED]] to i32*
1791 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV10]], align 4
1792 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
1793 // CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 8
1794 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
1795 // CHECK9-NEXT: [[CONV11:%.*]] = bitcast i64* [[C_CASTED]] to i32*
1796 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV11]], align 4
1797 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8
1798 // CHECK9-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8
1799 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64, [4 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], [4 x i32]* [[TMP10]])
1800 // CHECK9-NEXT: ret void
1801 //
1802 //
1803 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
1804 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] {
1805 // CHECK9-NEXT: entry:
1806 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1807 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1808 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
1809 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1810 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
1811 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8
1812 // CHECK9-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 8
1813 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8
1814 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8
1815 // CHECK9-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 8
1816 // CHECK9-NEXT: [[E5:%.*]] = alloca [4 x i32], align 16
1817 // CHECK9-NEXT: [[_TMP6:%.*]] = alloca [4 x i32]*, align 8
1818 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1819 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1820 // CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
1821 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1822 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
1823 // CHECK9-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8
1824 // CHECK9-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 8
1825 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
1826 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1827 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1828 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32*
1829 // CHECK9-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 8
1830 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8
1831 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8
1832 // CHECK9-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP4]], align 8
1833 // CHECK9-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP4]], align 8
1834 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8*
1835 // CHECK9-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8*
1836 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false)
1837 // CHECK9-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8
1838 // CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8
1839 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
1840 // CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
1841 // CHECK9-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4
1842 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 4
1843 // CHECK9-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1
1844 // CHECK9-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
1845 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP3]], align 8
1846 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
1847 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1
1848 // CHECK9-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4
1849 // CHECK9-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP6]], align 8
1850 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i64 0, i64 2
1851 // CHECK9-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4
1852 // CHECK9-NEXT: ret void
1853 //
1854 //
1855 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1856 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1857 // CHECK9-NEXT: entry:
1858 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1859 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1860 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1861 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1862 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128
1863 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1864 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4
1865 // CHECK9-NEXT: ret void
1866 //
1867 //
1868 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1869 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1870 // CHECK9-NEXT: entry:
1871 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1872 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1873 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1874 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1875 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1876 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1877 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1878 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128
1879 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1880 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1881 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4
1882 // CHECK9-NEXT: ret void
1883 //
1884 //
1885 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC2Ev
1886 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1887 // CHECK9-NEXT: entry:
1888 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1889 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1890 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1891 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
1892 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4
1893 // CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
1894 // CHECK9-NEXT: store i32 0, i32* [[B]], align 4
1895 // CHECK9-NEXT: ret void
1896 //
1897 //
1898 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
1899 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1900 // CHECK9-NEXT: entry:
1901 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1902 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
1903 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1904 // CHECK9-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
1905 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1906 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1907 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
1908 // CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
1909 // CHECK9-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
1910 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
1911 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
1912 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
1913 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
1914 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4
1915 // CHECK9-NEXT: ret void
1916 //
1917 //
1918 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD2Ev
1919 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1920 // CHECK9-NEXT: entry:
1921 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1922 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1923 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1924 // CHECK9-NEXT: ret void
1925 //
1926 //
1927 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1928 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1929 // CHECK9-NEXT: entry:
1930 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1931 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1932 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1933 // CHECK9-NEXT: ret void
1934 //
1935 //
1936 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1937 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1938 // CHECK9-NEXT: entry:
1939 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1940 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1941 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1942 // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
1943 // CHECK9-NEXT: ret void
1944 //
1945 //
1946 // CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev
1947 // CHECK9-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1948 // CHECK9-NEXT: entry:
1949 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8
1950 // CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8
1951 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8
1952 // CHECK9-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]])
1953 // CHECK9-NEXT: ret void
1954 //
1955 //
1956 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1957 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1958 // CHECK9-NEXT: entry:
1959 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1960 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1961 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1962 // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1963 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1964 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1965 // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
1966 // CHECK9-NEXT: ret void
1967 //
1968 //
1969 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
1970 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1971 // CHECK9-NEXT: entry:
1972 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1973 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1974 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1975 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
1976 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
1977 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
1978 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128
1979 // CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128
1980 // CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128
1981 // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1982 // CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128
1983 // CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
1984 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1985 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1986 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1987 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
1988 // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1989 // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
1990 // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1991 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
1992 // CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1993 // CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
1994 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128
1995 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128
1996 // CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
1997 // CHECK9-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1998 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i64 8, i1 false)
1999 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
2000 // CHECK9-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0*
2001 // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
2002 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
2003 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2004 // CHECK9: omp.arraycpy.body:
2005 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2006 // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2007 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2008 // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
2009 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
2010 // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2011 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2012 // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
2013 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
2014 // CHECK9: omp.arraycpy.done4:
2015 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
2016 // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]])
2017 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
2018 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128
2019 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0
2020 // CHECK9-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128
2021 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0
2022 // CHECK9-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8*
2023 // CHECK9-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8*
2024 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 4, i1 false)
2025 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
2026 // CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
2027 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2
2028 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2029 // CHECK9: arraydestroy.body:
2030 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2031 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2032 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2033 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
2034 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
2035 // CHECK9: arraydestroy.done9:
2036 // CHECK9-NEXT: ret void
2037 //
2038 //
2039 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
2040 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2041 // CHECK9-NEXT: entry:
2042 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2043 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
2044 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2045 // CHECK9-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
2046 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2047 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
2048 // CHECK9-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
2049 // CHECK9-NEXT: ret void
2050 //
2051 //
2052 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2053 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2054 // CHECK9-NEXT: entry:
2055 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2056 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2057 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2058 // CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2059 // CHECK9-NEXT: ret void
2060 //
2061 //
2062 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4
2063 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] {
2064 // CHECK9-NEXT: entry:
2065 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2066 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2067 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
2068 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128
2069 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2070 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2071 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
2072 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
2073 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128
2074 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128
2075 // CHECK9-NEXT: ret void
2076 //
2077 //
2078 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2079 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2080 // CHECK9-NEXT: entry:
2081 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2082 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2083 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2084 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2085 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128
2086 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
2087 // CHECK9-NEXT: ret void
2088 //
2089 //
2090 // CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev
2091 // CHECK9-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2092 // CHECK9-NEXT: entry:
2093 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8
2094 // CHECK9-NEXT: [[A2:%.*]] = alloca i32*, align 8
2095 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
2096 // CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8
2097 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8
2098 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0
2099 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4
2100 // CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0
2101 // CHECK9-NEXT: store i32* [[A3]], i32** [[A2]], align 8
2102 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8
2103 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2104 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2105 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4
2106 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
2107 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.SST* [[THIS1]], i64 [[TMP2]])
2108 // CHECK9-NEXT: ret void
2109 //
2110 //
2111 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
2112 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR3]] {
2113 // CHECK9-NEXT: entry:
2114 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2115 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2116 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8
2117 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
2118 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8
2119 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2120 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2121 // CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8
2122 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
2123 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8
2124 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2125 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8
2126 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8
2127 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
2128 // CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
2129 // CHECK9-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4
2130 // CHECK9-NEXT: ret void
2131 //
2132 //
2133 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2134 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2135 // CHECK9-NEXT: entry:
2136 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2137 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2138 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2139 // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2140 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2141 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2142 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2143 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128
2144 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2145 // CHECK9-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2146 // CHECK9-NEXT: ret void
2147 //
2148 //
2149 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
2150 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2151 // CHECK9-NEXT: entry:
2152 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2153 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
2154 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2155 // CHECK9-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
2156 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2157 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2158 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
2159 // CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
2160 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
2161 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
2162 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
2163 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
2164 // CHECK9-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2165 // CHECK9-NEXT: ret void
2166 //
2167 //
2168 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2169 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2170 // CHECK9-NEXT: entry:
2171 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2172 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2173 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2174 // CHECK9-NEXT: ret void
2175 //
2176 //
2177 // CHECK11-LABEL: define {{[^@]+}}@main
2178 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
2179 // CHECK11-NEXT: entry:
2180 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2181 // CHECK11-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8
2182 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
2183 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4
2184 // CHECK11-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)
2185 // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0
2186 // CHECK11-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8
2187 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]])
2188 // CHECK11-NEXT: ret i32 0
2189 //
2190 //
2191 // CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC1ERi
2192 // CHECK11-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2193 // CHECK11-NEXT: entry:
2194 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
2195 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8
2196 // CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
2197 // CHECK11-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8
2198 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
2199 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8
2200 // CHECK11-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]])
2201 // CHECK11-NEXT: ret void
2202 //
2203 //
2204 // CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC2ERi
2205 // CHECK11-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2206 // CHECK11-NEXT: entry:
2207 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
2208 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8
2209 // CHECK11-NEXT: [[A2:%.*]] = alloca i32*, align 8
2210 // CHECK11-NEXT: [[B4:%.*]] = alloca i32, align 4
2211 // CHECK11-NEXT: [[C7:%.*]] = alloca i32*, align 8
2212 // CHECK11-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8
2213 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
2214 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
2215 // CHECK11-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8
2216 // CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
2217 // CHECK11-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8
2218 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
2219 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
2220 // CHECK11-NEXT: store i32 0, i32* [[A]], align 8
2221 // CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
2222 // CHECK11-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4
2223 // CHECK11-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16
2224 // CHECK11-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0
2225 // CHECK11-NEXT: store i8 [[BF_SET]], i8* [[B]], align 4
2226 // CHECK11-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2
2227 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8
2228 // CHECK11-NEXT: store i32* [[TMP0]], i32** [[C]], align 8
2229 // CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
2230 // CHECK11-NEXT: store i32* [[A3]], i32** [[A2]], align 8
2231 // CHECK11-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
2232 // CHECK11-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4
2233 // CHECK11-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4
2234 // CHECK11-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4
2235 // CHECK11-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32
2236 // CHECK11-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4
2237 // CHECK11-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2
2238 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8
2239 // CHECK11-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8
2240 // CHECK11-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3
2241 // CHECK11-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8
2242 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8
2243 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2244 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2245 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4
2246 // CHECK11-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
2247 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4
2248 // CHECK11-NEXT: [[CONV10:%.*]] = bitcast i64* [[B_CASTED]] to i32*
2249 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[CONV10]], align 4
2250 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
2251 // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 8
2252 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
2253 // CHECK11-NEXT: [[CONV11:%.*]] = bitcast i64* [[C_CASTED]] to i32*
2254 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[CONV11]], align 4
2255 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8
2256 // CHECK11-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8
2257 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64, [4 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], [4 x i32]* [[TMP10]])
2258 // CHECK11-NEXT: ret void
2259 //
2260 //
2261 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
2262 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3:[0-9]+]] {
2263 // CHECK11-NEXT: entry:
2264 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2265 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2266 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
2267 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
2268 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
2269 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8
2270 // CHECK11-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 8
2271 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8
2272 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8
2273 // CHECK11-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 8
2274 // CHECK11-NEXT: [[E5:%.*]] = alloca [4 x i32], align 16
2275 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca [4 x i32]*, align 8
2276 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
2277 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2278 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2279 // CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
2280 // CHECK11-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
2281 // CHECK11-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
2282 // CHECK11-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8
2283 // CHECK11-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 8
2284 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
2285 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2286 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
2287 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32*
2288 // CHECK11-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 8
2289 // CHECK11-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8
2290 // CHECK11-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8
2291 // CHECK11-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP4]], align 8
2292 // CHECK11-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP4]], align 8
2293 // CHECK11-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8*
2294 // CHECK11-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8*
2295 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false)
2296 // CHECK11-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8
2297 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
2298 // CHECK11-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[TMP5]], align 8
2299 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
2300 // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8
2301 // CHECK11-NEXT: store i32* [[TMP7]], i32** [[TMP6]], align 8
2302 // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
2303 // CHECK11-NEXT: store i32* [[CONV1]], i32** [[TMP8]], align 8
2304 // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3
2305 // CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8
2306 // CHECK11-NEXT: store i32* [[TMP10]], i32** [[TMP9]], align 8
2307 // CHECK11-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]])
2308 // CHECK11-NEXT: ret void
2309 //
2310 //
2311 // CHECK11-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv
2312 // CHECK11-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 {
2313 // CHECK11-NEXT: entry:
2314 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8
2315 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
2316 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
2317 // CHECK11-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8
2318 // CHECK11-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8
2319 // CHECK11-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8
2320 // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0
2321 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8
2322 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1
2323 // CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8
2324 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
2325 // CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
2326 // CHECK11-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4
2327 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2
2328 // CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8
2329 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
2330 // CHECK11-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1
2331 // CHECK11-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4
2332 // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3
2333 // CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8
2334 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
2335 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1
2336 // CHECK11-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4
2337 // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1
2338 // CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8
2339 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
2340 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2341 // CHECK11-NEXT: store i32 [[TMP13]], i32* [[CONV]], align 4
2342 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[A_CASTED]], align 8
2343 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2
2344 // CHECK11-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8
2345 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
2346 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
2347 // CHECK11-NEXT: store i32 [[TMP17]], i32* [[CONV2]], align 4
2348 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[B_CASTED]], align 8
2349 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3
2350 // CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP19]], align 8
2351 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4
2352 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i64* [[C_CASTED]] to i32*
2353 // CHECK11-NEXT: store i32 [[TMP21]], i32* [[CONV3]], align 4
2354 // CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[C_CASTED]], align 8
2355 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP1]], i64 [[TMP14]], i64 [[TMP18]], i64 [[TMP22]])
2356 // CHECK11-NEXT: ret void
2357 //
2358 //
2359 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1
2360 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR3]] {
2361 // CHECK11-NEXT: entry:
2362 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2363 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2364 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
2365 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
2366 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
2367 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8
2368 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8
2369 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8
2370 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2371 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2372 // CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
2373 // CHECK11-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
2374 // CHECK11-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
2375 // CHECK11-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8
2376 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
2377 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2378 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
2379 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32*
2380 // CHECK11-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8
2381 // CHECK11-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8
2382 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8
2383 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
2384 // CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
2385 // CHECK11-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4
2386 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
2387 // CHECK11-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1
2388 // CHECK11-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
2389 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP3]], align 8
2390 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
2391 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1
2392 // CHECK11-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4
2393 // CHECK11-NEXT: ret void
2394 //
2395 //
2396 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2
2397 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3]] {
2398 // CHECK11-NEXT: entry:
2399 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2400 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2401 // CHECK11-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8
2402 // CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
2403 // CHECK11-NEXT: [[G1:%.*]] = alloca i32, align 128
2404 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8
2405 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2406 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2407 // CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
2408 // CHECK11-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
2409 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8
2410 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
2411 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[TMP0]], align 128
2412 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128
2413 // CHECK11-NEXT: store i32 1, i32* [[G1]], align 128
2414 // CHECK11-NEXT: store i32 2, i32* [[CONV]], align 4
2415 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0
2416 // CHECK11-NEXT: store i32* [[G1]], i32** [[TMP2]], align 8
2417 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1
2418 // CHECK11-NEXT: store i32* [[CONV]], i32** [[TMP3]], align 8
2419 // CHECK11-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* nonnull align 8 dereferenceable(16) [[REF_TMP]])
2420 // CHECK11-NEXT: ret void
2421 //
2422 //
2423 // CHECK12-LABEL: define {{[^@]+}}@main
2424 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] {
2425 // CHECK12-NEXT: entry:
2426 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2427 // CHECK12-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8
2428 // CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8
2429 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4
2430 // CHECK12-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)
2431 // CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0
2432 // CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8
2433 // CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1
2434 // CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8
2435 // CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2
2436 // CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4
2437 // CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3
2438 // CHECK12-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8
2439 // CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4
2440 // CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8
2441 // CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5
2442 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
2443 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8
2444 // CHECK12-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()*
2445 // CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic*
2446 // CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3
2447 // CHECK12-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8*
2448 // CHECK12-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8
2449 // CHECK12-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)*
2450 // CHECK12-NEXT: call void [[TMP5]](i8* [[TMP3]])
2451 // CHECK12-NEXT: ret i32 0
2452 //
2453 //
2454 // CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC1ERi
2455 // CHECK12-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2456 // CHECK12-NEXT: entry:
2457 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
2458 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8
2459 // CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
2460 // CHECK12-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8
2461 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
2462 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8
2463 // CHECK12-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]])
2464 // CHECK12-NEXT: ret void
2465 //
2466 //
2467 // CHECK12-LABEL: define {{[^@]+}}@__main_block_invoke
2468 // CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] {
2469 // CHECK12-NEXT: entry:
2470 // CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
2471 // CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8
2472 // CHECK12-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
2473 // CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
2474 // CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*
2475 // CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8
2476 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
2477 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
2478 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
2479 // CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
2480 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @g, i64 [[TMP1]])
2481 // CHECK12-NEXT: ret void
2482 //
2483 //
2484 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.
2485 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] {
2486 // CHECK12-NEXT: entry:
2487 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2488 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2489 // CHECK12-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8
2490 // CHECK12-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
2491 // CHECK12-NEXT: [[G1:%.*]] = alloca i32, align 128
2492 // CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, align 128
2493 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2494 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2495 // CHECK12-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
2496 // CHECK12-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
2497 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8
2498 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
2499 // CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[TMP0]], align 128
2500 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128
2501 // CHECK12-NEXT: store i32 1, i32* [[G1]], align 128
2502 // CHECK12-NEXT: store i32 2, i32* [[CONV]], align 4
2503 // CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 0
2504 // CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128
2505 // CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 1
2506 // CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8
2507 // CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 2
2508 // CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4
2509 // CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 3
2510 // CHECK12-NEXT: store i8* bitcast (void (i8*)* @g_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 16
2511 // CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 4
2512 // CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8
2513 // CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 7
2514 // CHECK12-NEXT: [[TMP2:%.*]] = load volatile i32, i32* [[G1]], align 128
2515 // CHECK12-NEXT: store volatile i32 [[TMP2]], i32* [[BLOCK_CAPTURED]], align 128
2516 // CHECK12-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 5
2517 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
2518 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[BLOCK_CAPTURED2]], align 32
2519 // CHECK12-NEXT: [[TMP4:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]] to void ()*
2520 // CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP4]] to %struct.__block_literal_generic*
2521 // CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3
2522 // CHECK12-NEXT: [[TMP6:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8*
2523 // CHECK12-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP5]], align 8
2524 // CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to void (i8*)*
2525 // CHECK12-NEXT: call void [[TMP8]](i8* [[TMP6]])
2526 // CHECK12-NEXT: ret void
2527 //
2528 //
2529 // CHECK12-LABEL: define {{[^@]+}}@g_block_invoke
2530 // CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] {
2531 // CHECK12-NEXT: entry:
2532 // CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
2533 // CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>*, align 8
2534 // CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
2535 // CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>*
2536 // CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>** [[BLOCK_ADDR]], align 8
2537 // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 7
2538 // CHECK12-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128
2539 // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 5
2540 // CHECK12-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR1]], align 32
2541 // CHECK12-NEXT: ret void
2542 //
2543 //
2544 // CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC2ERi
2545 // CHECK12-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2546 // CHECK12-NEXT: entry:
2547 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
2548 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8
2549 // CHECK12-NEXT: [[A2:%.*]] = alloca i32*, align 8
2550 // CHECK12-NEXT: [[B4:%.*]] = alloca i32, align 4
2551 // CHECK12-NEXT: [[C7:%.*]] = alloca i32*, align 8
2552 // CHECK12-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8
2553 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
2554 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
2555 // CHECK12-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8
2556 // CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
2557 // CHECK12-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8
2558 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
2559 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
2560 // CHECK12-NEXT: store i32 0, i32* [[A]], align 8
2561 // CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
2562 // CHECK12-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4
2563 // CHECK12-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16
2564 // CHECK12-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0
2565 // CHECK12-NEXT: store i8 [[BF_SET]], i8* [[B]], align 4
2566 // CHECK12-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2
2567 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8
2568 // CHECK12-NEXT: store i32* [[TMP0]], i32** [[C]], align 8
2569 // CHECK12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
2570 // CHECK12-NEXT: store i32* [[A3]], i32** [[A2]], align 8
2571 // CHECK12-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
2572 // CHECK12-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4
2573 // CHECK12-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4
2574 // CHECK12-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4
2575 // CHECK12-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32
2576 // CHECK12-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4
2577 // CHECK12-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2
2578 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8
2579 // CHECK12-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8
2580 // CHECK12-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3
2581 // CHECK12-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8
2582 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8
2583 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2584 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2585 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4
2586 // CHECK12-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
2587 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4
2588 // CHECK12-NEXT: [[CONV10:%.*]] = bitcast i64* [[B_CASTED]] to i32*
2589 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[CONV10]], align 4
2590 // CHECK12-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
2591 // CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 8
2592 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
2593 // CHECK12-NEXT: [[CONV11:%.*]] = bitcast i64* [[C_CASTED]] to i32*
2594 // CHECK12-NEXT: store i32 [[TMP8]], i32* [[CONV11]], align 4
2595 // CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8
2596 // CHECK12-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8
2597 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64, [4 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], [4 x i32]* [[TMP10]])
2598 // CHECK12-NEXT: ret void
2599 //
2600 //
2601 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2
2602 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR2]] {
2603 // CHECK12-NEXT: entry:
2604 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2605 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2606 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
2607 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
2608 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
2609 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8
2610 // CHECK12-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 8
2611 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8
2612 // CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8
2613 // CHECK12-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 8
2614 // CHECK12-NEXT: [[E5:%.*]] = alloca [4 x i32], align 16
2615 // CHECK12-NEXT: [[_TMP6:%.*]] = alloca [4 x i32]*, align 8
2616 // CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, align 8
2617 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2618 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2619 // CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
2620 // CHECK12-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
2621 // CHECK12-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
2622 // CHECK12-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8
2623 // CHECK12-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 8
2624 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
2625 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2626 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
2627 // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32*
2628 // CHECK12-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 8
2629 // CHECK12-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8
2630 // CHECK12-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8
2631 // CHECK12-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP4]], align 8
2632 // CHECK12-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP4]], align 8
2633 // CHECK12-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8*
2634 // CHECK12-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8*
2635 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false)
2636 // CHECK12-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8
2637 // CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 0
2638 // CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8
2639 // CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 1
2640 // CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8
2641 // CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 2
2642 // CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4
2643 // CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 3
2644 // CHECK12-NEXT: store i8* bitcast (void (i8*)* @g_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8
2645 // CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4
2646 // CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.4 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8
2647 // CHECK12-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5
2648 // CHECK12-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8
2649 // CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6
2650 // CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8
2651 // CHECK12-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED]], align 8
2652 // CHECK12-NEXT: [[BLOCK_CAPTURED7:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8
2653 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
2654 // CHECK12-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED7]], align 8
2655 // CHECK12-NEXT: [[BLOCK_CAPTURED8:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7
2656 // CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP3]], align 8
2657 // CHECK12-NEXT: store i32* [[TMP7]], i32** [[BLOCK_CAPTURED8]], align 8
2658 // CHECK12-NEXT: [[TMP8:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()*
2659 // CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP8]] to %struct.__block_literal_generic*
2660 // CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3
2661 // CHECK12-NEXT: [[TMP10:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8*
2662 // CHECK12-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP9]], align 8
2663 // CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8* [[TMP11]] to void (i8*)*
2664 // CHECK12-NEXT: call void [[TMP12]](i8* [[TMP10]])
2665 // CHECK12-NEXT: ret void
2666 //
2667 //
2668 // CHECK12-LABEL: define {{[^@]+}}@g_block_invoke_2
2669 // CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] {
2670 // CHECK12-NEXT: entry:
2671 // CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
2672 // CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8
2673 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
2674 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
2675 // CHECK12-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8
2676 // CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
2677 // CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*
2678 // CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>** [[BLOCK_ADDR]], align 8
2679 // CHECK12-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5
2680 // CHECK12-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8
2681 // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6
2682 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8
2683 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2684 // CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
2685 // CHECK12-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
2686 // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8
2687 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 8
2688 // CHECK12-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1
2689 // CHECK12-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 8
2690 // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7
2691 // CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8
2692 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
2693 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1
2694 // CHECK12-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4
2695 // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6
2696 // CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 8
2697 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
2698 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2699 // CHECK12-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4
2700 // CHECK12-NEXT: [[TMP7:%.*]] = load i64, i64* [[A_CASTED]], align 8
2701 // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8
2702 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 8
2703 // CHECK12-NEXT: [[CONV5:%.*]] = bitcast i64* [[B_CASTED]] to i32*
2704 // CHECK12-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
2705 // CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[B_CASTED]], align 8
2706 // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR6:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7
2707 // CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR6]], align 8
2708 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
2709 // CHECK12-NEXT: [[CONV7:%.*]] = bitcast i64* [[C_CASTED]] to i32*
2710 // CHECK12-NEXT: store i32 [[TMP11]], i32* [[CONV7]], align 4
2711 // CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[C_CASTED]], align 8
2712 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SS* [[THIS]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP12]])
2713 // CHECK12-NEXT: ret void
2714 //
2715 //
2716 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3
2717 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR2]] {
2718 // CHECK12-NEXT: entry:
2719 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2720 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2721 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
2722 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
2723 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
2724 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8
2725 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8
2726 // CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8
2727 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2728 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2729 // CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
2730 // CHECK12-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
2731 // CHECK12-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
2732 // CHECK12-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8
2733 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
2734 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2735 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
2736 // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32*
2737 // CHECK12-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8
2738 // CHECK12-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8
2739 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8
2740 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
2741 // CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
2742 // CHECK12-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4
2743 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
2744 // CHECK12-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1
2745 // CHECK12-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
2746 // CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP3]], align 8
2747 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
2748 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1
2749 // CHECK12-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4
2750 // CHECK12-NEXT: ret void
2751 //
2752 //
2753 // CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe
2754 // CHECK17-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] {
2755 // CHECK17-NEXT: entry:
2756 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
2757 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8
2758 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
2759 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8
2760 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
2761 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
2762 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
2763 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
2764 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8
2765 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
2766 // CHECK17-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8
2767 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2768 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
2769 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
2770 // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
2771 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
2772 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
2773 // CHECK17-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave()
2774 // CHECK17-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8
2775 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]]
2776 // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128
2777 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8
2778 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
2779 // CHECK17-NEXT: [[TMP8:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8
2780 // CHECK17-NEXT: [[TMP9:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8
2781 // CHECK17-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8
2782 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i64, x86_fp80*, float*, i64, i64, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP8]], i32* [[N_ADDR]], i64 [[TMP1]], x86_fp80* [[TMP9]], float* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]])
2783 // CHECK17-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
2784 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP11]])
2785 // CHECK17-NEXT: ret void
2786 //
2787 //
2788 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
2789 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], float* [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2:[0-9]+]] {
2790 // CHECK17-NEXT: entry:
2791 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2792 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2793 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8
2794 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8
2795 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
2796 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8
2797 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
2798 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8
2799 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8
2800 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8
2801 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
2802 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
2803 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
2804 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2805 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2806 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8
2807 // CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8
2808 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2809 // CHECK17-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8
2810 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
2811 // CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8
2812 // CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8
2813 // CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8
2814 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8
2815 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2816 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8
2817 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8
2818 // CHECK17-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8
2819 // CHECK17-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave()
2820 // CHECK17-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 8
2821 // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]]
2822 // CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128
2823 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
2824 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8
2825 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]]
2826 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8
2827 // CHECK17-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8*
2828 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8*
2829 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i64 [[TMP8]], i1 false)
2830 // CHECK17-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8
2831 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i64 0
2832 // CHECK17-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8
2833 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4
2834 // CHECK17-NEXT: [[TMP14:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8
2835 // CHECK17-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 [[TMP13]], x86_fp80* [[TMP14]])
2836 // CHECK17-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
2837 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP15]])
2838 // CHECK17-NEXT: ret void
2839 //
2840 //
2841 // CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe
2842 // CHECK17-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] align 2 {
2843 // CHECK17-NEXT: entry:
2844 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
2845 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8
2846 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
2847 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8
2848 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
2849 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
2850 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
2851 // CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
2852 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8
2853 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
2854 // CHECK17-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8
2855 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
2856 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2857 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
2858 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
2859 // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
2860 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
2861 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
2862 // CHECK17-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave()
2863 // CHECK17-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8
2864 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]]
2865 // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128
2866 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8
2867 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
2868 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1
2869 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4
2870 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0
2871 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[A]], align 4
2872 // CHECK17-NEXT: [[TMP9:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8
2873 // CHECK17-NEXT: [[TMP10:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8
2874 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, x86_fp80*, %struct.St*, i64, i64, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], x86_fp80* [[TMP9]], %struct.St* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], i32* [[N_ADDR]], %struct.St* [[TMP10]])
2875 // CHECK17-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
2876 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP11]])
2877 // CHECK17-NEXT: ret void
2878 //
2879 //
2880 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1
2881 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] {
2882 // CHECK17-NEXT: entry:
2883 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2884 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2885 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
2886 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8
2887 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
2888 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8
2889 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8
2890 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8
2891 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8
2892 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8
2893 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2894 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2895 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2896 // CHECK17-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8
2897 // CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
2898 // CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8
2899 // CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8
2900 // CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8
2901 // CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8
2902 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8
2903 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2904 // CHECK17-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
2905 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8
2906 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8
2907 // CHECK17-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8
2908 // CHECK17-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 8
2909 // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]]
2910 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 8
2911 // CHECK17-NEXT: [[TMP8:%.*]] = add nuw i64 [[TMP7]], 127
2912 // CHECK17-NEXT: [[TMP9:%.*]] = udiv i64 [[TMP8]], 128
2913 // CHECK17-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP9]], 128
2914 // CHECK17-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2915 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
2916 // CHECK17-NEXT: [[DOTVLA2__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP12]], i64 [[TMP10]], i8* inttoptr (i64 8 to i8*))
2917 // CHECK17-NEXT: [[DOTVLA2__ADDR:%.*]] = bitcast i8* [[DOTVLA2__VOID_ADDR]] to double*
2918 // CHECK17-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]]
2919 // CHECK17-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8
2920 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast double* [[DOTVLA2__ADDR]] to i8*
2921 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast double* [[TMP4]] to i8*
2922 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP15]], i8* align 128 [[TMP16]], i64 [[TMP14]], i1 false)
2923 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1
2924 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[B]], align 4
2925 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0
2926 // CHECK17-NEXT: store i32 [[TMP17]], i32* [[A]], align 4
2927 // CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP17]] to double
2928 // CHECK17-NEXT: [[TMP18:%.*]] = mul nsw i64 1, [[TMP3]]
2929 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[DOTVLA2__ADDR]], i64 [[TMP18]]
2930 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP5]], align 4
2931 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP19]], 1
2932 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64
2933 // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]]
2934 // CHECK17-NEXT: store double [[CONV]], double* [[ARRAYIDX7]], align 8
2935 // CHECK17-NEXT: [[CONV8:%.*]] = fpext double [[CONV]] to x86_fp80
2936 // CHECK17-NEXT: [[TMP20:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8
2937 // CHECK17-NEXT: [[B9:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1
2938 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[B9]], align 4
2939 // CHECK17-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP21]] to i64
2940 // CHECK17-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP20]], i64 [[IDXPROM10]]
2941 // CHECK17-NEXT: store x86_fp80 [[CONV8]], x86_fp80* [[ARRAYIDX11]], align 16
2942 // CHECK17-NEXT: [[TMP22:%.*]] = bitcast double* [[DOTVLA2__ADDR]] to i8*
2943 // CHECK17-NEXT: call void @__kmpc_free(i32 [[TMP12]], i8* [[TMP22]], i8* inttoptr (i64 8 to i8*))
2944 // CHECK17-NEXT: ret void
2945 //
2946