1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test target codegen - host bc file has to be created first.
3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
4 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK
5 // expected-no-diagnostics
6 #ifndef HEADER
7 #define HEADER
8 
9 template<typename tx>
ftemplate(int n)10 tx ftemplate(int n) {
11   tx b[10];
12 
13   #pragma omp target
14   {
15     tx d = n;
16     #pragma omp parallel for
17     for(int i=0; i<10; i++) {
18       b[i] += d;
19     }
20     b[3] += 1;
21   }
22 
23   return b[3];
24 }
25 
bar(int n)26 int bar(int n){
27   int a = 0;
28 
29   a += ftemplate<int>(n);
30 
31   return a;
32 }
33 
34 #endif
35 // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l13
36 // CHECK-SAME: (i64 noundef [[N:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0:[0-9]+]] {
37 // CHECK-NEXT:  entry:
38 // CHECK-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
39 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
40 // CHECK-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x i8*], align 8
41 // CHECK-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
42 // CHECK-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
43 // CHECK-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
44 // CHECK-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
45 // CHECK-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)
46 // CHECK-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
47 // CHECK-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
48 // CHECK:       user_code.entry:
49 // CHECK-NEXT:    [[D:%.*]] = call align 8 i8* @__kmpc_alloc_shared(i64 4)
50 // CHECK-NEXT:    [[D_ON_STACK:%.*]] = bitcast i8* [[D]] to i32*
51 // CHECK-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
52 // CHECK-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
53 // CHECK-NEXT:    store i32 [[TMP3]], i32* [[D_ON_STACK]], align 4
54 // CHECK-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
55 // CHECK-NEXT:    [[TMP5:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
56 // CHECK-NEXT:    store i8* [[TMP5]], i8** [[TMP4]], align 8
57 // CHECK-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
58 // CHECK-NEXT:    [[TMP7:%.*]] = bitcast i32* [[D_ON_STACK]] to i8*
59 // CHECK-NEXT:    store i8* [[TMP7]], i8** [[TMP6]], align 8
60 // CHECK-NEXT:    [[TMP8:%.*]] = bitcast [2 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
61 // CHECK-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, [10 x i32]*, i32*)* @__omp_outlined__ to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8*), i8** [[TMP8]], i64 2)
62 // CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 3
63 // CHECK-NEXT:    [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
64 // CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP9]], 1
65 // CHECK-NEXT:    store i32 [[ADD]], i32* [[ARRAYIDX]], align 4
66 // CHECK-NEXT:    call void @__kmpc_free_shared(i8* [[D]], i64 4)
67 // CHECK-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
68 // CHECK-NEXT:    ret void
69 // CHECK:       worker.exit:
70 // CHECK-NEXT:    ret void
71 //
72 //
73 // CHECK-LABEL: define {{[^@]+}}@__omp_outlined__
74 // CHECK-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR2:[0-9]+]] {
75 // CHECK-NEXT:  entry:
76 // CHECK-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
77 // CHECK-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
78 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
79 // CHECK-NEXT:    [[D_ADDR:%.*]] = alloca i32*, align 8
80 // CHECK-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
81 // CHECK-NEXT:    [[TMP:%.*]] = alloca i32, align 4
82 // CHECK-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
83 // CHECK-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
84 // CHECK-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
85 // CHECK-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
86 // CHECK-NEXT:    [[I:%.*]] = alloca i32, align 4
87 // CHECK-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
88 // CHECK-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
89 // CHECK-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
90 // CHECK-NEXT:    store i32* [[D]], i32** [[D_ADDR]], align 8
91 // CHECK-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
92 // CHECK-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[D_ADDR]], align 8
93 // CHECK-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
94 // CHECK-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
95 // CHECK-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
96 // CHECK-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
97 // CHECK-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
98 // CHECK-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
99 // CHECK-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
100 // CHECK-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
101 // CHECK:       omp.dispatch.cond:
102 // CHECK-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
103 // CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
104 // CHECK-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
105 // CHECK:       cond.true:
106 // CHECK-NEXT:    br label [[COND_END:%.*]]
107 // CHECK:       cond.false:
108 // CHECK-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
109 // CHECK-NEXT:    br label [[COND_END]]
110 // CHECK:       cond.end:
111 // CHECK-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
112 // CHECK-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
113 // CHECK-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
114 // CHECK-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
115 // CHECK-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
116 // CHECK-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
117 // CHECK-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
118 // CHECK-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
119 // CHECK:       omp.dispatch.body:
120 // CHECK-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
121 // CHECK:       omp.inner.for.cond:
122 // CHECK-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
123 // CHECK-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
124 // CHECK-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
125 // CHECK-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
126 // CHECK:       omp.inner.for.body:
127 // CHECK-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
128 // CHECK-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
129 // CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
130 // CHECK-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
131 // CHECK-NEXT:    [[TMP12:%.*]] = load i32, i32* [[TMP1]], align 4
132 // CHECK-NEXT:    [[TMP13:%.*]] = load i32, i32* [[I]], align 4
133 // CHECK-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
134 // CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]]
135 // CHECK-NEXT:    [[TMP14:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
136 // CHECK-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP12]]
137 // CHECK-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
138 // CHECK-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
139 // CHECK:       omp.body.continue:
140 // CHECK-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
141 // CHECK:       omp.inner.for.inc:
142 // CHECK-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
143 // CHECK-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1
144 // CHECK-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
145 // CHECK-NEXT:    br label [[OMP_INNER_FOR_COND]]
146 // CHECK:       omp.inner.for.end:
147 // CHECK-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
148 // CHECK:       omp.dispatch.inc:
149 // CHECK-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
150 // CHECK-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
151 // CHECK-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
152 // CHECK-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_LB]], align 4
153 // CHECK-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
154 // CHECK-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
155 // CHECK-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
156 // CHECK-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_UB]], align 4
157 // CHECK-NEXT:    br label [[OMP_DISPATCH_COND]]
158 // CHECK:       omp.dispatch.end:
159 // CHECK-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]])
160 // CHECK-NEXT:    ret void
161 //
162 //
163 // CHECK-LABEL: define {{[^@]+}}@__omp_outlined___wrapper
164 // CHECK-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
165 // CHECK-NEXT:  entry:
166 // CHECK-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
167 // CHECK-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
168 // CHECK-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
169 // CHECK-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
170 // CHECK-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
171 // CHECK-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
172 // CHECK-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
173 // CHECK-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
174 // CHECK-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 8
175 // CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 0
176 // CHECK-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to [10 x i32]**
177 // CHECK-NEXT:    [[TMP5:%.*]] = load [10 x i32]*, [10 x i32]** [[TMP4]], align 8
178 // CHECK-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 1
179 // CHECK-NEXT:    [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32**
180 // CHECK-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[TMP7]], align 8
181 // CHECK-NEXT:    call void @__omp_outlined__(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP5]], i32* [[TMP8]]) #[[ATTR3:[0-9]+]]
182 // CHECK-NEXT:    ret void
183 //
184