1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 9 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -DOMP5 | FileCheck %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -DOMP5 11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -DOMP5| FileCheck %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -DOMP5 14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 19 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 20 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 22 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -DOMP5 | FileCheck %s --check-prefix=CHECK13 23 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -DOMP5 24 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK13 25 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -DOMP5 | FileCheck %s --check-prefix=CHECK15 26 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -DOMP5 27 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK15 28 29 // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) 30 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 31 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17 32 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 33 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 34 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 35 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK19 36 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 37 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 38 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -DOMP5 39 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK21 40 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -DOMP5 41 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK21 42 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -DOMP5 43 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK23 44 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -DOMP5 45 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK23 46 47 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 48 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 49 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 50 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 51 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 52 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 53 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 54 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 55 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -DOMP5 56 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK13 57 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -DOMP5 58 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK13 59 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -DOMP5 60 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK15 61 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -DOMP5 62 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK15 63 64 // expected-no-diagnostics 65 #ifndef HEADER 66 #define HEADER 67 68 69 void without_schedule_clause(float *a, float *b, float *c, float *d) { 70 #pragma omp target 71 #pragma omp teams 72 #ifdef OMP5 73 #pragma omp distribute simd simdlen(8) aligned(a) if(true) 74 #else 75 #pragma omp distribute simd simdlen(8) aligned(a) 76 #endif // OMP5 77 for (int i = 33; i < 32000000; i += 7) { 78 a[i] = b[i] * c[i] * d[i]; 79 } 80 } 81 82 // ... loop body ... 83 84 85 void static_not_chunked(float *a, float *b, float *c, float *d) { 86 #pragma omp target 87 #pragma omp teams 88 #ifdef OMP5 89 #pragma omp distribute simd dist_schedule(static) safelen(32) if(simd: true) nontemporal(a, b) 90 #else 91 #pragma omp distribute simd dist_schedule(static) safelen(32) 92 #endif // OMP5 93 for (int i = 32000000; i > 33; i += -7) { 94 a[i] = b[i] * c[i] * d[i]; 95 } 96 } 97 98 // ... loop body ... 99 100 101 102 void static_chunked(float *a, float *b, float *c, float *d) { 103 #pragma omp target 104 #pragma omp teams 105 #pragma omp distribute simd dist_schedule(static, 5) 106 for (unsigned i = 131071; i <= 2147483647; i += 127) { 107 a[i] = b[i] * c[i] * d[i]; 108 } 109 } 110 111 // ... loop body ... 112 113 void test_precond() { 114 char a = 0; char i; 115 #pragma omp target 116 #pragma omp teams 117 #ifdef OMP5 118 #pragma omp distribute simd linear(i) if(a) nontemporal(i) 119 #else 120 #pragma omp distribute simd linear(i) 121 #endif // OMP5 122 for(i = a; i < 10; ++i); 123 } 124 125 // a is passed as a parameter to the outlined functions 126 // ..many loads of %0.. 127 128 // no templates for now, as these require special handling in target regions and/or declare target 129 130 131 template <typename T> 132 T ftemplate() { 133 short aa = 0; 134 135 #pragma omp target 136 #pragma omp teams 137 #pragma omp distribute simd dist_schedule(static, aa) 138 for (int i = 0; i < 100; i++) { 139 } 140 return T(); 141 } 142 143 int fint(void) { return ftemplate<int>(); } 144 145 #endif 146 147 // CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 148 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 149 // CHECK1-NEXT: entry: 150 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 151 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 152 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 153 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 154 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 155 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 156 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 157 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 158 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 159 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 160 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 161 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 162 // CHECK1-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 163 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 164 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 165 // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 166 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 167 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 168 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 169 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 170 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 171 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 172 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 173 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 174 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 175 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 176 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 177 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 178 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 179 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 180 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 181 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 182 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 183 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 184 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 185 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 186 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 187 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 188 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 189 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 190 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 191 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 192 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 193 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 194 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 195 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 196 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 197 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 198 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 199 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 200 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424) 201 // CHECK1-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 202 // CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 203 // CHECK1-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 204 // CHECK1: omp_offload.failed: 205 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3:[0-9]+]] 206 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 207 // CHECK1: omp_offload.cont: 208 // CHECK1-NEXT: ret void 209 // 210 // 211 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 212 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { 213 // CHECK1-NEXT: entry: 214 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 215 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 216 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 217 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 218 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 219 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 220 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 221 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 222 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 223 // CHECK1-NEXT: ret void 224 // 225 // 226 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 227 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 228 // CHECK1-NEXT: entry: 229 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 230 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 231 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 232 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 233 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 234 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 235 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 236 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 237 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 238 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 239 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 240 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 241 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 242 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 243 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 244 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 245 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 246 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 247 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 248 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 249 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 250 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 251 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 252 // CHECK1-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 8 253 // CHECK1-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i64 16) ] 254 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 255 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 256 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 257 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 258 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 259 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 260 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 261 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 262 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 263 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 264 // CHECK1: cond.true: 265 // CHECK1-NEXT: br label [[COND_END:%.*]] 266 // CHECK1: cond.false: 267 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 268 // CHECK1-NEXT: br label [[COND_END]] 269 // CHECK1: cond.end: 270 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 271 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 272 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 273 // CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 274 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 275 // CHECK1: omp.inner.for.cond: 276 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 277 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 278 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 279 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 280 // CHECK1: omp.inner.for.body: 281 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 282 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 283 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 284 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 285 // CHECK1-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !8 286 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8 287 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 288 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]] 289 // CHECK1-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !8 290 // CHECK1-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !8 291 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8 292 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64 293 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM2]] 294 // CHECK1-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !8 295 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]] 296 // CHECK1-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !8 297 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8 298 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64 299 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM5]] 300 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !llvm.access.group !8 301 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]] 302 // CHECK1-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !8 303 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8 304 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64 305 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM8]] 306 // CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !8 307 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 308 // CHECK1: omp.body.continue: 309 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 310 // CHECK1: omp.inner.for.inc: 311 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 312 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 313 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 314 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 315 // CHECK1: omp.inner.for.end: 316 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 317 // CHECK1: omp.loop.exit: 318 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]]) 319 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 320 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 321 // CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 322 // CHECK1: .omp.final.then: 323 // CHECK1-NEXT: store i32 32000001, i32* [[I]], align 4 324 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 325 // CHECK1: .omp.final.done: 326 // CHECK1-NEXT: ret void 327 // 328 // 329 // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 330 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 331 // CHECK1-NEXT: entry: 332 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 333 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 334 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 335 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 336 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 337 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 338 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 339 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 340 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 341 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 342 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 343 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 344 // CHECK1-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 345 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 346 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 347 // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 348 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 349 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 350 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 351 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 352 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 353 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 354 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 355 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 356 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 357 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 358 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 359 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 360 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 361 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 362 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 363 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 364 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 365 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 366 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 367 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 368 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 369 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 370 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 371 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 372 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 373 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 374 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 375 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 376 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 377 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 378 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 379 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 380 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 381 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 382 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424) 383 // CHECK1-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 384 // CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 385 // CHECK1-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 386 // CHECK1: omp_offload.failed: 387 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]] 388 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 389 // CHECK1: omp_offload.cont: 390 // CHECK1-NEXT: ret void 391 // 392 // 393 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 394 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { 395 // CHECK1-NEXT: entry: 396 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 397 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 398 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 399 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 400 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 401 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 402 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 403 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 404 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 405 // CHECK1-NEXT: ret void 406 // 407 // 408 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 409 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 410 // CHECK1-NEXT: entry: 411 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 412 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 413 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 414 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 415 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 416 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 417 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 418 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 419 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 420 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 421 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 422 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 423 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 424 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 425 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 426 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 427 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 428 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 429 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 430 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 431 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 432 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 433 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 434 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 435 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 436 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 437 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 438 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 439 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 440 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 441 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 442 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 443 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 444 // CHECK1: cond.true: 445 // CHECK1-NEXT: br label [[COND_END:%.*]] 446 // CHECK1: cond.false: 447 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 448 // CHECK1-NEXT: br label [[COND_END]] 449 // CHECK1: cond.end: 450 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 451 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 452 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 453 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 454 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 455 // CHECK1: omp.inner.for.cond: 456 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 457 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 458 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 459 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 460 // CHECK1: omp.inner.for.body: 461 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 462 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 463 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 464 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4 465 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 466 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 467 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 468 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 469 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 470 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 471 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 472 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 473 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 474 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 475 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 476 // CHECK1-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 477 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 478 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 479 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 480 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 481 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 482 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 483 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 484 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 485 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 486 // CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 487 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 488 // CHECK1: omp.body.continue: 489 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 490 // CHECK1: omp.inner.for.inc: 491 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 492 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 493 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 494 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 495 // CHECK1: omp.inner.for.end: 496 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 497 // CHECK1: omp.loop.exit: 498 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 499 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 500 // CHECK1-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 501 // CHECK1-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 502 // CHECK1: .omp.final.then: 503 // CHECK1-NEXT: store i32 32, i32* [[I]], align 4 504 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 505 // CHECK1: .omp.final.done: 506 // CHECK1-NEXT: ret void 507 // 508 // 509 // CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 510 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 511 // CHECK1-NEXT: entry: 512 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 513 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 514 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 515 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 516 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 517 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 518 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 519 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 520 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 521 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 522 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 523 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 524 // CHECK1-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 525 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 526 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 527 // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 528 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 529 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 530 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 531 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 532 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 533 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 534 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 535 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 536 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 537 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 538 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 539 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 540 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 541 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 542 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 543 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 544 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 545 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 546 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 547 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 548 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 549 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 550 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 551 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 552 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 553 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 554 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 555 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 556 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 557 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 558 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 559 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 560 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 561 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 562 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289) 563 // CHECK1-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 564 // CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 565 // CHECK1-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 566 // CHECK1: omp_offload.failed: 567 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]] 568 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 569 // CHECK1: omp_offload.cont: 570 // CHECK1-NEXT: ret void 571 // 572 // 573 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 574 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { 575 // CHECK1-NEXT: entry: 576 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 577 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 578 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 579 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 580 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 581 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 582 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 583 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 584 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 585 // CHECK1-NEXT: ret void 586 // 587 // 588 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 589 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 590 // CHECK1-NEXT: entry: 591 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 592 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 593 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 594 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 595 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 596 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 597 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 598 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 599 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 600 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 601 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 602 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 603 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 604 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 605 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 606 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 607 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 608 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 609 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 610 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 611 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 612 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 613 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 614 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 615 // CHECK1-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 616 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 617 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 618 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 619 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 620 // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 621 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 622 // CHECK1: omp.dispatch.cond: 623 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 624 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 625 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 626 // CHECK1: cond.true: 627 // CHECK1-NEXT: br label [[COND_END:%.*]] 628 // CHECK1: cond.false: 629 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 630 // CHECK1-NEXT: br label [[COND_END]] 631 // CHECK1: cond.end: 632 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 633 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 634 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 635 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 636 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 637 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 638 // CHECK1-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 639 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 640 // CHECK1: omp.dispatch.body: 641 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 642 // CHECK1: omp.inner.for.cond: 643 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 644 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 645 // CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 646 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 647 // CHECK1: omp.inner.for.body: 648 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 649 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 650 // CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 651 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 652 // CHECK1-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !17 653 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 654 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 655 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 656 // CHECK1-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !17 657 // CHECK1-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !17 658 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 659 // CHECK1-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 660 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 661 // CHECK1-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !17 662 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 663 // CHECK1-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !17 664 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 665 // CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 666 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 667 // CHECK1-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !17 668 // CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 669 // CHECK1-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !17 670 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 671 // CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 672 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 673 // CHECK1-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !17 674 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 675 // CHECK1: omp.body.continue: 676 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 677 // CHECK1: omp.inner.for.inc: 678 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 679 // CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 680 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 681 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 682 // CHECK1: omp.inner.for.end: 683 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 684 // CHECK1: omp.dispatch.inc: 685 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 686 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 687 // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 688 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 689 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 690 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 691 // CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 692 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 693 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 694 // CHECK1: omp.dispatch.end: 695 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 696 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 697 // CHECK1-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 698 // CHECK1-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 699 // CHECK1: .omp.final.then: 700 // CHECK1-NEXT: store i32 -2147483522, i32* [[I]], align 4 701 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 702 // CHECK1: .omp.final.done: 703 // CHECK1-NEXT: ret void 704 // 705 // 706 // CHECK1-LABEL: define {{[^@]+}}@_Z12test_precondv 707 // CHECK1-SAME: () #[[ATTR0]] { 708 // CHECK1-NEXT: entry: 709 // CHECK1-NEXT: [[A:%.*]] = alloca i8, align 1 710 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1 711 // CHECK1-NEXT: [[I_CASTED:%.*]] = alloca i64, align 8 712 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 713 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8 714 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8 715 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8 716 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 717 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 718 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 719 // CHECK1-NEXT: store i8 0, i8* [[A]], align 1 720 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1 721 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[I_CASTED]] to i8* 722 // CHECK1-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 723 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[I_CASTED]], align 8 724 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[A]], align 1 725 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i8* 726 // CHECK1-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1 727 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8 728 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 729 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 730 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 731 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 732 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* 733 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8 734 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 735 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 736 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 737 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 738 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 739 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 740 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 741 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 742 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 743 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 744 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 745 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 746 // CHECK1-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 747 // CHECK1-NEXT: store i8 [[TMP16]], i8* [[DOTCAPTURE_EXPR_]], align 1 748 // CHECK1-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 749 // CHECK1-NEXT: [[CONV3:%.*]] = sext i8 [[TMP17]] to i32 750 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV3]] 751 // CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 752 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 753 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 754 // CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1 755 // CHECK1-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 756 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 757 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 758 // CHECK1-NEXT: [[TMP19:%.*]] = zext i32 [[ADD6]] to i64 759 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP19]]) 760 // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, i32 2, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 761 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 762 // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 763 // CHECK1: omp_offload.failed: 764 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i64 [[TMP1]], i64 [[TMP3]]) #[[ATTR3]] 765 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 766 // CHECK1: omp_offload.cont: 767 // CHECK1-NEXT: ret void 768 // 769 // 770 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 771 // CHECK1-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 772 // CHECK1-NEXT: entry: 773 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 774 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 775 // CHECK1-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 776 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 777 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i8* 778 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i8* 779 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]]) 780 // CHECK1-NEXT: ret void 781 // 782 // 783 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 784 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 785 // CHECK1-NEXT: entry: 786 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 787 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 788 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 8 789 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 790 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 791 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 792 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 793 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 794 // CHECK1-NEXT: [[I4:%.*]] = alloca i8, align 1 795 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 796 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 797 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 798 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 799 // CHECK1-NEXT: [[I6:%.*]] = alloca i8, align 1 800 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 801 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 802 // CHECK1-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 8 803 // CHECK1-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 804 // CHECK1-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 8 805 // CHECK1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 8 806 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1 807 // CHECK1-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1 808 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 809 // CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 810 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 811 // CHECK1-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 812 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 813 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 814 // CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 815 // CHECK1-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 816 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 817 // CHECK1-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1 818 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 819 // CHECK1-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 820 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 821 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 822 // CHECK1: omp.precond.then: 823 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 824 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 825 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 826 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 827 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 828 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 829 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 830 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 831 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 832 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 833 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] 834 // CHECK1-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 835 // CHECK1: cond.true: 836 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 837 // CHECK1-NEXT: br label [[COND_END:%.*]] 838 // CHECK1: cond.false: 839 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 840 // CHECK1-NEXT: br label [[COND_END]] 841 // CHECK1: cond.end: 842 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 843 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 844 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 845 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 846 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 847 // CHECK1: omp.inner.for.cond: 848 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 849 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20 850 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 851 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 852 // CHECK1: omp.inner.for.body: 853 // CHECK1-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !20 854 // CHECK1-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32 855 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 856 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 857 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 858 // CHECK1-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 859 // CHECK1-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !20 860 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 861 // CHECK1: omp.body.continue: 862 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 863 // CHECK1: omp.inner.for.inc: 864 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 865 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 866 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 867 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 868 // CHECK1: omp.inner.for.end: 869 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 870 // CHECK1: omp.loop.exit: 871 // CHECK1-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 872 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 873 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) 874 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 875 // CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 876 // CHECK1-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 877 // CHECK1: .omp.final.then: 878 // CHECK1-NEXT: [[TMP23:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 879 // CHECK1-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32 880 // CHECK1-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 881 // CHECK1-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32 882 // CHECK1-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]] 883 // CHECK1-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1 884 // CHECK1-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1 885 // CHECK1-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1 886 // CHECK1-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1 887 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]] 888 // CHECK1-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 889 // CHECK1-NEXT: store i8 [[CONV21]], i8* [[TMP0]], align 1 890 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 891 // CHECK1: .omp.final.done: 892 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 893 // CHECK1: omp.precond.end: 894 // CHECK1-NEXT: ret void 895 // 896 // 897 // CHECK1-LABEL: define {{[^@]+}}@_Z4fintv 898 // CHECK1-SAME: () #[[ATTR0]] { 899 // CHECK1-NEXT: entry: 900 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() 901 // CHECK1-NEXT: ret i32 [[CALL]] 902 // 903 // 904 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 905 // CHECK1-SAME: () #[[ATTR0]] comdat { 906 // CHECK1-NEXT: entry: 907 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 908 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 909 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 910 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 911 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 912 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 913 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 914 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2 915 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 916 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2 917 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 918 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 919 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 920 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 921 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 922 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 923 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 924 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 925 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8 926 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 927 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 928 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100) 929 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 930 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 931 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 932 // CHECK1: omp_offload.failed: 933 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i64 [[TMP1]]) #[[ATTR3]] 934 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 935 // CHECK1: omp_offload.cont: 936 // CHECK1-NEXT: ret i32 0 937 // 938 // 939 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 940 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] { 941 // CHECK1-NEXT: entry: 942 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 943 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 944 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 945 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]]) 946 // CHECK1-NEXT: ret void 947 // 948 // 949 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 950 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 951 // CHECK1-NEXT: entry: 952 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 953 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 954 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 955 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 956 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 957 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 958 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 959 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 960 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 961 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 962 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 963 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 964 // CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 965 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 966 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 967 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 968 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 969 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 970 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 971 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 972 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 973 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 974 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 975 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 976 // CHECK1: omp.dispatch.cond: 977 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 978 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 979 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 980 // CHECK1: cond.true: 981 // CHECK1-NEXT: br label [[COND_END:%.*]] 982 // CHECK1: cond.false: 983 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 984 // CHECK1-NEXT: br label [[COND_END]] 985 // CHECK1: cond.end: 986 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 987 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 988 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 989 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 990 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 991 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 992 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 993 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 994 // CHECK1: omp.dispatch.body: 995 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 996 // CHECK1: omp.inner.for.cond: 997 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 998 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 999 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1000 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1001 // CHECK1: omp.inner.for.body: 1002 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 1003 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 1004 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1005 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 1006 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1007 // CHECK1: omp.body.continue: 1008 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1009 // CHECK1: omp.inner.for.inc: 1010 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 1011 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 1012 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 1013 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] 1014 // CHECK1: omp.inner.for.end: 1015 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1016 // CHECK1: omp.dispatch.inc: 1017 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1018 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1019 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 1020 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 1021 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1022 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1023 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 1024 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 1025 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1026 // CHECK1: omp.dispatch.end: 1027 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 1028 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1029 // CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 1030 // CHECK1-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1031 // CHECK1: .omp.final.then: 1032 // CHECK1-NEXT: store i32 100, i32* [[I]], align 4 1033 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1034 // CHECK1: .omp.final.done: 1035 // CHECK1-NEXT: ret void 1036 // 1037 // 1038 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1039 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 1040 // CHECK1-NEXT: entry: 1041 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1042 // CHECK1-NEXT: ret void 1043 // 1044 // 1045 // CHECK3-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 1046 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 1047 // CHECK3-NEXT: entry: 1048 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1049 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1050 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1051 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1052 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 1053 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 1054 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 1055 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1056 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1057 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1058 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1059 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1060 // CHECK3-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 1061 // CHECK3-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 1062 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 1063 // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 1064 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1065 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 1066 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 1067 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1068 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 1069 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 1070 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1071 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 1072 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1073 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 1074 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 1075 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1076 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 1077 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 1078 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1079 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 1080 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1081 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 1082 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 1083 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1084 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 1085 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 1086 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1087 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 1088 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1089 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 1090 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 1091 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1092 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 1093 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 1094 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1095 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1096 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1097 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1098 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424) 1099 // CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1100 // CHECK3-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 1101 // CHECK3-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1102 // CHECK3: omp_offload.failed: 1103 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3:[0-9]+]] 1104 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1105 // CHECK3: omp_offload.cont: 1106 // CHECK3-NEXT: ret void 1107 // 1108 // 1109 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 1110 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { 1111 // CHECK3-NEXT: entry: 1112 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1113 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1114 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1115 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1116 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1117 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1118 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1119 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1120 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1121 // CHECK3-NEXT: ret void 1122 // 1123 // 1124 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1125 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 1126 // CHECK3-NEXT: entry: 1127 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1128 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1129 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 1130 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 1131 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 1132 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 1133 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1134 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1135 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1136 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1137 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1138 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1139 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1140 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1141 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1142 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 1143 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 1144 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 1145 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 1146 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 1147 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 1148 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 1149 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 1150 // CHECK3-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 4 1151 // CHECK3-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i32 16) ] 1152 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1153 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1154 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1155 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1156 // CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1157 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 1158 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1159 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1160 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 1161 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1162 // CHECK3: cond.true: 1163 // CHECK3-NEXT: br label [[COND_END:%.*]] 1164 // CHECK3: cond.false: 1165 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1166 // CHECK3-NEXT: br label [[COND_END]] 1167 // CHECK3: cond.end: 1168 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 1169 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1170 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1171 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 1172 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1173 // CHECK3: omp.inner.for.cond: 1174 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 1175 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 1176 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 1177 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1178 // CHECK3: omp.inner.for.body: 1179 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 1180 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 1181 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 1182 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 1183 // CHECK3-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !9 1184 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 1185 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]] 1186 // CHECK3-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 1187 // CHECK3-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !9 1188 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 1189 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP16]], i32 [[TMP17]] 1190 // CHECK3-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !9 1191 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]] 1192 // CHECK3-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !9 1193 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 1194 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP19]], i32 [[TMP20]] 1195 // CHECK3-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !9 1196 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]] 1197 // CHECK3-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !9 1198 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 1199 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP22]], i32 [[TMP23]] 1200 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !9 1201 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1202 // CHECK3: omp.body.continue: 1203 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1204 // CHECK3: omp.inner.for.inc: 1205 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 1206 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1 1207 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 1208 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 1209 // CHECK3: omp.inner.for.end: 1210 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1211 // CHECK3: omp.loop.exit: 1212 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]]) 1213 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1214 // CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 1215 // CHECK3-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1216 // CHECK3: .omp.final.then: 1217 // CHECK3-NEXT: store i32 32000001, i32* [[I]], align 4 1218 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1219 // CHECK3: .omp.final.done: 1220 // CHECK3-NEXT: ret void 1221 // 1222 // 1223 // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 1224 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 1225 // CHECK3-NEXT: entry: 1226 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1227 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1228 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1229 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1230 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 1231 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 1232 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 1233 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1234 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1235 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1236 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1237 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1238 // CHECK3-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 1239 // CHECK3-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 1240 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 1241 // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 1242 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1243 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 1244 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 1245 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1246 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 1247 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 1248 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1249 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 1250 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1251 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 1252 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 1253 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1254 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 1255 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 1256 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1257 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 1258 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1259 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 1260 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 1261 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1262 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 1263 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 1264 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1265 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 1266 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1267 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 1268 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 1269 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1270 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 1271 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 1272 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1273 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1274 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1275 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1276 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424) 1277 // CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1278 // CHECK3-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 1279 // CHECK3-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1280 // CHECK3: omp_offload.failed: 1281 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]] 1282 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1283 // CHECK3: omp_offload.cont: 1284 // CHECK3-NEXT: ret void 1285 // 1286 // 1287 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 1288 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { 1289 // CHECK3-NEXT: entry: 1290 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1291 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1292 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1293 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1294 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1295 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1296 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1297 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1298 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1299 // CHECK3-NEXT: ret void 1300 // 1301 // 1302 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 1303 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 1304 // CHECK3-NEXT: entry: 1305 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1306 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1307 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 1308 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 1309 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 1310 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 1311 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1312 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1313 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1314 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1315 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1316 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1317 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1318 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1319 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1320 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 1321 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 1322 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 1323 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 1324 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 1325 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 1326 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 1327 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 1328 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1329 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1330 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1331 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1332 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1333 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1334 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1335 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1336 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 1337 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1338 // CHECK3: cond.true: 1339 // CHECK3-NEXT: br label [[COND_END:%.*]] 1340 // CHECK3: cond.false: 1341 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1342 // CHECK3-NEXT: br label [[COND_END]] 1343 // CHECK3: cond.end: 1344 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1345 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1346 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1347 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1348 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1349 // CHECK3: omp.inner.for.cond: 1350 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1351 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1352 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1353 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1354 // CHECK3: omp.inner.for.body: 1355 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1356 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 1357 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 1358 // CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4 1359 // CHECK3-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 1360 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1361 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 1362 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 1363 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 1364 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1365 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 1366 // CHECK3-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 1367 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 1368 // CHECK3-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 1369 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 1370 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 1371 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 1372 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 1373 // CHECK3-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 1374 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 1375 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 1376 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 1377 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1378 // CHECK3: omp.body.continue: 1379 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1380 // CHECK3: omp.inner.for.inc: 1381 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1382 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 1383 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1384 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 1385 // CHECK3: omp.inner.for.end: 1386 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1387 // CHECK3: omp.loop.exit: 1388 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1389 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1390 // CHECK3-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 1391 // CHECK3-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1392 // CHECK3: .omp.final.then: 1393 // CHECK3-NEXT: store i32 32, i32* [[I]], align 4 1394 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1395 // CHECK3: .omp.final.done: 1396 // CHECK3-NEXT: ret void 1397 // 1398 // 1399 // CHECK3-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 1400 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 1401 // CHECK3-NEXT: entry: 1402 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1403 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1404 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1405 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1406 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 1407 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 1408 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 1409 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1410 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1411 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1412 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1413 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1414 // CHECK3-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 1415 // CHECK3-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 1416 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 1417 // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 1418 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1419 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 1420 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 1421 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1422 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 1423 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 1424 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1425 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 1426 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1427 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 1428 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 1429 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1430 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 1431 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 1432 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1433 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 1434 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1435 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 1436 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 1437 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1438 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 1439 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 1440 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1441 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 1442 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1443 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 1444 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 1445 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1446 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 1447 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 1448 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1449 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1450 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1451 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1452 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289) 1453 // CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1454 // CHECK3-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 1455 // CHECK3-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1456 // CHECK3: omp_offload.failed: 1457 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]] 1458 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1459 // CHECK3: omp_offload.cont: 1460 // CHECK3-NEXT: ret void 1461 // 1462 // 1463 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 1464 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { 1465 // CHECK3-NEXT: entry: 1466 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 1467 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 1468 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 1469 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 1470 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 1471 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 1472 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 1473 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 1474 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1475 // CHECK3-NEXT: ret void 1476 // 1477 // 1478 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 1479 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 1480 // CHECK3-NEXT: entry: 1481 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1482 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1483 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 1484 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 1485 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 1486 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 1487 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1488 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1489 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1490 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1491 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1492 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1493 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1494 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1495 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1496 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 1497 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 1498 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 1499 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 1500 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 1501 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 1502 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 1503 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 1504 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1505 // CHECK3-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 1506 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1507 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1508 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1509 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1510 // CHECK3-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 1511 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1512 // CHECK3: omp.dispatch.cond: 1513 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1514 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 1515 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1516 // CHECK3: cond.true: 1517 // CHECK3-NEXT: br label [[COND_END:%.*]] 1518 // CHECK3: cond.false: 1519 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1520 // CHECK3-NEXT: br label [[COND_END]] 1521 // CHECK3: cond.end: 1522 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1523 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1524 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1525 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1526 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1527 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1528 // CHECK3-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 1529 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1530 // CHECK3: omp.dispatch.body: 1531 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1532 // CHECK3: omp.inner.for.cond: 1533 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 1534 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 1535 // CHECK3-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 1536 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1537 // CHECK3: omp.inner.for.body: 1538 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 1539 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 1540 // CHECK3-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 1541 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 1542 // CHECK3-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !18 1543 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 1544 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] 1545 // CHECK3-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !18 1546 // CHECK3-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !18 1547 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 1548 // CHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] 1549 // CHECK3-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !18 1550 // CHECK3-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] 1551 // CHECK3-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !18 1552 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 1553 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] 1554 // CHECK3-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !18 1555 // CHECK3-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] 1556 // CHECK3-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !18 1557 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 1558 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] 1559 // CHECK3-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !18 1560 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1561 // CHECK3: omp.body.continue: 1562 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1563 // CHECK3: omp.inner.for.inc: 1564 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 1565 // CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 1566 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 1567 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 1568 // CHECK3: omp.inner.for.end: 1569 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1570 // CHECK3: omp.dispatch.inc: 1571 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1572 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1573 // CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] 1574 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 1575 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1576 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1577 // CHECK3-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] 1578 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 1579 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 1580 // CHECK3: omp.dispatch.end: 1581 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1582 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1583 // CHECK3-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 1584 // CHECK3-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1585 // CHECK3: .omp.final.then: 1586 // CHECK3-NEXT: store i32 -2147483522, i32* [[I]], align 4 1587 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1588 // CHECK3: .omp.final.done: 1589 // CHECK3-NEXT: ret void 1590 // 1591 // 1592 // CHECK3-LABEL: define {{[^@]+}}@_Z12test_precondv 1593 // CHECK3-SAME: () #[[ATTR0]] { 1594 // CHECK3-NEXT: entry: 1595 // CHECK3-NEXT: [[A:%.*]] = alloca i8, align 1 1596 // CHECK3-NEXT: [[I:%.*]] = alloca i8, align 1 1597 // CHECK3-NEXT: [[I_CASTED:%.*]] = alloca i32, align 4 1598 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1599 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4 1600 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4 1601 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4 1602 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 1603 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1604 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1605 // CHECK3-NEXT: store i8 0, i8* [[A]], align 1 1606 // CHECK3-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1 1607 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[I_CASTED]] to i8* 1608 // CHECK3-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 1609 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I_CASTED]], align 4 1610 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[A]], align 1 1611 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_CASTED]] to i8* 1612 // CHECK3-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1 1613 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4 1614 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1615 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 1616 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 1617 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1618 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* 1619 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4 1620 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1621 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 1622 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1623 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 1624 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 1625 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1626 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 1627 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 1628 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1629 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 1630 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1631 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1632 // CHECK3-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 1633 // CHECK3-NEXT: store i8 [[TMP16]], i8* [[DOTCAPTURE_EXPR_]], align 1 1634 // CHECK3-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1635 // CHECK3-NEXT: [[CONV3:%.*]] = sext i8 [[TMP17]] to i32 1636 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV3]] 1637 // CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 1638 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 1639 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1640 // CHECK3-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1 1641 // CHECK3-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1642 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1643 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 1644 // CHECK3-NEXT: [[TMP19:%.*]] = zext i32 [[ADD6]] to i64 1645 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP19]]) 1646 // CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, i32 2, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1647 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 1648 // CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1649 // CHECK3: omp_offload.failed: 1650 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i32 [[TMP1]], i32 [[TMP3]]) #[[ATTR3]] 1651 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1652 // CHECK3: omp_offload.cont: 1653 // CHECK3-NEXT: ret void 1654 // 1655 // 1656 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 1657 // CHECK3-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 1658 // CHECK3-NEXT: entry: 1659 // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 1660 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1661 // CHECK3-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 1662 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1663 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[I_ADDR]] to i8* 1664 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_ADDR]] to i8* 1665 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]]) 1666 // CHECK3-NEXT: ret void 1667 // 1668 // 1669 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 1670 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 1671 // CHECK3-NEXT: entry: 1672 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1673 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1674 // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 4 1675 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 1676 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1677 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 1678 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1679 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1680 // CHECK3-NEXT: [[I4:%.*]] = alloca i8, align 1 1681 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1682 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1683 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1684 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1685 // CHECK3-NEXT: [[I6:%.*]] = alloca i8, align 1 1686 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1687 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1688 // CHECK3-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 4 1689 // CHECK3-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 1690 // CHECK3-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 4 1691 // CHECK3-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 4 1692 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1 1693 // CHECK3-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1 1694 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1695 // CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 1696 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 1697 // CHECK3-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 1698 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 1699 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1700 // CHECK3-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 1701 // CHECK3-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 1702 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1703 // CHECK3-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1 1704 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1705 // CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 1706 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 1707 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1708 // CHECK3: omp.precond.then: 1709 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1710 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1711 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 1712 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1713 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1714 // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1715 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 1716 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1717 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1718 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1719 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] 1720 // CHECK3-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1721 // CHECK3: cond.true: 1722 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1723 // CHECK3-NEXT: br label [[COND_END:%.*]] 1724 // CHECK3: cond.false: 1725 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1726 // CHECK3-NEXT: br label [[COND_END]] 1727 // CHECK3: cond.end: 1728 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 1729 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1730 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1731 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 1732 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1733 // CHECK3: omp.inner.for.cond: 1734 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 1735 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 1736 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 1737 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1738 // CHECK3: omp.inner.for.body: 1739 // CHECK3-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21 1740 // CHECK3-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32 1741 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 1742 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 1743 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 1744 // CHECK3-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 1745 // CHECK3-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !21 1746 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1747 // CHECK3: omp.body.continue: 1748 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1749 // CHECK3: omp.inner.for.inc: 1750 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 1751 // CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 1752 // CHECK3-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 1753 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 1754 // CHECK3: omp.inner.for.end: 1755 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1756 // CHECK3: omp.loop.exit: 1757 // CHECK3-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1758 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 1759 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) 1760 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1761 // CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 1762 // CHECK3-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1763 // CHECK3: .omp.final.then: 1764 // CHECK3-NEXT: [[TMP23:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1765 // CHECK3-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32 1766 // CHECK3-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1767 // CHECK3-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32 1768 // CHECK3-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]] 1769 // CHECK3-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1 1770 // CHECK3-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1 1771 // CHECK3-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1 1772 // CHECK3-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1 1773 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]] 1774 // CHECK3-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 1775 // CHECK3-NEXT: store i8 [[CONV21]], i8* [[TMP0]], align 1 1776 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1777 // CHECK3: .omp.final.done: 1778 // CHECK3-NEXT: br label [[OMP_PRECOND_END]] 1779 // CHECK3: omp.precond.end: 1780 // CHECK3-NEXT: ret void 1781 // 1782 // 1783 // CHECK3-LABEL: define {{[^@]+}}@_Z4fintv 1784 // CHECK3-SAME: () #[[ATTR0]] { 1785 // CHECK3-NEXT: entry: 1786 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() 1787 // CHECK3-NEXT: ret i32 [[CALL]] 1788 // 1789 // 1790 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 1791 // CHECK3-SAME: () #[[ATTR0]] comdat { 1792 // CHECK3-NEXT: entry: 1793 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 1794 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1795 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1796 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1797 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1798 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1799 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 1800 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2 1801 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 1802 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2 1803 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 1804 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1805 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 1806 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 1807 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1808 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 1809 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 1810 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1811 // CHECK3-NEXT: store i8* null, i8** [[TMP6]], align 4 1812 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1813 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1814 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100) 1815 // CHECK3-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1816 // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 1817 // CHECK3-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1818 // CHECK3: omp_offload.failed: 1819 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i32 [[TMP1]]) #[[ATTR3]] 1820 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1821 // CHECK3: omp_offload.cont: 1822 // CHECK3-NEXT: ret i32 0 1823 // 1824 // 1825 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 1826 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] { 1827 // CHECK3-NEXT: entry: 1828 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 1829 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 1830 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 1831 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]]) 1832 // CHECK3-NEXT: ret void 1833 // 1834 // 1835 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 1836 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 1837 // CHECK3-NEXT: entry: 1838 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1839 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1840 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 1841 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1842 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1843 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1844 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1845 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1846 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1847 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1848 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1849 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1850 // CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 1851 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 1852 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1853 // CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 1854 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1855 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1856 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 1857 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 1858 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1859 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 1860 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 1861 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1862 // CHECK3: omp.dispatch.cond: 1863 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1864 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 1865 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1866 // CHECK3: cond.true: 1867 // CHECK3-NEXT: br label [[COND_END:%.*]] 1868 // CHECK3: cond.false: 1869 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1870 // CHECK3-NEXT: br label [[COND_END]] 1871 // CHECK3: cond.end: 1872 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1873 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1874 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1875 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 1876 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1877 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1878 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1879 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1880 // CHECK3: omp.dispatch.body: 1881 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1882 // CHECK3: omp.inner.for.cond: 1883 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 1884 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 1885 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1886 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1887 // CHECK3: omp.inner.for.body: 1888 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 1889 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 1890 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1891 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 1892 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1893 // CHECK3: omp.body.continue: 1894 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1895 // CHECK3: omp.inner.for.inc: 1896 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 1897 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 1898 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 1899 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 1900 // CHECK3: omp.inner.for.end: 1901 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1902 // CHECK3: omp.dispatch.inc: 1903 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1904 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1905 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 1906 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 1907 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1908 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1909 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 1910 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 1911 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 1912 // CHECK3: omp.dispatch.end: 1913 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 1914 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1915 // CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 1916 // CHECK3-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1917 // CHECK3: .omp.final.then: 1918 // CHECK3-NEXT: store i32 100, i32* [[I]], align 4 1919 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1920 // CHECK3: .omp.final.done: 1921 // CHECK3-NEXT: ret void 1922 // 1923 // 1924 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1925 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 1926 // CHECK3-NEXT: entry: 1927 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 1928 // CHECK3-NEXT: ret void 1929 // 1930 // 1931 // CHECK5-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 1932 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 1933 // CHECK5-NEXT: entry: 1934 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1935 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1936 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1937 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1938 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1939 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1940 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1941 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1942 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1943 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1944 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1945 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1946 // CHECK5-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 1947 // CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 1948 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 1949 // CHECK5-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 1950 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1951 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 1952 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 1953 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1954 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 1955 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 1956 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1957 // CHECK5-NEXT: store i8* null, i8** [[TMP8]], align 8 1958 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1959 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 1960 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 1961 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1962 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 1963 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 1964 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1965 // CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8 1966 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1967 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 1968 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 1969 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1970 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 1971 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 1972 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1973 // CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8 1974 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1975 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 1976 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 1977 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1978 // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 1979 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 1980 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1981 // CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 1982 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1983 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1984 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424) 1985 // CHECK5-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1986 // CHECK5-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 1987 // CHECK5-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1988 // CHECK5: omp_offload.failed: 1989 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3:[0-9]+]] 1990 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 1991 // CHECK5: omp_offload.cont: 1992 // CHECK5-NEXT: ret void 1993 // 1994 // 1995 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 1996 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { 1997 // CHECK5-NEXT: entry: 1998 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1999 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2000 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2001 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2002 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2003 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2004 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2005 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2006 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2007 // CHECK5-NEXT: ret void 2008 // 2009 // 2010 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. 2011 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 2012 // CHECK5-NEXT: entry: 2013 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2014 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2015 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2016 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 2017 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 2018 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 2019 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2020 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2021 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2022 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2023 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2024 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2025 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2026 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2027 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2028 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2029 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 2030 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 2031 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 2032 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 2033 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 2034 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 2035 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 2036 // CHECK5-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 8 2037 // CHECK5-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i64 16) ] 2038 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2039 // CHECK5-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 2040 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2041 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2042 // CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2043 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 2044 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2045 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2046 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 2047 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2048 // CHECK5: cond.true: 2049 // CHECK5-NEXT: br label [[COND_END:%.*]] 2050 // CHECK5: cond.false: 2051 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2052 // CHECK5-NEXT: br label [[COND_END]] 2053 // CHECK5: cond.end: 2054 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 2055 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2056 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2057 // CHECK5-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 2058 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2059 // CHECK5: omp.inner.for.cond: 2060 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 2061 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 2062 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 2063 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2064 // CHECK5: omp.inner.for.body: 2065 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 2066 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 2067 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 2068 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 2069 // CHECK5-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !8 2070 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8 2071 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 2072 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]] 2073 // CHECK5-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !8 2074 // CHECK5-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !8 2075 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8 2076 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64 2077 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM2]] 2078 // CHECK5-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !8 2079 // CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]] 2080 // CHECK5-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !8 2081 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8 2082 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64 2083 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM5]] 2084 // CHECK5-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !llvm.access.group !8 2085 // CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]] 2086 // CHECK5-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !8 2087 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8 2088 // CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64 2089 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM8]] 2090 // CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !8 2091 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2092 // CHECK5: omp.body.continue: 2093 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2094 // CHECK5: omp.inner.for.inc: 2095 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 2096 // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 2097 // CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 2098 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 2099 // CHECK5: omp.inner.for.end: 2100 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2101 // CHECK5: omp.loop.exit: 2102 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]]) 2103 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2104 // CHECK5-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 2105 // CHECK5-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2106 // CHECK5: .omp.final.then: 2107 // CHECK5-NEXT: store i32 32000001, i32* [[I]], align 4 2108 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2109 // CHECK5: .omp.final.done: 2110 // CHECK5-NEXT: ret void 2111 // 2112 // 2113 // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 2114 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 2115 // CHECK5-NEXT: entry: 2116 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2117 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2118 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2119 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2120 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 2121 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 2122 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 2123 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2124 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2125 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2126 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2127 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2128 // CHECK5-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 2129 // CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 2130 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 2131 // CHECK5-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 2132 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2133 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 2134 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 2135 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2136 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 2137 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 2138 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2139 // CHECK5-NEXT: store i8* null, i8** [[TMP8]], align 8 2140 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2141 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 2142 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 2143 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2144 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 2145 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 2146 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2147 // CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8 2148 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2149 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 2150 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 2151 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2152 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 2153 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 2154 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2155 // CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8 2156 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2157 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 2158 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 2159 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2160 // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 2161 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 2162 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 2163 // CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 2164 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2165 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2166 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424) 2167 // CHECK5-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2168 // CHECK5-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 2169 // CHECK5-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2170 // CHECK5: omp_offload.failed: 2171 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]] 2172 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 2173 // CHECK5: omp_offload.cont: 2174 // CHECK5-NEXT: ret void 2175 // 2176 // 2177 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 2178 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { 2179 // CHECK5-NEXT: entry: 2180 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2181 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2182 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2183 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2184 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2185 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2186 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2187 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2188 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2189 // CHECK5-NEXT: ret void 2190 // 2191 // 2192 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 2193 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 2194 // CHECK5-NEXT: entry: 2195 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2196 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2197 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2198 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 2199 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 2200 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 2201 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2202 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2203 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2204 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2205 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2206 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2207 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2208 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2209 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2210 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2211 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 2212 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 2213 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 2214 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 2215 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 2216 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 2217 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 2218 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2219 // CHECK5-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 2220 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2221 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2222 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2223 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2224 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2225 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2226 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 2227 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2228 // CHECK5: cond.true: 2229 // CHECK5-NEXT: br label [[COND_END:%.*]] 2230 // CHECK5: cond.false: 2231 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2232 // CHECK5-NEXT: br label [[COND_END]] 2233 // CHECK5: cond.end: 2234 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2235 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2236 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2237 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2238 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2239 // CHECK5: omp.inner.for.cond: 2240 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2241 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2242 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2243 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2244 // CHECK5: omp.inner.for.body: 2245 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2246 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 2247 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 2248 // CHECK5-NEXT: store i32 [[SUB]], i32* [[I]], align 4 2249 // CHECK5-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8, !nontemporal !15 2250 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 2251 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 2252 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 2253 // CHECK5-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 2254 // CHECK5-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 2255 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 2256 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 2257 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 2258 // CHECK5-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 2259 // CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 2260 // CHECK5-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 2261 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 2262 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 2263 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 2264 // CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 2265 // CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 2266 // CHECK5-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8, !nontemporal !15 2267 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 2268 // CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 2269 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 2270 // CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 2271 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2272 // CHECK5: omp.body.continue: 2273 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2274 // CHECK5: omp.inner.for.inc: 2275 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2276 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 2277 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 2278 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 2279 // CHECK5: omp.inner.for.end: 2280 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2281 // CHECK5: omp.loop.exit: 2282 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2283 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2284 // CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 2285 // CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2286 // CHECK5: .omp.final.then: 2287 // CHECK5-NEXT: store i32 32, i32* [[I]], align 4 2288 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2289 // CHECK5: .omp.final.done: 2290 // CHECK5-NEXT: ret void 2291 // 2292 // 2293 // CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 2294 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 2295 // CHECK5-NEXT: entry: 2296 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2297 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2298 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2299 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2300 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 2301 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 2302 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 2303 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2304 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2305 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2306 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2307 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2308 // CHECK5-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8 2309 // CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 2310 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8 2311 // CHECK5-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8 2312 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2313 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 2314 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8 2315 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2316 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 2317 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8 2318 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2319 // CHECK5-NEXT: store i8* null, i8** [[TMP8]], align 8 2320 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2321 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 2322 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8 2323 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2324 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 2325 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8 2326 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2327 // CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8 2328 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2329 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 2330 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8 2331 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2332 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 2333 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8 2334 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2335 // CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8 2336 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2337 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 2338 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8 2339 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2340 // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 2341 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8 2342 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 2343 // CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 2344 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2345 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2346 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289) 2347 // CHECK5-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2348 // CHECK5-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 2349 // CHECK5-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2350 // CHECK5: omp_offload.failed: 2351 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]] 2352 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 2353 // CHECK5: omp_offload.cont: 2354 // CHECK5-NEXT: ret void 2355 // 2356 // 2357 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 2358 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { 2359 // CHECK5-NEXT: entry: 2360 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2361 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2362 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2363 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2364 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2365 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2366 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2367 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2368 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2369 // CHECK5-NEXT: ret void 2370 // 2371 // 2372 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 2373 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 2374 // CHECK5-NEXT: entry: 2375 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2376 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2377 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2378 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 2379 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 2380 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 2381 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2382 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2383 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2384 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2385 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2386 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2387 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2388 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2389 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2390 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2391 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 2392 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 2393 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 2394 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 2395 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 2396 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 2397 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 2398 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2399 // CHECK5-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 2400 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2401 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2402 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2403 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2404 // CHECK5-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 2405 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2406 // CHECK5: omp.dispatch.cond: 2407 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2408 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 2409 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2410 // CHECK5: cond.true: 2411 // CHECK5-NEXT: br label [[COND_END:%.*]] 2412 // CHECK5: cond.false: 2413 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2414 // CHECK5-NEXT: br label [[COND_END]] 2415 // CHECK5: cond.end: 2416 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2417 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2418 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2419 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2420 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2421 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2422 // CHECK5-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 2423 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2424 // CHECK5: omp.dispatch.body: 2425 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2426 // CHECK5: omp.inner.for.cond: 2427 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 2428 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 2429 // CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 2430 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2431 // CHECK5: omp.inner.for.body: 2432 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 2433 // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 2434 // CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 2435 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 2436 // CHECK5-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !18 2437 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 2438 // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 2439 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 2440 // CHECK5-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !18 2441 // CHECK5-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !18 2442 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 2443 // CHECK5-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 2444 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 2445 // CHECK5-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !18 2446 // CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 2447 // CHECK5-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !18 2448 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 2449 // CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 2450 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 2451 // CHECK5-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !18 2452 // CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 2453 // CHECK5-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !18 2454 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 2455 // CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 2456 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 2457 // CHECK5-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !18 2458 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2459 // CHECK5: omp.body.continue: 2460 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2461 // CHECK5: omp.inner.for.inc: 2462 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 2463 // CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 2464 // CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 2465 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 2466 // CHECK5: omp.inner.for.end: 2467 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2468 // CHECK5: omp.dispatch.inc: 2469 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2470 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2471 // CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 2472 // CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 2473 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2474 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2475 // CHECK5-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 2476 // CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 2477 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] 2478 // CHECK5: omp.dispatch.end: 2479 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2480 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2481 // CHECK5-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 2482 // CHECK5-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2483 // CHECK5: .omp.final.then: 2484 // CHECK5-NEXT: store i32 -2147483522, i32* [[I]], align 4 2485 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2486 // CHECK5: .omp.final.done: 2487 // CHECK5-NEXT: ret void 2488 // 2489 // 2490 // CHECK5-LABEL: define {{[^@]+}}@_Z12test_precondv 2491 // CHECK5-SAME: () #[[ATTR0]] { 2492 // CHECK5-NEXT: entry: 2493 // CHECK5-NEXT: [[A:%.*]] = alloca i8, align 1 2494 // CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1 2495 // CHECK5-NEXT: [[I_CASTED:%.*]] = alloca i64, align 8 2496 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2497 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8 2498 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8 2499 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8 2500 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1 2501 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2502 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 2503 // CHECK5-NEXT: store i8 0, i8* [[A]], align 1 2504 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1 2505 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[I_CASTED]] to i8* 2506 // CHECK5-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 2507 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[I_CASTED]], align 8 2508 // CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[A]], align 1 2509 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i8* 2510 // CHECK5-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1 2511 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8 2512 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2513 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 2514 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 2515 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2516 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* 2517 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8 2518 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2519 // CHECK5-NEXT: store i8* null, i8** [[TMP8]], align 8 2520 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2521 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 2522 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 2523 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2524 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 2525 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 2526 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2527 // CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8 2528 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2529 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2530 // CHECK5-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 2531 // CHECK5-NEXT: store i8 [[TMP16]], i8* [[DOTCAPTURE_EXPR_]], align 1 2532 // CHECK5-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2533 // CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP17]] to i32 2534 // CHECK5-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV3]] 2535 // CHECK5-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 2536 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 2537 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2538 // CHECK5-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1 2539 // CHECK5-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 2540 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 2541 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 2542 // CHECK5-NEXT: [[TMP19:%.*]] = zext i32 [[ADD6]] to i64 2543 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP19]]) 2544 // CHECK5-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, i32 2, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2545 // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 2546 // CHECK5-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2547 // CHECK5: omp_offload.failed: 2548 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i64 [[TMP1]], i64 [[TMP3]]) #[[ATTR3]] 2549 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 2550 // CHECK5: omp_offload.cont: 2551 // CHECK5-NEXT: ret void 2552 // 2553 // 2554 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 2555 // CHECK5-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 2556 // CHECK5-NEXT: entry: 2557 // CHECK5-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 2558 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2559 // CHECK5-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 2560 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2561 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i8* 2562 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i8* 2563 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]]) 2564 // CHECK5-NEXT: ret void 2565 // 2566 // 2567 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 2568 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 2569 // CHECK5-NEXT: entry: 2570 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2571 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2572 // CHECK5-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 8 2573 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 2574 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2575 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1 2576 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2577 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2578 // CHECK5-NEXT: [[I4:%.*]] = alloca i8, align 1 2579 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2580 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2581 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2582 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2583 // CHECK5-NEXT: [[I6:%.*]] = alloca i8, align 1 2584 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2585 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2586 // CHECK5-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 8 2587 // CHECK5-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 2588 // CHECK5-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 8 2589 // CHECK5-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 8 2590 // CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1 2591 // CHECK5-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1 2592 // CHECK5-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2593 // CHECK5-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 2594 // CHECK5-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 2595 // CHECK5-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 2596 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 2597 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2598 // CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 2599 // CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2600 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2601 // CHECK5-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1 2602 // CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2603 // CHECK5-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 2604 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 2605 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2606 // CHECK5: omp.precond.then: 2607 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2608 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2609 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 2610 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2611 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2612 // CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2613 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 2614 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2615 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2616 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2617 // CHECK5-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] 2618 // CHECK5-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2619 // CHECK5: cond.true: 2620 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2621 // CHECK5-NEXT: br label [[COND_END:%.*]] 2622 // CHECK5: cond.false: 2623 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2624 // CHECK5-NEXT: br label [[COND_END]] 2625 // CHECK5: cond.end: 2626 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 2627 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2628 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2629 // CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 2630 // CHECK5-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP1]], align 1 2631 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0 2632 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2633 // CHECK5: omp_if.then: 2634 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2635 // CHECK5: omp.inner.for.cond: 2636 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 2637 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 2638 // CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 2639 // CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2640 // CHECK5: omp.inner.for.body: 2641 // CHECK5-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21 2642 // CHECK5-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32 2643 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 2644 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 2645 // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 2646 // CHECK5-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 2647 // CHECK5-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !15, !llvm.access.group !21 2648 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2649 // CHECK5: omp.body.continue: 2650 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2651 // CHECK5: omp.inner.for.inc: 2652 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 2653 // CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 2654 // CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 2655 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 2656 // CHECK5: omp.inner.for.end: 2657 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 2658 // CHECK5: omp_if.else: 2659 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 2660 // CHECK5: omp.inner.for.cond13: 2661 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2662 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2663 // CHECK5-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] 2664 // CHECK5-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]] 2665 // CHECK5: omp.inner.for.body15: 2666 // CHECK5-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2667 // CHECK5-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32 2668 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2669 // CHECK5-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1 2670 // CHECK5-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]] 2671 // CHECK5-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 2672 // CHECK5-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1 2673 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]] 2674 // CHECK5: omp.body.continue20: 2675 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]] 2676 // CHECK5: omp.inner.for.inc21: 2677 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2678 // CHECK5-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1 2679 // CHECK5-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4 2680 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP24:![0-9]+]] 2681 // CHECK5: omp.inner.for.end23: 2682 // CHECK5-NEXT: br label [[OMP_IF_END]] 2683 // CHECK5: omp_if.end: 2684 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2685 // CHECK5: omp.loop.exit: 2686 // CHECK5-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2687 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 2688 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 2689 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2690 // CHECK5-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 2691 // CHECK5-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2692 // CHECK5: .omp.final.then: 2693 // CHECK5-NEXT: [[TMP29:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2694 // CHECK5-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32 2695 // CHECK5-NEXT: [[TMP30:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2696 // CHECK5-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32 2697 // CHECK5-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]] 2698 // CHECK5-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1 2699 // CHECK5-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1 2700 // CHECK5-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1 2701 // CHECK5-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1 2702 // CHECK5-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]] 2703 // CHECK5-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8 2704 // CHECK5-NEXT: store i8 [[CONV32]], i8* [[TMP0]], align 1 2705 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2706 // CHECK5: .omp.final.done: 2707 // CHECK5-NEXT: br label [[OMP_PRECOND_END]] 2708 // CHECK5: omp.precond.end: 2709 // CHECK5-NEXT: ret void 2710 // 2711 // 2712 // CHECK5-LABEL: define {{[^@]+}}@_Z4fintv 2713 // CHECK5-SAME: () #[[ATTR0]] { 2714 // CHECK5-NEXT: entry: 2715 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() 2716 // CHECK5-NEXT: ret i32 [[CALL]] 2717 // 2718 // 2719 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 2720 // CHECK5-SAME: () #[[ATTR0]] comdat { 2721 // CHECK5-NEXT: entry: 2722 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 2723 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2724 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 2725 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 2726 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 2727 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2728 // CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 2729 // CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2 2730 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2731 // CHECK5-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2 2732 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2733 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2734 // CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 2735 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 2736 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2737 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 2738 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 2739 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2740 // CHECK5-NEXT: store i8* null, i8** [[TMP6]], align 8 2741 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2742 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2743 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100) 2744 // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2745 // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 2746 // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2747 // CHECK5: omp_offload.failed: 2748 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i64 [[TMP1]]) #[[ATTR3]] 2749 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 2750 // CHECK5: omp_offload.cont: 2751 // CHECK5-NEXT: ret i32 0 2752 // 2753 // 2754 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 2755 // CHECK5-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] { 2756 // CHECK5-NEXT: entry: 2757 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2758 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2759 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2760 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]]) 2761 // CHECK5-NEXT: ret void 2762 // 2763 // 2764 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 2765 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 2766 // CHECK5-NEXT: entry: 2767 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2768 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2769 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 2770 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2771 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2772 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2773 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2774 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2775 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2776 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2777 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2778 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2779 // CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 2780 // CHECK5-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 2781 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2782 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 2783 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2784 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2785 // CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 2786 // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 2787 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2788 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2789 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 2790 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2791 // CHECK5: omp.dispatch.cond: 2792 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2793 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 2794 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2795 // CHECK5: cond.true: 2796 // CHECK5-NEXT: br label [[COND_END:%.*]] 2797 // CHECK5: cond.false: 2798 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2799 // CHECK5-NEXT: br label [[COND_END]] 2800 // CHECK5: cond.end: 2801 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2802 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2803 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2804 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 2805 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2806 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2807 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2808 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2809 // CHECK5: omp.dispatch.body: 2810 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2811 // CHECK5: omp.inner.for.cond: 2812 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 2813 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !26 2814 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2815 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2816 // CHECK5: omp.inner.for.body: 2817 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 2818 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 2819 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2820 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !26 2821 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2822 // CHECK5: omp.body.continue: 2823 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2824 // CHECK5: omp.inner.for.inc: 2825 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 2826 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 2827 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 2828 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] 2829 // CHECK5: omp.inner.for.end: 2830 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2831 // CHECK5: omp.dispatch.inc: 2832 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2833 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2834 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 2835 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 2836 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2837 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2838 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 2839 // CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 2840 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] 2841 // CHECK5: omp.dispatch.end: 2842 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 2843 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2844 // CHECK5-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 2845 // CHECK5-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2846 // CHECK5: .omp.final.then: 2847 // CHECK5-NEXT: store i32 100, i32* [[I]], align 4 2848 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 2849 // CHECK5: .omp.final.done: 2850 // CHECK5-NEXT: ret void 2851 // 2852 // 2853 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2854 // CHECK5-SAME: () #[[ATTR4:[0-9]+]] { 2855 // CHECK5-NEXT: entry: 2856 // CHECK5-NEXT: call void @__tgt_register_requires(i64 1) 2857 // CHECK5-NEXT: ret void 2858 // 2859 // 2860 // CHECK7-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 2861 // CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 2862 // CHECK7-NEXT: entry: 2863 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2864 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 2865 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 2866 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 2867 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2868 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2869 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2870 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 2871 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2872 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 2873 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 2874 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 2875 // CHECK7-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 2876 // CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 2877 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 2878 // CHECK7-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 2879 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2880 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 2881 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 2882 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2883 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 2884 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 2885 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2886 // CHECK7-NEXT: store i8* null, i8** [[TMP8]], align 4 2887 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2888 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 2889 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 2890 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2891 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 2892 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 2893 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2894 // CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4 2895 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2896 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 2897 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 2898 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2899 // CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 2900 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 2901 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2902 // CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4 2903 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2904 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 2905 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 2906 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2907 // CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 2908 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 2909 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2910 // CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 2911 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2912 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2913 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424) 2914 // CHECK7-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2915 // CHECK7-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 2916 // CHECK7-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2917 // CHECK7: omp_offload.failed: 2918 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3:[0-9]+]] 2919 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 2920 // CHECK7: omp_offload.cont: 2921 // CHECK7-NEXT: ret void 2922 // 2923 // 2924 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 2925 // CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { 2926 // CHECK7-NEXT: entry: 2927 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2928 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 2929 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 2930 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 2931 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2932 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 2933 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 2934 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 2935 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2936 // CHECK7-NEXT: ret void 2937 // 2938 // 2939 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. 2940 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 2941 // CHECK7-NEXT: entry: 2942 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2943 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2944 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 2945 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 2946 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 2947 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 2948 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2949 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 2950 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2951 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2952 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2953 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2954 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2955 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2956 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2957 // CHECK7-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 2958 // CHECK7-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 2959 // CHECK7-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 2960 // CHECK7-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 2961 // CHECK7-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 2962 // CHECK7-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 2963 // CHECK7-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 2964 // CHECK7-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 2965 // CHECK7-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 4 2966 // CHECK7-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i32 16) ] 2967 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2968 // CHECK7-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 2969 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2970 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2971 // CHECK7-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2972 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 2973 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2974 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2975 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 2976 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2977 // CHECK7: cond.true: 2978 // CHECK7-NEXT: br label [[COND_END:%.*]] 2979 // CHECK7: cond.false: 2980 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2981 // CHECK7-NEXT: br label [[COND_END]] 2982 // CHECK7: cond.end: 2983 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 2984 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2985 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2986 // CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 2987 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2988 // CHECK7: omp.inner.for.cond: 2989 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 2990 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 2991 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 2992 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2993 // CHECK7: omp.inner.for.body: 2994 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 2995 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 2996 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 2997 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 2998 // CHECK7-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !9 2999 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 3000 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]] 3001 // CHECK7-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 3002 // CHECK7-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !9 3003 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 3004 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP16]], i32 [[TMP17]] 3005 // CHECK7-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !9 3006 // CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]] 3007 // CHECK7-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !9 3008 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 3009 // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP19]], i32 [[TMP20]] 3010 // CHECK7-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !9 3011 // CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]] 3012 // CHECK7-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !9 3013 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 3014 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP22]], i32 [[TMP23]] 3015 // CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !9 3016 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3017 // CHECK7: omp.body.continue: 3018 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3019 // CHECK7: omp.inner.for.inc: 3020 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 3021 // CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1 3022 // CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 3023 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 3024 // CHECK7: omp.inner.for.end: 3025 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3026 // CHECK7: omp.loop.exit: 3027 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]]) 3028 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3029 // CHECK7-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 3030 // CHECK7-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3031 // CHECK7: .omp.final.then: 3032 // CHECK7-NEXT: store i32 32000001, i32* [[I]], align 4 3033 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 3034 // CHECK7: .omp.final.done: 3035 // CHECK7-NEXT: ret void 3036 // 3037 // 3038 // CHECK7-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 3039 // CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 3040 // CHECK7-NEXT: entry: 3041 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 3042 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 3043 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 3044 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 3045 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 3046 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 3047 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 3048 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 3049 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 3050 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 3051 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 3052 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 3053 // CHECK7-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 3054 // CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 3055 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 3056 // CHECK7-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 3057 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3058 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 3059 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 3060 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3061 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 3062 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 3063 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3064 // CHECK7-NEXT: store i8* null, i8** [[TMP8]], align 4 3065 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3066 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 3067 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 3068 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3069 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 3070 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 3071 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3072 // CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4 3073 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3074 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 3075 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 3076 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3077 // CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 3078 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 3079 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3080 // CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4 3081 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3082 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 3083 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 3084 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3085 // CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 3086 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 3087 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3088 // CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 3089 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3090 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3091 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424) 3092 // CHECK7-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 3093 // CHECK7-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 3094 // CHECK7-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3095 // CHECK7: omp_offload.failed: 3096 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]] 3097 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 3098 // CHECK7: omp_offload.cont: 3099 // CHECK7-NEXT: ret void 3100 // 3101 // 3102 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 3103 // CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { 3104 // CHECK7-NEXT: entry: 3105 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 3106 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 3107 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 3108 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 3109 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 3110 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 3111 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 3112 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 3113 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 3114 // CHECK7-NEXT: ret void 3115 // 3116 // 3117 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 3118 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 3119 // CHECK7-NEXT: entry: 3120 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3121 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3122 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 3123 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 3124 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 3125 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 3126 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3127 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 3128 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3129 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3130 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3131 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3132 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 3133 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3134 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3135 // CHECK7-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 3136 // CHECK7-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 3137 // CHECK7-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 3138 // CHECK7-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 3139 // CHECK7-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 3140 // CHECK7-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 3141 // CHECK7-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 3142 // CHECK7-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 3143 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3144 // CHECK7-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 3145 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3146 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3147 // CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3148 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3149 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3150 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3151 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 3152 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3153 // CHECK7: cond.true: 3154 // CHECK7-NEXT: br label [[COND_END:%.*]] 3155 // CHECK7: cond.false: 3156 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3157 // CHECK7-NEXT: br label [[COND_END]] 3158 // CHECK7: cond.end: 3159 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3160 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3161 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3162 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 3163 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3164 // CHECK7: omp.inner.for.cond: 3165 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3166 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3167 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 3168 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3169 // CHECK7: omp.inner.for.body: 3170 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3171 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 3172 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 3173 // CHECK7-NEXT: store i32 [[SUB]], i32* [[I]], align 4 3174 // CHECK7-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4, !nontemporal !16 3175 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 3176 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 3177 // CHECK7-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 3178 // CHECK7-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 3179 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 3180 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 3181 // CHECK7-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 3182 // CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 3183 // CHECK7-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 3184 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 3185 // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 3186 // CHECK7-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 3187 // CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 3188 // CHECK7-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4, !nontemporal !16 3189 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 3190 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 3191 // CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 3192 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3193 // CHECK7: omp.body.continue: 3194 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3195 // CHECK7: omp.inner.for.inc: 3196 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3197 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 3198 // CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 3199 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] 3200 // CHECK7: omp.inner.for.end: 3201 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3202 // CHECK7: omp.loop.exit: 3203 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 3204 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3205 // CHECK7-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 3206 // CHECK7-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3207 // CHECK7: .omp.final.then: 3208 // CHECK7-NEXT: store i32 32, i32* [[I]], align 4 3209 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 3210 // CHECK7: .omp.final.done: 3211 // CHECK7-NEXT: ret void 3212 // 3213 // 3214 // CHECK7-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 3215 // CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 3216 // CHECK7-NEXT: entry: 3217 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 3218 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 3219 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 3220 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 3221 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 3222 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 3223 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 3224 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 3225 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 3226 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 3227 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 3228 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 3229 // CHECK7-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4 3230 // CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 3231 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4 3232 // CHECK7-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4 3233 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3234 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float** 3235 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4 3236 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3237 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float** 3238 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4 3239 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3240 // CHECK7-NEXT: store i8* null, i8** [[TMP8]], align 4 3241 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3242 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float** 3243 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4 3244 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3245 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float** 3246 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4 3247 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3248 // CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4 3249 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3250 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 3251 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4 3252 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3253 // CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 3254 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4 3255 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3256 // CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4 3257 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3258 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float** 3259 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4 3260 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3261 // CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 3262 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4 3263 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3264 // CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 3265 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3266 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3267 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289) 3268 // CHECK7-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 3269 // CHECK7-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 3270 // CHECK7-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3271 // CHECK7: omp_offload.failed: 3272 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]] 3273 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 3274 // CHECK7: omp_offload.cont: 3275 // CHECK7-NEXT: ret void 3276 // 3277 // 3278 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 3279 // CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { 3280 // CHECK7-NEXT: entry: 3281 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 3282 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 3283 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 3284 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 3285 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 3286 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 3287 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 3288 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 3289 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 3290 // CHECK7-NEXT: ret void 3291 // 3292 // 3293 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 3294 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { 3295 // CHECK7-NEXT: entry: 3296 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3297 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3298 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 3299 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 3300 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 3301 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 3302 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3303 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 3304 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3305 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3306 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3307 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3308 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 3309 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3310 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3311 // CHECK7-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 3312 // CHECK7-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 3313 // CHECK7-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 3314 // CHECK7-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 3315 // CHECK7-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 3316 // CHECK7-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 3317 // CHECK7-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 3318 // CHECK7-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 3319 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3320 // CHECK7-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 3321 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3322 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3323 // CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3324 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3325 // CHECK7-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 3326 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3327 // CHECK7: omp.dispatch.cond: 3328 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3329 // CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 3330 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3331 // CHECK7: cond.true: 3332 // CHECK7-NEXT: br label [[COND_END:%.*]] 3333 // CHECK7: cond.false: 3334 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3335 // CHECK7-NEXT: br label [[COND_END]] 3336 // CHECK7: cond.end: 3337 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3338 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3339 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3340 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 3341 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3342 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3343 // CHECK7-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 3344 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3345 // CHECK7: omp.dispatch.body: 3346 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3347 // CHECK7: omp.inner.for.cond: 3348 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 3349 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 3350 // CHECK7-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 3351 // CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3352 // CHECK7: omp.inner.for.body: 3353 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 3354 // CHECK7-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 3355 // CHECK7-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 3356 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 3357 // CHECK7-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !19 3358 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 3359 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] 3360 // CHECK7-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !19 3361 // CHECK7-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !19 3362 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 3363 // CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] 3364 // CHECK7-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !19 3365 // CHECK7-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] 3366 // CHECK7-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !19 3367 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 3368 // CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] 3369 // CHECK7-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !19 3370 // CHECK7-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] 3371 // CHECK7-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !19 3372 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 3373 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] 3374 // CHECK7-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !19 3375 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3376 // CHECK7: omp.body.continue: 3377 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3378 // CHECK7: omp.inner.for.inc: 3379 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 3380 // CHECK7-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 3381 // CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 3382 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 3383 // CHECK7: omp.inner.for.end: 3384 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3385 // CHECK7: omp.dispatch.inc: 3386 // CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3387 // CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3388 // CHECK7-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] 3389 // CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 3390 // CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3391 // CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3392 // CHECK7-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] 3393 // CHECK7-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 3394 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] 3395 // CHECK7: omp.dispatch.end: 3396 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 3397 // CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3398 // CHECK7-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 3399 // CHECK7-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3400 // CHECK7: .omp.final.then: 3401 // CHECK7-NEXT: store i32 -2147483522, i32* [[I]], align 4 3402 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 3403 // CHECK7: .omp.final.done: 3404 // CHECK7-NEXT: ret void 3405 // 3406 // 3407 // CHECK7-LABEL: define {{[^@]+}}@_Z12test_precondv 3408 // CHECK7-SAME: () #[[ATTR0]] { 3409 // CHECK7-NEXT: entry: 3410 // CHECK7-NEXT: [[A:%.*]] = alloca i8, align 1 3411 // CHECK7-NEXT: [[I:%.*]] = alloca i8, align 1 3412 // CHECK7-NEXT: [[I_CASTED:%.*]] = alloca i32, align 4 3413 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3414 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4 3415 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4 3416 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4 3417 // CHECK7-NEXT: [[TMP:%.*]] = alloca i8, align 1 3418 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 3419 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3420 // CHECK7-NEXT: store i8 0, i8* [[A]], align 1 3421 // CHECK7-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1 3422 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[I_CASTED]] to i8* 3423 // CHECK7-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1 3424 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I_CASTED]], align 4 3425 // CHECK7-NEXT: [[TMP2:%.*]] = load i8, i8* [[A]], align 1 3426 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_CASTED]] to i8* 3427 // CHECK7-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1 3428 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4 3429 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3430 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 3431 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 3432 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3433 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* 3434 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4 3435 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3436 // CHECK7-NEXT: store i8* null, i8** [[TMP8]], align 4 3437 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3438 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 3439 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 3440 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3441 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 3442 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 3443 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3444 // CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4 3445 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3446 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3447 // CHECK7-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 3448 // CHECK7-NEXT: store i8 [[TMP16]], i8* [[DOTCAPTURE_EXPR_]], align 1 3449 // CHECK7-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3450 // CHECK7-NEXT: [[CONV3:%.*]] = sext i8 [[TMP17]] to i32 3451 // CHECK7-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV3]] 3452 // CHECK7-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 3453 // CHECK7-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 3454 // CHECK7-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3455 // CHECK7-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1 3456 // CHECK7-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 3457 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3458 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 3459 // CHECK7-NEXT: [[TMP19:%.*]] = zext i32 [[ADD6]] to i64 3460 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP19]]) 3461 // CHECK7-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, i32 2, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 3462 // CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 3463 // CHECK7-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3464 // CHECK7: omp_offload.failed: 3465 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i32 [[TMP1]], i32 [[TMP3]]) #[[ATTR3]] 3466 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 3467 // CHECK7: omp_offload.cont: 3468 // CHECK7-NEXT: ret void 3469 // 3470 // 3471 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 3472 // CHECK7-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 3473 // CHECK7-NEXT: entry: 3474 // CHECK7-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 3475 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3476 // CHECK7-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 3477 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3478 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[I_ADDR]] to i8* 3479 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_ADDR]] to i8* 3480 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]]) 3481 // CHECK7-NEXT: ret void 3482 // 3483 // 3484 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 3485 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { 3486 // CHECK7-NEXT: entry: 3487 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3488 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3489 // CHECK7-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 4 3490 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 3491 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3492 // CHECK7-NEXT: [[TMP:%.*]] = alloca i8, align 1 3493 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 3494 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3495 // CHECK7-NEXT: [[I4:%.*]] = alloca i8, align 1 3496 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3497 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3498 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3499 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3500 // CHECK7-NEXT: [[I6:%.*]] = alloca i8, align 1 3501 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3502 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3503 // CHECK7-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 4 3504 // CHECK7-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 3505 // CHECK7-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 4 3506 // CHECK7-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 4 3507 // CHECK7-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1 3508 // CHECK7-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1 3509 // CHECK7-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3510 // CHECK7-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 3511 // CHECK7-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 3512 // CHECK7-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 3513 // CHECK7-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 3514 // CHECK7-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3515 // CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 3516 // CHECK7-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 3517 // CHECK7-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3518 // CHECK7-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1 3519 // CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3520 // CHECK7-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 3521 // CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 3522 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 3523 // CHECK7: omp.precond.then: 3524 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3525 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3526 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 3527 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3528 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3529 // CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3530 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 3531 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3532 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3533 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3534 // CHECK7-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] 3535 // CHECK7-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3536 // CHECK7: cond.true: 3537 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3538 // CHECK7-NEXT: br label [[COND_END:%.*]] 3539 // CHECK7: cond.false: 3540 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3541 // CHECK7-NEXT: br label [[COND_END]] 3542 // CHECK7: cond.end: 3543 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 3544 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3545 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3546 // CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 3547 // CHECK7-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP1]], align 1 3548 // CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0 3549 // CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3550 // CHECK7: omp_if.then: 3551 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3552 // CHECK7: omp.inner.for.cond: 3553 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 3554 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 3555 // CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 3556 // CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3557 // CHECK7: omp.inner.for.body: 3558 // CHECK7-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22 3559 // CHECK7-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32 3560 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 3561 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 3562 // CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 3563 // CHECK7-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 3564 // CHECK7-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !16, !llvm.access.group !22 3565 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3566 // CHECK7: omp.body.continue: 3567 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3568 // CHECK7: omp.inner.for.inc: 3569 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 3570 // CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 3571 // CHECK7-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 3572 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] 3573 // CHECK7: omp.inner.for.end: 3574 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 3575 // CHECK7: omp_if.else: 3576 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 3577 // CHECK7: omp.inner.for.cond13: 3578 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3579 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3580 // CHECK7-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] 3581 // CHECK7-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]] 3582 // CHECK7: omp.inner.for.body15: 3583 // CHECK7-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3584 // CHECK7-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32 3585 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3586 // CHECK7-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1 3587 // CHECK7-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]] 3588 // CHECK7-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 3589 // CHECK7-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1 3590 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]] 3591 // CHECK7: omp.body.continue20: 3592 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]] 3593 // CHECK7: omp.inner.for.inc21: 3594 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3595 // CHECK7-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1 3596 // CHECK7-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4 3597 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]] 3598 // CHECK7: omp.inner.for.end23: 3599 // CHECK7-NEXT: br label [[OMP_IF_END]] 3600 // CHECK7: omp_if.end: 3601 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3602 // CHECK7: omp.loop.exit: 3603 // CHECK7-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3604 // CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 3605 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 3606 // CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3607 // CHECK7-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 3608 // CHECK7-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3609 // CHECK7: .omp.final.then: 3610 // CHECK7-NEXT: [[TMP29:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3611 // CHECK7-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32 3612 // CHECK7-NEXT: [[TMP30:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3613 // CHECK7-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32 3614 // CHECK7-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]] 3615 // CHECK7-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1 3616 // CHECK7-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1 3617 // CHECK7-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1 3618 // CHECK7-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1 3619 // CHECK7-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]] 3620 // CHECK7-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8 3621 // CHECK7-NEXT: store i8 [[CONV32]], i8* [[TMP0]], align 1 3622 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 3623 // CHECK7: .omp.final.done: 3624 // CHECK7-NEXT: br label [[OMP_PRECOND_END]] 3625 // CHECK7: omp.precond.end: 3626 // CHECK7-NEXT: ret void 3627 // 3628 // 3629 // CHECK7-LABEL: define {{[^@]+}}@_Z4fintv 3630 // CHECK7-SAME: () #[[ATTR0]] { 3631 // CHECK7-NEXT: entry: 3632 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() 3633 // CHECK7-NEXT: ret i32 [[CALL]] 3634 // 3635 // 3636 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 3637 // CHECK7-SAME: () #[[ATTR0]] comdat { 3638 // CHECK7-NEXT: entry: 3639 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 3640 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3641 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 3642 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 3643 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 3644 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 3645 // CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 3646 // CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2 3647 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3648 // CHECK7-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2 3649 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3650 // CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3651 // CHECK7-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 3652 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 3653 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3654 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 3655 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 3656 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3657 // CHECK7-NEXT: store i8* null, i8** [[TMP6]], align 4 3658 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3659 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3660 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100) 3661 // CHECK7-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 3662 // CHECK7-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 3663 // CHECK7-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3664 // CHECK7: omp_offload.failed: 3665 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i32 [[TMP1]]) #[[ATTR3]] 3666 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 3667 // CHECK7: omp_offload.cont: 3668 // CHECK7-NEXT: ret i32 0 3669 // 3670 // 3671 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 3672 // CHECK7-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] { 3673 // CHECK7-NEXT: entry: 3674 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3675 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3676 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3677 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]]) 3678 // CHECK7-NEXT: ret void 3679 // 3680 // 3681 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 3682 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { 3683 // CHECK7-NEXT: entry: 3684 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3685 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3686 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 3687 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3688 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 3689 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3690 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3691 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3692 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3693 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 3694 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3695 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3696 // CHECK7-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 3697 // CHECK7-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 3698 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3699 // CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 3700 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3701 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3702 // CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 3703 // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 3704 // CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3705 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 3706 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 3707 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3708 // CHECK7: omp.dispatch.cond: 3709 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3710 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 3711 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3712 // CHECK7: cond.true: 3713 // CHECK7-NEXT: br label [[COND_END:%.*]] 3714 // CHECK7: cond.false: 3715 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3716 // CHECK7-NEXT: br label [[COND_END]] 3717 // CHECK7: cond.end: 3718 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 3719 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3720 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3721 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 3722 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3723 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3724 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 3725 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3726 // CHECK7: omp.dispatch.body: 3727 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3728 // CHECK7: omp.inner.for.cond: 3729 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 3730 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 3731 // CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 3732 // CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3733 // CHECK7: omp.inner.for.body: 3734 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 3735 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 3736 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3737 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 3738 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3739 // CHECK7: omp.body.continue: 3740 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3741 // CHECK7: omp.inner.for.inc: 3742 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 3743 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 3744 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 3745 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 3746 // CHECK7: omp.inner.for.end: 3747 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3748 // CHECK7: omp.dispatch.inc: 3749 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3750 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3751 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 3752 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 3753 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3754 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3755 // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 3756 // CHECK7-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 3757 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] 3758 // CHECK7: omp.dispatch.end: 3759 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 3760 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3761 // CHECK7-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 3762 // CHECK7-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3763 // CHECK7: .omp.final.then: 3764 // CHECK7-NEXT: store i32 100, i32* [[I]], align 4 3765 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 3766 // CHECK7: .omp.final.done: 3767 // CHECK7-NEXT: ret void 3768 // 3769 // 3770 // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3771 // CHECK7-SAME: () #[[ATTR4:[0-9]+]] { 3772 // CHECK7-NEXT: entry: 3773 // CHECK7-NEXT: call void @__tgt_register_requires(i64 1) 3774 // CHECK7-NEXT: ret void 3775 // 3776 // 3777 // CHECK9-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 3778 // CHECK9-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 3779 // CHECK9-NEXT: entry: 3780 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3781 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3782 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3783 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3784 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 3785 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3786 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3787 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3788 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 3789 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3790 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3791 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3792 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3793 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3794 // CHECK9-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 3795 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3796 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 3797 // CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 8 3798 // CHECK9-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i64 16) ] 3799 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3800 // CHECK9: omp.inner.for.cond: 3801 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 3802 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 3803 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 3804 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3805 // CHECK9: omp.inner.for.body: 3806 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 3807 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 3808 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 3809 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 3810 // CHECK9-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !2 3811 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 3812 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 3813 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]] 3814 // CHECK9-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !2 3815 // CHECK9-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !2 3816 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 3817 // CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 3818 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM1]] 3819 // CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !2 3820 // CHECK9-NEXT: [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]] 3821 // CHECK9-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !2 3822 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 3823 // CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 3824 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM4]] 3825 // CHECK9-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !2 3826 // CHECK9-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]] 3827 // CHECK9-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !2 3828 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 3829 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64 3830 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM7]] 3831 // CHECK9-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !2 3832 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3833 // CHECK9: omp.body.continue: 3834 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3835 // CHECK9: omp.inner.for.inc: 3836 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 3837 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1 3838 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 3839 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 3840 // CHECK9: omp.inner.for.end: 3841 // CHECK9-NEXT: store i32 32000001, i32* [[I]], align 4 3842 // CHECK9-NEXT: ret void 3843 // 3844 // 3845 // CHECK9-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 3846 // CHECK9-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 3847 // CHECK9-NEXT: entry: 3848 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3849 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3850 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3851 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3852 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 3853 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3854 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3855 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3856 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 3857 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3858 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3859 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3860 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3861 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3862 // CHECK9-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 3863 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3864 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 3865 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3866 // CHECK9: omp.inner.for.cond: 3867 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3868 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3869 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 3870 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3871 // CHECK9: omp.inner.for.body: 3872 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3873 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7 3874 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 3875 // CHECK9-NEXT: store i32 [[SUB]], i32* [[I]], align 4 3876 // CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8 3877 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 3878 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 3879 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]] 3880 // CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 3881 // CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8 3882 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 3883 // CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 3884 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]] 3885 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 3886 // CHECK9-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]] 3887 // CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8 3888 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 3889 // CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 3890 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]] 3891 // CHECK9-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4 3892 // CHECK9-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]] 3893 // CHECK9-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8 3894 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 3895 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 3896 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]] 3897 // CHECK9-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4 3898 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3899 // CHECK9: omp.body.continue: 3900 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3901 // CHECK9: omp.inner.for.inc: 3902 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3903 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 3904 // CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 3905 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 3906 // CHECK9: omp.inner.for.end: 3907 // CHECK9-NEXT: store i32 32, i32* [[I]], align 4 3908 // CHECK9-NEXT: ret void 3909 // 3910 // 3911 // CHECK9-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 3912 // CHECK9-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 3913 // CHECK9-NEXT: entry: 3914 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3915 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3916 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3917 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3918 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 3919 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3920 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3921 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3922 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 3923 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3924 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3925 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3926 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3927 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3928 // CHECK9-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 3929 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3930 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 3931 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3932 // CHECK9: omp.inner.for.cond: 3933 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 3934 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 3935 // CHECK9-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]] 3936 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3937 // CHECK9: omp.inner.for.body: 3938 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 3939 // CHECK9-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127 3940 // CHECK9-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 3941 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 3942 // CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !9 3943 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 3944 // CHECK9-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64 3945 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]] 3946 // CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 3947 // CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !9 3948 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 3949 // CHECK9-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64 3950 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]] 3951 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !9 3952 // CHECK9-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]] 3953 // CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !9 3954 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 3955 // CHECK9-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64 3956 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]] 3957 // CHECK9-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !9 3958 // CHECK9-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]] 3959 // CHECK9-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !9 3960 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 3961 // CHECK9-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64 3962 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]] 3963 // CHECK9-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !9 3964 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3965 // CHECK9: omp.body.continue: 3966 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3967 // CHECK9: omp.inner.for.inc: 3968 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 3969 // CHECK9-NEXT: [[ADD9:%.*]] = add i32 [[TMP15]], 1 3970 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 3971 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 3972 // CHECK9: omp.inner.for.end: 3973 // CHECK9-NEXT: store i32 -2147483522, i32* [[I]], align 4 3974 // CHECK9-NEXT: ret void 3975 // 3976 // 3977 // CHECK9-LABEL: define {{[^@]+}}@_Z12test_precondv 3978 // CHECK9-SAME: () #[[ATTR0]] { 3979 // CHECK9-NEXT: entry: 3980 // CHECK9-NEXT: [[A:%.*]] = alloca i8, align 1 3981 // CHECK9-NEXT: [[I:%.*]] = alloca i8, align 1 3982 // CHECK9-NEXT: [[TMP:%.*]] = alloca i8, align 1 3983 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 3984 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3985 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3986 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3987 // CHECK9-NEXT: [[I4:%.*]] = alloca i8, align 1 3988 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3989 // CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1 3990 // CHECK9-NEXT: [[I6:%.*]] = alloca i8, align 1 3991 // CHECK9-NEXT: [[I7:%.*]] = alloca i8, align 1 3992 // CHECK9-NEXT: store i8 0, i8* [[A]], align 1 3993 // CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 3994 // CHECK9-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 3995 // CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3996 // CHECK9-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 3997 // CHECK9-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 3998 // CHECK9-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 3999 // CHECK9-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 4000 // CHECK9-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4001 // CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 4002 // CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 4003 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4004 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4005 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 4006 // CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4007 // CHECK9-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1 4008 // CHECK9-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4009 // CHECK9-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 4010 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 4011 // CHECK9-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 4012 // CHECK9: simd.if.then: 4013 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4014 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 4015 // CHECK9-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 4016 // CHECK9-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1 4017 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4018 // CHECK9: omp.inner.for.cond: 4019 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 4020 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 4021 // CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 4022 // CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4023 // CHECK9: omp.inner.for.body: 4024 // CHECK9-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !12 4025 // CHECK9-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32 4026 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 4027 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 4028 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 4029 // CHECK9-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 4030 // CHECK9-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !12 4031 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4032 // CHECK9: omp.body.continue: 4033 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4034 // CHECK9: omp.inner.for.inc: 4035 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 4036 // CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1 4037 // CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 4038 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 4039 // CHECK9: omp.inner.for.end: 4040 // CHECK9-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4041 // CHECK9-NEXT: [[CONV13:%.*]] = sext i8 [[TMP12]] to i32 4042 // CHECK9-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4043 // CHECK9-NEXT: [[CONV14:%.*]] = sext i8 [[TMP13]] to i32 4044 // CHECK9-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]] 4045 // CHECK9-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1 4046 // CHECK9-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1 4047 // CHECK9-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1 4048 // CHECK9-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1 4049 // CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]] 4050 // CHECK9-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 4051 // CHECK9-NEXT: store i8 [[CONV21]], i8* [[I]], align 1 4052 // CHECK9-NEXT: br label [[SIMD_IF_END]] 4053 // CHECK9: simd.if.end: 4054 // CHECK9-NEXT: ret void 4055 // 4056 // 4057 // CHECK9-LABEL: define {{[^@]+}}@_Z4fintv 4058 // CHECK9-SAME: () #[[ATTR0]] { 4059 // CHECK9-NEXT: entry: 4060 // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() 4061 // CHECK9-NEXT: ret i32 [[CALL]] 4062 // 4063 // 4064 // CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 4065 // CHECK9-SAME: () #[[ATTR0]] comdat { 4066 // CHECK9-NEXT: entry: 4067 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 4068 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 4069 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4070 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4071 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4072 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 4073 // CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 4074 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4075 // CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 4076 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4077 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 4078 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4079 // CHECK9: omp.inner.for.cond: 4080 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 4081 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 4082 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 4083 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4084 // CHECK9: omp.inner.for.body: 4085 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 4086 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 4087 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4088 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15 4089 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4090 // CHECK9: omp.body.continue: 4091 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4092 // CHECK9: omp.inner.for.inc: 4093 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 4094 // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 4095 // CHECK9-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 4096 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 4097 // CHECK9: omp.inner.for.end: 4098 // CHECK9-NEXT: store i32 100, i32* [[I]], align 4 4099 // CHECK9-NEXT: ret i32 0 4100 // 4101 // 4102 // CHECK11-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 4103 // CHECK11-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 4104 // CHECK11-NEXT: entry: 4105 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 4106 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 4107 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 4108 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 4109 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4110 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4111 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4112 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4113 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4114 // CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 4115 // CHECK11-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 4116 // CHECK11-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 4117 // CHECK11-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 4118 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4119 // CHECK11-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 4120 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4121 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 4122 // CHECK11-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 4 4123 // CHECK11-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i32 16) ] 4124 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4125 // CHECK11: omp.inner.for.cond: 4126 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4127 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 4128 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 4129 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4130 // CHECK11: omp.inner.for.body: 4131 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4132 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 4133 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 4134 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 4135 // CHECK11-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !3 4136 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 4137 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i32 [[TMP6]] 4138 // CHECK11-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !3 4139 // CHECK11-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !3 4140 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 4141 // CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP8]], i32 [[TMP9]] 4142 // CHECK11-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !3 4143 // CHECK11-NEXT: [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]] 4144 // CHECK11-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !3 4145 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 4146 // CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP11]], i32 [[TMP12]] 4147 // CHECK11-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !3 4148 // CHECK11-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]] 4149 // CHECK11-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !3 4150 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 4151 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] 4152 // CHECK11-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !3 4153 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4154 // CHECK11: omp.body.continue: 4155 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4156 // CHECK11: omp.inner.for.inc: 4157 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4158 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 4159 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4160 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 4161 // CHECK11: omp.inner.for.end: 4162 // CHECK11-NEXT: store i32 32000001, i32* [[I]], align 4 4163 // CHECK11-NEXT: ret void 4164 // 4165 // 4166 // CHECK11-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 4167 // CHECK11-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 4168 // CHECK11-NEXT: entry: 4169 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 4170 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 4171 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 4172 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 4173 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4174 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4175 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4176 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4177 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4178 // CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 4179 // CHECK11-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 4180 // CHECK11-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 4181 // CHECK11-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 4182 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4183 // CHECK11-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 4184 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4185 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 4186 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4187 // CHECK11: omp.inner.for.cond: 4188 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4189 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4190 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 4191 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4192 // CHECK11: omp.inner.for.body: 4193 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4194 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7 4195 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 4196 // CHECK11-NEXT: store i32 [[SUB]], i32* [[I]], align 4 4197 // CHECK11-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4 4198 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 4199 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 4200 // CHECK11-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 4201 // CHECK11-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4 4202 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 4203 // CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 4204 // CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4 4205 // CHECK11-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]] 4206 // CHECK11-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4 4207 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 4208 // CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 4209 // CHECK11-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4 4210 // CHECK11-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]] 4211 // CHECK11-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4 4212 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 4213 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]] 4214 // CHECK11-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4 4215 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4216 // CHECK11: omp.body.continue: 4217 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4218 // CHECK11: omp.inner.for.inc: 4219 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4220 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 4221 // CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 4222 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 4223 // CHECK11: omp.inner.for.end: 4224 // CHECK11-NEXT: store i32 32, i32* [[I]], align 4 4225 // CHECK11-NEXT: ret void 4226 // 4227 // 4228 // CHECK11-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 4229 // CHECK11-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 4230 // CHECK11-NEXT: entry: 4231 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 4232 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 4233 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 4234 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 4235 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4236 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4237 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4238 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4239 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4240 // CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 4241 // CHECK11-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 4242 // CHECK11-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 4243 // CHECK11-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 4244 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4245 // CHECK11-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 4246 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4247 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 4248 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4249 // CHECK11: omp.inner.for.cond: 4250 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 4251 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 4252 // CHECK11-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]] 4253 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4254 // CHECK11: omp.inner.for.body: 4255 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 4256 // CHECK11-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127 4257 // CHECK11-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 4258 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 4259 // CHECK11-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !10 4260 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 4261 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 4262 // CHECK11-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 4263 // CHECK11-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !10 4264 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 4265 // CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 4266 // CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !10 4267 // CHECK11-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]] 4268 // CHECK11-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !10 4269 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 4270 // CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 4271 // CHECK11-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !10 4272 // CHECK11-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]] 4273 // CHECK11-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !10 4274 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 4275 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]] 4276 // CHECK11-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !10 4277 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4278 // CHECK11: omp.body.continue: 4279 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4280 // CHECK11: omp.inner.for.inc: 4281 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 4282 // CHECK11-NEXT: [[ADD6:%.*]] = add i32 [[TMP15]], 1 4283 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 4284 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 4285 // CHECK11: omp.inner.for.end: 4286 // CHECK11-NEXT: store i32 -2147483522, i32* [[I]], align 4 4287 // CHECK11-NEXT: ret void 4288 // 4289 // 4290 // CHECK11-LABEL: define {{[^@]+}}@_Z12test_precondv 4291 // CHECK11-SAME: () #[[ATTR0]] { 4292 // CHECK11-NEXT: entry: 4293 // CHECK11-NEXT: [[A:%.*]] = alloca i8, align 1 4294 // CHECK11-NEXT: [[I:%.*]] = alloca i8, align 1 4295 // CHECK11-NEXT: [[TMP:%.*]] = alloca i8, align 1 4296 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4297 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4298 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4299 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4300 // CHECK11-NEXT: [[I4:%.*]] = alloca i8, align 1 4301 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4302 // CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1 4303 // CHECK11-NEXT: [[I6:%.*]] = alloca i8, align 1 4304 // CHECK11-NEXT: [[I7:%.*]] = alloca i8, align 1 4305 // CHECK11-NEXT: store i8 0, i8* [[A]], align 1 4306 // CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 4307 // CHECK11-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 4308 // CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4309 // CHECK11-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 4310 // CHECK11-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 4311 // CHECK11-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 4312 // CHECK11-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 4313 // CHECK11-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4314 // CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 4315 // CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 4316 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4317 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4318 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 4319 // CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4320 // CHECK11-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1 4321 // CHECK11-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4322 // CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 4323 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 4324 // CHECK11-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 4325 // CHECK11: simd.if.then: 4326 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4327 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 4328 // CHECK11-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 4329 // CHECK11-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1 4330 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4331 // CHECK11: omp.inner.for.cond: 4332 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4333 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 4334 // CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 4335 // CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4336 // CHECK11: omp.inner.for.body: 4337 // CHECK11-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !13 4338 // CHECK11-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32 4339 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4340 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 4341 // CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 4342 // CHECK11-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 4343 // CHECK11-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !13 4344 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4345 // CHECK11: omp.body.continue: 4346 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4347 // CHECK11: omp.inner.for.inc: 4348 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4349 // CHECK11-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1 4350 // CHECK11-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4351 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 4352 // CHECK11: omp.inner.for.end: 4353 // CHECK11-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4354 // CHECK11-NEXT: [[CONV13:%.*]] = sext i8 [[TMP12]] to i32 4355 // CHECK11-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4356 // CHECK11-NEXT: [[CONV14:%.*]] = sext i8 [[TMP13]] to i32 4357 // CHECK11-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]] 4358 // CHECK11-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1 4359 // CHECK11-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1 4360 // CHECK11-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1 4361 // CHECK11-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1 4362 // CHECK11-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]] 4363 // CHECK11-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 4364 // CHECK11-NEXT: store i8 [[CONV21]], i8* [[I]], align 1 4365 // CHECK11-NEXT: br label [[SIMD_IF_END]] 4366 // CHECK11: simd.if.end: 4367 // CHECK11-NEXT: ret void 4368 // 4369 // 4370 // CHECK11-LABEL: define {{[^@]+}}@_Z4fintv 4371 // CHECK11-SAME: () #[[ATTR0]] { 4372 // CHECK11-NEXT: entry: 4373 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() 4374 // CHECK11-NEXT: ret i32 [[CALL]] 4375 // 4376 // 4377 // CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 4378 // CHECK11-SAME: () #[[ATTR0]] comdat { 4379 // CHECK11-NEXT: entry: 4380 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 4381 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4382 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4383 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4384 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4385 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4386 // CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 4387 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4388 // CHECK11-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 4389 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4390 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 4391 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4392 // CHECK11: omp.inner.for.cond: 4393 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 4394 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !16 4395 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 4396 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4397 // CHECK11: omp.inner.for.body: 4398 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 4399 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 4400 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4401 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16 4402 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4403 // CHECK11: omp.body.continue: 4404 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4405 // CHECK11: omp.inner.for.inc: 4406 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 4407 // CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 4408 // CHECK11-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 4409 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] 4410 // CHECK11: omp.inner.for.end: 4411 // CHECK11-NEXT: store i32 100, i32* [[I]], align 4 4412 // CHECK11-NEXT: ret i32 0 4413 // 4414 // 4415 // CHECK13-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 4416 // CHECK13-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 4417 // CHECK13-NEXT: entry: 4418 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4419 // CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4420 // CHECK13-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4421 // CHECK13-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4422 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 4423 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4424 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4425 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4426 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 4427 // CHECK13-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4428 // CHECK13-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4429 // CHECK13-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4430 // CHECK13-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4431 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4432 // CHECK13-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 4433 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4434 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 4435 // CHECK13-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 8 4436 // CHECK13-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i64 16) ] 4437 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4438 // CHECK13: omp.inner.for.cond: 4439 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 4440 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 4441 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 4442 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4443 // CHECK13: omp.inner.for.body: 4444 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 4445 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 4446 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 4447 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 4448 // CHECK13-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !2 4449 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 4450 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 4451 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]] 4452 // CHECK13-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !2 4453 // CHECK13-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !2 4454 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 4455 // CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 4456 // CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM1]] 4457 // CHECK13-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !2 4458 // CHECK13-NEXT: [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]] 4459 // CHECK13-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !2 4460 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 4461 // CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 4462 // CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM4]] 4463 // CHECK13-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !2 4464 // CHECK13-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]] 4465 // CHECK13-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !2 4466 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 4467 // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64 4468 // CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM7]] 4469 // CHECK13-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !2 4470 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4471 // CHECK13: omp.body.continue: 4472 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4473 // CHECK13: omp.inner.for.inc: 4474 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 4475 // CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1 4476 // CHECK13-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 4477 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 4478 // CHECK13: omp.inner.for.end: 4479 // CHECK13-NEXT: store i32 32000001, i32* [[I]], align 4 4480 // CHECK13-NEXT: ret void 4481 // 4482 // 4483 // CHECK13-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 4484 // CHECK13-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 4485 // CHECK13-NEXT: entry: 4486 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4487 // CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4488 // CHECK13-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4489 // CHECK13-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4490 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 4491 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4492 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4493 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4494 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 4495 // CHECK13-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4496 // CHECK13-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4497 // CHECK13-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4498 // CHECK13-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4499 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4500 // CHECK13-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 4501 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4502 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 4503 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4504 // CHECK13: omp.inner.for.cond: 4505 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4506 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4507 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 4508 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4509 // CHECK13: omp.inner.for.body: 4510 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4511 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7 4512 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 4513 // CHECK13-NEXT: store i32 [[SUB]], i32* [[I]], align 4 4514 // CHECK13-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !nontemporal !7 4515 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 4516 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 4517 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]] 4518 // CHECK13-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 4519 // CHECK13-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8 4520 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 4521 // CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 4522 // CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]] 4523 // CHECK13-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 4524 // CHECK13-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]] 4525 // CHECK13-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8 4526 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 4527 // CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 4528 // CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]] 4529 // CHECK13-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4 4530 // CHECK13-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]] 4531 // CHECK13-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !nontemporal !7 4532 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 4533 // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 4534 // CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]] 4535 // CHECK13-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4 4536 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4537 // CHECK13: omp.body.continue: 4538 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4539 // CHECK13: omp.inner.for.inc: 4540 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4541 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 4542 // CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 4543 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 4544 // CHECK13: omp.inner.for.end: 4545 // CHECK13-NEXT: store i32 32, i32* [[I]], align 4 4546 // CHECK13-NEXT: ret void 4547 // 4548 // 4549 // CHECK13-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 4550 // CHECK13-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 4551 // CHECK13-NEXT: entry: 4552 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4553 // CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4554 // CHECK13-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4555 // CHECK13-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4556 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 4557 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4558 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4559 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4560 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 4561 // CHECK13-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4562 // CHECK13-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4563 // CHECK13-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4564 // CHECK13-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4565 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4566 // CHECK13-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 4567 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4568 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 4569 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4570 // CHECK13: omp.inner.for.cond: 4571 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 4572 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 4573 // CHECK13-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]] 4574 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4575 // CHECK13: omp.inner.for.body: 4576 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 4577 // CHECK13-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127 4578 // CHECK13-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 4579 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 4580 // CHECK13-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !10 4581 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 4582 // CHECK13-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64 4583 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]] 4584 // CHECK13-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 4585 // CHECK13-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !10 4586 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 4587 // CHECK13-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64 4588 // CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]] 4589 // CHECK13-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !10 4590 // CHECK13-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]] 4591 // CHECK13-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !10 4592 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 4593 // CHECK13-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64 4594 // CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]] 4595 // CHECK13-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !10 4596 // CHECK13-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]] 4597 // CHECK13-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !10 4598 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 4599 // CHECK13-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64 4600 // CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]] 4601 // CHECK13-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !10 4602 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4603 // CHECK13: omp.body.continue: 4604 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4605 // CHECK13: omp.inner.for.inc: 4606 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 4607 // CHECK13-NEXT: [[ADD9:%.*]] = add i32 [[TMP15]], 1 4608 // CHECK13-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 4609 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 4610 // CHECK13: omp.inner.for.end: 4611 // CHECK13-NEXT: store i32 -2147483522, i32* [[I]], align 4 4612 // CHECK13-NEXT: ret void 4613 // 4614 // 4615 // CHECK13-LABEL: define {{[^@]+}}@_Z12test_precondv 4616 // CHECK13-SAME: () #[[ATTR0]] { 4617 // CHECK13-NEXT: entry: 4618 // CHECK13-NEXT: [[A:%.*]] = alloca i8, align 1 4619 // CHECK13-NEXT: [[I:%.*]] = alloca i8, align 1 4620 // CHECK13-NEXT: [[TMP:%.*]] = alloca i8, align 1 4621 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4622 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4623 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4624 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4625 // CHECK13-NEXT: [[I4:%.*]] = alloca i8, align 1 4626 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4627 // CHECK13-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1 4628 // CHECK13-NEXT: [[I6:%.*]] = alloca i8, align 1 4629 // CHECK13-NEXT: [[I7:%.*]] = alloca i8, align 1 4630 // CHECK13-NEXT: store i8 0, i8* [[A]], align 1 4631 // CHECK13-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 4632 // CHECK13-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 4633 // CHECK13-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4634 // CHECK13-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 4635 // CHECK13-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 4636 // CHECK13-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 4637 // CHECK13-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 4638 // CHECK13-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4639 // CHECK13-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 4640 // CHECK13-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 4641 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4642 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4643 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 4644 // CHECK13-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4645 // CHECK13-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1 4646 // CHECK13-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4647 // CHECK13-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 4648 // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 4649 // CHECK13-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 4650 // CHECK13: simd.if.then: 4651 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4652 // CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 4653 // CHECK13-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 4654 // CHECK13-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1 4655 // CHECK13-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 4656 // CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0 4657 // CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4658 // CHECK13: omp_if.then: 4659 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4660 // CHECK13: omp.inner.for.cond: 4661 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4662 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 4663 // CHECK13-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 4664 // CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4665 // CHECK13: omp.inner.for.body: 4666 // CHECK13-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !13 4667 // CHECK13-NEXT: [[CONV9:%.*]] = sext i8 [[TMP10]] to i32 4668 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4669 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 4670 // CHECK13-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 4671 // CHECK13-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 4672 // CHECK13-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !7, !llvm.access.group !13 4673 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4674 // CHECK13: omp.body.continue: 4675 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4676 // CHECK13: omp.inner.for.inc: 4677 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4678 // CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1 4679 // CHECK13-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4680 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 4681 // CHECK13: omp.inner.for.end: 4682 // CHECK13-NEXT: br label [[OMP_IF_END:%.*]] 4683 // CHECK13: omp_if.else: 4684 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 4685 // CHECK13: omp.inner.for.cond13: 4686 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4687 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4688 // CHECK13-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 4689 // CHECK13-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]] 4690 // CHECK13: omp.inner.for.body15: 4691 // CHECK13-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4692 // CHECK13-NEXT: [[CONV16:%.*]] = sext i8 [[TMP15]] to i32 4693 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4694 // CHECK13-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1 4695 // CHECK13-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]] 4696 // CHECK13-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 4697 // CHECK13-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1 4698 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]] 4699 // CHECK13: omp.body.continue20: 4700 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]] 4701 // CHECK13: omp.inner.for.inc21: 4702 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4703 // CHECK13-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1 4704 // CHECK13-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4 4705 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP16:![0-9]+]] 4706 // CHECK13: omp.inner.for.end23: 4707 // CHECK13-NEXT: br label [[OMP_IF_END]] 4708 // CHECK13: omp_if.end: 4709 // CHECK13-NEXT: [[TMP18:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4710 // CHECK13-NEXT: [[CONV24:%.*]] = sext i8 [[TMP18]] to i32 4711 // CHECK13-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4712 // CHECK13-NEXT: [[CONV25:%.*]] = sext i8 [[TMP19]] to i32 4713 // CHECK13-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]] 4714 // CHECK13-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1 4715 // CHECK13-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1 4716 // CHECK13-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1 4717 // CHECK13-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1 4718 // CHECK13-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]] 4719 // CHECK13-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8 4720 // CHECK13-NEXT: store i8 [[CONV32]], i8* [[I]], align 1 4721 // CHECK13-NEXT: br label [[SIMD_IF_END]] 4722 // CHECK13: simd.if.end: 4723 // CHECK13-NEXT: ret void 4724 // 4725 // 4726 // CHECK13-LABEL: define {{[^@]+}}@_Z4fintv 4727 // CHECK13-SAME: () #[[ATTR0]] { 4728 // CHECK13-NEXT: entry: 4729 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() 4730 // CHECK13-NEXT: ret i32 [[CALL]] 4731 // 4732 // 4733 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 4734 // CHECK13-SAME: () #[[ATTR0]] comdat { 4735 // CHECK13-NEXT: entry: 4736 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 4737 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 4738 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4739 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4740 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4741 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 4742 // CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 4743 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4744 // CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 4745 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4746 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 4747 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4748 // CHECK13: omp.inner.for.cond: 4749 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 4750 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 4751 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 4752 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4753 // CHECK13: omp.inner.for.body: 4754 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 4755 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 4756 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4757 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 4758 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4759 // CHECK13: omp.body.continue: 4760 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4761 // CHECK13: omp.inner.for.inc: 4762 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 4763 // CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 4764 // CHECK13-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 4765 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 4766 // CHECK13: omp.inner.for.end: 4767 // CHECK13-NEXT: store i32 100, i32* [[I]], align 4 4768 // CHECK13-NEXT: ret i32 0 4769 // 4770 // 4771 // CHECK15-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 4772 // CHECK15-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 4773 // CHECK15-NEXT: entry: 4774 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 4775 // CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 4776 // CHECK15-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 4777 // CHECK15-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 4778 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 4779 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4780 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4781 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4782 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 4783 // CHECK15-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 4784 // CHECK15-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 4785 // CHECK15-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 4786 // CHECK15-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 4787 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4788 // CHECK15-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 4789 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4790 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 4791 // CHECK15-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 4 4792 // CHECK15-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i32 16) ] 4793 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4794 // CHECK15: omp.inner.for.cond: 4795 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4796 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 4797 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 4798 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4799 // CHECK15: omp.inner.for.body: 4800 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4801 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7 4802 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 4803 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 4804 // CHECK15-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !3 4805 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 4806 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i32 [[TMP6]] 4807 // CHECK15-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !3 4808 // CHECK15-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !3 4809 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 4810 // CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP8]], i32 [[TMP9]] 4811 // CHECK15-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !3 4812 // CHECK15-NEXT: [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]] 4813 // CHECK15-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !3 4814 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 4815 // CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP11]], i32 [[TMP12]] 4816 // CHECK15-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !3 4817 // CHECK15-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]] 4818 // CHECK15-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !3 4819 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 4820 // CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] 4821 // CHECK15-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !3 4822 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4823 // CHECK15: omp.body.continue: 4824 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4825 // CHECK15: omp.inner.for.inc: 4826 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4827 // CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 4828 // CHECK15-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4829 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 4830 // CHECK15: omp.inner.for.end: 4831 // CHECK15-NEXT: store i32 32000001, i32* [[I]], align 4 4832 // CHECK15-NEXT: ret void 4833 // 4834 // 4835 // CHECK15-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 4836 // CHECK15-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 4837 // CHECK15-NEXT: entry: 4838 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 4839 // CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 4840 // CHECK15-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 4841 // CHECK15-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 4842 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 4843 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4844 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4845 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4846 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 4847 // CHECK15-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 4848 // CHECK15-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 4849 // CHECK15-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 4850 // CHECK15-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 4851 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4852 // CHECK15-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 4853 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4854 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 4855 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4856 // CHECK15: omp.inner.for.cond: 4857 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4858 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4859 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 4860 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4861 // CHECK15: omp.inner.for.body: 4862 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4863 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7 4864 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 4865 // CHECK15-NEXT: store i32 [[SUB]], i32* [[I]], align 4 4866 // CHECK15-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !nontemporal !8 4867 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 4868 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 4869 // CHECK15-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 4870 // CHECK15-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4 4871 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 4872 // CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 4873 // CHECK15-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4 4874 // CHECK15-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]] 4875 // CHECK15-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4 4876 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 4877 // CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 4878 // CHECK15-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4 4879 // CHECK15-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]] 4880 // CHECK15-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !nontemporal !8 4881 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 4882 // CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]] 4883 // CHECK15-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4 4884 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4885 // CHECK15: omp.body.continue: 4886 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4887 // CHECK15: omp.inner.for.inc: 4888 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4889 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 4890 // CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 4891 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 4892 // CHECK15: omp.inner.for.end: 4893 // CHECK15-NEXT: store i32 32, i32* [[I]], align 4 4894 // CHECK15-NEXT: ret void 4895 // 4896 // 4897 // CHECK15-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 4898 // CHECK15-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 4899 // CHECK15-NEXT: entry: 4900 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 4901 // CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 4902 // CHECK15-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 4903 // CHECK15-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 4904 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 4905 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4906 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4907 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4908 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 4909 // CHECK15-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 4910 // CHECK15-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 4911 // CHECK15-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 4912 // CHECK15-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 4913 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4914 // CHECK15-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 4915 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4916 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 4917 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4918 // CHECK15: omp.inner.for.cond: 4919 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 4920 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 4921 // CHECK15-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]] 4922 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4923 // CHECK15: omp.inner.for.body: 4924 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 4925 // CHECK15-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127 4926 // CHECK15-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 4927 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 4928 // CHECK15-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !11 4929 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 4930 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] 4931 // CHECK15-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 4932 // CHECK15-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !11 4933 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 4934 // CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] 4935 // CHECK15-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !11 4936 // CHECK15-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]] 4937 // CHECK15-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !11 4938 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 4939 // CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] 4940 // CHECK15-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !11 4941 // CHECK15-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]] 4942 // CHECK15-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !11 4943 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 4944 // CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]] 4945 // CHECK15-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !11 4946 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4947 // CHECK15: omp.body.continue: 4948 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4949 // CHECK15: omp.inner.for.inc: 4950 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 4951 // CHECK15-NEXT: [[ADD6:%.*]] = add i32 [[TMP15]], 1 4952 // CHECK15-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 4953 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 4954 // CHECK15: omp.inner.for.end: 4955 // CHECK15-NEXT: store i32 -2147483522, i32* [[I]], align 4 4956 // CHECK15-NEXT: ret void 4957 // 4958 // 4959 // CHECK15-LABEL: define {{[^@]+}}@_Z12test_precondv 4960 // CHECK15-SAME: () #[[ATTR0]] { 4961 // CHECK15-NEXT: entry: 4962 // CHECK15-NEXT: [[A:%.*]] = alloca i8, align 1 4963 // CHECK15-NEXT: [[I:%.*]] = alloca i8, align 1 4964 // CHECK15-NEXT: [[TMP:%.*]] = alloca i8, align 1 4965 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4966 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4967 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4968 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4969 // CHECK15-NEXT: [[I4:%.*]] = alloca i8, align 1 4970 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4971 // CHECK15-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1 4972 // CHECK15-NEXT: [[I6:%.*]] = alloca i8, align 1 4973 // CHECK15-NEXT: [[I7:%.*]] = alloca i8, align 1 4974 // CHECK15-NEXT: store i8 0, i8* [[A]], align 1 4975 // CHECK15-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 4976 // CHECK15-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 4977 // CHECK15-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4978 // CHECK15-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 4979 // CHECK15-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 4980 // CHECK15-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 4981 // CHECK15-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 4982 // CHECK15-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4983 // CHECK15-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 4984 // CHECK15-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 4985 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4986 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4987 // CHECK15-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4 4988 // CHECK15-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4989 // CHECK15-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1 4990 // CHECK15-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4991 // CHECK15-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 4992 // CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 4993 // CHECK15-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 4994 // CHECK15: simd.if.then: 4995 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4996 // CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 4997 // CHECK15-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 4998 // CHECK15-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1 4999 // CHECK15-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 5000 // CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0 5001 // CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5002 // CHECK15: omp_if.then: 5003 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5004 // CHECK15: omp.inner.for.cond: 5005 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 5006 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 5007 // CHECK15-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 5008 // CHECK15-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5009 // CHECK15: omp.inner.for.body: 5010 // CHECK15-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !14 5011 // CHECK15-NEXT: [[CONV9:%.*]] = sext i8 [[TMP10]] to i32 5012 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 5013 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 5014 // CHECK15-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 5015 // CHECK15-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 5016 // CHECK15-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !8, !llvm.access.group !14 5017 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5018 // CHECK15: omp.body.continue: 5019 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5020 // CHECK15: omp.inner.for.inc: 5021 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 5022 // CHECK15-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1 5023 // CHECK15-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 5024 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 5025 // CHECK15: omp.inner.for.end: 5026 // CHECK15-NEXT: br label [[OMP_IF_END:%.*]] 5027 // CHECK15: omp_if.else: 5028 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 5029 // CHECK15: omp.inner.for.cond13: 5030 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5031 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5032 // CHECK15-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 5033 // CHECK15-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]] 5034 // CHECK15: omp.inner.for.body15: 5035 // CHECK15-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 5036 // CHECK15-NEXT: [[CONV16:%.*]] = sext i8 [[TMP15]] to i32 5037 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5038 // CHECK15-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1 5039 // CHECK15-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]] 5040 // CHECK15-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 5041 // CHECK15-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1 5042 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]] 5043 // CHECK15: omp.body.continue20: 5044 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]] 5045 // CHECK15: omp.inner.for.inc21: 5046 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5047 // CHECK15-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1 5048 // CHECK15-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4 5049 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP17:![0-9]+]] 5050 // CHECK15: omp.inner.for.end23: 5051 // CHECK15-NEXT: br label [[OMP_IF_END]] 5052 // CHECK15: omp_if.end: 5053 // CHECK15-NEXT: [[TMP18:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 5054 // CHECK15-NEXT: [[CONV24:%.*]] = sext i8 [[TMP18]] to i32 5055 // CHECK15-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 5056 // CHECK15-NEXT: [[CONV25:%.*]] = sext i8 [[TMP19]] to i32 5057 // CHECK15-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]] 5058 // CHECK15-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1 5059 // CHECK15-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1 5060 // CHECK15-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1 5061 // CHECK15-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1 5062 // CHECK15-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]] 5063 // CHECK15-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8 5064 // CHECK15-NEXT: store i8 [[CONV32]], i8* [[I]], align 1 5065 // CHECK15-NEXT: br label [[SIMD_IF_END]] 5066 // CHECK15: simd.if.end: 5067 // CHECK15-NEXT: ret void 5068 // 5069 // 5070 // CHECK15-LABEL: define {{[^@]+}}@_Z4fintv 5071 // CHECK15-SAME: () #[[ATTR0]] { 5072 // CHECK15-NEXT: entry: 5073 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() 5074 // CHECK15-NEXT: ret i32 [[CALL]] 5075 // 5076 // 5077 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v 5078 // CHECK15-SAME: () #[[ATTR0]] comdat { 5079 // CHECK15-NEXT: entry: 5080 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 5081 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 5082 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5083 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5084 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5085 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 5086 // CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 5087 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5088 // CHECK15-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 5089 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5090 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 5091 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5092 // CHECK15: omp.inner.for.cond: 5093 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 5094 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 5095 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 5096 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5097 // CHECK15: omp.inner.for.body: 5098 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 5099 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 5100 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 5101 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 5102 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5103 // CHECK15: omp.body.continue: 5104 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5105 // CHECK15: omp.inner.for.inc: 5106 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 5107 // CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 5108 // CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 5109 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 5110 // CHECK15: omp.inner.for.end: 5111 // CHECK15-NEXT: store i32 100, i32* [[I]], align 4 5112 // CHECK15-NEXT: ret i32 0 5113 // 5114 // 5115 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 5116 // CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 5117 // CHECK17-NEXT: entry: 5118 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5119 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5120 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5121 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5122 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5123 // CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5124 // CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5125 // CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5126 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 5127 // CHECK17-NEXT: ret void 5128 // 5129 // 5130 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 5131 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 5132 // CHECK17-NEXT: entry: 5133 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5134 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5135 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 5136 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 5137 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 5138 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 5139 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5140 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 5141 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5142 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5143 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5144 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5145 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 5146 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5147 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5148 // CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 5149 // CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 5150 // CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 5151 // CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 5152 // CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 5153 // CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 5154 // CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 5155 // CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 5156 // CHECK17-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 8 5157 // CHECK17-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i64 16) ] 5158 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5159 // CHECK17-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 5160 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5161 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5162 // CHECK17-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5163 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 5164 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5165 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5166 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 5167 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5168 // CHECK17: cond.true: 5169 // CHECK17-NEXT: br label [[COND_END:%.*]] 5170 // CHECK17: cond.false: 5171 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5172 // CHECK17-NEXT: br label [[COND_END]] 5173 // CHECK17: cond.end: 5174 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 5175 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5176 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5177 // CHECK17-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 5178 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5179 // CHECK17: omp.inner.for.cond: 5180 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 5181 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 5182 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 5183 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5184 // CHECK17: omp.inner.for.body: 5185 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 5186 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 5187 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 5188 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 5189 // CHECK17-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9 5190 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 5191 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 5192 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]] 5193 // CHECK17-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 5194 // CHECK17-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9 5195 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 5196 // CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64 5197 // CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM2]] 5198 // CHECK17-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !9 5199 // CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]] 5200 // CHECK17-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9 5201 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 5202 // CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64 5203 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM5]] 5204 // CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !llvm.access.group !9 5205 // CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]] 5206 // CHECK17-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9 5207 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 5208 // CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64 5209 // CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM8]] 5210 // CHECK17-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !9 5211 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5212 // CHECK17: omp.body.continue: 5213 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5214 // CHECK17: omp.inner.for.inc: 5215 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 5216 // CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 5217 // CHECK17-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 5218 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 5219 // CHECK17: omp.inner.for.end: 5220 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5221 // CHECK17: omp.loop.exit: 5222 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]]) 5223 // CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5224 // CHECK17-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 5225 // CHECK17-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5226 // CHECK17: .omp.final.then: 5227 // CHECK17-NEXT: store i32 32000001, i32* [[I]], align 4 5228 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 5229 // CHECK17: .omp.final.done: 5230 // CHECK17-NEXT: ret void 5231 // 5232 // 5233 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 5234 // CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 5235 // CHECK17-NEXT: entry: 5236 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5237 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5238 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5239 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5240 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5241 // CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5242 // CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5243 // CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5244 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 5245 // CHECK17-NEXT: ret void 5246 // 5247 // 5248 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 5249 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 5250 // CHECK17-NEXT: entry: 5251 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5252 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5253 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 5254 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 5255 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 5256 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 5257 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5258 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 5259 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5260 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5261 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5262 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5263 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 5264 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5265 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5266 // CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 5267 // CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 5268 // CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 5269 // CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 5270 // CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 5271 // CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 5272 // CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 5273 // CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 5274 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5275 // CHECK17-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 5276 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5277 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5278 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5279 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 5280 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5281 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5282 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 5283 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5284 // CHECK17: cond.true: 5285 // CHECK17-NEXT: br label [[COND_END:%.*]] 5286 // CHECK17: cond.false: 5287 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5288 // CHECK17-NEXT: br label [[COND_END]] 5289 // CHECK17: cond.end: 5290 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 5291 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5292 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5293 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 5294 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5295 // CHECK17: omp.inner.for.cond: 5296 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5297 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5298 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 5299 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5300 // CHECK17: omp.inner.for.body: 5301 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5302 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 5303 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 5304 // CHECK17-NEXT: store i32 [[SUB]], i32* [[I]], align 4 5305 // CHECK17-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 5306 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 5307 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 5308 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 5309 // CHECK17-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 5310 // CHECK17-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 5311 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 5312 // CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 5313 // CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 5314 // CHECK17-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 5315 // CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 5316 // CHECK17-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 5317 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 5318 // CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 5319 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 5320 // CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 5321 // CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 5322 // CHECK17-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 5323 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 5324 // CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 5325 // CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 5326 // CHECK17-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 5327 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5328 // CHECK17: omp.body.continue: 5329 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5330 // CHECK17: omp.inner.for.inc: 5331 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5332 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 5333 // CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 5334 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] 5335 // CHECK17: omp.inner.for.end: 5336 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5337 // CHECK17: omp.loop.exit: 5338 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 5339 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5340 // CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 5341 // CHECK17-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5342 // CHECK17: .omp.final.then: 5343 // CHECK17-NEXT: store i32 32, i32* [[I]], align 4 5344 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 5345 // CHECK17: .omp.final.done: 5346 // CHECK17-NEXT: ret void 5347 // 5348 // 5349 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 5350 // CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 5351 // CHECK17-NEXT: entry: 5352 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5353 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5354 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5355 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5356 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5357 // CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5358 // CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5359 // CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5360 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 5361 // CHECK17-NEXT: ret void 5362 // 5363 // 5364 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 5365 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 5366 // CHECK17-NEXT: entry: 5367 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5368 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5369 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 5370 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 5371 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 5372 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 5373 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5374 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 5375 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5376 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5377 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5378 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5379 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 5380 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5381 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5382 // CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 5383 // CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 5384 // CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 5385 // CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 5386 // CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 5387 // CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 5388 // CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 5389 // CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 5390 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5391 // CHECK17-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 5392 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5393 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5394 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5395 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 5396 // CHECK17-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 5397 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 5398 // CHECK17: omp.dispatch.cond: 5399 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5400 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 5401 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5402 // CHECK17: cond.true: 5403 // CHECK17-NEXT: br label [[COND_END:%.*]] 5404 // CHECK17: cond.false: 5405 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5406 // CHECK17-NEXT: br label [[COND_END]] 5407 // CHECK17: cond.end: 5408 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 5409 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5410 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5411 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 5412 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5413 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5414 // CHECK17-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 5415 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 5416 // CHECK17: omp.dispatch.body: 5417 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5418 // CHECK17: omp.inner.for.cond: 5419 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 5420 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 5421 // CHECK17-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 5422 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5423 // CHECK17: omp.inner.for.body: 5424 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 5425 // CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 5426 // CHECK17-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 5427 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 5428 // CHECK17-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !18 5429 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 5430 // CHECK17-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 5431 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 5432 // CHECK17-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !18 5433 // CHECK17-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !18 5434 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 5435 // CHECK17-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 5436 // CHECK17-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 5437 // CHECK17-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !18 5438 // CHECK17-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 5439 // CHECK17-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !18 5440 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 5441 // CHECK17-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 5442 // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 5443 // CHECK17-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !18 5444 // CHECK17-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 5445 // CHECK17-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !18 5446 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 5447 // CHECK17-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 5448 // CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 5449 // CHECK17-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !18 5450 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5451 // CHECK17: omp.body.continue: 5452 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5453 // CHECK17: omp.inner.for.inc: 5454 // CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 5455 // CHECK17-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 5456 // CHECK17-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 5457 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 5458 // CHECK17: omp.inner.for.end: 5459 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 5460 // CHECK17: omp.dispatch.inc: 5461 // CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5462 // CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 5463 // CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 5464 // CHECK17-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 5465 // CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5466 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 5467 // CHECK17-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 5468 // CHECK17-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 5469 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 5470 // CHECK17: omp.dispatch.end: 5471 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 5472 // CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5473 // CHECK17-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 5474 // CHECK17-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5475 // CHECK17: .omp.final.then: 5476 // CHECK17-NEXT: store i32 -2147483522, i32* [[I]], align 4 5477 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 5478 // CHECK17: .omp.final.done: 5479 // CHECK17-NEXT: ret void 5480 // 5481 // 5482 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 5483 // CHECK17-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 5484 // CHECK17-NEXT: entry: 5485 // CHECK17-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 5486 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5487 // CHECK17-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 5488 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5489 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i8* 5490 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i8* 5491 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]]) 5492 // CHECK17-NEXT: ret void 5493 // 5494 // 5495 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 5496 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { 5497 // CHECK17-NEXT: entry: 5498 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5499 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5500 // CHECK17-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 8 5501 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 5502 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5503 // CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1 5504 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 5505 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 5506 // CHECK17-NEXT: [[I4:%.*]] = alloca i8, align 1 5507 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5508 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5509 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5510 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5511 // CHECK17-NEXT: [[I6:%.*]] = alloca i8, align 1 5512 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5513 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5514 // CHECK17-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 8 5515 // CHECK17-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 5516 // CHECK17-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 8 5517 // CHECK17-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 8 5518 // CHECK17-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1 5519 // CHECK17-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1 5520 // CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 5521 // CHECK17-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 5522 // CHECK17-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 5523 // CHECK17-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 5524 // CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 5525 // CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 5526 // CHECK17-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 5527 // CHECK17-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 5528 // CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 5529 // CHECK17-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1 5530 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 5531 // CHECK17-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 5532 // CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 5533 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 5534 // CHECK17: omp.precond.then: 5535 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5536 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 5537 // CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 5538 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5539 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5540 // CHECK17-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5541 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 5542 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5543 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5544 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 5545 // CHECK17-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] 5546 // CHECK17-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5547 // CHECK17: cond.true: 5548 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 5549 // CHECK17-NEXT: br label [[COND_END:%.*]] 5550 // CHECK17: cond.false: 5551 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5552 // CHECK17-NEXT: br label [[COND_END]] 5553 // CHECK17: cond.end: 5554 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 5555 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5556 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5557 // CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 5558 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5559 // CHECK17: omp.inner.for.cond: 5560 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 5561 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 5562 // CHECK17-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 5563 // CHECK17-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5564 // CHECK17: omp.inner.for.body: 5565 // CHECK17-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21 5566 // CHECK17-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32 5567 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 5568 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 5569 // CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 5570 // CHECK17-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 5571 // CHECK17-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !21 5572 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5573 // CHECK17: omp.body.continue: 5574 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5575 // CHECK17: omp.inner.for.inc: 5576 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 5577 // CHECK17-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 5578 // CHECK17-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 5579 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 5580 // CHECK17: omp.inner.for.end: 5581 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5582 // CHECK17: omp.loop.exit: 5583 // CHECK17-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5584 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 5585 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) 5586 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5587 // CHECK17-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 5588 // CHECK17-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5589 // CHECK17: .omp.final.then: 5590 // CHECK17-NEXT: [[TMP23:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 5591 // CHECK17-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32 5592 // CHECK17-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 5593 // CHECK17-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32 5594 // CHECK17-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]] 5595 // CHECK17-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1 5596 // CHECK17-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1 5597 // CHECK17-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1 5598 // CHECK17-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1 5599 // CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]] 5600 // CHECK17-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 5601 // CHECK17-NEXT: store i8 [[CONV21]], i8* [[TMP0]], align 1 5602 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 5603 // CHECK17: .omp.final.done: 5604 // CHECK17-NEXT: br label [[OMP_PRECOND_END]] 5605 // CHECK17: omp.precond.end: 5606 // CHECK17-NEXT: ret void 5607 // 5608 // 5609 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 5610 // CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 5611 // CHECK17-NEXT: entry: 5612 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5613 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5614 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5615 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) 5616 // CHECK17-NEXT: ret void 5617 // 5618 // 5619 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 5620 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { 5621 // CHECK17-NEXT: entry: 5622 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5623 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5624 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 5625 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5626 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 5627 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5628 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5629 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5630 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5631 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 5632 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5633 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5634 // CHECK17-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 5635 // CHECK17-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 5636 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5637 // CHECK17-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 5638 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5639 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5640 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 5641 // CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 5642 // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5643 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 5644 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 5645 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 5646 // CHECK17: omp.dispatch.cond: 5647 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5648 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 5649 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5650 // CHECK17: cond.true: 5651 // CHECK17-NEXT: br label [[COND_END:%.*]] 5652 // CHECK17: cond.false: 5653 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5654 // CHECK17-NEXT: br label [[COND_END]] 5655 // CHECK17: cond.end: 5656 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 5657 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5658 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5659 // CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 5660 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5661 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5662 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 5663 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 5664 // CHECK17: omp.dispatch.body: 5665 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5666 // CHECK17: omp.inner.for.cond: 5667 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 5668 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 5669 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 5670 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5671 // CHECK17: omp.inner.for.body: 5672 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 5673 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 5674 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 5675 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 5676 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5677 // CHECK17: omp.body.continue: 5678 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5679 // CHECK17: omp.inner.for.inc: 5680 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 5681 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 5682 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 5683 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 5684 // CHECK17: omp.inner.for.end: 5685 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 5686 // CHECK17: omp.dispatch.inc: 5687 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5688 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 5689 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 5690 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 5691 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5692 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 5693 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 5694 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 5695 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 5696 // CHECK17: omp.dispatch.end: 5697 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 5698 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5699 // CHECK17-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 5700 // CHECK17-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5701 // CHECK17: .omp.final.then: 5702 // CHECK17-NEXT: store i32 100, i32* [[I]], align 4 5703 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 5704 // CHECK17: .omp.final.done: 5705 // CHECK17-NEXT: ret void 5706 // 5707 // 5708 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 5709 // CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 5710 // CHECK19-NEXT: entry: 5711 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 5712 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 5713 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 5714 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 5715 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 5716 // CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 5717 // CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 5718 // CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 5719 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 5720 // CHECK19-NEXT: ret void 5721 // 5722 // 5723 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 5724 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 5725 // CHECK19-NEXT: entry: 5726 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5727 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5728 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 5729 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 5730 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 5731 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 5732 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5733 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 5734 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5735 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5736 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5737 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5738 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 5739 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5740 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5741 // CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 5742 // CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 5743 // CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 5744 // CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 5745 // CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 5746 // CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 5747 // CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 5748 // CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 5749 // CHECK19-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 4 5750 // CHECK19-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i32 16) ] 5751 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5752 // CHECK19-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 5753 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5754 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5755 // CHECK19-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5756 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 5757 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5758 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5759 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 5760 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5761 // CHECK19: cond.true: 5762 // CHECK19-NEXT: br label [[COND_END:%.*]] 5763 // CHECK19: cond.false: 5764 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5765 // CHECK19-NEXT: br label [[COND_END]] 5766 // CHECK19: cond.end: 5767 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 5768 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5769 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5770 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 5771 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5772 // CHECK19: omp.inner.for.cond: 5773 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 5774 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 5775 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 5776 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5777 // CHECK19: omp.inner.for.body: 5778 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 5779 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 5780 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 5781 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 5782 // CHECK19-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10 5783 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 5784 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]] 5785 // CHECK19-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 5786 // CHECK19-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10 5787 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 5788 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP16]], i32 [[TMP17]] 5789 // CHECK19-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !10 5790 // CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]] 5791 // CHECK19-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10 5792 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 5793 // CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP19]], i32 [[TMP20]] 5794 // CHECK19-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !10 5795 // CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]] 5796 // CHECK19-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10 5797 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 5798 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP22]], i32 [[TMP23]] 5799 // CHECK19-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !10 5800 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5801 // CHECK19: omp.body.continue: 5802 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5803 // CHECK19: omp.inner.for.inc: 5804 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 5805 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1 5806 // CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 5807 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 5808 // CHECK19: omp.inner.for.end: 5809 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5810 // CHECK19: omp.loop.exit: 5811 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]]) 5812 // CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5813 // CHECK19-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 5814 // CHECK19-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5815 // CHECK19: .omp.final.then: 5816 // CHECK19-NEXT: store i32 32000001, i32* [[I]], align 4 5817 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 5818 // CHECK19: .omp.final.done: 5819 // CHECK19-NEXT: ret void 5820 // 5821 // 5822 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 5823 // CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 5824 // CHECK19-NEXT: entry: 5825 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 5826 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 5827 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 5828 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 5829 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 5830 // CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 5831 // CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 5832 // CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 5833 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 5834 // CHECK19-NEXT: ret void 5835 // 5836 // 5837 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 5838 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 5839 // CHECK19-NEXT: entry: 5840 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5841 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5842 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 5843 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 5844 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 5845 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 5846 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5847 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 5848 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5849 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5850 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5851 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5852 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 5853 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5854 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5855 // CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 5856 // CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 5857 // CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 5858 // CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 5859 // CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 5860 // CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 5861 // CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 5862 // CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 5863 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5864 // CHECK19-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 5865 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5866 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5867 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5868 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 5869 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5870 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5871 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 5872 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5873 // CHECK19: cond.true: 5874 // CHECK19-NEXT: br label [[COND_END:%.*]] 5875 // CHECK19: cond.false: 5876 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5877 // CHECK19-NEXT: br label [[COND_END]] 5878 // CHECK19: cond.end: 5879 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 5880 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5881 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5882 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 5883 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5884 // CHECK19: omp.inner.for.cond: 5885 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5886 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5887 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 5888 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5889 // CHECK19: omp.inner.for.body: 5890 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5891 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 5892 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 5893 // CHECK19-NEXT: store i32 [[SUB]], i32* [[I]], align 4 5894 // CHECK19-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4 5895 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 5896 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 5897 // CHECK19-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 5898 // CHECK19-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 5899 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 5900 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 5901 // CHECK19-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 5902 // CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 5903 // CHECK19-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 5904 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 5905 // CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 5906 // CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 5907 // CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 5908 // CHECK19-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4 5909 // CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 5910 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 5911 // CHECK19-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 5912 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5913 // CHECK19: omp.body.continue: 5914 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5915 // CHECK19: omp.inner.for.inc: 5916 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5917 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 5918 // CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 5919 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] 5920 // CHECK19: omp.inner.for.end: 5921 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5922 // CHECK19: omp.loop.exit: 5923 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 5924 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5925 // CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 5926 // CHECK19-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5927 // CHECK19: .omp.final.then: 5928 // CHECK19-NEXT: store i32 32, i32* [[I]], align 4 5929 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 5930 // CHECK19: .omp.final.done: 5931 // CHECK19-NEXT: ret void 5932 // 5933 // 5934 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 5935 // CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 5936 // CHECK19-NEXT: entry: 5937 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 5938 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 5939 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 5940 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 5941 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 5942 // CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 5943 // CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 5944 // CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 5945 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 5946 // CHECK19-NEXT: ret void 5947 // 5948 // 5949 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 5950 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 5951 // CHECK19-NEXT: entry: 5952 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5953 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5954 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 5955 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 5956 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 5957 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 5958 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5959 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 5960 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5961 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5962 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5963 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5964 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 5965 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5966 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5967 // CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 5968 // CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 5969 // CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 5970 // CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 5971 // CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 5972 // CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 5973 // CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 5974 // CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 5975 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5976 // CHECK19-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 5977 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5978 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5979 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5980 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 5981 // CHECK19-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 5982 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 5983 // CHECK19: omp.dispatch.cond: 5984 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5985 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 5986 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5987 // CHECK19: cond.true: 5988 // CHECK19-NEXT: br label [[COND_END:%.*]] 5989 // CHECK19: cond.false: 5990 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5991 // CHECK19-NEXT: br label [[COND_END]] 5992 // CHECK19: cond.end: 5993 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 5994 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5995 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5996 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 5997 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5998 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5999 // CHECK19-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 6000 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6001 // CHECK19: omp.dispatch.body: 6002 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6003 // CHECK19: omp.inner.for.cond: 6004 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 6005 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 6006 // CHECK19-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 6007 // CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6008 // CHECK19: omp.inner.for.body: 6009 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 6010 // CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 6011 // CHECK19-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 6012 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 6013 // CHECK19-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !19 6014 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 6015 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] 6016 // CHECK19-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !19 6017 // CHECK19-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !19 6018 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 6019 // CHECK19-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] 6020 // CHECK19-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !19 6021 // CHECK19-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] 6022 // CHECK19-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !19 6023 // CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 6024 // CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] 6025 // CHECK19-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !19 6026 // CHECK19-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] 6027 // CHECK19-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !19 6028 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 6029 // CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] 6030 // CHECK19-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !19 6031 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6032 // CHECK19: omp.body.continue: 6033 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6034 // CHECK19: omp.inner.for.inc: 6035 // CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 6036 // CHECK19-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 6037 // CHECK19-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 6038 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 6039 // CHECK19: omp.inner.for.end: 6040 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6041 // CHECK19: omp.dispatch.inc: 6042 // CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6043 // CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6044 // CHECK19-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] 6045 // CHECK19-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 6046 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6047 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6048 // CHECK19-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] 6049 // CHECK19-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 6050 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 6051 // CHECK19: omp.dispatch.end: 6052 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 6053 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6054 // CHECK19-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 6055 // CHECK19-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6056 // CHECK19: .omp.final.then: 6057 // CHECK19-NEXT: store i32 -2147483522, i32* [[I]], align 4 6058 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 6059 // CHECK19: .omp.final.done: 6060 // CHECK19-NEXT: ret void 6061 // 6062 // 6063 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 6064 // CHECK19-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 6065 // CHECK19-NEXT: entry: 6066 // CHECK19-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 6067 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6068 // CHECK19-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 6069 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6070 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[I_ADDR]] to i8* 6071 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_ADDR]] to i8* 6072 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]]) 6073 // CHECK19-NEXT: ret void 6074 // 6075 // 6076 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 6077 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { 6078 // CHECK19-NEXT: entry: 6079 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6080 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6081 // CHECK19-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 4 6082 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 6083 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6084 // CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1 6085 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 6086 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 6087 // CHECK19-NEXT: [[I4:%.*]] = alloca i8, align 1 6088 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6089 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6090 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6091 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6092 // CHECK19-NEXT: [[I6:%.*]] = alloca i8, align 1 6093 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6094 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6095 // CHECK19-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 4 6096 // CHECK19-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 6097 // CHECK19-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 4 6098 // CHECK19-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 4 6099 // CHECK19-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1 6100 // CHECK19-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1 6101 // CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6102 // CHECK19-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 6103 // CHECK19-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 6104 // CHECK19-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 6105 // CHECK19-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 6106 // CHECK19-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 6107 // CHECK19-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 6108 // CHECK19-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 6109 // CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6110 // CHECK19-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1 6111 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6112 // CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 6113 // CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 6114 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 6115 // CHECK19: omp.precond.then: 6116 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6117 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 6118 // CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 6119 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6120 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6121 // CHECK19-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6122 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 6123 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6124 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6125 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 6126 // CHECK19-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] 6127 // CHECK19-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6128 // CHECK19: cond.true: 6129 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 6130 // CHECK19-NEXT: br label [[COND_END:%.*]] 6131 // CHECK19: cond.false: 6132 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6133 // CHECK19-NEXT: br label [[COND_END]] 6134 // CHECK19: cond.end: 6135 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 6136 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6137 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6138 // CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 6139 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6140 // CHECK19: omp.inner.for.cond: 6141 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 6142 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 6143 // CHECK19-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 6144 // CHECK19-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6145 // CHECK19: omp.inner.for.body: 6146 // CHECK19-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22 6147 // CHECK19-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32 6148 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 6149 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 6150 // CHECK19-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 6151 // CHECK19-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 6152 // CHECK19-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !22 6153 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6154 // CHECK19: omp.body.continue: 6155 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6156 // CHECK19: omp.inner.for.inc: 6157 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 6158 // CHECK19-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 6159 // CHECK19-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 6160 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] 6161 // CHECK19: omp.inner.for.end: 6162 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6163 // CHECK19: omp.loop.exit: 6164 // CHECK19-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6165 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 6166 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) 6167 // CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6168 // CHECK19-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 6169 // CHECK19-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6170 // CHECK19: .omp.final.then: 6171 // CHECK19-NEXT: [[TMP23:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6172 // CHECK19-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32 6173 // CHECK19-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6174 // CHECK19-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32 6175 // CHECK19-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]] 6176 // CHECK19-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1 6177 // CHECK19-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1 6178 // CHECK19-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1 6179 // CHECK19-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1 6180 // CHECK19-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]] 6181 // CHECK19-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 6182 // CHECK19-NEXT: store i8 [[CONV21]], i8* [[TMP0]], align 1 6183 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 6184 // CHECK19: .omp.final.done: 6185 // CHECK19-NEXT: br label [[OMP_PRECOND_END]] 6186 // CHECK19: omp.precond.end: 6187 // CHECK19-NEXT: ret void 6188 // 6189 // 6190 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 6191 // CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 6192 // CHECK19-NEXT: entry: 6193 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6194 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6195 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6196 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) 6197 // CHECK19-NEXT: ret void 6198 // 6199 // 6200 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 6201 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { 6202 // CHECK19-NEXT: entry: 6203 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6204 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6205 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 6206 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6207 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 6208 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6209 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6210 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6211 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6212 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 6213 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6214 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6215 // CHECK19-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 6216 // CHECK19-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 6217 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6218 // CHECK19-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 6219 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6220 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6221 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 6222 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 6223 // CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6224 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 6225 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 6226 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6227 // CHECK19: omp.dispatch.cond: 6228 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6229 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 6230 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6231 // CHECK19: cond.true: 6232 // CHECK19-NEXT: br label [[COND_END:%.*]] 6233 // CHECK19: cond.false: 6234 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6235 // CHECK19-NEXT: br label [[COND_END]] 6236 // CHECK19: cond.end: 6237 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 6238 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6239 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6240 // CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 6241 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6242 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6243 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 6244 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6245 // CHECK19: omp.dispatch.body: 6246 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6247 // CHECK19: omp.inner.for.cond: 6248 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 6249 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 6250 // CHECK19-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 6251 // CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6252 // CHECK19: omp.inner.for.body: 6253 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 6254 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 6255 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 6256 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25 6257 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6258 // CHECK19: omp.body.continue: 6259 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6260 // CHECK19: omp.inner.for.inc: 6261 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 6262 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 6263 // CHECK19-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 6264 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] 6265 // CHECK19: omp.inner.for.end: 6266 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6267 // CHECK19: omp.dispatch.inc: 6268 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6269 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6270 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 6271 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 6272 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6273 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6274 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 6275 // CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 6276 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 6277 // CHECK19: omp.dispatch.end: 6278 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 6279 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6280 // CHECK19-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 6281 // CHECK19-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6282 // CHECK19: .omp.final.then: 6283 // CHECK19-NEXT: store i32 100, i32* [[I]], align 4 6284 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 6285 // CHECK19: .omp.final.done: 6286 // CHECK19-NEXT: ret void 6287 // 6288 // 6289 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 6290 // CHECK21-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 6291 // CHECK21-NEXT: entry: 6292 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6293 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6294 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6295 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6296 // CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6297 // CHECK21-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6298 // CHECK21-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6299 // CHECK21-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6300 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 6301 // CHECK21-NEXT: ret void 6302 // 6303 // 6304 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. 6305 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 6306 // CHECK21-NEXT: entry: 6307 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6308 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6309 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 6310 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 6311 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 6312 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 6313 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6314 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 6315 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6316 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6317 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6318 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6319 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 6320 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6321 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6322 // CHECK21-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 6323 // CHECK21-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 6324 // CHECK21-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 6325 // CHECK21-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 6326 // CHECK21-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 6327 // CHECK21-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 6328 // CHECK21-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 6329 // CHECK21-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 6330 // CHECK21-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 8 6331 // CHECK21-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i64 16) ] 6332 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6333 // CHECK21-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 6334 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6335 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6336 // CHECK21-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6337 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 6338 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6339 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6340 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 6341 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6342 // CHECK21: cond.true: 6343 // CHECK21-NEXT: br label [[COND_END:%.*]] 6344 // CHECK21: cond.false: 6345 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6346 // CHECK21-NEXT: br label [[COND_END]] 6347 // CHECK21: cond.end: 6348 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 6349 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6350 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6351 // CHECK21-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 6352 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6353 // CHECK21: omp.inner.for.cond: 6354 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 6355 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 6356 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 6357 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6358 // CHECK21: omp.inner.for.body: 6359 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 6360 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 6361 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 6362 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 6363 // CHECK21-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9 6364 // CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 6365 // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 6366 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]] 6367 // CHECK21-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 6368 // CHECK21-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9 6369 // CHECK21-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 6370 // CHECK21-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64 6371 // CHECK21-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM2]] 6372 // CHECK21-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !9 6373 // CHECK21-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]] 6374 // CHECK21-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9 6375 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 6376 // CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64 6377 // CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM5]] 6378 // CHECK21-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !llvm.access.group !9 6379 // CHECK21-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]] 6380 // CHECK21-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9 6381 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 6382 // CHECK21-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64 6383 // CHECK21-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM8]] 6384 // CHECK21-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !9 6385 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6386 // CHECK21: omp.body.continue: 6387 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6388 // CHECK21: omp.inner.for.inc: 6389 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 6390 // CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 6391 // CHECK21-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 6392 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 6393 // CHECK21: omp.inner.for.end: 6394 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6395 // CHECK21: omp.loop.exit: 6396 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]]) 6397 // CHECK21-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6398 // CHECK21-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 6399 // CHECK21-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6400 // CHECK21: .omp.final.then: 6401 // CHECK21-NEXT: store i32 32000001, i32* [[I]], align 4 6402 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 6403 // CHECK21: .omp.final.done: 6404 // CHECK21-NEXT: ret void 6405 // 6406 // 6407 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 6408 // CHECK21-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 6409 // CHECK21-NEXT: entry: 6410 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6411 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6412 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6413 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6414 // CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6415 // CHECK21-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6416 // CHECK21-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6417 // CHECK21-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6418 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 6419 // CHECK21-NEXT: ret void 6420 // 6421 // 6422 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1 6423 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 6424 // CHECK21-NEXT: entry: 6425 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6426 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6427 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 6428 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 6429 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 6430 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 6431 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6432 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 6433 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6434 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6435 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6436 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6437 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 6438 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6439 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6440 // CHECK21-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 6441 // CHECK21-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 6442 // CHECK21-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 6443 // CHECK21-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 6444 // CHECK21-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 6445 // CHECK21-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 6446 // CHECK21-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 6447 // CHECK21-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 6448 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6449 // CHECK21-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 6450 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6451 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6452 // CHECK21-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6453 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 6454 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6455 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6456 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 6457 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6458 // CHECK21: cond.true: 6459 // CHECK21-NEXT: br label [[COND_END:%.*]] 6460 // CHECK21: cond.false: 6461 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6462 // CHECK21-NEXT: br label [[COND_END]] 6463 // CHECK21: cond.end: 6464 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 6465 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6466 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6467 // CHECK21-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 6468 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6469 // CHECK21: omp.inner.for.cond: 6470 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6471 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6472 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 6473 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6474 // CHECK21: omp.inner.for.body: 6475 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6476 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 6477 // CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 6478 // CHECK21-NEXT: store i32 [[SUB]], i32* [[I]], align 4 6479 // CHECK21-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8, !nontemporal !16 6480 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 6481 // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 6482 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 6483 // CHECK21-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 6484 // CHECK21-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 6485 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 6486 // CHECK21-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 6487 // CHECK21-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 6488 // CHECK21-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 6489 // CHECK21-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 6490 // CHECK21-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 6491 // CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 6492 // CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 6493 // CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 6494 // CHECK21-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 6495 // CHECK21-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 6496 // CHECK21-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8, !nontemporal !16 6497 // CHECK21-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 6498 // CHECK21-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 6499 // CHECK21-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 6500 // CHECK21-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 6501 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6502 // CHECK21: omp.body.continue: 6503 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6504 // CHECK21: omp.inner.for.inc: 6505 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6506 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 6507 // CHECK21-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 6508 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] 6509 // CHECK21: omp.inner.for.end: 6510 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6511 // CHECK21: omp.loop.exit: 6512 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 6513 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6514 // CHECK21-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 6515 // CHECK21-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6516 // CHECK21: .omp.final.then: 6517 // CHECK21-NEXT: store i32 32, i32* [[I]], align 4 6518 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 6519 // CHECK21: .omp.final.done: 6520 // CHECK21-NEXT: ret void 6521 // 6522 // 6523 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 6524 // CHECK21-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 6525 // CHECK21-NEXT: entry: 6526 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6527 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6528 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6529 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6530 // CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6531 // CHECK21-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6532 // CHECK21-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6533 // CHECK21-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6534 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 6535 // CHECK21-NEXT: ret void 6536 // 6537 // 6538 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2 6539 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { 6540 // CHECK21-NEXT: entry: 6541 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6542 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6543 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 6544 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 6545 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 6546 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 6547 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6548 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 6549 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6550 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6551 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6552 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6553 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 6554 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6555 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6556 // CHECK21-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 6557 // CHECK21-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 6558 // CHECK21-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 6559 // CHECK21-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 6560 // CHECK21-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 6561 // CHECK21-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 6562 // CHECK21-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 6563 // CHECK21-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 6564 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6565 // CHECK21-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 6566 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6567 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6568 // CHECK21-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6569 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 6570 // CHECK21-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 6571 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6572 // CHECK21: omp.dispatch.cond: 6573 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6574 // CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 6575 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6576 // CHECK21: cond.true: 6577 // CHECK21-NEXT: br label [[COND_END:%.*]] 6578 // CHECK21: cond.false: 6579 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6580 // CHECK21-NEXT: br label [[COND_END]] 6581 // CHECK21: cond.end: 6582 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 6583 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6584 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6585 // CHECK21-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 6586 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6587 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6588 // CHECK21-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 6589 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6590 // CHECK21: omp.dispatch.body: 6591 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6592 // CHECK21: omp.inner.for.cond: 6593 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 6594 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 6595 // CHECK21-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 6596 // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6597 // CHECK21: omp.inner.for.body: 6598 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 6599 // CHECK21-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 6600 // CHECK21-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 6601 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 6602 // CHECK21-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !19 6603 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 6604 // CHECK21-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 6605 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 6606 // CHECK21-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !19 6607 // CHECK21-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !19 6608 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 6609 // CHECK21-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 6610 // CHECK21-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 6611 // CHECK21-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !19 6612 // CHECK21-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 6613 // CHECK21-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !19 6614 // CHECK21-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 6615 // CHECK21-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 6616 // CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 6617 // CHECK21-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !19 6618 // CHECK21-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 6619 // CHECK21-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !19 6620 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 6621 // CHECK21-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 6622 // CHECK21-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 6623 // CHECK21-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !19 6624 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6625 // CHECK21: omp.body.continue: 6626 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6627 // CHECK21: omp.inner.for.inc: 6628 // CHECK21-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 6629 // CHECK21-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 6630 // CHECK21-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 6631 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 6632 // CHECK21: omp.inner.for.end: 6633 // CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6634 // CHECK21: omp.dispatch.inc: 6635 // CHECK21-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6636 // CHECK21-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6637 // CHECK21-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 6638 // CHECK21-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 6639 // CHECK21-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6640 // CHECK21-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6641 // CHECK21-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 6642 // CHECK21-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 6643 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND]] 6644 // CHECK21: omp.dispatch.end: 6645 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 6646 // CHECK21-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6647 // CHECK21-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 6648 // CHECK21-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6649 // CHECK21: .omp.final.then: 6650 // CHECK21-NEXT: store i32 -2147483522, i32* [[I]], align 4 6651 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 6652 // CHECK21: .omp.final.done: 6653 // CHECK21-NEXT: ret void 6654 // 6655 // 6656 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 6657 // CHECK21-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 6658 // CHECK21-NEXT: entry: 6659 // CHECK21-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 6660 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6661 // CHECK21-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 6662 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6663 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i8* 6664 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i8* 6665 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]]) 6666 // CHECK21-NEXT: ret void 6667 // 6668 // 6669 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3 6670 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { 6671 // CHECK21-NEXT: entry: 6672 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6673 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6674 // CHECK21-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 8 6675 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8 6676 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6677 // CHECK21-NEXT: [[TMP:%.*]] = alloca i8, align 1 6678 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 6679 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 6680 // CHECK21-NEXT: [[I4:%.*]] = alloca i8, align 1 6681 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6682 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6683 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6684 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6685 // CHECK21-NEXT: [[I6:%.*]] = alloca i8, align 1 6686 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6687 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6688 // CHECK21-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 8 6689 // CHECK21-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8 6690 // CHECK21-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 8 6691 // CHECK21-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 8 6692 // CHECK21-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1 6693 // CHECK21-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1 6694 // CHECK21-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6695 // CHECK21-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 6696 // CHECK21-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 6697 // CHECK21-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 6698 // CHECK21-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 6699 // CHECK21-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 6700 // CHECK21-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 6701 // CHECK21-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 6702 // CHECK21-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6703 // CHECK21-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1 6704 // CHECK21-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6705 // CHECK21-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 6706 // CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 6707 // CHECK21-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 6708 // CHECK21: omp.precond.then: 6709 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6710 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 6711 // CHECK21-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 6712 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6713 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6714 // CHECK21-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6715 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 6716 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6717 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6718 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 6719 // CHECK21-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] 6720 // CHECK21-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6721 // CHECK21: cond.true: 6722 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 6723 // CHECK21-NEXT: br label [[COND_END:%.*]] 6724 // CHECK21: cond.false: 6725 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6726 // CHECK21-NEXT: br label [[COND_END]] 6727 // CHECK21: cond.end: 6728 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 6729 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6730 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6731 // CHECK21-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 6732 // CHECK21-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP1]], align 1 6733 // CHECK21-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0 6734 // CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6735 // CHECK21: omp_if.then: 6736 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6737 // CHECK21: omp.inner.for.cond: 6738 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 6739 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 6740 // CHECK21-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 6741 // CHECK21-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6742 // CHECK21: omp.inner.for.body: 6743 // CHECK21-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22 6744 // CHECK21-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32 6745 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 6746 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 6747 // CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 6748 // CHECK21-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 6749 // CHECK21-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !16, !llvm.access.group !22 6750 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6751 // CHECK21: omp.body.continue: 6752 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6753 // CHECK21: omp.inner.for.inc: 6754 // CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 6755 // CHECK21-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 6756 // CHECK21-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 6757 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] 6758 // CHECK21: omp.inner.for.end: 6759 // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] 6760 // CHECK21: omp_if.else: 6761 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 6762 // CHECK21: omp.inner.for.cond13: 6763 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6764 // CHECK21-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6765 // CHECK21-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] 6766 // CHECK21-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]] 6767 // CHECK21: omp.inner.for.body15: 6768 // CHECK21-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6769 // CHECK21-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32 6770 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6771 // CHECK21-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1 6772 // CHECK21-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]] 6773 // CHECK21-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 6774 // CHECK21-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1 6775 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]] 6776 // CHECK21: omp.body.continue20: 6777 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]] 6778 // CHECK21: omp.inner.for.inc21: 6779 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6780 // CHECK21-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1 6781 // CHECK21-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4 6782 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]] 6783 // CHECK21: omp.inner.for.end23: 6784 // CHECK21-NEXT: br label [[OMP_IF_END]] 6785 // CHECK21: omp_if.end: 6786 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6787 // CHECK21: omp.loop.exit: 6788 // CHECK21-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6789 // CHECK21-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 6790 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 6791 // CHECK21-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6792 // CHECK21-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 6793 // CHECK21-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6794 // CHECK21: .omp.final.then: 6795 // CHECK21-NEXT: [[TMP29:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6796 // CHECK21-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32 6797 // CHECK21-NEXT: [[TMP30:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6798 // CHECK21-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32 6799 // CHECK21-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]] 6800 // CHECK21-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1 6801 // CHECK21-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1 6802 // CHECK21-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1 6803 // CHECK21-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1 6804 // CHECK21-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]] 6805 // CHECK21-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8 6806 // CHECK21-NEXT: store i8 [[CONV32]], i8* [[TMP0]], align 1 6807 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 6808 // CHECK21: .omp.final.done: 6809 // CHECK21-NEXT: br label [[OMP_PRECOND_END]] 6810 // CHECK21: omp.precond.end: 6811 // CHECK21-NEXT: ret void 6812 // 6813 // 6814 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 6815 // CHECK21-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 6816 // CHECK21-NEXT: entry: 6817 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6818 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6819 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6820 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) 6821 // CHECK21-NEXT: ret void 6822 // 6823 // 6824 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4 6825 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { 6826 // CHECK21-NEXT: entry: 6827 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6828 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6829 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 6830 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6831 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 6832 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6833 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6834 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6835 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6836 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 6837 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6838 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6839 // CHECK21-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 6840 // CHECK21-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 6841 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6842 // CHECK21-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 6843 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6844 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6845 // CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 6846 // CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 6847 // CHECK21-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6848 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 6849 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 6850 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6851 // CHECK21: omp.dispatch.cond: 6852 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6853 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 6854 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6855 // CHECK21: cond.true: 6856 // CHECK21-NEXT: br label [[COND_END:%.*]] 6857 // CHECK21: cond.false: 6858 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6859 // CHECK21-NEXT: br label [[COND_END]] 6860 // CHECK21: cond.end: 6861 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 6862 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6863 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6864 // CHECK21-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 6865 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6866 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6867 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 6868 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6869 // CHECK21: omp.dispatch.body: 6870 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6871 // CHECK21: omp.inner.for.cond: 6872 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 6873 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 6874 // CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 6875 // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6876 // CHECK21: omp.inner.for.body: 6877 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 6878 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 6879 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 6880 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 6881 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6882 // CHECK21: omp.body.continue: 6883 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6884 // CHECK21: omp.inner.for.inc: 6885 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 6886 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 6887 // CHECK21-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 6888 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 6889 // CHECK21: omp.inner.for.end: 6890 // CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6891 // CHECK21: omp.dispatch.inc: 6892 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6893 // CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6894 // CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 6895 // CHECK21-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 6896 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6897 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6898 // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 6899 // CHECK21-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 6900 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND]] 6901 // CHECK21: omp.dispatch.end: 6902 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 6903 // CHECK21-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6904 // CHECK21-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 6905 // CHECK21-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6906 // CHECK21: .omp.final.then: 6907 // CHECK21-NEXT: store i32 100, i32* [[I]], align 4 6908 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 6909 // CHECK21: .omp.final.done: 6910 // CHECK21-NEXT: ret void 6911 // 6912 // 6913 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 6914 // CHECK23-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { 6915 // CHECK23-NEXT: entry: 6916 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 6917 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 6918 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 6919 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 6920 // CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 6921 // CHECK23-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 6922 // CHECK23-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 6923 // CHECK23-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 6924 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 6925 // CHECK23-NEXT: ret void 6926 // 6927 // 6928 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined. 6929 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 6930 // CHECK23-NEXT: entry: 6931 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6932 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6933 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 6934 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 6935 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 6936 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 6937 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6938 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 6939 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6940 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6941 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6942 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6943 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 6944 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6945 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6946 // CHECK23-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 6947 // CHECK23-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 6948 // CHECK23-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 6949 // CHECK23-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 6950 // CHECK23-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 6951 // CHECK23-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 6952 // CHECK23-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 6953 // CHECK23-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 6954 // CHECK23-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 4 6955 // CHECK23-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i32 16) ] 6956 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6957 // CHECK23-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 6958 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6959 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6960 // CHECK23-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6961 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 6962 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6963 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6964 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423 6965 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6966 // CHECK23: cond.true: 6967 // CHECK23-NEXT: br label [[COND_END:%.*]] 6968 // CHECK23: cond.false: 6969 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6970 // CHECK23-NEXT: br label [[COND_END]] 6971 // CHECK23: cond.end: 6972 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 6973 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6974 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6975 // CHECK23-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 6976 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6977 // CHECK23: omp.inner.for.cond: 6978 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 6979 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 6980 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 6981 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6982 // CHECK23: omp.inner.for.body: 6983 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 6984 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 6985 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 6986 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 6987 // CHECK23-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10 6988 // CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 6989 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]] 6990 // CHECK23-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 6991 // CHECK23-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10 6992 // CHECK23-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 6993 // CHECK23-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP16]], i32 [[TMP17]] 6994 // CHECK23-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !10 6995 // CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]] 6996 // CHECK23-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10 6997 // CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 6998 // CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP19]], i32 [[TMP20]] 6999 // CHECK23-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !10 7000 // CHECK23-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]] 7001 // CHECK23-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10 7002 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 7003 // CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP22]], i32 [[TMP23]] 7004 // CHECK23-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !10 7005 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7006 // CHECK23: omp.body.continue: 7007 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7008 // CHECK23: omp.inner.for.inc: 7009 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 7010 // CHECK23-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1 7011 // CHECK23-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 7012 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 7013 // CHECK23: omp.inner.for.end: 7014 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7015 // CHECK23: omp.loop.exit: 7016 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]]) 7017 // CHECK23-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 7018 // CHECK23-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 7019 // CHECK23-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 7020 // CHECK23: .omp.final.then: 7021 // CHECK23-NEXT: store i32 32000001, i32* [[I]], align 4 7022 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 7023 // CHECK23: .omp.final.done: 7024 // CHECK23-NEXT: ret void 7025 // 7026 // 7027 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 7028 // CHECK23-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 7029 // CHECK23-NEXT: entry: 7030 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 7031 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 7032 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 7033 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 7034 // CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 7035 // CHECK23-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 7036 // CHECK23-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 7037 // CHECK23-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 7038 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 7039 // CHECK23-NEXT: ret void 7040 // 7041 // 7042 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1 7043 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 7044 // CHECK23-NEXT: entry: 7045 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7046 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7047 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 7048 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 7049 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 7050 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 7051 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7052 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 7053 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7054 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7055 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7056 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7057 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 7058 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7059 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7060 // CHECK23-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 7061 // CHECK23-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 7062 // CHECK23-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 7063 // CHECK23-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 7064 // CHECK23-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 7065 // CHECK23-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 7066 // CHECK23-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 7067 // CHECK23-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 7068 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7069 // CHECK23-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 7070 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7071 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7072 // CHECK23-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 7073 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 7074 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 7075 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7076 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 7077 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7078 // CHECK23: cond.true: 7079 // CHECK23-NEXT: br label [[COND_END:%.*]] 7080 // CHECK23: cond.false: 7081 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7082 // CHECK23-NEXT: br label [[COND_END]] 7083 // CHECK23: cond.end: 7084 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 7085 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7086 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7087 // CHECK23-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 7088 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7089 // CHECK23: omp.inner.for.cond: 7090 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7091 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7092 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 7093 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7094 // CHECK23: omp.inner.for.body: 7095 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7096 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 7097 // CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 7098 // CHECK23-NEXT: store i32 [[SUB]], i32* [[I]], align 4 7099 // CHECK23-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4, !nontemporal !17 7100 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 7101 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]] 7102 // CHECK23-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 7103 // CHECK23-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4 7104 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 7105 // CHECK23-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]] 7106 // CHECK23-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7107 // CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] 7108 // CHECK23-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4 7109 // CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 7110 // CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]] 7111 // CHECK23-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4 7112 // CHECK23-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] 7113 // CHECK23-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4, !nontemporal !17 7114 // CHECK23-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 7115 // CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]] 7116 // CHECK23-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 7117 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7118 // CHECK23: omp.body.continue: 7119 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7120 // CHECK23: omp.inner.for.inc: 7121 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7122 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 7123 // CHECK23-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 7124 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 7125 // CHECK23: omp.inner.for.end: 7126 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7127 // CHECK23: omp.loop.exit: 7128 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 7129 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 7130 // CHECK23-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 7131 // CHECK23-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 7132 // CHECK23: .omp.final.then: 7133 // CHECK23-NEXT: store i32 32, i32* [[I]], align 4 7134 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 7135 // CHECK23: .omp.final.done: 7136 // CHECK23-NEXT: ret void 7137 // 7138 // 7139 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 7140 // CHECK23-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 7141 // CHECK23-NEXT: entry: 7142 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 7143 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 7144 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 7145 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 7146 // CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 7147 // CHECK23-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 7148 // CHECK23-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 7149 // CHECK23-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 7150 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 7151 // CHECK23-NEXT: ret void 7152 // 7153 // 7154 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2 7155 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { 7156 // CHECK23-NEXT: entry: 7157 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7158 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7159 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4 7160 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4 7161 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4 7162 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4 7163 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7164 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 7165 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7166 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7167 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7168 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7169 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 7170 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7171 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7172 // CHECK23-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4 7173 // CHECK23-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4 7174 // CHECK23-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4 7175 // CHECK23-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4 7176 // CHECK23-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4 7177 // CHECK23-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4 7178 // CHECK23-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4 7179 // CHECK23-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4 7180 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7181 // CHECK23-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 7182 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7183 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7184 // CHECK23-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 7185 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 7186 // CHECK23-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 7187 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 7188 // CHECK23: omp.dispatch.cond: 7189 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7190 // CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 7191 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7192 // CHECK23: cond.true: 7193 // CHECK23-NEXT: br label [[COND_END:%.*]] 7194 // CHECK23: cond.false: 7195 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7196 // CHECK23-NEXT: br label [[COND_END]] 7197 // CHECK23: cond.end: 7198 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 7199 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7200 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7201 // CHECK23-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 7202 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7203 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7204 // CHECK23-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 7205 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 7206 // CHECK23: omp.dispatch.body: 7207 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7208 // CHECK23: omp.inner.for.cond: 7209 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 7210 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20 7211 // CHECK23-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 7212 // CHECK23-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7213 // CHECK23: omp.inner.for.body: 7214 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 7215 // CHECK23-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 7216 // CHECK23-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 7217 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20 7218 // CHECK23-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !20 7219 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20 7220 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]] 7221 // CHECK23-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !20 7222 // CHECK23-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !20 7223 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20 7224 // CHECK23-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]] 7225 // CHECK23-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !20 7226 // CHECK23-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] 7227 // CHECK23-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !20 7228 // CHECK23-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20 7229 // CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]] 7230 // CHECK23-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !20 7231 // CHECK23-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] 7232 // CHECK23-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !20 7233 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20 7234 // CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]] 7235 // CHECK23-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !20 7236 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7237 // CHECK23: omp.body.continue: 7238 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7239 // CHECK23: omp.inner.for.inc: 7240 // CHECK23-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 7241 // CHECK23-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 7242 // CHECK23-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 7243 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 7244 // CHECK23: omp.inner.for.end: 7245 // CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 7246 // CHECK23: omp.dispatch.inc: 7247 // CHECK23-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7248 // CHECK23-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 7249 // CHECK23-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] 7250 // CHECK23-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4 7251 // CHECK23-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7252 // CHECK23-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 7253 // CHECK23-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] 7254 // CHECK23-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4 7255 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND]] 7256 // CHECK23: omp.dispatch.end: 7257 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 7258 // CHECK23-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 7259 // CHECK23-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 7260 // CHECK23-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 7261 // CHECK23: .omp.final.then: 7262 // CHECK23-NEXT: store i32 -2147483522, i32* [[I]], align 4 7263 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 7264 // CHECK23: .omp.final.done: 7265 // CHECK23-NEXT: ret void 7266 // 7267 // 7268 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 7269 // CHECK23-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 7270 // CHECK23-NEXT: entry: 7271 // CHECK23-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 7272 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7273 // CHECK23-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 7274 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7275 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[I_ADDR]] to i8* 7276 // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_ADDR]] to i8* 7277 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]]) 7278 // CHECK23-NEXT: ret void 7279 // 7280 // 7281 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3 7282 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { 7283 // CHECK23-NEXT: entry: 7284 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7285 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7286 // CHECK23-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 4 7287 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4 7288 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7289 // CHECK23-NEXT: [[TMP:%.*]] = alloca i8, align 1 7290 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 7291 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 7292 // CHECK23-NEXT: [[I4:%.*]] = alloca i8, align 1 7293 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7294 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7295 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7296 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7297 // CHECK23-NEXT: [[I6:%.*]] = alloca i8, align 1 7298 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7299 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7300 // CHECK23-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 4 7301 // CHECK23-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4 7302 // CHECK23-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 4 7303 // CHECK23-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 4 7304 // CHECK23-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1 7305 // CHECK23-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1 7306 // CHECK23-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 7307 // CHECK23-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 7308 // CHECK23-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] 7309 // CHECK23-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 7310 // CHECK23-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 7311 // CHECK23-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 7312 // CHECK23-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 7313 // CHECK23-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 7314 // CHECK23-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 7315 // CHECK23-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1 7316 // CHECK23-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 7317 // CHECK23-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32 7318 // CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10 7319 // CHECK23-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 7320 // CHECK23: omp.precond.then: 7321 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7322 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 7323 // CHECK23-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 7324 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7325 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7326 // CHECK23-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 7327 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 7328 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 7329 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7330 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 7331 // CHECK23-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] 7332 // CHECK23-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7333 // CHECK23: cond.true: 7334 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 7335 // CHECK23-NEXT: br label [[COND_END:%.*]] 7336 // CHECK23: cond.false: 7337 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7338 // CHECK23-NEXT: br label [[COND_END]] 7339 // CHECK23: cond.end: 7340 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 7341 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7342 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7343 // CHECK23-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 7344 // CHECK23-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP1]], align 1 7345 // CHECK23-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0 7346 // CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 7347 // CHECK23: omp_if.then: 7348 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7349 // CHECK23: omp.inner.for.cond: 7350 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 7351 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 7352 // CHECK23-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 7353 // CHECK23-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7354 // CHECK23: omp.inner.for.body: 7355 // CHECK23-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !23 7356 // CHECK23-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32 7357 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 7358 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 7359 // CHECK23-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] 7360 // CHECK23-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 7361 // CHECK23-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !17, !llvm.access.group !23 7362 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7363 // CHECK23: omp.body.continue: 7364 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7365 // CHECK23: omp.inner.for.inc: 7366 // CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 7367 // CHECK23-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 7368 // CHECK23-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 7369 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] 7370 // CHECK23: omp.inner.for.end: 7371 // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] 7372 // CHECK23: omp_if.else: 7373 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]] 7374 // CHECK23: omp.inner.for.cond13: 7375 // CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7376 // CHECK23-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7377 // CHECK23-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] 7378 // CHECK23-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]] 7379 // CHECK23: omp.inner.for.body15: 7380 // CHECK23-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 7381 // CHECK23-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32 7382 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7383 // CHECK23-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1 7384 // CHECK23-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]] 7385 // CHECK23-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 7386 // CHECK23-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1 7387 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]] 7388 // CHECK23: omp.body.continue20: 7389 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]] 7390 // CHECK23: omp.inner.for.inc21: 7391 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7392 // CHECK23-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1 7393 // CHECK23-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4 7394 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP26:![0-9]+]] 7395 // CHECK23: omp.inner.for.end23: 7396 // CHECK23-NEXT: br label [[OMP_IF_END]] 7397 // CHECK23: omp_if.end: 7398 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7399 // CHECK23: omp.loop.exit: 7400 // CHECK23-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 7401 // CHECK23-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 7402 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 7403 // CHECK23-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 7404 // CHECK23-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 7405 // CHECK23-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 7406 // CHECK23: .omp.final.then: 7407 // CHECK23-NEXT: [[TMP29:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 7408 // CHECK23-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32 7409 // CHECK23-NEXT: [[TMP30:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 7410 // CHECK23-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32 7411 // CHECK23-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]] 7412 // CHECK23-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1 7413 // CHECK23-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1 7414 // CHECK23-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1 7415 // CHECK23-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1 7416 // CHECK23-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]] 7417 // CHECK23-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8 7418 // CHECK23-NEXT: store i8 [[CONV32]], i8* [[TMP0]], align 1 7419 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 7420 // CHECK23: .omp.final.done: 7421 // CHECK23-NEXT: br label [[OMP_PRECOND_END]] 7422 // CHECK23: omp.precond.end: 7423 // CHECK23-NEXT: ret void 7424 // 7425 // 7426 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 7427 // CHECK23-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 7428 // CHECK23-NEXT: entry: 7429 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7430 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7431 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7432 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]]) 7433 // CHECK23-NEXT: ret void 7434 // 7435 // 7436 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4 7437 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { 7438 // CHECK23-NEXT: entry: 7439 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7440 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7441 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 7442 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7443 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 7444 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7445 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7446 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7447 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7448 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 7449 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7450 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7451 // CHECK23-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 7452 // CHECK23-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 7453 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7454 // CHECK23-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4 7455 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7456 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7457 // CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 7458 // CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 7459 // CHECK23-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 7460 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 7461 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) 7462 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 7463 // CHECK23: omp.dispatch.cond: 7464 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7465 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 7466 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7467 // CHECK23: cond.true: 7468 // CHECK23-NEXT: br label [[COND_END:%.*]] 7469 // CHECK23: cond.false: 7470 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7471 // CHECK23-NEXT: br label [[COND_END]] 7472 // CHECK23: cond.end: 7473 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 7474 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7475 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7476 // CHECK23-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 7477 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7478 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7479 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 7480 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 7481 // CHECK23: omp.dispatch.body: 7482 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7483 // CHECK23: omp.inner.for.cond: 7484 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 7485 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28 7486 // CHECK23-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 7487 // CHECK23-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7488 // CHECK23: omp.inner.for.body: 7489 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 7490 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 7491 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 7492 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28 7493 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7494 // CHECK23: omp.body.continue: 7495 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7496 // CHECK23: omp.inner.for.inc: 7497 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 7498 // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 7499 // CHECK23-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 7500 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] 7501 // CHECK23: omp.inner.for.end: 7502 // CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 7503 // CHECK23: omp.dispatch.inc: 7504 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7505 // CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 7506 // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] 7507 // CHECK23-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4 7508 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7509 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 7510 // CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] 7511 // CHECK23-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4 7512 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND]] 7513 // CHECK23: omp.dispatch.end: 7514 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 7515 // CHECK23-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 7516 // CHECK23-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 7517 // CHECK23-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 7518 // CHECK23: .omp.final.then: 7519 // CHECK23-NEXT: store i32 100, i32* [[I]], align 4 7520 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 7521 // CHECK23: .omp.final.done: 7522 // CHECK23-NEXT: ret void 7523 // 7524