1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test host codegen.
3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
9 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -DOMP5 | FileCheck %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -DOMP5
11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK5
12 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -DOMP5| FileCheck %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -DOMP5
14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK7
15
16 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9
19 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
20 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11
22 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -DOMP5 | FileCheck %s --check-prefix=CHECK13
23 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -DOMP5
24 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK13
25 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -DOMP5 | FileCheck %s --check-prefix=CHECK15
26 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -DOMP5
27 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK15
28
29 // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region)
30 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
31 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17
32 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
33 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17
34 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
35 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK19
36 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
37 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19
38 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -DOMP5
39 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK21
40 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -DOMP5
41 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK21
42 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -DOMP5
43 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK23
44 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -DOMP5
45 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK23
46
47 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
48 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9
49 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
50 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9
51 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
52 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11
53 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
54 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11
55 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -DOMP5
56 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK13
57 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -DOMP5
58 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK13
59 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -DOMP5
60 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK15
61 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -DOMP5
62 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK15
63
64 // expected-no-diagnostics
65 #ifndef HEADER
66 #define HEADER
67
68
without_schedule_clause(float * a,float * b,float * c,float * d)69 void without_schedule_clause(float *a, float *b, float *c, float *d) {
70 #pragma omp target
71 #pragma omp teams
72 #ifdef OMP5
73 #pragma omp distribute simd simdlen(8) aligned(a) if(true)
74 #else
75 #pragma omp distribute simd simdlen(8) aligned(a)
76 #endif // OMP5
77 for (int i = 33; i < 32000000; i += 7) {
78 a[i] = b[i] * c[i] * d[i];
79 }
80 }
81
82 // ... loop body ...
83
84
static_not_chunked(float * a,float * b,float * c,float * d)85 void static_not_chunked(float *a, float *b, float *c, float *d) {
86 #pragma omp target
87 #pragma omp teams
88 #ifdef OMP5
89 #pragma omp distribute simd dist_schedule(static) safelen(32) if(simd: true) nontemporal(a, b)
90 #else
91 #pragma omp distribute simd dist_schedule(static) safelen(32)
92 #endif // OMP5
93 for (int i = 32000000; i > 33; i += -7) {
94 a[i] = b[i] * c[i] * d[i];
95 }
96 }
97
98 // ... loop body ...
99
100
101
static_chunked(float * a,float * b,float * c,float * d)102 void static_chunked(float *a, float *b, float *c, float *d) {
103 #pragma omp target
104 #pragma omp teams
105 #pragma omp distribute simd dist_schedule(static, 5)
106 for (unsigned i = 131071; i <= 2147483647; i += 127) {
107 a[i] = b[i] * c[i] * d[i];
108 }
109 }
110
111 // ... loop body ...
112
test_precond()113 void test_precond() {
114 char a = 0; char i;
115 #pragma omp target
116 #pragma omp teams
117 #ifdef OMP5
118 #pragma omp distribute simd linear(i) if(a) nontemporal(i)
119 #else
120 #pragma omp distribute simd linear(i)
121 #endif // OMP5
122 for(i = a; i < 10; ++i);
123 }
124
125 // a is passed as a parameter to the outlined functions
126 // ..many loads of %0..
127
128 // no templates for now, as these require special handling in target regions and/or declare target
129
130
131 template <typename T>
ftemplate()132 T ftemplate() {
133 short aa = 0;
134
135 #pragma omp target
136 #pragma omp teams
137 #pragma omp distribute simd dist_schedule(static, aa)
138 for (int i = 0; i < 100; i++) {
139 }
140 return T();
141 }
142
fint(void)143 int fint(void) { return ftemplate<int>(); }
144
145 #endif
146
147 // CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
148 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
149 // CHECK1-NEXT: entry:
150 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
151 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
152 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
153 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
154 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
155 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
156 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
157 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
158 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
159 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
160 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
161 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
162 // CHECK1-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8
163 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8
164 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8
165 // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8
166 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
167 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
168 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8
169 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
170 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
171 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8
172 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
173 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8
174 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
175 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
176 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8
177 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
178 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
179 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8
180 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
181 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8
182 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
183 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
184 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8
185 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
186 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
187 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8
188 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
189 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8
190 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
191 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
192 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8
193 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
194 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
195 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8
196 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
197 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8
198 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
199 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
200 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
201 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
202 // CHECK1-NEXT: store i32 1, i32* [[TMP26]], align 4
203 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
204 // CHECK1-NEXT: store i32 4, i32* [[TMP27]], align 4
205 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
206 // CHECK1-NEXT: store i8** [[TMP24]], i8*** [[TMP28]], align 8
207 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
208 // CHECK1-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 8
209 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
210 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP30]], align 8
211 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
212 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP31]], align 8
213 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
214 // CHECK1-NEXT: store i8** null, i8*** [[TMP32]], align 8
215 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
216 // CHECK1-NEXT: store i8** null, i8*** [[TMP33]], align 8
217 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
218 // CHECK1-NEXT: store i64 4571424, i64* [[TMP34]], align 8
219 // CHECK1-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
220 // CHECK1-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
221 // CHECK1-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
222 // CHECK1: omp_offload.failed:
223 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3:[0-9]+]]
224 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
225 // CHECK1: omp_offload.cont:
226 // CHECK1-NEXT: ret void
227 //
228 //
229 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
230 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] {
231 // CHECK1-NEXT: entry:
232 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
233 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
234 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
235 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
236 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
237 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
238 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
239 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
240 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
241 // CHECK1-NEXT: ret void
242 //
243 //
244 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
245 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
246 // CHECK1-NEXT: entry:
247 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
248 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
249 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
250 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
251 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
252 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
253 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
254 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
255 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
256 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
257 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
258 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
259 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
260 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
261 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
262 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
263 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
264 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
265 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
266 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
267 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
268 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
269 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
270 // CHECK1-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 8
271 // CHECK1-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i64 16) ]
272 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
273 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
274 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
275 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
276 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
277 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
278 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
279 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
280 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
281 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
282 // CHECK1: cond.true:
283 // CHECK1-NEXT: br label [[COND_END:%.*]]
284 // CHECK1: cond.false:
285 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
286 // CHECK1-NEXT: br label [[COND_END]]
287 // CHECK1: cond.end:
288 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
289 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
290 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
291 // CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
292 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
293 // CHECK1: omp.inner.for.cond:
294 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
295 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8
296 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
297 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
298 // CHECK1: omp.inner.for.body:
299 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
300 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
301 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
302 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
303 // CHECK1-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !8
304 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
305 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
306 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]]
307 // CHECK1-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !8
308 // CHECK1-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !8
309 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
310 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
311 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM2]]
312 // CHECK1-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !8
313 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
314 // CHECK1-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !8
315 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
316 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
317 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM5]]
318 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !llvm.access.group !8
319 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
320 // CHECK1-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !8
321 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
322 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
323 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM8]]
324 // CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !8
325 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
326 // CHECK1: omp.body.continue:
327 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
328 // CHECK1: omp.inner.for.inc:
329 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
330 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
331 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
332 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
333 // CHECK1: omp.inner.for.end:
334 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
335 // CHECK1: omp.loop.exit:
336 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
337 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
338 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
339 // CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
340 // CHECK1: .omp.final.then:
341 // CHECK1-NEXT: store i32 32000001, i32* [[I]], align 4
342 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
343 // CHECK1: .omp.final.done:
344 // CHECK1-NEXT: ret void
345 //
346 //
347 // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
348 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
349 // CHECK1-NEXT: entry:
350 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
351 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
352 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
353 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
354 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
355 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
356 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
357 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
358 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
359 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
360 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
361 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
362 // CHECK1-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8
363 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8
364 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8
365 // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8
366 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
367 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
368 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8
369 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
370 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
371 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8
372 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
373 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8
374 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
375 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
376 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8
377 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
378 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
379 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8
380 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
381 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8
382 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
383 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
384 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8
385 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
386 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
387 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8
388 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
389 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8
390 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
391 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
392 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8
393 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
394 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
395 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8
396 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
397 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8
398 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
399 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
400 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
401 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
402 // CHECK1-NEXT: store i32 1, i32* [[TMP26]], align 4
403 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
404 // CHECK1-NEXT: store i32 4, i32* [[TMP27]], align 4
405 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
406 // CHECK1-NEXT: store i8** [[TMP24]], i8*** [[TMP28]], align 8
407 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
408 // CHECK1-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 8
409 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
410 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64** [[TMP30]], align 8
411 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
412 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i64** [[TMP31]], align 8
413 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
414 // CHECK1-NEXT: store i8** null, i8*** [[TMP32]], align 8
415 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
416 // CHECK1-NEXT: store i8** null, i8*** [[TMP33]], align 8
417 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
418 // CHECK1-NEXT: store i64 4571424, i64* [[TMP34]], align 8
419 // CHECK1-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
420 // CHECK1-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
421 // CHECK1-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
422 // CHECK1: omp_offload.failed:
423 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
424 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
425 // CHECK1: omp_offload.cont:
426 // CHECK1-NEXT: ret void
427 //
428 //
429 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
430 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] {
431 // CHECK1-NEXT: entry:
432 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
433 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
434 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
435 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
436 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
437 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
438 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
439 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
440 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
441 // CHECK1-NEXT: ret void
442 //
443 //
444 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
445 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
446 // CHECK1-NEXT: entry:
447 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
448 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
449 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
450 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
451 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
452 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
453 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
454 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
455 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
456 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
457 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
458 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
459 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
460 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
461 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
462 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
463 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
464 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
465 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
466 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
467 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
468 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
469 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
470 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
471 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
472 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
473 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
474 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
475 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
476 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
477 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
478 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
479 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
480 // CHECK1: cond.true:
481 // CHECK1-NEXT: br label [[COND_END:%.*]]
482 // CHECK1: cond.false:
483 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
484 // CHECK1-NEXT: br label [[COND_END]]
485 // CHECK1: cond.end:
486 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
487 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
488 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
489 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
490 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
491 // CHECK1: omp.inner.for.cond:
492 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
493 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
494 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
495 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
496 // CHECK1: omp.inner.for.body:
497 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
498 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
499 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
500 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4
501 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8
502 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
503 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
504 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]]
505 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
506 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8
507 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
508 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
509 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]]
510 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4
511 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
512 // CHECK1-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8
513 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
514 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
515 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]]
516 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4
517 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
518 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8
519 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
520 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
521 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]]
522 // CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
523 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
524 // CHECK1: omp.body.continue:
525 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
526 // CHECK1: omp.inner.for.inc:
527 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
528 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
529 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
530 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
531 // CHECK1: omp.inner.for.end:
532 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
533 // CHECK1: omp.loop.exit:
534 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
535 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
536 // CHECK1-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
537 // CHECK1-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
538 // CHECK1: .omp.final.then:
539 // CHECK1-NEXT: store i32 32, i32* [[I]], align 4
540 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
541 // CHECK1: .omp.final.done:
542 // CHECK1-NEXT: ret void
543 //
544 //
545 // CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
546 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
547 // CHECK1-NEXT: entry:
548 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
549 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
550 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
551 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
552 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
553 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
554 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
555 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
556 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
557 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
558 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
559 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
560 // CHECK1-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8
561 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8
562 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8
563 // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8
564 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
565 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
566 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8
567 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
568 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
569 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8
570 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
571 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8
572 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
573 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
574 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8
575 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
576 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
577 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8
578 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
579 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8
580 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
581 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
582 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8
583 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
584 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
585 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8
586 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
587 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8
588 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
589 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
590 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8
591 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
592 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
593 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8
594 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
595 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8
596 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
597 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
598 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
599 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
600 // CHECK1-NEXT: store i32 1, i32* [[TMP26]], align 4
601 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
602 // CHECK1-NEXT: store i32 4, i32* [[TMP27]], align 4
603 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
604 // CHECK1-NEXT: store i8** [[TMP24]], i8*** [[TMP28]], align 8
605 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
606 // CHECK1-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 8
607 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
608 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64** [[TMP30]], align 8
609 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
610 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP31]], align 8
611 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
612 // CHECK1-NEXT: store i8** null, i8*** [[TMP32]], align 8
613 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
614 // CHECK1-NEXT: store i8** null, i8*** [[TMP33]], align 8
615 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
616 // CHECK1-NEXT: store i64 16908289, i64* [[TMP34]], align 8
617 // CHECK1-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
618 // CHECK1-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
619 // CHECK1-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
620 // CHECK1: omp_offload.failed:
621 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
622 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
623 // CHECK1: omp_offload.cont:
624 // CHECK1-NEXT: ret void
625 //
626 //
627 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
628 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] {
629 // CHECK1-NEXT: entry:
630 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
631 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
632 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
633 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
634 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
635 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
636 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
637 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
638 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
639 // CHECK1-NEXT: ret void
640 //
641 //
642 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
643 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
644 // CHECK1-NEXT: entry:
645 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
646 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
647 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
648 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
649 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
650 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
651 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
652 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
653 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
654 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
655 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
656 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
657 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
658 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
659 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
660 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
661 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
662 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
663 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
664 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
665 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
666 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
667 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
668 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
669 // CHECK1-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
670 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
671 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
672 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
673 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
674 // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
675 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
676 // CHECK1: omp.dispatch.cond:
677 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
678 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
679 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
680 // CHECK1: cond.true:
681 // CHECK1-NEXT: br label [[COND_END:%.*]]
682 // CHECK1: cond.false:
683 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
684 // CHECK1-NEXT: br label [[COND_END]]
685 // CHECK1: cond.end:
686 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
687 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
688 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
689 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
690 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
691 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
692 // CHECK1-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
693 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
694 // CHECK1: omp.dispatch.body:
695 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
696 // CHECK1: omp.inner.for.cond:
697 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
698 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17
699 // CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
700 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
701 // CHECK1: omp.inner.for.body:
702 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
703 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
704 // CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
705 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
706 // CHECK1-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !17
707 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
708 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
709 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]]
710 // CHECK1-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !17
711 // CHECK1-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !17
712 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
713 // CHECK1-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
714 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]]
715 // CHECK1-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !17
716 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
717 // CHECK1-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !17
718 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
719 // CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
720 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]]
721 // CHECK1-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !17
722 // CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
723 // CHECK1-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !17
724 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
725 // CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
726 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]]
727 // CHECK1-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !17
728 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
729 // CHECK1: omp.body.continue:
730 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
731 // CHECK1: omp.inner.for.inc:
732 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
733 // CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
734 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
735 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
736 // CHECK1: omp.inner.for.end:
737 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
738 // CHECK1: omp.dispatch.inc:
739 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
740 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
741 // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
742 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
743 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
744 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
745 // CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
746 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4
747 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
748 // CHECK1: omp.dispatch.end:
749 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
750 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
751 // CHECK1-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
752 // CHECK1-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
753 // CHECK1: .omp.final.then:
754 // CHECK1-NEXT: store i32 -2147483522, i32* [[I]], align 4
755 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
756 // CHECK1: .omp.final.done:
757 // CHECK1-NEXT: ret void
758 //
759 //
760 // CHECK1-LABEL: define {{[^@]+}}@_Z12test_precondv
761 // CHECK1-SAME: () #[[ATTR0]] {
762 // CHECK1-NEXT: entry:
763 // CHECK1-NEXT: [[A:%.*]] = alloca i8, align 1
764 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1
765 // CHECK1-NEXT: [[I_CASTED:%.*]] = alloca i64, align 8
766 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
767 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8
768 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8
769 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8
770 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1
771 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
772 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
773 // CHECK1-NEXT: store i8 0, i8* [[A]], align 1
774 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1
775 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[I_CASTED]] to i8*
776 // CHECK1-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1
777 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[I_CASTED]], align 8
778 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[A]], align 1
779 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i8*
780 // CHECK1-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
781 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8
782 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
783 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
784 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
785 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
786 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
787 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8
788 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
789 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8
790 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
791 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
792 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8
793 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
794 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
795 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8
796 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
797 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8
798 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
799 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
800 // CHECK1-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1
801 // CHECK1-NEXT: store i8 [[TMP16]], i8* [[DOTCAPTURE_EXPR_]], align 1
802 // CHECK1-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
803 // CHECK1-NEXT: [[CONV3:%.*]] = sext i8 [[TMP17]] to i32
804 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV3]]
805 // CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1
806 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1
807 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
808 // CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1
809 // CHECK1-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
810 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
811 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
812 // CHECK1-NEXT: [[TMP19:%.*]] = zext i32 [[ADD6]] to i64
813 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
814 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
815 // CHECK1-NEXT: store i32 1, i32* [[TMP20]], align 4
816 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
817 // CHECK1-NEXT: store i32 2, i32* [[TMP21]], align 4
818 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
819 // CHECK1-NEXT: store i8** [[TMP14]], i8*** [[TMP22]], align 8
820 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
821 // CHECK1-NEXT: store i8** [[TMP15]], i8*** [[TMP23]], align 8
822 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
823 // CHECK1-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64** [[TMP24]], align 8
824 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
825 // CHECK1-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i64** [[TMP25]], align 8
826 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
827 // CHECK1-NEXT: store i8** null, i8*** [[TMP26]], align 8
828 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
829 // CHECK1-NEXT: store i8** null, i8*** [[TMP27]], align 8
830 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
831 // CHECK1-NEXT: store i64 [[TMP19]], i64* [[TMP28]], align 8
832 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
833 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
834 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
835 // CHECK1: omp_offload.failed:
836 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i64 [[TMP1]], i64 [[TMP3]]) #[[ATTR3]]
837 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
838 // CHECK1: omp_offload.cont:
839 // CHECK1-NEXT: ret void
840 //
841 //
842 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
843 // CHECK1-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {
844 // CHECK1-NEXT: entry:
845 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8
846 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
847 // CHECK1-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
848 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
849 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i8*
850 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i8*
851 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
852 // CHECK1-NEXT: ret void
853 //
854 //
855 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
856 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] {
857 // CHECK1-NEXT: entry:
858 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
859 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
860 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 8
861 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8
862 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
863 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1
864 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
865 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
866 // CHECK1-NEXT: [[I4:%.*]] = alloca i8, align 1
867 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
868 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
869 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
870 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
871 // CHECK1-NEXT: [[I6:%.*]] = alloca i8, align 1
872 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
873 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
874 // CHECK1-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 8
875 // CHECK1-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8
876 // CHECK1-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 8
877 // CHECK1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 8
878 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
879 // CHECK1-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
880 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
881 // CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
882 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
883 // CHECK1-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
884 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
885 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
886 // CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
887 // CHECK1-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
888 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
889 // CHECK1-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
890 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
891 // CHECK1-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
892 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
893 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
894 // CHECK1: omp.precond.then:
895 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
896 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
897 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
898 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
899 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
900 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
901 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
902 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
903 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
904 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
905 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
906 // CHECK1-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
907 // CHECK1: cond.true:
908 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
909 // CHECK1-NEXT: br label [[COND_END:%.*]]
910 // CHECK1: cond.false:
911 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
912 // CHECK1-NEXT: br label [[COND_END]]
913 // CHECK1: cond.end:
914 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
915 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
916 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
917 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
918 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
919 // CHECK1: omp.inner.for.cond:
920 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
921 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
922 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
923 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
924 // CHECK1: omp.inner.for.body:
925 // CHECK1-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !20
926 // CHECK1-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
927 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
928 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
929 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
930 // CHECK1-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
931 // CHECK1-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !20
932 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
933 // CHECK1: omp.body.continue:
934 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
935 // CHECK1: omp.inner.for.inc:
936 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
937 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
938 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
939 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
940 // CHECK1: omp.inner.for.end:
941 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
942 // CHECK1: omp.loop.exit:
943 // CHECK1-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
944 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
945 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
946 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
947 // CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
948 // CHECK1-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
949 // CHECK1: .omp.final.then:
950 // CHECK1-NEXT: [[TMP23:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
951 // CHECK1-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32
952 // CHECK1-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
953 // CHECK1-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32
954 // CHECK1-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
955 // CHECK1-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
956 // CHECK1-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
957 // CHECK1-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
958 // CHECK1-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
959 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
960 // CHECK1-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
961 // CHECK1-NEXT: store i8 [[CONV21]], i8* [[TMP0]], align 1
962 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
963 // CHECK1: .omp.final.done:
964 // CHECK1-NEXT: br label [[OMP_PRECOND_END]]
965 // CHECK1: omp.precond.end:
966 // CHECK1-NEXT: ret void
967 //
968 //
969 // CHECK1-LABEL: define {{[^@]+}}@_Z4fintv
970 // CHECK1-SAME: () #[[ATTR0]] {
971 // CHECK1-NEXT: entry:
972 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v()
973 // CHECK1-NEXT: ret i32 [[CALL]]
974 //
975 //
976 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
977 // CHECK1-SAME: () #[[ATTR0]] comdat {
978 // CHECK1-NEXT: entry:
979 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
980 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
981 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
982 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
983 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
984 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
985 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2
986 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2
987 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
988 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2
989 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
990 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
991 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
992 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8
993 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
994 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
995 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
996 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
997 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8
998 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
999 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1000 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1001 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1002 // CHECK1-NEXT: store i32 1, i32* [[TMP9]], align 4
1003 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1004 // CHECK1-NEXT: store i32 1, i32* [[TMP10]], align 4
1005 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1006 // CHECK1-NEXT: store i8** [[TMP7]], i8*** [[TMP11]], align 8
1007 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1008 // CHECK1-NEXT: store i8** [[TMP8]], i8*** [[TMP12]], align 8
1009 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1010 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64** [[TMP13]], align 8
1011 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1012 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i64** [[TMP14]], align 8
1013 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1014 // CHECK1-NEXT: store i8** null, i8*** [[TMP15]], align 8
1015 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1016 // CHECK1-NEXT: store i8** null, i8*** [[TMP16]], align 8
1017 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1018 // CHECK1-NEXT: store i64 100, i64* [[TMP17]], align 8
1019 // CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1020 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
1021 // CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1022 // CHECK1: omp_offload.failed:
1023 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i64 [[TMP1]]) #[[ATTR3]]
1024 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
1025 // CHECK1: omp_offload.cont:
1026 // CHECK1-NEXT: ret i32 0
1027 //
1028 //
1029 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
1030 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] {
1031 // CHECK1-NEXT: entry:
1032 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
1033 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
1034 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1035 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]])
1036 // CHECK1-NEXT: ret void
1037 //
1038 //
1039 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10
1040 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] {
1041 // CHECK1-NEXT: entry:
1042 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1043 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1044 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8
1045 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1046 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1047 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1048 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1049 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1050 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1051 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
1052 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1053 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1054 // CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
1055 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
1056 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1057 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
1058 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1059 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1060 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
1061 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
1062 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1063 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1064 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
1065 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
1066 // CHECK1: omp.dispatch.cond:
1067 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1068 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
1069 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1070 // CHECK1: cond.true:
1071 // CHECK1-NEXT: br label [[COND_END:%.*]]
1072 // CHECK1: cond.false:
1073 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1074 // CHECK1-NEXT: br label [[COND_END]]
1075 // CHECK1: cond.end:
1076 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1077 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1078 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1079 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
1080 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1081 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1082 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1083 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1084 // CHECK1: omp.dispatch.body:
1085 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1086 // CHECK1: omp.inner.for.cond:
1087 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
1088 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23
1089 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1090 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1091 // CHECK1: omp.inner.for.body:
1092 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
1093 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
1094 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1095 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23
1096 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1097 // CHECK1: omp.body.continue:
1098 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1099 // CHECK1: omp.inner.for.inc:
1100 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
1101 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
1102 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
1103 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
1104 // CHECK1: omp.inner.for.end:
1105 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
1106 // CHECK1: omp.dispatch.inc:
1107 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1108 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1109 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
1110 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
1111 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1112 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1113 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
1114 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
1115 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
1116 // CHECK1: omp.dispatch.end:
1117 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
1118 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1119 // CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
1120 // CHECK1-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1121 // CHECK1: .omp.final.then:
1122 // CHECK1-NEXT: store i32 100, i32* [[I]], align 4
1123 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
1124 // CHECK1: .omp.final.done:
1125 // CHECK1-NEXT: ret void
1126 //
1127 //
1128 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1129 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
1130 // CHECK1-NEXT: entry:
1131 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
1132 // CHECK1-NEXT: ret void
1133 //
1134 //
1135 // CHECK3-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
1136 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
1137 // CHECK3-NEXT: entry:
1138 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
1139 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
1140 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
1141 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
1142 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
1143 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
1144 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
1145 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1146 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
1147 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
1148 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
1149 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
1150 // CHECK3-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4
1151 // CHECK3-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4
1152 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4
1153 // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4
1154 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1155 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
1156 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4
1157 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1158 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
1159 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4
1160 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1161 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4
1162 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1163 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
1164 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4
1165 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1166 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
1167 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4
1168 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1169 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4
1170 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1171 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
1172 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4
1173 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1174 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
1175 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4
1176 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1177 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4
1178 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1179 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
1180 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4
1181 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1182 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
1183 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4
1184 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1185 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4
1186 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1187 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1188 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1189 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1190 // CHECK3-NEXT: store i32 1, i32* [[TMP26]], align 4
1191 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1192 // CHECK3-NEXT: store i32 4, i32* [[TMP27]], align 4
1193 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1194 // CHECK3-NEXT: store i8** [[TMP24]], i8*** [[TMP28]], align 4
1195 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1196 // CHECK3-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 4
1197 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1198 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP30]], align 4
1199 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1200 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP31]], align 4
1201 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1202 // CHECK3-NEXT: store i8** null, i8*** [[TMP32]], align 4
1203 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1204 // CHECK3-NEXT: store i8** null, i8*** [[TMP33]], align 4
1205 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1206 // CHECK3-NEXT: store i64 4571424, i64* [[TMP34]], align 8
1207 // CHECK3-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1208 // CHECK3-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
1209 // CHECK3-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1210 // CHECK3: omp_offload.failed:
1211 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3:[0-9]+]]
1212 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1213 // CHECK3: omp_offload.cont:
1214 // CHECK3-NEXT: ret void
1215 //
1216 //
1217 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
1218 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] {
1219 // CHECK3-NEXT: entry:
1220 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
1221 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
1222 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
1223 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
1224 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
1225 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
1226 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
1227 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
1228 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
1229 // CHECK3-NEXT: ret void
1230 //
1231 //
1232 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
1233 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
1234 // CHECK3-NEXT: entry:
1235 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1236 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1237 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
1238 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
1239 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
1240 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
1241 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1242 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1243 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1244 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1245 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1246 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1247 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1248 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1249 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1250 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
1251 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
1252 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
1253 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
1254 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
1255 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
1256 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
1257 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
1258 // CHECK3-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 4
1259 // CHECK3-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i32 16) ]
1260 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1261 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
1262 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1263 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1264 // CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1265 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
1266 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1267 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1268 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
1269 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1270 // CHECK3: cond.true:
1271 // CHECK3-NEXT: br label [[COND_END:%.*]]
1272 // CHECK3: cond.false:
1273 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1274 // CHECK3-NEXT: br label [[COND_END]]
1275 // CHECK3: cond.end:
1276 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
1277 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1278 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1279 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
1280 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1281 // CHECK3: omp.inner.for.cond:
1282 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
1283 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
1284 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
1285 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1286 // CHECK3: omp.inner.for.body:
1287 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
1288 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
1289 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
1290 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
1291 // CHECK3-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !9
1292 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
1293 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
1294 // CHECK3-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9
1295 // CHECK3-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !9
1296 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
1297 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP16]], i32 [[TMP17]]
1298 // CHECK3-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !9
1299 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
1300 // CHECK3-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !9
1301 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
1302 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP19]], i32 [[TMP20]]
1303 // CHECK3-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !9
1304 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
1305 // CHECK3-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !9
1306 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
1307 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP22]], i32 [[TMP23]]
1308 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !9
1309 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1310 // CHECK3: omp.body.continue:
1311 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1312 // CHECK3: omp.inner.for.inc:
1313 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
1314 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
1315 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
1316 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
1317 // CHECK3: omp.inner.for.end:
1318 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1319 // CHECK3: omp.loop.exit:
1320 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
1321 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1322 // CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
1323 // CHECK3-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1324 // CHECK3: .omp.final.then:
1325 // CHECK3-NEXT: store i32 32000001, i32* [[I]], align 4
1326 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
1327 // CHECK3: .omp.final.done:
1328 // CHECK3-NEXT: ret void
1329 //
1330 //
1331 // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
1332 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
1333 // CHECK3-NEXT: entry:
1334 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
1335 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
1336 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
1337 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
1338 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
1339 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
1340 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
1341 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1342 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
1343 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
1344 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
1345 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
1346 // CHECK3-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4
1347 // CHECK3-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4
1348 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4
1349 // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4
1350 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1351 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
1352 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4
1353 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1354 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
1355 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4
1356 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1357 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4
1358 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1359 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
1360 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4
1361 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1362 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
1363 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4
1364 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1365 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4
1366 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1367 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
1368 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4
1369 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1370 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
1371 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4
1372 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1373 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4
1374 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1375 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
1376 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4
1377 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1378 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
1379 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4
1380 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1381 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4
1382 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1383 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1384 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1385 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1386 // CHECK3-NEXT: store i32 1, i32* [[TMP26]], align 4
1387 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1388 // CHECK3-NEXT: store i32 4, i32* [[TMP27]], align 4
1389 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1390 // CHECK3-NEXT: store i8** [[TMP24]], i8*** [[TMP28]], align 4
1391 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1392 // CHECK3-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 4
1393 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1394 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64** [[TMP30]], align 4
1395 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1396 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i64** [[TMP31]], align 4
1397 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1398 // CHECK3-NEXT: store i8** null, i8*** [[TMP32]], align 4
1399 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1400 // CHECK3-NEXT: store i8** null, i8*** [[TMP33]], align 4
1401 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1402 // CHECK3-NEXT: store i64 4571424, i64* [[TMP34]], align 8
1403 // CHECK3-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1404 // CHECK3-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
1405 // CHECK3-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1406 // CHECK3: omp_offload.failed:
1407 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
1408 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1409 // CHECK3: omp_offload.cont:
1410 // CHECK3-NEXT: ret void
1411 //
1412 //
1413 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
1414 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] {
1415 // CHECK3-NEXT: entry:
1416 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
1417 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
1418 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
1419 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
1420 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
1421 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
1422 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
1423 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
1424 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
1425 // CHECK3-NEXT: ret void
1426 //
1427 //
1428 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
1429 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
1430 // CHECK3-NEXT: entry:
1431 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1432 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1433 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
1434 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
1435 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
1436 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
1437 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1438 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1439 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1440 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1441 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1442 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1443 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1444 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1445 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1446 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
1447 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
1448 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
1449 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
1450 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
1451 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
1452 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
1453 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
1454 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1455 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
1456 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1457 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1458 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1459 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
1460 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1461 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1462 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
1463 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1464 // CHECK3: cond.true:
1465 // CHECK3-NEXT: br label [[COND_END:%.*]]
1466 // CHECK3: cond.false:
1467 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1468 // CHECK3-NEXT: br label [[COND_END]]
1469 // CHECK3: cond.end:
1470 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1471 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1472 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1473 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
1474 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1475 // CHECK3: omp.inner.for.cond:
1476 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1477 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1478 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1479 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1480 // CHECK3: omp.inner.for.body:
1481 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1482 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
1483 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
1484 // CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4
1485 // CHECK3-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4
1486 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
1487 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]]
1488 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
1489 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4
1490 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
1491 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]]
1492 // CHECK3-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4
1493 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
1494 // CHECK3-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4
1495 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
1496 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]]
1497 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4
1498 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
1499 // CHECK3-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4
1500 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
1501 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]]
1502 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
1503 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1504 // CHECK3: omp.body.continue:
1505 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1506 // CHECK3: omp.inner.for.inc:
1507 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1508 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
1509 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1510 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
1511 // CHECK3: omp.inner.for.end:
1512 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1513 // CHECK3: omp.loop.exit:
1514 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
1515 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1516 // CHECK3-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
1517 // CHECK3-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1518 // CHECK3: .omp.final.then:
1519 // CHECK3-NEXT: store i32 32, i32* [[I]], align 4
1520 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
1521 // CHECK3: .omp.final.done:
1522 // CHECK3-NEXT: ret void
1523 //
1524 //
1525 // CHECK3-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
1526 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
1527 // CHECK3-NEXT: entry:
1528 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
1529 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
1530 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
1531 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
1532 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
1533 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
1534 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
1535 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1536 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
1537 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
1538 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
1539 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
1540 // CHECK3-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4
1541 // CHECK3-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4
1542 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4
1543 // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4
1544 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1545 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
1546 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4
1547 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1548 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
1549 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4
1550 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1551 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4
1552 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1553 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
1554 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4
1555 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1556 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
1557 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4
1558 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1559 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4
1560 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1561 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
1562 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4
1563 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1564 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
1565 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4
1566 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1567 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4
1568 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1569 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
1570 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4
1571 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1572 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
1573 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4
1574 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1575 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4
1576 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1577 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1578 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1579 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1580 // CHECK3-NEXT: store i32 1, i32* [[TMP26]], align 4
1581 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1582 // CHECK3-NEXT: store i32 4, i32* [[TMP27]], align 4
1583 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1584 // CHECK3-NEXT: store i8** [[TMP24]], i8*** [[TMP28]], align 4
1585 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1586 // CHECK3-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 4
1587 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1588 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64** [[TMP30]], align 4
1589 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1590 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP31]], align 4
1591 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1592 // CHECK3-NEXT: store i8** null, i8*** [[TMP32]], align 4
1593 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1594 // CHECK3-NEXT: store i8** null, i8*** [[TMP33]], align 4
1595 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1596 // CHECK3-NEXT: store i64 16908289, i64* [[TMP34]], align 8
1597 // CHECK3-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1598 // CHECK3-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
1599 // CHECK3-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1600 // CHECK3: omp_offload.failed:
1601 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
1602 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1603 // CHECK3: omp_offload.cont:
1604 // CHECK3-NEXT: ret void
1605 //
1606 //
1607 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
1608 // CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] {
1609 // CHECK3-NEXT: entry:
1610 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
1611 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
1612 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
1613 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
1614 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
1615 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
1616 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
1617 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
1618 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
1619 // CHECK3-NEXT: ret void
1620 //
1621 //
1622 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
1623 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
1624 // CHECK3-NEXT: entry:
1625 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1626 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1627 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
1628 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
1629 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
1630 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
1631 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1632 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1633 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1634 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1635 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1636 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1637 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1638 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1639 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1640 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
1641 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
1642 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
1643 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
1644 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
1645 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
1646 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
1647 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
1648 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1649 // CHECK3-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
1650 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1651 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1652 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1653 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
1654 // CHECK3-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
1655 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
1656 // CHECK3: omp.dispatch.cond:
1657 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1658 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
1659 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1660 // CHECK3: cond.true:
1661 // CHECK3-NEXT: br label [[COND_END:%.*]]
1662 // CHECK3: cond.false:
1663 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1664 // CHECK3-NEXT: br label [[COND_END]]
1665 // CHECK3: cond.end:
1666 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1667 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1668 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1669 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
1670 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1671 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1672 // CHECK3-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
1673 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1674 // CHECK3: omp.dispatch.body:
1675 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1676 // CHECK3: omp.inner.for.cond:
1677 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
1678 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
1679 // CHECK3-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
1680 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1681 // CHECK3: omp.inner.for.body:
1682 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
1683 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
1684 // CHECK3-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
1685 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
1686 // CHECK3-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !18
1687 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
1688 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
1689 // CHECK3-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !18
1690 // CHECK3-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !18
1691 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
1692 // CHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]]
1693 // CHECK3-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !18
1694 // CHECK3-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
1695 // CHECK3-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !18
1696 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
1697 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]]
1698 // CHECK3-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !18
1699 // CHECK3-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
1700 // CHECK3-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !18
1701 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
1702 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]]
1703 // CHECK3-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !18
1704 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1705 // CHECK3: omp.body.continue:
1706 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1707 // CHECK3: omp.inner.for.inc:
1708 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
1709 // CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
1710 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
1711 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
1712 // CHECK3: omp.inner.for.end:
1713 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
1714 // CHECK3: omp.dispatch.inc:
1715 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1716 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1717 // CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
1718 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
1719 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1720 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1721 // CHECK3-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]]
1722 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4
1723 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
1724 // CHECK3: omp.dispatch.end:
1725 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
1726 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1727 // CHECK3-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
1728 // CHECK3-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1729 // CHECK3: .omp.final.then:
1730 // CHECK3-NEXT: store i32 -2147483522, i32* [[I]], align 4
1731 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
1732 // CHECK3: .omp.final.done:
1733 // CHECK3-NEXT: ret void
1734 //
1735 //
1736 // CHECK3-LABEL: define {{[^@]+}}@_Z12test_precondv
1737 // CHECK3-SAME: () #[[ATTR0]] {
1738 // CHECK3-NEXT: entry:
1739 // CHECK3-NEXT: [[A:%.*]] = alloca i8, align 1
1740 // CHECK3-NEXT: [[I:%.*]] = alloca i8, align 1
1741 // CHECK3-NEXT: [[I_CASTED:%.*]] = alloca i32, align 4
1742 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
1743 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4
1744 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4
1745 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4
1746 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1
1747 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1748 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1749 // CHECK3-NEXT: store i8 0, i8* [[A]], align 1
1750 // CHECK3-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1
1751 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[I_CASTED]] to i8*
1752 // CHECK3-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1
1753 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I_CASTED]], align 4
1754 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[A]], align 1
1755 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_CASTED]] to i8*
1756 // CHECK3-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
1757 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4
1758 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1759 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
1760 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
1761 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1762 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
1763 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4
1764 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1765 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4
1766 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1767 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
1768 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4
1769 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1770 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
1771 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4
1772 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1773 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4
1774 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1775 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1776 // CHECK3-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1
1777 // CHECK3-NEXT: store i8 [[TMP16]], i8* [[DOTCAPTURE_EXPR_]], align 1
1778 // CHECK3-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1779 // CHECK3-NEXT: [[CONV3:%.*]] = sext i8 [[TMP17]] to i32
1780 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV3]]
1781 // CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1
1782 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1
1783 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
1784 // CHECK3-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1
1785 // CHECK3-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
1786 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1787 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
1788 // CHECK3-NEXT: [[TMP19:%.*]] = zext i32 [[ADD6]] to i64
1789 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1790 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1791 // CHECK3-NEXT: store i32 1, i32* [[TMP20]], align 4
1792 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1793 // CHECK3-NEXT: store i32 2, i32* [[TMP21]], align 4
1794 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1795 // CHECK3-NEXT: store i8** [[TMP14]], i8*** [[TMP22]], align 4
1796 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1797 // CHECK3-NEXT: store i8** [[TMP15]], i8*** [[TMP23]], align 4
1798 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1799 // CHECK3-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64** [[TMP24]], align 4
1800 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1801 // CHECK3-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i64** [[TMP25]], align 4
1802 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1803 // CHECK3-NEXT: store i8** null, i8*** [[TMP26]], align 4
1804 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1805 // CHECK3-NEXT: store i8** null, i8*** [[TMP27]], align 4
1806 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1807 // CHECK3-NEXT: store i64 [[TMP19]], i64* [[TMP28]], align 8
1808 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1809 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
1810 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1811 // CHECK3: omp_offload.failed:
1812 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i32 [[TMP1]], i32 [[TMP3]]) #[[ATTR3]]
1813 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1814 // CHECK3: omp_offload.cont:
1815 // CHECK3-NEXT: ret void
1816 //
1817 //
1818 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
1819 // CHECK3-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] {
1820 // CHECK3-NEXT: entry:
1821 // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4
1822 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1823 // CHECK3-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4
1824 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1825 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[I_ADDR]] to i8*
1826 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_ADDR]] to i8*
1827 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
1828 // CHECK3-NEXT: ret void
1829 //
1830 //
1831 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7
1832 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] {
1833 // CHECK3-NEXT: entry:
1834 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1835 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1836 // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 4
1837 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4
1838 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1839 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1
1840 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1841 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1842 // CHECK3-NEXT: [[I4:%.*]] = alloca i8, align 1
1843 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1844 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1845 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1846 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1847 // CHECK3-NEXT: [[I6:%.*]] = alloca i8, align 1
1848 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1849 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1850 // CHECK3-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 4
1851 // CHECK3-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4
1852 // CHECK3-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 4
1853 // CHECK3-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 4
1854 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
1855 // CHECK3-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
1856 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1857 // CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
1858 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
1859 // CHECK3-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
1860 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
1861 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
1862 // CHECK3-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
1863 // CHECK3-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
1864 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1865 // CHECK3-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
1866 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1867 // CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
1868 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
1869 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1870 // CHECK3: omp.precond.then:
1871 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1872 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
1873 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
1874 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1875 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1876 // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1877 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
1878 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1879 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1880 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
1881 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
1882 // CHECK3-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1883 // CHECK3: cond.true:
1884 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
1885 // CHECK3-NEXT: br label [[COND_END:%.*]]
1886 // CHECK3: cond.false:
1887 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1888 // CHECK3-NEXT: br label [[COND_END]]
1889 // CHECK3: cond.end:
1890 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
1891 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1892 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1893 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
1894 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1895 // CHECK3: omp.inner.for.cond:
1896 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
1897 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
1898 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
1899 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1900 // CHECK3: omp.inner.for.body:
1901 // CHECK3-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21
1902 // CHECK3-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
1903 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
1904 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
1905 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
1906 // CHECK3-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
1907 // CHECK3-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !21
1908 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1909 // CHECK3: omp.body.continue:
1910 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1911 // CHECK3: omp.inner.for.inc:
1912 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
1913 // CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
1914 // CHECK3-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
1915 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
1916 // CHECK3: omp.inner.for.end:
1917 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1918 // CHECK3: omp.loop.exit:
1919 // CHECK3-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1920 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
1921 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
1922 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1923 // CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
1924 // CHECK3-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1925 // CHECK3: .omp.final.then:
1926 // CHECK3-NEXT: [[TMP23:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1927 // CHECK3-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32
1928 // CHECK3-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1929 // CHECK3-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32
1930 // CHECK3-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
1931 // CHECK3-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
1932 // CHECK3-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
1933 // CHECK3-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
1934 // CHECK3-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
1935 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
1936 // CHECK3-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
1937 // CHECK3-NEXT: store i8 [[CONV21]], i8* [[TMP0]], align 1
1938 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
1939 // CHECK3: .omp.final.done:
1940 // CHECK3-NEXT: br label [[OMP_PRECOND_END]]
1941 // CHECK3: omp.precond.end:
1942 // CHECK3-NEXT: ret void
1943 //
1944 //
1945 // CHECK3-LABEL: define {{[^@]+}}@_Z4fintv
1946 // CHECK3-SAME: () #[[ATTR0]] {
1947 // CHECK3-NEXT: entry:
1948 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v()
1949 // CHECK3-NEXT: ret i32 [[CALL]]
1950 //
1951 //
1952 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
1953 // CHECK3-SAME: () #[[ATTR0]] comdat {
1954 // CHECK3-NEXT: entry:
1955 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
1956 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
1957 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
1958 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
1959 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
1960 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1961 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2
1962 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2
1963 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
1964 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2
1965 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
1966 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1967 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
1968 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4
1969 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1970 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
1971 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
1972 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1973 // CHECK3-NEXT: store i8* null, i8** [[TMP6]], align 4
1974 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1975 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1976 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1977 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1978 // CHECK3-NEXT: store i32 1, i32* [[TMP9]], align 4
1979 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1980 // CHECK3-NEXT: store i32 1, i32* [[TMP10]], align 4
1981 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1982 // CHECK3-NEXT: store i8** [[TMP7]], i8*** [[TMP11]], align 4
1983 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1984 // CHECK3-NEXT: store i8** [[TMP8]], i8*** [[TMP12]], align 4
1985 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1986 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64** [[TMP13]], align 4
1987 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1988 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i64** [[TMP14]], align 4
1989 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1990 // CHECK3-NEXT: store i8** null, i8*** [[TMP15]], align 4
1991 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1992 // CHECK3-NEXT: store i8** null, i8*** [[TMP16]], align 4
1993 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1994 // CHECK3-NEXT: store i64 100, i64* [[TMP17]], align 8
1995 // CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1996 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
1997 // CHECK3-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1998 // CHECK3: omp_offload.failed:
1999 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i32 [[TMP1]]) #[[ATTR3]]
2000 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
2001 // CHECK3: omp_offload.cont:
2002 // CHECK3-NEXT: ret i32 0
2003 //
2004 //
2005 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
2006 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] {
2007 // CHECK3-NEXT: entry:
2008 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
2009 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
2010 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
2011 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]])
2012 // CHECK3-NEXT: ret void
2013 //
2014 //
2015 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10
2016 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] {
2017 // CHECK3-NEXT: entry:
2018 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2019 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2020 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4
2021 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2022 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2023 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2024 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2025 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2026 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2027 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2028 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2029 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2030 // CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
2031 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
2032 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2033 // CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
2034 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2035 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2036 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
2037 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
2038 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2039 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2040 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
2041 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
2042 // CHECK3: omp.dispatch.cond:
2043 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2044 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
2045 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2046 // CHECK3: cond.true:
2047 // CHECK3-NEXT: br label [[COND_END:%.*]]
2048 // CHECK3: cond.false:
2049 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2050 // CHECK3-NEXT: br label [[COND_END]]
2051 // CHECK3: cond.end:
2052 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2053 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2054 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2055 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2056 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2057 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2058 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2059 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2060 // CHECK3: omp.dispatch.body:
2061 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2062 // CHECK3: omp.inner.for.cond:
2063 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
2064 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
2065 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
2066 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2067 // CHECK3: omp.inner.for.body:
2068 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
2069 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
2070 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2071 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
2072 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2073 // CHECK3: omp.body.continue:
2074 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2075 // CHECK3: omp.inner.for.inc:
2076 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
2077 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
2078 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
2079 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
2080 // CHECK3: omp.inner.for.end:
2081 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
2082 // CHECK3: omp.dispatch.inc:
2083 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2084 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2085 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
2086 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
2087 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2088 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2089 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
2090 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
2091 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
2092 // CHECK3: omp.dispatch.end:
2093 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
2094 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2095 // CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
2096 // CHECK3-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2097 // CHECK3: .omp.final.then:
2098 // CHECK3-NEXT: store i32 100, i32* [[I]], align 4
2099 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
2100 // CHECK3: .omp.final.done:
2101 // CHECK3-NEXT: ret void
2102 //
2103 //
2104 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2105 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
2106 // CHECK3-NEXT: entry:
2107 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
2108 // CHECK3-NEXT: ret void
2109 //
2110 //
2111 // CHECK5-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
2112 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
2113 // CHECK5-NEXT: entry:
2114 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
2115 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
2116 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
2117 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
2118 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
2119 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
2120 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
2121 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2122 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
2123 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
2124 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
2125 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
2126 // CHECK5-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8
2127 // CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8
2128 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8
2129 // CHECK5-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8
2130 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2131 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
2132 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8
2133 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2134 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
2135 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8
2136 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2137 // CHECK5-NEXT: store i8* null, i8** [[TMP8]], align 8
2138 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2139 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
2140 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8
2141 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2142 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
2143 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8
2144 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2145 // CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8
2146 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2147 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
2148 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8
2149 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2150 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
2151 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8
2152 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
2153 // CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8
2154 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2155 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
2156 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8
2157 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2158 // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
2159 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8
2160 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
2161 // CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8
2162 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2163 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2164 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2165 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
2166 // CHECK5-NEXT: store i32 1, i32* [[TMP26]], align 4
2167 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
2168 // CHECK5-NEXT: store i32 4, i32* [[TMP27]], align 4
2169 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
2170 // CHECK5-NEXT: store i8** [[TMP24]], i8*** [[TMP28]], align 8
2171 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
2172 // CHECK5-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 8
2173 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
2174 // CHECK5-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP30]], align 8
2175 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
2176 // CHECK5-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP31]], align 8
2177 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
2178 // CHECK5-NEXT: store i8** null, i8*** [[TMP32]], align 8
2179 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
2180 // CHECK5-NEXT: store i8** null, i8*** [[TMP33]], align 8
2181 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
2182 // CHECK5-NEXT: store i64 4571424, i64* [[TMP34]], align 8
2183 // CHECK5-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
2184 // CHECK5-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
2185 // CHECK5-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2186 // CHECK5: omp_offload.failed:
2187 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3:[0-9]+]]
2188 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
2189 // CHECK5: omp_offload.cont:
2190 // CHECK5-NEXT: ret void
2191 //
2192 //
2193 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
2194 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] {
2195 // CHECK5-NEXT: entry:
2196 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
2197 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
2198 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
2199 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
2200 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
2201 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
2202 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
2203 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
2204 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
2205 // CHECK5-NEXT: ret void
2206 //
2207 //
2208 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
2209 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
2210 // CHECK5-NEXT: entry:
2211 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2212 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2213 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
2214 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
2215 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
2216 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
2217 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2218 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2219 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2220 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2221 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2222 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2223 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2224 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2225 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2226 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
2227 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
2228 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
2229 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
2230 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
2231 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
2232 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
2233 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
2234 // CHECK5-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 8
2235 // CHECK5-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i64 16) ]
2236 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2237 // CHECK5-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
2238 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2239 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2240 // CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2241 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
2242 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2243 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2244 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
2245 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2246 // CHECK5: cond.true:
2247 // CHECK5-NEXT: br label [[COND_END:%.*]]
2248 // CHECK5: cond.false:
2249 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2250 // CHECK5-NEXT: br label [[COND_END]]
2251 // CHECK5: cond.end:
2252 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
2253 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2254 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2255 // CHECK5-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
2256 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2257 // CHECK5: omp.inner.for.cond:
2258 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
2259 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8
2260 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
2261 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2262 // CHECK5: omp.inner.for.body:
2263 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
2264 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
2265 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
2266 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
2267 // CHECK5-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !8
2268 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
2269 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
2270 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]]
2271 // CHECK5-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !8
2272 // CHECK5-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !8
2273 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
2274 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
2275 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM2]]
2276 // CHECK5-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !8
2277 // CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
2278 // CHECK5-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !8
2279 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
2280 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
2281 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM5]]
2282 // CHECK5-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !llvm.access.group !8
2283 // CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
2284 // CHECK5-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !8
2285 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
2286 // CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
2287 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM8]]
2288 // CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !8
2289 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2290 // CHECK5: omp.body.continue:
2291 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2292 // CHECK5: omp.inner.for.inc:
2293 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
2294 // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
2295 // CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
2296 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
2297 // CHECK5: omp.inner.for.end:
2298 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2299 // CHECK5: omp.loop.exit:
2300 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
2301 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2302 // CHECK5-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
2303 // CHECK5-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2304 // CHECK5: .omp.final.then:
2305 // CHECK5-NEXT: store i32 32000001, i32* [[I]], align 4
2306 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
2307 // CHECK5: .omp.final.done:
2308 // CHECK5-NEXT: ret void
2309 //
2310 //
2311 // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
2312 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
2313 // CHECK5-NEXT: entry:
2314 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
2315 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
2316 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
2317 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
2318 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
2319 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
2320 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
2321 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2322 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
2323 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
2324 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
2325 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
2326 // CHECK5-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8
2327 // CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8
2328 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8
2329 // CHECK5-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8
2330 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2331 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
2332 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8
2333 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2334 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
2335 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8
2336 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2337 // CHECK5-NEXT: store i8* null, i8** [[TMP8]], align 8
2338 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2339 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
2340 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8
2341 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2342 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
2343 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8
2344 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2345 // CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8
2346 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2347 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
2348 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8
2349 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2350 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
2351 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8
2352 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
2353 // CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8
2354 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2355 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
2356 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8
2357 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2358 // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
2359 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8
2360 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
2361 // CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8
2362 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2363 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2364 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2365 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
2366 // CHECK5-NEXT: store i32 1, i32* [[TMP26]], align 4
2367 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
2368 // CHECK5-NEXT: store i32 4, i32* [[TMP27]], align 4
2369 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
2370 // CHECK5-NEXT: store i8** [[TMP24]], i8*** [[TMP28]], align 8
2371 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
2372 // CHECK5-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 8
2373 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
2374 // CHECK5-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64** [[TMP30]], align 8
2375 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
2376 // CHECK5-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i64** [[TMP31]], align 8
2377 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
2378 // CHECK5-NEXT: store i8** null, i8*** [[TMP32]], align 8
2379 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
2380 // CHECK5-NEXT: store i8** null, i8*** [[TMP33]], align 8
2381 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
2382 // CHECK5-NEXT: store i64 4571424, i64* [[TMP34]], align 8
2383 // CHECK5-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
2384 // CHECK5-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
2385 // CHECK5-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2386 // CHECK5: omp_offload.failed:
2387 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
2388 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
2389 // CHECK5: omp_offload.cont:
2390 // CHECK5-NEXT: ret void
2391 //
2392 //
2393 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
2394 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] {
2395 // CHECK5-NEXT: entry:
2396 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
2397 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
2398 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
2399 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
2400 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
2401 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
2402 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
2403 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
2404 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
2405 // CHECK5-NEXT: ret void
2406 //
2407 //
2408 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1
2409 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
2410 // CHECK5-NEXT: entry:
2411 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2412 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2413 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
2414 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
2415 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
2416 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
2417 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2418 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2419 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2420 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2421 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2422 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2423 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2424 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2425 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2426 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
2427 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
2428 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
2429 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
2430 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
2431 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
2432 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
2433 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
2434 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2435 // CHECK5-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
2436 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2437 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2438 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2439 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
2440 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2441 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2442 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
2443 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2444 // CHECK5: cond.true:
2445 // CHECK5-NEXT: br label [[COND_END:%.*]]
2446 // CHECK5: cond.false:
2447 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2448 // CHECK5-NEXT: br label [[COND_END]]
2449 // CHECK5: cond.end:
2450 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
2451 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2452 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2453 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
2454 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2455 // CHECK5: omp.inner.for.cond:
2456 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2457 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2458 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
2459 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2460 // CHECK5: omp.inner.for.body:
2461 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2462 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
2463 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
2464 // CHECK5-NEXT: store i32 [[SUB]], i32* [[I]], align 4
2465 // CHECK5-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8, !nontemporal !15
2466 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
2467 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
2468 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]]
2469 // CHECK5-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
2470 // CHECK5-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8
2471 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
2472 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
2473 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]]
2474 // CHECK5-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4
2475 // CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
2476 // CHECK5-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8
2477 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
2478 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
2479 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]]
2480 // CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4
2481 // CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
2482 // CHECK5-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8, !nontemporal !15
2483 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
2484 // CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
2485 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]]
2486 // CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
2487 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2488 // CHECK5: omp.body.continue:
2489 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2490 // CHECK5: omp.inner.for.inc:
2491 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2492 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
2493 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2494 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
2495 // CHECK5: omp.inner.for.end:
2496 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2497 // CHECK5: omp.loop.exit:
2498 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
2499 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2500 // CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
2501 // CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2502 // CHECK5: .omp.final.then:
2503 // CHECK5-NEXT: store i32 32, i32* [[I]], align 4
2504 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
2505 // CHECK5: .omp.final.done:
2506 // CHECK5-NEXT: ret void
2507 //
2508 //
2509 // CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
2510 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
2511 // CHECK5-NEXT: entry:
2512 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
2513 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
2514 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
2515 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
2516 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
2517 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
2518 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
2519 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2520 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
2521 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
2522 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
2523 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
2524 // CHECK5-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8
2525 // CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8
2526 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8
2527 // CHECK5-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8
2528 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2529 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
2530 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8
2531 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2532 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
2533 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8
2534 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2535 // CHECK5-NEXT: store i8* null, i8** [[TMP8]], align 8
2536 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2537 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
2538 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8
2539 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2540 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
2541 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8
2542 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2543 // CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8
2544 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2545 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
2546 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8
2547 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2548 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
2549 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8
2550 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
2551 // CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8
2552 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2553 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
2554 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8
2555 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2556 // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
2557 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8
2558 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
2559 // CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8
2560 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2561 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2562 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2563 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
2564 // CHECK5-NEXT: store i32 1, i32* [[TMP26]], align 4
2565 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
2566 // CHECK5-NEXT: store i32 4, i32* [[TMP27]], align 4
2567 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
2568 // CHECK5-NEXT: store i8** [[TMP24]], i8*** [[TMP28]], align 8
2569 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
2570 // CHECK5-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 8
2571 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
2572 // CHECK5-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64** [[TMP30]], align 8
2573 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
2574 // CHECK5-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP31]], align 8
2575 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
2576 // CHECK5-NEXT: store i8** null, i8*** [[TMP32]], align 8
2577 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
2578 // CHECK5-NEXT: store i8** null, i8*** [[TMP33]], align 8
2579 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
2580 // CHECK5-NEXT: store i64 16908289, i64* [[TMP34]], align 8
2581 // CHECK5-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
2582 // CHECK5-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
2583 // CHECK5-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2584 // CHECK5: omp_offload.failed:
2585 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
2586 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
2587 // CHECK5: omp_offload.cont:
2588 // CHECK5-NEXT: ret void
2589 //
2590 //
2591 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
2592 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] {
2593 // CHECK5-NEXT: entry:
2594 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
2595 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
2596 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
2597 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
2598 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
2599 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
2600 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
2601 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
2602 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
2603 // CHECK5-NEXT: ret void
2604 //
2605 //
2606 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4
2607 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
2608 // CHECK5-NEXT: entry:
2609 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2610 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2611 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
2612 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
2613 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
2614 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
2615 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2616 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2617 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2618 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2619 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2620 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2621 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2622 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2623 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2624 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
2625 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
2626 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
2627 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
2628 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
2629 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
2630 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
2631 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
2632 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2633 // CHECK5-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
2634 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2635 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2636 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2637 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
2638 // CHECK5-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
2639 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
2640 // CHECK5: omp.dispatch.cond:
2641 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2642 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
2643 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2644 // CHECK5: cond.true:
2645 // CHECK5-NEXT: br label [[COND_END:%.*]]
2646 // CHECK5: cond.false:
2647 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2648 // CHECK5-NEXT: br label [[COND_END]]
2649 // CHECK5: cond.end:
2650 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
2651 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2652 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2653 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
2654 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2655 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2656 // CHECK5-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
2657 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2658 // CHECK5: omp.dispatch.body:
2659 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2660 // CHECK5: omp.inner.for.cond:
2661 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
2662 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
2663 // CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
2664 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2665 // CHECK5: omp.inner.for.body:
2666 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
2667 // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
2668 // CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
2669 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
2670 // CHECK5-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !18
2671 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
2672 // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
2673 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]]
2674 // CHECK5-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !18
2675 // CHECK5-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !18
2676 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
2677 // CHECK5-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
2678 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]]
2679 // CHECK5-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !18
2680 // CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
2681 // CHECK5-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !18
2682 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
2683 // CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
2684 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]]
2685 // CHECK5-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !18
2686 // CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
2687 // CHECK5-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !18
2688 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
2689 // CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
2690 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]]
2691 // CHECK5-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !18
2692 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2693 // CHECK5: omp.body.continue:
2694 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2695 // CHECK5: omp.inner.for.inc:
2696 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
2697 // CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
2698 // CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
2699 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
2700 // CHECK5: omp.inner.for.end:
2701 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
2702 // CHECK5: omp.dispatch.inc:
2703 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2704 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2705 // CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
2706 // CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
2707 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2708 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2709 // CHECK5-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
2710 // CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4
2711 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]]
2712 // CHECK5: omp.dispatch.end:
2713 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
2714 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2715 // CHECK5-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
2716 // CHECK5-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2717 // CHECK5: .omp.final.then:
2718 // CHECK5-NEXT: store i32 -2147483522, i32* [[I]], align 4
2719 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
2720 // CHECK5: .omp.final.done:
2721 // CHECK5-NEXT: ret void
2722 //
2723 //
2724 // CHECK5-LABEL: define {{[^@]+}}@_Z12test_precondv
2725 // CHECK5-SAME: () #[[ATTR0]] {
2726 // CHECK5-NEXT: entry:
2727 // CHECK5-NEXT: [[A:%.*]] = alloca i8, align 1
2728 // CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1
2729 // CHECK5-NEXT: [[I_CASTED:%.*]] = alloca i64, align 8
2730 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
2731 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8
2732 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8
2733 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8
2734 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1
2735 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2736 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
2737 // CHECK5-NEXT: store i8 0, i8* [[A]], align 1
2738 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1
2739 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[I_CASTED]] to i8*
2740 // CHECK5-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1
2741 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[I_CASTED]], align 8
2742 // CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[A]], align 1
2743 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i8*
2744 // CHECK5-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
2745 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8
2746 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2747 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
2748 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
2749 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2750 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
2751 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8
2752 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2753 // CHECK5-NEXT: store i8* null, i8** [[TMP8]], align 8
2754 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2755 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
2756 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8
2757 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2758 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
2759 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8
2760 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2761 // CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8
2762 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2763 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2764 // CHECK5-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1
2765 // CHECK5-NEXT: store i8 [[TMP16]], i8* [[DOTCAPTURE_EXPR_]], align 1
2766 // CHECK5-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
2767 // CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP17]] to i32
2768 // CHECK5-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV3]]
2769 // CHECK5-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1
2770 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1
2771 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
2772 // CHECK5-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1
2773 // CHECK5-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
2774 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
2775 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
2776 // CHECK5-NEXT: [[TMP19:%.*]] = zext i32 [[ADD6]] to i64
2777 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2778 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
2779 // CHECK5-NEXT: store i32 1, i32* [[TMP20]], align 4
2780 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
2781 // CHECK5-NEXT: store i32 2, i32* [[TMP21]], align 4
2782 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
2783 // CHECK5-NEXT: store i8** [[TMP14]], i8*** [[TMP22]], align 8
2784 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
2785 // CHECK5-NEXT: store i8** [[TMP15]], i8*** [[TMP23]], align 8
2786 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
2787 // CHECK5-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64** [[TMP24]], align 8
2788 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
2789 // CHECK5-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i64** [[TMP25]], align 8
2790 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
2791 // CHECK5-NEXT: store i8** null, i8*** [[TMP26]], align 8
2792 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
2793 // CHECK5-NEXT: store i8** null, i8*** [[TMP27]], align 8
2794 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
2795 // CHECK5-NEXT: store i64 [[TMP19]], i64* [[TMP28]], align 8
2796 // CHECK5-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
2797 // CHECK5-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
2798 // CHECK5-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2799 // CHECK5: omp_offload.failed:
2800 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i64 [[TMP1]], i64 [[TMP3]]) #[[ATTR3]]
2801 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
2802 // CHECK5: omp_offload.cont:
2803 // CHECK5-NEXT: ret void
2804 //
2805 //
2806 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
2807 // CHECK5-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {
2808 // CHECK5-NEXT: entry:
2809 // CHECK5-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8
2810 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
2811 // CHECK5-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
2812 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
2813 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i8*
2814 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i8*
2815 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
2816 // CHECK5-NEXT: ret void
2817 //
2818 //
2819 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7
2820 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] {
2821 // CHECK5-NEXT: entry:
2822 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2823 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2824 // CHECK5-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 8
2825 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8
2826 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2827 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1
2828 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2829 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
2830 // CHECK5-NEXT: [[I4:%.*]] = alloca i8, align 1
2831 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2832 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2833 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2834 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2835 // CHECK5-NEXT: [[I6:%.*]] = alloca i8, align 1
2836 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2837 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2838 // CHECK5-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 8
2839 // CHECK5-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8
2840 // CHECK5-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 8
2841 // CHECK5-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 8
2842 // CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
2843 // CHECK5-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
2844 // CHECK5-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
2845 // CHECK5-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
2846 // CHECK5-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
2847 // CHECK5-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
2848 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
2849 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
2850 // CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
2851 // CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
2852 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
2853 // CHECK5-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
2854 // CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
2855 // CHECK5-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
2856 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
2857 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
2858 // CHECK5: omp.precond.then:
2859 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2860 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
2861 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
2862 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2863 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2864 // CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2865 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
2866 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2867 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2868 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
2869 // CHECK5-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
2870 // CHECK5-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2871 // CHECK5: cond.true:
2872 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
2873 // CHECK5-NEXT: br label [[COND_END:%.*]]
2874 // CHECK5: cond.false:
2875 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2876 // CHECK5-NEXT: br label [[COND_END]]
2877 // CHECK5: cond.end:
2878 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
2879 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2880 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2881 // CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
2882 // CHECK5-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP1]], align 1
2883 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
2884 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2885 // CHECK5: omp_if.then:
2886 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2887 // CHECK5: omp.inner.for.cond:
2888 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
2889 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
2890 // CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
2891 // CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2892 // CHECK5: omp.inner.for.body:
2893 // CHECK5-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21
2894 // CHECK5-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
2895 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
2896 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
2897 // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
2898 // CHECK5-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
2899 // CHECK5-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !15, !llvm.access.group !21
2900 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2901 // CHECK5: omp.body.continue:
2902 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2903 // CHECK5: omp.inner.for.inc:
2904 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
2905 // CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
2906 // CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
2907 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
2908 // CHECK5: omp.inner.for.end:
2909 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]]
2910 // CHECK5: omp_if.else:
2911 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
2912 // CHECK5: omp.inner.for.cond13:
2913 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2914 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2915 // CHECK5-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
2916 // CHECK5-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
2917 // CHECK5: omp.inner.for.body15:
2918 // CHECK5-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
2919 // CHECK5-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
2920 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2921 // CHECK5-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
2922 // CHECK5-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
2923 // CHECK5-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
2924 // CHECK5-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
2925 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
2926 // CHECK5: omp.body.continue20:
2927 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
2928 // CHECK5: omp.inner.for.inc21:
2929 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2930 // CHECK5-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
2931 // CHECK5-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
2932 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP24:![0-9]+]]
2933 // CHECK5: omp.inner.for.end23:
2934 // CHECK5-NEXT: br label [[OMP_IF_END]]
2935 // CHECK5: omp_if.end:
2936 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2937 // CHECK5: omp.loop.exit:
2938 // CHECK5-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2939 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
2940 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
2941 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2942 // CHECK5-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
2943 // CHECK5-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2944 // CHECK5: .omp.final.then:
2945 // CHECK5-NEXT: [[TMP29:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
2946 // CHECK5-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32
2947 // CHECK5-NEXT: [[TMP30:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
2948 // CHECK5-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32
2949 // CHECK5-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
2950 // CHECK5-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
2951 // CHECK5-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
2952 // CHECK5-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
2953 // CHECK5-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
2954 // CHECK5-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
2955 // CHECK5-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
2956 // CHECK5-NEXT: store i8 [[CONV32]], i8* [[TMP0]], align 1
2957 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
2958 // CHECK5: .omp.final.done:
2959 // CHECK5-NEXT: br label [[OMP_PRECOND_END]]
2960 // CHECK5: omp.precond.end:
2961 // CHECK5-NEXT: ret void
2962 //
2963 //
2964 // CHECK5-LABEL: define {{[^@]+}}@_Z4fintv
2965 // CHECK5-SAME: () #[[ATTR0]] {
2966 // CHECK5-NEXT: entry:
2967 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v()
2968 // CHECK5-NEXT: ret i32 [[CALL]]
2969 //
2970 //
2971 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
2972 // CHECK5-SAME: () #[[ATTR0]] comdat {
2973 // CHECK5-NEXT: entry:
2974 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2
2975 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
2976 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
2977 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
2978 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
2979 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2980 // CHECK5-NEXT: store i16 0, i16* [[AA]], align 2
2981 // CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2
2982 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2983 // CHECK5-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2
2984 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2985 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2986 // CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
2987 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8
2988 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2989 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
2990 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
2991 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2992 // CHECK5-NEXT: store i8* null, i8** [[TMP6]], align 8
2993 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2994 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2995 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2996 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
2997 // CHECK5-NEXT: store i32 1, i32* [[TMP9]], align 4
2998 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
2999 // CHECK5-NEXT: store i32 1, i32* [[TMP10]], align 4
3000 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
3001 // CHECK5-NEXT: store i8** [[TMP7]], i8*** [[TMP11]], align 8
3002 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
3003 // CHECK5-NEXT: store i8** [[TMP8]], i8*** [[TMP12]], align 8
3004 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
3005 // CHECK5-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64** [[TMP13]], align 8
3006 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
3007 // CHECK5-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i64** [[TMP14]], align 8
3008 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
3009 // CHECK5-NEXT: store i8** null, i8*** [[TMP15]], align 8
3010 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
3011 // CHECK5-NEXT: store i8** null, i8*** [[TMP16]], align 8
3012 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
3013 // CHECK5-NEXT: store i64 100, i64* [[TMP17]], align 8
3014 // CHECK5-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
3015 // CHECK5-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
3016 // CHECK5-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3017 // CHECK5: omp_offload.failed:
3018 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i64 [[TMP1]]) #[[ATTR3]]
3019 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
3020 // CHECK5: omp_offload.cont:
3021 // CHECK5-NEXT: ret i32 0
3022 //
3023 //
3024 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
3025 // CHECK5-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] {
3026 // CHECK5-NEXT: entry:
3027 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
3028 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
3029 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3030 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]])
3031 // CHECK5-NEXT: ret void
3032 //
3033 //
3034 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10
3035 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] {
3036 // CHECK5-NEXT: entry:
3037 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3038 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3039 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8
3040 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3041 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
3042 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3043 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3044 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3045 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3046 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
3047 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3048 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3049 // CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
3050 // CHECK5-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
3051 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3052 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
3053 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3054 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3055 // CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
3056 // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
3057 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3058 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
3059 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
3060 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
3061 // CHECK5: omp.dispatch.cond:
3062 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3063 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
3064 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3065 // CHECK5: cond.true:
3066 // CHECK5-NEXT: br label [[COND_END:%.*]]
3067 // CHECK5: cond.false:
3068 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3069 // CHECK5-NEXT: br label [[COND_END]]
3070 // CHECK5: cond.end:
3071 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
3072 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3073 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3074 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
3075 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3076 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3077 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
3078 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
3079 // CHECK5: omp.dispatch.body:
3080 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3081 // CHECK5: omp.inner.for.cond:
3082 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
3083 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !26
3084 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
3085 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3086 // CHECK5: omp.inner.for.body:
3087 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
3088 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
3089 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3090 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !26
3091 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3092 // CHECK5: omp.body.continue:
3093 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3094 // CHECK5: omp.inner.for.inc:
3095 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
3096 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
3097 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
3098 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
3099 // CHECK5: omp.inner.for.end:
3100 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
3101 // CHECK5: omp.dispatch.inc:
3102 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3103 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3104 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
3105 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
3106 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3107 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3108 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
3109 // CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
3110 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]]
3111 // CHECK5: omp.dispatch.end:
3112 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
3113 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3114 // CHECK5-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
3115 // CHECK5-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3116 // CHECK5: .omp.final.then:
3117 // CHECK5-NEXT: store i32 100, i32* [[I]], align 4
3118 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
3119 // CHECK5: .omp.final.done:
3120 // CHECK5-NEXT: ret void
3121 //
3122 //
3123 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3124 // CHECK5-SAME: () #[[ATTR4:[0-9]+]] {
3125 // CHECK5-NEXT: entry:
3126 // CHECK5-NEXT: call void @__tgt_register_requires(i64 1)
3127 // CHECK5-NEXT: ret void
3128 //
3129 //
3130 // CHECK7-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
3131 // CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
3132 // CHECK7-NEXT: entry:
3133 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
3134 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
3135 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
3136 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
3137 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
3138 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
3139 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
3140 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
3141 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
3142 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
3143 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
3144 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
3145 // CHECK7-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4
3146 // CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4
3147 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4
3148 // CHECK7-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4
3149 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3150 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
3151 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4
3152 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3153 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
3154 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4
3155 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3156 // CHECK7-NEXT: store i8* null, i8** [[TMP8]], align 4
3157 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3158 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
3159 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4
3160 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3161 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
3162 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4
3163 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3164 // CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4
3165 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3166 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
3167 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4
3168 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3169 // CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
3170 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4
3171 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3172 // CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4
3173 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3174 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
3175 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4
3176 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3177 // CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
3178 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4
3179 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3180 // CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4
3181 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3182 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3183 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3184 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
3185 // CHECK7-NEXT: store i32 1, i32* [[TMP26]], align 4
3186 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
3187 // CHECK7-NEXT: store i32 4, i32* [[TMP27]], align 4
3188 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
3189 // CHECK7-NEXT: store i8** [[TMP24]], i8*** [[TMP28]], align 4
3190 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
3191 // CHECK7-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 4
3192 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
3193 // CHECK7-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP30]], align 4
3194 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
3195 // CHECK7-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP31]], align 4
3196 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
3197 // CHECK7-NEXT: store i8** null, i8*** [[TMP32]], align 4
3198 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
3199 // CHECK7-NEXT: store i8** null, i8*** [[TMP33]], align 4
3200 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
3201 // CHECK7-NEXT: store i64 4571424, i64* [[TMP34]], align 8
3202 // CHECK7-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
3203 // CHECK7-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
3204 // CHECK7-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3205 // CHECK7: omp_offload.failed:
3206 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3:[0-9]+]]
3207 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
3208 // CHECK7: omp_offload.cont:
3209 // CHECK7-NEXT: ret void
3210 //
3211 //
3212 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
3213 // CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] {
3214 // CHECK7-NEXT: entry:
3215 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
3216 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
3217 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
3218 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
3219 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
3220 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
3221 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
3222 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
3223 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
3224 // CHECK7-NEXT: ret void
3225 //
3226 //
3227 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined.
3228 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
3229 // CHECK7-NEXT: entry:
3230 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3231 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3232 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
3233 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
3234 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
3235 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
3236 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3237 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
3238 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3239 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3240 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3241 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3242 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
3243 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3244 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3245 // CHECK7-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
3246 // CHECK7-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
3247 // CHECK7-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
3248 // CHECK7-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
3249 // CHECK7-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
3250 // CHECK7-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
3251 // CHECK7-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
3252 // CHECK7-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
3253 // CHECK7-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 4
3254 // CHECK7-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i32 16) ]
3255 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3256 // CHECK7-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
3257 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3258 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3259 // CHECK7-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3260 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
3261 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3262 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3263 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
3264 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3265 // CHECK7: cond.true:
3266 // CHECK7-NEXT: br label [[COND_END:%.*]]
3267 // CHECK7: cond.false:
3268 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3269 // CHECK7-NEXT: br label [[COND_END]]
3270 // CHECK7: cond.end:
3271 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
3272 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3273 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3274 // CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
3275 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3276 // CHECK7: omp.inner.for.cond:
3277 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
3278 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
3279 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
3280 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3281 // CHECK7: omp.inner.for.body:
3282 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
3283 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
3284 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
3285 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
3286 // CHECK7-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !9
3287 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
3288 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
3289 // CHECK7-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9
3290 // CHECK7-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !9
3291 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
3292 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP16]], i32 [[TMP17]]
3293 // CHECK7-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !9
3294 // CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
3295 // CHECK7-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !9
3296 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
3297 // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP19]], i32 [[TMP20]]
3298 // CHECK7-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !9
3299 // CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
3300 // CHECK7-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !9
3301 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
3302 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP22]], i32 [[TMP23]]
3303 // CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !9
3304 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3305 // CHECK7: omp.body.continue:
3306 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3307 // CHECK7: omp.inner.for.inc:
3308 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
3309 // CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
3310 // CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
3311 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
3312 // CHECK7: omp.inner.for.end:
3313 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3314 // CHECK7: omp.loop.exit:
3315 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
3316 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3317 // CHECK7-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
3318 // CHECK7-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3319 // CHECK7: .omp.final.then:
3320 // CHECK7-NEXT: store i32 32000001, i32* [[I]], align 4
3321 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]
3322 // CHECK7: .omp.final.done:
3323 // CHECK7-NEXT: ret void
3324 //
3325 //
3326 // CHECK7-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
3327 // CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
3328 // CHECK7-NEXT: entry:
3329 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
3330 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
3331 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
3332 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
3333 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
3334 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
3335 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
3336 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
3337 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
3338 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
3339 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
3340 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
3341 // CHECK7-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4
3342 // CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4
3343 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4
3344 // CHECK7-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4
3345 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3346 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
3347 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4
3348 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3349 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
3350 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4
3351 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3352 // CHECK7-NEXT: store i8* null, i8** [[TMP8]], align 4
3353 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3354 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
3355 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4
3356 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3357 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
3358 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4
3359 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3360 // CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4
3361 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3362 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
3363 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4
3364 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3365 // CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
3366 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4
3367 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3368 // CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4
3369 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3370 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
3371 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4
3372 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3373 // CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
3374 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4
3375 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3376 // CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4
3377 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3378 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3379 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3380 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
3381 // CHECK7-NEXT: store i32 1, i32* [[TMP26]], align 4
3382 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
3383 // CHECK7-NEXT: store i32 4, i32* [[TMP27]], align 4
3384 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
3385 // CHECK7-NEXT: store i8** [[TMP24]], i8*** [[TMP28]], align 4
3386 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
3387 // CHECK7-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 4
3388 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
3389 // CHECK7-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64** [[TMP30]], align 4
3390 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
3391 // CHECK7-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i64** [[TMP31]], align 4
3392 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
3393 // CHECK7-NEXT: store i8** null, i8*** [[TMP32]], align 4
3394 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
3395 // CHECK7-NEXT: store i8** null, i8*** [[TMP33]], align 4
3396 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
3397 // CHECK7-NEXT: store i64 4571424, i64* [[TMP34]], align 8
3398 // CHECK7-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
3399 // CHECK7-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
3400 // CHECK7-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3401 // CHECK7: omp_offload.failed:
3402 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
3403 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
3404 // CHECK7: omp_offload.cont:
3405 // CHECK7-NEXT: ret void
3406 //
3407 //
3408 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
3409 // CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] {
3410 // CHECK7-NEXT: entry:
3411 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
3412 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
3413 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
3414 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
3415 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
3416 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
3417 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
3418 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
3419 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
3420 // CHECK7-NEXT: ret void
3421 //
3422 //
3423 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1
3424 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
3425 // CHECK7-NEXT: entry:
3426 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3427 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3428 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
3429 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
3430 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
3431 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
3432 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3433 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
3434 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3435 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3436 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3437 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3438 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
3439 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3440 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3441 // CHECK7-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
3442 // CHECK7-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
3443 // CHECK7-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
3444 // CHECK7-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
3445 // CHECK7-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
3446 // CHECK7-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
3447 // CHECK7-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
3448 // CHECK7-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
3449 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3450 // CHECK7-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
3451 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3452 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3453 // CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3454 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
3455 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3456 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3457 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
3458 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3459 // CHECK7: cond.true:
3460 // CHECK7-NEXT: br label [[COND_END:%.*]]
3461 // CHECK7: cond.false:
3462 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3463 // CHECK7-NEXT: br label [[COND_END]]
3464 // CHECK7: cond.end:
3465 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3466 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3467 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3468 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
3469 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3470 // CHECK7: omp.inner.for.cond:
3471 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3472 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3473 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
3474 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3475 // CHECK7: omp.inner.for.body:
3476 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3477 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
3478 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
3479 // CHECK7-NEXT: store i32 [[SUB]], i32* [[I]], align 4
3480 // CHECK7-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4, !nontemporal !16
3481 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
3482 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]]
3483 // CHECK7-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
3484 // CHECK7-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4
3485 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
3486 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]]
3487 // CHECK7-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4
3488 // CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
3489 // CHECK7-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4
3490 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
3491 // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]]
3492 // CHECK7-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4
3493 // CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
3494 // CHECK7-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4, !nontemporal !16
3495 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
3496 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]]
3497 // CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
3498 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3499 // CHECK7: omp.body.continue:
3500 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3501 // CHECK7: omp.inner.for.inc:
3502 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3503 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
3504 // CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
3505 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
3506 // CHECK7: omp.inner.for.end:
3507 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3508 // CHECK7: omp.loop.exit:
3509 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
3510 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3511 // CHECK7-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
3512 // CHECK7-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3513 // CHECK7: .omp.final.then:
3514 // CHECK7-NEXT: store i32 32, i32* [[I]], align 4
3515 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]
3516 // CHECK7: .omp.final.done:
3517 // CHECK7-NEXT: ret void
3518 //
3519 //
3520 // CHECK7-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
3521 // CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
3522 // CHECK7-NEXT: entry:
3523 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
3524 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
3525 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
3526 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
3527 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
3528 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
3529 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
3530 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
3531 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
3532 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
3533 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
3534 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
3535 // CHECK7-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4
3536 // CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4
3537 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4
3538 // CHECK7-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4
3539 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3540 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
3541 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4
3542 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3543 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
3544 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4
3545 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3546 // CHECK7-NEXT: store i8* null, i8** [[TMP8]], align 4
3547 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3548 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
3549 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4
3550 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3551 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
3552 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4
3553 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3554 // CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4
3555 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3556 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
3557 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4
3558 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3559 // CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
3560 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4
3561 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3562 // CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4
3563 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3564 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
3565 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4
3566 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3567 // CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
3568 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4
3569 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3570 // CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4
3571 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3572 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3573 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3574 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
3575 // CHECK7-NEXT: store i32 1, i32* [[TMP26]], align 4
3576 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
3577 // CHECK7-NEXT: store i32 4, i32* [[TMP27]], align 4
3578 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
3579 // CHECK7-NEXT: store i8** [[TMP24]], i8*** [[TMP28]], align 4
3580 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
3581 // CHECK7-NEXT: store i8** [[TMP25]], i8*** [[TMP29]], align 4
3582 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
3583 // CHECK7-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64** [[TMP30]], align 4
3584 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
3585 // CHECK7-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP31]], align 4
3586 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
3587 // CHECK7-NEXT: store i8** null, i8*** [[TMP32]], align 4
3588 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
3589 // CHECK7-NEXT: store i8** null, i8*** [[TMP33]], align 4
3590 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
3591 // CHECK7-NEXT: store i64 16908289, i64* [[TMP34]], align 8
3592 // CHECK7-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
3593 // CHECK7-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
3594 // CHECK7-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3595 // CHECK7: omp_offload.failed:
3596 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
3597 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
3598 // CHECK7: omp_offload.cont:
3599 // CHECK7-NEXT: ret void
3600 //
3601 //
3602 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
3603 // CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] {
3604 // CHECK7-NEXT: entry:
3605 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
3606 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
3607 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
3608 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
3609 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
3610 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
3611 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
3612 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
3613 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
3614 // CHECK7-NEXT: ret void
3615 //
3616 //
3617 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4
3618 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
3619 // CHECK7-NEXT: entry:
3620 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3621 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3622 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
3623 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
3624 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
3625 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
3626 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3627 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
3628 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3629 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3630 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3631 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3632 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
3633 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3634 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3635 // CHECK7-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
3636 // CHECK7-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
3637 // CHECK7-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
3638 // CHECK7-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
3639 // CHECK7-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
3640 // CHECK7-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
3641 // CHECK7-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
3642 // CHECK7-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
3643 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3644 // CHECK7-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
3645 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3646 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3647 // CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3648 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
3649 // CHECK7-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
3650 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
3651 // CHECK7: omp.dispatch.cond:
3652 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3653 // CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
3654 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3655 // CHECK7: cond.true:
3656 // CHECK7-NEXT: br label [[COND_END:%.*]]
3657 // CHECK7: cond.false:
3658 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3659 // CHECK7-NEXT: br label [[COND_END]]
3660 // CHECK7: cond.end:
3661 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3662 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3663 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3664 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
3665 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3666 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3667 // CHECK7-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
3668 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
3669 // CHECK7: omp.dispatch.body:
3670 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3671 // CHECK7: omp.inner.for.cond:
3672 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
3673 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
3674 // CHECK7-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
3675 // CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3676 // CHECK7: omp.inner.for.body:
3677 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
3678 // CHECK7-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
3679 // CHECK7-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
3680 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
3681 // CHECK7-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !19
3682 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
3683 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
3684 // CHECK7-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !19
3685 // CHECK7-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !19
3686 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
3687 // CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]]
3688 // CHECK7-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !19
3689 // CHECK7-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
3690 // CHECK7-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !19
3691 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
3692 // CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]]
3693 // CHECK7-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !19
3694 // CHECK7-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
3695 // CHECK7-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !19
3696 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
3697 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]]
3698 // CHECK7-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !19
3699 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3700 // CHECK7: omp.body.continue:
3701 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3702 // CHECK7: omp.inner.for.inc:
3703 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
3704 // CHECK7-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
3705 // CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
3706 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
3707 // CHECK7: omp.inner.for.end:
3708 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
3709 // CHECK7: omp.dispatch.inc:
3710 // CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3711 // CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3712 // CHECK7-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
3713 // CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
3714 // CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3715 // CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3716 // CHECK7-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]]
3717 // CHECK7-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4
3718 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]]
3719 // CHECK7: omp.dispatch.end:
3720 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
3721 // CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3722 // CHECK7-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
3723 // CHECK7-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3724 // CHECK7: .omp.final.then:
3725 // CHECK7-NEXT: store i32 -2147483522, i32* [[I]], align 4
3726 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]
3727 // CHECK7: .omp.final.done:
3728 // CHECK7-NEXT: ret void
3729 //
3730 //
3731 // CHECK7-LABEL: define {{[^@]+}}@_Z12test_precondv
3732 // CHECK7-SAME: () #[[ATTR0]] {
3733 // CHECK7-NEXT: entry:
3734 // CHECK7-NEXT: [[A:%.*]] = alloca i8, align 1
3735 // CHECK7-NEXT: [[I:%.*]] = alloca i8, align 1
3736 // CHECK7-NEXT: [[I_CASTED:%.*]] = alloca i32, align 4
3737 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
3738 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4
3739 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4
3740 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4
3741 // CHECK7-NEXT: [[TMP:%.*]] = alloca i8, align 1
3742 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
3743 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
3744 // CHECK7-NEXT: store i8 0, i8* [[A]], align 1
3745 // CHECK7-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1
3746 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[I_CASTED]] to i8*
3747 // CHECK7-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1
3748 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I_CASTED]], align 4
3749 // CHECK7-NEXT: [[TMP2:%.*]] = load i8, i8* [[A]], align 1
3750 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_CASTED]] to i8*
3751 // CHECK7-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
3752 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4
3753 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3754 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
3755 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
3756 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3757 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
3758 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4
3759 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3760 // CHECK7-NEXT: store i8* null, i8** [[TMP8]], align 4
3761 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3762 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
3763 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4
3764 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3765 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
3766 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4
3767 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3768 // CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4
3769 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3770 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3771 // CHECK7-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1
3772 // CHECK7-NEXT: store i8 [[TMP16]], i8* [[DOTCAPTURE_EXPR_]], align 1
3773 // CHECK7-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
3774 // CHECK7-NEXT: [[CONV3:%.*]] = sext i8 [[TMP17]] to i32
3775 // CHECK7-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV3]]
3776 // CHECK7-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1
3777 // CHECK7-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1
3778 // CHECK7-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
3779 // CHECK7-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1
3780 // CHECK7-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
3781 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
3782 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
3783 // CHECK7-NEXT: [[TMP19:%.*]] = zext i32 [[ADD6]] to i64
3784 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3785 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
3786 // CHECK7-NEXT: store i32 1, i32* [[TMP20]], align 4
3787 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
3788 // CHECK7-NEXT: store i32 2, i32* [[TMP21]], align 4
3789 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
3790 // CHECK7-NEXT: store i8** [[TMP14]], i8*** [[TMP22]], align 4
3791 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
3792 // CHECK7-NEXT: store i8** [[TMP15]], i8*** [[TMP23]], align 4
3793 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
3794 // CHECK7-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64** [[TMP24]], align 4
3795 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
3796 // CHECK7-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i64** [[TMP25]], align 4
3797 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
3798 // CHECK7-NEXT: store i8** null, i8*** [[TMP26]], align 4
3799 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
3800 // CHECK7-NEXT: store i8** null, i8*** [[TMP27]], align 4
3801 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
3802 // CHECK7-NEXT: store i64 [[TMP19]], i64* [[TMP28]], align 8
3803 // CHECK7-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
3804 // CHECK7-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
3805 // CHECK7-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3806 // CHECK7: omp_offload.failed:
3807 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i32 [[TMP1]], i32 [[TMP3]]) #[[ATTR3]]
3808 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
3809 // CHECK7: omp_offload.cont:
3810 // CHECK7-NEXT: ret void
3811 //
3812 //
3813 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
3814 // CHECK7-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] {
3815 // CHECK7-NEXT: entry:
3816 // CHECK7-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4
3817 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3818 // CHECK7-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4
3819 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3820 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[I_ADDR]] to i8*
3821 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_ADDR]] to i8*
3822 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
3823 // CHECK7-NEXT: ret void
3824 //
3825 //
3826 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7
3827 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] {
3828 // CHECK7-NEXT: entry:
3829 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3830 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3831 // CHECK7-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 4
3832 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4
3833 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3834 // CHECK7-NEXT: [[TMP:%.*]] = alloca i8, align 1
3835 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
3836 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
3837 // CHECK7-NEXT: [[I4:%.*]] = alloca i8, align 1
3838 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3839 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3840 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3841 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3842 // CHECK7-NEXT: [[I6:%.*]] = alloca i8, align 1
3843 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3844 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3845 // CHECK7-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 4
3846 // CHECK7-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4
3847 // CHECK7-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 4
3848 // CHECK7-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 4
3849 // CHECK7-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
3850 // CHECK7-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
3851 // CHECK7-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
3852 // CHECK7-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
3853 // CHECK7-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
3854 // CHECK7-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
3855 // CHECK7-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
3856 // CHECK7-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
3857 // CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
3858 // CHECK7-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
3859 // CHECK7-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
3860 // CHECK7-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
3861 // CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
3862 // CHECK7-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
3863 // CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
3864 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
3865 // CHECK7: omp.precond.then:
3866 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3867 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
3868 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
3869 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3870 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3871 // CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3872 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
3873 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3874 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3875 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
3876 // CHECK7-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
3877 // CHECK7-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3878 // CHECK7: cond.true:
3879 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
3880 // CHECK7-NEXT: br label [[COND_END:%.*]]
3881 // CHECK7: cond.false:
3882 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3883 // CHECK7-NEXT: br label [[COND_END]]
3884 // CHECK7: cond.end:
3885 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
3886 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3887 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3888 // CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
3889 // CHECK7-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP1]], align 1
3890 // CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
3891 // CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3892 // CHECK7: omp_if.then:
3893 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3894 // CHECK7: omp.inner.for.cond:
3895 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
3896 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
3897 // CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
3898 // CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3899 // CHECK7: omp.inner.for.body:
3900 // CHECK7-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22
3901 // CHECK7-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
3902 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
3903 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
3904 // CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
3905 // CHECK7-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
3906 // CHECK7-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !16, !llvm.access.group !22
3907 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3908 // CHECK7: omp.body.continue:
3909 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3910 // CHECK7: omp.inner.for.inc:
3911 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
3912 // CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
3913 // CHECK7-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
3914 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
3915 // CHECK7: omp.inner.for.end:
3916 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]]
3917 // CHECK7: omp_if.else:
3918 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
3919 // CHECK7: omp.inner.for.cond13:
3920 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3921 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3922 // CHECK7-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
3923 // CHECK7-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
3924 // CHECK7: omp.inner.for.body15:
3925 // CHECK7-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
3926 // CHECK7-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
3927 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3928 // CHECK7-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
3929 // CHECK7-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
3930 // CHECK7-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
3931 // CHECK7-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
3932 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
3933 // CHECK7: omp.body.continue20:
3934 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
3935 // CHECK7: omp.inner.for.inc21:
3936 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3937 // CHECK7-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
3938 // CHECK7-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
3939 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]]
3940 // CHECK7: omp.inner.for.end23:
3941 // CHECK7-NEXT: br label [[OMP_IF_END]]
3942 // CHECK7: omp_if.end:
3943 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3944 // CHECK7: omp.loop.exit:
3945 // CHECK7-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3946 // CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
3947 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
3948 // CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3949 // CHECK7-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
3950 // CHECK7-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3951 // CHECK7: .omp.final.then:
3952 // CHECK7-NEXT: [[TMP29:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
3953 // CHECK7-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32
3954 // CHECK7-NEXT: [[TMP30:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
3955 // CHECK7-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32
3956 // CHECK7-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
3957 // CHECK7-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
3958 // CHECK7-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
3959 // CHECK7-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
3960 // CHECK7-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
3961 // CHECK7-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
3962 // CHECK7-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
3963 // CHECK7-NEXT: store i8 [[CONV32]], i8* [[TMP0]], align 1
3964 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]
3965 // CHECK7: .omp.final.done:
3966 // CHECK7-NEXT: br label [[OMP_PRECOND_END]]
3967 // CHECK7: omp.precond.end:
3968 // CHECK7-NEXT: ret void
3969 //
3970 //
3971 // CHECK7-LABEL: define {{[^@]+}}@_Z4fintv
3972 // CHECK7-SAME: () #[[ATTR0]] {
3973 // CHECK7-NEXT: entry:
3974 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v()
3975 // CHECK7-NEXT: ret i32 [[CALL]]
3976 //
3977 //
3978 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
3979 // CHECK7-SAME: () #[[ATTR0]] comdat {
3980 // CHECK7-NEXT: entry:
3981 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2
3982 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
3983 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
3984 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
3985 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
3986 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
3987 // CHECK7-NEXT: store i16 0, i16* [[AA]], align 2
3988 // CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2
3989 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3990 // CHECK7-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2
3991 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3992 // CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3993 // CHECK7-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
3994 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4
3995 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3996 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
3997 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
3998 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3999 // CHECK7-NEXT: store i8* null, i8** [[TMP6]], align 4
4000 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4001 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4002 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
4003 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
4004 // CHECK7-NEXT: store i32 1, i32* [[TMP9]], align 4
4005 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
4006 // CHECK7-NEXT: store i32 1, i32* [[TMP10]], align 4
4007 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
4008 // CHECK7-NEXT: store i8** [[TMP7]], i8*** [[TMP11]], align 4
4009 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
4010 // CHECK7-NEXT: store i8** [[TMP8]], i8*** [[TMP12]], align 4
4011 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
4012 // CHECK7-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64** [[TMP13]], align 4
4013 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
4014 // CHECK7-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i64** [[TMP14]], align 4
4015 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
4016 // CHECK7-NEXT: store i8** null, i8*** [[TMP15]], align 4
4017 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
4018 // CHECK7-NEXT: store i8** null, i8*** [[TMP16]], align 4
4019 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
4020 // CHECK7-NEXT: store i64 100, i64* [[TMP17]], align 8
4021 // CHECK7-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
4022 // CHECK7-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
4023 // CHECK7-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4024 // CHECK7: omp_offload.failed:
4025 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i32 [[TMP1]]) #[[ATTR3]]
4026 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
4027 // CHECK7: omp_offload.cont:
4028 // CHECK7-NEXT: ret i32 0
4029 //
4030 //
4031 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
4032 // CHECK7-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] {
4033 // CHECK7-NEXT: entry:
4034 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4035 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
4036 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4037 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]])
4038 // CHECK7-NEXT: ret void
4039 //
4040 //
4041 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10
4042 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] {
4043 // CHECK7-NEXT: entry:
4044 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4045 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4046 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4
4047 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4048 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
4049 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4050 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4051 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4052 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4053 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
4054 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4055 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4056 // CHECK7-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
4057 // CHECK7-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
4058 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4059 // CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
4060 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4061 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4062 // CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
4063 // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
4064 // CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4065 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
4066 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
4067 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
4068 // CHECK7: omp.dispatch.cond:
4069 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4070 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
4071 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4072 // CHECK7: cond.true:
4073 // CHECK7-NEXT: br label [[COND_END:%.*]]
4074 // CHECK7: cond.false:
4075 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4076 // CHECK7-NEXT: br label [[COND_END]]
4077 // CHECK7: cond.end:
4078 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
4079 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4080 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4081 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
4082 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4083 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4084 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
4085 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
4086 // CHECK7: omp.dispatch.body:
4087 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4088 // CHECK7: omp.inner.for.cond:
4089 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
4090 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
4091 // CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
4092 // CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4093 // CHECK7: omp.inner.for.body:
4094 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
4095 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
4096 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4097 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
4098 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4099 // CHECK7: omp.body.continue:
4100 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4101 // CHECK7: omp.inner.for.inc:
4102 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
4103 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
4104 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
4105 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
4106 // CHECK7: omp.inner.for.end:
4107 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
4108 // CHECK7: omp.dispatch.inc:
4109 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4110 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4111 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
4112 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
4113 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4114 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4115 // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
4116 // CHECK7-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
4117 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]]
4118 // CHECK7: omp.dispatch.end:
4119 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
4120 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4121 // CHECK7-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
4122 // CHECK7-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4123 // CHECK7: .omp.final.then:
4124 // CHECK7-NEXT: store i32 100, i32* [[I]], align 4
4125 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]
4126 // CHECK7: .omp.final.done:
4127 // CHECK7-NEXT: ret void
4128 //
4129 //
4130 // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
4131 // CHECK7-SAME: () #[[ATTR4:[0-9]+]] {
4132 // CHECK7-NEXT: entry:
4133 // CHECK7-NEXT: call void @__tgt_register_requires(i64 1)
4134 // CHECK7-NEXT: ret void
4135 //
4136 //
4137 // CHECK9-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
4138 // CHECK9-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
4139 // CHECK9-NEXT: entry:
4140 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
4141 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
4142 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
4143 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
4144 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
4145 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4146 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4147 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4148 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
4149 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
4150 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
4151 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
4152 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
4153 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4154 // CHECK9-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
4155 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4156 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4157 // CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 8
4158 // CHECK9-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i64 16) ]
4159 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4160 // CHECK9: omp.inner.for.cond:
4161 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
4162 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
4163 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
4164 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4165 // CHECK9: omp.inner.for.body:
4166 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
4167 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
4168 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
4169 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
4170 // CHECK9-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !2
4171 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
4172 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
4173 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]]
4174 // CHECK9-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !2
4175 // CHECK9-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !2
4176 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
4177 // CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64
4178 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM1]]
4179 // CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !2
4180 // CHECK9-NEXT: [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]]
4181 // CHECK9-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !2
4182 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
4183 // CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64
4184 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM4]]
4185 // CHECK9-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !2
4186 // CHECK9-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]]
4187 // CHECK9-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !2
4188 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
4189 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64
4190 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM7]]
4191 // CHECK9-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !2
4192 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4193 // CHECK9: omp.body.continue:
4194 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4195 // CHECK9: omp.inner.for.inc:
4196 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
4197 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1
4198 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
4199 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
4200 // CHECK9: omp.inner.for.end:
4201 // CHECK9-NEXT: store i32 32000001, i32* [[I]], align 4
4202 // CHECK9-NEXT: ret void
4203 //
4204 //
4205 // CHECK9-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
4206 // CHECK9-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
4207 // CHECK9-NEXT: entry:
4208 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
4209 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
4210 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
4211 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
4212 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
4213 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4214 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4215 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4216 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
4217 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
4218 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
4219 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
4220 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
4221 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4222 // CHECK9-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
4223 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4224 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4225 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4226 // CHECK9: omp.inner.for.cond:
4227 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4228 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4229 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4230 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4231 // CHECK9: omp.inner.for.body:
4232 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4233 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
4234 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
4235 // CHECK9-NEXT: store i32 [[SUB]], i32* [[I]], align 4
4236 // CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8
4237 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
4238 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
4239 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
4240 // CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
4241 // CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8
4242 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
4243 // CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64
4244 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
4245 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4
4246 // CHECK9-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
4247 // CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8
4248 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
4249 // CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
4250 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
4251 // CHECK9-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4
4252 // CHECK9-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
4253 // CHECK9-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8
4254 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
4255 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64
4256 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
4257 // CHECK9-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4
4258 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4259 // CHECK9: omp.body.continue:
4260 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4261 // CHECK9: omp.inner.for.inc:
4262 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4263 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
4264 // CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
4265 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
4266 // CHECK9: omp.inner.for.end:
4267 // CHECK9-NEXT: store i32 32, i32* [[I]], align 4
4268 // CHECK9-NEXT: ret void
4269 //
4270 //
4271 // CHECK9-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
4272 // CHECK9-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
4273 // CHECK9-NEXT: entry:
4274 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
4275 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
4276 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
4277 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
4278 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
4279 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4280 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4281 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4282 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
4283 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
4284 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
4285 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
4286 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
4287 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4288 // CHECK9-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
4289 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4290 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4291 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4292 // CHECK9: omp.inner.for.cond:
4293 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
4294 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
4295 // CHECK9-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
4296 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4297 // CHECK9: omp.inner.for.body:
4298 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
4299 // CHECK9-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
4300 // CHECK9-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
4301 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
4302 // CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !9
4303 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
4304 // CHECK9-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64
4305 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
4306 // CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9
4307 // CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !9
4308 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
4309 // CHECK9-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64
4310 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
4311 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !9
4312 // CHECK9-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
4313 // CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !9
4314 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
4315 // CHECK9-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64
4316 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
4317 // CHECK9-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !9
4318 // CHECK9-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
4319 // CHECK9-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !9
4320 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
4321 // CHECK9-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64
4322 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
4323 // CHECK9-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !9
4324 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4325 // CHECK9: omp.body.continue:
4326 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4327 // CHECK9: omp.inner.for.inc:
4328 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
4329 // CHECK9-NEXT: [[ADD9:%.*]] = add i32 [[TMP15]], 1
4330 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
4331 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
4332 // CHECK9: omp.inner.for.end:
4333 // CHECK9-NEXT: store i32 -2147483522, i32* [[I]], align 4
4334 // CHECK9-NEXT: ret void
4335 //
4336 //
4337 // CHECK9-LABEL: define {{[^@]+}}@_Z12test_precondv
4338 // CHECK9-SAME: () #[[ATTR0]] {
4339 // CHECK9-NEXT: entry:
4340 // CHECK9-NEXT: [[A:%.*]] = alloca i8, align 1
4341 // CHECK9-NEXT: [[I:%.*]] = alloca i8, align 1
4342 // CHECK9-NEXT: [[TMP:%.*]] = alloca i8, align 1
4343 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
4344 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
4345 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4346 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4347 // CHECK9-NEXT: [[I4:%.*]] = alloca i8, align 1
4348 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4349 // CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
4350 // CHECK9-NEXT: [[I6:%.*]] = alloca i8, align 1
4351 // CHECK9-NEXT: [[I7:%.*]] = alloca i8, align 1
4352 // CHECK9-NEXT: store i8 0, i8* [[A]], align 1
4353 // CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
4354 // CHECK9-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
4355 // CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4356 // CHECK9-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
4357 // CHECK9-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
4358 // CHECK9-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
4359 // CHECK9-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
4360 // CHECK9-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
4361 // CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
4362 // CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
4363 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4364 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
4365 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
4366 // CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4367 // CHECK9-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
4368 // CHECK9-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4369 // CHECK9-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
4370 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
4371 // CHECK9-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
4372 // CHECK9: simd.if.then:
4373 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4374 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
4375 // CHECK9-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
4376 // CHECK9-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
4377 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4378 // CHECK9: omp.inner.for.cond:
4379 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
4380 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
4381 // CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
4382 // CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4383 // CHECK9: omp.inner.for.body:
4384 // CHECK9-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !12
4385 // CHECK9-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32
4386 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
4387 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
4388 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
4389 // CHECK9-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
4390 // CHECK9-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !12
4391 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4392 // CHECK9: omp.body.continue:
4393 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4394 // CHECK9: omp.inner.for.inc:
4395 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
4396 // CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1
4397 // CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
4398 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
4399 // CHECK9: omp.inner.for.end:
4400 // CHECK9-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4401 // CHECK9-NEXT: [[CONV13:%.*]] = sext i8 [[TMP12]] to i32
4402 // CHECK9-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4403 // CHECK9-NEXT: [[CONV14:%.*]] = sext i8 [[TMP13]] to i32
4404 // CHECK9-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
4405 // CHECK9-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
4406 // CHECK9-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
4407 // CHECK9-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
4408 // CHECK9-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
4409 // CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
4410 // CHECK9-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
4411 // CHECK9-NEXT: store i8 [[CONV21]], i8* [[I]], align 1
4412 // CHECK9-NEXT: br label [[SIMD_IF_END]]
4413 // CHECK9: simd.if.end:
4414 // CHECK9-NEXT: ret void
4415 //
4416 //
4417 // CHECK9-LABEL: define {{[^@]+}}@_Z4fintv
4418 // CHECK9-SAME: () #[[ATTR0]] {
4419 // CHECK9-NEXT: entry:
4420 // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v()
4421 // CHECK9-NEXT: ret i32 [[CALL]]
4422 //
4423 //
4424 // CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
4425 // CHECK9-SAME: () #[[ATTR0]] comdat {
4426 // CHECK9-NEXT: entry:
4427 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2
4428 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
4429 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4430 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4431 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4432 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
4433 // CHECK9-NEXT: store i16 0, i16* [[AA]], align 2
4434 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4435 // CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
4436 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4437 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4438 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4439 // CHECK9: omp.inner.for.cond:
4440 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
4441 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15
4442 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4443 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4444 // CHECK9: omp.inner.for.body:
4445 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
4446 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
4447 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4448 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15
4449 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4450 // CHECK9: omp.body.continue:
4451 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4452 // CHECK9: omp.inner.for.inc:
4453 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
4454 // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
4455 // CHECK9-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
4456 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
4457 // CHECK9: omp.inner.for.end:
4458 // CHECK9-NEXT: store i32 100, i32* [[I]], align 4
4459 // CHECK9-NEXT: ret i32 0
4460 //
4461 //
4462 // CHECK11-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
4463 // CHECK11-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
4464 // CHECK11-NEXT: entry:
4465 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
4466 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
4467 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
4468 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
4469 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
4470 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4471 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4472 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4473 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
4474 // CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
4475 // CHECK11-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
4476 // CHECK11-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
4477 // CHECK11-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
4478 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4479 // CHECK11-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
4480 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4481 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4482 // CHECK11-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 4
4483 // CHECK11-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i32 16) ]
4484 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4485 // CHECK11: omp.inner.for.cond:
4486 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
4487 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
4488 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
4489 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4490 // CHECK11: omp.inner.for.body:
4491 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
4492 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
4493 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
4494 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
4495 // CHECK11-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !3
4496 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
4497 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i32 [[TMP6]]
4498 // CHECK11-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !3
4499 // CHECK11-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !3
4500 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
4501 // CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP8]], i32 [[TMP9]]
4502 // CHECK11-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !3
4503 // CHECK11-NEXT: [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]]
4504 // CHECK11-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !3
4505 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
4506 // CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP11]], i32 [[TMP12]]
4507 // CHECK11-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !3
4508 // CHECK11-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]]
4509 // CHECK11-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !3
4510 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
4511 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
4512 // CHECK11-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !3
4513 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4514 // CHECK11: omp.body.continue:
4515 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4516 // CHECK11: omp.inner.for.inc:
4517 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
4518 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
4519 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
4520 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
4521 // CHECK11: omp.inner.for.end:
4522 // CHECK11-NEXT: store i32 32000001, i32* [[I]], align 4
4523 // CHECK11-NEXT: ret void
4524 //
4525 //
4526 // CHECK11-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
4527 // CHECK11-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
4528 // CHECK11-NEXT: entry:
4529 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
4530 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
4531 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
4532 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
4533 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
4534 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4535 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4536 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4537 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
4538 // CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
4539 // CHECK11-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
4540 // CHECK11-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
4541 // CHECK11-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
4542 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4543 // CHECK11-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
4544 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4545 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4546 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4547 // CHECK11: omp.inner.for.cond:
4548 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4549 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4550 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4551 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4552 // CHECK11: omp.inner.for.body:
4553 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4554 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
4555 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
4556 // CHECK11-NEXT: store i32 [[SUB]], i32* [[I]], align 4
4557 // CHECK11-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4
4558 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
4559 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
4560 // CHECK11-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
4561 // CHECK11-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4
4562 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
4563 // CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
4564 // CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4
4565 // CHECK11-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
4566 // CHECK11-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4
4567 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
4568 // CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
4569 // CHECK11-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4
4570 // CHECK11-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
4571 // CHECK11-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4
4572 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
4573 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
4574 // CHECK11-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4
4575 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4576 // CHECK11: omp.body.continue:
4577 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4578 // CHECK11: omp.inner.for.inc:
4579 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4580 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
4581 // CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
4582 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
4583 // CHECK11: omp.inner.for.end:
4584 // CHECK11-NEXT: store i32 32, i32* [[I]], align 4
4585 // CHECK11-NEXT: ret void
4586 //
4587 //
4588 // CHECK11-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
4589 // CHECK11-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
4590 // CHECK11-NEXT: entry:
4591 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
4592 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
4593 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
4594 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
4595 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
4596 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4597 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4598 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4599 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
4600 // CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
4601 // CHECK11-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
4602 // CHECK11-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
4603 // CHECK11-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
4604 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4605 // CHECK11-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
4606 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4607 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4608 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4609 // CHECK11: omp.inner.for.cond:
4610 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
4611 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
4612 // CHECK11-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
4613 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4614 // CHECK11: omp.inner.for.body:
4615 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
4616 // CHECK11-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
4617 // CHECK11-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
4618 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
4619 // CHECK11-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !10
4620 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
4621 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
4622 // CHECK11-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10
4623 // CHECK11-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !10
4624 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
4625 // CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
4626 // CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !10
4627 // CHECK11-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
4628 // CHECK11-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !10
4629 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
4630 // CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
4631 // CHECK11-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !10
4632 // CHECK11-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
4633 // CHECK11-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !10
4634 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
4635 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
4636 // CHECK11-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !10
4637 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4638 // CHECK11: omp.body.continue:
4639 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4640 // CHECK11: omp.inner.for.inc:
4641 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
4642 // CHECK11-NEXT: [[ADD6:%.*]] = add i32 [[TMP15]], 1
4643 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
4644 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
4645 // CHECK11: omp.inner.for.end:
4646 // CHECK11-NEXT: store i32 -2147483522, i32* [[I]], align 4
4647 // CHECK11-NEXT: ret void
4648 //
4649 //
4650 // CHECK11-LABEL: define {{[^@]+}}@_Z12test_precondv
4651 // CHECK11-SAME: () #[[ATTR0]] {
4652 // CHECK11-NEXT: entry:
4653 // CHECK11-NEXT: [[A:%.*]] = alloca i8, align 1
4654 // CHECK11-NEXT: [[I:%.*]] = alloca i8, align 1
4655 // CHECK11-NEXT: [[TMP:%.*]] = alloca i8, align 1
4656 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
4657 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
4658 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4659 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4660 // CHECK11-NEXT: [[I4:%.*]] = alloca i8, align 1
4661 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4662 // CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
4663 // CHECK11-NEXT: [[I6:%.*]] = alloca i8, align 1
4664 // CHECK11-NEXT: [[I7:%.*]] = alloca i8, align 1
4665 // CHECK11-NEXT: store i8 0, i8* [[A]], align 1
4666 // CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
4667 // CHECK11-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
4668 // CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4669 // CHECK11-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
4670 // CHECK11-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
4671 // CHECK11-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
4672 // CHECK11-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
4673 // CHECK11-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
4674 // CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
4675 // CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
4676 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4677 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
4678 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
4679 // CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4680 // CHECK11-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
4681 // CHECK11-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4682 // CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
4683 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
4684 // CHECK11-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
4685 // CHECK11: simd.if.then:
4686 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4687 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
4688 // CHECK11-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
4689 // CHECK11-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
4690 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4691 // CHECK11: omp.inner.for.cond:
4692 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
4693 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
4694 // CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
4695 // CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4696 // CHECK11: omp.inner.for.body:
4697 // CHECK11-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !13
4698 // CHECK11-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32
4699 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
4700 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
4701 // CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
4702 // CHECK11-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
4703 // CHECK11-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !13
4704 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4705 // CHECK11: omp.body.continue:
4706 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4707 // CHECK11: omp.inner.for.inc:
4708 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
4709 // CHECK11-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1
4710 // CHECK11-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
4711 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
4712 // CHECK11: omp.inner.for.end:
4713 // CHECK11-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4714 // CHECK11-NEXT: [[CONV13:%.*]] = sext i8 [[TMP12]] to i32
4715 // CHECK11-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4716 // CHECK11-NEXT: [[CONV14:%.*]] = sext i8 [[TMP13]] to i32
4717 // CHECK11-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
4718 // CHECK11-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
4719 // CHECK11-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
4720 // CHECK11-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
4721 // CHECK11-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
4722 // CHECK11-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
4723 // CHECK11-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
4724 // CHECK11-NEXT: store i8 [[CONV21]], i8* [[I]], align 1
4725 // CHECK11-NEXT: br label [[SIMD_IF_END]]
4726 // CHECK11: simd.if.end:
4727 // CHECK11-NEXT: ret void
4728 //
4729 //
4730 // CHECK11-LABEL: define {{[^@]+}}@_Z4fintv
4731 // CHECK11-SAME: () #[[ATTR0]] {
4732 // CHECK11-NEXT: entry:
4733 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v()
4734 // CHECK11-NEXT: ret i32 [[CALL]]
4735 //
4736 //
4737 // CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
4738 // CHECK11-SAME: () #[[ATTR0]] comdat {
4739 // CHECK11-NEXT: entry:
4740 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2
4741 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
4742 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4743 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4744 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4745 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
4746 // CHECK11-NEXT: store i16 0, i16* [[AA]], align 2
4747 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4748 // CHECK11-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
4749 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4750 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4751 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4752 // CHECK11: omp.inner.for.cond:
4753 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
4754 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !16
4755 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4756 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4757 // CHECK11: omp.inner.for.body:
4758 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
4759 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
4760 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4761 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16
4762 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4763 // CHECK11: omp.body.continue:
4764 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4765 // CHECK11: omp.inner.for.inc:
4766 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
4767 // CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
4768 // CHECK11-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
4769 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
4770 // CHECK11: omp.inner.for.end:
4771 // CHECK11-NEXT: store i32 100, i32* [[I]], align 4
4772 // CHECK11-NEXT: ret i32 0
4773 //
4774 //
4775 // CHECK13-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
4776 // CHECK13-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
4777 // CHECK13-NEXT: entry:
4778 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
4779 // CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
4780 // CHECK13-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
4781 // CHECK13-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
4782 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4
4783 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4784 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4785 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4786 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
4787 // CHECK13-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
4788 // CHECK13-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
4789 // CHECK13-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
4790 // CHECK13-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
4791 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4792 // CHECK13-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
4793 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4794 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4795 // CHECK13-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 8
4796 // CHECK13-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i64 16) ]
4797 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4798 // CHECK13: omp.inner.for.cond:
4799 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
4800 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
4801 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
4802 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4803 // CHECK13: omp.inner.for.body:
4804 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
4805 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
4806 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
4807 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
4808 // CHECK13-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !2
4809 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
4810 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
4811 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]]
4812 // CHECK13-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !2
4813 // CHECK13-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !2
4814 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
4815 // CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64
4816 // CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM1]]
4817 // CHECK13-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !2
4818 // CHECK13-NEXT: [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]]
4819 // CHECK13-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !2
4820 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
4821 // CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64
4822 // CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM4]]
4823 // CHECK13-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !2
4824 // CHECK13-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]]
4825 // CHECK13-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !2
4826 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
4827 // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64
4828 // CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM7]]
4829 // CHECK13-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !2
4830 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4831 // CHECK13: omp.body.continue:
4832 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4833 // CHECK13: omp.inner.for.inc:
4834 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
4835 // CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1
4836 // CHECK13-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
4837 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
4838 // CHECK13: omp.inner.for.end:
4839 // CHECK13-NEXT: store i32 32000001, i32* [[I]], align 4
4840 // CHECK13-NEXT: ret void
4841 //
4842 //
4843 // CHECK13-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
4844 // CHECK13-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
4845 // CHECK13-NEXT: entry:
4846 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
4847 // CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
4848 // CHECK13-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
4849 // CHECK13-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
4850 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4
4851 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4852 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4853 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4854 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
4855 // CHECK13-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
4856 // CHECK13-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
4857 // CHECK13-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
4858 // CHECK13-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
4859 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4860 // CHECK13-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
4861 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4862 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4863 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4864 // CHECK13: omp.inner.for.cond:
4865 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4866 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4867 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4868 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4869 // CHECK13: omp.inner.for.body:
4870 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4871 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
4872 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
4873 // CHECK13-NEXT: store i32 [[SUB]], i32* [[I]], align 4
4874 // CHECK13-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !nontemporal !7
4875 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
4876 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
4877 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
4878 // CHECK13-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
4879 // CHECK13-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8
4880 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
4881 // CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64
4882 // CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
4883 // CHECK13-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4
4884 // CHECK13-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
4885 // CHECK13-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8
4886 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
4887 // CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
4888 // CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
4889 // CHECK13-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4
4890 // CHECK13-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
4891 // CHECK13-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !nontemporal !7
4892 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
4893 // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64
4894 // CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
4895 // CHECK13-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4
4896 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4897 // CHECK13: omp.body.continue:
4898 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4899 // CHECK13: omp.inner.for.inc:
4900 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4901 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
4902 // CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
4903 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
4904 // CHECK13: omp.inner.for.end:
4905 // CHECK13-NEXT: store i32 32, i32* [[I]], align 4
4906 // CHECK13-NEXT: ret void
4907 //
4908 //
4909 // CHECK13-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
4910 // CHECK13-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
4911 // CHECK13-NEXT: entry:
4912 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
4913 // CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
4914 // CHECK13-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
4915 // CHECK13-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
4916 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4
4917 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4918 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4919 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4920 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
4921 // CHECK13-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
4922 // CHECK13-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
4923 // CHECK13-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
4924 // CHECK13-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
4925 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4926 // CHECK13-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
4927 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4928 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4929 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4930 // CHECK13: omp.inner.for.cond:
4931 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
4932 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
4933 // CHECK13-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
4934 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4935 // CHECK13: omp.inner.for.body:
4936 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
4937 // CHECK13-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
4938 // CHECK13-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
4939 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
4940 // CHECK13-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !10
4941 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
4942 // CHECK13-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64
4943 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
4944 // CHECK13-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10
4945 // CHECK13-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !10
4946 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
4947 // CHECK13-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64
4948 // CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
4949 // CHECK13-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !10
4950 // CHECK13-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
4951 // CHECK13-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !10
4952 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
4953 // CHECK13-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64
4954 // CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
4955 // CHECK13-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !10
4956 // CHECK13-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
4957 // CHECK13-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !10
4958 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
4959 // CHECK13-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64
4960 // CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
4961 // CHECK13-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !10
4962 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4963 // CHECK13: omp.body.continue:
4964 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4965 // CHECK13: omp.inner.for.inc:
4966 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
4967 // CHECK13-NEXT: [[ADD9:%.*]] = add i32 [[TMP15]], 1
4968 // CHECK13-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
4969 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
4970 // CHECK13: omp.inner.for.end:
4971 // CHECK13-NEXT: store i32 -2147483522, i32* [[I]], align 4
4972 // CHECK13-NEXT: ret void
4973 //
4974 //
4975 // CHECK13-LABEL: define {{[^@]+}}@_Z12test_precondv
4976 // CHECK13-SAME: () #[[ATTR0]] {
4977 // CHECK13-NEXT: entry:
4978 // CHECK13-NEXT: [[A:%.*]] = alloca i8, align 1
4979 // CHECK13-NEXT: [[I:%.*]] = alloca i8, align 1
4980 // CHECK13-NEXT: [[TMP:%.*]] = alloca i8, align 1
4981 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
4982 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
4983 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4984 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4985 // CHECK13-NEXT: [[I4:%.*]] = alloca i8, align 1
4986 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4987 // CHECK13-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
4988 // CHECK13-NEXT: [[I6:%.*]] = alloca i8, align 1
4989 // CHECK13-NEXT: [[I7:%.*]] = alloca i8, align 1
4990 // CHECK13-NEXT: store i8 0, i8* [[A]], align 1
4991 // CHECK13-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
4992 // CHECK13-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
4993 // CHECK13-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4994 // CHECK13-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
4995 // CHECK13-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
4996 // CHECK13-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
4997 // CHECK13-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
4998 // CHECK13-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
4999 // CHECK13-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
5000 // CHECK13-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
5001 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5002 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
5003 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
5004 // CHECK13-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5005 // CHECK13-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
5006 // CHECK13-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5007 // CHECK13-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
5008 // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
5009 // CHECK13-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
5010 // CHECK13: simd.if.then:
5011 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5012 // CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
5013 // CHECK13-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
5014 // CHECK13-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
5015 // CHECK13-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1
5016 // CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0
5017 // CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5018 // CHECK13: omp_if.then:
5019 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5020 // CHECK13: omp.inner.for.cond:
5021 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
5022 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
5023 // CHECK13-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
5024 // CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5025 // CHECK13: omp.inner.for.body:
5026 // CHECK13-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !13
5027 // CHECK13-NEXT: [[CONV9:%.*]] = sext i8 [[TMP10]] to i32
5028 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
5029 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
5030 // CHECK13-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
5031 // CHECK13-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
5032 // CHECK13-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !7, !llvm.access.group !13
5033 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5034 // CHECK13: omp.body.continue:
5035 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5036 // CHECK13: omp.inner.for.inc:
5037 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
5038 // CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1
5039 // CHECK13-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
5040 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
5041 // CHECK13: omp.inner.for.end:
5042 // CHECK13-NEXT: br label [[OMP_IF_END:%.*]]
5043 // CHECK13: omp_if.else:
5044 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
5045 // CHECK13: omp.inner.for.cond13:
5046 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5047 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5048 // CHECK13-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
5049 // CHECK13-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
5050 // CHECK13: omp.inner.for.body15:
5051 // CHECK13-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5052 // CHECK13-NEXT: [[CONV16:%.*]] = sext i8 [[TMP15]] to i32
5053 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5054 // CHECK13-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1
5055 // CHECK13-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
5056 // CHECK13-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
5057 // CHECK13-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
5058 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
5059 // CHECK13: omp.body.continue20:
5060 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
5061 // CHECK13: omp.inner.for.inc21:
5062 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5063 // CHECK13-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1
5064 // CHECK13-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
5065 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP16:![0-9]+]]
5066 // CHECK13: omp.inner.for.end23:
5067 // CHECK13-NEXT: br label [[OMP_IF_END]]
5068 // CHECK13: omp_if.end:
5069 // CHECK13-NEXT: [[TMP18:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5070 // CHECK13-NEXT: [[CONV24:%.*]] = sext i8 [[TMP18]] to i32
5071 // CHECK13-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5072 // CHECK13-NEXT: [[CONV25:%.*]] = sext i8 [[TMP19]] to i32
5073 // CHECK13-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
5074 // CHECK13-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
5075 // CHECK13-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
5076 // CHECK13-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
5077 // CHECK13-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
5078 // CHECK13-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
5079 // CHECK13-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
5080 // CHECK13-NEXT: store i8 [[CONV32]], i8* [[I]], align 1
5081 // CHECK13-NEXT: br label [[SIMD_IF_END]]
5082 // CHECK13: simd.if.end:
5083 // CHECK13-NEXT: ret void
5084 //
5085 //
5086 // CHECK13-LABEL: define {{[^@]+}}@_Z4fintv
5087 // CHECK13-SAME: () #[[ATTR0]] {
5088 // CHECK13-NEXT: entry:
5089 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v()
5090 // CHECK13-NEXT: ret i32 [[CALL]]
5091 //
5092 //
5093 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
5094 // CHECK13-SAME: () #[[ATTR0]] comdat {
5095 // CHECK13-NEXT: entry:
5096 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2
5097 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4
5098 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5099 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5100 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5101 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
5102 // CHECK13-NEXT: store i16 0, i16* [[AA]], align 2
5103 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5104 // CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
5105 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5106 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
5107 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5108 // CHECK13: omp.inner.for.cond:
5109 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
5110 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
5111 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
5112 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5113 // CHECK13: omp.inner.for.body:
5114 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
5115 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
5116 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5117 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
5118 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5119 // CHECK13: omp.body.continue:
5120 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5121 // CHECK13: omp.inner.for.inc:
5122 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
5123 // CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
5124 // CHECK13-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
5125 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
5126 // CHECK13: omp.inner.for.end:
5127 // CHECK13-NEXT: store i32 100, i32* [[I]], align 4
5128 // CHECK13-NEXT: ret i32 0
5129 //
5130 //
5131 // CHECK15-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
5132 // CHECK15-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
5133 // CHECK15-NEXT: entry:
5134 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
5135 // CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
5136 // CHECK15-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
5137 // CHECK15-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
5138 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4
5139 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5140 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5141 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5142 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
5143 // CHECK15-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
5144 // CHECK15-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
5145 // CHECK15-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
5146 // CHECK15-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
5147 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5148 // CHECK15-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
5149 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5150 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
5151 // CHECK15-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 4
5152 // CHECK15-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i32 16) ]
5153 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5154 // CHECK15: omp.inner.for.cond:
5155 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
5156 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
5157 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
5158 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5159 // CHECK15: omp.inner.for.body:
5160 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
5161 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
5162 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
5163 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
5164 // CHECK15-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !3
5165 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
5166 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i32 [[TMP6]]
5167 // CHECK15-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !3
5168 // CHECK15-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !3
5169 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
5170 // CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP8]], i32 [[TMP9]]
5171 // CHECK15-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !3
5172 // CHECK15-NEXT: [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]]
5173 // CHECK15-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !3
5174 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
5175 // CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP11]], i32 [[TMP12]]
5176 // CHECK15-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !3
5177 // CHECK15-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]]
5178 // CHECK15-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !3
5179 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
5180 // CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
5181 // CHECK15-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !3
5182 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5183 // CHECK15: omp.body.continue:
5184 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5185 // CHECK15: omp.inner.for.inc:
5186 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
5187 // CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
5188 // CHECK15-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
5189 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
5190 // CHECK15: omp.inner.for.end:
5191 // CHECK15-NEXT: store i32 32000001, i32* [[I]], align 4
5192 // CHECK15-NEXT: ret void
5193 //
5194 //
5195 // CHECK15-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
5196 // CHECK15-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
5197 // CHECK15-NEXT: entry:
5198 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
5199 // CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
5200 // CHECK15-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
5201 // CHECK15-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
5202 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4
5203 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5204 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5205 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5206 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
5207 // CHECK15-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
5208 // CHECK15-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
5209 // CHECK15-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
5210 // CHECK15-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
5211 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5212 // CHECK15-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
5213 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5214 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
5215 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5216 // CHECK15: omp.inner.for.cond:
5217 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5218 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5219 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
5220 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5221 // CHECK15: omp.inner.for.body:
5222 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5223 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
5224 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
5225 // CHECK15-NEXT: store i32 [[SUB]], i32* [[I]], align 4
5226 // CHECK15-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !nontemporal !8
5227 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
5228 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
5229 // CHECK15-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
5230 // CHECK15-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4
5231 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
5232 // CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
5233 // CHECK15-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4
5234 // CHECK15-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
5235 // CHECK15-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4
5236 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
5237 // CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
5238 // CHECK15-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4
5239 // CHECK15-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
5240 // CHECK15-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !nontemporal !8
5241 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
5242 // CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
5243 // CHECK15-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4
5244 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5245 // CHECK15: omp.body.continue:
5246 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5247 // CHECK15: omp.inner.for.inc:
5248 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5249 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
5250 // CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
5251 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
5252 // CHECK15: omp.inner.for.end:
5253 // CHECK15-NEXT: store i32 32, i32* [[I]], align 4
5254 // CHECK15-NEXT: ret void
5255 //
5256 //
5257 // CHECK15-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
5258 // CHECK15-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
5259 // CHECK15-NEXT: entry:
5260 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
5261 // CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
5262 // CHECK15-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
5263 // CHECK15-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
5264 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4
5265 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5266 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5267 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5268 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
5269 // CHECK15-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
5270 // CHECK15-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
5271 // CHECK15-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
5272 // CHECK15-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
5273 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5274 // CHECK15-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
5275 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5276 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
5277 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5278 // CHECK15: omp.inner.for.cond:
5279 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
5280 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
5281 // CHECK15-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
5282 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5283 // CHECK15: omp.inner.for.body:
5284 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
5285 // CHECK15-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
5286 // CHECK15-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
5287 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
5288 // CHECK15-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !11
5289 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
5290 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
5291 // CHECK15-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11
5292 // CHECK15-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !11
5293 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
5294 // CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
5295 // CHECK15-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !11
5296 // CHECK15-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
5297 // CHECK15-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !11
5298 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
5299 // CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
5300 // CHECK15-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !11
5301 // CHECK15-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
5302 // CHECK15-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !11
5303 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
5304 // CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
5305 // CHECK15-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !11
5306 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5307 // CHECK15: omp.body.continue:
5308 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5309 // CHECK15: omp.inner.for.inc:
5310 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
5311 // CHECK15-NEXT: [[ADD6:%.*]] = add i32 [[TMP15]], 1
5312 // CHECK15-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
5313 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
5314 // CHECK15: omp.inner.for.end:
5315 // CHECK15-NEXT: store i32 -2147483522, i32* [[I]], align 4
5316 // CHECK15-NEXT: ret void
5317 //
5318 //
5319 // CHECK15-LABEL: define {{[^@]+}}@_Z12test_precondv
5320 // CHECK15-SAME: () #[[ATTR0]] {
5321 // CHECK15-NEXT: entry:
5322 // CHECK15-NEXT: [[A:%.*]] = alloca i8, align 1
5323 // CHECK15-NEXT: [[I:%.*]] = alloca i8, align 1
5324 // CHECK15-NEXT: [[TMP:%.*]] = alloca i8, align 1
5325 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
5326 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
5327 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5328 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5329 // CHECK15-NEXT: [[I4:%.*]] = alloca i8, align 1
5330 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5331 // CHECK15-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
5332 // CHECK15-NEXT: [[I6:%.*]] = alloca i8, align 1
5333 // CHECK15-NEXT: [[I7:%.*]] = alloca i8, align 1
5334 // CHECK15-NEXT: store i8 0, i8* [[A]], align 1
5335 // CHECK15-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
5336 // CHECK15-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
5337 // CHECK15-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5338 // CHECK15-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
5339 // CHECK15-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
5340 // CHECK15-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
5341 // CHECK15-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
5342 // CHECK15-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
5343 // CHECK15-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
5344 // CHECK15-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
5345 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5346 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
5347 // CHECK15-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
5348 // CHECK15-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5349 // CHECK15-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
5350 // CHECK15-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5351 // CHECK15-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
5352 // CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
5353 // CHECK15-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
5354 // CHECK15: simd.if.then:
5355 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5356 // CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
5357 // CHECK15-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
5358 // CHECK15-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
5359 // CHECK15-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1
5360 // CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0
5361 // CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5362 // CHECK15: omp_if.then:
5363 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5364 // CHECK15: omp.inner.for.cond:
5365 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
5366 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14
5367 // CHECK15-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
5368 // CHECK15-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5369 // CHECK15: omp.inner.for.body:
5370 // CHECK15-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !14
5371 // CHECK15-NEXT: [[CONV9:%.*]] = sext i8 [[TMP10]] to i32
5372 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
5373 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
5374 // CHECK15-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
5375 // CHECK15-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
5376 // CHECK15-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !8, !llvm.access.group !14
5377 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5378 // CHECK15: omp.body.continue:
5379 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5380 // CHECK15: omp.inner.for.inc:
5381 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
5382 // CHECK15-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1
5383 // CHECK15-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
5384 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
5385 // CHECK15: omp.inner.for.end:
5386 // CHECK15-NEXT: br label [[OMP_IF_END:%.*]]
5387 // CHECK15: omp_if.else:
5388 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
5389 // CHECK15: omp.inner.for.cond13:
5390 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5391 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5392 // CHECK15-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
5393 // CHECK15-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
5394 // CHECK15: omp.inner.for.body15:
5395 // CHECK15-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5396 // CHECK15-NEXT: [[CONV16:%.*]] = sext i8 [[TMP15]] to i32
5397 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5398 // CHECK15-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1
5399 // CHECK15-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
5400 // CHECK15-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
5401 // CHECK15-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
5402 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
5403 // CHECK15: omp.body.continue20:
5404 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
5405 // CHECK15: omp.inner.for.inc21:
5406 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5407 // CHECK15-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1
5408 // CHECK15-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
5409 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP17:![0-9]+]]
5410 // CHECK15: omp.inner.for.end23:
5411 // CHECK15-NEXT: br label [[OMP_IF_END]]
5412 // CHECK15: omp_if.end:
5413 // CHECK15-NEXT: [[TMP18:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5414 // CHECK15-NEXT: [[CONV24:%.*]] = sext i8 [[TMP18]] to i32
5415 // CHECK15-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5416 // CHECK15-NEXT: [[CONV25:%.*]] = sext i8 [[TMP19]] to i32
5417 // CHECK15-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
5418 // CHECK15-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
5419 // CHECK15-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
5420 // CHECK15-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
5421 // CHECK15-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
5422 // CHECK15-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
5423 // CHECK15-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
5424 // CHECK15-NEXT: store i8 [[CONV32]], i8* [[I]], align 1
5425 // CHECK15-NEXT: br label [[SIMD_IF_END]]
5426 // CHECK15: simd.if.end:
5427 // CHECK15-NEXT: ret void
5428 //
5429 //
5430 // CHECK15-LABEL: define {{[^@]+}}@_Z4fintv
5431 // CHECK15-SAME: () #[[ATTR0]] {
5432 // CHECK15-NEXT: entry:
5433 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v()
5434 // CHECK15-NEXT: ret i32 [[CALL]]
5435 //
5436 //
5437 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
5438 // CHECK15-SAME: () #[[ATTR0]] comdat {
5439 // CHECK15-NEXT: entry:
5440 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2
5441 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4
5442 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5443 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5444 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5445 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
5446 // CHECK15-NEXT: store i16 0, i16* [[AA]], align 2
5447 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5448 // CHECK15-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
5449 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5450 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
5451 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5452 // CHECK15: omp.inner.for.cond:
5453 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
5454 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
5455 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
5456 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5457 // CHECK15: omp.inner.for.body:
5458 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
5459 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
5460 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5461 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
5462 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5463 // CHECK15: omp.body.continue:
5464 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5465 // CHECK15: omp.inner.for.inc:
5466 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
5467 // CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
5468 // CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
5469 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
5470 // CHECK15: omp.inner.for.end:
5471 // CHECK15-NEXT: store i32 100, i32* [[I]], align 4
5472 // CHECK15-NEXT: ret i32 0
5473 //
5474 //
5475 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
5476 // CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
5477 // CHECK17-NEXT: entry:
5478 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
5479 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
5480 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
5481 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
5482 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
5483 // CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
5484 // CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
5485 // CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
5486 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
5487 // CHECK17-NEXT: ret void
5488 //
5489 //
5490 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
5491 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
5492 // CHECK17-NEXT: entry:
5493 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5494 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5495 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
5496 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
5497 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
5498 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
5499 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5500 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
5501 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5502 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5503 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5504 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5505 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4
5506 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5507 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5508 // CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
5509 // CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
5510 // CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
5511 // CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
5512 // CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
5513 // CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
5514 // CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
5515 // CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
5516 // CHECK17-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 8
5517 // CHECK17-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i64 16) ]
5518 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5519 // CHECK17-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
5520 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5521 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5522 // CHECK17-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5523 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
5524 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5525 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5526 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
5527 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5528 // CHECK17: cond.true:
5529 // CHECK17-NEXT: br label [[COND_END:%.*]]
5530 // CHECK17: cond.false:
5531 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5532 // CHECK17-NEXT: br label [[COND_END]]
5533 // CHECK17: cond.end:
5534 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
5535 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5536 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5537 // CHECK17-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
5538 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5539 // CHECK17: omp.inner.for.cond:
5540 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
5541 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
5542 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
5543 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5544 // CHECK17: omp.inner.for.body:
5545 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
5546 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
5547 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
5548 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
5549 // CHECK17-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9
5550 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
5551 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
5552 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]]
5553 // CHECK17-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9
5554 // CHECK17-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9
5555 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
5556 // CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
5557 // CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM2]]
5558 // CHECK17-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !9
5559 // CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
5560 // CHECK17-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9
5561 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
5562 // CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
5563 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM5]]
5564 // CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !llvm.access.group !9
5565 // CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
5566 // CHECK17-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9
5567 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
5568 // CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
5569 // CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM8]]
5570 // CHECK17-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !9
5571 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5572 // CHECK17: omp.body.continue:
5573 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5574 // CHECK17: omp.inner.for.inc:
5575 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
5576 // CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
5577 // CHECK17-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
5578 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
5579 // CHECK17: omp.inner.for.end:
5580 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5581 // CHECK17: omp.loop.exit:
5582 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
5583 // CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5584 // CHECK17-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
5585 // CHECK17-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5586 // CHECK17: .omp.final.then:
5587 // CHECK17-NEXT: store i32 32000001, i32* [[I]], align 4
5588 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]
5589 // CHECK17: .omp.final.done:
5590 // CHECK17-NEXT: ret void
5591 //
5592 //
5593 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
5594 // CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
5595 // CHECK17-NEXT: entry:
5596 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
5597 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
5598 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
5599 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
5600 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
5601 // CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
5602 // CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
5603 // CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
5604 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
5605 // CHECK17-NEXT: ret void
5606 //
5607 //
5608 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1
5609 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
5610 // CHECK17-NEXT: entry:
5611 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5612 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5613 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
5614 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
5615 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
5616 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
5617 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5618 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
5619 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5620 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5621 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5622 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5623 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4
5624 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5625 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5626 // CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
5627 // CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
5628 // CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
5629 // CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
5630 // CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
5631 // CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
5632 // CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
5633 // CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
5634 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5635 // CHECK17-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
5636 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5637 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5638 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5639 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
5640 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5641 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5642 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
5643 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5644 // CHECK17: cond.true:
5645 // CHECK17-NEXT: br label [[COND_END:%.*]]
5646 // CHECK17: cond.false:
5647 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5648 // CHECK17-NEXT: br label [[COND_END]]
5649 // CHECK17: cond.end:
5650 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
5651 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5652 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5653 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
5654 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5655 // CHECK17: omp.inner.for.cond:
5656 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5657 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5658 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
5659 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5660 // CHECK17: omp.inner.for.body:
5661 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5662 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
5663 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
5664 // CHECK17-NEXT: store i32 [[SUB]], i32* [[I]], align 4
5665 // CHECK17-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8
5666 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
5667 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
5668 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]]
5669 // CHECK17-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
5670 // CHECK17-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8
5671 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
5672 // CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
5673 // CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]]
5674 // CHECK17-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4
5675 // CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
5676 // CHECK17-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8
5677 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
5678 // CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
5679 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]]
5680 // CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4
5681 // CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
5682 // CHECK17-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8
5683 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
5684 // CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
5685 // CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]]
5686 // CHECK17-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
5687 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5688 // CHECK17: omp.body.continue:
5689 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5690 // CHECK17: omp.inner.for.inc:
5691 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5692 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
5693 // CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
5694 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
5695 // CHECK17: omp.inner.for.end:
5696 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5697 // CHECK17: omp.loop.exit:
5698 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
5699 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5700 // CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
5701 // CHECK17-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5702 // CHECK17: .omp.final.then:
5703 // CHECK17-NEXT: store i32 32, i32* [[I]], align 4
5704 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]
5705 // CHECK17: .omp.final.done:
5706 // CHECK17-NEXT: ret void
5707 //
5708 //
5709 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
5710 // CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
5711 // CHECK17-NEXT: entry:
5712 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
5713 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
5714 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
5715 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
5716 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
5717 // CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
5718 // CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
5719 // CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
5720 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
5721 // CHECK17-NEXT: ret void
5722 //
5723 //
5724 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
5725 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
5726 // CHECK17-NEXT: entry:
5727 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5728 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5729 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
5730 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
5731 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
5732 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
5733 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5734 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
5735 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5736 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5737 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5738 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5739 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4
5740 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5741 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5742 // CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
5743 // CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
5744 // CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
5745 // CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
5746 // CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
5747 // CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
5748 // CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
5749 // CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
5750 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5751 // CHECK17-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
5752 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5753 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5754 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5755 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
5756 // CHECK17-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
5757 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
5758 // CHECK17: omp.dispatch.cond:
5759 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5760 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
5761 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5762 // CHECK17: cond.true:
5763 // CHECK17-NEXT: br label [[COND_END:%.*]]
5764 // CHECK17: cond.false:
5765 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5766 // CHECK17-NEXT: br label [[COND_END]]
5767 // CHECK17: cond.end:
5768 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
5769 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5770 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5771 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
5772 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5773 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5774 // CHECK17-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
5775 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
5776 // CHECK17: omp.dispatch.body:
5777 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5778 // CHECK17: omp.inner.for.cond:
5779 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
5780 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
5781 // CHECK17-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
5782 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5783 // CHECK17: omp.inner.for.body:
5784 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
5785 // CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
5786 // CHECK17-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
5787 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
5788 // CHECK17-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !18
5789 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
5790 // CHECK17-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
5791 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]]
5792 // CHECK17-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !18
5793 // CHECK17-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !18
5794 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
5795 // CHECK17-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
5796 // CHECK17-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]]
5797 // CHECK17-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !18
5798 // CHECK17-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
5799 // CHECK17-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !18
5800 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
5801 // CHECK17-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
5802 // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]]
5803 // CHECK17-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !18
5804 // CHECK17-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
5805 // CHECK17-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !18
5806 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
5807 // CHECK17-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
5808 // CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]]
5809 // CHECK17-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !18
5810 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5811 // CHECK17: omp.body.continue:
5812 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5813 // CHECK17: omp.inner.for.inc:
5814 // CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
5815 // CHECK17-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
5816 // CHECK17-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
5817 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
5818 // CHECK17: omp.inner.for.end:
5819 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
5820 // CHECK17: omp.dispatch.inc:
5821 // CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5822 // CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
5823 // CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
5824 // CHECK17-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
5825 // CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5826 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
5827 // CHECK17-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
5828 // CHECK17-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4
5829 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
5830 // CHECK17: omp.dispatch.end:
5831 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
5832 // CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5833 // CHECK17-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
5834 // CHECK17-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5835 // CHECK17: .omp.final.then:
5836 // CHECK17-NEXT: store i32 -2147483522, i32* [[I]], align 4
5837 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]
5838 // CHECK17: .omp.final.done:
5839 // CHECK17-NEXT: ret void
5840 //
5841 //
5842 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
5843 // CHECK17-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {
5844 // CHECK17-NEXT: entry:
5845 // CHECK17-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8
5846 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
5847 // CHECK17-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
5848 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
5849 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i8*
5850 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i8*
5851 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
5852 // CHECK17-NEXT: ret void
5853 //
5854 //
5855 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3
5856 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] {
5857 // CHECK17-NEXT: entry:
5858 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5859 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5860 // CHECK17-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 8
5861 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8
5862 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5863 // CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1
5864 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
5865 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
5866 // CHECK17-NEXT: [[I4:%.*]] = alloca i8, align 1
5867 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5868 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5869 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5870 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5871 // CHECK17-NEXT: [[I6:%.*]] = alloca i8, align 1
5872 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5873 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5874 // CHECK17-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 8
5875 // CHECK17-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8
5876 // CHECK17-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 8
5877 // CHECK17-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 8
5878 // CHECK17-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
5879 // CHECK17-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
5880 // CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5881 // CHECK17-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
5882 // CHECK17-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
5883 // CHECK17-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
5884 // CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
5885 // CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
5886 // CHECK17-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
5887 // CHECK17-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
5888 // CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5889 // CHECK17-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
5890 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5891 // CHECK17-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
5892 // CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
5893 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
5894 // CHECK17: omp.precond.then:
5895 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5896 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
5897 // CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
5898 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5899 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5900 // CHECK17-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5901 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
5902 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5903 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5904 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
5905 // CHECK17-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
5906 // CHECK17-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5907 // CHECK17: cond.true:
5908 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
5909 // CHECK17-NEXT: br label [[COND_END:%.*]]
5910 // CHECK17: cond.false:
5911 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5912 // CHECK17-NEXT: br label [[COND_END]]
5913 // CHECK17: cond.end:
5914 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
5915 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5916 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5917 // CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
5918 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5919 // CHECK17: omp.inner.for.cond:
5920 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
5921 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
5922 // CHECK17-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
5923 // CHECK17-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5924 // CHECK17: omp.inner.for.body:
5925 // CHECK17-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21
5926 // CHECK17-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
5927 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
5928 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
5929 // CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
5930 // CHECK17-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
5931 // CHECK17-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !21
5932 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5933 // CHECK17: omp.body.continue:
5934 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5935 // CHECK17: omp.inner.for.inc:
5936 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
5937 // CHECK17-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
5938 // CHECK17-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
5939 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
5940 // CHECK17: omp.inner.for.end:
5941 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5942 // CHECK17: omp.loop.exit:
5943 // CHECK17-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5944 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
5945 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
5946 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5947 // CHECK17-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
5948 // CHECK17-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5949 // CHECK17: .omp.final.then:
5950 // CHECK17-NEXT: [[TMP23:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5951 // CHECK17-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32
5952 // CHECK17-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5953 // CHECK17-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32
5954 // CHECK17-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
5955 // CHECK17-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
5956 // CHECK17-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
5957 // CHECK17-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
5958 // CHECK17-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
5959 // CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
5960 // CHECK17-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
5961 // CHECK17-NEXT: store i8 [[CONV21]], i8* [[TMP0]], align 1
5962 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]
5963 // CHECK17: .omp.final.done:
5964 // CHECK17-NEXT: br label [[OMP_PRECOND_END]]
5965 // CHECK17: omp.precond.end:
5966 // CHECK17-NEXT: ret void
5967 //
5968 //
5969 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
5970 // CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] {
5971 // CHECK17-NEXT: entry:
5972 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
5973 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
5974 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5975 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]])
5976 // CHECK17-NEXT: ret void
5977 //
5978 //
5979 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
5980 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
5981 // CHECK17-NEXT: entry:
5982 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5983 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5984 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8
5985 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5986 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
5987 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5988 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5989 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5990 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5991 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4
5992 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5993 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5994 // CHECK17-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
5995 // CHECK17-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
5996 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5997 // CHECK17-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
5998 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5999 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6000 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
6001 // CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
6002 // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
6003 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
6004 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
6005 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
6006 // CHECK17: omp.dispatch.cond:
6007 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6008 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
6009 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6010 // CHECK17: cond.true:
6011 // CHECK17-NEXT: br label [[COND_END:%.*]]
6012 // CHECK17: cond.false:
6013 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6014 // CHECK17-NEXT: br label [[COND_END]]
6015 // CHECK17: cond.end:
6016 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
6017 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6018 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6019 // CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
6020 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6021 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6022 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
6023 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
6024 // CHECK17: omp.dispatch.body:
6025 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6026 // CHECK17: omp.inner.for.cond:
6027 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
6028 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
6029 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
6030 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6031 // CHECK17: omp.inner.for.body:
6032 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
6033 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
6034 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6035 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
6036 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6037 // CHECK17: omp.body.continue:
6038 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6039 // CHECK17: omp.inner.for.inc:
6040 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
6041 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
6042 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
6043 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
6044 // CHECK17: omp.inner.for.end:
6045 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
6046 // CHECK17: omp.dispatch.inc:
6047 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6048 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6049 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
6050 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
6051 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6052 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6053 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
6054 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
6055 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
6056 // CHECK17: omp.dispatch.end:
6057 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
6058 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6059 // CHECK17-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
6060 // CHECK17-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6061 // CHECK17: .omp.final.then:
6062 // CHECK17-NEXT: store i32 100, i32* [[I]], align 4
6063 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]
6064 // CHECK17: .omp.final.done:
6065 // CHECK17-NEXT: ret void
6066 //
6067 //
6068 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
6069 // CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
6070 // CHECK19-NEXT: entry:
6071 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
6072 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
6073 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
6074 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
6075 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
6076 // CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
6077 // CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
6078 // CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
6079 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
6080 // CHECK19-NEXT: ret void
6081 //
6082 //
6083 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
6084 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
6085 // CHECK19-NEXT: entry:
6086 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6087 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6088 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
6089 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
6090 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
6091 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
6092 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6093 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
6094 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6095 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6096 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6097 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6098 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4
6099 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6100 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6101 // CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
6102 // CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
6103 // CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
6104 // CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
6105 // CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
6106 // CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
6107 // CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
6108 // CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
6109 // CHECK19-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 4
6110 // CHECK19-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i32 16) ]
6111 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6112 // CHECK19-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
6113 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6114 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6115 // CHECK19-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6116 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
6117 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6118 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6119 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
6120 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6121 // CHECK19: cond.true:
6122 // CHECK19-NEXT: br label [[COND_END:%.*]]
6123 // CHECK19: cond.false:
6124 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6125 // CHECK19-NEXT: br label [[COND_END]]
6126 // CHECK19: cond.end:
6127 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
6128 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6129 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6130 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
6131 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6132 // CHECK19: omp.inner.for.cond:
6133 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
6134 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
6135 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
6136 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6137 // CHECK19: omp.inner.for.body:
6138 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
6139 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
6140 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
6141 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
6142 // CHECK19-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10
6143 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
6144 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
6145 // CHECK19-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10
6146 // CHECK19-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10
6147 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
6148 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP16]], i32 [[TMP17]]
6149 // CHECK19-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !10
6150 // CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
6151 // CHECK19-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10
6152 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
6153 // CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP19]], i32 [[TMP20]]
6154 // CHECK19-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !10
6155 // CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
6156 // CHECK19-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10
6157 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
6158 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP22]], i32 [[TMP23]]
6159 // CHECK19-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !10
6160 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6161 // CHECK19: omp.body.continue:
6162 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6163 // CHECK19: omp.inner.for.inc:
6164 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
6165 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
6166 // CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
6167 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
6168 // CHECK19: omp.inner.for.end:
6169 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6170 // CHECK19: omp.loop.exit:
6171 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
6172 // CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6173 // CHECK19-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
6174 // CHECK19-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6175 // CHECK19: .omp.final.then:
6176 // CHECK19-NEXT: store i32 32000001, i32* [[I]], align 4
6177 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]
6178 // CHECK19: .omp.final.done:
6179 // CHECK19-NEXT: ret void
6180 //
6181 //
6182 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
6183 // CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
6184 // CHECK19-NEXT: entry:
6185 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
6186 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
6187 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
6188 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
6189 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
6190 // CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
6191 // CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
6192 // CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
6193 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
6194 // CHECK19-NEXT: ret void
6195 //
6196 //
6197 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1
6198 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
6199 // CHECK19-NEXT: entry:
6200 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6201 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6202 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
6203 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
6204 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
6205 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
6206 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6207 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
6208 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6209 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6210 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6211 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6212 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4
6213 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6214 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6215 // CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
6216 // CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
6217 // CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
6218 // CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
6219 // CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
6220 // CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
6221 // CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
6222 // CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
6223 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6224 // CHECK19-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
6225 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6226 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6227 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6228 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
6229 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6230 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6231 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
6232 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6233 // CHECK19: cond.true:
6234 // CHECK19-NEXT: br label [[COND_END:%.*]]
6235 // CHECK19: cond.false:
6236 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6237 // CHECK19-NEXT: br label [[COND_END]]
6238 // CHECK19: cond.end:
6239 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
6240 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6241 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6242 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
6243 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6244 // CHECK19: omp.inner.for.cond:
6245 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6246 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6247 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
6248 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6249 // CHECK19: omp.inner.for.body:
6250 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6251 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
6252 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
6253 // CHECK19-NEXT: store i32 [[SUB]], i32* [[I]], align 4
6254 // CHECK19-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4
6255 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
6256 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]]
6257 // CHECK19-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
6258 // CHECK19-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4
6259 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
6260 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]]
6261 // CHECK19-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4
6262 // CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
6263 // CHECK19-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4
6264 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
6265 // CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]]
6266 // CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4
6267 // CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
6268 // CHECK19-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4
6269 // CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
6270 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]]
6271 // CHECK19-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
6272 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6273 // CHECK19: omp.body.continue:
6274 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6275 // CHECK19: omp.inner.for.inc:
6276 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6277 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
6278 // CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
6279 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
6280 // CHECK19: omp.inner.for.end:
6281 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6282 // CHECK19: omp.loop.exit:
6283 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
6284 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6285 // CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
6286 // CHECK19-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6287 // CHECK19: .omp.final.then:
6288 // CHECK19-NEXT: store i32 32, i32* [[I]], align 4
6289 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]
6290 // CHECK19: .omp.final.done:
6291 // CHECK19-NEXT: ret void
6292 //
6293 //
6294 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
6295 // CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
6296 // CHECK19-NEXT: entry:
6297 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
6298 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
6299 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
6300 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
6301 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
6302 // CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
6303 // CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
6304 // CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
6305 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
6306 // CHECK19-NEXT: ret void
6307 //
6308 //
6309 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2
6310 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
6311 // CHECK19-NEXT: entry:
6312 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6313 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6314 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
6315 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
6316 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
6317 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
6318 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6319 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
6320 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6321 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6322 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6323 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6324 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4
6325 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6326 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6327 // CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
6328 // CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
6329 // CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
6330 // CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
6331 // CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
6332 // CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
6333 // CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
6334 // CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
6335 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6336 // CHECK19-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
6337 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6338 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6339 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6340 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
6341 // CHECK19-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
6342 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
6343 // CHECK19: omp.dispatch.cond:
6344 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6345 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
6346 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6347 // CHECK19: cond.true:
6348 // CHECK19-NEXT: br label [[COND_END:%.*]]
6349 // CHECK19: cond.false:
6350 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6351 // CHECK19-NEXT: br label [[COND_END]]
6352 // CHECK19: cond.end:
6353 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
6354 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6355 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6356 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
6357 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6358 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6359 // CHECK19-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
6360 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
6361 // CHECK19: omp.dispatch.body:
6362 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6363 // CHECK19: omp.inner.for.cond:
6364 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
6365 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
6366 // CHECK19-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
6367 // CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6368 // CHECK19: omp.inner.for.body:
6369 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
6370 // CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
6371 // CHECK19-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
6372 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
6373 // CHECK19-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !19
6374 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
6375 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
6376 // CHECK19-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !19
6377 // CHECK19-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !19
6378 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
6379 // CHECK19-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]]
6380 // CHECK19-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !19
6381 // CHECK19-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
6382 // CHECK19-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !19
6383 // CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
6384 // CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]]
6385 // CHECK19-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !19
6386 // CHECK19-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
6387 // CHECK19-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !19
6388 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
6389 // CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]]
6390 // CHECK19-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !19
6391 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6392 // CHECK19: omp.body.continue:
6393 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6394 // CHECK19: omp.inner.for.inc:
6395 // CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
6396 // CHECK19-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
6397 // CHECK19-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
6398 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
6399 // CHECK19: omp.inner.for.end:
6400 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
6401 // CHECK19: omp.dispatch.inc:
6402 // CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6403 // CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6404 // CHECK19-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
6405 // CHECK19-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
6406 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6407 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6408 // CHECK19-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]]
6409 // CHECK19-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4
6410 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
6411 // CHECK19: omp.dispatch.end:
6412 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
6413 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6414 // CHECK19-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
6415 // CHECK19-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6416 // CHECK19: .omp.final.then:
6417 // CHECK19-NEXT: store i32 -2147483522, i32* [[I]], align 4
6418 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]
6419 // CHECK19: .omp.final.done:
6420 // CHECK19-NEXT: ret void
6421 //
6422 //
6423 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
6424 // CHECK19-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {
6425 // CHECK19-NEXT: entry:
6426 // CHECK19-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4
6427 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
6428 // CHECK19-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4
6429 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
6430 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[I_ADDR]] to i8*
6431 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_ADDR]] to i8*
6432 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
6433 // CHECK19-NEXT: ret void
6434 //
6435 //
6436 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3
6437 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] {
6438 // CHECK19-NEXT: entry:
6439 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6440 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6441 // CHECK19-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 4
6442 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4
6443 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6444 // CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1
6445 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
6446 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
6447 // CHECK19-NEXT: [[I4:%.*]] = alloca i8, align 1
6448 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6449 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6450 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6451 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6452 // CHECK19-NEXT: [[I6:%.*]] = alloca i8, align 1
6453 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6454 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6455 // CHECK19-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 4
6456 // CHECK19-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4
6457 // CHECK19-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 4
6458 // CHECK19-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 4
6459 // CHECK19-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
6460 // CHECK19-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
6461 // CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
6462 // CHECK19-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
6463 // CHECK19-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
6464 // CHECK19-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
6465 // CHECK19-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
6466 // CHECK19-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
6467 // CHECK19-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
6468 // CHECK19-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
6469 // CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
6470 // CHECK19-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
6471 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
6472 // CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
6473 // CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
6474 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
6475 // CHECK19: omp.precond.then:
6476 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6477 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
6478 // CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
6479 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6480 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6481 // CHECK19-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6482 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
6483 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6484 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6485 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
6486 // CHECK19-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
6487 // CHECK19-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6488 // CHECK19: cond.true:
6489 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
6490 // CHECK19-NEXT: br label [[COND_END:%.*]]
6491 // CHECK19: cond.false:
6492 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6493 // CHECK19-NEXT: br label [[COND_END]]
6494 // CHECK19: cond.end:
6495 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
6496 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6497 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6498 // CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
6499 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6500 // CHECK19: omp.inner.for.cond:
6501 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
6502 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
6503 // CHECK19-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
6504 // CHECK19-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6505 // CHECK19: omp.inner.for.body:
6506 // CHECK19-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22
6507 // CHECK19-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
6508 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
6509 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
6510 // CHECK19-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
6511 // CHECK19-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
6512 // CHECK19-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !22
6513 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6514 // CHECK19: omp.body.continue:
6515 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6516 // CHECK19: omp.inner.for.inc:
6517 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
6518 // CHECK19-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
6519 // CHECK19-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
6520 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
6521 // CHECK19: omp.inner.for.end:
6522 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6523 // CHECK19: omp.loop.exit:
6524 // CHECK19-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6525 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
6526 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
6527 // CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6528 // CHECK19-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
6529 // CHECK19-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6530 // CHECK19: .omp.final.then:
6531 // CHECK19-NEXT: [[TMP23:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
6532 // CHECK19-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32
6533 // CHECK19-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
6534 // CHECK19-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32
6535 // CHECK19-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
6536 // CHECK19-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
6537 // CHECK19-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
6538 // CHECK19-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
6539 // CHECK19-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
6540 // CHECK19-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
6541 // CHECK19-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
6542 // CHECK19-NEXT: store i8 [[CONV21]], i8* [[TMP0]], align 1
6543 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]
6544 // CHECK19: .omp.final.done:
6545 // CHECK19-NEXT: br label [[OMP_PRECOND_END]]
6546 // CHECK19: omp.precond.end:
6547 // CHECK19-NEXT: ret void
6548 //
6549 //
6550 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
6551 // CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] {
6552 // CHECK19-NEXT: entry:
6553 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
6554 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
6555 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6556 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]])
6557 // CHECK19-NEXT: ret void
6558 //
6559 //
6560 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4
6561 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
6562 // CHECK19-NEXT: entry:
6563 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6564 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6565 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4
6566 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6567 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
6568 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6569 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6570 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6571 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6572 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4
6573 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6574 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6575 // CHECK19-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
6576 // CHECK19-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
6577 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6578 // CHECK19-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
6579 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6580 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6581 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
6582 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
6583 // CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6584 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
6585 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
6586 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
6587 // CHECK19: omp.dispatch.cond:
6588 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6589 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
6590 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6591 // CHECK19: cond.true:
6592 // CHECK19-NEXT: br label [[COND_END:%.*]]
6593 // CHECK19: cond.false:
6594 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6595 // CHECK19-NEXT: br label [[COND_END]]
6596 // CHECK19: cond.end:
6597 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
6598 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6599 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6600 // CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
6601 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6602 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6603 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
6604 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
6605 // CHECK19: omp.dispatch.body:
6606 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6607 // CHECK19: omp.inner.for.cond:
6608 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
6609 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
6610 // CHECK19-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
6611 // CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6612 // CHECK19: omp.inner.for.body:
6613 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
6614 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
6615 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6616 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
6617 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6618 // CHECK19: omp.body.continue:
6619 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6620 // CHECK19: omp.inner.for.inc:
6621 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
6622 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
6623 // CHECK19-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
6624 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
6625 // CHECK19: omp.inner.for.end:
6626 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
6627 // CHECK19: omp.dispatch.inc:
6628 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6629 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6630 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
6631 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
6632 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6633 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6634 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
6635 // CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
6636 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
6637 // CHECK19: omp.dispatch.end:
6638 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
6639 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6640 // CHECK19-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
6641 // CHECK19-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6642 // CHECK19: .omp.final.then:
6643 // CHECK19-NEXT: store i32 100, i32* [[I]], align 4
6644 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]
6645 // CHECK19: .omp.final.done:
6646 // CHECK19-NEXT: ret void
6647 //
6648 //
6649 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
6650 // CHECK21-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
6651 // CHECK21-NEXT: entry:
6652 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
6653 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
6654 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
6655 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
6656 // CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
6657 // CHECK21-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
6658 // CHECK21-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
6659 // CHECK21-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
6660 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
6661 // CHECK21-NEXT: ret void
6662 //
6663 //
6664 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined.
6665 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
6666 // CHECK21-NEXT: entry:
6667 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6668 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6669 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
6670 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
6671 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
6672 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
6673 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6674 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4
6675 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6676 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6677 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6678 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6679 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4
6680 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6681 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6682 // CHECK21-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
6683 // CHECK21-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
6684 // CHECK21-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
6685 // CHECK21-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
6686 // CHECK21-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
6687 // CHECK21-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
6688 // CHECK21-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
6689 // CHECK21-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
6690 // CHECK21-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 8
6691 // CHECK21-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i64 16) ]
6692 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6693 // CHECK21-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
6694 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6695 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6696 // CHECK21-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
6697 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
6698 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6699 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6700 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
6701 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6702 // CHECK21: cond.true:
6703 // CHECK21-NEXT: br label [[COND_END:%.*]]
6704 // CHECK21: cond.false:
6705 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6706 // CHECK21-NEXT: br label [[COND_END]]
6707 // CHECK21: cond.end:
6708 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
6709 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6710 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6711 // CHECK21-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
6712 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6713 // CHECK21: omp.inner.for.cond:
6714 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
6715 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
6716 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
6717 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6718 // CHECK21: omp.inner.for.body:
6719 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
6720 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
6721 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
6722 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
6723 // CHECK21-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9
6724 // CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
6725 // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
6726 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]]
6727 // CHECK21-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9
6728 // CHECK21-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9
6729 // CHECK21-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
6730 // CHECK21-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
6731 // CHECK21-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM2]]
6732 // CHECK21-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !9
6733 // CHECK21-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
6734 // CHECK21-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9
6735 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
6736 // CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
6737 // CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM5]]
6738 // CHECK21-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !llvm.access.group !9
6739 // CHECK21-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
6740 // CHECK21-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9
6741 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
6742 // CHECK21-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
6743 // CHECK21-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM8]]
6744 // CHECK21-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !9
6745 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6746 // CHECK21: omp.body.continue:
6747 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6748 // CHECK21: omp.inner.for.inc:
6749 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
6750 // CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
6751 // CHECK21-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
6752 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
6753 // CHECK21: omp.inner.for.end:
6754 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6755 // CHECK21: omp.loop.exit:
6756 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
6757 // CHECK21-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6758 // CHECK21-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
6759 // CHECK21-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6760 // CHECK21: .omp.final.then:
6761 // CHECK21-NEXT: store i32 32000001, i32* [[I]], align 4
6762 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]
6763 // CHECK21: .omp.final.done:
6764 // CHECK21-NEXT: ret void
6765 //
6766 //
6767 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
6768 // CHECK21-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
6769 // CHECK21-NEXT: entry:
6770 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
6771 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
6772 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
6773 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
6774 // CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
6775 // CHECK21-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
6776 // CHECK21-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
6777 // CHECK21-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
6778 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
6779 // CHECK21-NEXT: ret void
6780 //
6781 //
6782 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1
6783 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
6784 // CHECK21-NEXT: entry:
6785 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6786 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6787 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
6788 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
6789 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
6790 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
6791 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6792 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4
6793 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6794 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6795 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6796 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6797 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4
6798 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6799 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6800 // CHECK21-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
6801 // CHECK21-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
6802 // CHECK21-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
6803 // CHECK21-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
6804 // CHECK21-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
6805 // CHECK21-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
6806 // CHECK21-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
6807 // CHECK21-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
6808 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6809 // CHECK21-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
6810 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6811 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6812 // CHECK21-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
6813 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
6814 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6815 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6816 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
6817 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6818 // CHECK21: cond.true:
6819 // CHECK21-NEXT: br label [[COND_END:%.*]]
6820 // CHECK21: cond.false:
6821 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6822 // CHECK21-NEXT: br label [[COND_END]]
6823 // CHECK21: cond.end:
6824 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
6825 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6826 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6827 // CHECK21-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
6828 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6829 // CHECK21: omp.inner.for.cond:
6830 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6831 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6832 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
6833 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6834 // CHECK21: omp.inner.for.body:
6835 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6836 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
6837 // CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
6838 // CHECK21-NEXT: store i32 [[SUB]], i32* [[I]], align 4
6839 // CHECK21-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8, !nontemporal !16
6840 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
6841 // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
6842 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]]
6843 // CHECK21-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
6844 // CHECK21-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8
6845 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
6846 // CHECK21-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
6847 // CHECK21-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]]
6848 // CHECK21-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4
6849 // CHECK21-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
6850 // CHECK21-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8
6851 // CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
6852 // CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
6853 // CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]]
6854 // CHECK21-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4
6855 // CHECK21-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
6856 // CHECK21-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8, !nontemporal !16
6857 // CHECK21-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
6858 // CHECK21-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
6859 // CHECK21-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]]
6860 // CHECK21-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
6861 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6862 // CHECK21: omp.body.continue:
6863 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6864 // CHECK21: omp.inner.for.inc:
6865 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6866 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
6867 // CHECK21-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
6868 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
6869 // CHECK21: omp.inner.for.end:
6870 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6871 // CHECK21: omp.loop.exit:
6872 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
6873 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6874 // CHECK21-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
6875 // CHECK21-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6876 // CHECK21: .omp.final.then:
6877 // CHECK21-NEXT: store i32 32, i32* [[I]], align 4
6878 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]
6879 // CHECK21: .omp.final.done:
6880 // CHECK21-NEXT: ret void
6881 //
6882 //
6883 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
6884 // CHECK21-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
6885 // CHECK21-NEXT: entry:
6886 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
6887 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
6888 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
6889 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
6890 // CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
6891 // CHECK21-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
6892 // CHECK21-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
6893 // CHECK21-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
6894 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
6895 // CHECK21-NEXT: ret void
6896 //
6897 //
6898 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2
6899 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
6900 // CHECK21-NEXT: entry:
6901 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6902 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6903 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
6904 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
6905 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
6906 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
6907 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6908 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4
6909 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6910 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6911 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6912 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6913 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4
6914 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6915 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6916 // CHECK21-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
6917 // CHECK21-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
6918 // CHECK21-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
6919 // CHECK21-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
6920 // CHECK21-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
6921 // CHECK21-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
6922 // CHECK21-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
6923 // CHECK21-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
6924 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6925 // CHECK21-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
6926 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6927 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6928 // CHECK21-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
6929 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
6930 // CHECK21-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
6931 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
6932 // CHECK21: omp.dispatch.cond:
6933 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6934 // CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
6935 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6936 // CHECK21: cond.true:
6937 // CHECK21-NEXT: br label [[COND_END:%.*]]
6938 // CHECK21: cond.false:
6939 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6940 // CHECK21-NEXT: br label [[COND_END]]
6941 // CHECK21: cond.end:
6942 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
6943 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6944 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6945 // CHECK21-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
6946 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6947 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6948 // CHECK21-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
6949 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
6950 // CHECK21: omp.dispatch.body:
6951 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6952 // CHECK21: omp.inner.for.cond:
6953 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
6954 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
6955 // CHECK21-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
6956 // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6957 // CHECK21: omp.inner.for.body:
6958 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
6959 // CHECK21-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
6960 // CHECK21-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
6961 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
6962 // CHECK21-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !19
6963 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
6964 // CHECK21-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
6965 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]]
6966 // CHECK21-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !19
6967 // CHECK21-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !19
6968 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
6969 // CHECK21-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
6970 // CHECK21-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]]
6971 // CHECK21-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !19
6972 // CHECK21-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
6973 // CHECK21-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !19
6974 // CHECK21-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
6975 // CHECK21-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
6976 // CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]]
6977 // CHECK21-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !19
6978 // CHECK21-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
6979 // CHECK21-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !19
6980 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
6981 // CHECK21-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
6982 // CHECK21-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]]
6983 // CHECK21-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !19
6984 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6985 // CHECK21: omp.body.continue:
6986 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6987 // CHECK21: omp.inner.for.inc:
6988 // CHECK21-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
6989 // CHECK21-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
6990 // CHECK21-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
6991 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
6992 // CHECK21: omp.inner.for.end:
6993 // CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
6994 // CHECK21: omp.dispatch.inc:
6995 // CHECK21-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6996 // CHECK21-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6997 // CHECK21-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
6998 // CHECK21-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
6999 // CHECK21-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7000 // CHECK21-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
7001 // CHECK21-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
7002 // CHECK21-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4
7003 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND]]
7004 // CHECK21: omp.dispatch.end:
7005 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
7006 // CHECK21-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7007 // CHECK21-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
7008 // CHECK21-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7009 // CHECK21: .omp.final.then:
7010 // CHECK21-NEXT: store i32 -2147483522, i32* [[I]], align 4
7011 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]
7012 // CHECK21: .omp.final.done:
7013 // CHECK21-NEXT: ret void
7014 //
7015 //
7016 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
7017 // CHECK21-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {
7018 // CHECK21-NEXT: entry:
7019 // CHECK21-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8
7020 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
7021 // CHECK21-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
7022 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
7023 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i8*
7024 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i8*
7025 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
7026 // CHECK21-NEXT: ret void
7027 //
7028 //
7029 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3
7030 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] {
7031 // CHECK21-NEXT: entry:
7032 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
7033 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
7034 // CHECK21-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 8
7035 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8
7036 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7037 // CHECK21-NEXT: [[TMP:%.*]] = alloca i8, align 1
7038 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
7039 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
7040 // CHECK21-NEXT: [[I4:%.*]] = alloca i8, align 1
7041 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7042 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7043 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7044 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7045 // CHECK21-NEXT: [[I6:%.*]] = alloca i8, align 1
7046 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
7047 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
7048 // CHECK21-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 8
7049 // CHECK21-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8
7050 // CHECK21-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 8
7051 // CHECK21-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 8
7052 // CHECK21-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
7053 // CHECK21-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
7054 // CHECK21-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7055 // CHECK21-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
7056 // CHECK21-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
7057 // CHECK21-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
7058 // CHECK21-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
7059 // CHECK21-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
7060 // CHECK21-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
7061 // CHECK21-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
7062 // CHECK21-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7063 // CHECK21-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
7064 // CHECK21-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7065 // CHECK21-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
7066 // CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
7067 // CHECK21-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
7068 // CHECK21: omp.precond.then:
7069 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7070 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
7071 // CHECK21-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
7072 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7073 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7074 // CHECK21-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
7075 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
7076 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7077 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7078 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
7079 // CHECK21-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
7080 // CHECK21-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7081 // CHECK21: cond.true:
7082 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
7083 // CHECK21-NEXT: br label [[COND_END:%.*]]
7084 // CHECK21: cond.false:
7085 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7086 // CHECK21-NEXT: br label [[COND_END]]
7087 // CHECK21: cond.end:
7088 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
7089 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7090 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7091 // CHECK21-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
7092 // CHECK21-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP1]], align 1
7093 // CHECK21-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
7094 // CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7095 // CHECK21: omp_if.then:
7096 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7097 // CHECK21: omp.inner.for.cond:
7098 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
7099 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
7100 // CHECK21-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
7101 // CHECK21-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7102 // CHECK21: omp.inner.for.body:
7103 // CHECK21-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22
7104 // CHECK21-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
7105 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
7106 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
7107 // CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
7108 // CHECK21-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
7109 // CHECK21-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !16, !llvm.access.group !22
7110 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7111 // CHECK21: omp.body.continue:
7112 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7113 // CHECK21: omp.inner.for.inc:
7114 // CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
7115 // CHECK21-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
7116 // CHECK21-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
7117 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
7118 // CHECK21: omp.inner.for.end:
7119 // CHECK21-NEXT: br label [[OMP_IF_END:%.*]]
7120 // CHECK21: omp_if.else:
7121 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
7122 // CHECK21: omp.inner.for.cond13:
7123 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7124 // CHECK21-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7125 // CHECK21-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
7126 // CHECK21-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
7127 // CHECK21: omp.inner.for.body15:
7128 // CHECK21-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7129 // CHECK21-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
7130 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7131 // CHECK21-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
7132 // CHECK21-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
7133 // CHECK21-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
7134 // CHECK21-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
7135 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
7136 // CHECK21: omp.body.continue20:
7137 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
7138 // CHECK21: omp.inner.for.inc21:
7139 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7140 // CHECK21-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
7141 // CHECK21-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
7142 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]]
7143 // CHECK21: omp.inner.for.end23:
7144 // CHECK21-NEXT: br label [[OMP_IF_END]]
7145 // CHECK21: omp_if.end:
7146 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
7147 // CHECK21: omp.loop.exit:
7148 // CHECK21-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
7149 // CHECK21-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
7150 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
7151 // CHECK21-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7152 // CHECK21-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
7153 // CHECK21-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7154 // CHECK21: .omp.final.then:
7155 // CHECK21-NEXT: [[TMP29:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7156 // CHECK21-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32
7157 // CHECK21-NEXT: [[TMP30:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7158 // CHECK21-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32
7159 // CHECK21-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
7160 // CHECK21-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
7161 // CHECK21-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
7162 // CHECK21-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
7163 // CHECK21-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
7164 // CHECK21-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
7165 // CHECK21-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
7166 // CHECK21-NEXT: store i8 [[CONV32]], i8* [[TMP0]], align 1
7167 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]
7168 // CHECK21: .omp.final.done:
7169 // CHECK21-NEXT: br label [[OMP_PRECOND_END]]
7170 // CHECK21: omp.precond.end:
7171 // CHECK21-NEXT: ret void
7172 //
7173 //
7174 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
7175 // CHECK21-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] {
7176 // CHECK21-NEXT: entry:
7177 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
7178 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
7179 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
7180 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]])
7181 // CHECK21-NEXT: ret void
7182 //
7183 //
7184 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4
7185 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
7186 // CHECK21-NEXT: entry:
7187 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
7188 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
7189 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8
7190 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7191 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4
7192 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7193 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7194 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7195 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7196 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4
7197 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
7198 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
7199 // CHECK21-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
7200 // CHECK21-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
7201 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7202 // CHECK21-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
7203 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7204 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7205 // CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
7206 // CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
7207 // CHECK21-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
7208 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
7209 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
7210 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
7211 // CHECK21: omp.dispatch.cond:
7212 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7213 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
7214 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7215 // CHECK21: cond.true:
7216 // CHECK21-NEXT: br label [[COND_END:%.*]]
7217 // CHECK21: cond.false:
7218 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7219 // CHECK21-NEXT: br label [[COND_END]]
7220 // CHECK21: cond.end:
7221 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
7222 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7223 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7224 // CHECK21-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
7225 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7226 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7227 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
7228 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
7229 // CHECK21: omp.dispatch.body:
7230 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7231 // CHECK21: omp.inner.for.cond:
7232 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
7233 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
7234 // CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
7235 // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7236 // CHECK21: omp.inner.for.body:
7237 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
7238 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
7239 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7240 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
7241 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7242 // CHECK21: omp.body.continue:
7243 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7244 // CHECK21: omp.inner.for.inc:
7245 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
7246 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
7247 // CHECK21-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
7248 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
7249 // CHECK21: omp.inner.for.end:
7250 // CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
7251 // CHECK21: omp.dispatch.inc:
7252 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7253 // CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
7254 // CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
7255 // CHECK21-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
7256 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7257 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
7258 // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
7259 // CHECK21-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
7260 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND]]
7261 // CHECK21: omp.dispatch.end:
7262 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
7263 // CHECK21-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7264 // CHECK21-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
7265 // CHECK21-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7266 // CHECK21: .omp.final.then:
7267 // CHECK21-NEXT: store i32 100, i32* [[I]], align 4
7268 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]
7269 // CHECK21: .omp.final.done:
7270 // CHECK21-NEXT: ret void
7271 //
7272 //
7273 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
7274 // CHECK23-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
7275 // CHECK23-NEXT: entry:
7276 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
7277 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
7278 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
7279 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
7280 // CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
7281 // CHECK23-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
7282 // CHECK23-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
7283 // CHECK23-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
7284 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
7285 // CHECK23-NEXT: ret void
7286 //
7287 //
7288 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined.
7289 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
7290 // CHECK23-NEXT: entry:
7291 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7292 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7293 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
7294 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
7295 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
7296 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
7297 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7298 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4
7299 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7300 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7301 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7302 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7303 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4
7304 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7305 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7306 // CHECK23-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
7307 // CHECK23-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
7308 // CHECK23-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
7309 // CHECK23-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
7310 // CHECK23-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
7311 // CHECK23-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
7312 // CHECK23-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
7313 // CHECK23-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
7314 // CHECK23-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 4
7315 // CHECK23-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i32 16) ]
7316 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7317 // CHECK23-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
7318 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7319 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7320 // CHECK23-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7321 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
7322 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7323 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7324 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
7325 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7326 // CHECK23: cond.true:
7327 // CHECK23-NEXT: br label [[COND_END:%.*]]
7328 // CHECK23: cond.false:
7329 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7330 // CHECK23-NEXT: br label [[COND_END]]
7331 // CHECK23: cond.end:
7332 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
7333 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7334 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7335 // CHECK23-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
7336 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7337 // CHECK23: omp.inner.for.cond:
7338 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
7339 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
7340 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
7341 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7342 // CHECK23: omp.inner.for.body:
7343 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
7344 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
7345 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
7346 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
7347 // CHECK23-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10
7348 // CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
7349 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
7350 // CHECK23-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10
7351 // CHECK23-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10
7352 // CHECK23-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
7353 // CHECK23-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP16]], i32 [[TMP17]]
7354 // CHECK23-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !10
7355 // CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
7356 // CHECK23-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10
7357 // CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
7358 // CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP19]], i32 [[TMP20]]
7359 // CHECK23-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !10
7360 // CHECK23-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
7361 // CHECK23-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10
7362 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
7363 // CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP22]], i32 [[TMP23]]
7364 // CHECK23-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !10
7365 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7366 // CHECK23: omp.body.continue:
7367 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7368 // CHECK23: omp.inner.for.inc:
7369 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
7370 // CHECK23-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
7371 // CHECK23-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
7372 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
7373 // CHECK23: omp.inner.for.end:
7374 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
7375 // CHECK23: omp.loop.exit:
7376 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
7377 // CHECK23-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7378 // CHECK23-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
7379 // CHECK23-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7380 // CHECK23: .omp.final.then:
7381 // CHECK23-NEXT: store i32 32000001, i32* [[I]], align 4
7382 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]
7383 // CHECK23: .omp.final.done:
7384 // CHECK23-NEXT: ret void
7385 //
7386 //
7387 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
7388 // CHECK23-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
7389 // CHECK23-NEXT: entry:
7390 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
7391 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
7392 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
7393 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
7394 // CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
7395 // CHECK23-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
7396 // CHECK23-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
7397 // CHECK23-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
7398 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
7399 // CHECK23-NEXT: ret void
7400 //
7401 //
7402 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1
7403 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
7404 // CHECK23-NEXT: entry:
7405 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7406 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7407 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
7408 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
7409 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
7410 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
7411 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7412 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4
7413 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7414 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7415 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7416 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7417 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4
7418 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7419 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7420 // CHECK23-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
7421 // CHECK23-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
7422 // CHECK23-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
7423 // CHECK23-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
7424 // CHECK23-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
7425 // CHECK23-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
7426 // CHECK23-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
7427 // CHECK23-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
7428 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7429 // CHECK23-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
7430 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7431 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7432 // CHECK23-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7433 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
7434 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7435 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7436 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
7437 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7438 // CHECK23: cond.true:
7439 // CHECK23-NEXT: br label [[COND_END:%.*]]
7440 // CHECK23: cond.false:
7441 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7442 // CHECK23-NEXT: br label [[COND_END]]
7443 // CHECK23: cond.end:
7444 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
7445 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7446 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7447 // CHECK23-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
7448 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7449 // CHECK23: omp.inner.for.cond:
7450 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7451 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7452 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
7453 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7454 // CHECK23: omp.inner.for.body:
7455 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7456 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
7457 // CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
7458 // CHECK23-NEXT: store i32 [[SUB]], i32* [[I]], align 4
7459 // CHECK23-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4, !nontemporal !17
7460 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
7461 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]]
7462 // CHECK23-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
7463 // CHECK23-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4
7464 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
7465 // CHECK23-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]]
7466 // CHECK23-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4
7467 // CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
7468 // CHECK23-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4
7469 // CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
7470 // CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]]
7471 // CHECK23-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4
7472 // CHECK23-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
7473 // CHECK23-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4, !nontemporal !17
7474 // CHECK23-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
7475 // CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]]
7476 // CHECK23-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
7477 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7478 // CHECK23: omp.body.continue:
7479 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7480 // CHECK23: omp.inner.for.inc:
7481 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7482 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
7483 // CHECK23-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
7484 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
7485 // CHECK23: omp.inner.for.end:
7486 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
7487 // CHECK23: omp.loop.exit:
7488 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
7489 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7490 // CHECK23-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
7491 // CHECK23-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7492 // CHECK23: .omp.final.then:
7493 // CHECK23-NEXT: store i32 32, i32* [[I]], align 4
7494 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]
7495 // CHECK23: .omp.final.done:
7496 // CHECK23-NEXT: ret void
7497 //
7498 //
7499 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
7500 // CHECK23-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] {
7501 // CHECK23-NEXT: entry:
7502 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
7503 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
7504 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
7505 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
7506 // CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
7507 // CHECK23-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
7508 // CHECK23-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
7509 // CHECK23-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
7510 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
7511 // CHECK23-NEXT: ret void
7512 //
7513 //
7514 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2
7515 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
7516 // CHECK23-NEXT: entry:
7517 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7518 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7519 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
7520 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
7521 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
7522 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
7523 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7524 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4
7525 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7526 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7527 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7528 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7529 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4
7530 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7531 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7532 // CHECK23-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
7533 // CHECK23-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
7534 // CHECK23-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
7535 // CHECK23-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
7536 // CHECK23-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
7537 // CHECK23-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
7538 // CHECK23-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
7539 // CHECK23-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
7540 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7541 // CHECK23-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
7542 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7543 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7544 // CHECK23-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7545 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
7546 // CHECK23-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
7547 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
7548 // CHECK23: omp.dispatch.cond:
7549 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7550 // CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
7551 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7552 // CHECK23: cond.true:
7553 // CHECK23-NEXT: br label [[COND_END:%.*]]
7554 // CHECK23: cond.false:
7555 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7556 // CHECK23-NEXT: br label [[COND_END]]
7557 // CHECK23: cond.end:
7558 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
7559 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7560 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7561 // CHECK23-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
7562 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7563 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7564 // CHECK23-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
7565 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
7566 // CHECK23: omp.dispatch.body:
7567 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7568 // CHECK23: omp.inner.for.cond:
7569 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
7570 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
7571 // CHECK23-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
7572 // CHECK23-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7573 // CHECK23: omp.inner.for.body:
7574 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
7575 // CHECK23-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
7576 // CHECK23-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
7577 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20
7578 // CHECK23-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !20
7579 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20
7580 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
7581 // CHECK23-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !20
7582 // CHECK23-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !20
7583 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20
7584 // CHECK23-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]]
7585 // CHECK23-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !20
7586 // CHECK23-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
7587 // CHECK23-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !20
7588 // CHECK23-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20
7589 // CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]]
7590 // CHECK23-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !20
7591 // CHECK23-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
7592 // CHECK23-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !20
7593 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20
7594 // CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]]
7595 // CHECK23-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !20
7596 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7597 // CHECK23: omp.body.continue:
7598 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7599 // CHECK23: omp.inner.for.inc:
7600 // CHECK23-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
7601 // CHECK23-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
7602 // CHECK23-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
7603 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
7604 // CHECK23: omp.inner.for.end:
7605 // CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
7606 // CHECK23: omp.dispatch.inc:
7607 // CHECK23-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7608 // CHECK23-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
7609 // CHECK23-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
7610 // CHECK23-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
7611 // CHECK23-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7612 // CHECK23-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
7613 // CHECK23-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]]
7614 // CHECK23-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4
7615 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND]]
7616 // CHECK23: omp.dispatch.end:
7617 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
7618 // CHECK23-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7619 // CHECK23-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
7620 // CHECK23-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7621 // CHECK23: .omp.final.then:
7622 // CHECK23-NEXT: store i32 -2147483522, i32* [[I]], align 4
7623 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]
7624 // CHECK23: .omp.final.done:
7625 // CHECK23-NEXT: ret void
7626 //
7627 //
7628 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
7629 // CHECK23-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {
7630 // CHECK23-NEXT: entry:
7631 // CHECK23-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4
7632 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7633 // CHECK23-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4
7634 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7635 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[I_ADDR]] to i8*
7636 // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_ADDR]] to i8*
7637 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
7638 // CHECK23-NEXT: ret void
7639 //
7640 //
7641 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3
7642 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] {
7643 // CHECK23-NEXT: entry:
7644 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7645 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7646 // CHECK23-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 4
7647 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4
7648 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7649 // CHECK23-NEXT: [[TMP:%.*]] = alloca i8, align 1
7650 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
7651 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
7652 // CHECK23-NEXT: [[I4:%.*]] = alloca i8, align 1
7653 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7654 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7655 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7656 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7657 // CHECK23-NEXT: [[I6:%.*]] = alloca i8, align 1
7658 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7659 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7660 // CHECK23-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 4
7661 // CHECK23-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4
7662 // CHECK23-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 4
7663 // CHECK23-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 4
7664 // CHECK23-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
7665 // CHECK23-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
7666 // CHECK23-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7667 // CHECK23-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
7668 // CHECK23-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
7669 // CHECK23-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
7670 // CHECK23-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
7671 // CHECK23-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
7672 // CHECK23-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
7673 // CHECK23-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
7674 // CHECK23-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7675 // CHECK23-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
7676 // CHECK23-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7677 // CHECK23-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
7678 // CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
7679 // CHECK23-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
7680 // CHECK23: omp.precond.then:
7681 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7682 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
7683 // CHECK23-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
7684 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7685 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7686 // CHECK23-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7687 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
7688 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7689 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7690 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
7691 // CHECK23-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
7692 // CHECK23-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7693 // CHECK23: cond.true:
7694 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
7695 // CHECK23-NEXT: br label [[COND_END:%.*]]
7696 // CHECK23: cond.false:
7697 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7698 // CHECK23-NEXT: br label [[COND_END]]
7699 // CHECK23: cond.end:
7700 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
7701 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7702 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7703 // CHECK23-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
7704 // CHECK23-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP1]], align 1
7705 // CHECK23-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
7706 // CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7707 // CHECK23: omp_if.then:
7708 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7709 // CHECK23: omp.inner.for.cond:
7710 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
7711 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23
7712 // CHECK23-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
7713 // CHECK23-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7714 // CHECK23: omp.inner.for.body:
7715 // CHECK23-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !23
7716 // CHECK23-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
7717 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
7718 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
7719 // CHECK23-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
7720 // CHECK23-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
7721 // CHECK23-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !17, !llvm.access.group !23
7722 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7723 // CHECK23: omp.body.continue:
7724 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7725 // CHECK23: omp.inner.for.inc:
7726 // CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
7727 // CHECK23-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
7728 // CHECK23-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
7729 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
7730 // CHECK23: omp.inner.for.end:
7731 // CHECK23-NEXT: br label [[OMP_IF_END:%.*]]
7732 // CHECK23: omp_if.else:
7733 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
7734 // CHECK23: omp.inner.for.cond13:
7735 // CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7736 // CHECK23-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7737 // CHECK23-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
7738 // CHECK23-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
7739 // CHECK23: omp.inner.for.body15:
7740 // CHECK23-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7741 // CHECK23-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
7742 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7743 // CHECK23-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
7744 // CHECK23-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
7745 // CHECK23-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
7746 // CHECK23-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
7747 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
7748 // CHECK23: omp.body.continue20:
7749 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
7750 // CHECK23: omp.inner.for.inc21:
7751 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7752 // CHECK23-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
7753 // CHECK23-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
7754 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP26:![0-9]+]]
7755 // CHECK23: omp.inner.for.end23:
7756 // CHECK23-NEXT: br label [[OMP_IF_END]]
7757 // CHECK23: omp_if.end:
7758 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
7759 // CHECK23: omp.loop.exit:
7760 // CHECK23-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7761 // CHECK23-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
7762 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
7763 // CHECK23-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7764 // CHECK23-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
7765 // CHECK23-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7766 // CHECK23: .omp.final.then:
7767 // CHECK23-NEXT: [[TMP29:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7768 // CHECK23-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32
7769 // CHECK23-NEXT: [[TMP30:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7770 // CHECK23-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32
7771 // CHECK23-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
7772 // CHECK23-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
7773 // CHECK23-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
7774 // CHECK23-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
7775 // CHECK23-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
7776 // CHECK23-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
7777 // CHECK23-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
7778 // CHECK23-NEXT: store i8 [[CONV32]], i8* [[TMP0]], align 1
7779 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]
7780 // CHECK23: .omp.final.done:
7781 // CHECK23-NEXT: br label [[OMP_PRECOND_END]]
7782 // CHECK23: omp.precond.end:
7783 // CHECK23-NEXT: ret void
7784 //
7785 //
7786 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
7787 // CHECK23-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] {
7788 // CHECK23-NEXT: entry:
7789 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7790 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7791 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7792 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]])
7793 // CHECK23-NEXT: ret void
7794 //
7795 //
7796 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4
7797 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
7798 // CHECK23-NEXT: entry:
7799 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7800 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7801 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4
7802 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7803 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4
7804 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7805 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7806 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7807 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7808 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4
7809 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7810 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7811 // CHECK23-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
7812 // CHECK23-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
7813 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7814 // CHECK23-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
7815 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7816 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7817 // CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
7818 // CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
7819 // CHECK23-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7820 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
7821 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
7822 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
7823 // CHECK23: omp.dispatch.cond:
7824 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7825 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
7826 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7827 // CHECK23: cond.true:
7828 // CHECK23-NEXT: br label [[COND_END:%.*]]
7829 // CHECK23: cond.false:
7830 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7831 // CHECK23-NEXT: br label [[COND_END]]
7832 // CHECK23: cond.end:
7833 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
7834 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7835 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7836 // CHECK23-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
7837 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7838 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7839 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
7840 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
7841 // CHECK23: omp.dispatch.body:
7842 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7843 // CHECK23: omp.inner.for.cond:
7844 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
7845 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28
7846 // CHECK23-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
7847 // CHECK23-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7848 // CHECK23: omp.inner.for.body:
7849 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
7850 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
7851 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7852 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28
7853 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7854 // CHECK23: omp.body.continue:
7855 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7856 // CHECK23: omp.inner.for.inc:
7857 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
7858 // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
7859 // CHECK23-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
7860 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
7861 // CHECK23: omp.inner.for.end:
7862 // CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
7863 // CHECK23: omp.dispatch.inc:
7864 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7865 // CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
7866 // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
7867 // CHECK23-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
7868 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7869 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
7870 // CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
7871 // CHECK23-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
7872 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND]]
7873 // CHECK23: omp.dispatch.end:
7874 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
7875 // CHECK23-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7876 // CHECK23-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
7877 // CHECK23-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7878 // CHECK23: .omp.final.then:
7879 // CHECK23-NEXT: store i32 100, i32* [[I]], align 4
7880 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]
7881 // CHECK23: .omp.final.done:
7882 // CHECK23-NEXT: ret void
7883 //
7884