1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
4
5 #include <riscv_vector.h>
6
7 // CHECK-RV64-LABEL: @test_vmseq_vv_i8mf8_b64(
8 // CHECK-RV64-NEXT: entry:
9 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
10 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
11 //
test_vmseq_vv_i8mf8_b64(vint8mf8_t op1,vint8mf8_t op2,size_t vl)12 vbool64_t test_vmseq_vv_i8mf8_b64(vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
13 return vmseq_vv_i8mf8_b64(op1, op2, vl);
14 }
15
16 // CHECK-RV64-LABEL: @test_vmseq_vx_i8mf8_b64(
17 // CHECK-RV64-NEXT: entry:
18 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
19 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
20 //
test_vmseq_vx_i8mf8_b64(vint8mf8_t op1,int8_t op2,size_t vl)21 vbool64_t test_vmseq_vx_i8mf8_b64(vint8mf8_t op1, int8_t op2, size_t vl) {
22 return vmseq_vx_i8mf8_b64(op1, op2, vl);
23 }
24
25 // CHECK-RV64-LABEL: @test_vmseq_vv_i8mf4_b32(
26 // CHECK-RV64-NEXT: entry:
27 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
28 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
29 //
test_vmseq_vv_i8mf4_b32(vint8mf4_t op1,vint8mf4_t op2,size_t vl)30 vbool32_t test_vmseq_vv_i8mf4_b32(vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
31 return vmseq_vv_i8mf4_b32(op1, op2, vl);
32 }
33
34 // CHECK-RV64-LABEL: @test_vmseq_vx_i8mf4_b32(
35 // CHECK-RV64-NEXT: entry:
36 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
37 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
38 //
test_vmseq_vx_i8mf4_b32(vint8mf4_t op1,int8_t op2,size_t vl)39 vbool32_t test_vmseq_vx_i8mf4_b32(vint8mf4_t op1, int8_t op2, size_t vl) {
40 return vmseq_vx_i8mf4_b32(op1, op2, vl);
41 }
42
43 // CHECK-RV64-LABEL: @test_vmseq_vv_i8mf2_b16(
44 // CHECK-RV64-NEXT: entry:
45 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
46 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
47 //
test_vmseq_vv_i8mf2_b16(vint8mf2_t op1,vint8mf2_t op2,size_t vl)48 vbool16_t test_vmseq_vv_i8mf2_b16(vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
49 return vmseq_vv_i8mf2_b16(op1, op2, vl);
50 }
51
52 // CHECK-RV64-LABEL: @test_vmseq_vx_i8mf2_b16(
53 // CHECK-RV64-NEXT: entry:
54 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
55 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
56 //
test_vmseq_vx_i8mf2_b16(vint8mf2_t op1,int8_t op2,size_t vl)57 vbool16_t test_vmseq_vx_i8mf2_b16(vint8mf2_t op1, int8_t op2, size_t vl) {
58 return vmseq_vx_i8mf2_b16(op1, op2, vl);
59 }
60
61 // CHECK-RV64-LABEL: @test_vmseq_vv_i8m1_b8(
62 // CHECK-RV64-NEXT: entry:
63 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
64 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
65 //
test_vmseq_vv_i8m1_b8(vint8m1_t op1,vint8m1_t op2,size_t vl)66 vbool8_t test_vmseq_vv_i8m1_b8(vint8m1_t op1, vint8m1_t op2, size_t vl) {
67 return vmseq_vv_i8m1_b8(op1, op2, vl);
68 }
69
70 // CHECK-RV64-LABEL: @test_vmseq_vx_i8m1_b8(
71 // CHECK-RV64-NEXT: entry:
72 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
73 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
74 //
test_vmseq_vx_i8m1_b8(vint8m1_t op1,int8_t op2,size_t vl)75 vbool8_t test_vmseq_vx_i8m1_b8(vint8m1_t op1, int8_t op2, size_t vl) {
76 return vmseq_vx_i8m1_b8(op1, op2, vl);
77 }
78
79 // CHECK-RV64-LABEL: @test_vmseq_vv_i8m2_b4(
80 // CHECK-RV64-NEXT: entry:
81 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
82 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
83 //
test_vmseq_vv_i8m2_b4(vint8m2_t op1,vint8m2_t op2,size_t vl)84 vbool4_t test_vmseq_vv_i8m2_b4(vint8m2_t op1, vint8m2_t op2, size_t vl) {
85 return vmseq_vv_i8m2_b4(op1, op2, vl);
86 }
87
88 // CHECK-RV64-LABEL: @test_vmseq_vx_i8m2_b4(
89 // CHECK-RV64-NEXT: entry:
90 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
91 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
92 //
test_vmseq_vx_i8m2_b4(vint8m2_t op1,int8_t op2,size_t vl)93 vbool4_t test_vmseq_vx_i8m2_b4(vint8m2_t op1, int8_t op2, size_t vl) {
94 return vmseq_vx_i8m2_b4(op1, op2, vl);
95 }
96
97 // CHECK-RV64-LABEL: @test_vmseq_vv_i8m4_b2(
98 // CHECK-RV64-NEXT: entry:
99 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
100 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
101 //
test_vmseq_vv_i8m4_b2(vint8m4_t op1,vint8m4_t op2,size_t vl)102 vbool2_t test_vmseq_vv_i8m4_b2(vint8m4_t op1, vint8m4_t op2, size_t vl) {
103 return vmseq_vv_i8m4_b2(op1, op2, vl);
104 }
105
106 // CHECK-RV64-LABEL: @test_vmseq_vx_i8m4_b2(
107 // CHECK-RV64-NEXT: entry:
108 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.i8.i64(<vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
109 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
110 //
test_vmseq_vx_i8m4_b2(vint8m4_t op1,int8_t op2,size_t vl)111 vbool2_t test_vmseq_vx_i8m4_b2(vint8m4_t op1, int8_t op2, size_t vl) {
112 return vmseq_vx_i8m4_b2(op1, op2, vl);
113 }
114
115 // CHECK-RV64-LABEL: @test_vmseq_vv_i8m8_b1(
116 // CHECK-RV64-NEXT: entry:
117 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmseq.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
118 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
119 //
test_vmseq_vv_i8m8_b1(vint8m8_t op1,vint8m8_t op2,size_t vl)120 vbool1_t test_vmseq_vv_i8m8_b1(vint8m8_t op1, vint8m8_t op2, size_t vl) {
121 return vmseq_vv_i8m8_b1(op1, op2, vl);
122 }
123
124 // CHECK-RV64-LABEL: @test_vmseq_vx_i8m8_b1(
125 // CHECK-RV64-NEXT: entry:
126 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmseq.nxv64i8.i8.i64(<vscale x 64 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
127 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
128 //
test_vmseq_vx_i8m8_b1(vint8m8_t op1,int8_t op2,size_t vl)129 vbool1_t test_vmseq_vx_i8m8_b1(vint8m8_t op1, int8_t op2, size_t vl) {
130 return vmseq_vx_i8m8_b1(op1, op2, vl);
131 }
132
133 // CHECK-RV64-LABEL: @test_vmseq_vv_i16mf4_b64(
134 // CHECK-RV64-NEXT: entry:
135 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
136 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
137 //
test_vmseq_vv_i16mf4_b64(vint16mf4_t op1,vint16mf4_t op2,size_t vl)138 vbool64_t test_vmseq_vv_i16mf4_b64(vint16mf4_t op1, vint16mf4_t op2,
139 size_t vl) {
140 return vmseq_vv_i16mf4_b64(op1, op2, vl);
141 }
142
143 // CHECK-RV64-LABEL: @test_vmseq_vx_i16mf4_b64(
144 // CHECK-RV64-NEXT: entry:
145 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16.i16.i64(<vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
146 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
147 //
test_vmseq_vx_i16mf4_b64(vint16mf4_t op1,int16_t op2,size_t vl)148 vbool64_t test_vmseq_vx_i16mf4_b64(vint16mf4_t op1, int16_t op2, size_t vl) {
149 return vmseq_vx_i16mf4_b64(op1, op2, vl);
150 }
151
152 // CHECK-RV64-LABEL: @test_vmseq_vv_i16mf2_b32(
153 // CHECK-RV64-NEXT: entry:
154 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
155 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
156 //
test_vmseq_vv_i16mf2_b32(vint16mf2_t op1,vint16mf2_t op2,size_t vl)157 vbool32_t test_vmseq_vv_i16mf2_b32(vint16mf2_t op1, vint16mf2_t op2,
158 size_t vl) {
159 return vmseq_vv_i16mf2_b32(op1, op2, vl);
160 }
161
162 // CHECK-RV64-LABEL: @test_vmseq_vx_i16mf2_b32(
163 // CHECK-RV64-NEXT: entry:
164 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16.i16.i64(<vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
165 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
166 //
test_vmseq_vx_i16mf2_b32(vint16mf2_t op1,int16_t op2,size_t vl)167 vbool32_t test_vmseq_vx_i16mf2_b32(vint16mf2_t op1, int16_t op2, size_t vl) {
168 return vmseq_vx_i16mf2_b32(op1, op2, vl);
169 }
170
171 // CHECK-RV64-LABEL: @test_vmseq_vv_i16m1_b16(
172 // CHECK-RV64-NEXT: entry:
173 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
174 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
175 //
test_vmseq_vv_i16m1_b16(vint16m1_t op1,vint16m1_t op2,size_t vl)176 vbool16_t test_vmseq_vv_i16m1_b16(vint16m1_t op1, vint16m1_t op2, size_t vl) {
177 return vmseq_vv_i16m1_b16(op1, op2, vl);
178 }
179
180 // CHECK-RV64-LABEL: @test_vmseq_vx_i16m1_b16(
181 // CHECK-RV64-NEXT: entry:
182 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16.i16.i64(<vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
183 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
184 //
test_vmseq_vx_i16m1_b16(vint16m1_t op1,int16_t op2,size_t vl)185 vbool16_t test_vmseq_vx_i16m1_b16(vint16m1_t op1, int16_t op2, size_t vl) {
186 return vmseq_vx_i16m1_b16(op1, op2, vl);
187 }
188
189 // CHECK-RV64-LABEL: @test_vmseq_vv_i16m2_b8(
190 // CHECK-RV64-NEXT: entry:
191 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
192 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
193 //
test_vmseq_vv_i16m2_b8(vint16m2_t op1,vint16m2_t op2,size_t vl)194 vbool8_t test_vmseq_vv_i16m2_b8(vint16m2_t op1, vint16m2_t op2, size_t vl) {
195 return vmseq_vv_i16m2_b8(op1, op2, vl);
196 }
197
198 // CHECK-RV64-LABEL: @test_vmseq_vx_i16m2_b8(
199 // CHECK-RV64-NEXT: entry:
200 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16.i16.i64(<vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
201 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
202 //
test_vmseq_vx_i16m2_b8(vint16m2_t op1,int16_t op2,size_t vl)203 vbool8_t test_vmseq_vx_i16m2_b8(vint16m2_t op1, int16_t op2, size_t vl) {
204 return vmseq_vx_i16m2_b8(op1, op2, vl);
205 }
206
207 // CHECK-RV64-LABEL: @test_vmseq_vv_i16m4_b4(
208 // CHECK-RV64-NEXT: entry:
209 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
210 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
211 //
test_vmseq_vv_i16m4_b4(vint16m4_t op1,vint16m4_t op2,size_t vl)212 vbool4_t test_vmseq_vv_i16m4_b4(vint16m4_t op1, vint16m4_t op2, size_t vl) {
213 return vmseq_vv_i16m4_b4(op1, op2, vl);
214 }
215
216 // CHECK-RV64-LABEL: @test_vmseq_vx_i16m4_b4(
217 // CHECK-RV64-NEXT: entry:
218 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16.i16.i64(<vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
219 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
220 //
test_vmseq_vx_i16m4_b4(vint16m4_t op1,int16_t op2,size_t vl)221 vbool4_t test_vmseq_vx_i16m4_b4(vint16m4_t op1, int16_t op2, size_t vl) {
222 return vmseq_vx_i16m4_b4(op1, op2, vl);
223 }
224
225 // CHECK-RV64-LABEL: @test_vmseq_vv_i16m8_b2(
226 // CHECK-RV64-NEXT: entry:
227 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
228 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
229 //
test_vmseq_vv_i16m8_b2(vint16m8_t op1,vint16m8_t op2,size_t vl)230 vbool2_t test_vmseq_vv_i16m8_b2(vint16m8_t op1, vint16m8_t op2, size_t vl) {
231 return vmseq_vv_i16m8_b2(op1, op2, vl);
232 }
233
234 // CHECK-RV64-LABEL: @test_vmseq_vx_i16m8_b2(
235 // CHECK-RV64-NEXT: entry:
236 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i16.i16.i64(<vscale x 32 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
237 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
238 //
test_vmseq_vx_i16m8_b2(vint16m8_t op1,int16_t op2,size_t vl)239 vbool2_t test_vmseq_vx_i16m8_b2(vint16m8_t op1, int16_t op2, size_t vl) {
240 return vmseq_vx_i16m8_b2(op1, op2, vl);
241 }
242
243 // CHECK-RV64-LABEL: @test_vmseq_vv_i32mf2_b64(
244 // CHECK-RV64-NEXT: entry:
245 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
246 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
247 //
test_vmseq_vv_i32mf2_b64(vint32mf2_t op1,vint32mf2_t op2,size_t vl)248 vbool64_t test_vmseq_vv_i32mf2_b64(vint32mf2_t op1, vint32mf2_t op2,
249 size_t vl) {
250 return vmseq_vv_i32mf2_b64(op1, op2, vl);
251 }
252
253 // CHECK-RV64-LABEL: @test_vmseq_vx_i32mf2_b64(
254 // CHECK-RV64-NEXT: entry:
255 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32.i32.i64(<vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
256 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
257 //
test_vmseq_vx_i32mf2_b64(vint32mf2_t op1,int32_t op2,size_t vl)258 vbool64_t test_vmseq_vx_i32mf2_b64(vint32mf2_t op1, int32_t op2, size_t vl) {
259 return vmseq_vx_i32mf2_b64(op1, op2, vl);
260 }
261
262 // CHECK-RV64-LABEL: @test_vmseq_vv_i32m1_b32(
263 // CHECK-RV64-NEXT: entry:
264 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
265 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
266 //
test_vmseq_vv_i32m1_b32(vint32m1_t op1,vint32m1_t op2,size_t vl)267 vbool32_t test_vmseq_vv_i32m1_b32(vint32m1_t op1, vint32m1_t op2, size_t vl) {
268 return vmseq_vv_i32m1_b32(op1, op2, vl);
269 }
270
271 // CHECK-RV64-LABEL: @test_vmseq_vx_i32m1_b32(
272 // CHECK-RV64-NEXT: entry:
273 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32.i32.i64(<vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
274 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
275 //
test_vmseq_vx_i32m1_b32(vint32m1_t op1,int32_t op2,size_t vl)276 vbool32_t test_vmseq_vx_i32m1_b32(vint32m1_t op1, int32_t op2, size_t vl) {
277 return vmseq_vx_i32m1_b32(op1, op2, vl);
278 }
279
280 // CHECK-RV64-LABEL: @test_vmseq_vv_i32m2_b16(
281 // CHECK-RV64-NEXT: entry:
282 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
283 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
284 //
test_vmseq_vv_i32m2_b16(vint32m2_t op1,vint32m2_t op2,size_t vl)285 vbool16_t test_vmseq_vv_i32m2_b16(vint32m2_t op1, vint32m2_t op2, size_t vl) {
286 return vmseq_vv_i32m2_b16(op1, op2, vl);
287 }
288
289 // CHECK-RV64-LABEL: @test_vmseq_vx_i32m2_b16(
290 // CHECK-RV64-NEXT: entry:
291 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32.i32.i64(<vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
292 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
293 //
test_vmseq_vx_i32m2_b16(vint32m2_t op1,int32_t op2,size_t vl)294 vbool16_t test_vmseq_vx_i32m2_b16(vint32m2_t op1, int32_t op2, size_t vl) {
295 return vmseq_vx_i32m2_b16(op1, op2, vl);
296 }
297
298 // CHECK-RV64-LABEL: @test_vmseq_vv_i32m4_b8(
299 // CHECK-RV64-NEXT: entry:
300 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
301 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
302 //
test_vmseq_vv_i32m4_b8(vint32m4_t op1,vint32m4_t op2,size_t vl)303 vbool8_t test_vmseq_vv_i32m4_b8(vint32m4_t op1, vint32m4_t op2, size_t vl) {
304 return vmseq_vv_i32m4_b8(op1, op2, vl);
305 }
306
307 // CHECK-RV64-LABEL: @test_vmseq_vx_i32m4_b8(
308 // CHECK-RV64-NEXT: entry:
309 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32.i32.i64(<vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
310 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
311 //
test_vmseq_vx_i32m4_b8(vint32m4_t op1,int32_t op2,size_t vl)312 vbool8_t test_vmseq_vx_i32m4_b8(vint32m4_t op1, int32_t op2, size_t vl) {
313 return vmseq_vx_i32m4_b8(op1, op2, vl);
314 }
315
316 // CHECK-RV64-LABEL: @test_vmseq_vv_i32m8_b4(
317 // CHECK-RV64-NEXT: entry:
318 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
319 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
320 //
test_vmseq_vv_i32m8_b4(vint32m8_t op1,vint32m8_t op2,size_t vl)321 vbool4_t test_vmseq_vv_i32m8_b4(vint32m8_t op1, vint32m8_t op2, size_t vl) {
322 return vmseq_vv_i32m8_b4(op1, op2, vl);
323 }
324
325 // CHECK-RV64-LABEL: @test_vmseq_vx_i32m8_b4(
326 // CHECK-RV64-NEXT: entry:
327 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i32.i32.i64(<vscale x 16 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
328 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
329 //
test_vmseq_vx_i32m8_b4(vint32m8_t op1,int32_t op2,size_t vl)330 vbool4_t test_vmseq_vx_i32m8_b4(vint32m8_t op1, int32_t op2, size_t vl) {
331 return vmseq_vx_i32m8_b4(op1, op2, vl);
332 }
333
334 // CHECK-RV64-LABEL: @test_vmseq_vv_i64m1_b64(
335 // CHECK-RV64-NEXT: entry:
336 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 [[VL:%.*]])
337 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
338 //
test_vmseq_vv_i64m1_b64(vint64m1_t op1,vint64m1_t op2,size_t vl)339 vbool64_t test_vmseq_vv_i64m1_b64(vint64m1_t op1, vint64m1_t op2, size_t vl) {
340 return vmseq_vv_i64m1_b64(op1, op2, vl);
341 }
342
343 // CHECK-RV64-LABEL: @test_vmseq_vx_i64m1_b64(
344 // CHECK-RV64-NEXT: entry:
345 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64.i64(<vscale x 1 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]])
346 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
347 //
test_vmseq_vx_i64m1_b64(vint64m1_t op1,int64_t op2,size_t vl)348 vbool64_t test_vmseq_vx_i64m1_b64(vint64m1_t op1, int64_t op2, size_t vl) {
349 return vmseq_vx_i64m1_b64(op1, op2, vl);
350 }
351
352 // CHECK-RV64-LABEL: @test_vmseq_vv_i64m2_b32(
353 // CHECK-RV64-NEXT: entry:
354 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 [[VL:%.*]])
355 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
356 //
test_vmseq_vv_i64m2_b32(vint64m2_t op1,vint64m2_t op2,size_t vl)357 vbool32_t test_vmseq_vv_i64m2_b32(vint64m2_t op1, vint64m2_t op2, size_t vl) {
358 return vmseq_vv_i64m2_b32(op1, op2, vl);
359 }
360
361 // CHECK-RV64-LABEL: @test_vmseq_vx_i64m2_b32(
362 // CHECK-RV64-NEXT: entry:
363 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64.i64.i64(<vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]])
364 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
365 //
test_vmseq_vx_i64m2_b32(vint64m2_t op1,int64_t op2,size_t vl)366 vbool32_t test_vmseq_vx_i64m2_b32(vint64m2_t op1, int64_t op2, size_t vl) {
367 return vmseq_vx_i64m2_b32(op1, op2, vl);
368 }
369
370 // CHECK-RV64-LABEL: @test_vmseq_vv_i64m4_b16(
371 // CHECK-RV64-NEXT: entry:
372 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 [[VL:%.*]])
373 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
374 //
test_vmseq_vv_i64m4_b16(vint64m4_t op1,vint64m4_t op2,size_t vl)375 vbool16_t test_vmseq_vv_i64m4_b16(vint64m4_t op1, vint64m4_t op2, size_t vl) {
376 return vmseq_vv_i64m4_b16(op1, op2, vl);
377 }
378
379 // CHECK-RV64-LABEL: @test_vmseq_vx_i64m4_b16(
380 // CHECK-RV64-NEXT: entry:
381 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64.i64.i64(<vscale x 4 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]])
382 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
383 //
test_vmseq_vx_i64m4_b16(vint64m4_t op1,int64_t op2,size_t vl)384 vbool16_t test_vmseq_vx_i64m4_b16(vint64m4_t op1, int64_t op2, size_t vl) {
385 return vmseq_vx_i64m4_b16(op1, op2, vl);
386 }
387
388 // CHECK-RV64-LABEL: @test_vmseq_vv_i64m8_b8(
389 // CHECK-RV64-NEXT: entry:
390 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 [[VL:%.*]])
391 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
392 //
test_vmseq_vv_i64m8_b8(vint64m8_t op1,vint64m8_t op2,size_t vl)393 vbool8_t test_vmseq_vv_i64m8_b8(vint64m8_t op1, vint64m8_t op2, size_t vl) {
394 return vmseq_vv_i64m8_b8(op1, op2, vl);
395 }
396
397 // CHECK-RV64-LABEL: @test_vmseq_vx_i64m8_b8(
398 // CHECK-RV64-NEXT: entry:
399 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i64.i64.i64(<vscale x 8 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]])
400 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
401 //
test_vmseq_vx_i64m8_b8(vint64m8_t op1,int64_t op2,size_t vl)402 vbool8_t test_vmseq_vx_i64m8_b8(vint64m8_t op1, int64_t op2, size_t vl) {
403 return vmseq_vx_i64m8_b8(op1, op2, vl);
404 }
405
406 // CHECK-RV64-LABEL: @test_vmseq_vv_u8mf8_b64(
407 // CHECK-RV64-NEXT: entry:
408 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
409 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
410 //
test_vmseq_vv_u8mf8_b64(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)411 vbool64_t test_vmseq_vv_u8mf8_b64(vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
412 return vmseq_vv_u8mf8_b64(op1, op2, vl);
413 }
414
415 // CHECK-RV64-LABEL: @test_vmseq_vx_u8mf8_b64(
416 // CHECK-RV64-NEXT: entry:
417 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
418 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
419 //
test_vmseq_vx_u8mf8_b64(vuint8mf8_t op1,uint8_t op2,size_t vl)420 vbool64_t test_vmseq_vx_u8mf8_b64(vuint8mf8_t op1, uint8_t op2, size_t vl) {
421 return vmseq_vx_u8mf8_b64(op1, op2, vl);
422 }
423
424 // CHECK-RV64-LABEL: @test_vmseq_vv_u8mf4_b32(
425 // CHECK-RV64-NEXT: entry:
426 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
427 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
428 //
test_vmseq_vv_u8mf4_b32(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)429 vbool32_t test_vmseq_vv_u8mf4_b32(vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
430 return vmseq_vv_u8mf4_b32(op1, op2, vl);
431 }
432
433 // CHECK-RV64-LABEL: @test_vmseq_vx_u8mf4_b32(
434 // CHECK-RV64-NEXT: entry:
435 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
436 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
437 //
test_vmseq_vx_u8mf4_b32(vuint8mf4_t op1,uint8_t op2,size_t vl)438 vbool32_t test_vmseq_vx_u8mf4_b32(vuint8mf4_t op1, uint8_t op2, size_t vl) {
439 return vmseq_vx_u8mf4_b32(op1, op2, vl);
440 }
441
442 // CHECK-RV64-LABEL: @test_vmseq_vv_u8mf2_b16(
443 // CHECK-RV64-NEXT: entry:
444 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
445 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
446 //
test_vmseq_vv_u8mf2_b16(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)447 vbool16_t test_vmseq_vv_u8mf2_b16(vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
448 return vmseq_vv_u8mf2_b16(op1, op2, vl);
449 }
450
451 // CHECK-RV64-LABEL: @test_vmseq_vx_u8mf2_b16(
452 // CHECK-RV64-NEXT: entry:
453 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
454 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
455 //
test_vmseq_vx_u8mf2_b16(vuint8mf2_t op1,uint8_t op2,size_t vl)456 vbool16_t test_vmseq_vx_u8mf2_b16(vuint8mf2_t op1, uint8_t op2, size_t vl) {
457 return vmseq_vx_u8mf2_b16(op1, op2, vl);
458 }
459
460 // CHECK-RV64-LABEL: @test_vmseq_vv_u8m1_b8(
461 // CHECK-RV64-NEXT: entry:
462 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
463 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
464 //
test_vmseq_vv_u8m1_b8(vuint8m1_t op1,vuint8m1_t op2,size_t vl)465 vbool8_t test_vmseq_vv_u8m1_b8(vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
466 return vmseq_vv_u8m1_b8(op1, op2, vl);
467 }
468
469 // CHECK-RV64-LABEL: @test_vmseq_vx_u8m1_b8(
470 // CHECK-RV64-NEXT: entry:
471 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
472 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
473 //
test_vmseq_vx_u8m1_b8(vuint8m1_t op1,uint8_t op2,size_t vl)474 vbool8_t test_vmseq_vx_u8m1_b8(vuint8m1_t op1, uint8_t op2, size_t vl) {
475 return vmseq_vx_u8m1_b8(op1, op2, vl);
476 }
477
478 // CHECK-RV64-LABEL: @test_vmseq_vv_u8m2_b4(
479 // CHECK-RV64-NEXT: entry:
480 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
481 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
482 //
test_vmseq_vv_u8m2_b4(vuint8m2_t op1,vuint8m2_t op2,size_t vl)483 vbool4_t test_vmseq_vv_u8m2_b4(vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
484 return vmseq_vv_u8m2_b4(op1, op2, vl);
485 }
486
487 // CHECK-RV64-LABEL: @test_vmseq_vx_u8m2_b4(
488 // CHECK-RV64-NEXT: entry:
489 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
490 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
491 //
test_vmseq_vx_u8m2_b4(vuint8m2_t op1,uint8_t op2,size_t vl)492 vbool4_t test_vmseq_vx_u8m2_b4(vuint8m2_t op1, uint8_t op2, size_t vl) {
493 return vmseq_vx_u8m2_b4(op1, op2, vl);
494 }
495
496 // CHECK-RV64-LABEL: @test_vmseq_vv_u8m4_b2(
497 // CHECK-RV64-NEXT: entry:
498 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
499 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
500 //
test_vmseq_vv_u8m4_b2(vuint8m4_t op1,vuint8m4_t op2,size_t vl)501 vbool2_t test_vmseq_vv_u8m4_b2(vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
502 return vmseq_vv_u8m4_b2(op1, op2, vl);
503 }
504
505 // CHECK-RV64-LABEL: @test_vmseq_vx_u8m4_b2(
506 // CHECK-RV64-NEXT: entry:
507 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.i8.i64(<vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
508 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
509 //
test_vmseq_vx_u8m4_b2(vuint8m4_t op1,uint8_t op2,size_t vl)510 vbool2_t test_vmseq_vx_u8m4_b2(vuint8m4_t op1, uint8_t op2, size_t vl) {
511 return vmseq_vx_u8m4_b2(op1, op2, vl);
512 }
513
514 // CHECK-RV64-LABEL: @test_vmseq_vv_u8m8_b1(
515 // CHECK-RV64-NEXT: entry:
516 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmseq.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
517 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
518 //
test_vmseq_vv_u8m8_b1(vuint8m8_t op1,vuint8m8_t op2,size_t vl)519 vbool1_t test_vmseq_vv_u8m8_b1(vuint8m8_t op1, vuint8m8_t op2, size_t vl) {
520 return vmseq_vv_u8m8_b1(op1, op2, vl);
521 }
522
523 // CHECK-RV64-LABEL: @test_vmseq_vx_u8m8_b1(
524 // CHECK-RV64-NEXT: entry:
525 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmseq.nxv64i8.i8.i64(<vscale x 64 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
526 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
527 //
test_vmseq_vx_u8m8_b1(vuint8m8_t op1,uint8_t op2,size_t vl)528 vbool1_t test_vmseq_vx_u8m8_b1(vuint8m8_t op1, uint8_t op2, size_t vl) {
529 return vmseq_vx_u8m8_b1(op1, op2, vl);
530 }
531
532 // CHECK-RV64-LABEL: @test_vmseq_vv_u16mf4_b64(
533 // CHECK-RV64-NEXT: entry:
534 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
535 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
536 //
test_vmseq_vv_u16mf4_b64(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)537 vbool64_t test_vmseq_vv_u16mf4_b64(vuint16mf4_t op1, vuint16mf4_t op2,
538 size_t vl) {
539 return vmseq_vv_u16mf4_b64(op1, op2, vl);
540 }
541
542 // CHECK-RV64-LABEL: @test_vmseq_vx_u16mf4_b64(
543 // CHECK-RV64-NEXT: entry:
544 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16.i16.i64(<vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
545 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
546 //
test_vmseq_vx_u16mf4_b64(vuint16mf4_t op1,uint16_t op2,size_t vl)547 vbool64_t test_vmseq_vx_u16mf4_b64(vuint16mf4_t op1, uint16_t op2, size_t vl) {
548 return vmseq_vx_u16mf4_b64(op1, op2, vl);
549 }
550
551 // CHECK-RV64-LABEL: @test_vmseq_vv_u16mf2_b32(
552 // CHECK-RV64-NEXT: entry:
553 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
554 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
555 //
test_vmseq_vv_u16mf2_b32(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)556 vbool32_t test_vmseq_vv_u16mf2_b32(vuint16mf2_t op1, vuint16mf2_t op2,
557 size_t vl) {
558 return vmseq_vv_u16mf2_b32(op1, op2, vl);
559 }
560
561 // CHECK-RV64-LABEL: @test_vmseq_vx_u16mf2_b32(
562 // CHECK-RV64-NEXT: entry:
563 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16.i16.i64(<vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
564 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
565 //
test_vmseq_vx_u16mf2_b32(vuint16mf2_t op1,uint16_t op2,size_t vl)566 vbool32_t test_vmseq_vx_u16mf2_b32(vuint16mf2_t op1, uint16_t op2, size_t vl) {
567 return vmseq_vx_u16mf2_b32(op1, op2, vl);
568 }
569
570 // CHECK-RV64-LABEL: @test_vmseq_vv_u16m1_b16(
571 // CHECK-RV64-NEXT: entry:
572 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
573 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
574 //
test_vmseq_vv_u16m1_b16(vuint16m1_t op1,vuint16m1_t op2,size_t vl)575 vbool16_t test_vmseq_vv_u16m1_b16(vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
576 return vmseq_vv_u16m1_b16(op1, op2, vl);
577 }
578
579 // CHECK-RV64-LABEL: @test_vmseq_vx_u16m1_b16(
580 // CHECK-RV64-NEXT: entry:
581 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16.i16.i64(<vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
582 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
583 //
test_vmseq_vx_u16m1_b16(vuint16m1_t op1,uint16_t op2,size_t vl)584 vbool16_t test_vmseq_vx_u16m1_b16(vuint16m1_t op1, uint16_t op2, size_t vl) {
585 return vmseq_vx_u16m1_b16(op1, op2, vl);
586 }
587
588 // CHECK-RV64-LABEL: @test_vmseq_vv_u16m2_b8(
589 // CHECK-RV64-NEXT: entry:
590 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
591 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
592 //
test_vmseq_vv_u16m2_b8(vuint16m2_t op1,vuint16m2_t op2,size_t vl)593 vbool8_t test_vmseq_vv_u16m2_b8(vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
594 return vmseq_vv_u16m2_b8(op1, op2, vl);
595 }
596
597 // CHECK-RV64-LABEL: @test_vmseq_vx_u16m2_b8(
598 // CHECK-RV64-NEXT: entry:
599 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16.i16.i64(<vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
600 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
601 //
test_vmseq_vx_u16m2_b8(vuint16m2_t op1,uint16_t op2,size_t vl)602 vbool8_t test_vmseq_vx_u16m2_b8(vuint16m2_t op1, uint16_t op2, size_t vl) {
603 return vmseq_vx_u16m2_b8(op1, op2, vl);
604 }
605
606 // CHECK-RV64-LABEL: @test_vmseq_vv_u16m4_b4(
607 // CHECK-RV64-NEXT: entry:
608 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
609 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
610 //
test_vmseq_vv_u16m4_b4(vuint16m4_t op1,vuint16m4_t op2,size_t vl)611 vbool4_t test_vmseq_vv_u16m4_b4(vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
612 return vmseq_vv_u16m4_b4(op1, op2, vl);
613 }
614
615 // CHECK-RV64-LABEL: @test_vmseq_vx_u16m4_b4(
616 // CHECK-RV64-NEXT: entry:
617 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16.i16.i64(<vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
618 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
619 //
test_vmseq_vx_u16m4_b4(vuint16m4_t op1,uint16_t op2,size_t vl)620 vbool4_t test_vmseq_vx_u16m4_b4(vuint16m4_t op1, uint16_t op2, size_t vl) {
621 return vmseq_vx_u16m4_b4(op1, op2, vl);
622 }
623
624 // CHECK-RV64-LABEL: @test_vmseq_vv_u16m8_b2(
625 // CHECK-RV64-NEXT: entry:
626 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
627 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
628 //
test_vmseq_vv_u16m8_b2(vuint16m8_t op1,vuint16m8_t op2,size_t vl)629 vbool2_t test_vmseq_vv_u16m8_b2(vuint16m8_t op1, vuint16m8_t op2, size_t vl) {
630 return vmseq_vv_u16m8_b2(op1, op2, vl);
631 }
632
633 // CHECK-RV64-LABEL: @test_vmseq_vx_u16m8_b2(
634 // CHECK-RV64-NEXT: entry:
635 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i16.i16.i64(<vscale x 32 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
636 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
637 //
test_vmseq_vx_u16m8_b2(vuint16m8_t op1,uint16_t op2,size_t vl)638 vbool2_t test_vmseq_vx_u16m8_b2(vuint16m8_t op1, uint16_t op2, size_t vl) {
639 return vmseq_vx_u16m8_b2(op1, op2, vl);
640 }
641
642 // CHECK-RV64-LABEL: @test_vmseq_vv_u32mf2_b64(
643 // CHECK-RV64-NEXT: entry:
644 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
645 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
646 //
test_vmseq_vv_u32mf2_b64(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)647 vbool64_t test_vmseq_vv_u32mf2_b64(vuint32mf2_t op1, vuint32mf2_t op2,
648 size_t vl) {
649 return vmseq_vv_u32mf2_b64(op1, op2, vl);
650 }
651
652 // CHECK-RV64-LABEL: @test_vmseq_vx_u32mf2_b64(
653 // CHECK-RV64-NEXT: entry:
654 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32.i32.i64(<vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
655 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
656 //
test_vmseq_vx_u32mf2_b64(vuint32mf2_t op1,uint32_t op2,size_t vl)657 vbool64_t test_vmseq_vx_u32mf2_b64(vuint32mf2_t op1, uint32_t op2, size_t vl) {
658 return vmseq_vx_u32mf2_b64(op1, op2, vl);
659 }
660
661 // CHECK-RV64-LABEL: @test_vmseq_vv_u32m1_b32(
662 // CHECK-RV64-NEXT: entry:
663 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
664 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
665 //
test_vmseq_vv_u32m1_b32(vuint32m1_t op1,vuint32m1_t op2,size_t vl)666 vbool32_t test_vmseq_vv_u32m1_b32(vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
667 return vmseq_vv_u32m1_b32(op1, op2, vl);
668 }
669
670 // CHECK-RV64-LABEL: @test_vmseq_vx_u32m1_b32(
671 // CHECK-RV64-NEXT: entry:
672 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32.i32.i64(<vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
673 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
674 //
test_vmseq_vx_u32m1_b32(vuint32m1_t op1,uint32_t op2,size_t vl)675 vbool32_t test_vmseq_vx_u32m1_b32(vuint32m1_t op1, uint32_t op2, size_t vl) {
676 return vmseq_vx_u32m1_b32(op1, op2, vl);
677 }
678
679 // CHECK-RV64-LABEL: @test_vmseq_vv_u32m2_b16(
680 // CHECK-RV64-NEXT: entry:
681 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
682 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
683 //
test_vmseq_vv_u32m2_b16(vuint32m2_t op1,vuint32m2_t op2,size_t vl)684 vbool16_t test_vmseq_vv_u32m2_b16(vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
685 return vmseq_vv_u32m2_b16(op1, op2, vl);
686 }
687
688 // CHECK-RV64-LABEL: @test_vmseq_vx_u32m2_b16(
689 // CHECK-RV64-NEXT: entry:
690 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32.i32.i64(<vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
691 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
692 //
test_vmseq_vx_u32m2_b16(vuint32m2_t op1,uint32_t op2,size_t vl)693 vbool16_t test_vmseq_vx_u32m2_b16(vuint32m2_t op1, uint32_t op2, size_t vl) {
694 return vmseq_vx_u32m2_b16(op1, op2, vl);
695 }
696
697 // CHECK-RV64-LABEL: @test_vmseq_vv_u32m4_b8(
698 // CHECK-RV64-NEXT: entry:
699 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
700 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
701 //
test_vmseq_vv_u32m4_b8(vuint32m4_t op1,vuint32m4_t op2,size_t vl)702 vbool8_t test_vmseq_vv_u32m4_b8(vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
703 return vmseq_vv_u32m4_b8(op1, op2, vl);
704 }
705
706 // CHECK-RV64-LABEL: @test_vmseq_vx_u32m4_b8(
707 // CHECK-RV64-NEXT: entry:
708 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32.i32.i64(<vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
709 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
710 //
test_vmseq_vx_u32m4_b8(vuint32m4_t op1,uint32_t op2,size_t vl)711 vbool8_t test_vmseq_vx_u32m4_b8(vuint32m4_t op1, uint32_t op2, size_t vl) {
712 return vmseq_vx_u32m4_b8(op1, op2, vl);
713 }
714
715 // CHECK-RV64-LABEL: @test_vmseq_vv_u32m8_b4(
716 // CHECK-RV64-NEXT: entry:
717 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
718 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
719 //
test_vmseq_vv_u32m8_b4(vuint32m8_t op1,vuint32m8_t op2,size_t vl)720 vbool4_t test_vmseq_vv_u32m8_b4(vuint32m8_t op1, vuint32m8_t op2, size_t vl) {
721 return vmseq_vv_u32m8_b4(op1, op2, vl);
722 }
723
724 // CHECK-RV64-LABEL: @test_vmseq_vx_u32m8_b4(
725 // CHECK-RV64-NEXT: entry:
726 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i32.i32.i64(<vscale x 16 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
727 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
728 //
test_vmseq_vx_u32m8_b4(vuint32m8_t op1,uint32_t op2,size_t vl)729 vbool4_t test_vmseq_vx_u32m8_b4(vuint32m8_t op1, uint32_t op2, size_t vl) {
730 return vmseq_vx_u32m8_b4(op1, op2, vl);
731 }
732
733 // CHECK-RV64-LABEL: @test_vmseq_vv_u64m1_b64(
734 // CHECK-RV64-NEXT: entry:
735 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 [[VL:%.*]])
736 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
737 //
test_vmseq_vv_u64m1_b64(vuint64m1_t op1,vuint64m1_t op2,size_t vl)738 vbool64_t test_vmseq_vv_u64m1_b64(vuint64m1_t op1, vuint64m1_t op2, size_t vl) {
739 return vmseq_vv_u64m1_b64(op1, op2, vl);
740 }
741
742 // CHECK-RV64-LABEL: @test_vmseq_vx_u64m1_b64(
743 // CHECK-RV64-NEXT: entry:
744 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64.i64(<vscale x 1 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]])
745 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
746 //
test_vmseq_vx_u64m1_b64(vuint64m1_t op1,uint64_t op2,size_t vl)747 vbool64_t test_vmseq_vx_u64m1_b64(vuint64m1_t op1, uint64_t op2, size_t vl) {
748 return vmseq_vx_u64m1_b64(op1, op2, vl);
749 }
750
751 // CHECK-RV64-LABEL: @test_vmseq_vv_u64m2_b32(
752 // CHECK-RV64-NEXT: entry:
753 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 [[VL:%.*]])
754 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
755 //
test_vmseq_vv_u64m2_b32(vuint64m2_t op1,vuint64m2_t op2,size_t vl)756 vbool32_t test_vmseq_vv_u64m2_b32(vuint64m2_t op1, vuint64m2_t op2, size_t vl) {
757 return vmseq_vv_u64m2_b32(op1, op2, vl);
758 }
759
760 // CHECK-RV64-LABEL: @test_vmseq_vx_u64m2_b32(
761 // CHECK-RV64-NEXT: entry:
762 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64.i64.i64(<vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]])
763 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
764 //
test_vmseq_vx_u64m2_b32(vuint64m2_t op1,uint64_t op2,size_t vl)765 vbool32_t test_vmseq_vx_u64m2_b32(vuint64m2_t op1, uint64_t op2, size_t vl) {
766 return vmseq_vx_u64m2_b32(op1, op2, vl);
767 }
768
769 // CHECK-RV64-LABEL: @test_vmseq_vv_u64m4_b16(
770 // CHECK-RV64-NEXT: entry:
771 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 [[VL:%.*]])
772 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
773 //
test_vmseq_vv_u64m4_b16(vuint64m4_t op1,vuint64m4_t op2,size_t vl)774 vbool16_t test_vmseq_vv_u64m4_b16(vuint64m4_t op1, vuint64m4_t op2, size_t vl) {
775 return vmseq_vv_u64m4_b16(op1, op2, vl);
776 }
777
778 // CHECK-RV64-LABEL: @test_vmseq_vx_u64m4_b16(
779 // CHECK-RV64-NEXT: entry:
780 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64.i64.i64(<vscale x 4 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]])
781 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
782 //
test_vmseq_vx_u64m4_b16(vuint64m4_t op1,uint64_t op2,size_t vl)783 vbool16_t test_vmseq_vx_u64m4_b16(vuint64m4_t op1, uint64_t op2, size_t vl) {
784 return vmseq_vx_u64m4_b16(op1, op2, vl);
785 }
786
787 // CHECK-RV64-LABEL: @test_vmseq_vv_u64m8_b8(
788 // CHECK-RV64-NEXT: entry:
789 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 [[VL:%.*]])
790 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
791 //
test_vmseq_vv_u64m8_b8(vuint64m8_t op1,vuint64m8_t op2,size_t vl)792 vbool8_t test_vmseq_vv_u64m8_b8(vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
793 return vmseq_vv_u64m8_b8(op1, op2, vl);
794 }
795
796 // CHECK-RV64-LABEL: @test_vmseq_vx_u64m8_b8(
797 // CHECK-RV64-NEXT: entry:
798 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i64.i64.i64(<vscale x 8 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]])
799 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
800 //
test_vmseq_vx_u64m8_b8(vuint64m8_t op1,uint64_t op2,size_t vl)801 vbool8_t test_vmseq_vx_u64m8_b8(vuint64m8_t op1, uint64_t op2, size_t vl) {
802 return vmseq_vx_u64m8_b8(op1, op2, vl);
803 }
804
805 // CHECK-RV64-LABEL: @test_vmseq_vv_i8mf8_b64_m(
806 // CHECK-RV64-NEXT: entry:
807 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
808 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
809 //
test_vmseq_vv_i8mf8_b64_m(vbool64_t mask,vbool64_t maskedoff,vint8mf8_t op1,vint8mf8_t op2,size_t vl)810 vbool64_t test_vmseq_vv_i8mf8_b64_m(vbool64_t mask, vbool64_t maskedoff,
811 vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
812 return vmseq_vv_i8mf8_b64_m(mask, maskedoff, op1, op2, vl);
813 }
814
815 // CHECK-RV64-LABEL: @test_vmseq_vx_i8mf8_b64_m(
816 // CHECK-RV64-NEXT: entry:
817 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
818 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
819 //
test_vmseq_vx_i8mf8_b64_m(vbool64_t mask,vbool64_t maskedoff,vint8mf8_t op1,int8_t op2,size_t vl)820 vbool64_t test_vmseq_vx_i8mf8_b64_m(vbool64_t mask, vbool64_t maskedoff,
821 vint8mf8_t op1, int8_t op2, size_t vl) {
822 return vmseq_vx_i8mf8_b64_m(mask, maskedoff, op1, op2, vl);
823 }
824
825 // CHECK-RV64-LABEL: @test_vmseq_vv_i8mf4_b32_m(
826 // CHECK-RV64-NEXT: entry:
827 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
828 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
829 //
test_vmseq_vv_i8mf4_b32_m(vbool32_t mask,vbool32_t maskedoff,vint8mf4_t op1,vint8mf4_t op2,size_t vl)830 vbool32_t test_vmseq_vv_i8mf4_b32_m(vbool32_t mask, vbool32_t maskedoff,
831 vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
832 return vmseq_vv_i8mf4_b32_m(mask, maskedoff, op1, op2, vl);
833 }
834
835 // CHECK-RV64-LABEL: @test_vmseq_vx_i8mf4_b32_m(
836 // CHECK-RV64-NEXT: entry:
837 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
838 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
839 //
test_vmseq_vx_i8mf4_b32_m(vbool32_t mask,vbool32_t maskedoff,vint8mf4_t op1,int8_t op2,size_t vl)840 vbool32_t test_vmseq_vx_i8mf4_b32_m(vbool32_t mask, vbool32_t maskedoff,
841 vint8mf4_t op1, int8_t op2, size_t vl) {
842 return vmseq_vx_i8mf4_b32_m(mask, maskedoff, op1, op2, vl);
843 }
844
845 // CHECK-RV64-LABEL: @test_vmseq_vv_i8mf2_b16_m(
846 // CHECK-RV64-NEXT: entry:
847 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
848 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
849 //
test_vmseq_vv_i8mf2_b16_m(vbool16_t mask,vbool16_t maskedoff,vint8mf2_t op1,vint8mf2_t op2,size_t vl)850 vbool16_t test_vmseq_vv_i8mf2_b16_m(vbool16_t mask, vbool16_t maskedoff,
851 vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
852 return vmseq_vv_i8mf2_b16_m(mask, maskedoff, op1, op2, vl);
853 }
854
855 // CHECK-RV64-LABEL: @test_vmseq_vx_i8mf2_b16_m(
856 // CHECK-RV64-NEXT: entry:
857 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
858 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
859 //
test_vmseq_vx_i8mf2_b16_m(vbool16_t mask,vbool16_t maskedoff,vint8mf2_t op1,int8_t op2,size_t vl)860 vbool16_t test_vmseq_vx_i8mf2_b16_m(vbool16_t mask, vbool16_t maskedoff,
861 vint8mf2_t op1, int8_t op2, size_t vl) {
862 return vmseq_vx_i8mf2_b16_m(mask, maskedoff, op1, op2, vl);
863 }
864
865 // CHECK-RV64-LABEL: @test_vmseq_vv_i8m1_b8_m(
866 // CHECK-RV64-NEXT: entry:
867 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
868 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
869 //
test_vmseq_vv_i8m1_b8_m(vbool8_t mask,vbool8_t maskedoff,vint8m1_t op1,vint8m1_t op2,size_t vl)870 vbool8_t test_vmseq_vv_i8m1_b8_m(vbool8_t mask, vbool8_t maskedoff,
871 vint8m1_t op1, vint8m1_t op2, size_t vl) {
872 return vmseq_vv_i8m1_b8_m(mask, maskedoff, op1, op2, vl);
873 }
874
875 // CHECK-RV64-LABEL: @test_vmseq_vx_i8m1_b8_m(
876 // CHECK-RV64-NEXT: entry:
877 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
878 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
879 //
test_vmseq_vx_i8m1_b8_m(vbool8_t mask,vbool8_t maskedoff,vint8m1_t op1,int8_t op2,size_t vl)880 vbool8_t test_vmseq_vx_i8m1_b8_m(vbool8_t mask, vbool8_t maskedoff,
881 vint8m1_t op1, int8_t op2, size_t vl) {
882 return vmseq_vx_i8m1_b8_m(mask, maskedoff, op1, op2, vl);
883 }
884
885 // CHECK-RV64-LABEL: @test_vmseq_vv_i8m2_b4_m(
886 // CHECK-RV64-NEXT: entry:
887 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
888 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
889 //
test_vmseq_vv_i8m2_b4_m(vbool4_t mask,vbool4_t maskedoff,vint8m2_t op1,vint8m2_t op2,size_t vl)890 vbool4_t test_vmseq_vv_i8m2_b4_m(vbool4_t mask, vbool4_t maskedoff,
891 vint8m2_t op1, vint8m2_t op2, size_t vl) {
892 return vmseq_vv_i8m2_b4_m(mask, maskedoff, op1, op2, vl);
893 }
894
895 // CHECK-RV64-LABEL: @test_vmseq_vx_i8m2_b4_m(
896 // CHECK-RV64-NEXT: entry:
897 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
898 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
899 //
test_vmseq_vx_i8m2_b4_m(vbool4_t mask,vbool4_t maskedoff,vint8m2_t op1,int8_t op2,size_t vl)900 vbool4_t test_vmseq_vx_i8m2_b4_m(vbool4_t mask, vbool4_t maskedoff,
901 vint8m2_t op1, int8_t op2, size_t vl) {
902 return vmseq_vx_i8m2_b4_m(mask, maskedoff, op1, op2, vl);
903 }
904
905 // CHECK-RV64-LABEL: @test_vmseq_vv_i8m4_b2_m(
906 // CHECK-RV64-NEXT: entry:
907 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
908 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
909 //
test_vmseq_vv_i8m4_b2_m(vbool2_t mask,vbool2_t maskedoff,vint8m4_t op1,vint8m4_t op2,size_t vl)910 vbool2_t test_vmseq_vv_i8m4_b2_m(vbool2_t mask, vbool2_t maskedoff,
911 vint8m4_t op1, vint8m4_t op2, size_t vl) {
912 return vmseq_vv_i8m4_b2_m(mask, maskedoff, op1, op2, vl);
913 }
914
915 // CHECK-RV64-LABEL: @test_vmseq_vx_i8m4_b2_m(
916 // CHECK-RV64-NEXT: entry:
917 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
918 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
919 //
test_vmseq_vx_i8m4_b2_m(vbool2_t mask,vbool2_t maskedoff,vint8m4_t op1,int8_t op2,size_t vl)920 vbool2_t test_vmseq_vx_i8m4_b2_m(vbool2_t mask, vbool2_t maskedoff,
921 vint8m4_t op1, int8_t op2, size_t vl) {
922 return vmseq_vx_i8m4_b2_m(mask, maskedoff, op1, op2, vl);
923 }
924
925 // CHECK-RV64-LABEL: @test_vmseq_vv_i8m8_b1_m(
926 // CHECK-RV64-NEXT: entry:
927 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmseq.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
928 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
929 //
test_vmseq_vv_i8m8_b1_m(vbool1_t mask,vbool1_t maskedoff,vint8m8_t op1,vint8m8_t op2,size_t vl)930 vbool1_t test_vmseq_vv_i8m8_b1_m(vbool1_t mask, vbool1_t maskedoff,
931 vint8m8_t op1, vint8m8_t op2, size_t vl) {
932 return vmseq_vv_i8m8_b1_m(mask, maskedoff, op1, op2, vl);
933 }
934
935 // CHECK-RV64-LABEL: @test_vmseq_vx_i8m8_b1_m(
936 // CHECK-RV64-NEXT: entry:
937 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmseq.mask.nxv64i8.i8.i64(<vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
938 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
939 //
test_vmseq_vx_i8m8_b1_m(vbool1_t mask,vbool1_t maskedoff,vint8m8_t op1,int8_t op2,size_t vl)940 vbool1_t test_vmseq_vx_i8m8_b1_m(vbool1_t mask, vbool1_t maskedoff,
941 vint8m8_t op1, int8_t op2, size_t vl) {
942 return vmseq_vx_i8m8_b1_m(mask, maskedoff, op1, op2, vl);
943 }
944
945 // CHECK-RV64-LABEL: @test_vmseq_vv_i16mf4_b64_m(
946 // CHECK-RV64-NEXT: entry:
947 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
948 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
949 //
test_vmseq_vv_i16mf4_b64_m(vbool64_t mask,vbool64_t maskedoff,vint16mf4_t op1,vint16mf4_t op2,size_t vl)950 vbool64_t test_vmseq_vv_i16mf4_b64_m(vbool64_t mask, vbool64_t maskedoff,
951 vint16mf4_t op1, vint16mf4_t op2,
952 size_t vl) {
953 return vmseq_vv_i16mf4_b64_m(mask, maskedoff, op1, op2, vl);
954 }
955
956 // CHECK-RV64-LABEL: @test_vmseq_vx_i16mf4_b64_m(
957 // CHECK-RV64-NEXT: entry:
958 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
959 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
960 //
test_vmseq_vx_i16mf4_b64_m(vbool64_t mask,vbool64_t maskedoff,vint16mf4_t op1,int16_t op2,size_t vl)961 vbool64_t test_vmseq_vx_i16mf4_b64_m(vbool64_t mask, vbool64_t maskedoff,
962 vint16mf4_t op1, int16_t op2, size_t vl) {
963 return vmseq_vx_i16mf4_b64_m(mask, maskedoff, op1, op2, vl);
964 }
965
966 // CHECK-RV64-LABEL: @test_vmseq_vv_i16mf2_b32_m(
967 // CHECK-RV64-NEXT: entry:
968 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
969 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
970 //
test_vmseq_vv_i16mf2_b32_m(vbool32_t mask,vbool32_t maskedoff,vint16mf2_t op1,vint16mf2_t op2,size_t vl)971 vbool32_t test_vmseq_vv_i16mf2_b32_m(vbool32_t mask, vbool32_t maskedoff,
972 vint16mf2_t op1, vint16mf2_t op2,
973 size_t vl) {
974 return vmseq_vv_i16mf2_b32_m(mask, maskedoff, op1, op2, vl);
975 }
976
977 // CHECK-RV64-LABEL: @test_vmseq_vx_i16mf2_b32_m(
978 // CHECK-RV64-NEXT: entry:
979 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
980 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
981 //
test_vmseq_vx_i16mf2_b32_m(vbool32_t mask,vbool32_t maskedoff,vint16mf2_t op1,int16_t op2,size_t vl)982 vbool32_t test_vmseq_vx_i16mf2_b32_m(vbool32_t mask, vbool32_t maskedoff,
983 vint16mf2_t op1, int16_t op2, size_t vl) {
984 return vmseq_vx_i16mf2_b32_m(mask, maskedoff, op1, op2, vl);
985 }
986
987 // CHECK-RV64-LABEL: @test_vmseq_vv_i16m1_b16_m(
988 // CHECK-RV64-NEXT: entry:
989 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
990 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
991 //
test_vmseq_vv_i16m1_b16_m(vbool16_t mask,vbool16_t maskedoff,vint16m1_t op1,vint16m1_t op2,size_t vl)992 vbool16_t test_vmseq_vv_i16m1_b16_m(vbool16_t mask, vbool16_t maskedoff,
993 vint16m1_t op1, vint16m1_t op2, size_t vl) {
994 return vmseq_vv_i16m1_b16_m(mask, maskedoff, op1, op2, vl);
995 }
996
997 // CHECK-RV64-LABEL: @test_vmseq_vx_i16m1_b16_m(
998 // CHECK-RV64-NEXT: entry:
999 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1000 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1001 //
test_vmseq_vx_i16m1_b16_m(vbool16_t mask,vbool16_t maskedoff,vint16m1_t op1,int16_t op2,size_t vl)1002 vbool16_t test_vmseq_vx_i16m1_b16_m(vbool16_t mask, vbool16_t maskedoff,
1003 vint16m1_t op1, int16_t op2, size_t vl) {
1004 return vmseq_vx_i16m1_b16_m(mask, maskedoff, op1, op2, vl);
1005 }
1006
1007 // CHECK-RV64-LABEL: @test_vmseq_vv_i16m2_b8_m(
1008 // CHECK-RV64-NEXT: entry:
1009 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1010 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1011 //
test_vmseq_vv_i16m2_b8_m(vbool8_t mask,vbool8_t maskedoff,vint16m2_t op1,vint16m2_t op2,size_t vl)1012 vbool8_t test_vmseq_vv_i16m2_b8_m(vbool8_t mask, vbool8_t maskedoff,
1013 vint16m2_t op1, vint16m2_t op2, size_t vl) {
1014 return vmseq_vv_i16m2_b8_m(mask, maskedoff, op1, op2, vl);
1015 }
1016
1017 // CHECK-RV64-LABEL: @test_vmseq_vx_i16m2_b8_m(
1018 // CHECK-RV64-NEXT: entry:
1019 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1020 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1021 //
test_vmseq_vx_i16m2_b8_m(vbool8_t mask,vbool8_t maskedoff,vint16m2_t op1,int16_t op2,size_t vl)1022 vbool8_t test_vmseq_vx_i16m2_b8_m(vbool8_t mask, vbool8_t maskedoff,
1023 vint16m2_t op1, int16_t op2, size_t vl) {
1024 return vmseq_vx_i16m2_b8_m(mask, maskedoff, op1, op2, vl);
1025 }
1026
1027 // CHECK-RV64-LABEL: @test_vmseq_vv_i16m4_b4_m(
1028 // CHECK-RV64-NEXT: entry:
1029 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1030 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1031 //
test_vmseq_vv_i16m4_b4_m(vbool4_t mask,vbool4_t maskedoff,vint16m4_t op1,vint16m4_t op2,size_t vl)1032 vbool4_t test_vmseq_vv_i16m4_b4_m(vbool4_t mask, vbool4_t maskedoff,
1033 vint16m4_t op1, vint16m4_t op2, size_t vl) {
1034 return vmseq_vv_i16m4_b4_m(mask, maskedoff, op1, op2, vl);
1035 }
1036
1037 // CHECK-RV64-LABEL: @test_vmseq_vx_i16m4_b4_m(
1038 // CHECK-RV64-NEXT: entry:
1039 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1040 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1041 //
test_vmseq_vx_i16m4_b4_m(vbool4_t mask,vbool4_t maskedoff,vint16m4_t op1,int16_t op2,size_t vl)1042 vbool4_t test_vmseq_vx_i16m4_b4_m(vbool4_t mask, vbool4_t maskedoff,
1043 vint16m4_t op1, int16_t op2, size_t vl) {
1044 return vmseq_vx_i16m4_b4_m(mask, maskedoff, op1, op2, vl);
1045 }
1046
1047 // CHECK-RV64-LABEL: @test_vmseq_vv_i16m8_b2_m(
1048 // CHECK-RV64-NEXT: entry:
1049 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1050 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
1051 //
test_vmseq_vv_i16m8_b2_m(vbool2_t mask,vbool2_t maskedoff,vint16m8_t op1,vint16m8_t op2,size_t vl)1052 vbool2_t test_vmseq_vv_i16m8_b2_m(vbool2_t mask, vbool2_t maskedoff,
1053 vint16m8_t op1, vint16m8_t op2, size_t vl) {
1054 return vmseq_vv_i16m8_b2_m(mask, maskedoff, op1, op2, vl);
1055 }
1056
1057 // CHECK-RV64-LABEL: @test_vmseq_vx_i16m8_b2_m(
1058 // CHECK-RV64-NEXT: entry:
1059 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i16.i16.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1060 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
1061 //
test_vmseq_vx_i16m8_b2_m(vbool2_t mask,vbool2_t maskedoff,vint16m8_t op1,int16_t op2,size_t vl)1062 vbool2_t test_vmseq_vx_i16m8_b2_m(vbool2_t mask, vbool2_t maskedoff,
1063 vint16m8_t op1, int16_t op2, size_t vl) {
1064 return vmseq_vx_i16m8_b2_m(mask, maskedoff, op1, op2, vl);
1065 }
1066
1067 // CHECK-RV64-LABEL: @test_vmseq_vv_i32mf2_b64_m(
1068 // CHECK-RV64-NEXT: entry:
1069 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1070 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1071 //
test_vmseq_vv_i32mf2_b64_m(vbool64_t mask,vbool64_t maskedoff,vint32mf2_t op1,vint32mf2_t op2,size_t vl)1072 vbool64_t test_vmseq_vv_i32mf2_b64_m(vbool64_t mask, vbool64_t maskedoff,
1073 vint32mf2_t op1, vint32mf2_t op2,
1074 size_t vl) {
1075 return vmseq_vv_i32mf2_b64_m(mask, maskedoff, op1, op2, vl);
1076 }
1077
1078 // CHECK-RV64-LABEL: @test_vmseq_vx_i32mf2_b64_m(
1079 // CHECK-RV64-NEXT: entry:
1080 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1081 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1082 //
test_vmseq_vx_i32mf2_b64_m(vbool64_t mask,vbool64_t maskedoff,vint32mf2_t op1,int32_t op2,size_t vl)1083 vbool64_t test_vmseq_vx_i32mf2_b64_m(vbool64_t mask, vbool64_t maskedoff,
1084 vint32mf2_t op1, int32_t op2, size_t vl) {
1085 return vmseq_vx_i32mf2_b64_m(mask, maskedoff, op1, op2, vl);
1086 }
1087
1088 // CHECK-RV64-LABEL: @test_vmseq_vv_i32m1_b32_m(
1089 // CHECK-RV64-NEXT: entry:
1090 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1091 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1092 //
test_vmseq_vv_i32m1_b32_m(vbool32_t mask,vbool32_t maskedoff,vint32m1_t op1,vint32m1_t op2,size_t vl)1093 vbool32_t test_vmseq_vv_i32m1_b32_m(vbool32_t mask, vbool32_t maskedoff,
1094 vint32m1_t op1, vint32m1_t op2, size_t vl) {
1095 return vmseq_vv_i32m1_b32_m(mask, maskedoff, op1, op2, vl);
1096 }
1097
1098 // CHECK-RV64-LABEL: @test_vmseq_vx_i32m1_b32_m(
1099 // CHECK-RV64-NEXT: entry:
1100 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1101 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1102 //
test_vmseq_vx_i32m1_b32_m(vbool32_t mask,vbool32_t maskedoff,vint32m1_t op1,int32_t op2,size_t vl)1103 vbool32_t test_vmseq_vx_i32m1_b32_m(vbool32_t mask, vbool32_t maskedoff,
1104 vint32m1_t op1, int32_t op2, size_t vl) {
1105 return vmseq_vx_i32m1_b32_m(mask, maskedoff, op1, op2, vl);
1106 }
1107
1108 // CHECK-RV64-LABEL: @test_vmseq_vv_i32m2_b16_m(
1109 // CHECK-RV64-NEXT: entry:
1110 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1111 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1112 //
test_vmseq_vv_i32m2_b16_m(vbool16_t mask,vbool16_t maskedoff,vint32m2_t op1,vint32m2_t op2,size_t vl)1113 vbool16_t test_vmseq_vv_i32m2_b16_m(vbool16_t mask, vbool16_t maskedoff,
1114 vint32m2_t op1, vint32m2_t op2, size_t vl) {
1115 return vmseq_vv_i32m2_b16_m(mask, maskedoff, op1, op2, vl);
1116 }
1117
1118 // CHECK-RV64-LABEL: @test_vmseq_vx_i32m2_b16_m(
1119 // CHECK-RV64-NEXT: entry:
1120 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1121 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1122 //
test_vmseq_vx_i32m2_b16_m(vbool16_t mask,vbool16_t maskedoff,vint32m2_t op1,int32_t op2,size_t vl)1123 vbool16_t test_vmseq_vx_i32m2_b16_m(vbool16_t mask, vbool16_t maskedoff,
1124 vint32m2_t op1, int32_t op2, size_t vl) {
1125 return vmseq_vx_i32m2_b16_m(mask, maskedoff, op1, op2, vl);
1126 }
1127
1128 // CHECK-RV64-LABEL: @test_vmseq_vv_i32m4_b8_m(
1129 // CHECK-RV64-NEXT: entry:
1130 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1131 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1132 //
test_vmseq_vv_i32m4_b8_m(vbool8_t mask,vbool8_t maskedoff,vint32m4_t op1,vint32m4_t op2,size_t vl)1133 vbool8_t test_vmseq_vv_i32m4_b8_m(vbool8_t mask, vbool8_t maskedoff,
1134 vint32m4_t op1, vint32m4_t op2, size_t vl) {
1135 return vmseq_vv_i32m4_b8_m(mask, maskedoff, op1, op2, vl);
1136 }
1137
1138 // CHECK-RV64-LABEL: @test_vmseq_vx_i32m4_b8_m(
1139 // CHECK-RV64-NEXT: entry:
1140 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1141 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1142 //
test_vmseq_vx_i32m4_b8_m(vbool8_t mask,vbool8_t maskedoff,vint32m4_t op1,int32_t op2,size_t vl)1143 vbool8_t test_vmseq_vx_i32m4_b8_m(vbool8_t mask, vbool8_t maskedoff,
1144 vint32m4_t op1, int32_t op2, size_t vl) {
1145 return vmseq_vx_i32m4_b8_m(mask, maskedoff, op1, op2, vl);
1146 }
1147
1148 // CHECK-RV64-LABEL: @test_vmseq_vv_i32m8_b4_m(
1149 // CHECK-RV64-NEXT: entry:
1150 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1151 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1152 //
test_vmseq_vv_i32m8_b4_m(vbool4_t mask,vbool4_t maskedoff,vint32m8_t op1,vint32m8_t op2,size_t vl)1153 vbool4_t test_vmseq_vv_i32m8_b4_m(vbool4_t mask, vbool4_t maskedoff,
1154 vint32m8_t op1, vint32m8_t op2, size_t vl) {
1155 return vmseq_vv_i32m8_b4_m(mask, maskedoff, op1, op2, vl);
1156 }
1157
1158 // CHECK-RV64-LABEL: @test_vmseq_vx_i32m8_b4_m(
1159 // CHECK-RV64-NEXT: entry:
1160 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i32.i32.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1161 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1162 //
test_vmseq_vx_i32m8_b4_m(vbool4_t mask,vbool4_t maskedoff,vint32m8_t op1,int32_t op2,size_t vl)1163 vbool4_t test_vmseq_vx_i32m8_b4_m(vbool4_t mask, vbool4_t maskedoff,
1164 vint32m8_t op1, int32_t op2, size_t vl) {
1165 return vmseq_vx_i32m8_b4_m(mask, maskedoff, op1, op2, vl);
1166 }
1167
1168 // CHECK-RV64-LABEL: @test_vmseq_vv_i64m1_b64_m(
1169 // CHECK-RV64-NEXT: entry:
1170 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1171 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1172 //
test_vmseq_vv_i64m1_b64_m(vbool64_t mask,vbool64_t maskedoff,vint64m1_t op1,vint64m1_t op2,size_t vl)1173 vbool64_t test_vmseq_vv_i64m1_b64_m(vbool64_t mask, vbool64_t maskedoff,
1174 vint64m1_t op1, vint64m1_t op2, size_t vl) {
1175 return vmseq_vv_i64m1_b64_m(mask, maskedoff, op1, op2, vl);
1176 }
1177
1178 // CHECK-RV64-LABEL: @test_vmseq_vx_i64m1_b64_m(
1179 // CHECK-RV64-NEXT: entry:
1180 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1181 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1182 //
test_vmseq_vx_i64m1_b64_m(vbool64_t mask,vbool64_t maskedoff,vint64m1_t op1,int64_t op2,size_t vl)1183 vbool64_t test_vmseq_vx_i64m1_b64_m(vbool64_t mask, vbool64_t maskedoff,
1184 vint64m1_t op1, int64_t op2, size_t vl) {
1185 return vmseq_vx_i64m1_b64_m(mask, maskedoff, op1, op2, vl);
1186 }
1187
1188 // CHECK-RV64-LABEL: @test_vmseq_vv_i64m2_b32_m(
1189 // CHECK-RV64-NEXT: entry:
1190 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1191 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1192 //
test_vmseq_vv_i64m2_b32_m(vbool32_t mask,vbool32_t maskedoff,vint64m2_t op1,vint64m2_t op2,size_t vl)1193 vbool32_t test_vmseq_vv_i64m2_b32_m(vbool32_t mask, vbool32_t maskedoff,
1194 vint64m2_t op1, vint64m2_t op2, size_t vl) {
1195 return vmseq_vv_i64m2_b32_m(mask, maskedoff, op1, op2, vl);
1196 }
1197
1198 // CHECK-RV64-LABEL: @test_vmseq_vx_i64m2_b32_m(
1199 // CHECK-RV64-NEXT: entry:
1200 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1201 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1202 //
test_vmseq_vx_i64m2_b32_m(vbool32_t mask,vbool32_t maskedoff,vint64m2_t op1,int64_t op2,size_t vl)1203 vbool32_t test_vmseq_vx_i64m2_b32_m(vbool32_t mask, vbool32_t maskedoff,
1204 vint64m2_t op1, int64_t op2, size_t vl) {
1205 return vmseq_vx_i64m2_b32_m(mask, maskedoff, op1, op2, vl);
1206 }
1207
1208 // CHECK-RV64-LABEL: @test_vmseq_vv_i64m4_b16_m(
1209 // CHECK-RV64-NEXT: entry:
1210 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1211 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1212 //
test_vmseq_vv_i64m4_b16_m(vbool16_t mask,vbool16_t maskedoff,vint64m4_t op1,vint64m4_t op2,size_t vl)1213 vbool16_t test_vmseq_vv_i64m4_b16_m(vbool16_t mask, vbool16_t maskedoff,
1214 vint64m4_t op1, vint64m4_t op2, size_t vl) {
1215 return vmseq_vv_i64m4_b16_m(mask, maskedoff, op1, op2, vl);
1216 }
1217
1218 // CHECK-RV64-LABEL: @test_vmseq_vx_i64m4_b16_m(
1219 // CHECK-RV64-NEXT: entry:
1220 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1221 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1222 //
test_vmseq_vx_i64m4_b16_m(vbool16_t mask,vbool16_t maskedoff,vint64m4_t op1,int64_t op2,size_t vl)1223 vbool16_t test_vmseq_vx_i64m4_b16_m(vbool16_t mask, vbool16_t maskedoff,
1224 vint64m4_t op1, int64_t op2, size_t vl) {
1225 return vmseq_vx_i64m4_b16_m(mask, maskedoff, op1, op2, vl);
1226 }
1227
1228 // CHECK-RV64-LABEL: @test_vmseq_vv_i64m8_b8_m(
1229 // CHECK-RV64-NEXT: entry:
1230 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1231 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1232 //
test_vmseq_vv_i64m8_b8_m(vbool8_t mask,vbool8_t maskedoff,vint64m8_t op1,vint64m8_t op2,size_t vl)1233 vbool8_t test_vmseq_vv_i64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,
1234 vint64m8_t op1, vint64m8_t op2, size_t vl) {
1235 return vmseq_vv_i64m8_b8_m(mask, maskedoff, op1, op2, vl);
1236 }
1237
1238 // CHECK-RV64-LABEL: @test_vmseq_vx_i64m8_b8_m(
1239 // CHECK-RV64-NEXT: entry:
1240 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1241 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1242 //
test_vmseq_vx_i64m8_b8_m(vbool8_t mask,vbool8_t maskedoff,vint64m8_t op1,int64_t op2,size_t vl)1243 vbool8_t test_vmseq_vx_i64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,
1244 vint64m8_t op1, int64_t op2, size_t vl) {
1245 return vmseq_vx_i64m8_b8_m(mask, maskedoff, op1, op2, vl);
1246 }
1247
1248 // CHECK-RV64-LABEL: @test_vmseq_vv_u8mf8_b64_m(
1249 // CHECK-RV64-NEXT: entry:
1250 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1251 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1252 //
test_vmseq_vv_u8mf8_b64_m(vbool64_t mask,vbool64_t maskedoff,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)1253 vbool64_t test_vmseq_vv_u8mf8_b64_m(vbool64_t mask, vbool64_t maskedoff,
1254 vuint8mf8_t op1, vuint8mf8_t op2,
1255 size_t vl) {
1256 return vmseq_vv_u8mf8_b64_m(mask, maskedoff, op1, op2, vl);
1257 }
1258
1259 // CHECK-RV64-LABEL: @test_vmseq_vx_u8mf8_b64_m(
1260 // CHECK-RV64-NEXT: entry:
1261 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1262 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1263 //
test_vmseq_vx_u8mf8_b64_m(vbool64_t mask,vbool64_t maskedoff,vuint8mf8_t op1,uint8_t op2,size_t vl)1264 vbool64_t test_vmseq_vx_u8mf8_b64_m(vbool64_t mask, vbool64_t maskedoff,
1265 vuint8mf8_t op1, uint8_t op2, size_t vl) {
1266 return vmseq_vx_u8mf8_b64_m(mask, maskedoff, op1, op2, vl);
1267 }
1268
1269 // CHECK-RV64-LABEL: @test_vmseq_vv_u8mf4_b32_m(
1270 // CHECK-RV64-NEXT: entry:
1271 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1272 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1273 //
test_vmseq_vv_u8mf4_b32_m(vbool32_t mask,vbool32_t maskedoff,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)1274 vbool32_t test_vmseq_vv_u8mf4_b32_m(vbool32_t mask, vbool32_t maskedoff,
1275 vuint8mf4_t op1, vuint8mf4_t op2,
1276 size_t vl) {
1277 return vmseq_vv_u8mf4_b32_m(mask, maskedoff, op1, op2, vl);
1278 }
1279
1280 // CHECK-RV64-LABEL: @test_vmseq_vx_u8mf4_b32_m(
1281 // CHECK-RV64-NEXT: entry:
1282 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1283 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1284 //
test_vmseq_vx_u8mf4_b32_m(vbool32_t mask,vbool32_t maskedoff,vuint8mf4_t op1,uint8_t op2,size_t vl)1285 vbool32_t test_vmseq_vx_u8mf4_b32_m(vbool32_t mask, vbool32_t maskedoff,
1286 vuint8mf4_t op1, uint8_t op2, size_t vl) {
1287 return vmseq_vx_u8mf4_b32_m(mask, maskedoff, op1, op2, vl);
1288 }
1289
1290 // CHECK-RV64-LABEL: @test_vmseq_vv_u8mf2_b16_m(
1291 // CHECK-RV64-NEXT: entry:
1292 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1293 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1294 //
test_vmseq_vv_u8mf2_b16_m(vbool16_t mask,vbool16_t maskedoff,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)1295 vbool16_t test_vmseq_vv_u8mf2_b16_m(vbool16_t mask, vbool16_t maskedoff,
1296 vuint8mf2_t op1, vuint8mf2_t op2,
1297 size_t vl) {
1298 return vmseq_vv_u8mf2_b16_m(mask, maskedoff, op1, op2, vl);
1299 }
1300
1301 // CHECK-RV64-LABEL: @test_vmseq_vx_u8mf2_b16_m(
1302 // CHECK-RV64-NEXT: entry:
1303 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1304 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1305 //
test_vmseq_vx_u8mf2_b16_m(vbool16_t mask,vbool16_t maskedoff,vuint8mf2_t op1,uint8_t op2,size_t vl)1306 vbool16_t test_vmseq_vx_u8mf2_b16_m(vbool16_t mask, vbool16_t maskedoff,
1307 vuint8mf2_t op1, uint8_t op2, size_t vl) {
1308 return vmseq_vx_u8mf2_b16_m(mask, maskedoff, op1, op2, vl);
1309 }
1310
1311 // CHECK-RV64-LABEL: @test_vmseq_vv_u8m1_b8_m(
1312 // CHECK-RV64-NEXT: entry:
1313 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1314 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1315 //
test_vmseq_vv_u8m1_b8_m(vbool8_t mask,vbool8_t maskedoff,vuint8m1_t op1,vuint8m1_t op2,size_t vl)1316 vbool8_t test_vmseq_vv_u8m1_b8_m(vbool8_t mask, vbool8_t maskedoff,
1317 vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
1318 return vmseq_vv_u8m1_b8_m(mask, maskedoff, op1, op2, vl);
1319 }
1320
1321 // CHECK-RV64-LABEL: @test_vmseq_vx_u8m1_b8_m(
1322 // CHECK-RV64-NEXT: entry:
1323 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1324 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1325 //
test_vmseq_vx_u8m1_b8_m(vbool8_t mask,vbool8_t maskedoff,vuint8m1_t op1,uint8_t op2,size_t vl)1326 vbool8_t test_vmseq_vx_u8m1_b8_m(vbool8_t mask, vbool8_t maskedoff,
1327 vuint8m1_t op1, uint8_t op2, size_t vl) {
1328 return vmseq_vx_u8m1_b8_m(mask, maskedoff, op1, op2, vl);
1329 }
1330
1331 // CHECK-RV64-LABEL: @test_vmseq_vv_u8m2_b4_m(
1332 // CHECK-RV64-NEXT: entry:
1333 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1334 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1335 //
test_vmseq_vv_u8m2_b4_m(vbool4_t mask,vbool4_t maskedoff,vuint8m2_t op1,vuint8m2_t op2,size_t vl)1336 vbool4_t test_vmseq_vv_u8m2_b4_m(vbool4_t mask, vbool4_t maskedoff,
1337 vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
1338 return vmseq_vv_u8m2_b4_m(mask, maskedoff, op1, op2, vl);
1339 }
1340
1341 // CHECK-RV64-LABEL: @test_vmseq_vx_u8m2_b4_m(
1342 // CHECK-RV64-NEXT: entry:
1343 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1344 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1345 //
test_vmseq_vx_u8m2_b4_m(vbool4_t mask,vbool4_t maskedoff,vuint8m2_t op1,uint8_t op2,size_t vl)1346 vbool4_t test_vmseq_vx_u8m2_b4_m(vbool4_t mask, vbool4_t maskedoff,
1347 vuint8m2_t op1, uint8_t op2, size_t vl) {
1348 return vmseq_vx_u8m2_b4_m(mask, maskedoff, op1, op2, vl);
1349 }
1350
1351 // CHECK-RV64-LABEL: @test_vmseq_vv_u8m4_b2_m(
1352 // CHECK-RV64-NEXT: entry:
1353 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1354 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
1355 //
test_vmseq_vv_u8m4_b2_m(vbool2_t mask,vbool2_t maskedoff,vuint8m4_t op1,vuint8m4_t op2,size_t vl)1356 vbool2_t test_vmseq_vv_u8m4_b2_m(vbool2_t mask, vbool2_t maskedoff,
1357 vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
1358 return vmseq_vv_u8m4_b2_m(mask, maskedoff, op1, op2, vl);
1359 }
1360
1361 // CHECK-RV64-LABEL: @test_vmseq_vx_u8m4_b2_m(
1362 // CHECK-RV64-NEXT: entry:
1363 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1364 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
1365 //
test_vmseq_vx_u8m4_b2_m(vbool2_t mask,vbool2_t maskedoff,vuint8m4_t op1,uint8_t op2,size_t vl)1366 vbool2_t test_vmseq_vx_u8m4_b2_m(vbool2_t mask, vbool2_t maskedoff,
1367 vuint8m4_t op1, uint8_t op2, size_t vl) {
1368 return vmseq_vx_u8m4_b2_m(mask, maskedoff, op1, op2, vl);
1369 }
1370
1371 // CHECK-RV64-LABEL: @test_vmseq_vv_u8m8_b1_m(
1372 // CHECK-RV64-NEXT: entry:
1373 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmseq.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1374 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
1375 //
test_vmseq_vv_u8m8_b1_m(vbool1_t mask,vbool1_t maskedoff,vuint8m8_t op1,vuint8m8_t op2,size_t vl)1376 vbool1_t test_vmseq_vv_u8m8_b1_m(vbool1_t mask, vbool1_t maskedoff,
1377 vuint8m8_t op1, vuint8m8_t op2, size_t vl) {
1378 return vmseq_vv_u8m8_b1_m(mask, maskedoff, op1, op2, vl);
1379 }
1380
1381 // CHECK-RV64-LABEL: @test_vmseq_vx_u8m8_b1_m(
1382 // CHECK-RV64-NEXT: entry:
1383 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmseq.mask.nxv64i8.i8.i64(<vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1384 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
1385 //
test_vmseq_vx_u8m8_b1_m(vbool1_t mask,vbool1_t maskedoff,vuint8m8_t op1,uint8_t op2,size_t vl)1386 vbool1_t test_vmseq_vx_u8m8_b1_m(vbool1_t mask, vbool1_t maskedoff,
1387 vuint8m8_t op1, uint8_t op2, size_t vl) {
1388 return vmseq_vx_u8m8_b1_m(mask, maskedoff, op1, op2, vl);
1389 }
1390
1391 // CHECK-RV64-LABEL: @test_vmseq_vv_u16mf4_b64_m(
1392 // CHECK-RV64-NEXT: entry:
1393 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1394 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1395 //
test_vmseq_vv_u16mf4_b64_m(vbool64_t mask,vbool64_t maskedoff,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)1396 vbool64_t test_vmseq_vv_u16mf4_b64_m(vbool64_t mask, vbool64_t maskedoff,
1397 vuint16mf4_t op1, vuint16mf4_t op2,
1398 size_t vl) {
1399 return vmseq_vv_u16mf4_b64_m(mask, maskedoff, op1, op2, vl);
1400 }
1401
1402 // CHECK-RV64-LABEL: @test_vmseq_vx_u16mf4_b64_m(
1403 // CHECK-RV64-NEXT: entry:
1404 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1405 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1406 //
test_vmseq_vx_u16mf4_b64_m(vbool64_t mask,vbool64_t maskedoff,vuint16mf4_t op1,uint16_t op2,size_t vl)1407 vbool64_t test_vmseq_vx_u16mf4_b64_m(vbool64_t mask, vbool64_t maskedoff,
1408 vuint16mf4_t op1, uint16_t op2,
1409 size_t vl) {
1410 return vmseq_vx_u16mf4_b64_m(mask, maskedoff, op1, op2, vl);
1411 }
1412
1413 // CHECK-RV64-LABEL: @test_vmseq_vv_u16mf2_b32_m(
1414 // CHECK-RV64-NEXT: entry:
1415 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1416 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1417 //
test_vmseq_vv_u16mf2_b32_m(vbool32_t mask,vbool32_t maskedoff,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)1418 vbool32_t test_vmseq_vv_u16mf2_b32_m(vbool32_t mask, vbool32_t maskedoff,
1419 vuint16mf2_t op1, vuint16mf2_t op2,
1420 size_t vl) {
1421 return vmseq_vv_u16mf2_b32_m(mask, maskedoff, op1, op2, vl);
1422 }
1423
1424 // CHECK-RV64-LABEL: @test_vmseq_vx_u16mf2_b32_m(
1425 // CHECK-RV64-NEXT: entry:
1426 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1427 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1428 //
test_vmseq_vx_u16mf2_b32_m(vbool32_t mask,vbool32_t maskedoff,vuint16mf2_t op1,uint16_t op2,size_t vl)1429 vbool32_t test_vmseq_vx_u16mf2_b32_m(vbool32_t mask, vbool32_t maskedoff,
1430 vuint16mf2_t op1, uint16_t op2,
1431 size_t vl) {
1432 return vmseq_vx_u16mf2_b32_m(mask, maskedoff, op1, op2, vl);
1433 }
1434
1435 // CHECK-RV64-LABEL: @test_vmseq_vv_u16m1_b16_m(
1436 // CHECK-RV64-NEXT: entry:
1437 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1438 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1439 //
test_vmseq_vv_u16m1_b16_m(vbool16_t mask,vbool16_t maskedoff,vuint16m1_t op1,vuint16m1_t op2,size_t vl)1440 vbool16_t test_vmseq_vv_u16m1_b16_m(vbool16_t mask, vbool16_t maskedoff,
1441 vuint16m1_t op1, vuint16m1_t op2,
1442 size_t vl) {
1443 return vmseq_vv_u16m1_b16_m(mask, maskedoff, op1, op2, vl);
1444 }
1445
1446 // CHECK-RV64-LABEL: @test_vmseq_vx_u16m1_b16_m(
1447 // CHECK-RV64-NEXT: entry:
1448 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1449 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1450 //
test_vmseq_vx_u16m1_b16_m(vbool16_t mask,vbool16_t maskedoff,vuint16m1_t op1,uint16_t op2,size_t vl)1451 vbool16_t test_vmseq_vx_u16m1_b16_m(vbool16_t mask, vbool16_t maskedoff,
1452 vuint16m1_t op1, uint16_t op2, size_t vl) {
1453 return vmseq_vx_u16m1_b16_m(mask, maskedoff, op1, op2, vl);
1454 }
1455
1456 // CHECK-RV64-LABEL: @test_vmseq_vv_u16m2_b8_m(
1457 // CHECK-RV64-NEXT: entry:
1458 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1459 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1460 //
test_vmseq_vv_u16m2_b8_m(vbool8_t mask,vbool8_t maskedoff,vuint16m2_t op1,vuint16m2_t op2,size_t vl)1461 vbool8_t test_vmseq_vv_u16m2_b8_m(vbool8_t mask, vbool8_t maskedoff,
1462 vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
1463 return vmseq_vv_u16m2_b8_m(mask, maskedoff, op1, op2, vl);
1464 }
1465
1466 // CHECK-RV64-LABEL: @test_vmseq_vx_u16m2_b8_m(
1467 // CHECK-RV64-NEXT: entry:
1468 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1469 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1470 //
test_vmseq_vx_u16m2_b8_m(vbool8_t mask,vbool8_t maskedoff,vuint16m2_t op1,uint16_t op2,size_t vl)1471 vbool8_t test_vmseq_vx_u16m2_b8_m(vbool8_t mask, vbool8_t maskedoff,
1472 vuint16m2_t op1, uint16_t op2, size_t vl) {
1473 return vmseq_vx_u16m2_b8_m(mask, maskedoff, op1, op2, vl);
1474 }
1475
1476 // CHECK-RV64-LABEL: @test_vmseq_vv_u16m4_b4_m(
1477 // CHECK-RV64-NEXT: entry:
1478 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1479 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1480 //
test_vmseq_vv_u16m4_b4_m(vbool4_t mask,vbool4_t maskedoff,vuint16m4_t op1,vuint16m4_t op2,size_t vl)1481 vbool4_t test_vmseq_vv_u16m4_b4_m(vbool4_t mask, vbool4_t maskedoff,
1482 vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
1483 return vmseq_vv_u16m4_b4_m(mask, maskedoff, op1, op2, vl);
1484 }
1485
1486 // CHECK-RV64-LABEL: @test_vmseq_vx_u16m4_b4_m(
1487 // CHECK-RV64-NEXT: entry:
1488 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1489 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1490 //
test_vmseq_vx_u16m4_b4_m(vbool4_t mask,vbool4_t maskedoff,vuint16m4_t op1,uint16_t op2,size_t vl)1491 vbool4_t test_vmseq_vx_u16m4_b4_m(vbool4_t mask, vbool4_t maskedoff,
1492 vuint16m4_t op1, uint16_t op2, size_t vl) {
1493 return vmseq_vx_u16m4_b4_m(mask, maskedoff, op1, op2, vl);
1494 }
1495
1496 // CHECK-RV64-LABEL: @test_vmseq_vv_u16m8_b2_m(
1497 // CHECK-RV64-NEXT: entry:
1498 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1499 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
1500 //
test_vmseq_vv_u16m8_b2_m(vbool2_t mask,vbool2_t maskedoff,vuint16m8_t op1,vuint16m8_t op2,size_t vl)1501 vbool2_t test_vmseq_vv_u16m8_b2_m(vbool2_t mask, vbool2_t maskedoff,
1502 vuint16m8_t op1, vuint16m8_t op2, size_t vl) {
1503 return vmseq_vv_u16m8_b2_m(mask, maskedoff, op1, op2, vl);
1504 }
1505
1506 // CHECK-RV64-LABEL: @test_vmseq_vx_u16m8_b2_m(
1507 // CHECK-RV64-NEXT: entry:
1508 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i16.i16.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1509 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
1510 //
test_vmseq_vx_u16m8_b2_m(vbool2_t mask,vbool2_t maskedoff,vuint16m8_t op1,uint16_t op2,size_t vl)1511 vbool2_t test_vmseq_vx_u16m8_b2_m(vbool2_t mask, vbool2_t maskedoff,
1512 vuint16m8_t op1, uint16_t op2, size_t vl) {
1513 return vmseq_vx_u16m8_b2_m(mask, maskedoff, op1, op2, vl);
1514 }
1515
1516 // CHECK-RV64-LABEL: @test_vmseq_vv_u32mf2_b64_m(
1517 // CHECK-RV64-NEXT: entry:
1518 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1519 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1520 //
test_vmseq_vv_u32mf2_b64_m(vbool64_t mask,vbool64_t maskedoff,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)1521 vbool64_t test_vmseq_vv_u32mf2_b64_m(vbool64_t mask, vbool64_t maskedoff,
1522 vuint32mf2_t op1, vuint32mf2_t op2,
1523 size_t vl) {
1524 return vmseq_vv_u32mf2_b64_m(mask, maskedoff, op1, op2, vl);
1525 }
1526
1527 // CHECK-RV64-LABEL: @test_vmseq_vx_u32mf2_b64_m(
1528 // CHECK-RV64-NEXT: entry:
1529 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1530 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1531 //
test_vmseq_vx_u32mf2_b64_m(vbool64_t mask,vbool64_t maskedoff,vuint32mf2_t op1,uint32_t op2,size_t vl)1532 vbool64_t test_vmseq_vx_u32mf2_b64_m(vbool64_t mask, vbool64_t maskedoff,
1533 vuint32mf2_t op1, uint32_t op2,
1534 size_t vl) {
1535 return vmseq_vx_u32mf2_b64_m(mask, maskedoff, op1, op2, vl);
1536 }
1537
1538 // CHECK-RV64-LABEL: @test_vmseq_vv_u32m1_b32_m(
1539 // CHECK-RV64-NEXT: entry:
1540 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1541 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1542 //
test_vmseq_vv_u32m1_b32_m(vbool32_t mask,vbool32_t maskedoff,vuint32m1_t op1,vuint32m1_t op2,size_t vl)1543 vbool32_t test_vmseq_vv_u32m1_b32_m(vbool32_t mask, vbool32_t maskedoff,
1544 vuint32m1_t op1, vuint32m1_t op2,
1545 size_t vl) {
1546 return vmseq_vv_u32m1_b32_m(mask, maskedoff, op1, op2, vl);
1547 }
1548
1549 // CHECK-RV64-LABEL: @test_vmseq_vx_u32m1_b32_m(
1550 // CHECK-RV64-NEXT: entry:
1551 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1552 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1553 //
test_vmseq_vx_u32m1_b32_m(vbool32_t mask,vbool32_t maskedoff,vuint32m1_t op1,uint32_t op2,size_t vl)1554 vbool32_t test_vmseq_vx_u32m1_b32_m(vbool32_t mask, vbool32_t maskedoff,
1555 vuint32m1_t op1, uint32_t op2, size_t vl) {
1556 return vmseq_vx_u32m1_b32_m(mask, maskedoff, op1, op2, vl);
1557 }
1558
1559 // CHECK-RV64-LABEL: @test_vmseq_vv_u32m2_b16_m(
1560 // CHECK-RV64-NEXT: entry:
1561 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1562 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1563 //
test_vmseq_vv_u32m2_b16_m(vbool16_t mask,vbool16_t maskedoff,vuint32m2_t op1,vuint32m2_t op2,size_t vl)1564 vbool16_t test_vmseq_vv_u32m2_b16_m(vbool16_t mask, vbool16_t maskedoff,
1565 vuint32m2_t op1, vuint32m2_t op2,
1566 size_t vl) {
1567 return vmseq_vv_u32m2_b16_m(mask, maskedoff, op1, op2, vl);
1568 }
1569
1570 // CHECK-RV64-LABEL: @test_vmseq_vx_u32m2_b16_m(
1571 // CHECK-RV64-NEXT: entry:
1572 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1573 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1574 //
test_vmseq_vx_u32m2_b16_m(vbool16_t mask,vbool16_t maskedoff,vuint32m2_t op1,uint32_t op2,size_t vl)1575 vbool16_t test_vmseq_vx_u32m2_b16_m(vbool16_t mask, vbool16_t maskedoff,
1576 vuint32m2_t op1, uint32_t op2, size_t vl) {
1577 return vmseq_vx_u32m2_b16_m(mask, maskedoff, op1, op2, vl);
1578 }
1579
1580 // CHECK-RV64-LABEL: @test_vmseq_vv_u32m4_b8_m(
1581 // CHECK-RV64-NEXT: entry:
1582 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1583 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1584 //
test_vmseq_vv_u32m4_b8_m(vbool8_t mask,vbool8_t maskedoff,vuint32m4_t op1,vuint32m4_t op2,size_t vl)1585 vbool8_t test_vmseq_vv_u32m4_b8_m(vbool8_t mask, vbool8_t maskedoff,
1586 vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
1587 return vmseq_vv_u32m4_b8_m(mask, maskedoff, op1, op2, vl);
1588 }
1589
1590 // CHECK-RV64-LABEL: @test_vmseq_vx_u32m4_b8_m(
1591 // CHECK-RV64-NEXT: entry:
1592 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1593 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1594 //
test_vmseq_vx_u32m4_b8_m(vbool8_t mask,vbool8_t maskedoff,vuint32m4_t op1,uint32_t op2,size_t vl)1595 vbool8_t test_vmseq_vx_u32m4_b8_m(vbool8_t mask, vbool8_t maskedoff,
1596 vuint32m4_t op1, uint32_t op2, size_t vl) {
1597 return vmseq_vx_u32m4_b8_m(mask, maskedoff, op1, op2, vl);
1598 }
1599
1600 // CHECK-RV64-LABEL: @test_vmseq_vv_u32m8_b4_m(
1601 // CHECK-RV64-NEXT: entry:
1602 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1603 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1604 //
test_vmseq_vv_u32m8_b4_m(vbool4_t mask,vbool4_t maskedoff,vuint32m8_t op1,vuint32m8_t op2,size_t vl)1605 vbool4_t test_vmseq_vv_u32m8_b4_m(vbool4_t mask, vbool4_t maskedoff,
1606 vuint32m8_t op1, vuint32m8_t op2, size_t vl) {
1607 return vmseq_vv_u32m8_b4_m(mask, maskedoff, op1, op2, vl);
1608 }
1609
1610 // CHECK-RV64-LABEL: @test_vmseq_vx_u32m8_b4_m(
1611 // CHECK-RV64-NEXT: entry:
1612 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i32.i32.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1613 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1614 //
test_vmseq_vx_u32m8_b4_m(vbool4_t mask,vbool4_t maskedoff,vuint32m8_t op1,uint32_t op2,size_t vl)1615 vbool4_t test_vmseq_vx_u32m8_b4_m(vbool4_t mask, vbool4_t maskedoff,
1616 vuint32m8_t op1, uint32_t op2, size_t vl) {
1617 return vmseq_vx_u32m8_b4_m(mask, maskedoff, op1, op2, vl);
1618 }
1619
1620 // CHECK-RV64-LABEL: @test_vmseq_vv_u64m1_b64_m(
1621 // CHECK-RV64-NEXT: entry:
1622 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1623 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1624 //
test_vmseq_vv_u64m1_b64_m(vbool64_t mask,vbool64_t maskedoff,vuint64m1_t op1,vuint64m1_t op2,size_t vl)1625 vbool64_t test_vmseq_vv_u64m1_b64_m(vbool64_t mask, vbool64_t maskedoff,
1626 vuint64m1_t op1, vuint64m1_t op2,
1627 size_t vl) {
1628 return vmseq_vv_u64m1_b64_m(mask, maskedoff, op1, op2, vl);
1629 }
1630
1631 // CHECK-RV64-LABEL: @test_vmseq_vx_u64m1_b64_m(
1632 // CHECK-RV64-NEXT: entry:
1633 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1634 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1635 //
test_vmseq_vx_u64m1_b64_m(vbool64_t mask,vbool64_t maskedoff,vuint64m1_t op1,uint64_t op2,size_t vl)1636 vbool64_t test_vmseq_vx_u64m1_b64_m(vbool64_t mask, vbool64_t maskedoff,
1637 vuint64m1_t op1, uint64_t op2, size_t vl) {
1638 return vmseq_vx_u64m1_b64_m(mask, maskedoff, op1, op2, vl);
1639 }
1640
1641 // CHECK-RV64-LABEL: @test_vmseq_vv_u64m2_b32_m(
1642 // CHECK-RV64-NEXT: entry:
1643 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1644 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1645 //
test_vmseq_vv_u64m2_b32_m(vbool32_t mask,vbool32_t maskedoff,vuint64m2_t op1,vuint64m2_t op2,size_t vl)1646 vbool32_t test_vmseq_vv_u64m2_b32_m(vbool32_t mask, vbool32_t maskedoff,
1647 vuint64m2_t op1, vuint64m2_t op2,
1648 size_t vl) {
1649 return vmseq_vv_u64m2_b32_m(mask, maskedoff, op1, op2, vl);
1650 }
1651
1652 // CHECK-RV64-LABEL: @test_vmseq_vx_u64m2_b32_m(
1653 // CHECK-RV64-NEXT: entry:
1654 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1655 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1656 //
test_vmseq_vx_u64m2_b32_m(vbool32_t mask,vbool32_t maskedoff,vuint64m2_t op1,uint64_t op2,size_t vl)1657 vbool32_t test_vmseq_vx_u64m2_b32_m(vbool32_t mask, vbool32_t maskedoff,
1658 vuint64m2_t op1, uint64_t op2, size_t vl) {
1659 return vmseq_vx_u64m2_b32_m(mask, maskedoff, op1, op2, vl);
1660 }
1661
1662 // CHECK-RV64-LABEL: @test_vmseq_vv_u64m4_b16_m(
1663 // CHECK-RV64-NEXT: entry:
1664 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1665 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1666 //
test_vmseq_vv_u64m4_b16_m(vbool16_t mask,vbool16_t maskedoff,vuint64m4_t op1,vuint64m4_t op2,size_t vl)1667 vbool16_t test_vmseq_vv_u64m4_b16_m(vbool16_t mask, vbool16_t maskedoff,
1668 vuint64m4_t op1, vuint64m4_t op2,
1669 size_t vl) {
1670 return vmseq_vv_u64m4_b16_m(mask, maskedoff, op1, op2, vl);
1671 }
1672
1673 // CHECK-RV64-LABEL: @test_vmseq_vx_u64m4_b16_m(
1674 // CHECK-RV64-NEXT: entry:
1675 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1676 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1677 //
test_vmseq_vx_u64m4_b16_m(vbool16_t mask,vbool16_t maskedoff,vuint64m4_t op1,uint64_t op2,size_t vl)1678 vbool16_t test_vmseq_vx_u64m4_b16_m(vbool16_t mask, vbool16_t maskedoff,
1679 vuint64m4_t op1, uint64_t op2, size_t vl) {
1680 return vmseq_vx_u64m4_b16_m(mask, maskedoff, op1, op2, vl);
1681 }
1682
1683 // CHECK-RV64-LABEL: @test_vmseq_vv_u64m8_b8_m(
1684 // CHECK-RV64-NEXT: entry:
1685 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1686 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1687 //
test_vmseq_vv_u64m8_b8_m(vbool8_t mask,vbool8_t maskedoff,vuint64m8_t op1,vuint64m8_t op2,size_t vl)1688 vbool8_t test_vmseq_vv_u64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,
1689 vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
1690 return vmseq_vv_u64m8_b8_m(mask, maskedoff, op1, op2, vl);
1691 }
1692
1693 // CHECK-RV64-LABEL: @test_vmseq_vx_u64m8_b8_m(
1694 // CHECK-RV64-NEXT: entry:
1695 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
1696 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1697 //
test_vmseq_vx_u64m8_b8_m(vbool8_t mask,vbool8_t maskedoff,vuint64m8_t op1,uint64_t op2,size_t vl)1698 vbool8_t test_vmseq_vx_u64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,
1699 vuint64m8_t op1, uint64_t op2, size_t vl) {
1700 return vmseq_vx_u64m8_b8_m(mask, maskedoff, op1, op2, vl);
1701 }
1702