1 //===---- CGBuiltin.cpp - Emit LLVM Code for builtins ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This contains code to emit Builtin calls as LLVM code. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "TargetInfo.h" 15 #include "CodeGenFunction.h" 16 #include "CodeGenModule.h" 17 #include "CGObjCRuntime.h" 18 #include "clang/Basic/TargetInfo.h" 19 #include "clang/AST/ASTContext.h" 20 #include "clang/AST/Decl.h" 21 #include "clang/Basic/TargetBuiltins.h" 22 #include "llvm/Intrinsics.h" 23 #include "llvm/Target/TargetData.h" 24 25 using namespace clang; 26 using namespace CodeGen; 27 using namespace llvm; 28 29 /// getBuiltinLibFunction - Given a builtin id for a function like 30 /// "__builtin_fabsf", return a Function* for "fabsf". 31 llvm::Value *CodeGenModule::getBuiltinLibFunction(const FunctionDecl *FD, 32 unsigned BuiltinID) { 33 assert(Context.BuiltinInfo.isLibFunction(BuiltinID)); 34 35 // Get the name, skip over the __builtin_ prefix (if necessary). 36 StringRef Name; 37 GlobalDecl D(FD); 38 39 // If the builtin has been declared explicitly with an assembler label, 40 // use the mangled name. This differs from the plain label on platforms 41 // that prefix labels. 42 if (FD->hasAttr<AsmLabelAttr>()) 43 Name = getMangledName(D); 44 else 45 Name = Context.BuiltinInfo.GetName(BuiltinID) + 10; 46 47 llvm::FunctionType *Ty = 48 cast<llvm::FunctionType>(getTypes().ConvertType(FD->getType())); 49 50 return GetOrCreateLLVMFunction(Name, Ty, D, /*ForVTable=*/false); 51 } 52 53 /// Emit the conversions required to turn the given value into an 54 /// integer of the given size. 55 static Value *EmitToInt(CodeGenFunction &CGF, llvm::Value *V, 56 QualType T, llvm::IntegerType *IntType) { 57 V = CGF.EmitToMemory(V, T); 58 59 if (V->getType()->isPointerTy()) 60 return CGF.Builder.CreatePtrToInt(V, IntType); 61 62 assert(V->getType() == IntType); 63 return V; 64 } 65 66 static Value *EmitFromInt(CodeGenFunction &CGF, llvm::Value *V, 67 QualType T, llvm::Type *ResultType) { 68 V = CGF.EmitFromMemory(V, T); 69 70 if (ResultType->isPointerTy()) 71 return CGF.Builder.CreateIntToPtr(V, ResultType); 72 73 assert(V->getType() == ResultType); 74 return V; 75 } 76 77 /// Utility to insert an atomic instruction based on Instrinsic::ID 78 /// and the expression node. 79 static RValue EmitBinaryAtomic(CodeGenFunction &CGF, 80 llvm::AtomicRMWInst::BinOp Kind, 81 const CallExpr *E) { 82 QualType T = E->getType(); 83 assert(E->getArg(0)->getType()->isPointerType()); 84 assert(CGF.getContext().hasSameUnqualifiedType(T, 85 E->getArg(0)->getType()->getPointeeType())); 86 assert(CGF.getContext().hasSameUnqualifiedType(T, E->getArg(1)->getType())); 87 88 llvm::Value *DestPtr = CGF.EmitScalarExpr(E->getArg(0)); 89 unsigned AddrSpace = 90 cast<llvm::PointerType>(DestPtr->getType())->getAddressSpace(); 91 92 llvm::IntegerType *IntType = 93 llvm::IntegerType::get(CGF.getLLVMContext(), 94 CGF.getContext().getTypeSize(T)); 95 llvm::Type *IntPtrType = IntType->getPointerTo(AddrSpace); 96 97 llvm::Value *Args[2]; 98 Args[0] = CGF.Builder.CreateBitCast(DestPtr, IntPtrType); 99 Args[1] = CGF.EmitScalarExpr(E->getArg(1)); 100 llvm::Type *ValueType = Args[1]->getType(); 101 Args[1] = EmitToInt(CGF, Args[1], T, IntType); 102 103 llvm::Value *Result = 104 CGF.Builder.CreateAtomicRMW(Kind, Args[0], Args[1], 105 llvm::SequentiallyConsistent); 106 Result = EmitFromInt(CGF, Result, T, ValueType); 107 return RValue::get(Result); 108 } 109 110 /// Utility to insert an atomic instruction based Instrinsic::ID and 111 /// the expression node, where the return value is the result of the 112 /// operation. 113 static RValue EmitBinaryAtomicPost(CodeGenFunction &CGF, 114 llvm::AtomicRMWInst::BinOp Kind, 115 const CallExpr *E, 116 Instruction::BinaryOps Op) { 117 QualType T = E->getType(); 118 assert(E->getArg(0)->getType()->isPointerType()); 119 assert(CGF.getContext().hasSameUnqualifiedType(T, 120 E->getArg(0)->getType()->getPointeeType())); 121 assert(CGF.getContext().hasSameUnqualifiedType(T, E->getArg(1)->getType())); 122 123 llvm::Value *DestPtr = CGF.EmitScalarExpr(E->getArg(0)); 124 unsigned AddrSpace = 125 cast<llvm::PointerType>(DestPtr->getType())->getAddressSpace(); 126 127 llvm::IntegerType *IntType = 128 llvm::IntegerType::get(CGF.getLLVMContext(), 129 CGF.getContext().getTypeSize(T)); 130 llvm::Type *IntPtrType = IntType->getPointerTo(AddrSpace); 131 132 llvm::Value *Args[2]; 133 Args[1] = CGF.EmitScalarExpr(E->getArg(1)); 134 llvm::Type *ValueType = Args[1]->getType(); 135 Args[1] = EmitToInt(CGF, Args[1], T, IntType); 136 Args[0] = CGF.Builder.CreateBitCast(DestPtr, IntPtrType); 137 138 llvm::Value *Result = 139 CGF.Builder.CreateAtomicRMW(Kind, Args[0], Args[1], 140 llvm::SequentiallyConsistent); 141 Result = CGF.Builder.CreateBinOp(Op, Result, Args[1]); 142 Result = EmitFromInt(CGF, Result, T, ValueType); 143 return RValue::get(Result); 144 } 145 146 /// EmitFAbs - Emit a call to fabs/fabsf/fabsl, depending on the type of ValTy, 147 /// which must be a scalar floating point type. 148 static Value *EmitFAbs(CodeGenFunction &CGF, Value *V, QualType ValTy) { 149 const BuiltinType *ValTyP = ValTy->getAs<BuiltinType>(); 150 assert(ValTyP && "isn't scalar fp type!"); 151 152 StringRef FnName; 153 switch (ValTyP->getKind()) { 154 default: llvm_unreachable("Isn't a scalar fp type!"); 155 case BuiltinType::Float: FnName = "fabsf"; break; 156 case BuiltinType::Double: FnName = "fabs"; break; 157 case BuiltinType::LongDouble: FnName = "fabsl"; break; 158 } 159 160 // The prototype is something that takes and returns whatever V's type is. 161 llvm::FunctionType *FT = llvm::FunctionType::get(V->getType(), V->getType(), 162 false); 163 llvm::Value *Fn = CGF.CGM.CreateRuntimeFunction(FT, FnName); 164 165 return CGF.Builder.CreateCall(Fn, V, "abs"); 166 } 167 168 static RValue emitLibraryCall(CodeGenFunction &CGF, const FunctionDecl *Fn, 169 const CallExpr *E, llvm::Value *calleeValue) { 170 return CGF.EmitCall(E->getCallee()->getType(), calleeValue, 171 ReturnValueSlot(), E->arg_begin(), E->arg_end(), Fn); 172 } 173 174 RValue CodeGenFunction::EmitBuiltinExpr(const FunctionDecl *FD, 175 unsigned BuiltinID, const CallExpr *E) { 176 // See if we can constant fold this builtin. If so, don't emit it at all. 177 Expr::EvalResult Result; 178 if (E->EvaluateAsRValue(Result, CGM.getContext()) && 179 !Result.hasSideEffects()) { 180 if (Result.Val.isInt()) 181 return RValue::get(llvm::ConstantInt::get(getLLVMContext(), 182 Result.Val.getInt())); 183 if (Result.Val.isFloat()) 184 return RValue::get(llvm::ConstantFP::get(getLLVMContext(), 185 Result.Val.getFloat())); 186 } 187 188 switch (BuiltinID) { 189 default: break; // Handle intrinsics and libm functions below. 190 case Builtin::BI__builtin___CFStringMakeConstantString: 191 case Builtin::BI__builtin___NSStringMakeConstantString: 192 return RValue::get(CGM.EmitConstantExpr(E, E->getType(), 0)); 193 case Builtin::BI__builtin_stdarg_start: 194 case Builtin::BI__builtin_va_start: 195 case Builtin::BI__builtin_va_end: { 196 Value *ArgValue = EmitVAListRef(E->getArg(0)); 197 llvm::Type *DestType = Int8PtrTy; 198 if (ArgValue->getType() != DestType) 199 ArgValue = Builder.CreateBitCast(ArgValue, DestType, 200 ArgValue->getName().data()); 201 202 Intrinsic::ID inst = (BuiltinID == Builtin::BI__builtin_va_end) ? 203 Intrinsic::vaend : Intrinsic::vastart; 204 return RValue::get(Builder.CreateCall(CGM.getIntrinsic(inst), ArgValue)); 205 } 206 case Builtin::BI__builtin_va_copy: { 207 Value *DstPtr = EmitVAListRef(E->getArg(0)); 208 Value *SrcPtr = EmitVAListRef(E->getArg(1)); 209 210 llvm::Type *Type = Int8PtrTy; 211 212 DstPtr = Builder.CreateBitCast(DstPtr, Type); 213 SrcPtr = Builder.CreateBitCast(SrcPtr, Type); 214 return RValue::get(Builder.CreateCall2(CGM.getIntrinsic(Intrinsic::vacopy), 215 DstPtr, SrcPtr)); 216 } 217 case Builtin::BI__builtin_abs: 218 case Builtin::BI__builtin_labs: 219 case Builtin::BI__builtin_llabs: { 220 Value *ArgValue = EmitScalarExpr(E->getArg(0)); 221 222 Value *NegOp = Builder.CreateNeg(ArgValue, "neg"); 223 Value *CmpResult = 224 Builder.CreateICmpSGE(ArgValue, 225 llvm::Constant::getNullValue(ArgValue->getType()), 226 "abscond"); 227 Value *Result = 228 Builder.CreateSelect(CmpResult, ArgValue, NegOp, "abs"); 229 230 return RValue::get(Result); 231 } 232 case Builtin::BI__builtin_ctzs: 233 case Builtin::BI__builtin_ctz: 234 case Builtin::BI__builtin_ctzl: 235 case Builtin::BI__builtin_ctzll: { 236 Value *ArgValue = EmitScalarExpr(E->getArg(0)); 237 238 llvm::Type *ArgType = ArgValue->getType(); 239 Value *F = CGM.getIntrinsic(Intrinsic::cttz, ArgType); 240 241 llvm::Type *ResultType = ConvertType(E->getType()); 242 Value *ZeroUndef = Builder.getInt1(Target.isCLZForZeroUndef()); 243 Value *Result = Builder.CreateCall2(F, ArgValue, ZeroUndef); 244 if (Result->getType() != ResultType) 245 Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true, 246 "cast"); 247 return RValue::get(Result); 248 } 249 case Builtin::BI__builtin_clzs: 250 case Builtin::BI__builtin_clz: 251 case Builtin::BI__builtin_clzl: 252 case Builtin::BI__builtin_clzll: { 253 Value *ArgValue = EmitScalarExpr(E->getArg(0)); 254 255 llvm::Type *ArgType = ArgValue->getType(); 256 Value *F = CGM.getIntrinsic(Intrinsic::ctlz, ArgType); 257 258 llvm::Type *ResultType = ConvertType(E->getType()); 259 Value *ZeroUndef = Builder.getInt1(Target.isCLZForZeroUndef()); 260 Value *Result = Builder.CreateCall2(F, ArgValue, ZeroUndef); 261 if (Result->getType() != ResultType) 262 Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true, 263 "cast"); 264 return RValue::get(Result); 265 } 266 case Builtin::BI__builtin_ffs: 267 case Builtin::BI__builtin_ffsl: 268 case Builtin::BI__builtin_ffsll: { 269 // ffs(x) -> x ? cttz(x) + 1 : 0 270 Value *ArgValue = EmitScalarExpr(E->getArg(0)); 271 272 llvm::Type *ArgType = ArgValue->getType(); 273 Value *F = CGM.getIntrinsic(Intrinsic::cttz, ArgType); 274 275 llvm::Type *ResultType = ConvertType(E->getType()); 276 Value *Tmp = Builder.CreateAdd(Builder.CreateCall2(F, ArgValue, 277 Builder.getTrue()), 278 llvm::ConstantInt::get(ArgType, 1)); 279 Value *Zero = llvm::Constant::getNullValue(ArgType); 280 Value *IsZero = Builder.CreateICmpEQ(ArgValue, Zero, "iszero"); 281 Value *Result = Builder.CreateSelect(IsZero, Zero, Tmp, "ffs"); 282 if (Result->getType() != ResultType) 283 Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true, 284 "cast"); 285 return RValue::get(Result); 286 } 287 case Builtin::BI__builtin_parity: 288 case Builtin::BI__builtin_parityl: 289 case Builtin::BI__builtin_parityll: { 290 // parity(x) -> ctpop(x) & 1 291 Value *ArgValue = EmitScalarExpr(E->getArg(0)); 292 293 llvm::Type *ArgType = ArgValue->getType(); 294 Value *F = CGM.getIntrinsic(Intrinsic::ctpop, ArgType); 295 296 llvm::Type *ResultType = ConvertType(E->getType()); 297 Value *Tmp = Builder.CreateCall(F, ArgValue); 298 Value *Result = Builder.CreateAnd(Tmp, llvm::ConstantInt::get(ArgType, 1)); 299 if (Result->getType() != ResultType) 300 Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true, 301 "cast"); 302 return RValue::get(Result); 303 } 304 case Builtin::BI__builtin_popcount: 305 case Builtin::BI__builtin_popcountl: 306 case Builtin::BI__builtin_popcountll: { 307 Value *ArgValue = EmitScalarExpr(E->getArg(0)); 308 309 llvm::Type *ArgType = ArgValue->getType(); 310 Value *F = CGM.getIntrinsic(Intrinsic::ctpop, ArgType); 311 312 llvm::Type *ResultType = ConvertType(E->getType()); 313 Value *Result = Builder.CreateCall(F, ArgValue); 314 if (Result->getType() != ResultType) 315 Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true, 316 "cast"); 317 return RValue::get(Result); 318 } 319 case Builtin::BI__builtin_expect: { 320 Value *ArgValue = EmitScalarExpr(E->getArg(0)); 321 llvm::Type *ArgType = ArgValue->getType(); 322 323 Value *FnExpect = CGM.getIntrinsic(Intrinsic::expect, ArgType); 324 Value *ExpectedValue = EmitScalarExpr(E->getArg(1)); 325 326 Value *Result = Builder.CreateCall2(FnExpect, ArgValue, ExpectedValue, 327 "expval"); 328 return RValue::get(Result); 329 } 330 case Builtin::BI__builtin_bswap32: 331 case Builtin::BI__builtin_bswap64: { 332 Value *ArgValue = EmitScalarExpr(E->getArg(0)); 333 llvm::Type *ArgType = ArgValue->getType(); 334 Value *F = CGM.getIntrinsic(Intrinsic::bswap, ArgType); 335 return RValue::get(Builder.CreateCall(F, ArgValue)); 336 } 337 case Builtin::BI__builtin_object_size: { 338 // We pass this builtin onto the optimizer so that it can 339 // figure out the object size in more complex cases. 340 llvm::Type *ResType = ConvertType(E->getType()); 341 342 // LLVM only supports 0 and 2, make sure that we pass along that 343 // as a boolean. 344 Value *Ty = EmitScalarExpr(E->getArg(1)); 345 ConstantInt *CI = dyn_cast<ConstantInt>(Ty); 346 assert(CI); 347 uint64_t val = CI->getZExtValue(); 348 CI = ConstantInt::get(Builder.getInt1Ty(), (val & 0x2) >> 1); 349 350 Value *F = CGM.getIntrinsic(Intrinsic::objectsize, ResType); 351 return RValue::get(Builder.CreateCall2(F, 352 EmitScalarExpr(E->getArg(0)), 353 CI)); 354 } 355 case Builtin::BI__builtin_prefetch: { 356 Value *Locality, *RW, *Address = EmitScalarExpr(E->getArg(0)); 357 // FIXME: Technically these constants should of type 'int', yes? 358 RW = (E->getNumArgs() > 1) ? EmitScalarExpr(E->getArg(1)) : 359 llvm::ConstantInt::get(Int32Ty, 0); 360 Locality = (E->getNumArgs() > 2) ? EmitScalarExpr(E->getArg(2)) : 361 llvm::ConstantInt::get(Int32Ty, 3); 362 Value *Data = llvm::ConstantInt::get(Int32Ty, 1); 363 Value *F = CGM.getIntrinsic(Intrinsic::prefetch); 364 return RValue::get(Builder.CreateCall4(F, Address, RW, Locality, Data)); 365 } 366 case Builtin::BI__builtin_trap: { 367 Value *F = CGM.getIntrinsic(Intrinsic::trap); 368 return RValue::get(Builder.CreateCall(F)); 369 } 370 case Builtin::BI__builtin_unreachable: { 371 if (CatchUndefined) 372 EmitBranch(getTrapBB()); 373 else 374 Builder.CreateUnreachable(); 375 376 // We do need to preserve an insertion point. 377 EmitBlock(createBasicBlock("unreachable.cont")); 378 379 return RValue::get(0); 380 } 381 382 case Builtin::BI__builtin_powi: 383 case Builtin::BI__builtin_powif: 384 case Builtin::BI__builtin_powil: { 385 Value *Base = EmitScalarExpr(E->getArg(0)); 386 Value *Exponent = EmitScalarExpr(E->getArg(1)); 387 llvm::Type *ArgType = Base->getType(); 388 Value *F = CGM.getIntrinsic(Intrinsic::powi, ArgType); 389 return RValue::get(Builder.CreateCall2(F, Base, Exponent)); 390 } 391 392 case Builtin::BI__builtin_isgreater: 393 case Builtin::BI__builtin_isgreaterequal: 394 case Builtin::BI__builtin_isless: 395 case Builtin::BI__builtin_islessequal: 396 case Builtin::BI__builtin_islessgreater: 397 case Builtin::BI__builtin_isunordered: { 398 // Ordered comparisons: we know the arguments to these are matching scalar 399 // floating point values. 400 Value *LHS = EmitScalarExpr(E->getArg(0)); 401 Value *RHS = EmitScalarExpr(E->getArg(1)); 402 403 switch (BuiltinID) { 404 default: llvm_unreachable("Unknown ordered comparison"); 405 case Builtin::BI__builtin_isgreater: 406 LHS = Builder.CreateFCmpOGT(LHS, RHS, "cmp"); 407 break; 408 case Builtin::BI__builtin_isgreaterequal: 409 LHS = Builder.CreateFCmpOGE(LHS, RHS, "cmp"); 410 break; 411 case Builtin::BI__builtin_isless: 412 LHS = Builder.CreateFCmpOLT(LHS, RHS, "cmp"); 413 break; 414 case Builtin::BI__builtin_islessequal: 415 LHS = Builder.CreateFCmpOLE(LHS, RHS, "cmp"); 416 break; 417 case Builtin::BI__builtin_islessgreater: 418 LHS = Builder.CreateFCmpONE(LHS, RHS, "cmp"); 419 break; 420 case Builtin::BI__builtin_isunordered: 421 LHS = Builder.CreateFCmpUNO(LHS, RHS, "cmp"); 422 break; 423 } 424 // ZExt bool to int type. 425 return RValue::get(Builder.CreateZExt(LHS, ConvertType(E->getType()))); 426 } 427 case Builtin::BI__builtin_isnan: { 428 Value *V = EmitScalarExpr(E->getArg(0)); 429 V = Builder.CreateFCmpUNO(V, V, "cmp"); 430 return RValue::get(Builder.CreateZExt(V, ConvertType(E->getType()))); 431 } 432 433 case Builtin::BI__builtin_isinf: { 434 // isinf(x) --> fabs(x) == infinity 435 Value *V = EmitScalarExpr(E->getArg(0)); 436 V = EmitFAbs(*this, V, E->getArg(0)->getType()); 437 438 V = Builder.CreateFCmpOEQ(V, ConstantFP::getInfinity(V->getType()),"isinf"); 439 return RValue::get(Builder.CreateZExt(V, ConvertType(E->getType()))); 440 } 441 442 // TODO: BI__builtin_isinf_sign 443 // isinf_sign(x) -> isinf(x) ? (signbit(x) ? -1 : 1) : 0 444 445 case Builtin::BI__builtin_isnormal: { 446 // isnormal(x) --> x == x && fabsf(x) < infinity && fabsf(x) >= float_min 447 Value *V = EmitScalarExpr(E->getArg(0)); 448 Value *Eq = Builder.CreateFCmpOEQ(V, V, "iseq"); 449 450 Value *Abs = EmitFAbs(*this, V, E->getArg(0)->getType()); 451 Value *IsLessThanInf = 452 Builder.CreateFCmpULT(Abs, ConstantFP::getInfinity(V->getType()),"isinf"); 453 APFloat Smallest = APFloat::getSmallestNormalized( 454 getContext().getFloatTypeSemantics(E->getArg(0)->getType())); 455 Value *IsNormal = 456 Builder.CreateFCmpUGE(Abs, ConstantFP::get(V->getContext(), Smallest), 457 "isnormal"); 458 V = Builder.CreateAnd(Eq, IsLessThanInf, "and"); 459 V = Builder.CreateAnd(V, IsNormal, "and"); 460 return RValue::get(Builder.CreateZExt(V, ConvertType(E->getType()))); 461 } 462 463 case Builtin::BI__builtin_isfinite: { 464 // isfinite(x) --> x == x && fabs(x) != infinity; 465 Value *V = EmitScalarExpr(E->getArg(0)); 466 Value *Eq = Builder.CreateFCmpOEQ(V, V, "iseq"); 467 468 Value *Abs = EmitFAbs(*this, V, E->getArg(0)->getType()); 469 Value *IsNotInf = 470 Builder.CreateFCmpUNE(Abs, ConstantFP::getInfinity(V->getType()),"isinf"); 471 472 V = Builder.CreateAnd(Eq, IsNotInf, "and"); 473 return RValue::get(Builder.CreateZExt(V, ConvertType(E->getType()))); 474 } 475 476 case Builtin::BI__builtin_fpclassify: { 477 Value *V = EmitScalarExpr(E->getArg(5)); 478 llvm::Type *Ty = ConvertType(E->getArg(5)->getType()); 479 480 // Create Result 481 BasicBlock *Begin = Builder.GetInsertBlock(); 482 BasicBlock *End = createBasicBlock("fpclassify_end", this->CurFn); 483 Builder.SetInsertPoint(End); 484 PHINode *Result = 485 Builder.CreatePHI(ConvertType(E->getArg(0)->getType()), 4, 486 "fpclassify_result"); 487 488 // if (V==0) return FP_ZERO 489 Builder.SetInsertPoint(Begin); 490 Value *IsZero = Builder.CreateFCmpOEQ(V, Constant::getNullValue(Ty), 491 "iszero"); 492 Value *ZeroLiteral = EmitScalarExpr(E->getArg(4)); 493 BasicBlock *NotZero = createBasicBlock("fpclassify_not_zero", this->CurFn); 494 Builder.CreateCondBr(IsZero, End, NotZero); 495 Result->addIncoming(ZeroLiteral, Begin); 496 497 // if (V != V) return FP_NAN 498 Builder.SetInsertPoint(NotZero); 499 Value *IsNan = Builder.CreateFCmpUNO(V, V, "cmp"); 500 Value *NanLiteral = EmitScalarExpr(E->getArg(0)); 501 BasicBlock *NotNan = createBasicBlock("fpclassify_not_nan", this->CurFn); 502 Builder.CreateCondBr(IsNan, End, NotNan); 503 Result->addIncoming(NanLiteral, NotZero); 504 505 // if (fabs(V) == infinity) return FP_INFINITY 506 Builder.SetInsertPoint(NotNan); 507 Value *VAbs = EmitFAbs(*this, V, E->getArg(5)->getType()); 508 Value *IsInf = 509 Builder.CreateFCmpOEQ(VAbs, ConstantFP::getInfinity(V->getType()), 510 "isinf"); 511 Value *InfLiteral = EmitScalarExpr(E->getArg(1)); 512 BasicBlock *NotInf = createBasicBlock("fpclassify_not_inf", this->CurFn); 513 Builder.CreateCondBr(IsInf, End, NotInf); 514 Result->addIncoming(InfLiteral, NotNan); 515 516 // if (fabs(V) >= MIN_NORMAL) return FP_NORMAL else FP_SUBNORMAL 517 Builder.SetInsertPoint(NotInf); 518 APFloat Smallest = APFloat::getSmallestNormalized( 519 getContext().getFloatTypeSemantics(E->getArg(5)->getType())); 520 Value *IsNormal = 521 Builder.CreateFCmpUGE(VAbs, ConstantFP::get(V->getContext(), Smallest), 522 "isnormal"); 523 Value *NormalResult = 524 Builder.CreateSelect(IsNormal, EmitScalarExpr(E->getArg(2)), 525 EmitScalarExpr(E->getArg(3))); 526 Builder.CreateBr(End); 527 Result->addIncoming(NormalResult, NotInf); 528 529 // return Result 530 Builder.SetInsertPoint(End); 531 return RValue::get(Result); 532 } 533 534 case Builtin::BIalloca: 535 case Builtin::BI__builtin_alloca: { 536 Value *Size = EmitScalarExpr(E->getArg(0)); 537 return RValue::get(Builder.CreateAlloca(Builder.getInt8Ty(), Size)); 538 } 539 case Builtin::BIbzero: 540 case Builtin::BI__builtin_bzero: { 541 Value *Address = EmitScalarExpr(E->getArg(0)); 542 Value *SizeVal = EmitScalarExpr(E->getArg(1)); 543 Builder.CreateMemSet(Address, Builder.getInt8(0), SizeVal, 1, false); 544 return RValue::get(Address); 545 } 546 case Builtin::BImemcpy: 547 case Builtin::BI__builtin_memcpy: { 548 Value *Address = EmitScalarExpr(E->getArg(0)); 549 Value *SrcAddr = EmitScalarExpr(E->getArg(1)); 550 Value *SizeVal = EmitScalarExpr(E->getArg(2)); 551 Builder.CreateMemCpy(Address, SrcAddr, SizeVal, 1, false); 552 return RValue::get(Address); 553 } 554 555 case Builtin::BI__builtin___memcpy_chk: { 556 // fold __builtin_memcpy_chk(x, y, cst1, cst2) to memset iff cst1<=cst2. 557 llvm::APSInt Size, DstSize; 558 if (!E->getArg(2)->EvaluateAsInt(Size, CGM.getContext()) || 559 !E->getArg(3)->EvaluateAsInt(DstSize, CGM.getContext())) 560 break; 561 if (Size.ugt(DstSize)) 562 break; 563 Value *Dest = EmitScalarExpr(E->getArg(0)); 564 Value *Src = EmitScalarExpr(E->getArg(1)); 565 Value *SizeVal = llvm::ConstantInt::get(Builder.getContext(), Size); 566 Builder.CreateMemCpy(Dest, Src, SizeVal, 1, false); 567 return RValue::get(Dest); 568 } 569 570 case Builtin::BI__builtin_objc_memmove_collectable: { 571 Value *Address = EmitScalarExpr(E->getArg(0)); 572 Value *SrcAddr = EmitScalarExpr(E->getArg(1)); 573 Value *SizeVal = EmitScalarExpr(E->getArg(2)); 574 CGM.getObjCRuntime().EmitGCMemmoveCollectable(*this, 575 Address, SrcAddr, SizeVal); 576 return RValue::get(Address); 577 } 578 579 case Builtin::BI__builtin___memmove_chk: { 580 // fold __builtin_memmove_chk(x, y, cst1, cst2) to memset iff cst1<=cst2. 581 llvm::APSInt Size, DstSize; 582 if (!E->getArg(2)->EvaluateAsInt(Size, CGM.getContext()) || 583 !E->getArg(3)->EvaluateAsInt(DstSize, CGM.getContext())) 584 break; 585 if (Size.ugt(DstSize)) 586 break; 587 Value *Dest = EmitScalarExpr(E->getArg(0)); 588 Value *Src = EmitScalarExpr(E->getArg(1)); 589 Value *SizeVal = llvm::ConstantInt::get(Builder.getContext(), Size); 590 Builder.CreateMemMove(Dest, Src, SizeVal, 1, false); 591 return RValue::get(Dest); 592 } 593 594 case Builtin::BImemmove: 595 case Builtin::BI__builtin_memmove: { 596 Value *Address = EmitScalarExpr(E->getArg(0)); 597 Value *SrcAddr = EmitScalarExpr(E->getArg(1)); 598 Value *SizeVal = EmitScalarExpr(E->getArg(2)); 599 Builder.CreateMemMove(Address, SrcAddr, SizeVal, 1, false); 600 return RValue::get(Address); 601 } 602 case Builtin::BImemset: 603 case Builtin::BI__builtin_memset: { 604 Value *Address = EmitScalarExpr(E->getArg(0)); 605 Value *ByteVal = Builder.CreateTrunc(EmitScalarExpr(E->getArg(1)), 606 Builder.getInt8Ty()); 607 Value *SizeVal = EmitScalarExpr(E->getArg(2)); 608 Builder.CreateMemSet(Address, ByteVal, SizeVal, 1, false); 609 return RValue::get(Address); 610 } 611 case Builtin::BI__builtin___memset_chk: { 612 // fold __builtin_memset_chk(x, y, cst1, cst2) to memset iff cst1<=cst2. 613 llvm::APSInt Size, DstSize; 614 if (!E->getArg(2)->EvaluateAsInt(Size, CGM.getContext()) || 615 !E->getArg(3)->EvaluateAsInt(DstSize, CGM.getContext())) 616 break; 617 if (Size.ugt(DstSize)) 618 break; 619 Value *Address = EmitScalarExpr(E->getArg(0)); 620 Value *ByteVal = Builder.CreateTrunc(EmitScalarExpr(E->getArg(1)), 621 Builder.getInt8Ty()); 622 Value *SizeVal = llvm::ConstantInt::get(Builder.getContext(), Size); 623 Builder.CreateMemSet(Address, ByteVal, SizeVal, 1, false); 624 625 return RValue::get(Address); 626 } 627 case Builtin::BI__builtin_dwarf_cfa: { 628 // The offset in bytes from the first argument to the CFA. 629 // 630 // Why on earth is this in the frontend? Is there any reason at 631 // all that the backend can't reasonably determine this while 632 // lowering llvm.eh.dwarf.cfa()? 633 // 634 // TODO: If there's a satisfactory reason, add a target hook for 635 // this instead of hard-coding 0, which is correct for most targets. 636 int32_t Offset = 0; 637 638 Value *F = CGM.getIntrinsic(Intrinsic::eh_dwarf_cfa); 639 return RValue::get(Builder.CreateCall(F, 640 llvm::ConstantInt::get(Int32Ty, Offset))); 641 } 642 case Builtin::BI__builtin_return_address: { 643 Value *Depth = EmitScalarExpr(E->getArg(0)); 644 Depth = Builder.CreateIntCast(Depth, Int32Ty, false); 645 Value *F = CGM.getIntrinsic(Intrinsic::returnaddress); 646 return RValue::get(Builder.CreateCall(F, Depth)); 647 } 648 case Builtin::BI__builtin_frame_address: { 649 Value *Depth = EmitScalarExpr(E->getArg(0)); 650 Depth = Builder.CreateIntCast(Depth, Int32Ty, false); 651 Value *F = CGM.getIntrinsic(Intrinsic::frameaddress); 652 return RValue::get(Builder.CreateCall(F, Depth)); 653 } 654 case Builtin::BI__builtin_extract_return_addr: { 655 Value *Address = EmitScalarExpr(E->getArg(0)); 656 Value *Result = getTargetHooks().decodeReturnAddress(*this, Address); 657 return RValue::get(Result); 658 } 659 case Builtin::BI__builtin_frob_return_addr: { 660 Value *Address = EmitScalarExpr(E->getArg(0)); 661 Value *Result = getTargetHooks().encodeReturnAddress(*this, Address); 662 return RValue::get(Result); 663 } 664 case Builtin::BI__builtin_dwarf_sp_column: { 665 llvm::IntegerType *Ty 666 = cast<llvm::IntegerType>(ConvertType(E->getType())); 667 int Column = getTargetHooks().getDwarfEHStackPointer(CGM); 668 if (Column == -1) { 669 CGM.ErrorUnsupported(E, "__builtin_dwarf_sp_column"); 670 return RValue::get(llvm::UndefValue::get(Ty)); 671 } 672 return RValue::get(llvm::ConstantInt::get(Ty, Column, true)); 673 } 674 case Builtin::BI__builtin_init_dwarf_reg_size_table: { 675 Value *Address = EmitScalarExpr(E->getArg(0)); 676 if (getTargetHooks().initDwarfEHRegSizeTable(*this, Address)) 677 CGM.ErrorUnsupported(E, "__builtin_init_dwarf_reg_size_table"); 678 return RValue::get(llvm::UndefValue::get(ConvertType(E->getType()))); 679 } 680 case Builtin::BI__builtin_eh_return: { 681 Value *Int = EmitScalarExpr(E->getArg(0)); 682 Value *Ptr = EmitScalarExpr(E->getArg(1)); 683 684 llvm::IntegerType *IntTy = cast<llvm::IntegerType>(Int->getType()); 685 assert((IntTy->getBitWidth() == 32 || IntTy->getBitWidth() == 64) && 686 "LLVM's __builtin_eh_return only supports 32- and 64-bit variants"); 687 Value *F = CGM.getIntrinsic(IntTy->getBitWidth() == 32 688 ? Intrinsic::eh_return_i32 689 : Intrinsic::eh_return_i64); 690 Builder.CreateCall2(F, Int, Ptr); 691 Builder.CreateUnreachable(); 692 693 // We do need to preserve an insertion point. 694 EmitBlock(createBasicBlock("builtin_eh_return.cont")); 695 696 return RValue::get(0); 697 } 698 case Builtin::BI__builtin_unwind_init: { 699 Value *F = CGM.getIntrinsic(Intrinsic::eh_unwind_init); 700 return RValue::get(Builder.CreateCall(F)); 701 } 702 case Builtin::BI__builtin_extend_pointer: { 703 // Extends a pointer to the size of an _Unwind_Word, which is 704 // uint64_t on all platforms. Generally this gets poked into a 705 // register and eventually used as an address, so if the 706 // addressing registers are wider than pointers and the platform 707 // doesn't implicitly ignore high-order bits when doing 708 // addressing, we need to make sure we zext / sext based on 709 // the platform's expectations. 710 // 711 // See: http://gcc.gnu.org/ml/gcc-bugs/2002-02/msg00237.html 712 713 // Cast the pointer to intptr_t. 714 Value *Ptr = EmitScalarExpr(E->getArg(0)); 715 Value *Result = Builder.CreatePtrToInt(Ptr, IntPtrTy, "extend.cast"); 716 717 // If that's 64 bits, we're done. 718 if (IntPtrTy->getBitWidth() == 64) 719 return RValue::get(Result); 720 721 // Otherwise, ask the codegen data what to do. 722 if (getTargetHooks().extendPointerWithSExt()) 723 return RValue::get(Builder.CreateSExt(Result, Int64Ty, "extend.sext")); 724 else 725 return RValue::get(Builder.CreateZExt(Result, Int64Ty, "extend.zext")); 726 } 727 case Builtin::BI__builtin_setjmp: { 728 // Buffer is a void**. 729 Value *Buf = EmitScalarExpr(E->getArg(0)); 730 731 // Store the frame pointer to the setjmp buffer. 732 Value *FrameAddr = 733 Builder.CreateCall(CGM.getIntrinsic(Intrinsic::frameaddress), 734 ConstantInt::get(Int32Ty, 0)); 735 Builder.CreateStore(FrameAddr, Buf); 736 737 // Store the stack pointer to the setjmp buffer. 738 Value *StackAddr = 739 Builder.CreateCall(CGM.getIntrinsic(Intrinsic::stacksave)); 740 Value *StackSaveSlot = 741 Builder.CreateGEP(Buf, ConstantInt::get(Int32Ty, 2)); 742 Builder.CreateStore(StackAddr, StackSaveSlot); 743 744 // Call LLVM's EH setjmp, which is lightweight. 745 Value *F = CGM.getIntrinsic(Intrinsic::eh_sjlj_setjmp); 746 Buf = Builder.CreateBitCast(Buf, Int8PtrTy); 747 return RValue::get(Builder.CreateCall(F, Buf)); 748 } 749 case Builtin::BI__builtin_longjmp: { 750 Value *Buf = EmitScalarExpr(E->getArg(0)); 751 Buf = Builder.CreateBitCast(Buf, Int8PtrTy); 752 753 // Call LLVM's EH longjmp, which is lightweight. 754 Builder.CreateCall(CGM.getIntrinsic(Intrinsic::eh_sjlj_longjmp), Buf); 755 756 // longjmp doesn't return; mark this as unreachable. 757 Builder.CreateUnreachable(); 758 759 // We do need to preserve an insertion point. 760 EmitBlock(createBasicBlock("longjmp.cont")); 761 762 return RValue::get(0); 763 } 764 case Builtin::BI__sync_fetch_and_add: 765 case Builtin::BI__sync_fetch_and_sub: 766 case Builtin::BI__sync_fetch_and_or: 767 case Builtin::BI__sync_fetch_and_and: 768 case Builtin::BI__sync_fetch_and_xor: 769 case Builtin::BI__sync_add_and_fetch: 770 case Builtin::BI__sync_sub_and_fetch: 771 case Builtin::BI__sync_and_and_fetch: 772 case Builtin::BI__sync_or_and_fetch: 773 case Builtin::BI__sync_xor_and_fetch: 774 case Builtin::BI__sync_val_compare_and_swap: 775 case Builtin::BI__sync_bool_compare_and_swap: 776 case Builtin::BI__sync_lock_test_and_set: 777 case Builtin::BI__sync_lock_release: 778 case Builtin::BI__sync_swap: 779 llvm_unreachable("Shouldn't make it through sema"); 780 case Builtin::BI__sync_fetch_and_add_1: 781 case Builtin::BI__sync_fetch_and_add_2: 782 case Builtin::BI__sync_fetch_and_add_4: 783 case Builtin::BI__sync_fetch_and_add_8: 784 case Builtin::BI__sync_fetch_and_add_16: 785 return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Add, E); 786 case Builtin::BI__sync_fetch_and_sub_1: 787 case Builtin::BI__sync_fetch_and_sub_2: 788 case Builtin::BI__sync_fetch_and_sub_4: 789 case Builtin::BI__sync_fetch_and_sub_8: 790 case Builtin::BI__sync_fetch_and_sub_16: 791 return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Sub, E); 792 case Builtin::BI__sync_fetch_and_or_1: 793 case Builtin::BI__sync_fetch_and_or_2: 794 case Builtin::BI__sync_fetch_and_or_4: 795 case Builtin::BI__sync_fetch_and_or_8: 796 case Builtin::BI__sync_fetch_and_or_16: 797 return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Or, E); 798 case Builtin::BI__sync_fetch_and_and_1: 799 case Builtin::BI__sync_fetch_and_and_2: 800 case Builtin::BI__sync_fetch_and_and_4: 801 case Builtin::BI__sync_fetch_and_and_8: 802 case Builtin::BI__sync_fetch_and_and_16: 803 return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::And, E); 804 case Builtin::BI__sync_fetch_and_xor_1: 805 case Builtin::BI__sync_fetch_and_xor_2: 806 case Builtin::BI__sync_fetch_and_xor_4: 807 case Builtin::BI__sync_fetch_and_xor_8: 808 case Builtin::BI__sync_fetch_and_xor_16: 809 return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Xor, E); 810 811 // Clang extensions: not overloaded yet. 812 case Builtin::BI__sync_fetch_and_min: 813 return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Min, E); 814 case Builtin::BI__sync_fetch_and_max: 815 return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Max, E); 816 case Builtin::BI__sync_fetch_and_umin: 817 return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::UMin, E); 818 case Builtin::BI__sync_fetch_and_umax: 819 return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::UMax, E); 820 821 case Builtin::BI__sync_add_and_fetch_1: 822 case Builtin::BI__sync_add_and_fetch_2: 823 case Builtin::BI__sync_add_and_fetch_4: 824 case Builtin::BI__sync_add_and_fetch_8: 825 case Builtin::BI__sync_add_and_fetch_16: 826 return EmitBinaryAtomicPost(*this, llvm::AtomicRMWInst::Add, E, 827 llvm::Instruction::Add); 828 case Builtin::BI__sync_sub_and_fetch_1: 829 case Builtin::BI__sync_sub_and_fetch_2: 830 case Builtin::BI__sync_sub_and_fetch_4: 831 case Builtin::BI__sync_sub_and_fetch_8: 832 case Builtin::BI__sync_sub_and_fetch_16: 833 return EmitBinaryAtomicPost(*this, llvm::AtomicRMWInst::Sub, E, 834 llvm::Instruction::Sub); 835 case Builtin::BI__sync_and_and_fetch_1: 836 case Builtin::BI__sync_and_and_fetch_2: 837 case Builtin::BI__sync_and_and_fetch_4: 838 case Builtin::BI__sync_and_and_fetch_8: 839 case Builtin::BI__sync_and_and_fetch_16: 840 return EmitBinaryAtomicPost(*this, llvm::AtomicRMWInst::And, E, 841 llvm::Instruction::And); 842 case Builtin::BI__sync_or_and_fetch_1: 843 case Builtin::BI__sync_or_and_fetch_2: 844 case Builtin::BI__sync_or_and_fetch_4: 845 case Builtin::BI__sync_or_and_fetch_8: 846 case Builtin::BI__sync_or_and_fetch_16: 847 return EmitBinaryAtomicPost(*this, llvm::AtomicRMWInst::Or, E, 848 llvm::Instruction::Or); 849 case Builtin::BI__sync_xor_and_fetch_1: 850 case Builtin::BI__sync_xor_and_fetch_2: 851 case Builtin::BI__sync_xor_and_fetch_4: 852 case Builtin::BI__sync_xor_and_fetch_8: 853 case Builtin::BI__sync_xor_and_fetch_16: 854 return EmitBinaryAtomicPost(*this, llvm::AtomicRMWInst::Xor, E, 855 llvm::Instruction::Xor); 856 857 case Builtin::BI__sync_val_compare_and_swap_1: 858 case Builtin::BI__sync_val_compare_and_swap_2: 859 case Builtin::BI__sync_val_compare_and_swap_4: 860 case Builtin::BI__sync_val_compare_and_swap_8: 861 case Builtin::BI__sync_val_compare_and_swap_16: { 862 QualType T = E->getType(); 863 llvm::Value *DestPtr = EmitScalarExpr(E->getArg(0)); 864 unsigned AddrSpace = 865 cast<llvm::PointerType>(DestPtr->getType())->getAddressSpace(); 866 867 llvm::IntegerType *IntType = 868 llvm::IntegerType::get(getLLVMContext(), 869 getContext().getTypeSize(T)); 870 llvm::Type *IntPtrType = IntType->getPointerTo(AddrSpace); 871 872 Value *Args[3]; 873 Args[0] = Builder.CreateBitCast(DestPtr, IntPtrType); 874 Args[1] = EmitScalarExpr(E->getArg(1)); 875 llvm::Type *ValueType = Args[1]->getType(); 876 Args[1] = EmitToInt(*this, Args[1], T, IntType); 877 Args[2] = EmitToInt(*this, EmitScalarExpr(E->getArg(2)), T, IntType); 878 879 Value *Result = Builder.CreateAtomicCmpXchg(Args[0], Args[1], Args[2], 880 llvm::SequentiallyConsistent); 881 Result = EmitFromInt(*this, Result, T, ValueType); 882 return RValue::get(Result); 883 } 884 885 case Builtin::BI__sync_bool_compare_and_swap_1: 886 case Builtin::BI__sync_bool_compare_and_swap_2: 887 case Builtin::BI__sync_bool_compare_and_swap_4: 888 case Builtin::BI__sync_bool_compare_and_swap_8: 889 case Builtin::BI__sync_bool_compare_and_swap_16: { 890 QualType T = E->getArg(1)->getType(); 891 llvm::Value *DestPtr = EmitScalarExpr(E->getArg(0)); 892 unsigned AddrSpace = 893 cast<llvm::PointerType>(DestPtr->getType())->getAddressSpace(); 894 895 llvm::IntegerType *IntType = 896 llvm::IntegerType::get(getLLVMContext(), 897 getContext().getTypeSize(T)); 898 llvm::Type *IntPtrType = IntType->getPointerTo(AddrSpace); 899 900 Value *Args[3]; 901 Args[0] = Builder.CreateBitCast(DestPtr, IntPtrType); 902 Args[1] = EmitToInt(*this, EmitScalarExpr(E->getArg(1)), T, IntType); 903 Args[2] = EmitToInt(*this, EmitScalarExpr(E->getArg(2)), T, IntType); 904 905 Value *OldVal = Args[1]; 906 Value *PrevVal = Builder.CreateAtomicCmpXchg(Args[0], Args[1], Args[2], 907 llvm::SequentiallyConsistent); 908 Value *Result = Builder.CreateICmpEQ(PrevVal, OldVal); 909 // zext bool to int. 910 Result = Builder.CreateZExt(Result, ConvertType(E->getType())); 911 return RValue::get(Result); 912 } 913 914 case Builtin::BI__sync_swap_1: 915 case Builtin::BI__sync_swap_2: 916 case Builtin::BI__sync_swap_4: 917 case Builtin::BI__sync_swap_8: 918 case Builtin::BI__sync_swap_16: 919 return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Xchg, E); 920 921 case Builtin::BI__sync_lock_test_and_set_1: 922 case Builtin::BI__sync_lock_test_and_set_2: 923 case Builtin::BI__sync_lock_test_and_set_4: 924 case Builtin::BI__sync_lock_test_and_set_8: 925 case Builtin::BI__sync_lock_test_and_set_16: 926 return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Xchg, E); 927 928 case Builtin::BI__sync_lock_release_1: 929 case Builtin::BI__sync_lock_release_2: 930 case Builtin::BI__sync_lock_release_4: 931 case Builtin::BI__sync_lock_release_8: 932 case Builtin::BI__sync_lock_release_16: { 933 Value *Ptr = EmitScalarExpr(E->getArg(0)); 934 llvm::Type *ElLLVMTy = 935 cast<llvm::PointerType>(Ptr->getType())->getElementType(); 936 llvm::StoreInst *Store = 937 Builder.CreateStore(llvm::Constant::getNullValue(ElLLVMTy), Ptr); 938 QualType ElTy = E->getArg(0)->getType()->getPointeeType(); 939 CharUnits StoreSize = getContext().getTypeSizeInChars(ElTy); 940 Store->setAlignment(StoreSize.getQuantity()); 941 Store->setAtomic(llvm::Release); 942 return RValue::get(0); 943 } 944 945 case Builtin::BI__sync_synchronize: { 946 // We assume this is supposed to correspond to a C++0x-style 947 // sequentially-consistent fence (i.e. this is only usable for 948 // synchonization, not device I/O or anything like that). This intrinsic 949 // is really badly designed in the sense that in theory, there isn't 950 // any way to safely use it... but in practice, it mostly works 951 // to use it with non-atomic loads and stores to get acquire/release 952 // semantics. 953 Builder.CreateFence(llvm::SequentiallyConsistent); 954 return RValue::get(0); 955 } 956 957 case Builtin::BI__atomic_thread_fence: 958 case Builtin::BI__atomic_signal_fence: { 959 llvm::SynchronizationScope Scope; 960 if (BuiltinID == Builtin::BI__atomic_signal_fence) 961 Scope = llvm::SingleThread; 962 else 963 Scope = llvm::CrossThread; 964 Value *Order = EmitScalarExpr(E->getArg(0)); 965 if (isa<llvm::ConstantInt>(Order)) { 966 int ord = cast<llvm::ConstantInt>(Order)->getZExtValue(); 967 switch (ord) { 968 case 0: // memory_order_relaxed 969 default: // invalid order 970 break; 971 case 1: // memory_order_consume 972 case 2: // memory_order_acquire 973 Builder.CreateFence(llvm::Acquire, Scope); 974 break; 975 case 3: // memory_order_release 976 Builder.CreateFence(llvm::Release, Scope); 977 break; 978 case 4: // memory_order_acq_rel 979 Builder.CreateFence(llvm::AcquireRelease, Scope); 980 break; 981 case 5: // memory_order_seq_cst 982 Builder.CreateFence(llvm::SequentiallyConsistent, Scope); 983 break; 984 } 985 return RValue::get(0); 986 } 987 988 llvm::BasicBlock *AcquireBB, *ReleaseBB, *AcqRelBB, *SeqCstBB; 989 AcquireBB = createBasicBlock("acquire", CurFn); 990 ReleaseBB = createBasicBlock("release", CurFn); 991 AcqRelBB = createBasicBlock("acqrel", CurFn); 992 SeqCstBB = createBasicBlock("seqcst", CurFn); 993 llvm::BasicBlock *ContBB = createBasicBlock("atomic.continue", CurFn); 994 995 Order = Builder.CreateIntCast(Order, Builder.getInt32Ty(), false); 996 llvm::SwitchInst *SI = Builder.CreateSwitch(Order, ContBB); 997 998 Builder.SetInsertPoint(AcquireBB); 999 Builder.CreateFence(llvm::Acquire, Scope); 1000 Builder.CreateBr(ContBB); 1001 SI->addCase(Builder.getInt32(1), AcquireBB); 1002 SI->addCase(Builder.getInt32(2), AcquireBB); 1003 1004 Builder.SetInsertPoint(ReleaseBB); 1005 Builder.CreateFence(llvm::Release, Scope); 1006 Builder.CreateBr(ContBB); 1007 SI->addCase(Builder.getInt32(3), ReleaseBB); 1008 1009 Builder.SetInsertPoint(AcqRelBB); 1010 Builder.CreateFence(llvm::AcquireRelease, Scope); 1011 Builder.CreateBr(ContBB); 1012 SI->addCase(Builder.getInt32(4), AcqRelBB); 1013 1014 Builder.SetInsertPoint(SeqCstBB); 1015 Builder.CreateFence(llvm::SequentiallyConsistent, Scope); 1016 Builder.CreateBr(ContBB); 1017 SI->addCase(Builder.getInt32(5), SeqCstBB); 1018 1019 Builder.SetInsertPoint(ContBB); 1020 return RValue::get(0); 1021 } 1022 1023 // Library functions with special handling. 1024 case Builtin::BIsqrt: 1025 case Builtin::BIsqrtf: 1026 case Builtin::BIsqrtl: { 1027 // TODO: there is currently no set of optimizer flags 1028 // sufficient for us to rewrite sqrt to @llvm.sqrt. 1029 // -fmath-errno=0 is not good enough; we need finiteness. 1030 // We could probably precondition the call with an ult 1031 // against 0, but is that worth the complexity? 1032 break; 1033 } 1034 1035 case Builtin::BIpow: 1036 case Builtin::BIpowf: 1037 case Builtin::BIpowl: { 1038 // Rewrite sqrt to intrinsic if allowed. 1039 if (!FD->hasAttr<ConstAttr>()) 1040 break; 1041 Value *Base = EmitScalarExpr(E->getArg(0)); 1042 Value *Exponent = EmitScalarExpr(E->getArg(1)); 1043 llvm::Type *ArgType = Base->getType(); 1044 Value *F = CGM.getIntrinsic(Intrinsic::pow, ArgType); 1045 return RValue::get(Builder.CreateCall2(F, Base, Exponent)); 1046 } 1047 1048 case Builtin::BIfma: 1049 case Builtin::BIfmaf: 1050 case Builtin::BIfmal: 1051 case Builtin::BI__builtin_fma: 1052 case Builtin::BI__builtin_fmaf: 1053 case Builtin::BI__builtin_fmal: { 1054 // Rewrite fma to intrinsic. 1055 Value *FirstArg = EmitScalarExpr(E->getArg(0)); 1056 llvm::Type *ArgType = FirstArg->getType(); 1057 Value *F = CGM.getIntrinsic(Intrinsic::fma, ArgType); 1058 return RValue::get(Builder.CreateCall3(F, FirstArg, 1059 EmitScalarExpr(E->getArg(1)), 1060 EmitScalarExpr(E->getArg(2)))); 1061 } 1062 1063 case Builtin::BI__builtin_signbit: 1064 case Builtin::BI__builtin_signbitf: 1065 case Builtin::BI__builtin_signbitl: { 1066 LLVMContext &C = CGM.getLLVMContext(); 1067 1068 Value *Arg = EmitScalarExpr(E->getArg(0)); 1069 llvm::Type *ArgTy = Arg->getType(); 1070 if (ArgTy->isPPC_FP128Ty()) 1071 break; // FIXME: I'm not sure what the right implementation is here. 1072 int ArgWidth = ArgTy->getPrimitiveSizeInBits(); 1073 llvm::Type *ArgIntTy = llvm::IntegerType::get(C, ArgWidth); 1074 Value *BCArg = Builder.CreateBitCast(Arg, ArgIntTy); 1075 Value *ZeroCmp = llvm::Constant::getNullValue(ArgIntTy); 1076 Value *Result = Builder.CreateICmpSLT(BCArg, ZeroCmp); 1077 return RValue::get(Builder.CreateZExt(Result, ConvertType(E->getType()))); 1078 } 1079 case Builtin::BI__builtin_annotation: { 1080 llvm::Value *AnnVal = EmitScalarExpr(E->getArg(0)); 1081 llvm::Value *F = CGM.getIntrinsic(llvm::Intrinsic::annotation, 1082 AnnVal->getType()); 1083 1084 // Get the annotation string, go through casts. Sema requires this to be a 1085 // non-wide string literal, potentially casted, so the cast<> is safe. 1086 const Expr *AnnotationStrExpr = E->getArg(1)->IgnoreParenCasts(); 1087 llvm::StringRef Str = cast<StringLiteral>(AnnotationStrExpr)->getString(); 1088 return RValue::get(EmitAnnotationCall(F, AnnVal, Str, E->getExprLoc())); 1089 } 1090 } 1091 1092 // If this is an alias for a lib function (e.g. __builtin_sin), emit 1093 // the call using the normal call path, but using the unmangled 1094 // version of the function name. 1095 if (getContext().BuiltinInfo.isLibFunction(BuiltinID)) 1096 return emitLibraryCall(*this, FD, E, 1097 CGM.getBuiltinLibFunction(FD, BuiltinID)); 1098 1099 // If this is a predefined lib function (e.g. malloc), emit the call 1100 // using exactly the normal call path. 1101 if (getContext().BuiltinInfo.isPredefinedLibFunction(BuiltinID)) 1102 return emitLibraryCall(*this, FD, E, EmitScalarExpr(E->getCallee())); 1103 1104 // See if we have a target specific intrinsic. 1105 const char *Name = getContext().BuiltinInfo.GetName(BuiltinID); 1106 Intrinsic::ID IntrinsicID = Intrinsic::not_intrinsic; 1107 if (const char *Prefix = 1108 llvm::Triple::getArchTypePrefix(Target.getTriple().getArch())) 1109 IntrinsicID = Intrinsic::getIntrinsicForGCCBuiltin(Prefix, Name); 1110 1111 if (IntrinsicID != Intrinsic::not_intrinsic) { 1112 SmallVector<Value*, 16> Args; 1113 1114 // Find out if any arguments are required to be integer constant 1115 // expressions. 1116 unsigned ICEArguments = 0; 1117 ASTContext::GetBuiltinTypeError Error; 1118 getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments); 1119 assert(Error == ASTContext::GE_None && "Should not codegen an error"); 1120 1121 Function *F = CGM.getIntrinsic(IntrinsicID); 1122 llvm::FunctionType *FTy = F->getFunctionType(); 1123 1124 for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) { 1125 Value *ArgValue; 1126 // If this is a normal argument, just emit it as a scalar. 1127 if ((ICEArguments & (1 << i)) == 0) { 1128 ArgValue = EmitScalarExpr(E->getArg(i)); 1129 } else { 1130 // If this is required to be a constant, constant fold it so that we 1131 // know that the generated intrinsic gets a ConstantInt. 1132 llvm::APSInt Result; 1133 bool IsConst = E->getArg(i)->isIntegerConstantExpr(Result,getContext()); 1134 assert(IsConst && "Constant arg isn't actually constant?"); 1135 (void)IsConst; 1136 ArgValue = llvm::ConstantInt::get(getLLVMContext(), Result); 1137 } 1138 1139 // If the intrinsic arg type is different from the builtin arg type 1140 // we need to do a bit cast. 1141 llvm::Type *PTy = FTy->getParamType(i); 1142 if (PTy != ArgValue->getType()) { 1143 assert(PTy->canLosslesslyBitCastTo(FTy->getParamType(i)) && 1144 "Must be able to losslessly bit cast to param"); 1145 ArgValue = Builder.CreateBitCast(ArgValue, PTy); 1146 } 1147 1148 Args.push_back(ArgValue); 1149 } 1150 1151 Value *V = Builder.CreateCall(F, Args); 1152 QualType BuiltinRetType = E->getType(); 1153 1154 llvm::Type *RetTy = VoidTy; 1155 if (!BuiltinRetType->isVoidType()) 1156 RetTy = ConvertType(BuiltinRetType); 1157 1158 if (RetTy != V->getType()) { 1159 assert(V->getType()->canLosslesslyBitCastTo(RetTy) && 1160 "Must be able to losslessly bit cast result type"); 1161 V = Builder.CreateBitCast(V, RetTy); 1162 } 1163 1164 return RValue::get(V); 1165 } 1166 1167 // See if we have a target specific builtin that needs to be lowered. 1168 if (Value *V = EmitTargetBuiltinExpr(BuiltinID, E)) 1169 return RValue::get(V); 1170 1171 ErrorUnsupported(E, "builtin function"); 1172 1173 // Unknown builtin, for now just dump it out and return undef. 1174 if (hasAggregateLLVMType(E->getType())) 1175 return RValue::getAggregate(CreateMemTemp(E->getType())); 1176 return RValue::get(llvm::UndefValue::get(ConvertType(E->getType()))); 1177 } 1178 1179 Value *CodeGenFunction::EmitTargetBuiltinExpr(unsigned BuiltinID, 1180 const CallExpr *E) { 1181 switch (Target.getTriple().getArch()) { 1182 case llvm::Triple::arm: 1183 case llvm::Triple::thumb: 1184 return EmitARMBuiltinExpr(BuiltinID, E); 1185 case llvm::Triple::x86: 1186 case llvm::Triple::x86_64: 1187 return EmitX86BuiltinExpr(BuiltinID, E); 1188 case llvm::Triple::ppc: 1189 case llvm::Triple::ppc64: 1190 return EmitPPCBuiltinExpr(BuiltinID, E); 1191 case llvm::Triple::hexagon: 1192 return EmitHexagonBuiltinExpr(BuiltinID, E); 1193 default: 1194 return 0; 1195 } 1196 } 1197 1198 static llvm::VectorType *GetNeonType(CodeGenFunction *CGF, 1199 NeonTypeFlags TypeFlags) { 1200 int IsQuad = TypeFlags.isQuad(); 1201 switch (TypeFlags.getEltType()) { 1202 case NeonTypeFlags::Int8: 1203 case NeonTypeFlags::Poly8: 1204 return llvm::VectorType::get(CGF->Int8Ty, 8 << IsQuad); 1205 case NeonTypeFlags::Int16: 1206 case NeonTypeFlags::Poly16: 1207 case NeonTypeFlags::Float16: 1208 return llvm::VectorType::get(CGF->Int16Ty, 4 << IsQuad); 1209 case NeonTypeFlags::Int32: 1210 return llvm::VectorType::get(CGF->Int32Ty, 2 << IsQuad); 1211 case NeonTypeFlags::Int64: 1212 return llvm::VectorType::get(CGF->Int64Ty, 1 << IsQuad); 1213 case NeonTypeFlags::Float32: 1214 return llvm::VectorType::get(CGF->FloatTy, 2 << IsQuad); 1215 } 1216 llvm_unreachable("Invalid NeonTypeFlags element type!"); 1217 } 1218 1219 Value *CodeGenFunction::EmitNeonSplat(Value *V, Constant *C) { 1220 unsigned nElts = cast<llvm::VectorType>(V->getType())->getNumElements(); 1221 Value* SV = llvm::ConstantVector::getSplat(nElts, C); 1222 return Builder.CreateShuffleVector(V, V, SV, "lane"); 1223 } 1224 1225 Value *CodeGenFunction::EmitNeonCall(Function *F, SmallVectorImpl<Value*> &Ops, 1226 const char *name, 1227 unsigned shift, bool rightshift) { 1228 unsigned j = 0; 1229 for (Function::const_arg_iterator ai = F->arg_begin(), ae = F->arg_end(); 1230 ai != ae; ++ai, ++j) 1231 if (shift > 0 && shift == j) 1232 Ops[j] = EmitNeonShiftVector(Ops[j], ai->getType(), rightshift); 1233 else 1234 Ops[j] = Builder.CreateBitCast(Ops[j], ai->getType(), name); 1235 1236 return Builder.CreateCall(F, Ops, name); 1237 } 1238 1239 Value *CodeGenFunction::EmitNeonShiftVector(Value *V, llvm::Type *Ty, 1240 bool neg) { 1241 int SV = cast<ConstantInt>(V)->getSExtValue(); 1242 1243 llvm::VectorType *VTy = cast<llvm::VectorType>(Ty); 1244 llvm::Constant *C = ConstantInt::get(VTy->getElementType(), neg ? -SV : SV); 1245 return llvm::ConstantVector::getSplat(VTy->getNumElements(), C); 1246 } 1247 1248 /// GetPointeeAlignment - Given an expression with a pointer type, find the 1249 /// alignment of the type referenced by the pointer. Skip over implicit 1250 /// casts. 1251 static Value *GetPointeeAlignment(CodeGenFunction &CGF, const Expr *Addr) { 1252 unsigned Align = 1; 1253 // Check if the type is a pointer. The implicit cast operand might not be. 1254 while (Addr->getType()->isPointerType()) { 1255 QualType PtTy = Addr->getType()->getPointeeType(); 1256 unsigned NewA = CGF.getContext().getTypeAlignInChars(PtTy).getQuantity(); 1257 if (NewA > Align) 1258 Align = NewA; 1259 1260 // If the address is an implicit cast, repeat with the cast operand. 1261 if (const ImplicitCastExpr *CastAddr = dyn_cast<ImplicitCastExpr>(Addr)) { 1262 Addr = CastAddr->getSubExpr(); 1263 continue; 1264 } 1265 break; 1266 } 1267 return llvm::ConstantInt::get(CGF.Int32Ty, Align); 1268 } 1269 1270 Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID, 1271 const CallExpr *E) { 1272 if (BuiltinID == ARM::BI__clear_cache) { 1273 const FunctionDecl *FD = E->getDirectCallee(); 1274 // Oddly people write this call without args on occasion and gcc accepts 1275 // it - it's also marked as varargs in the description file. 1276 SmallVector<Value*, 2> Ops; 1277 for (unsigned i = 0; i < E->getNumArgs(); i++) 1278 Ops.push_back(EmitScalarExpr(E->getArg(i))); 1279 llvm::Type *Ty = CGM.getTypes().ConvertType(FD->getType()); 1280 llvm::FunctionType *FTy = cast<llvm::FunctionType>(Ty); 1281 StringRef Name = FD->getName(); 1282 return Builder.CreateCall(CGM.CreateRuntimeFunction(FTy, Name), Ops); 1283 } 1284 1285 if (BuiltinID == ARM::BI__builtin_arm_ldrexd) { 1286 Function *F = CGM.getIntrinsic(Intrinsic::arm_ldrexd); 1287 1288 Value *LdPtr = EmitScalarExpr(E->getArg(0)); 1289 Value *Val = Builder.CreateCall(F, LdPtr, "ldrexd"); 1290 1291 Value *Val0 = Builder.CreateExtractValue(Val, 1); 1292 Value *Val1 = Builder.CreateExtractValue(Val, 0); 1293 Val0 = Builder.CreateZExt(Val0, Int64Ty); 1294 Val1 = Builder.CreateZExt(Val1, Int64Ty); 1295 1296 Value *ShiftCst = llvm::ConstantInt::get(Int64Ty, 32); 1297 Val = Builder.CreateShl(Val0, ShiftCst, "shl", true /* nuw */); 1298 return Builder.CreateOr(Val, Val1); 1299 } 1300 1301 if (BuiltinID == ARM::BI__builtin_arm_strexd) { 1302 Function *F = CGM.getIntrinsic(Intrinsic::arm_strexd); 1303 llvm::Type *STy = llvm::StructType::get(Int32Ty, Int32Ty, NULL); 1304 1305 Value *One = llvm::ConstantInt::get(Int32Ty, 1); 1306 Value *Tmp = Builder.CreateAlloca(Int64Ty, One); 1307 Value *Val = EmitScalarExpr(E->getArg(0)); 1308 Builder.CreateStore(Val, Tmp); 1309 1310 Value *LdPtr = Builder.CreateBitCast(Tmp,llvm::PointerType::getUnqual(STy)); 1311 Val = Builder.CreateLoad(LdPtr); 1312 1313 Value *Arg0 = Builder.CreateExtractValue(Val, 0); 1314 Value *Arg1 = Builder.CreateExtractValue(Val, 1); 1315 Value *StPtr = EmitScalarExpr(E->getArg(1)); 1316 return Builder.CreateCall3(F, Arg0, Arg1, StPtr, "strexd"); 1317 } 1318 1319 SmallVector<Value*, 4> Ops; 1320 for (unsigned i = 0, e = E->getNumArgs() - 1; i != e; i++) 1321 Ops.push_back(EmitScalarExpr(E->getArg(i))); 1322 1323 // vget_lane and vset_lane are not overloaded and do not have an extra 1324 // argument that specifies the vector type. 1325 switch (BuiltinID) { 1326 default: break; 1327 case ARM::BI__builtin_neon_vget_lane_i8: 1328 case ARM::BI__builtin_neon_vget_lane_i16: 1329 case ARM::BI__builtin_neon_vget_lane_i32: 1330 case ARM::BI__builtin_neon_vget_lane_i64: 1331 case ARM::BI__builtin_neon_vget_lane_f32: 1332 case ARM::BI__builtin_neon_vgetq_lane_i8: 1333 case ARM::BI__builtin_neon_vgetq_lane_i16: 1334 case ARM::BI__builtin_neon_vgetq_lane_i32: 1335 case ARM::BI__builtin_neon_vgetq_lane_i64: 1336 case ARM::BI__builtin_neon_vgetq_lane_f32: 1337 return Builder.CreateExtractElement(Ops[0], EmitScalarExpr(E->getArg(1)), 1338 "vget_lane"); 1339 case ARM::BI__builtin_neon_vset_lane_i8: 1340 case ARM::BI__builtin_neon_vset_lane_i16: 1341 case ARM::BI__builtin_neon_vset_lane_i32: 1342 case ARM::BI__builtin_neon_vset_lane_i64: 1343 case ARM::BI__builtin_neon_vset_lane_f32: 1344 case ARM::BI__builtin_neon_vsetq_lane_i8: 1345 case ARM::BI__builtin_neon_vsetq_lane_i16: 1346 case ARM::BI__builtin_neon_vsetq_lane_i32: 1347 case ARM::BI__builtin_neon_vsetq_lane_i64: 1348 case ARM::BI__builtin_neon_vsetq_lane_f32: 1349 Ops.push_back(EmitScalarExpr(E->getArg(2))); 1350 return Builder.CreateInsertElement(Ops[1], Ops[0], Ops[2], "vset_lane"); 1351 } 1352 1353 // Get the last argument, which specifies the vector type. 1354 llvm::APSInt Result; 1355 const Expr *Arg = E->getArg(E->getNumArgs()-1); 1356 if (!Arg->isIntegerConstantExpr(Result, getContext())) 1357 return 0; 1358 1359 if (BuiltinID == ARM::BI__builtin_arm_vcvtr_f || 1360 BuiltinID == ARM::BI__builtin_arm_vcvtr_d) { 1361 // Determine the overloaded type of this builtin. 1362 llvm::Type *Ty; 1363 if (BuiltinID == ARM::BI__builtin_arm_vcvtr_f) 1364 Ty = FloatTy; 1365 else 1366 Ty = DoubleTy; 1367 1368 // Determine whether this is an unsigned conversion or not. 1369 bool usgn = Result.getZExtValue() == 1; 1370 unsigned Int = usgn ? Intrinsic::arm_vcvtru : Intrinsic::arm_vcvtr; 1371 1372 // Call the appropriate intrinsic. 1373 Function *F = CGM.getIntrinsic(Int, Ty); 1374 return Builder.CreateCall(F, Ops, "vcvtr"); 1375 } 1376 1377 // Determine the type of this overloaded NEON intrinsic. 1378 NeonTypeFlags Type(Result.getZExtValue()); 1379 bool usgn = Type.isUnsigned(); 1380 bool quad = Type.isQuad(); 1381 bool rightShift = false; 1382 1383 llvm::VectorType *VTy = GetNeonType(this, Type); 1384 llvm::Type *Ty = VTy; 1385 if (!Ty) 1386 return 0; 1387 1388 unsigned Int; 1389 switch (BuiltinID) { 1390 default: return 0; 1391 case ARM::BI__builtin_neon_vabd_v: 1392 case ARM::BI__builtin_neon_vabdq_v: 1393 Int = usgn ? Intrinsic::arm_neon_vabdu : Intrinsic::arm_neon_vabds; 1394 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vabd"); 1395 case ARM::BI__builtin_neon_vabs_v: 1396 case ARM::BI__builtin_neon_vabsq_v: 1397 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vabs, Ty), 1398 Ops, "vabs"); 1399 case ARM::BI__builtin_neon_vaddhn_v: 1400 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vaddhn, Ty), 1401 Ops, "vaddhn"); 1402 case ARM::BI__builtin_neon_vcale_v: 1403 std::swap(Ops[0], Ops[1]); 1404 case ARM::BI__builtin_neon_vcage_v: { 1405 Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vacged); 1406 return EmitNeonCall(F, Ops, "vcage"); 1407 } 1408 case ARM::BI__builtin_neon_vcaleq_v: 1409 std::swap(Ops[0], Ops[1]); 1410 case ARM::BI__builtin_neon_vcageq_v: { 1411 Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vacgeq); 1412 return EmitNeonCall(F, Ops, "vcage"); 1413 } 1414 case ARM::BI__builtin_neon_vcalt_v: 1415 std::swap(Ops[0], Ops[1]); 1416 case ARM::BI__builtin_neon_vcagt_v: { 1417 Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vacgtd); 1418 return EmitNeonCall(F, Ops, "vcagt"); 1419 } 1420 case ARM::BI__builtin_neon_vcaltq_v: 1421 std::swap(Ops[0], Ops[1]); 1422 case ARM::BI__builtin_neon_vcagtq_v: { 1423 Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vacgtq); 1424 return EmitNeonCall(F, Ops, "vcagt"); 1425 } 1426 case ARM::BI__builtin_neon_vcls_v: 1427 case ARM::BI__builtin_neon_vclsq_v: { 1428 Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vcls, Ty); 1429 return EmitNeonCall(F, Ops, "vcls"); 1430 } 1431 case ARM::BI__builtin_neon_vclz_v: 1432 case ARM::BI__builtin_neon_vclzq_v: { 1433 Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vclz, Ty); 1434 return EmitNeonCall(F, Ops, "vclz"); 1435 } 1436 case ARM::BI__builtin_neon_vcnt_v: 1437 case ARM::BI__builtin_neon_vcntq_v: { 1438 Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vcnt, Ty); 1439 return EmitNeonCall(F, Ops, "vcnt"); 1440 } 1441 case ARM::BI__builtin_neon_vcvt_f16_v: { 1442 assert(Type.getEltType() == NeonTypeFlags::Float16 && !quad && 1443 "unexpected vcvt_f16_v builtin"); 1444 Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vcvtfp2hf); 1445 return EmitNeonCall(F, Ops, "vcvt"); 1446 } 1447 case ARM::BI__builtin_neon_vcvt_f32_f16: { 1448 assert(Type.getEltType() == NeonTypeFlags::Float16 && !quad && 1449 "unexpected vcvt_f32_f16 builtin"); 1450 Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vcvthf2fp); 1451 return EmitNeonCall(F, Ops, "vcvt"); 1452 } 1453 case ARM::BI__builtin_neon_vcvt_f32_v: 1454 case ARM::BI__builtin_neon_vcvtq_f32_v: 1455 Ops[0] = Builder.CreateBitCast(Ops[0], Ty); 1456 Ty = GetNeonType(this, NeonTypeFlags(NeonTypeFlags::Float32, false, quad)); 1457 return usgn ? Builder.CreateUIToFP(Ops[0], Ty, "vcvt") 1458 : Builder.CreateSIToFP(Ops[0], Ty, "vcvt"); 1459 case ARM::BI__builtin_neon_vcvt_s32_v: 1460 case ARM::BI__builtin_neon_vcvt_u32_v: 1461 case ARM::BI__builtin_neon_vcvtq_s32_v: 1462 case ARM::BI__builtin_neon_vcvtq_u32_v: { 1463 llvm::Type *FloatTy = 1464 GetNeonType(this, NeonTypeFlags(NeonTypeFlags::Float32, false, quad)); 1465 Ops[0] = Builder.CreateBitCast(Ops[0], FloatTy); 1466 return usgn ? Builder.CreateFPToUI(Ops[0], Ty, "vcvt") 1467 : Builder.CreateFPToSI(Ops[0], Ty, "vcvt"); 1468 } 1469 case ARM::BI__builtin_neon_vcvt_n_f32_v: 1470 case ARM::BI__builtin_neon_vcvtq_n_f32_v: { 1471 llvm::Type *FloatTy = 1472 GetNeonType(this, NeonTypeFlags(NeonTypeFlags::Float32, false, quad)); 1473 llvm::Type *Tys[2] = { FloatTy, Ty }; 1474 Int = usgn ? Intrinsic::arm_neon_vcvtfxu2fp 1475 : Intrinsic::arm_neon_vcvtfxs2fp; 1476 Function *F = CGM.getIntrinsic(Int, Tys); 1477 return EmitNeonCall(F, Ops, "vcvt_n"); 1478 } 1479 case ARM::BI__builtin_neon_vcvt_n_s32_v: 1480 case ARM::BI__builtin_neon_vcvt_n_u32_v: 1481 case ARM::BI__builtin_neon_vcvtq_n_s32_v: 1482 case ARM::BI__builtin_neon_vcvtq_n_u32_v: { 1483 llvm::Type *FloatTy = 1484 GetNeonType(this, NeonTypeFlags(NeonTypeFlags::Float32, false, quad)); 1485 llvm::Type *Tys[2] = { Ty, FloatTy }; 1486 Int = usgn ? Intrinsic::arm_neon_vcvtfp2fxu 1487 : Intrinsic::arm_neon_vcvtfp2fxs; 1488 Function *F = CGM.getIntrinsic(Int, Tys); 1489 return EmitNeonCall(F, Ops, "vcvt_n"); 1490 } 1491 case ARM::BI__builtin_neon_vext_v: 1492 case ARM::BI__builtin_neon_vextq_v: { 1493 int CV = cast<ConstantInt>(Ops[2])->getSExtValue(); 1494 SmallVector<Constant*, 16> Indices; 1495 for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) 1496 Indices.push_back(ConstantInt::get(Int32Ty, i+CV)); 1497 1498 Ops[0] = Builder.CreateBitCast(Ops[0], Ty); 1499 Ops[1] = Builder.CreateBitCast(Ops[1], Ty); 1500 Value *SV = llvm::ConstantVector::get(Indices); 1501 return Builder.CreateShuffleVector(Ops[0], Ops[1], SV, "vext"); 1502 } 1503 case ARM::BI__builtin_neon_vhadd_v: 1504 case ARM::BI__builtin_neon_vhaddq_v: 1505 Int = usgn ? Intrinsic::arm_neon_vhaddu : Intrinsic::arm_neon_vhadds; 1506 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vhadd"); 1507 case ARM::BI__builtin_neon_vhsub_v: 1508 case ARM::BI__builtin_neon_vhsubq_v: 1509 Int = usgn ? Intrinsic::arm_neon_vhsubu : Intrinsic::arm_neon_vhsubs; 1510 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vhsub"); 1511 case ARM::BI__builtin_neon_vld1_v: 1512 case ARM::BI__builtin_neon_vld1q_v: 1513 Ops.push_back(GetPointeeAlignment(*this, E->getArg(0))); 1514 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vld1, Ty), 1515 Ops, "vld1"); 1516 case ARM::BI__builtin_neon_vld1_lane_v: 1517 case ARM::BI__builtin_neon_vld1q_lane_v: { 1518 Ops[1] = Builder.CreateBitCast(Ops[1], Ty); 1519 Ty = llvm::PointerType::getUnqual(VTy->getElementType()); 1520 Ops[0] = Builder.CreateBitCast(Ops[0], Ty); 1521 LoadInst *Ld = Builder.CreateLoad(Ops[0]); 1522 Value *Align = GetPointeeAlignment(*this, E->getArg(0)); 1523 Ld->setAlignment(cast<ConstantInt>(Align)->getZExtValue()); 1524 return Builder.CreateInsertElement(Ops[1], Ld, Ops[2], "vld1_lane"); 1525 } 1526 case ARM::BI__builtin_neon_vld1_dup_v: 1527 case ARM::BI__builtin_neon_vld1q_dup_v: { 1528 Value *V = UndefValue::get(Ty); 1529 Ty = llvm::PointerType::getUnqual(VTy->getElementType()); 1530 Ops[0] = Builder.CreateBitCast(Ops[0], Ty); 1531 LoadInst *Ld = Builder.CreateLoad(Ops[0]); 1532 Value *Align = GetPointeeAlignment(*this, E->getArg(0)); 1533 Ld->setAlignment(cast<ConstantInt>(Align)->getZExtValue()); 1534 llvm::Constant *CI = ConstantInt::get(Int32Ty, 0); 1535 Ops[0] = Builder.CreateInsertElement(V, Ld, CI); 1536 return EmitNeonSplat(Ops[0], CI); 1537 } 1538 case ARM::BI__builtin_neon_vld2_v: 1539 case ARM::BI__builtin_neon_vld2q_v: { 1540 Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vld2, Ty); 1541 Value *Align = GetPointeeAlignment(*this, E->getArg(1)); 1542 Ops[1] = Builder.CreateCall2(F, Ops[1], Align, "vld2"); 1543 Ty = llvm::PointerType::getUnqual(Ops[1]->getType()); 1544 Ops[0] = Builder.CreateBitCast(Ops[0], Ty); 1545 return Builder.CreateStore(Ops[1], Ops[0]); 1546 } 1547 case ARM::BI__builtin_neon_vld3_v: 1548 case ARM::BI__builtin_neon_vld3q_v: { 1549 Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vld3, Ty); 1550 Value *Align = GetPointeeAlignment(*this, E->getArg(1)); 1551 Ops[1] = Builder.CreateCall2(F, Ops[1], Align, "vld3"); 1552 Ty = llvm::PointerType::getUnqual(Ops[1]->getType()); 1553 Ops[0] = Builder.CreateBitCast(Ops[0], Ty); 1554 return Builder.CreateStore(Ops[1], Ops[0]); 1555 } 1556 case ARM::BI__builtin_neon_vld4_v: 1557 case ARM::BI__builtin_neon_vld4q_v: { 1558 Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vld4, Ty); 1559 Value *Align = GetPointeeAlignment(*this, E->getArg(1)); 1560 Ops[1] = Builder.CreateCall2(F, Ops[1], Align, "vld4"); 1561 Ty = llvm::PointerType::getUnqual(Ops[1]->getType()); 1562 Ops[0] = Builder.CreateBitCast(Ops[0], Ty); 1563 return Builder.CreateStore(Ops[1], Ops[0]); 1564 } 1565 case ARM::BI__builtin_neon_vld2_lane_v: 1566 case ARM::BI__builtin_neon_vld2q_lane_v: { 1567 Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vld2lane, Ty); 1568 Ops[2] = Builder.CreateBitCast(Ops[2], Ty); 1569 Ops[3] = Builder.CreateBitCast(Ops[3], Ty); 1570 Ops.push_back(GetPointeeAlignment(*this, E->getArg(1))); 1571 Ops[1] = Builder.CreateCall(F, makeArrayRef(Ops).slice(1), "vld2_lane"); 1572 Ty = llvm::PointerType::getUnqual(Ops[1]->getType()); 1573 Ops[0] = Builder.CreateBitCast(Ops[0], Ty); 1574 return Builder.CreateStore(Ops[1], Ops[0]); 1575 } 1576 case ARM::BI__builtin_neon_vld3_lane_v: 1577 case ARM::BI__builtin_neon_vld3q_lane_v: { 1578 Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vld3lane, Ty); 1579 Ops[2] = Builder.CreateBitCast(Ops[2], Ty); 1580 Ops[3] = Builder.CreateBitCast(Ops[3], Ty); 1581 Ops[4] = Builder.CreateBitCast(Ops[4], Ty); 1582 Ops.push_back(GetPointeeAlignment(*this, E->getArg(1))); 1583 Ops[1] = Builder.CreateCall(F, makeArrayRef(Ops).slice(1), "vld3_lane"); 1584 Ty = llvm::PointerType::getUnqual(Ops[1]->getType()); 1585 Ops[0] = Builder.CreateBitCast(Ops[0], Ty); 1586 return Builder.CreateStore(Ops[1], Ops[0]); 1587 } 1588 case ARM::BI__builtin_neon_vld4_lane_v: 1589 case ARM::BI__builtin_neon_vld4q_lane_v: { 1590 Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vld4lane, Ty); 1591 Ops[2] = Builder.CreateBitCast(Ops[2], Ty); 1592 Ops[3] = Builder.CreateBitCast(Ops[3], Ty); 1593 Ops[4] = Builder.CreateBitCast(Ops[4], Ty); 1594 Ops[5] = Builder.CreateBitCast(Ops[5], Ty); 1595 Ops.push_back(GetPointeeAlignment(*this, E->getArg(1))); 1596 Ops[1] = Builder.CreateCall(F, makeArrayRef(Ops).slice(1), "vld3_lane"); 1597 Ty = llvm::PointerType::getUnqual(Ops[1]->getType()); 1598 Ops[0] = Builder.CreateBitCast(Ops[0], Ty); 1599 return Builder.CreateStore(Ops[1], Ops[0]); 1600 } 1601 case ARM::BI__builtin_neon_vld2_dup_v: 1602 case ARM::BI__builtin_neon_vld3_dup_v: 1603 case ARM::BI__builtin_neon_vld4_dup_v: { 1604 // Handle 64-bit elements as a special-case. There is no "dup" needed. 1605 if (VTy->getElementType()->getPrimitiveSizeInBits() == 64) { 1606 switch (BuiltinID) { 1607 case ARM::BI__builtin_neon_vld2_dup_v: 1608 Int = Intrinsic::arm_neon_vld2; 1609 break; 1610 case ARM::BI__builtin_neon_vld3_dup_v: 1611 Int = Intrinsic::arm_neon_vld2; 1612 break; 1613 case ARM::BI__builtin_neon_vld4_dup_v: 1614 Int = Intrinsic::arm_neon_vld2; 1615 break; 1616 default: llvm_unreachable("unknown vld_dup intrinsic?"); 1617 } 1618 Function *F = CGM.getIntrinsic(Int, Ty); 1619 Value *Align = GetPointeeAlignment(*this, E->getArg(1)); 1620 Ops[1] = Builder.CreateCall2(F, Ops[1], Align, "vld_dup"); 1621 Ty = llvm::PointerType::getUnqual(Ops[1]->getType()); 1622 Ops[0] = Builder.CreateBitCast(Ops[0], Ty); 1623 return Builder.CreateStore(Ops[1], Ops[0]); 1624 } 1625 switch (BuiltinID) { 1626 case ARM::BI__builtin_neon_vld2_dup_v: 1627 Int = Intrinsic::arm_neon_vld2lane; 1628 break; 1629 case ARM::BI__builtin_neon_vld3_dup_v: 1630 Int = Intrinsic::arm_neon_vld2lane; 1631 break; 1632 case ARM::BI__builtin_neon_vld4_dup_v: 1633 Int = Intrinsic::arm_neon_vld2lane; 1634 break; 1635 default: llvm_unreachable("unknown vld_dup intrinsic?"); 1636 } 1637 Function *F = CGM.getIntrinsic(Int, Ty); 1638 llvm::StructType *STy = cast<llvm::StructType>(F->getReturnType()); 1639 1640 SmallVector<Value*, 6> Args; 1641 Args.push_back(Ops[1]); 1642 Args.append(STy->getNumElements(), UndefValue::get(Ty)); 1643 1644 llvm::Constant *CI = ConstantInt::get(Int32Ty, 0); 1645 Args.push_back(CI); 1646 Args.push_back(GetPointeeAlignment(*this, E->getArg(1))); 1647 1648 Ops[1] = Builder.CreateCall(F, Args, "vld_dup"); 1649 // splat lane 0 to all elts in each vector of the result. 1650 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1651 Value *Val = Builder.CreateExtractValue(Ops[1], i); 1652 Value *Elt = Builder.CreateBitCast(Val, Ty); 1653 Elt = EmitNeonSplat(Elt, CI); 1654 Elt = Builder.CreateBitCast(Elt, Val->getType()); 1655 Ops[1] = Builder.CreateInsertValue(Ops[1], Elt, i); 1656 } 1657 Ty = llvm::PointerType::getUnqual(Ops[1]->getType()); 1658 Ops[0] = Builder.CreateBitCast(Ops[0], Ty); 1659 return Builder.CreateStore(Ops[1], Ops[0]); 1660 } 1661 case ARM::BI__builtin_neon_vmax_v: 1662 case ARM::BI__builtin_neon_vmaxq_v: 1663 Int = usgn ? Intrinsic::arm_neon_vmaxu : Intrinsic::arm_neon_vmaxs; 1664 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vmax"); 1665 case ARM::BI__builtin_neon_vmin_v: 1666 case ARM::BI__builtin_neon_vminq_v: 1667 Int = usgn ? Intrinsic::arm_neon_vminu : Intrinsic::arm_neon_vmins; 1668 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vmin"); 1669 case ARM::BI__builtin_neon_vmovl_v: { 1670 llvm::Type *DTy =llvm::VectorType::getTruncatedElementVectorType(VTy); 1671 Ops[0] = Builder.CreateBitCast(Ops[0], DTy); 1672 if (usgn) 1673 return Builder.CreateZExt(Ops[0], Ty, "vmovl"); 1674 return Builder.CreateSExt(Ops[0], Ty, "vmovl"); 1675 } 1676 case ARM::BI__builtin_neon_vmovn_v: { 1677 llvm::Type *QTy = llvm::VectorType::getExtendedElementVectorType(VTy); 1678 Ops[0] = Builder.CreateBitCast(Ops[0], QTy); 1679 return Builder.CreateTrunc(Ops[0], Ty, "vmovn"); 1680 } 1681 case ARM::BI__builtin_neon_vmul_v: 1682 case ARM::BI__builtin_neon_vmulq_v: 1683 assert(Type.isPoly() && "vmul builtin only supported for polynomial types"); 1684 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vmulp, Ty), 1685 Ops, "vmul"); 1686 case ARM::BI__builtin_neon_vmull_v: 1687 Int = usgn ? Intrinsic::arm_neon_vmullu : Intrinsic::arm_neon_vmulls; 1688 Int = Type.isPoly() ? (unsigned)Intrinsic::arm_neon_vmullp : Int; 1689 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vmull"); 1690 case ARM::BI__builtin_neon_vpadal_v: 1691 case ARM::BI__builtin_neon_vpadalq_v: { 1692 Int = usgn ? Intrinsic::arm_neon_vpadalu : Intrinsic::arm_neon_vpadals; 1693 // The source operand type has twice as many elements of half the size. 1694 unsigned EltBits = VTy->getElementType()->getPrimitiveSizeInBits(); 1695 llvm::Type *EltTy = 1696 llvm::IntegerType::get(getLLVMContext(), EltBits / 2); 1697 llvm::Type *NarrowTy = 1698 llvm::VectorType::get(EltTy, VTy->getNumElements() * 2); 1699 llvm::Type *Tys[2] = { Ty, NarrowTy }; 1700 return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vpadal"); 1701 } 1702 case ARM::BI__builtin_neon_vpadd_v: 1703 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vpadd, Ty), 1704 Ops, "vpadd"); 1705 case ARM::BI__builtin_neon_vpaddl_v: 1706 case ARM::BI__builtin_neon_vpaddlq_v: { 1707 Int = usgn ? Intrinsic::arm_neon_vpaddlu : Intrinsic::arm_neon_vpaddls; 1708 // The source operand type has twice as many elements of half the size. 1709 unsigned EltBits = VTy->getElementType()->getPrimitiveSizeInBits(); 1710 llvm::Type *EltTy = llvm::IntegerType::get(getLLVMContext(), EltBits / 2); 1711 llvm::Type *NarrowTy = 1712 llvm::VectorType::get(EltTy, VTy->getNumElements() * 2); 1713 llvm::Type *Tys[2] = { Ty, NarrowTy }; 1714 return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vpaddl"); 1715 } 1716 case ARM::BI__builtin_neon_vpmax_v: 1717 Int = usgn ? Intrinsic::arm_neon_vpmaxu : Intrinsic::arm_neon_vpmaxs; 1718 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vpmax"); 1719 case ARM::BI__builtin_neon_vpmin_v: 1720 Int = usgn ? Intrinsic::arm_neon_vpminu : Intrinsic::arm_neon_vpmins; 1721 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vpmin"); 1722 case ARM::BI__builtin_neon_vqabs_v: 1723 case ARM::BI__builtin_neon_vqabsq_v: 1724 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqabs, Ty), 1725 Ops, "vqabs"); 1726 case ARM::BI__builtin_neon_vqadd_v: 1727 case ARM::BI__builtin_neon_vqaddq_v: 1728 Int = usgn ? Intrinsic::arm_neon_vqaddu : Intrinsic::arm_neon_vqadds; 1729 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqadd"); 1730 case ARM::BI__builtin_neon_vqdmlal_v: 1731 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqdmlal, Ty), 1732 Ops, "vqdmlal"); 1733 case ARM::BI__builtin_neon_vqdmlsl_v: 1734 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqdmlsl, Ty), 1735 Ops, "vqdmlsl"); 1736 case ARM::BI__builtin_neon_vqdmulh_v: 1737 case ARM::BI__builtin_neon_vqdmulhq_v: 1738 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqdmulh, Ty), 1739 Ops, "vqdmulh"); 1740 case ARM::BI__builtin_neon_vqdmull_v: 1741 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqdmull, Ty), 1742 Ops, "vqdmull"); 1743 case ARM::BI__builtin_neon_vqmovn_v: 1744 Int = usgn ? Intrinsic::arm_neon_vqmovnu : Intrinsic::arm_neon_vqmovns; 1745 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqmovn"); 1746 case ARM::BI__builtin_neon_vqmovun_v: 1747 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqmovnsu, Ty), 1748 Ops, "vqdmull"); 1749 case ARM::BI__builtin_neon_vqneg_v: 1750 case ARM::BI__builtin_neon_vqnegq_v: 1751 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqneg, Ty), 1752 Ops, "vqneg"); 1753 case ARM::BI__builtin_neon_vqrdmulh_v: 1754 case ARM::BI__builtin_neon_vqrdmulhq_v: 1755 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqrdmulh, Ty), 1756 Ops, "vqrdmulh"); 1757 case ARM::BI__builtin_neon_vqrshl_v: 1758 case ARM::BI__builtin_neon_vqrshlq_v: 1759 Int = usgn ? Intrinsic::arm_neon_vqrshiftu : Intrinsic::arm_neon_vqrshifts; 1760 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqrshl"); 1761 case ARM::BI__builtin_neon_vqrshrn_n_v: 1762 Int = usgn ? Intrinsic::arm_neon_vqrshiftnu : Intrinsic::arm_neon_vqrshiftns; 1763 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqrshrn_n", 1764 1, true); 1765 case ARM::BI__builtin_neon_vqrshrun_n_v: 1766 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqrshiftnsu, Ty), 1767 Ops, "vqrshrun_n", 1, true); 1768 case ARM::BI__builtin_neon_vqshl_v: 1769 case ARM::BI__builtin_neon_vqshlq_v: 1770 Int = usgn ? Intrinsic::arm_neon_vqshiftu : Intrinsic::arm_neon_vqshifts; 1771 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqshl"); 1772 case ARM::BI__builtin_neon_vqshl_n_v: 1773 case ARM::BI__builtin_neon_vqshlq_n_v: 1774 Int = usgn ? Intrinsic::arm_neon_vqshiftu : Intrinsic::arm_neon_vqshifts; 1775 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqshl_n", 1776 1, false); 1777 case ARM::BI__builtin_neon_vqshlu_n_v: 1778 case ARM::BI__builtin_neon_vqshluq_n_v: 1779 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqshiftsu, Ty), 1780 Ops, "vqshlu", 1, false); 1781 case ARM::BI__builtin_neon_vqshrn_n_v: 1782 Int = usgn ? Intrinsic::arm_neon_vqshiftnu : Intrinsic::arm_neon_vqshiftns; 1783 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqshrn_n", 1784 1, true); 1785 case ARM::BI__builtin_neon_vqshrun_n_v: 1786 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqshiftnsu, Ty), 1787 Ops, "vqshrun_n", 1, true); 1788 case ARM::BI__builtin_neon_vqsub_v: 1789 case ARM::BI__builtin_neon_vqsubq_v: 1790 Int = usgn ? Intrinsic::arm_neon_vqsubu : Intrinsic::arm_neon_vqsubs; 1791 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqsub"); 1792 case ARM::BI__builtin_neon_vraddhn_v: 1793 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vraddhn, Ty), 1794 Ops, "vraddhn"); 1795 case ARM::BI__builtin_neon_vrecpe_v: 1796 case ARM::BI__builtin_neon_vrecpeq_v: 1797 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrecpe, Ty), 1798 Ops, "vrecpe"); 1799 case ARM::BI__builtin_neon_vrecps_v: 1800 case ARM::BI__builtin_neon_vrecpsq_v: 1801 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrecps, Ty), 1802 Ops, "vrecps"); 1803 case ARM::BI__builtin_neon_vrhadd_v: 1804 case ARM::BI__builtin_neon_vrhaddq_v: 1805 Int = usgn ? Intrinsic::arm_neon_vrhaddu : Intrinsic::arm_neon_vrhadds; 1806 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vrhadd"); 1807 case ARM::BI__builtin_neon_vrshl_v: 1808 case ARM::BI__builtin_neon_vrshlq_v: 1809 Int = usgn ? Intrinsic::arm_neon_vrshiftu : Intrinsic::arm_neon_vrshifts; 1810 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vrshl"); 1811 case ARM::BI__builtin_neon_vrshrn_n_v: 1812 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrshiftn, Ty), 1813 Ops, "vrshrn_n", 1, true); 1814 case ARM::BI__builtin_neon_vrshr_n_v: 1815 case ARM::BI__builtin_neon_vrshrq_n_v: 1816 Int = usgn ? Intrinsic::arm_neon_vrshiftu : Intrinsic::arm_neon_vrshifts; 1817 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vrshr_n", 1, true); 1818 case ARM::BI__builtin_neon_vrsqrte_v: 1819 case ARM::BI__builtin_neon_vrsqrteq_v: 1820 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrsqrte, Ty), 1821 Ops, "vrsqrte"); 1822 case ARM::BI__builtin_neon_vrsqrts_v: 1823 case ARM::BI__builtin_neon_vrsqrtsq_v: 1824 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrsqrts, Ty), 1825 Ops, "vrsqrts"); 1826 case ARM::BI__builtin_neon_vrsra_n_v: 1827 case ARM::BI__builtin_neon_vrsraq_n_v: 1828 Ops[0] = Builder.CreateBitCast(Ops[0], Ty); 1829 Ops[1] = Builder.CreateBitCast(Ops[1], Ty); 1830 Ops[2] = EmitNeonShiftVector(Ops[2], Ty, true); 1831 Int = usgn ? Intrinsic::arm_neon_vrshiftu : Intrinsic::arm_neon_vrshifts; 1832 Ops[1] = Builder.CreateCall2(CGM.getIntrinsic(Int, Ty), Ops[1], Ops[2]); 1833 return Builder.CreateAdd(Ops[0], Ops[1], "vrsra_n"); 1834 case ARM::BI__builtin_neon_vrsubhn_v: 1835 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrsubhn, Ty), 1836 Ops, "vrsubhn"); 1837 case ARM::BI__builtin_neon_vshl_v: 1838 case ARM::BI__builtin_neon_vshlq_v: 1839 Int = usgn ? Intrinsic::arm_neon_vshiftu : Intrinsic::arm_neon_vshifts; 1840 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vshl"); 1841 case ARM::BI__builtin_neon_vshll_n_v: 1842 Int = usgn ? Intrinsic::arm_neon_vshiftlu : Intrinsic::arm_neon_vshiftls; 1843 return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vshll", 1); 1844 case ARM::BI__builtin_neon_vshl_n_v: 1845 case ARM::BI__builtin_neon_vshlq_n_v: 1846 Ops[1] = EmitNeonShiftVector(Ops[1], Ty, false); 1847 return Builder.CreateShl(Builder.CreateBitCast(Ops[0],Ty), Ops[1], "vshl_n"); 1848 case ARM::BI__builtin_neon_vshrn_n_v: 1849 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vshiftn, Ty), 1850 Ops, "vshrn_n", 1, true); 1851 case ARM::BI__builtin_neon_vshr_n_v: 1852 case ARM::BI__builtin_neon_vshrq_n_v: 1853 Ops[0] = Builder.CreateBitCast(Ops[0], Ty); 1854 Ops[1] = EmitNeonShiftVector(Ops[1], Ty, false); 1855 if (usgn) 1856 return Builder.CreateLShr(Ops[0], Ops[1], "vshr_n"); 1857 else 1858 return Builder.CreateAShr(Ops[0], Ops[1], "vshr_n"); 1859 case ARM::BI__builtin_neon_vsri_n_v: 1860 case ARM::BI__builtin_neon_vsriq_n_v: 1861 rightShift = true; 1862 case ARM::BI__builtin_neon_vsli_n_v: 1863 case ARM::BI__builtin_neon_vsliq_n_v: 1864 Ops[2] = EmitNeonShiftVector(Ops[2], Ty, rightShift); 1865 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vshiftins, Ty), 1866 Ops, "vsli_n"); 1867 case ARM::BI__builtin_neon_vsra_n_v: 1868 case ARM::BI__builtin_neon_vsraq_n_v: 1869 Ops[0] = Builder.CreateBitCast(Ops[0], Ty); 1870 Ops[1] = Builder.CreateBitCast(Ops[1], Ty); 1871 Ops[2] = EmitNeonShiftVector(Ops[2], Ty, false); 1872 if (usgn) 1873 Ops[1] = Builder.CreateLShr(Ops[1], Ops[2], "vsra_n"); 1874 else 1875 Ops[1] = Builder.CreateAShr(Ops[1], Ops[2], "vsra_n"); 1876 return Builder.CreateAdd(Ops[0], Ops[1]); 1877 case ARM::BI__builtin_neon_vst1_v: 1878 case ARM::BI__builtin_neon_vst1q_v: 1879 Ops.push_back(GetPointeeAlignment(*this, E->getArg(0))); 1880 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst1, Ty), 1881 Ops, ""); 1882 case ARM::BI__builtin_neon_vst1_lane_v: 1883 case ARM::BI__builtin_neon_vst1q_lane_v: { 1884 Ops[1] = Builder.CreateBitCast(Ops[1], Ty); 1885 Ops[1] = Builder.CreateExtractElement(Ops[1], Ops[2]); 1886 Ty = llvm::PointerType::getUnqual(Ops[1]->getType()); 1887 StoreInst *St = Builder.CreateStore(Ops[1], 1888 Builder.CreateBitCast(Ops[0], Ty)); 1889 Value *Align = GetPointeeAlignment(*this, E->getArg(0)); 1890 St->setAlignment(cast<ConstantInt>(Align)->getZExtValue()); 1891 return St; 1892 } 1893 case ARM::BI__builtin_neon_vst2_v: 1894 case ARM::BI__builtin_neon_vst2q_v: 1895 Ops.push_back(GetPointeeAlignment(*this, E->getArg(0))); 1896 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst2, Ty), 1897 Ops, ""); 1898 case ARM::BI__builtin_neon_vst2_lane_v: 1899 case ARM::BI__builtin_neon_vst2q_lane_v: 1900 Ops.push_back(GetPointeeAlignment(*this, E->getArg(0))); 1901 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst2lane, Ty), 1902 Ops, ""); 1903 case ARM::BI__builtin_neon_vst3_v: 1904 case ARM::BI__builtin_neon_vst3q_v: 1905 Ops.push_back(GetPointeeAlignment(*this, E->getArg(0))); 1906 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst3, Ty), 1907 Ops, ""); 1908 case ARM::BI__builtin_neon_vst3_lane_v: 1909 case ARM::BI__builtin_neon_vst3q_lane_v: 1910 Ops.push_back(GetPointeeAlignment(*this, E->getArg(0))); 1911 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst3lane, Ty), 1912 Ops, ""); 1913 case ARM::BI__builtin_neon_vst4_v: 1914 case ARM::BI__builtin_neon_vst4q_v: 1915 Ops.push_back(GetPointeeAlignment(*this, E->getArg(0))); 1916 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst4, Ty), 1917 Ops, ""); 1918 case ARM::BI__builtin_neon_vst4_lane_v: 1919 case ARM::BI__builtin_neon_vst4q_lane_v: 1920 Ops.push_back(GetPointeeAlignment(*this, E->getArg(0))); 1921 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst4lane, Ty), 1922 Ops, ""); 1923 case ARM::BI__builtin_neon_vsubhn_v: 1924 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vsubhn, Ty), 1925 Ops, "vsubhn"); 1926 case ARM::BI__builtin_neon_vtbl1_v: 1927 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbl1), 1928 Ops, "vtbl1"); 1929 case ARM::BI__builtin_neon_vtbl2_v: 1930 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbl2), 1931 Ops, "vtbl2"); 1932 case ARM::BI__builtin_neon_vtbl3_v: 1933 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbl3), 1934 Ops, "vtbl3"); 1935 case ARM::BI__builtin_neon_vtbl4_v: 1936 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbl4), 1937 Ops, "vtbl4"); 1938 case ARM::BI__builtin_neon_vtbx1_v: 1939 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbx1), 1940 Ops, "vtbx1"); 1941 case ARM::BI__builtin_neon_vtbx2_v: 1942 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbx2), 1943 Ops, "vtbx2"); 1944 case ARM::BI__builtin_neon_vtbx3_v: 1945 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbx3), 1946 Ops, "vtbx3"); 1947 case ARM::BI__builtin_neon_vtbx4_v: 1948 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbx4), 1949 Ops, "vtbx4"); 1950 case ARM::BI__builtin_neon_vtst_v: 1951 case ARM::BI__builtin_neon_vtstq_v: { 1952 Ops[0] = Builder.CreateBitCast(Ops[0], Ty); 1953 Ops[1] = Builder.CreateBitCast(Ops[1], Ty); 1954 Ops[0] = Builder.CreateAnd(Ops[0], Ops[1]); 1955 Ops[0] = Builder.CreateICmp(ICmpInst::ICMP_NE, Ops[0], 1956 ConstantAggregateZero::get(Ty)); 1957 return Builder.CreateSExt(Ops[0], Ty, "vtst"); 1958 } 1959 case ARM::BI__builtin_neon_vtrn_v: 1960 case ARM::BI__builtin_neon_vtrnq_v: { 1961 Ops[0] = Builder.CreateBitCast(Ops[0], llvm::PointerType::getUnqual(Ty)); 1962 Ops[1] = Builder.CreateBitCast(Ops[1], Ty); 1963 Ops[2] = Builder.CreateBitCast(Ops[2], Ty); 1964 Value *SV = 0; 1965 1966 for (unsigned vi = 0; vi != 2; ++vi) { 1967 SmallVector<Constant*, 16> Indices; 1968 for (unsigned i = 0, e = VTy->getNumElements(); i != e; i += 2) { 1969 Indices.push_back(Builder.getInt32(i+vi)); 1970 Indices.push_back(Builder.getInt32(i+e+vi)); 1971 } 1972 Value *Addr = Builder.CreateConstInBoundsGEP1_32(Ops[0], vi); 1973 SV = llvm::ConstantVector::get(Indices); 1974 SV = Builder.CreateShuffleVector(Ops[1], Ops[2], SV, "vtrn"); 1975 SV = Builder.CreateStore(SV, Addr); 1976 } 1977 return SV; 1978 } 1979 case ARM::BI__builtin_neon_vuzp_v: 1980 case ARM::BI__builtin_neon_vuzpq_v: { 1981 Ops[0] = Builder.CreateBitCast(Ops[0], llvm::PointerType::getUnqual(Ty)); 1982 Ops[1] = Builder.CreateBitCast(Ops[1], Ty); 1983 Ops[2] = Builder.CreateBitCast(Ops[2], Ty); 1984 Value *SV = 0; 1985 1986 for (unsigned vi = 0; vi != 2; ++vi) { 1987 SmallVector<Constant*, 16> Indices; 1988 for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) 1989 Indices.push_back(ConstantInt::get(Int32Ty, 2*i+vi)); 1990 1991 Value *Addr = Builder.CreateConstInBoundsGEP1_32(Ops[0], vi); 1992 SV = llvm::ConstantVector::get(Indices); 1993 SV = Builder.CreateShuffleVector(Ops[1], Ops[2], SV, "vuzp"); 1994 SV = Builder.CreateStore(SV, Addr); 1995 } 1996 return SV; 1997 } 1998 case ARM::BI__builtin_neon_vzip_v: 1999 case ARM::BI__builtin_neon_vzipq_v: { 2000 Ops[0] = Builder.CreateBitCast(Ops[0], llvm::PointerType::getUnqual(Ty)); 2001 Ops[1] = Builder.CreateBitCast(Ops[1], Ty); 2002 Ops[2] = Builder.CreateBitCast(Ops[2], Ty); 2003 Value *SV = 0; 2004 2005 for (unsigned vi = 0; vi != 2; ++vi) { 2006 SmallVector<Constant*, 16> Indices; 2007 for (unsigned i = 0, e = VTy->getNumElements(); i != e; i += 2) { 2008 Indices.push_back(ConstantInt::get(Int32Ty, (i + vi*e) >> 1)); 2009 Indices.push_back(ConstantInt::get(Int32Ty, ((i + vi*e) >> 1)+e)); 2010 } 2011 Value *Addr = Builder.CreateConstInBoundsGEP1_32(Ops[0], vi); 2012 SV = llvm::ConstantVector::get(Indices); 2013 SV = Builder.CreateShuffleVector(Ops[1], Ops[2], SV, "vzip"); 2014 SV = Builder.CreateStore(SV, Addr); 2015 } 2016 return SV; 2017 } 2018 } 2019 } 2020 2021 llvm::Value *CodeGenFunction:: 2022 BuildVector(ArrayRef<llvm::Value*> Ops) { 2023 assert((Ops.size() & (Ops.size() - 1)) == 0 && 2024 "Not a power-of-two sized vector!"); 2025 bool AllConstants = true; 2026 for (unsigned i = 0, e = Ops.size(); i != e && AllConstants; ++i) 2027 AllConstants &= isa<Constant>(Ops[i]); 2028 2029 // If this is a constant vector, create a ConstantVector. 2030 if (AllConstants) { 2031 SmallVector<llvm::Constant*, 16> CstOps; 2032 for (unsigned i = 0, e = Ops.size(); i != e; ++i) 2033 CstOps.push_back(cast<Constant>(Ops[i])); 2034 return llvm::ConstantVector::get(CstOps); 2035 } 2036 2037 // Otherwise, insertelement the values to build the vector. 2038 Value *Result = 2039 llvm::UndefValue::get(llvm::VectorType::get(Ops[0]->getType(), Ops.size())); 2040 2041 for (unsigned i = 0, e = Ops.size(); i != e; ++i) 2042 Result = Builder.CreateInsertElement(Result, Ops[i], Builder.getInt32(i)); 2043 2044 return Result; 2045 } 2046 2047 Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID, 2048 const CallExpr *E) { 2049 SmallVector<Value*, 4> Ops; 2050 2051 // Find out if any arguments are required to be integer constant expressions. 2052 unsigned ICEArguments = 0; 2053 ASTContext::GetBuiltinTypeError Error; 2054 getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments); 2055 assert(Error == ASTContext::GE_None && "Should not codegen an error"); 2056 2057 for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) { 2058 // If this is a normal argument, just emit it as a scalar. 2059 if ((ICEArguments & (1 << i)) == 0) { 2060 Ops.push_back(EmitScalarExpr(E->getArg(i))); 2061 continue; 2062 } 2063 2064 // If this is required to be a constant, constant fold it so that we know 2065 // that the generated intrinsic gets a ConstantInt. 2066 llvm::APSInt Result; 2067 bool IsConst = E->getArg(i)->isIntegerConstantExpr(Result, getContext()); 2068 assert(IsConst && "Constant arg isn't actually constant?"); (void)IsConst; 2069 Ops.push_back(llvm::ConstantInt::get(getLLVMContext(), Result)); 2070 } 2071 2072 switch (BuiltinID) { 2073 default: return 0; 2074 case X86::BI__builtin_ia32_vec_init_v8qi: 2075 case X86::BI__builtin_ia32_vec_init_v4hi: 2076 case X86::BI__builtin_ia32_vec_init_v2si: 2077 return Builder.CreateBitCast(BuildVector(Ops), 2078 llvm::Type::getX86_MMXTy(getLLVMContext())); 2079 case X86::BI__builtin_ia32_vec_ext_v2si: 2080 return Builder.CreateExtractElement(Ops[0], 2081 llvm::ConstantInt::get(Ops[1]->getType(), 0)); 2082 case X86::BI__builtin_ia32_ldmxcsr: { 2083 llvm::Type *PtrTy = Int8PtrTy; 2084 Value *One = llvm::ConstantInt::get(Int32Ty, 1); 2085 Value *Tmp = Builder.CreateAlloca(Int32Ty, One); 2086 Builder.CreateStore(Ops[0], Tmp); 2087 return Builder.CreateCall(CGM.getIntrinsic(Intrinsic::x86_sse_ldmxcsr), 2088 Builder.CreateBitCast(Tmp, PtrTy)); 2089 } 2090 case X86::BI__builtin_ia32_stmxcsr: { 2091 llvm::Type *PtrTy = Int8PtrTy; 2092 Value *One = llvm::ConstantInt::get(Int32Ty, 1); 2093 Value *Tmp = Builder.CreateAlloca(Int32Ty, One); 2094 Builder.CreateCall(CGM.getIntrinsic(Intrinsic::x86_sse_stmxcsr), 2095 Builder.CreateBitCast(Tmp, PtrTy)); 2096 return Builder.CreateLoad(Tmp, "stmxcsr"); 2097 } 2098 case X86::BI__builtin_ia32_storehps: 2099 case X86::BI__builtin_ia32_storelps: { 2100 llvm::Type *PtrTy = llvm::PointerType::getUnqual(Int64Ty); 2101 llvm::Type *VecTy = llvm::VectorType::get(Int64Ty, 2); 2102 2103 // cast val v2i64 2104 Ops[1] = Builder.CreateBitCast(Ops[1], VecTy, "cast"); 2105 2106 // extract (0, 1) 2107 unsigned Index = BuiltinID == X86::BI__builtin_ia32_storelps ? 0 : 1; 2108 llvm::Value *Idx = llvm::ConstantInt::get(Int32Ty, Index); 2109 Ops[1] = Builder.CreateExtractElement(Ops[1], Idx, "extract"); 2110 2111 // cast pointer to i64 & store 2112 Ops[0] = Builder.CreateBitCast(Ops[0], PtrTy); 2113 return Builder.CreateStore(Ops[1], Ops[0]); 2114 } 2115 case X86::BI__builtin_ia32_palignr: { 2116 unsigned shiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue(); 2117 2118 // If palignr is shifting the pair of input vectors less than 9 bytes, 2119 // emit a shuffle instruction. 2120 if (shiftVal <= 8) { 2121 SmallVector<llvm::Constant*, 8> Indices; 2122 for (unsigned i = 0; i != 8; ++i) 2123 Indices.push_back(llvm::ConstantInt::get(Int32Ty, shiftVal + i)); 2124 2125 Value* SV = llvm::ConstantVector::get(Indices); 2126 return Builder.CreateShuffleVector(Ops[1], Ops[0], SV, "palignr"); 2127 } 2128 2129 // If palignr is shifting the pair of input vectors more than 8 but less 2130 // than 16 bytes, emit a logical right shift of the destination. 2131 if (shiftVal < 16) { 2132 // MMX has these as 1 x i64 vectors for some odd optimization reasons. 2133 llvm::Type *VecTy = llvm::VectorType::get(Int64Ty, 1); 2134 2135 Ops[0] = Builder.CreateBitCast(Ops[0], VecTy, "cast"); 2136 Ops[1] = llvm::ConstantInt::get(VecTy, (shiftVal-8) * 8); 2137 2138 // create i32 constant 2139 llvm::Function *F = CGM.getIntrinsic(Intrinsic::x86_mmx_psrl_q); 2140 return Builder.CreateCall(F, makeArrayRef(&Ops[0], 2), "palignr"); 2141 } 2142 2143 // If palignr is shifting the pair of vectors more than 16 bytes, emit zero. 2144 return llvm::Constant::getNullValue(ConvertType(E->getType())); 2145 } 2146 case X86::BI__builtin_ia32_palignr128: { 2147 unsigned shiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue(); 2148 2149 // If palignr is shifting the pair of input vectors less than 17 bytes, 2150 // emit a shuffle instruction. 2151 if (shiftVal <= 16) { 2152 SmallVector<llvm::Constant*, 16> Indices; 2153 for (unsigned i = 0; i != 16; ++i) 2154 Indices.push_back(llvm::ConstantInt::get(Int32Ty, shiftVal + i)); 2155 2156 Value* SV = llvm::ConstantVector::get(Indices); 2157 return Builder.CreateShuffleVector(Ops[1], Ops[0], SV, "palignr"); 2158 } 2159 2160 // If palignr is shifting the pair of input vectors more than 16 but less 2161 // than 32 bytes, emit a logical right shift of the destination. 2162 if (shiftVal < 32) { 2163 llvm::Type *VecTy = llvm::VectorType::get(Int64Ty, 2); 2164 2165 Ops[0] = Builder.CreateBitCast(Ops[0], VecTy, "cast"); 2166 Ops[1] = llvm::ConstantInt::get(Int32Ty, (shiftVal-16) * 8); 2167 2168 // create i32 constant 2169 llvm::Function *F = CGM.getIntrinsic(Intrinsic::x86_sse2_psrl_dq); 2170 return Builder.CreateCall(F, makeArrayRef(&Ops[0], 2), "palignr"); 2171 } 2172 2173 // If palignr is shifting the pair of vectors more than 32 bytes, emit zero. 2174 return llvm::Constant::getNullValue(ConvertType(E->getType())); 2175 } 2176 case X86::BI__builtin_ia32_palignr256: { 2177 unsigned shiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue(); 2178 2179 // If palignr is shifting the pair of input vectors less than 17 bytes, 2180 // emit a shuffle instruction. 2181 if (shiftVal <= 16) { 2182 SmallVector<llvm::Constant*, 32> Indices; 2183 // 256-bit palignr operates on 128-bit lanes so we need to handle that 2184 for (unsigned l = 0; l != 2; ++l) { 2185 unsigned LaneStart = l * 16; 2186 unsigned LaneEnd = (l+1) * 16; 2187 for (unsigned i = 0; i != 16; ++i) { 2188 unsigned Idx = shiftVal + i + LaneStart; 2189 if (Idx >= LaneEnd) Idx += 16; // end of lane, switch operand 2190 Indices.push_back(llvm::ConstantInt::get(Int32Ty, Idx)); 2191 } 2192 } 2193 2194 Value* SV = llvm::ConstantVector::get(Indices); 2195 return Builder.CreateShuffleVector(Ops[1], Ops[0], SV, "palignr"); 2196 } 2197 2198 // If palignr is shifting the pair of input vectors more than 16 but less 2199 // than 32 bytes, emit a logical right shift of the destination. 2200 if (shiftVal < 32) { 2201 llvm::Type *VecTy = llvm::VectorType::get(Int64Ty, 4); 2202 2203 Ops[0] = Builder.CreateBitCast(Ops[0], VecTy, "cast"); 2204 Ops[1] = llvm::ConstantInt::get(Int32Ty, (shiftVal-16) * 8); 2205 2206 // create i32 constant 2207 llvm::Function *F = CGM.getIntrinsic(Intrinsic::x86_avx2_psrl_dq); 2208 return Builder.CreateCall(F, makeArrayRef(&Ops[0], 2), "palignr"); 2209 } 2210 2211 // If palignr is shifting the pair of vectors more than 32 bytes, emit zero. 2212 return llvm::Constant::getNullValue(ConvertType(E->getType())); 2213 } 2214 case X86::BI__builtin_ia32_movntps: 2215 case X86::BI__builtin_ia32_movntpd: 2216 case X86::BI__builtin_ia32_movntdq: 2217 case X86::BI__builtin_ia32_movnti: { 2218 llvm::MDNode *Node = llvm::MDNode::get(getLLVMContext(), 2219 Builder.getInt32(1)); 2220 2221 // Convert the type of the pointer to a pointer to the stored type. 2222 Value *BC = Builder.CreateBitCast(Ops[0], 2223 llvm::PointerType::getUnqual(Ops[1]->getType()), 2224 "cast"); 2225 StoreInst *SI = Builder.CreateStore(Ops[1], BC); 2226 SI->setMetadata(CGM.getModule().getMDKindID("nontemporal"), Node); 2227 SI->setAlignment(16); 2228 return SI; 2229 } 2230 // 3DNow! 2231 case X86::BI__builtin_ia32_pswapdsf: 2232 case X86::BI__builtin_ia32_pswapdsi: { 2233 const char *name = 0; 2234 Intrinsic::ID ID = Intrinsic::not_intrinsic; 2235 switch(BuiltinID) { 2236 default: llvm_unreachable("Unsupported intrinsic!"); 2237 case X86::BI__builtin_ia32_pswapdsf: 2238 case X86::BI__builtin_ia32_pswapdsi: 2239 name = "pswapd"; 2240 ID = Intrinsic::x86_3dnowa_pswapd; 2241 break; 2242 } 2243 llvm::Type *MMXTy = llvm::Type::getX86_MMXTy(getLLVMContext()); 2244 Ops[0] = Builder.CreateBitCast(Ops[0], MMXTy, "cast"); 2245 llvm::Function *F = CGM.getIntrinsic(ID); 2246 return Builder.CreateCall(F, Ops, name); 2247 } 2248 } 2249 } 2250 2251 2252 Value *CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID, 2253 const CallExpr *E) { 2254 llvm::SmallVector<Value*, 4> Ops; 2255 2256 for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) 2257 Ops.push_back(EmitScalarExpr(E->getArg(i))); 2258 2259 Intrinsic::ID ID = Intrinsic::not_intrinsic; 2260 2261 switch (BuiltinID) { 2262 default: return 0; 2263 2264 case Hexagon::BI__builtin_HEXAGON_C2_cmpeq: 2265 ID = Intrinsic::hexagon_C2_cmpeq; break; 2266 2267 case Hexagon::BI__builtin_HEXAGON_C2_cmpgt: 2268 ID = Intrinsic::hexagon_C2_cmpgt; break; 2269 2270 case Hexagon::BI__builtin_HEXAGON_C2_cmpgtu: 2271 ID = Intrinsic::hexagon_C2_cmpgtu; break; 2272 2273 case Hexagon::BI__builtin_HEXAGON_C2_cmpeqp: 2274 ID = Intrinsic::hexagon_C2_cmpeqp; break; 2275 2276 case Hexagon::BI__builtin_HEXAGON_C2_cmpgtp: 2277 ID = Intrinsic::hexagon_C2_cmpgtp; break; 2278 2279 case Hexagon::BI__builtin_HEXAGON_C2_cmpgtup: 2280 ID = Intrinsic::hexagon_C2_cmpgtup; break; 2281 2282 case Hexagon::BI__builtin_HEXAGON_C2_bitsset: 2283 ID = Intrinsic::hexagon_C2_bitsset; break; 2284 2285 case Hexagon::BI__builtin_HEXAGON_C2_bitsclr: 2286 ID = Intrinsic::hexagon_C2_bitsclr; break; 2287 2288 case Hexagon::BI__builtin_HEXAGON_C2_cmpeqi: 2289 ID = Intrinsic::hexagon_C2_cmpeqi; break; 2290 2291 case Hexagon::BI__builtin_HEXAGON_C2_cmpgti: 2292 ID = Intrinsic::hexagon_C2_cmpgti; break; 2293 2294 case Hexagon::BI__builtin_HEXAGON_C2_cmpgtui: 2295 ID = Intrinsic::hexagon_C2_cmpgtui; break; 2296 2297 case Hexagon::BI__builtin_HEXAGON_C2_cmpgei: 2298 ID = Intrinsic::hexagon_C2_cmpgei; break; 2299 2300 case Hexagon::BI__builtin_HEXAGON_C2_cmpgeui: 2301 ID = Intrinsic::hexagon_C2_cmpgeui; break; 2302 2303 case Hexagon::BI__builtin_HEXAGON_C2_cmplt: 2304 ID = Intrinsic::hexagon_C2_cmplt; break; 2305 2306 case Hexagon::BI__builtin_HEXAGON_C2_cmpltu: 2307 ID = Intrinsic::hexagon_C2_cmpltu; break; 2308 2309 case Hexagon::BI__builtin_HEXAGON_C2_bitsclri: 2310 ID = Intrinsic::hexagon_C2_bitsclri; break; 2311 2312 case Hexagon::BI__builtin_HEXAGON_C2_and: 2313 ID = Intrinsic::hexagon_C2_and; break; 2314 2315 case Hexagon::BI__builtin_HEXAGON_C2_or: 2316 ID = Intrinsic::hexagon_C2_or; break; 2317 2318 case Hexagon::BI__builtin_HEXAGON_C2_xor: 2319 ID = Intrinsic::hexagon_C2_xor; break; 2320 2321 case Hexagon::BI__builtin_HEXAGON_C2_andn: 2322 ID = Intrinsic::hexagon_C2_andn; break; 2323 2324 case Hexagon::BI__builtin_HEXAGON_C2_not: 2325 ID = Intrinsic::hexagon_C2_not; break; 2326 2327 case Hexagon::BI__builtin_HEXAGON_C2_orn: 2328 ID = Intrinsic::hexagon_C2_orn; break; 2329 2330 case Hexagon::BI__builtin_HEXAGON_C2_pxfer_map: 2331 ID = Intrinsic::hexagon_C2_pxfer_map; break; 2332 2333 case Hexagon::BI__builtin_HEXAGON_C2_any8: 2334 ID = Intrinsic::hexagon_C2_any8; break; 2335 2336 case Hexagon::BI__builtin_HEXAGON_C2_all8: 2337 ID = Intrinsic::hexagon_C2_all8; break; 2338 2339 case Hexagon::BI__builtin_HEXAGON_C2_vitpack: 2340 ID = Intrinsic::hexagon_C2_vitpack; break; 2341 2342 case Hexagon::BI__builtin_HEXAGON_C2_mux: 2343 ID = Intrinsic::hexagon_C2_mux; break; 2344 2345 case Hexagon::BI__builtin_HEXAGON_C2_muxii: 2346 ID = Intrinsic::hexagon_C2_muxii; break; 2347 2348 case Hexagon::BI__builtin_HEXAGON_C2_muxir: 2349 ID = Intrinsic::hexagon_C2_muxir; break; 2350 2351 case Hexagon::BI__builtin_HEXAGON_C2_muxri: 2352 ID = Intrinsic::hexagon_C2_muxri; break; 2353 2354 case Hexagon::BI__builtin_HEXAGON_C2_vmux: 2355 ID = Intrinsic::hexagon_C2_vmux; break; 2356 2357 case Hexagon::BI__builtin_HEXAGON_C2_mask: 2358 ID = Intrinsic::hexagon_C2_mask; break; 2359 2360 case Hexagon::BI__builtin_HEXAGON_A2_vcmpbeq: 2361 ID = Intrinsic::hexagon_A2_vcmpbeq; break; 2362 2363 case Hexagon::BI__builtin_HEXAGON_A2_vcmpbgtu: 2364 ID = Intrinsic::hexagon_A2_vcmpbgtu; break; 2365 2366 case Hexagon::BI__builtin_HEXAGON_A2_vcmpheq: 2367 ID = Intrinsic::hexagon_A2_vcmpheq; break; 2368 2369 case Hexagon::BI__builtin_HEXAGON_A2_vcmphgt: 2370 ID = Intrinsic::hexagon_A2_vcmphgt; break; 2371 2372 case Hexagon::BI__builtin_HEXAGON_A2_vcmphgtu: 2373 ID = Intrinsic::hexagon_A2_vcmphgtu; break; 2374 2375 case Hexagon::BI__builtin_HEXAGON_A2_vcmpweq: 2376 ID = Intrinsic::hexagon_A2_vcmpweq; break; 2377 2378 case Hexagon::BI__builtin_HEXAGON_A2_vcmpwgt: 2379 ID = Intrinsic::hexagon_A2_vcmpwgt; break; 2380 2381 case Hexagon::BI__builtin_HEXAGON_A2_vcmpwgtu: 2382 ID = Intrinsic::hexagon_A2_vcmpwgtu; break; 2383 2384 case Hexagon::BI__builtin_HEXAGON_C2_tfrpr: 2385 ID = Intrinsic::hexagon_C2_tfrpr; break; 2386 2387 case Hexagon::BI__builtin_HEXAGON_C2_tfrrp: 2388 ID = Intrinsic::hexagon_C2_tfrrp; break; 2389 2390 case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_hh_s0: 2391 ID = Intrinsic::hexagon_M2_mpy_acc_hh_s0; break; 2392 2393 case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_hh_s1: 2394 ID = Intrinsic::hexagon_M2_mpy_acc_hh_s1; break; 2395 2396 case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_hl_s0: 2397 ID = Intrinsic::hexagon_M2_mpy_acc_hl_s0; break; 2398 2399 case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_hl_s1: 2400 ID = Intrinsic::hexagon_M2_mpy_acc_hl_s1; break; 2401 2402 case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_lh_s0: 2403 ID = Intrinsic::hexagon_M2_mpy_acc_lh_s0; break; 2404 2405 case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_lh_s1: 2406 ID = Intrinsic::hexagon_M2_mpy_acc_lh_s1; break; 2407 2408 case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_ll_s0: 2409 ID = Intrinsic::hexagon_M2_mpy_acc_ll_s0; break; 2410 2411 case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_ll_s1: 2412 ID = Intrinsic::hexagon_M2_mpy_acc_ll_s1; break; 2413 2414 case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_hh_s0: 2415 ID = Intrinsic::hexagon_M2_mpy_nac_hh_s0; break; 2416 2417 case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_hh_s1: 2418 ID = Intrinsic::hexagon_M2_mpy_nac_hh_s1; break; 2419 2420 case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_hl_s0: 2421 ID = Intrinsic::hexagon_M2_mpy_nac_hl_s0; break; 2422 2423 case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_hl_s1: 2424 ID = Intrinsic::hexagon_M2_mpy_nac_hl_s1; break; 2425 2426 case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_lh_s0: 2427 ID = Intrinsic::hexagon_M2_mpy_nac_lh_s0; break; 2428 2429 case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_lh_s1: 2430 ID = Intrinsic::hexagon_M2_mpy_nac_lh_s1; break; 2431 2432 case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_ll_s0: 2433 ID = Intrinsic::hexagon_M2_mpy_nac_ll_s0; break; 2434 2435 case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_ll_s1: 2436 ID = Intrinsic::hexagon_M2_mpy_nac_ll_s1; break; 2437 2438 case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_hh_s0: 2439 ID = Intrinsic::hexagon_M2_mpy_acc_sat_hh_s0; break; 2440 2441 case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_hh_s1: 2442 ID = Intrinsic::hexagon_M2_mpy_acc_sat_hh_s1; break; 2443 2444 case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_hl_s0: 2445 ID = Intrinsic::hexagon_M2_mpy_acc_sat_hl_s0; break; 2446 2447 case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_hl_s1: 2448 ID = Intrinsic::hexagon_M2_mpy_acc_sat_hl_s1; break; 2449 2450 case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_lh_s0: 2451 ID = Intrinsic::hexagon_M2_mpy_acc_sat_lh_s0; break; 2452 2453 case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_lh_s1: 2454 ID = Intrinsic::hexagon_M2_mpy_acc_sat_lh_s1; break; 2455 2456 case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_ll_s0: 2457 ID = Intrinsic::hexagon_M2_mpy_acc_sat_ll_s0; break; 2458 2459 case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_ll_s1: 2460 ID = Intrinsic::hexagon_M2_mpy_acc_sat_ll_s1; break; 2461 2462 case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_hh_s0: 2463 ID = Intrinsic::hexagon_M2_mpy_nac_sat_hh_s0; break; 2464 2465 case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_hh_s1: 2466 ID = Intrinsic::hexagon_M2_mpy_nac_sat_hh_s1; break; 2467 2468 case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_hl_s0: 2469 ID = Intrinsic::hexagon_M2_mpy_nac_sat_hl_s0; break; 2470 2471 case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_hl_s1: 2472 ID = Intrinsic::hexagon_M2_mpy_nac_sat_hl_s1; break; 2473 2474 case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_lh_s0: 2475 ID = Intrinsic::hexagon_M2_mpy_nac_sat_lh_s0; break; 2476 2477 case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_lh_s1: 2478 ID = Intrinsic::hexagon_M2_mpy_nac_sat_lh_s1; break; 2479 2480 case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_ll_s0: 2481 ID = Intrinsic::hexagon_M2_mpy_nac_sat_ll_s0; break; 2482 2483 case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_ll_s1: 2484 ID = Intrinsic::hexagon_M2_mpy_nac_sat_ll_s1; break; 2485 2486 case Hexagon::BI__builtin_HEXAGON_M2_mpy_hh_s0: 2487 ID = Intrinsic::hexagon_M2_mpy_hh_s0; break; 2488 2489 case Hexagon::BI__builtin_HEXAGON_M2_mpy_hh_s1: 2490 ID = Intrinsic::hexagon_M2_mpy_hh_s1; break; 2491 2492 case Hexagon::BI__builtin_HEXAGON_M2_mpy_hl_s0: 2493 ID = Intrinsic::hexagon_M2_mpy_hl_s0; break; 2494 2495 case Hexagon::BI__builtin_HEXAGON_M2_mpy_hl_s1: 2496 ID = Intrinsic::hexagon_M2_mpy_hl_s1; break; 2497 2498 case Hexagon::BI__builtin_HEXAGON_M2_mpy_lh_s0: 2499 ID = Intrinsic::hexagon_M2_mpy_lh_s0; break; 2500 2501 case Hexagon::BI__builtin_HEXAGON_M2_mpy_lh_s1: 2502 ID = Intrinsic::hexagon_M2_mpy_lh_s1; break; 2503 2504 case Hexagon::BI__builtin_HEXAGON_M2_mpy_ll_s0: 2505 ID = Intrinsic::hexagon_M2_mpy_ll_s0; break; 2506 2507 case Hexagon::BI__builtin_HEXAGON_M2_mpy_ll_s1: 2508 ID = Intrinsic::hexagon_M2_mpy_ll_s1; break; 2509 2510 case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_hh_s0: 2511 ID = Intrinsic::hexagon_M2_mpy_sat_hh_s0; break; 2512 2513 case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_hh_s1: 2514 ID = Intrinsic::hexagon_M2_mpy_sat_hh_s1; break; 2515 2516 case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_hl_s0: 2517 ID = Intrinsic::hexagon_M2_mpy_sat_hl_s0; break; 2518 2519 case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_hl_s1: 2520 ID = Intrinsic::hexagon_M2_mpy_sat_hl_s1; break; 2521 2522 case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_lh_s0: 2523 ID = Intrinsic::hexagon_M2_mpy_sat_lh_s0; break; 2524 2525 case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_lh_s1: 2526 ID = Intrinsic::hexagon_M2_mpy_sat_lh_s1; break; 2527 2528 case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_ll_s0: 2529 ID = Intrinsic::hexagon_M2_mpy_sat_ll_s0; break; 2530 2531 case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_ll_s1: 2532 ID = Intrinsic::hexagon_M2_mpy_sat_ll_s1; break; 2533 2534 case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_hh_s0: 2535 ID = Intrinsic::hexagon_M2_mpy_rnd_hh_s0; break; 2536 2537 case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_hh_s1: 2538 ID = Intrinsic::hexagon_M2_mpy_rnd_hh_s1; break; 2539 2540 case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_hl_s0: 2541 ID = Intrinsic::hexagon_M2_mpy_rnd_hl_s0; break; 2542 2543 case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_hl_s1: 2544 ID = Intrinsic::hexagon_M2_mpy_rnd_hl_s1; break; 2545 2546 case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_lh_s0: 2547 ID = Intrinsic::hexagon_M2_mpy_rnd_lh_s0; break; 2548 2549 case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_lh_s1: 2550 ID = Intrinsic::hexagon_M2_mpy_rnd_lh_s1; break; 2551 2552 case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_ll_s0: 2553 ID = Intrinsic::hexagon_M2_mpy_rnd_ll_s0; break; 2554 2555 case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_ll_s1: 2556 ID = Intrinsic::hexagon_M2_mpy_rnd_ll_s1; break; 2557 2558 case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s0: 2559 ID = Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s0; break; 2560 2561 case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s1: 2562 ID = Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s1; break; 2563 2564 case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s0: 2565 ID = Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s0; break; 2566 2567 case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s1: 2568 ID = Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s1; break; 2569 2570 case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s0: 2571 ID = Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s0; break; 2572 2573 case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s1: 2574 ID = Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s1; break; 2575 2576 case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s0: 2577 ID = Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s0; break; 2578 2579 case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s1: 2580 ID = Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s1; break; 2581 2582 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_hh_s0: 2583 ID = Intrinsic::hexagon_M2_mpyd_acc_hh_s0; break; 2584 2585 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_hh_s1: 2586 ID = Intrinsic::hexagon_M2_mpyd_acc_hh_s1; break; 2587 2588 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_hl_s0: 2589 ID = Intrinsic::hexagon_M2_mpyd_acc_hl_s0; break; 2590 2591 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_hl_s1: 2592 ID = Intrinsic::hexagon_M2_mpyd_acc_hl_s1; break; 2593 2594 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_lh_s0: 2595 ID = Intrinsic::hexagon_M2_mpyd_acc_lh_s0; break; 2596 2597 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_lh_s1: 2598 ID = Intrinsic::hexagon_M2_mpyd_acc_lh_s1; break; 2599 2600 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_ll_s0: 2601 ID = Intrinsic::hexagon_M2_mpyd_acc_ll_s0; break; 2602 2603 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_ll_s1: 2604 ID = Intrinsic::hexagon_M2_mpyd_acc_ll_s1; break; 2605 2606 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_hh_s0: 2607 ID = Intrinsic::hexagon_M2_mpyd_nac_hh_s0; break; 2608 2609 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_hh_s1: 2610 ID = Intrinsic::hexagon_M2_mpyd_nac_hh_s1; break; 2611 2612 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_hl_s0: 2613 ID = Intrinsic::hexagon_M2_mpyd_nac_hl_s0; break; 2614 2615 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_hl_s1: 2616 ID = Intrinsic::hexagon_M2_mpyd_nac_hl_s1; break; 2617 2618 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_lh_s0: 2619 ID = Intrinsic::hexagon_M2_mpyd_nac_lh_s0; break; 2620 2621 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_lh_s1: 2622 ID = Intrinsic::hexagon_M2_mpyd_nac_lh_s1; break; 2623 2624 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_ll_s0: 2625 ID = Intrinsic::hexagon_M2_mpyd_nac_ll_s0; break; 2626 2627 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_ll_s1: 2628 ID = Intrinsic::hexagon_M2_mpyd_nac_ll_s1; break; 2629 2630 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_hh_s0: 2631 ID = Intrinsic::hexagon_M2_mpyd_hh_s0; break; 2632 2633 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_hh_s1: 2634 ID = Intrinsic::hexagon_M2_mpyd_hh_s1; break; 2635 2636 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_hl_s0: 2637 ID = Intrinsic::hexagon_M2_mpyd_hl_s0; break; 2638 2639 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_hl_s1: 2640 ID = Intrinsic::hexagon_M2_mpyd_hl_s1; break; 2641 2642 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_lh_s0: 2643 ID = Intrinsic::hexagon_M2_mpyd_lh_s0; break; 2644 2645 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_lh_s1: 2646 ID = Intrinsic::hexagon_M2_mpyd_lh_s1; break; 2647 2648 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_ll_s0: 2649 ID = Intrinsic::hexagon_M2_mpyd_ll_s0; break; 2650 2651 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_ll_s1: 2652 ID = Intrinsic::hexagon_M2_mpyd_ll_s1; break; 2653 2654 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_hh_s0: 2655 ID = Intrinsic::hexagon_M2_mpyd_rnd_hh_s0; break; 2656 2657 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_hh_s1: 2658 ID = Intrinsic::hexagon_M2_mpyd_rnd_hh_s1; break; 2659 2660 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_hl_s0: 2661 ID = Intrinsic::hexagon_M2_mpyd_rnd_hl_s0; break; 2662 2663 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_hl_s1: 2664 ID = Intrinsic::hexagon_M2_mpyd_rnd_hl_s1; break; 2665 2666 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_lh_s0: 2667 ID = Intrinsic::hexagon_M2_mpyd_rnd_lh_s0; break; 2668 2669 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_lh_s1: 2670 ID = Intrinsic::hexagon_M2_mpyd_rnd_lh_s1; break; 2671 2672 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_ll_s0: 2673 ID = Intrinsic::hexagon_M2_mpyd_rnd_ll_s0; break; 2674 2675 case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_ll_s1: 2676 ID = Intrinsic::hexagon_M2_mpyd_rnd_ll_s1; break; 2677 2678 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_hh_s0: 2679 ID = Intrinsic::hexagon_M2_mpyu_acc_hh_s0; break; 2680 2681 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_hh_s1: 2682 ID = Intrinsic::hexagon_M2_mpyu_acc_hh_s1; break; 2683 2684 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_hl_s0: 2685 ID = Intrinsic::hexagon_M2_mpyu_acc_hl_s0; break; 2686 2687 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_hl_s1: 2688 ID = Intrinsic::hexagon_M2_mpyu_acc_hl_s1; break; 2689 2690 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_lh_s0: 2691 ID = Intrinsic::hexagon_M2_mpyu_acc_lh_s0; break; 2692 2693 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_lh_s1: 2694 ID = Intrinsic::hexagon_M2_mpyu_acc_lh_s1; break; 2695 2696 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_ll_s0: 2697 ID = Intrinsic::hexagon_M2_mpyu_acc_ll_s0; break; 2698 2699 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_ll_s1: 2700 ID = Intrinsic::hexagon_M2_mpyu_acc_ll_s1; break; 2701 2702 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_hh_s0: 2703 ID = Intrinsic::hexagon_M2_mpyu_nac_hh_s0; break; 2704 2705 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_hh_s1: 2706 ID = Intrinsic::hexagon_M2_mpyu_nac_hh_s1; break; 2707 2708 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_hl_s0: 2709 ID = Intrinsic::hexagon_M2_mpyu_nac_hl_s0; break; 2710 2711 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_hl_s1: 2712 ID = Intrinsic::hexagon_M2_mpyu_nac_hl_s1; break; 2713 2714 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_lh_s0: 2715 ID = Intrinsic::hexagon_M2_mpyu_nac_lh_s0; break; 2716 2717 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_lh_s1: 2718 ID = Intrinsic::hexagon_M2_mpyu_nac_lh_s1; break; 2719 2720 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_ll_s0: 2721 ID = Intrinsic::hexagon_M2_mpyu_nac_ll_s0; break; 2722 2723 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_ll_s1: 2724 ID = Intrinsic::hexagon_M2_mpyu_nac_ll_s1; break; 2725 2726 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_hh_s0: 2727 ID = Intrinsic::hexagon_M2_mpyu_hh_s0; break; 2728 2729 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_hh_s1: 2730 ID = Intrinsic::hexagon_M2_mpyu_hh_s1; break; 2731 2732 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_hl_s0: 2733 ID = Intrinsic::hexagon_M2_mpyu_hl_s0; break; 2734 2735 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_hl_s1: 2736 ID = Intrinsic::hexagon_M2_mpyu_hl_s1; break; 2737 2738 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_lh_s0: 2739 ID = Intrinsic::hexagon_M2_mpyu_lh_s0; break; 2740 2741 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_lh_s1: 2742 ID = Intrinsic::hexagon_M2_mpyu_lh_s1; break; 2743 2744 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_ll_s0: 2745 ID = Intrinsic::hexagon_M2_mpyu_ll_s0; break; 2746 2747 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_ll_s1: 2748 ID = Intrinsic::hexagon_M2_mpyu_ll_s1; break; 2749 2750 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_hh_s0: 2751 ID = Intrinsic::hexagon_M2_mpyud_acc_hh_s0; break; 2752 2753 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_hh_s1: 2754 ID = Intrinsic::hexagon_M2_mpyud_acc_hh_s1; break; 2755 2756 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_hl_s0: 2757 ID = Intrinsic::hexagon_M2_mpyud_acc_hl_s0; break; 2758 2759 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_hl_s1: 2760 ID = Intrinsic::hexagon_M2_mpyud_acc_hl_s1; break; 2761 2762 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_lh_s0: 2763 ID = Intrinsic::hexagon_M2_mpyud_acc_lh_s0; break; 2764 2765 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_lh_s1: 2766 ID = Intrinsic::hexagon_M2_mpyud_acc_lh_s1; break; 2767 2768 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_ll_s0: 2769 ID = Intrinsic::hexagon_M2_mpyud_acc_ll_s0; break; 2770 2771 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_ll_s1: 2772 ID = Intrinsic::hexagon_M2_mpyud_acc_ll_s1; break; 2773 2774 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_hh_s0: 2775 ID = Intrinsic::hexagon_M2_mpyud_nac_hh_s0; break; 2776 2777 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_hh_s1: 2778 ID = Intrinsic::hexagon_M2_mpyud_nac_hh_s1; break; 2779 2780 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_hl_s0: 2781 ID = Intrinsic::hexagon_M2_mpyud_nac_hl_s0; break; 2782 2783 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_hl_s1: 2784 ID = Intrinsic::hexagon_M2_mpyud_nac_hl_s1; break; 2785 2786 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_lh_s0: 2787 ID = Intrinsic::hexagon_M2_mpyud_nac_lh_s0; break; 2788 2789 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_lh_s1: 2790 ID = Intrinsic::hexagon_M2_mpyud_nac_lh_s1; break; 2791 2792 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_ll_s0: 2793 ID = Intrinsic::hexagon_M2_mpyud_nac_ll_s0; break; 2794 2795 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_ll_s1: 2796 ID = Intrinsic::hexagon_M2_mpyud_nac_ll_s1; break; 2797 2798 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_hh_s0: 2799 ID = Intrinsic::hexagon_M2_mpyud_hh_s0; break; 2800 2801 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_hh_s1: 2802 ID = Intrinsic::hexagon_M2_mpyud_hh_s1; break; 2803 2804 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_hl_s0: 2805 ID = Intrinsic::hexagon_M2_mpyud_hl_s0; break; 2806 2807 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_hl_s1: 2808 ID = Intrinsic::hexagon_M2_mpyud_hl_s1; break; 2809 2810 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_lh_s0: 2811 ID = Intrinsic::hexagon_M2_mpyud_lh_s0; break; 2812 2813 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_lh_s1: 2814 ID = Intrinsic::hexagon_M2_mpyud_lh_s1; break; 2815 2816 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_ll_s0: 2817 ID = Intrinsic::hexagon_M2_mpyud_ll_s0; break; 2818 2819 case Hexagon::BI__builtin_HEXAGON_M2_mpyud_ll_s1: 2820 ID = Intrinsic::hexagon_M2_mpyud_ll_s1; break; 2821 2822 case Hexagon::BI__builtin_HEXAGON_M2_mpysmi: 2823 ID = Intrinsic::hexagon_M2_mpysmi; break; 2824 2825 case Hexagon::BI__builtin_HEXAGON_M2_macsip: 2826 ID = Intrinsic::hexagon_M2_macsip; break; 2827 2828 case Hexagon::BI__builtin_HEXAGON_M2_macsin: 2829 ID = Intrinsic::hexagon_M2_macsin; break; 2830 2831 case Hexagon::BI__builtin_HEXAGON_M2_dpmpyss_s0: 2832 ID = Intrinsic::hexagon_M2_dpmpyss_s0; break; 2833 2834 case Hexagon::BI__builtin_HEXAGON_M2_dpmpyss_acc_s0: 2835 ID = Intrinsic::hexagon_M2_dpmpyss_acc_s0; break; 2836 2837 case Hexagon::BI__builtin_HEXAGON_M2_dpmpyss_nac_s0: 2838 ID = Intrinsic::hexagon_M2_dpmpyss_nac_s0; break; 2839 2840 case Hexagon::BI__builtin_HEXAGON_M2_dpmpyuu_s0: 2841 ID = Intrinsic::hexagon_M2_dpmpyuu_s0; break; 2842 2843 case Hexagon::BI__builtin_HEXAGON_M2_dpmpyuu_acc_s0: 2844 ID = Intrinsic::hexagon_M2_dpmpyuu_acc_s0; break; 2845 2846 case Hexagon::BI__builtin_HEXAGON_M2_dpmpyuu_nac_s0: 2847 ID = Intrinsic::hexagon_M2_dpmpyuu_nac_s0; break; 2848 2849 case Hexagon::BI__builtin_HEXAGON_M2_mpy_up: 2850 ID = Intrinsic::hexagon_M2_mpy_up; break; 2851 2852 case Hexagon::BI__builtin_HEXAGON_M2_mpyu_up: 2853 ID = Intrinsic::hexagon_M2_mpyu_up; break; 2854 2855 case Hexagon::BI__builtin_HEXAGON_M2_dpmpyss_rnd_s0: 2856 ID = Intrinsic::hexagon_M2_dpmpyss_rnd_s0; break; 2857 2858 case Hexagon::BI__builtin_HEXAGON_M2_mpyi: 2859 ID = Intrinsic::hexagon_M2_mpyi; break; 2860 2861 case Hexagon::BI__builtin_HEXAGON_M2_mpyui: 2862 ID = Intrinsic::hexagon_M2_mpyui; break; 2863 2864 case Hexagon::BI__builtin_HEXAGON_M2_maci: 2865 ID = Intrinsic::hexagon_M2_maci; break; 2866 2867 case Hexagon::BI__builtin_HEXAGON_M2_acci: 2868 ID = Intrinsic::hexagon_M2_acci; break; 2869 2870 case Hexagon::BI__builtin_HEXAGON_M2_accii: 2871 ID = Intrinsic::hexagon_M2_accii; break; 2872 2873 case Hexagon::BI__builtin_HEXAGON_M2_nacci: 2874 ID = Intrinsic::hexagon_M2_nacci; break; 2875 2876 case Hexagon::BI__builtin_HEXAGON_M2_naccii: 2877 ID = Intrinsic::hexagon_M2_naccii; break; 2878 2879 case Hexagon::BI__builtin_HEXAGON_M2_subacc: 2880 ID = Intrinsic::hexagon_M2_subacc; break; 2881 2882 case Hexagon::BI__builtin_HEXAGON_M2_vmpy2s_s0: 2883 ID = Intrinsic::hexagon_M2_vmpy2s_s0; break; 2884 2885 case Hexagon::BI__builtin_HEXAGON_M2_vmpy2s_s1: 2886 ID = Intrinsic::hexagon_M2_vmpy2s_s1; break; 2887 2888 case Hexagon::BI__builtin_HEXAGON_M2_vmac2s_s0: 2889 ID = Intrinsic::hexagon_M2_vmac2s_s0; break; 2890 2891 case Hexagon::BI__builtin_HEXAGON_M2_vmac2s_s1: 2892 ID = Intrinsic::hexagon_M2_vmac2s_s1; break; 2893 2894 case Hexagon::BI__builtin_HEXAGON_M2_vmpy2s_s0pack: 2895 ID = Intrinsic::hexagon_M2_vmpy2s_s0pack; break; 2896 2897 case Hexagon::BI__builtin_HEXAGON_M2_vmpy2s_s1pack: 2898 ID = Intrinsic::hexagon_M2_vmpy2s_s1pack; break; 2899 2900 case Hexagon::BI__builtin_HEXAGON_M2_vmac2: 2901 ID = Intrinsic::hexagon_M2_vmac2; break; 2902 2903 case Hexagon::BI__builtin_HEXAGON_M2_vmpy2es_s0: 2904 ID = Intrinsic::hexagon_M2_vmpy2es_s0; break; 2905 2906 case Hexagon::BI__builtin_HEXAGON_M2_vmpy2es_s1: 2907 ID = Intrinsic::hexagon_M2_vmpy2es_s1; break; 2908 2909 case Hexagon::BI__builtin_HEXAGON_M2_vmac2es_s0: 2910 ID = Intrinsic::hexagon_M2_vmac2es_s0; break; 2911 2912 case Hexagon::BI__builtin_HEXAGON_M2_vmac2es_s1: 2913 ID = Intrinsic::hexagon_M2_vmac2es_s1; break; 2914 2915 case Hexagon::BI__builtin_HEXAGON_M2_vmac2es: 2916 ID = Intrinsic::hexagon_M2_vmac2es; break; 2917 2918 case Hexagon::BI__builtin_HEXAGON_M2_vrmac_s0: 2919 ID = Intrinsic::hexagon_M2_vrmac_s0; break; 2920 2921 case Hexagon::BI__builtin_HEXAGON_M2_vrmpy_s0: 2922 ID = Intrinsic::hexagon_M2_vrmpy_s0; break; 2923 2924 case Hexagon::BI__builtin_HEXAGON_M2_vdmpyrs_s0: 2925 ID = Intrinsic::hexagon_M2_vdmpyrs_s0; break; 2926 2927 case Hexagon::BI__builtin_HEXAGON_M2_vdmpyrs_s1: 2928 ID = Intrinsic::hexagon_M2_vdmpyrs_s1; break; 2929 2930 case Hexagon::BI__builtin_HEXAGON_M2_vdmacs_s0: 2931 ID = Intrinsic::hexagon_M2_vdmacs_s0; break; 2932 2933 case Hexagon::BI__builtin_HEXAGON_M2_vdmacs_s1: 2934 ID = Intrinsic::hexagon_M2_vdmacs_s1; break; 2935 2936 case Hexagon::BI__builtin_HEXAGON_M2_vdmpys_s0: 2937 ID = Intrinsic::hexagon_M2_vdmpys_s0; break; 2938 2939 case Hexagon::BI__builtin_HEXAGON_M2_vdmpys_s1: 2940 ID = Intrinsic::hexagon_M2_vdmpys_s1; break; 2941 2942 case Hexagon::BI__builtin_HEXAGON_M2_cmpyrs_s0: 2943 ID = Intrinsic::hexagon_M2_cmpyrs_s0; break; 2944 2945 case Hexagon::BI__builtin_HEXAGON_M2_cmpyrs_s1: 2946 ID = Intrinsic::hexagon_M2_cmpyrs_s1; break; 2947 2948 case Hexagon::BI__builtin_HEXAGON_M2_cmpyrsc_s0: 2949 ID = Intrinsic::hexagon_M2_cmpyrsc_s0; break; 2950 2951 case Hexagon::BI__builtin_HEXAGON_M2_cmpyrsc_s1: 2952 ID = Intrinsic::hexagon_M2_cmpyrsc_s1; break; 2953 2954 case Hexagon::BI__builtin_HEXAGON_M2_cmacs_s0: 2955 ID = Intrinsic::hexagon_M2_cmacs_s0; break; 2956 2957 case Hexagon::BI__builtin_HEXAGON_M2_cmacs_s1: 2958 ID = Intrinsic::hexagon_M2_cmacs_s1; break; 2959 2960 case Hexagon::BI__builtin_HEXAGON_M2_cmacsc_s0: 2961 ID = Intrinsic::hexagon_M2_cmacsc_s0; break; 2962 2963 case Hexagon::BI__builtin_HEXAGON_M2_cmacsc_s1: 2964 ID = Intrinsic::hexagon_M2_cmacsc_s1; break; 2965 2966 case Hexagon::BI__builtin_HEXAGON_M2_cmpys_s0: 2967 ID = Intrinsic::hexagon_M2_cmpys_s0; break; 2968 2969 case Hexagon::BI__builtin_HEXAGON_M2_cmpys_s1: 2970 ID = Intrinsic::hexagon_M2_cmpys_s1; break; 2971 2972 case Hexagon::BI__builtin_HEXAGON_M2_cmpysc_s0: 2973 ID = Intrinsic::hexagon_M2_cmpysc_s0; break; 2974 2975 case Hexagon::BI__builtin_HEXAGON_M2_cmpysc_s1: 2976 ID = Intrinsic::hexagon_M2_cmpysc_s1; break; 2977 2978 case Hexagon::BI__builtin_HEXAGON_M2_cnacs_s0: 2979 ID = Intrinsic::hexagon_M2_cnacs_s0; break; 2980 2981 case Hexagon::BI__builtin_HEXAGON_M2_cnacs_s1: 2982 ID = Intrinsic::hexagon_M2_cnacs_s1; break; 2983 2984 case Hexagon::BI__builtin_HEXAGON_M2_cnacsc_s0: 2985 ID = Intrinsic::hexagon_M2_cnacsc_s0; break; 2986 2987 case Hexagon::BI__builtin_HEXAGON_M2_cnacsc_s1: 2988 ID = Intrinsic::hexagon_M2_cnacsc_s1; break; 2989 2990 case Hexagon::BI__builtin_HEXAGON_M2_vrcmpys_s1: 2991 ID = Intrinsic::hexagon_M2_vrcmpys_s1; break; 2992 2993 case Hexagon::BI__builtin_HEXAGON_M2_vrcmpys_acc_s1: 2994 ID = Intrinsic::hexagon_M2_vrcmpys_acc_s1; break; 2995 2996 case Hexagon::BI__builtin_HEXAGON_M2_vrcmpys_s1rp: 2997 ID = Intrinsic::hexagon_M2_vrcmpys_s1rp; break; 2998 2999 case Hexagon::BI__builtin_HEXAGON_M2_mmacls_s0: 3000 ID = Intrinsic::hexagon_M2_mmacls_s0; break; 3001 3002 case Hexagon::BI__builtin_HEXAGON_M2_mmacls_s1: 3003 ID = Intrinsic::hexagon_M2_mmacls_s1; break; 3004 3005 case Hexagon::BI__builtin_HEXAGON_M2_mmachs_s0: 3006 ID = Intrinsic::hexagon_M2_mmachs_s0; break; 3007 3008 case Hexagon::BI__builtin_HEXAGON_M2_mmachs_s1: 3009 ID = Intrinsic::hexagon_M2_mmachs_s1; break; 3010 3011 case Hexagon::BI__builtin_HEXAGON_M2_mmpyl_s0: 3012 ID = Intrinsic::hexagon_M2_mmpyl_s0; break; 3013 3014 case Hexagon::BI__builtin_HEXAGON_M2_mmpyl_s1: 3015 ID = Intrinsic::hexagon_M2_mmpyl_s1; break; 3016 3017 case Hexagon::BI__builtin_HEXAGON_M2_mmpyh_s0: 3018 ID = Intrinsic::hexagon_M2_mmpyh_s0; break; 3019 3020 case Hexagon::BI__builtin_HEXAGON_M2_mmpyh_s1: 3021 ID = Intrinsic::hexagon_M2_mmpyh_s1; break; 3022 3023 case Hexagon::BI__builtin_HEXAGON_M2_mmacls_rs0: 3024 ID = Intrinsic::hexagon_M2_mmacls_rs0; break; 3025 3026 case Hexagon::BI__builtin_HEXAGON_M2_mmacls_rs1: 3027 ID = Intrinsic::hexagon_M2_mmacls_rs1; break; 3028 3029 case Hexagon::BI__builtin_HEXAGON_M2_mmachs_rs0: 3030 ID = Intrinsic::hexagon_M2_mmachs_rs0; break; 3031 3032 case Hexagon::BI__builtin_HEXAGON_M2_mmachs_rs1: 3033 ID = Intrinsic::hexagon_M2_mmachs_rs1; break; 3034 3035 case Hexagon::BI__builtin_HEXAGON_M2_mmpyl_rs0: 3036 ID = Intrinsic::hexagon_M2_mmpyl_rs0; break; 3037 3038 case Hexagon::BI__builtin_HEXAGON_M2_mmpyl_rs1: 3039 ID = Intrinsic::hexagon_M2_mmpyl_rs1; break; 3040 3041 case Hexagon::BI__builtin_HEXAGON_M2_mmpyh_rs0: 3042 ID = Intrinsic::hexagon_M2_mmpyh_rs0; break; 3043 3044 case Hexagon::BI__builtin_HEXAGON_M2_mmpyh_rs1: 3045 ID = Intrinsic::hexagon_M2_mmpyh_rs1; break; 3046 3047 case Hexagon::BI__builtin_HEXAGON_M2_hmmpyl_rs1: 3048 ID = Intrinsic::hexagon_M2_hmmpyl_rs1; break; 3049 3050 case Hexagon::BI__builtin_HEXAGON_M2_hmmpyh_rs1: 3051 ID = Intrinsic::hexagon_M2_hmmpyh_rs1; break; 3052 3053 case Hexagon::BI__builtin_HEXAGON_M2_mmaculs_s0: 3054 ID = Intrinsic::hexagon_M2_mmaculs_s0; break; 3055 3056 case Hexagon::BI__builtin_HEXAGON_M2_mmaculs_s1: 3057 ID = Intrinsic::hexagon_M2_mmaculs_s1; break; 3058 3059 case Hexagon::BI__builtin_HEXAGON_M2_mmacuhs_s0: 3060 ID = Intrinsic::hexagon_M2_mmacuhs_s0; break; 3061 3062 case Hexagon::BI__builtin_HEXAGON_M2_mmacuhs_s1: 3063 ID = Intrinsic::hexagon_M2_mmacuhs_s1; break; 3064 3065 case Hexagon::BI__builtin_HEXAGON_M2_mmpyul_s0: 3066 ID = Intrinsic::hexagon_M2_mmpyul_s0; break; 3067 3068 case Hexagon::BI__builtin_HEXAGON_M2_mmpyul_s1: 3069 ID = Intrinsic::hexagon_M2_mmpyul_s1; break; 3070 3071 case Hexagon::BI__builtin_HEXAGON_M2_mmpyuh_s0: 3072 ID = Intrinsic::hexagon_M2_mmpyuh_s0; break; 3073 3074 case Hexagon::BI__builtin_HEXAGON_M2_mmpyuh_s1: 3075 ID = Intrinsic::hexagon_M2_mmpyuh_s1; break; 3076 3077 case Hexagon::BI__builtin_HEXAGON_M2_mmaculs_rs0: 3078 ID = Intrinsic::hexagon_M2_mmaculs_rs0; break; 3079 3080 case Hexagon::BI__builtin_HEXAGON_M2_mmaculs_rs1: 3081 ID = Intrinsic::hexagon_M2_mmaculs_rs1; break; 3082 3083 case Hexagon::BI__builtin_HEXAGON_M2_mmacuhs_rs0: 3084 ID = Intrinsic::hexagon_M2_mmacuhs_rs0; break; 3085 3086 case Hexagon::BI__builtin_HEXAGON_M2_mmacuhs_rs1: 3087 ID = Intrinsic::hexagon_M2_mmacuhs_rs1; break; 3088 3089 case Hexagon::BI__builtin_HEXAGON_M2_mmpyul_rs0: 3090 ID = Intrinsic::hexagon_M2_mmpyul_rs0; break; 3091 3092 case Hexagon::BI__builtin_HEXAGON_M2_mmpyul_rs1: 3093 ID = Intrinsic::hexagon_M2_mmpyul_rs1; break; 3094 3095 case Hexagon::BI__builtin_HEXAGON_M2_mmpyuh_rs0: 3096 ID = Intrinsic::hexagon_M2_mmpyuh_rs0; break; 3097 3098 case Hexagon::BI__builtin_HEXAGON_M2_mmpyuh_rs1: 3099 ID = Intrinsic::hexagon_M2_mmpyuh_rs1; break; 3100 3101 case Hexagon::BI__builtin_HEXAGON_M2_vrcmaci_s0: 3102 ID = Intrinsic::hexagon_M2_vrcmaci_s0; break; 3103 3104 case Hexagon::BI__builtin_HEXAGON_M2_vrcmacr_s0: 3105 ID = Intrinsic::hexagon_M2_vrcmacr_s0; break; 3106 3107 case Hexagon::BI__builtin_HEXAGON_M2_vrcmaci_s0c: 3108 ID = Intrinsic::hexagon_M2_vrcmaci_s0c; break; 3109 3110 case Hexagon::BI__builtin_HEXAGON_M2_vrcmacr_s0c: 3111 ID = Intrinsic::hexagon_M2_vrcmacr_s0c; break; 3112 3113 case Hexagon::BI__builtin_HEXAGON_M2_cmaci_s0: 3114 ID = Intrinsic::hexagon_M2_cmaci_s0; break; 3115 3116 case Hexagon::BI__builtin_HEXAGON_M2_cmacr_s0: 3117 ID = Intrinsic::hexagon_M2_cmacr_s0; break; 3118 3119 case Hexagon::BI__builtin_HEXAGON_M2_vrcmpyi_s0: 3120 ID = Intrinsic::hexagon_M2_vrcmpyi_s0; break; 3121 3122 case Hexagon::BI__builtin_HEXAGON_M2_vrcmpyr_s0: 3123 ID = Intrinsic::hexagon_M2_vrcmpyr_s0; break; 3124 3125 case Hexagon::BI__builtin_HEXAGON_M2_vrcmpyi_s0c: 3126 ID = Intrinsic::hexagon_M2_vrcmpyi_s0c; break; 3127 3128 case Hexagon::BI__builtin_HEXAGON_M2_vrcmpyr_s0c: 3129 ID = Intrinsic::hexagon_M2_vrcmpyr_s0c; break; 3130 3131 case Hexagon::BI__builtin_HEXAGON_M2_cmpyi_s0: 3132 ID = Intrinsic::hexagon_M2_cmpyi_s0; break; 3133 3134 case Hexagon::BI__builtin_HEXAGON_M2_cmpyr_s0: 3135 ID = Intrinsic::hexagon_M2_cmpyr_s0; break; 3136 3137 case Hexagon::BI__builtin_HEXAGON_M2_vcmpy_s0_sat_i: 3138 ID = Intrinsic::hexagon_M2_vcmpy_s0_sat_i; break; 3139 3140 case Hexagon::BI__builtin_HEXAGON_M2_vcmpy_s0_sat_r: 3141 ID = Intrinsic::hexagon_M2_vcmpy_s0_sat_r; break; 3142 3143 case Hexagon::BI__builtin_HEXAGON_M2_vcmpy_s1_sat_i: 3144 ID = Intrinsic::hexagon_M2_vcmpy_s1_sat_i; break; 3145 3146 case Hexagon::BI__builtin_HEXAGON_M2_vcmpy_s1_sat_r: 3147 ID = Intrinsic::hexagon_M2_vcmpy_s1_sat_r; break; 3148 3149 case Hexagon::BI__builtin_HEXAGON_M2_vcmac_s0_sat_i: 3150 ID = Intrinsic::hexagon_M2_vcmac_s0_sat_i; break; 3151 3152 case Hexagon::BI__builtin_HEXAGON_M2_vcmac_s0_sat_r: 3153 ID = Intrinsic::hexagon_M2_vcmac_s0_sat_r; break; 3154 3155 case Hexagon::BI__builtin_HEXAGON_S2_vcrotate: 3156 ID = Intrinsic::hexagon_S2_vcrotate; break; 3157 3158 case Hexagon::BI__builtin_HEXAGON_A2_add: 3159 ID = Intrinsic::hexagon_A2_add; break; 3160 3161 case Hexagon::BI__builtin_HEXAGON_A2_sub: 3162 ID = Intrinsic::hexagon_A2_sub; break; 3163 3164 case Hexagon::BI__builtin_HEXAGON_A2_addsat: 3165 ID = Intrinsic::hexagon_A2_addsat; break; 3166 3167 case Hexagon::BI__builtin_HEXAGON_A2_subsat: 3168 ID = Intrinsic::hexagon_A2_subsat; break; 3169 3170 case Hexagon::BI__builtin_HEXAGON_A2_addi: 3171 ID = Intrinsic::hexagon_A2_addi; break; 3172 3173 case Hexagon::BI__builtin_HEXAGON_A2_addh_l16_ll: 3174 ID = Intrinsic::hexagon_A2_addh_l16_ll; break; 3175 3176 case Hexagon::BI__builtin_HEXAGON_A2_addh_l16_hl: 3177 ID = Intrinsic::hexagon_A2_addh_l16_hl; break; 3178 3179 case Hexagon::BI__builtin_HEXAGON_A2_addh_l16_sat_ll: 3180 ID = Intrinsic::hexagon_A2_addh_l16_sat_ll; break; 3181 3182 case Hexagon::BI__builtin_HEXAGON_A2_addh_l16_sat_hl: 3183 ID = Intrinsic::hexagon_A2_addh_l16_sat_hl; break; 3184 3185 case Hexagon::BI__builtin_HEXAGON_A2_subh_l16_ll: 3186 ID = Intrinsic::hexagon_A2_subh_l16_ll; break; 3187 3188 case Hexagon::BI__builtin_HEXAGON_A2_subh_l16_hl: 3189 ID = Intrinsic::hexagon_A2_subh_l16_hl; break; 3190 3191 case Hexagon::BI__builtin_HEXAGON_A2_subh_l16_sat_ll: 3192 ID = Intrinsic::hexagon_A2_subh_l16_sat_ll; break; 3193 3194 case Hexagon::BI__builtin_HEXAGON_A2_subh_l16_sat_hl: 3195 ID = Intrinsic::hexagon_A2_subh_l16_sat_hl; break; 3196 3197 case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_ll: 3198 ID = Intrinsic::hexagon_A2_addh_h16_ll; break; 3199 3200 case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_lh: 3201 ID = Intrinsic::hexagon_A2_addh_h16_lh; break; 3202 3203 case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_hl: 3204 ID = Intrinsic::hexagon_A2_addh_h16_hl; break; 3205 3206 case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_hh: 3207 ID = Intrinsic::hexagon_A2_addh_h16_hh; break; 3208 3209 case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_sat_ll: 3210 ID = Intrinsic::hexagon_A2_addh_h16_sat_ll; break; 3211 3212 case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_sat_lh: 3213 ID = Intrinsic::hexagon_A2_addh_h16_sat_lh; break; 3214 3215 case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_sat_hl: 3216 ID = Intrinsic::hexagon_A2_addh_h16_sat_hl; break; 3217 3218 case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_sat_hh: 3219 ID = Intrinsic::hexagon_A2_addh_h16_sat_hh; break; 3220 3221 case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_ll: 3222 ID = Intrinsic::hexagon_A2_subh_h16_ll; break; 3223 3224 case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_lh: 3225 ID = Intrinsic::hexagon_A2_subh_h16_lh; break; 3226 3227 case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_hl: 3228 ID = Intrinsic::hexagon_A2_subh_h16_hl; break; 3229 3230 case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_hh: 3231 ID = Intrinsic::hexagon_A2_subh_h16_hh; break; 3232 3233 case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_sat_ll: 3234 ID = Intrinsic::hexagon_A2_subh_h16_sat_ll; break; 3235 3236 case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_sat_lh: 3237 ID = Intrinsic::hexagon_A2_subh_h16_sat_lh; break; 3238 3239 case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_sat_hl: 3240 ID = Intrinsic::hexagon_A2_subh_h16_sat_hl; break; 3241 3242 case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_sat_hh: 3243 ID = Intrinsic::hexagon_A2_subh_h16_sat_hh; break; 3244 3245 case Hexagon::BI__builtin_HEXAGON_A2_aslh: 3246 ID = Intrinsic::hexagon_A2_aslh; break; 3247 3248 case Hexagon::BI__builtin_HEXAGON_A2_asrh: 3249 ID = Intrinsic::hexagon_A2_asrh; break; 3250 3251 case Hexagon::BI__builtin_HEXAGON_A2_addp: 3252 ID = Intrinsic::hexagon_A2_addp; break; 3253 3254 case Hexagon::BI__builtin_HEXAGON_A2_addpsat: 3255 ID = Intrinsic::hexagon_A2_addpsat; break; 3256 3257 case Hexagon::BI__builtin_HEXAGON_A2_addsp: 3258 ID = Intrinsic::hexagon_A2_addsp; break; 3259 3260 case Hexagon::BI__builtin_HEXAGON_A2_subp: 3261 ID = Intrinsic::hexagon_A2_subp; break; 3262 3263 case Hexagon::BI__builtin_HEXAGON_A2_neg: 3264 ID = Intrinsic::hexagon_A2_neg; break; 3265 3266 case Hexagon::BI__builtin_HEXAGON_A2_negsat: 3267 ID = Intrinsic::hexagon_A2_negsat; break; 3268 3269 case Hexagon::BI__builtin_HEXAGON_A2_abs: 3270 ID = Intrinsic::hexagon_A2_abs; break; 3271 3272 case Hexagon::BI__builtin_HEXAGON_A2_abssat: 3273 ID = Intrinsic::hexagon_A2_abssat; break; 3274 3275 case Hexagon::BI__builtin_HEXAGON_A2_vconj: 3276 ID = Intrinsic::hexagon_A2_vconj; break; 3277 3278 case Hexagon::BI__builtin_HEXAGON_A2_negp: 3279 ID = Intrinsic::hexagon_A2_negp; break; 3280 3281 case Hexagon::BI__builtin_HEXAGON_A2_absp: 3282 ID = Intrinsic::hexagon_A2_absp; break; 3283 3284 case Hexagon::BI__builtin_HEXAGON_A2_max: 3285 ID = Intrinsic::hexagon_A2_max; break; 3286 3287 case Hexagon::BI__builtin_HEXAGON_A2_maxu: 3288 ID = Intrinsic::hexagon_A2_maxu; break; 3289 3290 case Hexagon::BI__builtin_HEXAGON_A2_min: 3291 ID = Intrinsic::hexagon_A2_min; break; 3292 3293 case Hexagon::BI__builtin_HEXAGON_A2_minu: 3294 ID = Intrinsic::hexagon_A2_minu; break; 3295 3296 case Hexagon::BI__builtin_HEXAGON_A2_maxp: 3297 ID = Intrinsic::hexagon_A2_maxp; break; 3298 3299 case Hexagon::BI__builtin_HEXAGON_A2_maxup: 3300 ID = Intrinsic::hexagon_A2_maxup; break; 3301 3302 case Hexagon::BI__builtin_HEXAGON_A2_minp: 3303 ID = Intrinsic::hexagon_A2_minp; break; 3304 3305 case Hexagon::BI__builtin_HEXAGON_A2_minup: 3306 ID = Intrinsic::hexagon_A2_minup; break; 3307 3308 case Hexagon::BI__builtin_HEXAGON_A2_tfr: 3309 ID = Intrinsic::hexagon_A2_tfr; break; 3310 3311 case Hexagon::BI__builtin_HEXAGON_A2_tfrsi: 3312 ID = Intrinsic::hexagon_A2_tfrsi; break; 3313 3314 case Hexagon::BI__builtin_HEXAGON_A2_tfrp: 3315 ID = Intrinsic::hexagon_A2_tfrp; break; 3316 3317 case Hexagon::BI__builtin_HEXAGON_A2_tfrpi: 3318 ID = Intrinsic::hexagon_A2_tfrpi; break; 3319 3320 case Hexagon::BI__builtin_HEXAGON_A2_zxtb: 3321 ID = Intrinsic::hexagon_A2_zxtb; break; 3322 3323 case Hexagon::BI__builtin_HEXAGON_A2_sxtb: 3324 ID = Intrinsic::hexagon_A2_sxtb; break; 3325 3326 case Hexagon::BI__builtin_HEXAGON_A2_zxth: 3327 ID = Intrinsic::hexagon_A2_zxth; break; 3328 3329 case Hexagon::BI__builtin_HEXAGON_A2_sxth: 3330 ID = Intrinsic::hexagon_A2_sxth; break; 3331 3332 case Hexagon::BI__builtin_HEXAGON_A2_combinew: 3333 ID = Intrinsic::hexagon_A2_combinew; break; 3334 3335 case Hexagon::BI__builtin_HEXAGON_A2_combineii: 3336 ID = Intrinsic::hexagon_A2_combineii; break; 3337 3338 case Hexagon::BI__builtin_HEXAGON_A2_combine_hh: 3339 ID = Intrinsic::hexagon_A2_combine_hh; break; 3340 3341 case Hexagon::BI__builtin_HEXAGON_A2_combine_hl: 3342 ID = Intrinsic::hexagon_A2_combine_hl; break; 3343 3344 case Hexagon::BI__builtin_HEXAGON_A2_combine_lh: 3345 ID = Intrinsic::hexagon_A2_combine_lh; break; 3346 3347 case Hexagon::BI__builtin_HEXAGON_A2_combine_ll: 3348 ID = Intrinsic::hexagon_A2_combine_ll; break; 3349 3350 case Hexagon::BI__builtin_HEXAGON_A2_tfril: 3351 ID = Intrinsic::hexagon_A2_tfril; break; 3352 3353 case Hexagon::BI__builtin_HEXAGON_A2_tfrih: 3354 ID = Intrinsic::hexagon_A2_tfrih; break; 3355 3356 case Hexagon::BI__builtin_HEXAGON_A2_and: 3357 ID = Intrinsic::hexagon_A2_and; break; 3358 3359 case Hexagon::BI__builtin_HEXAGON_A2_or: 3360 ID = Intrinsic::hexagon_A2_or; break; 3361 3362 case Hexagon::BI__builtin_HEXAGON_A2_xor: 3363 ID = Intrinsic::hexagon_A2_xor; break; 3364 3365 case Hexagon::BI__builtin_HEXAGON_A2_not: 3366 ID = Intrinsic::hexagon_A2_not; break; 3367 3368 case Hexagon::BI__builtin_HEXAGON_M2_xor_xacc: 3369 ID = Intrinsic::hexagon_M2_xor_xacc; break; 3370 3371 case Hexagon::BI__builtin_HEXAGON_A2_subri: 3372 ID = Intrinsic::hexagon_A2_subri; break; 3373 3374 case Hexagon::BI__builtin_HEXAGON_A2_andir: 3375 ID = Intrinsic::hexagon_A2_andir; break; 3376 3377 case Hexagon::BI__builtin_HEXAGON_A2_orir: 3378 ID = Intrinsic::hexagon_A2_orir; break; 3379 3380 case Hexagon::BI__builtin_HEXAGON_A2_andp: 3381 ID = Intrinsic::hexagon_A2_andp; break; 3382 3383 case Hexagon::BI__builtin_HEXAGON_A2_orp: 3384 ID = Intrinsic::hexagon_A2_orp; break; 3385 3386 case Hexagon::BI__builtin_HEXAGON_A2_xorp: 3387 ID = Intrinsic::hexagon_A2_xorp; break; 3388 3389 case Hexagon::BI__builtin_HEXAGON_A2_notp: 3390 ID = Intrinsic::hexagon_A2_notp; break; 3391 3392 case Hexagon::BI__builtin_HEXAGON_A2_sxtw: 3393 ID = Intrinsic::hexagon_A2_sxtw; break; 3394 3395 case Hexagon::BI__builtin_HEXAGON_A2_sat: 3396 ID = Intrinsic::hexagon_A2_sat; break; 3397 3398 case Hexagon::BI__builtin_HEXAGON_A2_sath: 3399 ID = Intrinsic::hexagon_A2_sath; break; 3400 3401 case Hexagon::BI__builtin_HEXAGON_A2_satuh: 3402 ID = Intrinsic::hexagon_A2_satuh; break; 3403 3404 case Hexagon::BI__builtin_HEXAGON_A2_satub: 3405 ID = Intrinsic::hexagon_A2_satub; break; 3406 3407 case Hexagon::BI__builtin_HEXAGON_A2_satb: 3408 ID = Intrinsic::hexagon_A2_satb; break; 3409 3410 case Hexagon::BI__builtin_HEXAGON_A2_vaddub: 3411 ID = Intrinsic::hexagon_A2_vaddub; break; 3412 3413 case Hexagon::BI__builtin_HEXAGON_A2_vaddubs: 3414 ID = Intrinsic::hexagon_A2_vaddubs; break; 3415 3416 case Hexagon::BI__builtin_HEXAGON_A2_vaddh: 3417 ID = Intrinsic::hexagon_A2_vaddh; break; 3418 3419 case Hexagon::BI__builtin_HEXAGON_A2_vaddhs: 3420 ID = Intrinsic::hexagon_A2_vaddhs; break; 3421 3422 case Hexagon::BI__builtin_HEXAGON_A2_vadduhs: 3423 ID = Intrinsic::hexagon_A2_vadduhs; break; 3424 3425 case Hexagon::BI__builtin_HEXAGON_A2_vaddw: 3426 ID = Intrinsic::hexagon_A2_vaddw; break; 3427 3428 case Hexagon::BI__builtin_HEXAGON_A2_vaddws: 3429 ID = Intrinsic::hexagon_A2_vaddws; break; 3430 3431 case Hexagon::BI__builtin_HEXAGON_A2_svavgh: 3432 ID = Intrinsic::hexagon_A2_svavgh; break; 3433 3434 case Hexagon::BI__builtin_HEXAGON_A2_svavghs: 3435 ID = Intrinsic::hexagon_A2_svavghs; break; 3436 3437 case Hexagon::BI__builtin_HEXAGON_A2_svnavgh: 3438 ID = Intrinsic::hexagon_A2_svnavgh; break; 3439 3440 case Hexagon::BI__builtin_HEXAGON_A2_svaddh: 3441 ID = Intrinsic::hexagon_A2_svaddh; break; 3442 3443 case Hexagon::BI__builtin_HEXAGON_A2_svaddhs: 3444 ID = Intrinsic::hexagon_A2_svaddhs; break; 3445 3446 case Hexagon::BI__builtin_HEXAGON_A2_svadduhs: 3447 ID = Intrinsic::hexagon_A2_svadduhs; break; 3448 3449 case Hexagon::BI__builtin_HEXAGON_A2_svsubh: 3450 ID = Intrinsic::hexagon_A2_svsubh; break; 3451 3452 case Hexagon::BI__builtin_HEXAGON_A2_svsubhs: 3453 ID = Intrinsic::hexagon_A2_svsubhs; break; 3454 3455 case Hexagon::BI__builtin_HEXAGON_A2_svsubuhs: 3456 ID = Intrinsic::hexagon_A2_svsubuhs; break; 3457 3458 case Hexagon::BI__builtin_HEXAGON_A2_vraddub: 3459 ID = Intrinsic::hexagon_A2_vraddub; break; 3460 3461 case Hexagon::BI__builtin_HEXAGON_A2_vraddub_acc: 3462 ID = Intrinsic::hexagon_A2_vraddub_acc; break; 3463 3464 case Hexagon::BI__builtin_HEXAGON_M2_vradduh: 3465 ID = Intrinsic::hexagon_M2_vradduh; break; 3466 3467 case Hexagon::BI__builtin_HEXAGON_A2_vsubub: 3468 ID = Intrinsic::hexagon_A2_vsubub; break; 3469 3470 case Hexagon::BI__builtin_HEXAGON_A2_vsububs: 3471 ID = Intrinsic::hexagon_A2_vsububs; break; 3472 3473 case Hexagon::BI__builtin_HEXAGON_A2_vsubh: 3474 ID = Intrinsic::hexagon_A2_vsubh; break; 3475 3476 case Hexagon::BI__builtin_HEXAGON_A2_vsubhs: 3477 ID = Intrinsic::hexagon_A2_vsubhs; break; 3478 3479 case Hexagon::BI__builtin_HEXAGON_A2_vsubuhs: 3480 ID = Intrinsic::hexagon_A2_vsubuhs; break; 3481 3482 case Hexagon::BI__builtin_HEXAGON_A2_vsubw: 3483 ID = Intrinsic::hexagon_A2_vsubw; break; 3484 3485 case Hexagon::BI__builtin_HEXAGON_A2_vsubws: 3486 ID = Intrinsic::hexagon_A2_vsubws; break; 3487 3488 case Hexagon::BI__builtin_HEXAGON_A2_vabsh: 3489 ID = Intrinsic::hexagon_A2_vabsh; break; 3490 3491 case Hexagon::BI__builtin_HEXAGON_A2_vabshsat: 3492 ID = Intrinsic::hexagon_A2_vabshsat; break; 3493 3494 case Hexagon::BI__builtin_HEXAGON_A2_vabsw: 3495 ID = Intrinsic::hexagon_A2_vabsw; break; 3496 3497 case Hexagon::BI__builtin_HEXAGON_A2_vabswsat: 3498 ID = Intrinsic::hexagon_A2_vabswsat; break; 3499 3500 case Hexagon::BI__builtin_HEXAGON_M2_vabsdiffw: 3501 ID = Intrinsic::hexagon_M2_vabsdiffw; break; 3502 3503 case Hexagon::BI__builtin_HEXAGON_M2_vabsdiffh: 3504 ID = Intrinsic::hexagon_M2_vabsdiffh; break; 3505 3506 case Hexagon::BI__builtin_HEXAGON_A2_vrsadub: 3507 ID = Intrinsic::hexagon_A2_vrsadub; break; 3508 3509 case Hexagon::BI__builtin_HEXAGON_A2_vrsadub_acc: 3510 ID = Intrinsic::hexagon_A2_vrsadub_acc; break; 3511 3512 case Hexagon::BI__builtin_HEXAGON_A2_vavgub: 3513 ID = Intrinsic::hexagon_A2_vavgub; break; 3514 3515 case Hexagon::BI__builtin_HEXAGON_A2_vavguh: 3516 ID = Intrinsic::hexagon_A2_vavguh; break; 3517 3518 case Hexagon::BI__builtin_HEXAGON_A2_vavgh: 3519 ID = Intrinsic::hexagon_A2_vavgh; break; 3520 3521 case Hexagon::BI__builtin_HEXAGON_A2_vnavgh: 3522 ID = Intrinsic::hexagon_A2_vnavgh; break; 3523 3524 case Hexagon::BI__builtin_HEXAGON_A2_vavgw: 3525 ID = Intrinsic::hexagon_A2_vavgw; break; 3526 3527 case Hexagon::BI__builtin_HEXAGON_A2_vnavgw: 3528 ID = Intrinsic::hexagon_A2_vnavgw; break; 3529 3530 case Hexagon::BI__builtin_HEXAGON_A2_vavgwr: 3531 ID = Intrinsic::hexagon_A2_vavgwr; break; 3532 3533 case Hexagon::BI__builtin_HEXAGON_A2_vnavgwr: 3534 ID = Intrinsic::hexagon_A2_vnavgwr; break; 3535 3536 case Hexagon::BI__builtin_HEXAGON_A2_vavgwcr: 3537 ID = Intrinsic::hexagon_A2_vavgwcr; break; 3538 3539 case Hexagon::BI__builtin_HEXAGON_A2_vnavgwcr: 3540 ID = Intrinsic::hexagon_A2_vnavgwcr; break; 3541 3542 case Hexagon::BI__builtin_HEXAGON_A2_vavghcr: 3543 ID = Intrinsic::hexagon_A2_vavghcr; break; 3544 3545 case Hexagon::BI__builtin_HEXAGON_A2_vnavghcr: 3546 ID = Intrinsic::hexagon_A2_vnavghcr; break; 3547 3548 case Hexagon::BI__builtin_HEXAGON_A2_vavguw: 3549 ID = Intrinsic::hexagon_A2_vavguw; break; 3550 3551 case Hexagon::BI__builtin_HEXAGON_A2_vavguwr: 3552 ID = Intrinsic::hexagon_A2_vavguwr; break; 3553 3554 case Hexagon::BI__builtin_HEXAGON_A2_vavgubr: 3555 ID = Intrinsic::hexagon_A2_vavgubr; break; 3556 3557 case Hexagon::BI__builtin_HEXAGON_A2_vavguhr: 3558 ID = Intrinsic::hexagon_A2_vavguhr; break; 3559 3560 case Hexagon::BI__builtin_HEXAGON_A2_vavghr: 3561 ID = Intrinsic::hexagon_A2_vavghr; break; 3562 3563 case Hexagon::BI__builtin_HEXAGON_A2_vnavghr: 3564 ID = Intrinsic::hexagon_A2_vnavghr; break; 3565 3566 case Hexagon::BI__builtin_HEXAGON_A2_vminh: 3567 ID = Intrinsic::hexagon_A2_vminh; break; 3568 3569 case Hexagon::BI__builtin_HEXAGON_A2_vmaxh: 3570 ID = Intrinsic::hexagon_A2_vmaxh; break; 3571 3572 case Hexagon::BI__builtin_HEXAGON_A2_vminub: 3573 ID = Intrinsic::hexagon_A2_vminub; break; 3574 3575 case Hexagon::BI__builtin_HEXAGON_A2_vmaxub: 3576 ID = Intrinsic::hexagon_A2_vmaxub; break; 3577 3578 case Hexagon::BI__builtin_HEXAGON_A2_vminuh: 3579 ID = Intrinsic::hexagon_A2_vminuh; break; 3580 3581 case Hexagon::BI__builtin_HEXAGON_A2_vmaxuh: 3582 ID = Intrinsic::hexagon_A2_vmaxuh; break; 3583 3584 case Hexagon::BI__builtin_HEXAGON_A2_vminw: 3585 ID = Intrinsic::hexagon_A2_vminw; break; 3586 3587 case Hexagon::BI__builtin_HEXAGON_A2_vmaxw: 3588 ID = Intrinsic::hexagon_A2_vmaxw; break; 3589 3590 case Hexagon::BI__builtin_HEXAGON_A2_vminuw: 3591 ID = Intrinsic::hexagon_A2_vminuw; break; 3592 3593 case Hexagon::BI__builtin_HEXAGON_A2_vmaxuw: 3594 ID = Intrinsic::hexagon_A2_vmaxuw; break; 3595 3596 case Hexagon::BI__builtin_HEXAGON_S2_asr_r_r: 3597 ID = Intrinsic::hexagon_S2_asr_r_r; break; 3598 3599 case Hexagon::BI__builtin_HEXAGON_S2_asl_r_r: 3600 ID = Intrinsic::hexagon_S2_asl_r_r; break; 3601 3602 case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_r: 3603 ID = Intrinsic::hexagon_S2_lsr_r_r; break; 3604 3605 case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_r: 3606 ID = Intrinsic::hexagon_S2_lsl_r_r; break; 3607 3608 case Hexagon::BI__builtin_HEXAGON_S2_asr_r_p: 3609 ID = Intrinsic::hexagon_S2_asr_r_p; break; 3610 3611 case Hexagon::BI__builtin_HEXAGON_S2_asl_r_p: 3612 ID = Intrinsic::hexagon_S2_asl_r_p; break; 3613 3614 case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_p: 3615 ID = Intrinsic::hexagon_S2_lsr_r_p; break; 3616 3617 case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_p: 3618 ID = Intrinsic::hexagon_S2_lsl_r_p; break; 3619 3620 case Hexagon::BI__builtin_HEXAGON_S2_asr_r_r_acc: 3621 ID = Intrinsic::hexagon_S2_asr_r_r_acc; break; 3622 3623 case Hexagon::BI__builtin_HEXAGON_S2_asl_r_r_acc: 3624 ID = Intrinsic::hexagon_S2_asl_r_r_acc; break; 3625 3626 case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_r_acc: 3627 ID = Intrinsic::hexagon_S2_lsr_r_r_acc; break; 3628 3629 case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_r_acc: 3630 ID = Intrinsic::hexagon_S2_lsl_r_r_acc; break; 3631 3632 case Hexagon::BI__builtin_HEXAGON_S2_asr_r_p_acc: 3633 ID = Intrinsic::hexagon_S2_asr_r_p_acc; break; 3634 3635 case Hexagon::BI__builtin_HEXAGON_S2_asl_r_p_acc: 3636 ID = Intrinsic::hexagon_S2_asl_r_p_acc; break; 3637 3638 case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_p_acc: 3639 ID = Intrinsic::hexagon_S2_lsr_r_p_acc; break; 3640 3641 case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_p_acc: 3642 ID = Intrinsic::hexagon_S2_lsl_r_p_acc; break; 3643 3644 case Hexagon::BI__builtin_HEXAGON_S2_asr_r_r_nac: 3645 ID = Intrinsic::hexagon_S2_asr_r_r_nac; break; 3646 3647 case Hexagon::BI__builtin_HEXAGON_S2_asl_r_r_nac: 3648 ID = Intrinsic::hexagon_S2_asl_r_r_nac; break; 3649 3650 case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_r_nac: 3651 ID = Intrinsic::hexagon_S2_lsr_r_r_nac; break; 3652 3653 case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_r_nac: 3654 ID = Intrinsic::hexagon_S2_lsl_r_r_nac; break; 3655 3656 case Hexagon::BI__builtin_HEXAGON_S2_asr_r_p_nac: 3657 ID = Intrinsic::hexagon_S2_asr_r_p_nac; break; 3658 3659 case Hexagon::BI__builtin_HEXAGON_S2_asl_r_p_nac: 3660 ID = Intrinsic::hexagon_S2_asl_r_p_nac; break; 3661 3662 case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_p_nac: 3663 ID = Intrinsic::hexagon_S2_lsr_r_p_nac; break; 3664 3665 case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_p_nac: 3666 ID = Intrinsic::hexagon_S2_lsl_r_p_nac; break; 3667 3668 case Hexagon::BI__builtin_HEXAGON_S2_asr_r_r_and: 3669 ID = Intrinsic::hexagon_S2_asr_r_r_and; break; 3670 3671 case Hexagon::BI__builtin_HEXAGON_S2_asl_r_r_and: 3672 ID = Intrinsic::hexagon_S2_asl_r_r_and; break; 3673 3674 case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_r_and: 3675 ID = Intrinsic::hexagon_S2_lsr_r_r_and; break; 3676 3677 case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_r_and: 3678 ID = Intrinsic::hexagon_S2_lsl_r_r_and; break; 3679 3680 case Hexagon::BI__builtin_HEXAGON_S2_asr_r_r_or: 3681 ID = Intrinsic::hexagon_S2_asr_r_r_or; break; 3682 3683 case Hexagon::BI__builtin_HEXAGON_S2_asl_r_r_or: 3684 ID = Intrinsic::hexagon_S2_asl_r_r_or; break; 3685 3686 case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_r_or: 3687 ID = Intrinsic::hexagon_S2_lsr_r_r_or; break; 3688 3689 case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_r_or: 3690 ID = Intrinsic::hexagon_S2_lsl_r_r_or; break; 3691 3692 case Hexagon::BI__builtin_HEXAGON_S2_asr_r_p_and: 3693 ID = Intrinsic::hexagon_S2_asr_r_p_and; break; 3694 3695 case Hexagon::BI__builtin_HEXAGON_S2_asl_r_p_and: 3696 ID = Intrinsic::hexagon_S2_asl_r_p_and; break; 3697 3698 case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_p_and: 3699 ID = Intrinsic::hexagon_S2_lsr_r_p_and; break; 3700 3701 case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_p_and: 3702 ID = Intrinsic::hexagon_S2_lsl_r_p_and; break; 3703 3704 case Hexagon::BI__builtin_HEXAGON_S2_asr_r_p_or: 3705 ID = Intrinsic::hexagon_S2_asr_r_p_or; break; 3706 3707 case Hexagon::BI__builtin_HEXAGON_S2_asl_r_p_or: 3708 ID = Intrinsic::hexagon_S2_asl_r_p_or; break; 3709 3710 case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_p_or: 3711 ID = Intrinsic::hexagon_S2_lsr_r_p_or; break; 3712 3713 case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_p_or: 3714 ID = Intrinsic::hexagon_S2_lsl_r_p_or; break; 3715 3716 case Hexagon::BI__builtin_HEXAGON_S2_asr_r_r_sat: 3717 ID = Intrinsic::hexagon_S2_asr_r_r_sat; break; 3718 3719 case Hexagon::BI__builtin_HEXAGON_S2_asl_r_r_sat: 3720 ID = Intrinsic::hexagon_S2_asl_r_r_sat; break; 3721 3722 case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r: 3723 ID = Intrinsic::hexagon_S2_asr_i_r; break; 3724 3725 case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r: 3726 ID = Intrinsic::hexagon_S2_lsr_i_r; break; 3727 3728 case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r: 3729 ID = Intrinsic::hexagon_S2_asl_i_r; break; 3730 3731 case Hexagon::BI__builtin_HEXAGON_S2_asr_i_p: 3732 ID = Intrinsic::hexagon_S2_asr_i_p; break; 3733 3734 case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p: 3735 ID = Intrinsic::hexagon_S2_lsr_i_p; break; 3736 3737 case Hexagon::BI__builtin_HEXAGON_S2_asl_i_p: 3738 ID = Intrinsic::hexagon_S2_asl_i_p; break; 3739 3740 case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_acc: 3741 ID = Intrinsic::hexagon_S2_asr_i_r_acc; break; 3742 3743 case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_acc: 3744 ID = Intrinsic::hexagon_S2_lsr_i_r_acc; break; 3745 3746 case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_acc: 3747 ID = Intrinsic::hexagon_S2_asl_i_r_acc; break; 3748 3749 case Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_acc: 3750 ID = Intrinsic::hexagon_S2_asr_i_p_acc; break; 3751 3752 case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_acc: 3753 ID = Intrinsic::hexagon_S2_lsr_i_p_acc; break; 3754 3755 case Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_acc: 3756 ID = Intrinsic::hexagon_S2_asl_i_p_acc; break; 3757 3758 case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_nac: 3759 ID = Intrinsic::hexagon_S2_asr_i_r_nac; break; 3760 3761 case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_nac: 3762 ID = Intrinsic::hexagon_S2_lsr_i_r_nac; break; 3763 3764 case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_nac: 3765 ID = Intrinsic::hexagon_S2_asl_i_r_nac; break; 3766 3767 case Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_nac: 3768 ID = Intrinsic::hexagon_S2_asr_i_p_nac; break; 3769 3770 case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_nac: 3771 ID = Intrinsic::hexagon_S2_lsr_i_p_nac; break; 3772 3773 case Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_nac: 3774 ID = Intrinsic::hexagon_S2_asl_i_p_nac; break; 3775 3776 case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_xacc: 3777 ID = Intrinsic::hexagon_S2_lsr_i_r_xacc; break; 3778 3779 case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_xacc: 3780 ID = Intrinsic::hexagon_S2_asl_i_r_xacc; break; 3781 3782 case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_xacc: 3783 ID = Intrinsic::hexagon_S2_lsr_i_p_xacc; break; 3784 3785 case Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_xacc: 3786 ID = Intrinsic::hexagon_S2_asl_i_p_xacc; break; 3787 3788 case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_and: 3789 ID = Intrinsic::hexagon_S2_asr_i_r_and; break; 3790 3791 case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_and: 3792 ID = Intrinsic::hexagon_S2_lsr_i_r_and; break; 3793 3794 case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_and: 3795 ID = Intrinsic::hexagon_S2_asl_i_r_and; break; 3796 3797 case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_or: 3798 ID = Intrinsic::hexagon_S2_asr_i_r_or; break; 3799 3800 case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_or: 3801 ID = Intrinsic::hexagon_S2_lsr_i_r_or; break; 3802 3803 case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_or: 3804 ID = Intrinsic::hexagon_S2_asl_i_r_or; break; 3805 3806 case Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_and: 3807 ID = Intrinsic::hexagon_S2_asr_i_p_and; break; 3808 3809 case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_and: 3810 ID = Intrinsic::hexagon_S2_lsr_i_p_and; break; 3811 3812 case Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_and: 3813 ID = Intrinsic::hexagon_S2_asl_i_p_and; break; 3814 3815 case Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_or: 3816 ID = Intrinsic::hexagon_S2_asr_i_p_or; break; 3817 3818 case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_or: 3819 ID = Intrinsic::hexagon_S2_lsr_i_p_or; break; 3820 3821 case Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_or: 3822 ID = Intrinsic::hexagon_S2_asl_i_p_or; break; 3823 3824 case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_sat: 3825 ID = Intrinsic::hexagon_S2_asl_i_r_sat; break; 3826 3827 case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_rnd: 3828 ID = Intrinsic::hexagon_S2_asr_i_r_rnd; break; 3829 3830 case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax: 3831 ID = Intrinsic::hexagon_S2_asr_i_r_rnd_goodsyntax; break; 3832 3833 case Hexagon::BI__builtin_HEXAGON_S2_addasl_rrri: 3834 ID = Intrinsic::hexagon_S2_addasl_rrri; break; 3835 3836 case Hexagon::BI__builtin_HEXAGON_S2_valignib: 3837 ID = Intrinsic::hexagon_S2_valignib; break; 3838 3839 case Hexagon::BI__builtin_HEXAGON_S2_valignrb: 3840 ID = Intrinsic::hexagon_S2_valignrb; break; 3841 3842 case Hexagon::BI__builtin_HEXAGON_S2_vspliceib: 3843 ID = Intrinsic::hexagon_S2_vspliceib; break; 3844 3845 case Hexagon::BI__builtin_HEXAGON_S2_vsplicerb: 3846 ID = Intrinsic::hexagon_S2_vsplicerb; break; 3847 3848 case Hexagon::BI__builtin_HEXAGON_S2_vsplatrh: 3849 ID = Intrinsic::hexagon_S2_vsplatrh; break; 3850 3851 case Hexagon::BI__builtin_HEXAGON_S2_vsplatrb: 3852 ID = Intrinsic::hexagon_S2_vsplatrb; break; 3853 3854 case Hexagon::BI__builtin_HEXAGON_S2_insert: 3855 ID = Intrinsic::hexagon_S2_insert; break; 3856 3857 case Hexagon::BI__builtin_HEXAGON_S2_tableidxb_goodsyntax: 3858 ID = Intrinsic::hexagon_S2_tableidxb_goodsyntax; break; 3859 3860 case Hexagon::BI__builtin_HEXAGON_S2_tableidxh_goodsyntax: 3861 ID = Intrinsic::hexagon_S2_tableidxh_goodsyntax; break; 3862 3863 case Hexagon::BI__builtin_HEXAGON_S2_tableidxw_goodsyntax: 3864 ID = Intrinsic::hexagon_S2_tableidxw_goodsyntax; break; 3865 3866 case Hexagon::BI__builtin_HEXAGON_S2_tableidxd_goodsyntax: 3867 ID = Intrinsic::hexagon_S2_tableidxd_goodsyntax; break; 3868 3869 case Hexagon::BI__builtin_HEXAGON_S2_extractu: 3870 ID = Intrinsic::hexagon_S2_extractu; break; 3871 3872 case Hexagon::BI__builtin_HEXAGON_S2_insertp: 3873 ID = Intrinsic::hexagon_S2_insertp; break; 3874 3875 case Hexagon::BI__builtin_HEXAGON_S2_extractup: 3876 ID = Intrinsic::hexagon_S2_extractup; break; 3877 3878 case Hexagon::BI__builtin_HEXAGON_S2_insert_rp: 3879 ID = Intrinsic::hexagon_S2_insert_rp; break; 3880 3881 case Hexagon::BI__builtin_HEXAGON_S2_extractu_rp: 3882 ID = Intrinsic::hexagon_S2_extractu_rp; break; 3883 3884 case Hexagon::BI__builtin_HEXAGON_S2_insertp_rp: 3885 ID = Intrinsic::hexagon_S2_insertp_rp; break; 3886 3887 case Hexagon::BI__builtin_HEXAGON_S2_extractup_rp: 3888 ID = Intrinsic::hexagon_S2_extractup_rp; break; 3889 3890 case Hexagon::BI__builtin_HEXAGON_S2_tstbit_i: 3891 ID = Intrinsic::hexagon_S2_tstbit_i; break; 3892 3893 case Hexagon::BI__builtin_HEXAGON_S2_setbit_i: 3894 ID = Intrinsic::hexagon_S2_setbit_i; break; 3895 3896 case Hexagon::BI__builtin_HEXAGON_S2_togglebit_i: 3897 ID = Intrinsic::hexagon_S2_togglebit_i; break; 3898 3899 case Hexagon::BI__builtin_HEXAGON_S2_clrbit_i: 3900 ID = Intrinsic::hexagon_S2_clrbit_i; break; 3901 3902 case Hexagon::BI__builtin_HEXAGON_S2_tstbit_r: 3903 ID = Intrinsic::hexagon_S2_tstbit_r; break; 3904 3905 case Hexagon::BI__builtin_HEXAGON_S2_setbit_r: 3906 ID = Intrinsic::hexagon_S2_setbit_r; break; 3907 3908 case Hexagon::BI__builtin_HEXAGON_S2_togglebit_r: 3909 ID = Intrinsic::hexagon_S2_togglebit_r; break; 3910 3911 case Hexagon::BI__builtin_HEXAGON_S2_clrbit_r: 3912 ID = Intrinsic::hexagon_S2_clrbit_r; break; 3913 3914 case Hexagon::BI__builtin_HEXAGON_S2_asr_i_vh: 3915 ID = Intrinsic::hexagon_S2_asr_i_vh; break; 3916 3917 case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_vh: 3918 ID = Intrinsic::hexagon_S2_lsr_i_vh; break; 3919 3920 case Hexagon::BI__builtin_HEXAGON_S2_asl_i_vh: 3921 ID = Intrinsic::hexagon_S2_asl_i_vh; break; 3922 3923 case Hexagon::BI__builtin_HEXAGON_S2_asr_r_vh: 3924 ID = Intrinsic::hexagon_S2_asr_r_vh; break; 3925 3926 case Hexagon::BI__builtin_HEXAGON_S2_asl_r_vh: 3927 ID = Intrinsic::hexagon_S2_asl_r_vh; break; 3928 3929 case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_vh: 3930 ID = Intrinsic::hexagon_S2_lsr_r_vh; break; 3931 3932 case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_vh: 3933 ID = Intrinsic::hexagon_S2_lsl_r_vh; break; 3934 3935 case Hexagon::BI__builtin_HEXAGON_S2_asr_i_vw: 3936 ID = Intrinsic::hexagon_S2_asr_i_vw; break; 3937 3938 case Hexagon::BI__builtin_HEXAGON_S2_asr_i_svw_trun: 3939 ID = Intrinsic::hexagon_S2_asr_i_svw_trun; break; 3940 3941 case Hexagon::BI__builtin_HEXAGON_S2_asr_r_svw_trun: 3942 ID = Intrinsic::hexagon_S2_asr_r_svw_trun; break; 3943 3944 case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_vw: 3945 ID = Intrinsic::hexagon_S2_lsr_i_vw; break; 3946 3947 case Hexagon::BI__builtin_HEXAGON_S2_asl_i_vw: 3948 ID = Intrinsic::hexagon_S2_asl_i_vw; break; 3949 3950 case Hexagon::BI__builtin_HEXAGON_S2_asr_r_vw: 3951 ID = Intrinsic::hexagon_S2_asr_r_vw; break; 3952 3953 case Hexagon::BI__builtin_HEXAGON_S2_asl_r_vw: 3954 ID = Intrinsic::hexagon_S2_asl_r_vw; break; 3955 3956 case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_vw: 3957 ID = Intrinsic::hexagon_S2_lsr_r_vw; break; 3958 3959 case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_vw: 3960 ID = Intrinsic::hexagon_S2_lsl_r_vw; break; 3961 3962 case Hexagon::BI__builtin_HEXAGON_S2_vrndpackwh: 3963 ID = Intrinsic::hexagon_S2_vrndpackwh; break; 3964 3965 case Hexagon::BI__builtin_HEXAGON_S2_vrndpackwhs: 3966 ID = Intrinsic::hexagon_S2_vrndpackwhs; break; 3967 3968 case Hexagon::BI__builtin_HEXAGON_S2_vsxtbh: 3969 ID = Intrinsic::hexagon_S2_vsxtbh; break; 3970 3971 case Hexagon::BI__builtin_HEXAGON_S2_vzxtbh: 3972 ID = Intrinsic::hexagon_S2_vzxtbh; break; 3973 3974 case Hexagon::BI__builtin_HEXAGON_S2_vsathub: 3975 ID = Intrinsic::hexagon_S2_vsathub; break; 3976 3977 case Hexagon::BI__builtin_HEXAGON_S2_svsathub: 3978 ID = Intrinsic::hexagon_S2_svsathub; break; 3979 3980 case Hexagon::BI__builtin_HEXAGON_S2_svsathb: 3981 ID = Intrinsic::hexagon_S2_svsathb; break; 3982 3983 case Hexagon::BI__builtin_HEXAGON_S2_vsathb: 3984 ID = Intrinsic::hexagon_S2_vsathb; break; 3985 3986 case Hexagon::BI__builtin_HEXAGON_S2_vtrunohb: 3987 ID = Intrinsic::hexagon_S2_vtrunohb; break; 3988 3989 case Hexagon::BI__builtin_HEXAGON_S2_vtrunewh: 3990 ID = Intrinsic::hexagon_S2_vtrunewh; break; 3991 3992 case Hexagon::BI__builtin_HEXAGON_S2_vtrunowh: 3993 ID = Intrinsic::hexagon_S2_vtrunowh; break; 3994 3995 case Hexagon::BI__builtin_HEXAGON_S2_vtrunehb: 3996 ID = Intrinsic::hexagon_S2_vtrunehb; break; 3997 3998 case Hexagon::BI__builtin_HEXAGON_S2_vsxthw: 3999 ID = Intrinsic::hexagon_S2_vsxthw; break; 4000 4001 case Hexagon::BI__builtin_HEXAGON_S2_vzxthw: 4002 ID = Intrinsic::hexagon_S2_vzxthw; break; 4003 4004 case Hexagon::BI__builtin_HEXAGON_S2_vsatwh: 4005 ID = Intrinsic::hexagon_S2_vsatwh; break; 4006 4007 case Hexagon::BI__builtin_HEXAGON_S2_vsatwuh: 4008 ID = Intrinsic::hexagon_S2_vsatwuh; break; 4009 4010 case Hexagon::BI__builtin_HEXAGON_S2_packhl: 4011 ID = Intrinsic::hexagon_S2_packhl; break; 4012 4013 case Hexagon::BI__builtin_HEXAGON_A2_swiz: 4014 ID = Intrinsic::hexagon_A2_swiz; break; 4015 4016 case Hexagon::BI__builtin_HEXAGON_S2_vsathub_nopack: 4017 ID = Intrinsic::hexagon_S2_vsathub_nopack; break; 4018 4019 case Hexagon::BI__builtin_HEXAGON_S2_vsathb_nopack: 4020 ID = Intrinsic::hexagon_S2_vsathb_nopack; break; 4021 4022 case Hexagon::BI__builtin_HEXAGON_S2_vsatwh_nopack: 4023 ID = Intrinsic::hexagon_S2_vsatwh_nopack; break; 4024 4025 case Hexagon::BI__builtin_HEXAGON_S2_vsatwuh_nopack: 4026 ID = Intrinsic::hexagon_S2_vsatwuh_nopack; break; 4027 4028 case Hexagon::BI__builtin_HEXAGON_S2_shuffob: 4029 ID = Intrinsic::hexagon_S2_shuffob; break; 4030 4031 case Hexagon::BI__builtin_HEXAGON_S2_shuffeb: 4032 ID = Intrinsic::hexagon_S2_shuffeb; break; 4033 4034 case Hexagon::BI__builtin_HEXAGON_S2_shuffoh: 4035 ID = Intrinsic::hexagon_S2_shuffoh; break; 4036 4037 case Hexagon::BI__builtin_HEXAGON_S2_shuffeh: 4038 ID = Intrinsic::hexagon_S2_shuffeh; break; 4039 4040 case Hexagon::BI__builtin_HEXAGON_S2_parityp: 4041 ID = Intrinsic::hexagon_S2_parityp; break; 4042 4043 case Hexagon::BI__builtin_HEXAGON_S2_lfsp: 4044 ID = Intrinsic::hexagon_S2_lfsp; break; 4045 4046 case Hexagon::BI__builtin_HEXAGON_S2_clbnorm: 4047 ID = Intrinsic::hexagon_S2_clbnorm; break; 4048 4049 case Hexagon::BI__builtin_HEXAGON_S2_clb: 4050 ID = Intrinsic::hexagon_S2_clb; break; 4051 4052 case Hexagon::BI__builtin_HEXAGON_S2_cl0: 4053 ID = Intrinsic::hexagon_S2_cl0; break; 4054 4055 case Hexagon::BI__builtin_HEXAGON_S2_cl1: 4056 ID = Intrinsic::hexagon_S2_cl1; break; 4057 4058 case Hexagon::BI__builtin_HEXAGON_S2_clbp: 4059 ID = Intrinsic::hexagon_S2_clbp; break; 4060 4061 case Hexagon::BI__builtin_HEXAGON_S2_cl0p: 4062 ID = Intrinsic::hexagon_S2_cl0p; break; 4063 4064 case Hexagon::BI__builtin_HEXAGON_S2_cl1p: 4065 ID = Intrinsic::hexagon_S2_cl1p; break; 4066 4067 case Hexagon::BI__builtin_HEXAGON_S2_brev: 4068 ID = Intrinsic::hexagon_S2_brev; break; 4069 4070 case Hexagon::BI__builtin_HEXAGON_S2_ct0: 4071 ID = Intrinsic::hexagon_S2_ct0; break; 4072 4073 case Hexagon::BI__builtin_HEXAGON_S2_ct1: 4074 ID = Intrinsic::hexagon_S2_ct1; break; 4075 4076 case Hexagon::BI__builtin_HEXAGON_S2_interleave: 4077 ID = Intrinsic::hexagon_S2_interleave; break; 4078 4079 case Hexagon::BI__builtin_HEXAGON_S2_deinterleave: 4080 ID = Intrinsic::hexagon_S2_deinterleave; break; 4081 4082 case Hexagon::BI__builtin_SI_to_SXTHI_asrh: 4083 ID = Intrinsic::hexagon_SI_to_SXTHI_asrh; break; 4084 4085 case Hexagon::BI__builtin_HEXAGON_A4_orn: 4086 ID = Intrinsic::hexagon_A4_orn; break; 4087 4088 case Hexagon::BI__builtin_HEXAGON_A4_andn: 4089 ID = Intrinsic::hexagon_A4_andn; break; 4090 4091 case Hexagon::BI__builtin_HEXAGON_A4_ornp: 4092 ID = Intrinsic::hexagon_A4_ornp; break; 4093 4094 case Hexagon::BI__builtin_HEXAGON_A4_andnp: 4095 ID = Intrinsic::hexagon_A4_andnp; break; 4096 4097 case Hexagon::BI__builtin_HEXAGON_A4_combineir: 4098 ID = Intrinsic::hexagon_A4_combineir; break; 4099 4100 case Hexagon::BI__builtin_HEXAGON_A4_combineri: 4101 ID = Intrinsic::hexagon_A4_combineri; break; 4102 4103 case Hexagon::BI__builtin_HEXAGON_C4_cmpneqi: 4104 ID = Intrinsic::hexagon_C4_cmpneqi; break; 4105 4106 case Hexagon::BI__builtin_HEXAGON_C4_cmpneq: 4107 ID = Intrinsic::hexagon_C4_cmpneq; break; 4108 4109 case Hexagon::BI__builtin_HEXAGON_C4_cmpltei: 4110 ID = Intrinsic::hexagon_C4_cmpltei; break; 4111 4112 case Hexagon::BI__builtin_HEXAGON_C4_cmplte: 4113 ID = Intrinsic::hexagon_C4_cmplte; break; 4114 4115 case Hexagon::BI__builtin_HEXAGON_C4_cmplteui: 4116 ID = Intrinsic::hexagon_C4_cmplteui; break; 4117 4118 case Hexagon::BI__builtin_HEXAGON_C4_cmplteu: 4119 ID = Intrinsic::hexagon_C4_cmplteu; break; 4120 4121 case Hexagon::BI__builtin_HEXAGON_A4_rcmpneq: 4122 ID = Intrinsic::hexagon_A4_rcmpneq; break; 4123 4124 case Hexagon::BI__builtin_HEXAGON_A4_rcmpneqi: 4125 ID = Intrinsic::hexagon_A4_rcmpneqi; break; 4126 4127 case Hexagon::BI__builtin_HEXAGON_A4_rcmpeq: 4128 ID = Intrinsic::hexagon_A4_rcmpeq; break; 4129 4130 case Hexagon::BI__builtin_HEXAGON_A4_rcmpeqi: 4131 ID = Intrinsic::hexagon_A4_rcmpeqi; break; 4132 4133 case Hexagon::BI__builtin_HEXAGON_C4_fastcorner9: 4134 ID = Intrinsic::hexagon_C4_fastcorner9; break; 4135 4136 case Hexagon::BI__builtin_HEXAGON_C4_fastcorner9_not: 4137 ID = Intrinsic::hexagon_C4_fastcorner9_not; break; 4138 4139 case Hexagon::BI__builtin_HEXAGON_C4_and_andn: 4140 ID = Intrinsic::hexagon_C4_and_andn; break; 4141 4142 case Hexagon::BI__builtin_HEXAGON_C4_and_and: 4143 ID = Intrinsic::hexagon_C4_and_and; break; 4144 4145 case Hexagon::BI__builtin_HEXAGON_C4_and_orn: 4146 ID = Intrinsic::hexagon_C4_and_orn; break; 4147 4148 case Hexagon::BI__builtin_HEXAGON_C4_and_or: 4149 ID = Intrinsic::hexagon_C4_and_or; break; 4150 4151 case Hexagon::BI__builtin_HEXAGON_C4_or_andn: 4152 ID = Intrinsic::hexagon_C4_or_andn; break; 4153 4154 case Hexagon::BI__builtin_HEXAGON_C4_or_and: 4155 ID = Intrinsic::hexagon_C4_or_and; break; 4156 4157 case Hexagon::BI__builtin_HEXAGON_C4_or_orn: 4158 ID = Intrinsic::hexagon_C4_or_orn; break; 4159 4160 case Hexagon::BI__builtin_HEXAGON_C4_or_or: 4161 ID = Intrinsic::hexagon_C4_or_or; break; 4162 4163 case Hexagon::BI__builtin_HEXAGON_S4_addaddi: 4164 ID = Intrinsic::hexagon_S4_addaddi; break; 4165 4166 case Hexagon::BI__builtin_HEXAGON_S4_subaddi: 4167 ID = Intrinsic::hexagon_S4_subaddi; break; 4168 4169 case Hexagon::BI__builtin_HEXAGON_M4_xor_xacc: 4170 ID = Intrinsic::hexagon_M4_xor_xacc; break; 4171 4172 case Hexagon::BI__builtin_HEXAGON_M4_and_and: 4173 ID = Intrinsic::hexagon_M4_and_and; break; 4174 4175 case Hexagon::BI__builtin_HEXAGON_M4_and_or: 4176 ID = Intrinsic::hexagon_M4_and_or; break; 4177 4178 case Hexagon::BI__builtin_HEXAGON_M4_and_xor: 4179 ID = Intrinsic::hexagon_M4_and_xor; break; 4180 4181 case Hexagon::BI__builtin_HEXAGON_M4_and_andn: 4182 ID = Intrinsic::hexagon_M4_and_andn; break; 4183 4184 case Hexagon::BI__builtin_HEXAGON_M4_xor_and: 4185 ID = Intrinsic::hexagon_M4_xor_and; break; 4186 4187 case Hexagon::BI__builtin_HEXAGON_M4_xor_or: 4188 ID = Intrinsic::hexagon_M4_xor_or; break; 4189 4190 case Hexagon::BI__builtin_HEXAGON_M4_xor_andn: 4191 ID = Intrinsic::hexagon_M4_xor_andn; break; 4192 4193 case Hexagon::BI__builtin_HEXAGON_M4_or_and: 4194 ID = Intrinsic::hexagon_M4_or_and; break; 4195 4196 case Hexagon::BI__builtin_HEXAGON_M4_or_or: 4197 ID = Intrinsic::hexagon_M4_or_or; break; 4198 4199 case Hexagon::BI__builtin_HEXAGON_M4_or_xor: 4200 ID = Intrinsic::hexagon_M4_or_xor; break; 4201 4202 case Hexagon::BI__builtin_HEXAGON_M4_or_andn: 4203 ID = Intrinsic::hexagon_M4_or_andn; break; 4204 4205 case Hexagon::BI__builtin_HEXAGON_S4_or_andix: 4206 ID = Intrinsic::hexagon_S4_or_andix; break; 4207 4208 case Hexagon::BI__builtin_HEXAGON_S4_or_andi: 4209 ID = Intrinsic::hexagon_S4_or_andi; break; 4210 4211 case Hexagon::BI__builtin_HEXAGON_S4_or_ori: 4212 ID = Intrinsic::hexagon_S4_or_ori; break; 4213 4214 case Hexagon::BI__builtin_HEXAGON_A4_modwrapu: 4215 ID = Intrinsic::hexagon_A4_modwrapu; break; 4216 4217 case Hexagon::BI__builtin_HEXAGON_A4_cround_rr: 4218 ID = Intrinsic::hexagon_A4_cround_rr; break; 4219 4220 case Hexagon::BI__builtin_HEXAGON_A4_round_ri: 4221 ID = Intrinsic::hexagon_A4_round_ri; break; 4222 4223 case Hexagon::BI__builtin_HEXAGON_A4_round_rr: 4224 ID = Intrinsic::hexagon_A4_round_rr; break; 4225 4226 case Hexagon::BI__builtin_HEXAGON_A4_round_ri_sat: 4227 ID = Intrinsic::hexagon_A4_round_ri_sat; break; 4228 4229 case Hexagon::BI__builtin_HEXAGON_A4_round_rr_sat: 4230 ID = Intrinsic::hexagon_A4_round_rr_sat; break; 4231 4232 } 4233 4234 llvm::Function *F = CGM.getIntrinsic(ID); 4235 return Builder.CreateCall(F, Ops, ""); 4236 } 4237 4238 Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID, 4239 const CallExpr *E) { 4240 SmallVector<Value*, 4> Ops; 4241 4242 for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) 4243 Ops.push_back(EmitScalarExpr(E->getArg(i))); 4244 4245 Intrinsic::ID ID = Intrinsic::not_intrinsic; 4246 4247 switch (BuiltinID) { 4248 default: return 0; 4249 4250 // vec_ld, vec_lvsl, vec_lvsr 4251 case PPC::BI__builtin_altivec_lvx: 4252 case PPC::BI__builtin_altivec_lvxl: 4253 case PPC::BI__builtin_altivec_lvebx: 4254 case PPC::BI__builtin_altivec_lvehx: 4255 case PPC::BI__builtin_altivec_lvewx: 4256 case PPC::BI__builtin_altivec_lvsl: 4257 case PPC::BI__builtin_altivec_lvsr: 4258 { 4259 Ops[1] = Builder.CreateBitCast(Ops[1], Int8PtrTy); 4260 4261 Ops[0] = Builder.CreateGEP(Ops[1], Ops[0]); 4262 Ops.pop_back(); 4263 4264 switch (BuiltinID) { 4265 default: llvm_unreachable("Unsupported ld/lvsl/lvsr intrinsic!"); 4266 case PPC::BI__builtin_altivec_lvx: 4267 ID = Intrinsic::ppc_altivec_lvx; 4268 break; 4269 case PPC::BI__builtin_altivec_lvxl: 4270 ID = Intrinsic::ppc_altivec_lvxl; 4271 break; 4272 case PPC::BI__builtin_altivec_lvebx: 4273 ID = Intrinsic::ppc_altivec_lvebx; 4274 break; 4275 case PPC::BI__builtin_altivec_lvehx: 4276 ID = Intrinsic::ppc_altivec_lvehx; 4277 break; 4278 case PPC::BI__builtin_altivec_lvewx: 4279 ID = Intrinsic::ppc_altivec_lvewx; 4280 break; 4281 case PPC::BI__builtin_altivec_lvsl: 4282 ID = Intrinsic::ppc_altivec_lvsl; 4283 break; 4284 case PPC::BI__builtin_altivec_lvsr: 4285 ID = Intrinsic::ppc_altivec_lvsr; 4286 break; 4287 } 4288 llvm::Function *F = CGM.getIntrinsic(ID); 4289 return Builder.CreateCall(F, Ops, ""); 4290 } 4291 4292 // vec_st 4293 case PPC::BI__builtin_altivec_stvx: 4294 case PPC::BI__builtin_altivec_stvxl: 4295 case PPC::BI__builtin_altivec_stvebx: 4296 case PPC::BI__builtin_altivec_stvehx: 4297 case PPC::BI__builtin_altivec_stvewx: 4298 { 4299 Ops[2] = Builder.CreateBitCast(Ops[2], Int8PtrTy); 4300 Ops[1] = Builder.CreateGEP(Ops[2], Ops[1]); 4301 Ops.pop_back(); 4302 4303 switch (BuiltinID) { 4304 default: llvm_unreachable("Unsupported st intrinsic!"); 4305 case PPC::BI__builtin_altivec_stvx: 4306 ID = Intrinsic::ppc_altivec_stvx; 4307 break; 4308 case PPC::BI__builtin_altivec_stvxl: 4309 ID = Intrinsic::ppc_altivec_stvxl; 4310 break; 4311 case PPC::BI__builtin_altivec_stvebx: 4312 ID = Intrinsic::ppc_altivec_stvebx; 4313 break; 4314 case PPC::BI__builtin_altivec_stvehx: 4315 ID = Intrinsic::ppc_altivec_stvehx; 4316 break; 4317 case PPC::BI__builtin_altivec_stvewx: 4318 ID = Intrinsic::ppc_altivec_stvewx; 4319 break; 4320 } 4321 llvm::Function *F = CGM.getIntrinsic(ID); 4322 return Builder.CreateCall(F, Ops, ""); 4323 } 4324 } 4325 } 4326