1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabled(Features, "sse2", true); 112 113 using namespace llvm::X86; 114 115 SmallVector<StringRef, 16> CPUFeatures; 116 getFeaturesForCPU(CPU, CPUFeatures); 117 for (auto &F : CPUFeatures) 118 setFeatureEnabled(Features, F, true); 119 120 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 121 return false; 122 123 // Can't do this earlier because we need to be able to explicitly enable 124 // or disable these features and the things that they depend upon. 125 126 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 127 auto I = Features.find("sse4.2"); 128 if (I != Features.end() && I->getValue() && 129 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 130 Features["popcnt"] = true; 131 132 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 133 // then enable MMX. 134 I = Features.find("sse"); 135 if (I != Features.end() && I->getValue() && 136 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 137 Features["mmx"] = true; 138 139 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 140 I = Features.find("avx"); 141 if (I != Features.end() && I->getValue() && 142 llvm::find(FeaturesVec, "-xsave") == FeaturesVec.end()) 143 Features["xsave"] = true; 144 145 return true; 146 } 147 148 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 149 StringRef Name, bool Enabled) const { 150 if (Name == "sse4") { 151 // We can get here via the __target__ attribute since that's not controlled 152 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 153 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 154 // disabled. 155 if (Enabled) 156 Name = "sse4.2"; 157 else 158 Name = "sse4.1"; 159 } 160 161 Features[Name] = Enabled; 162 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 163 } 164 165 /// handleTargetFeatures - Perform initialization based on the user 166 /// configured set of features. 167 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 168 DiagnosticsEngine &Diags) { 169 for (const auto &Feature : Features) { 170 if (Feature[0] != '+') 171 continue; 172 173 if (Feature == "+aes") { 174 HasAES = true; 175 } else if (Feature == "+vaes") { 176 HasVAES = true; 177 } else if (Feature == "+pclmul") { 178 HasPCLMUL = true; 179 } else if (Feature == "+vpclmulqdq") { 180 HasVPCLMULQDQ = true; 181 } else if (Feature == "+lzcnt") { 182 HasLZCNT = true; 183 } else if (Feature == "+rdrnd") { 184 HasRDRND = true; 185 } else if (Feature == "+fsgsbase") { 186 HasFSGSBASE = true; 187 } else if (Feature == "+bmi") { 188 HasBMI = true; 189 } else if (Feature == "+bmi2") { 190 HasBMI2 = true; 191 } else if (Feature == "+popcnt") { 192 HasPOPCNT = true; 193 } else if (Feature == "+rtm") { 194 HasRTM = true; 195 } else if (Feature == "+prfchw") { 196 HasPRFCHW = true; 197 } else if (Feature == "+rdseed") { 198 HasRDSEED = true; 199 } else if (Feature == "+adx") { 200 HasADX = true; 201 } else if (Feature == "+tbm") { 202 HasTBM = true; 203 } else if (Feature == "+lwp") { 204 HasLWP = true; 205 } else if (Feature == "+fma") { 206 HasFMA = true; 207 } else if (Feature == "+f16c") { 208 HasF16C = true; 209 } else if (Feature == "+gfni") { 210 HasGFNI = true; 211 } else if (Feature == "+avx512cd") { 212 HasAVX512CD = true; 213 } else if (Feature == "+avx512vpopcntdq") { 214 HasAVX512VPOPCNTDQ = true; 215 } else if (Feature == "+avx512vnni") { 216 HasAVX512VNNI = true; 217 } else if (Feature == "+avx512bf16") { 218 HasAVX512BF16 = true; 219 } else if (Feature == "+avx512er") { 220 HasAVX512ER = true; 221 } else if (Feature == "+avx512pf") { 222 HasAVX512PF = true; 223 } else if (Feature == "+avx512dq") { 224 HasAVX512DQ = true; 225 } else if (Feature == "+avx512bitalg") { 226 HasAVX512BITALG = true; 227 } else if (Feature == "+avx512bw") { 228 HasAVX512BW = true; 229 } else if (Feature == "+avx512vl") { 230 HasAVX512VL = true; 231 } else if (Feature == "+avx512vbmi") { 232 HasAVX512VBMI = true; 233 } else if (Feature == "+avx512vbmi2") { 234 HasAVX512VBMI2 = true; 235 } else if (Feature == "+avx512ifma") { 236 HasAVX512IFMA = true; 237 } else if (Feature == "+avx512vp2intersect") { 238 HasAVX512VP2INTERSECT = true; 239 } else if (Feature == "+sha") { 240 HasSHA = true; 241 } else if (Feature == "+shstk") { 242 HasSHSTK = true; 243 } else if (Feature == "+movbe") { 244 HasMOVBE = true; 245 } else if (Feature == "+sgx") { 246 HasSGX = true; 247 } else if (Feature == "+cx8") { 248 HasCX8 = true; 249 } else if (Feature == "+cx16") { 250 HasCX16 = true; 251 } else if (Feature == "+fxsr") { 252 HasFXSR = true; 253 } else if (Feature == "+xsave") { 254 HasXSAVE = true; 255 } else if (Feature == "+xsaveopt") { 256 HasXSAVEOPT = true; 257 } else if (Feature == "+xsavec") { 258 HasXSAVEC = true; 259 } else if (Feature == "+xsaves") { 260 HasXSAVES = true; 261 } else if (Feature == "+mwaitx") { 262 HasMWAITX = true; 263 } else if (Feature == "+pku") { 264 HasPKU = true; 265 } else if (Feature == "+clflushopt") { 266 HasCLFLUSHOPT = true; 267 } else if (Feature == "+clwb") { 268 HasCLWB = true; 269 } else if (Feature == "+wbnoinvd") { 270 HasWBNOINVD = true; 271 } else if (Feature == "+prefetchwt1") { 272 HasPREFETCHWT1 = true; 273 } else if (Feature == "+clzero") { 274 HasCLZERO = true; 275 } else if (Feature == "+cldemote") { 276 HasCLDEMOTE = true; 277 } else if (Feature == "+rdpid") { 278 HasRDPID = true; 279 } else if (Feature == "+kl") { 280 HasKL = true; 281 } else if (Feature == "+widekl") { 282 HasWIDEKL = true; 283 } else if (Feature == "+retpoline-external-thunk") { 284 HasRetpolineExternalThunk = true; 285 } else if (Feature == "+sahf") { 286 HasLAHFSAHF = true; 287 } else if (Feature == "+waitpkg") { 288 HasWAITPKG = true; 289 } else if (Feature == "+movdiri") { 290 HasMOVDIRI = true; 291 } else if (Feature == "+movdir64b") { 292 HasMOVDIR64B = true; 293 } else if (Feature == "+pconfig") { 294 HasPCONFIG = true; 295 } else if (Feature == "+ptwrite") { 296 HasPTWRITE = true; 297 } else if (Feature == "+invpcid") { 298 HasINVPCID = true; 299 } else if (Feature == "+enqcmd") { 300 HasENQCMD = true; 301 } else if (Feature == "+hreset") { 302 HasHRESET = true; 303 } else if (Feature == "+amx-bf16") { 304 HasAMXBF16 = true; 305 } else if (Feature == "+amx-int8") { 306 HasAMXINT8 = true; 307 } else if (Feature == "+amx-tile") { 308 HasAMXTILE = true; 309 } else if (Feature == "+serialize") { 310 HasSERIALIZE = true; 311 } else if (Feature == "+tsxldtrk") { 312 HasTSXLDTRK = true; 313 } else if (Feature == "+uintr") { 314 HasUINTR = true; 315 } 316 317 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 318 .Case("+avx512f", AVX512F) 319 .Case("+avx2", AVX2) 320 .Case("+avx", AVX) 321 .Case("+sse4.2", SSE42) 322 .Case("+sse4.1", SSE41) 323 .Case("+ssse3", SSSE3) 324 .Case("+sse3", SSE3) 325 .Case("+sse2", SSE2) 326 .Case("+sse", SSE1) 327 .Default(NoSSE); 328 SSELevel = std::max(SSELevel, Level); 329 330 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 331 .Case("+3dnowa", AMD3DNowAthlon) 332 .Case("+3dnow", AMD3DNow) 333 .Case("+mmx", MMX) 334 .Default(NoMMX3DNow); 335 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 336 337 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 338 .Case("+xop", XOP) 339 .Case("+fma4", FMA4) 340 .Case("+sse4a", SSE4A) 341 .Default(NoXOP); 342 XOPLevel = std::max(XOPLevel, XLevel); 343 } 344 345 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 346 // matches the selected sse level. 347 if ((FPMath == FP_SSE && SSELevel < SSE1) || 348 (FPMath == FP_387 && SSELevel >= SSE1)) { 349 Diags.Report(diag::err_target_unsupported_fpmath) 350 << (FPMath == FP_SSE ? "sse" : "387"); 351 return false; 352 } 353 354 SimdDefaultAlign = 355 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 356 return true; 357 } 358 359 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 360 /// definitions for this particular subtarget. 361 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 362 MacroBuilder &Builder) const { 363 // Inline assembly supports X86 flag outputs. 364 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 365 366 std::string CodeModel = getTargetOpts().CodeModel; 367 if (CodeModel == "default") 368 CodeModel = "small"; 369 Builder.defineMacro("__code_model_" + CodeModel + "__"); 370 371 // Target identification. 372 if (getTriple().getArch() == llvm::Triple::x86_64) { 373 Builder.defineMacro("__amd64__"); 374 Builder.defineMacro("__amd64"); 375 Builder.defineMacro("__x86_64"); 376 Builder.defineMacro("__x86_64__"); 377 if (getTriple().getArchName() == "x86_64h") { 378 Builder.defineMacro("__x86_64h"); 379 Builder.defineMacro("__x86_64h__"); 380 } 381 } else { 382 DefineStd(Builder, "i386", Opts); 383 } 384 385 Builder.defineMacro("__SEG_GS"); 386 Builder.defineMacro("__SEG_FS"); 387 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 388 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 389 390 // Subtarget options. 391 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 392 // truly should be based on -mtune options. 393 using namespace llvm::X86; 394 switch (CPU) { 395 case CK_None: 396 break; 397 case CK_i386: 398 // The rest are coming from the i386 define above. 399 Builder.defineMacro("__tune_i386__"); 400 break; 401 case CK_i486: 402 case CK_WinChipC6: 403 case CK_WinChip2: 404 case CK_C3: 405 defineCPUMacros(Builder, "i486"); 406 break; 407 case CK_PentiumMMX: 408 Builder.defineMacro("__pentium_mmx__"); 409 Builder.defineMacro("__tune_pentium_mmx__"); 410 LLVM_FALLTHROUGH; 411 case CK_i586: 412 case CK_Pentium: 413 defineCPUMacros(Builder, "i586"); 414 defineCPUMacros(Builder, "pentium"); 415 break; 416 case CK_Pentium3: 417 case CK_PentiumM: 418 Builder.defineMacro("__tune_pentium3__"); 419 LLVM_FALLTHROUGH; 420 case CK_Pentium2: 421 case CK_C3_2: 422 Builder.defineMacro("__tune_pentium2__"); 423 LLVM_FALLTHROUGH; 424 case CK_PentiumPro: 425 case CK_i686: 426 defineCPUMacros(Builder, "i686"); 427 defineCPUMacros(Builder, "pentiumpro"); 428 break; 429 case CK_Pentium4: 430 defineCPUMacros(Builder, "pentium4"); 431 break; 432 case CK_Yonah: 433 case CK_Prescott: 434 case CK_Nocona: 435 defineCPUMacros(Builder, "nocona"); 436 break; 437 case CK_Core2: 438 case CK_Penryn: 439 defineCPUMacros(Builder, "core2"); 440 break; 441 case CK_Bonnell: 442 defineCPUMacros(Builder, "atom"); 443 break; 444 case CK_Silvermont: 445 defineCPUMacros(Builder, "slm"); 446 break; 447 case CK_Goldmont: 448 defineCPUMacros(Builder, "goldmont"); 449 break; 450 case CK_GoldmontPlus: 451 defineCPUMacros(Builder, "goldmont_plus"); 452 break; 453 case CK_Tremont: 454 defineCPUMacros(Builder, "tremont"); 455 break; 456 case CK_Nehalem: 457 case CK_Westmere: 458 case CK_SandyBridge: 459 case CK_IvyBridge: 460 case CK_Haswell: 461 case CK_Broadwell: 462 case CK_SkylakeClient: 463 case CK_SkylakeServer: 464 case CK_Cascadelake: 465 case CK_Cooperlake: 466 case CK_Cannonlake: 467 case CK_IcelakeClient: 468 case CK_IcelakeServer: 469 case CK_Tigerlake: 470 case CK_SapphireRapids: 471 // FIXME: Historically, we defined this legacy name, it would be nice to 472 // remove it at some point. We've never exposed fine-grained names for 473 // recent primary x86 CPUs, and we should keep it that way. 474 defineCPUMacros(Builder, "corei7"); 475 break; 476 case CK_KNL: 477 defineCPUMacros(Builder, "knl"); 478 break; 479 case CK_KNM: 480 break; 481 case CK_Lakemont: 482 defineCPUMacros(Builder, "i586", /*Tuning*/false); 483 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 484 Builder.defineMacro("__tune_lakemont__"); 485 break; 486 case CK_K6_2: 487 Builder.defineMacro("__k6_2__"); 488 Builder.defineMacro("__tune_k6_2__"); 489 LLVM_FALLTHROUGH; 490 case CK_K6_3: 491 if (CPU != CK_K6_2) { // In case of fallthrough 492 // FIXME: GCC may be enabling these in cases where some other k6 493 // architecture is specified but -m3dnow is explicitly provided. The 494 // exact semantics need to be determined and emulated here. 495 Builder.defineMacro("__k6_3__"); 496 Builder.defineMacro("__tune_k6_3__"); 497 } 498 LLVM_FALLTHROUGH; 499 case CK_K6: 500 defineCPUMacros(Builder, "k6"); 501 break; 502 case CK_Athlon: 503 case CK_AthlonXP: 504 defineCPUMacros(Builder, "athlon"); 505 if (SSELevel != NoSSE) { 506 Builder.defineMacro("__athlon_sse__"); 507 Builder.defineMacro("__tune_athlon_sse__"); 508 } 509 break; 510 case CK_K8: 511 case CK_K8SSE3: 512 case CK_x86_64: 513 case CK_x86_64_v2: 514 case CK_x86_64_v3: 515 case CK_x86_64_v4: 516 defineCPUMacros(Builder, "k8"); 517 break; 518 case CK_AMDFAM10: 519 defineCPUMacros(Builder, "amdfam10"); 520 break; 521 case CK_BTVER1: 522 defineCPUMacros(Builder, "btver1"); 523 break; 524 case CK_BTVER2: 525 defineCPUMacros(Builder, "btver2"); 526 break; 527 case CK_BDVER1: 528 defineCPUMacros(Builder, "bdver1"); 529 break; 530 case CK_BDVER2: 531 defineCPUMacros(Builder, "bdver2"); 532 break; 533 case CK_BDVER3: 534 defineCPUMacros(Builder, "bdver3"); 535 break; 536 case CK_BDVER4: 537 defineCPUMacros(Builder, "bdver4"); 538 break; 539 case CK_ZNVER1: 540 defineCPUMacros(Builder, "znver1"); 541 break; 542 case CK_ZNVER2: 543 defineCPUMacros(Builder, "znver2"); 544 break; 545 case CK_Geode: 546 defineCPUMacros(Builder, "geode"); 547 break; 548 } 549 550 // Target properties. 551 Builder.defineMacro("__REGISTER_PREFIX__", ""); 552 553 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 554 // functions in glibc header files that use FP Stack inline asm which the 555 // backend can't deal with (PR879). 556 Builder.defineMacro("__NO_MATH_INLINES"); 557 558 if (HasAES) 559 Builder.defineMacro("__AES__"); 560 561 if (HasVAES) 562 Builder.defineMacro("__VAES__"); 563 564 if (HasPCLMUL) 565 Builder.defineMacro("__PCLMUL__"); 566 567 if (HasVPCLMULQDQ) 568 Builder.defineMacro("__VPCLMULQDQ__"); 569 570 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, 571 // the feature flag only applies to 64-bit mode. 572 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86) 573 Builder.defineMacro("__LAHF_SAHF__"); 574 575 if (HasLZCNT) 576 Builder.defineMacro("__LZCNT__"); 577 578 if (HasRDRND) 579 Builder.defineMacro("__RDRND__"); 580 581 if (HasFSGSBASE) 582 Builder.defineMacro("__FSGSBASE__"); 583 584 if (HasBMI) 585 Builder.defineMacro("__BMI__"); 586 587 if (HasBMI2) 588 Builder.defineMacro("__BMI2__"); 589 590 if (HasPOPCNT) 591 Builder.defineMacro("__POPCNT__"); 592 593 if (HasRTM) 594 Builder.defineMacro("__RTM__"); 595 596 if (HasPRFCHW) 597 Builder.defineMacro("__PRFCHW__"); 598 599 if (HasRDSEED) 600 Builder.defineMacro("__RDSEED__"); 601 602 if (HasADX) 603 Builder.defineMacro("__ADX__"); 604 605 if (HasTBM) 606 Builder.defineMacro("__TBM__"); 607 608 if (HasLWP) 609 Builder.defineMacro("__LWP__"); 610 611 if (HasMWAITX) 612 Builder.defineMacro("__MWAITX__"); 613 614 if (HasMOVBE) 615 Builder.defineMacro("__MOVBE__"); 616 617 switch (XOPLevel) { 618 case XOP: 619 Builder.defineMacro("__XOP__"); 620 LLVM_FALLTHROUGH; 621 case FMA4: 622 Builder.defineMacro("__FMA4__"); 623 LLVM_FALLTHROUGH; 624 case SSE4A: 625 Builder.defineMacro("__SSE4A__"); 626 LLVM_FALLTHROUGH; 627 case NoXOP: 628 break; 629 } 630 631 if (HasFMA) 632 Builder.defineMacro("__FMA__"); 633 634 if (HasF16C) 635 Builder.defineMacro("__F16C__"); 636 637 if (HasGFNI) 638 Builder.defineMacro("__GFNI__"); 639 640 if (HasAVX512CD) 641 Builder.defineMacro("__AVX512CD__"); 642 if (HasAVX512VPOPCNTDQ) 643 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 644 if (HasAVX512VNNI) 645 Builder.defineMacro("__AVX512VNNI__"); 646 if (HasAVX512BF16) 647 Builder.defineMacro("__AVX512BF16__"); 648 if (HasAVX512ER) 649 Builder.defineMacro("__AVX512ER__"); 650 if (HasAVX512PF) 651 Builder.defineMacro("__AVX512PF__"); 652 if (HasAVX512DQ) 653 Builder.defineMacro("__AVX512DQ__"); 654 if (HasAVX512BITALG) 655 Builder.defineMacro("__AVX512BITALG__"); 656 if (HasAVX512BW) 657 Builder.defineMacro("__AVX512BW__"); 658 if (HasAVX512VL) 659 Builder.defineMacro("__AVX512VL__"); 660 if (HasAVX512VBMI) 661 Builder.defineMacro("__AVX512VBMI__"); 662 if (HasAVX512VBMI2) 663 Builder.defineMacro("__AVX512VBMI2__"); 664 if (HasAVX512IFMA) 665 Builder.defineMacro("__AVX512IFMA__"); 666 if (HasAVX512VP2INTERSECT) 667 Builder.defineMacro("__AVX512VP2INTERSECT__"); 668 if (HasSHA) 669 Builder.defineMacro("__SHA__"); 670 671 if (HasFXSR) 672 Builder.defineMacro("__FXSR__"); 673 if (HasXSAVE) 674 Builder.defineMacro("__XSAVE__"); 675 if (HasXSAVEOPT) 676 Builder.defineMacro("__XSAVEOPT__"); 677 if (HasXSAVEC) 678 Builder.defineMacro("__XSAVEC__"); 679 if (HasXSAVES) 680 Builder.defineMacro("__XSAVES__"); 681 if (HasPKU) 682 Builder.defineMacro("__PKU__"); 683 if (HasCLFLUSHOPT) 684 Builder.defineMacro("__CLFLUSHOPT__"); 685 if (HasCLWB) 686 Builder.defineMacro("__CLWB__"); 687 if (HasWBNOINVD) 688 Builder.defineMacro("__WBNOINVD__"); 689 if (HasSHSTK) 690 Builder.defineMacro("__SHSTK__"); 691 if (HasSGX) 692 Builder.defineMacro("__SGX__"); 693 if (HasPREFETCHWT1) 694 Builder.defineMacro("__PREFETCHWT1__"); 695 if (HasCLZERO) 696 Builder.defineMacro("__CLZERO__"); 697 if (HasKL) 698 Builder.defineMacro("__KL__"); 699 if (HasWIDEKL) 700 Builder.defineMacro("__WIDEKL__"); 701 if (HasRDPID) 702 Builder.defineMacro("__RDPID__"); 703 if (HasCLDEMOTE) 704 Builder.defineMacro("__CLDEMOTE__"); 705 if (HasWAITPKG) 706 Builder.defineMacro("__WAITPKG__"); 707 if (HasMOVDIRI) 708 Builder.defineMacro("__MOVDIRI__"); 709 if (HasMOVDIR64B) 710 Builder.defineMacro("__MOVDIR64B__"); 711 if (HasPCONFIG) 712 Builder.defineMacro("__PCONFIG__"); 713 if (HasPTWRITE) 714 Builder.defineMacro("__PTWRITE__"); 715 if (HasINVPCID) 716 Builder.defineMacro("__INVPCID__"); 717 if (HasENQCMD) 718 Builder.defineMacro("__ENQCMD__"); 719 if (HasHRESET) 720 Builder.defineMacro("__HRESET__"); 721 if (HasAMXTILE) 722 Builder.defineMacro("__AMXTILE__"); 723 if (HasAMXINT8) 724 Builder.defineMacro("__AMXINT8__"); 725 if (HasAMXBF16) 726 Builder.defineMacro("__AMXBF16__"); 727 if (HasSERIALIZE) 728 Builder.defineMacro("__SERIALIZE__"); 729 if (HasTSXLDTRK) 730 Builder.defineMacro("__TSXLDTRK__"); 731 if (HasUINTR) 732 Builder.defineMacro("__UINTR__"); 733 734 // Each case falls through to the previous one here. 735 switch (SSELevel) { 736 case AVX512F: 737 Builder.defineMacro("__AVX512F__"); 738 LLVM_FALLTHROUGH; 739 case AVX2: 740 Builder.defineMacro("__AVX2__"); 741 LLVM_FALLTHROUGH; 742 case AVX: 743 Builder.defineMacro("__AVX__"); 744 LLVM_FALLTHROUGH; 745 case SSE42: 746 Builder.defineMacro("__SSE4_2__"); 747 LLVM_FALLTHROUGH; 748 case SSE41: 749 Builder.defineMacro("__SSE4_1__"); 750 LLVM_FALLTHROUGH; 751 case SSSE3: 752 Builder.defineMacro("__SSSE3__"); 753 LLVM_FALLTHROUGH; 754 case SSE3: 755 Builder.defineMacro("__SSE3__"); 756 LLVM_FALLTHROUGH; 757 case SSE2: 758 Builder.defineMacro("__SSE2__"); 759 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 760 LLVM_FALLTHROUGH; 761 case SSE1: 762 Builder.defineMacro("__SSE__"); 763 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 764 LLVM_FALLTHROUGH; 765 case NoSSE: 766 break; 767 } 768 769 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 770 switch (SSELevel) { 771 case AVX512F: 772 case AVX2: 773 case AVX: 774 case SSE42: 775 case SSE41: 776 case SSSE3: 777 case SSE3: 778 case SSE2: 779 Builder.defineMacro("_M_IX86_FP", Twine(2)); 780 break; 781 case SSE1: 782 Builder.defineMacro("_M_IX86_FP", Twine(1)); 783 break; 784 default: 785 Builder.defineMacro("_M_IX86_FP", Twine(0)); 786 break; 787 } 788 } 789 790 // Each case falls through to the previous one here. 791 switch (MMX3DNowLevel) { 792 case AMD3DNowAthlon: 793 Builder.defineMacro("__3dNOW_A__"); 794 LLVM_FALLTHROUGH; 795 case AMD3DNow: 796 Builder.defineMacro("__3dNOW__"); 797 LLVM_FALLTHROUGH; 798 case MMX: 799 Builder.defineMacro("__MMX__"); 800 LLVM_FALLTHROUGH; 801 case NoMMX3DNow: 802 break; 803 } 804 805 if (CPU >= CK_i486 || CPU == CK_None) { 806 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 807 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 808 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 809 } 810 if (HasCX8) 811 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 812 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 813 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 814 815 if (HasFloat128) 816 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 817 } 818 819 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 820 return llvm::StringSwitch<bool>(Name) 821 .Case("3dnow", true) 822 .Case("3dnowa", true) 823 .Case("adx", true) 824 .Case("aes", true) 825 .Case("amx-bf16", true) 826 .Case("amx-int8", true) 827 .Case("amx-tile", true) 828 .Case("avx", true) 829 .Case("avx2", true) 830 .Case("avx512f", true) 831 .Case("avx512cd", true) 832 .Case("avx512vpopcntdq", true) 833 .Case("avx512vnni", true) 834 .Case("avx512bf16", true) 835 .Case("avx512er", true) 836 .Case("avx512pf", true) 837 .Case("avx512dq", true) 838 .Case("avx512bitalg", true) 839 .Case("avx512bw", true) 840 .Case("avx512vl", true) 841 .Case("avx512vbmi", true) 842 .Case("avx512vbmi2", true) 843 .Case("avx512ifma", true) 844 .Case("avx512vp2intersect", true) 845 .Case("bmi", true) 846 .Case("bmi2", true) 847 .Case("cldemote", true) 848 .Case("clflushopt", true) 849 .Case("clwb", true) 850 .Case("clzero", true) 851 .Case("cx16", true) 852 .Case("enqcmd", true) 853 .Case("f16c", true) 854 .Case("fma", true) 855 .Case("fma4", true) 856 .Case("fsgsbase", true) 857 .Case("fxsr", true) 858 .Case("gfni", true) 859 .Case("hreset", true) 860 .Case("invpcid", true) 861 .Case("kl", true) 862 .Case("widekl", true) 863 .Case("lwp", true) 864 .Case("lzcnt", true) 865 .Case("mmx", true) 866 .Case("movbe", true) 867 .Case("movdiri", true) 868 .Case("movdir64b", true) 869 .Case("mwaitx", true) 870 .Case("pclmul", true) 871 .Case("pconfig", true) 872 .Case("pku", true) 873 .Case("popcnt", true) 874 .Case("prefetchwt1", true) 875 .Case("prfchw", true) 876 .Case("ptwrite", true) 877 .Case("rdpid", true) 878 .Case("rdrnd", true) 879 .Case("rdseed", true) 880 .Case("rtm", true) 881 .Case("sahf", true) 882 .Case("serialize", true) 883 .Case("sgx", true) 884 .Case("sha", true) 885 .Case("shstk", true) 886 .Case("sse", true) 887 .Case("sse2", true) 888 .Case("sse3", true) 889 .Case("ssse3", true) 890 .Case("sse4", true) 891 .Case("sse4.1", true) 892 .Case("sse4.2", true) 893 .Case("sse4a", true) 894 .Case("tbm", true) 895 .Case("tsxldtrk", true) 896 .Case("uintr", true) 897 .Case("vaes", true) 898 .Case("vpclmulqdq", true) 899 .Case("wbnoinvd", true) 900 .Case("waitpkg", true) 901 .Case("x87", true) 902 .Case("xop", true) 903 .Case("xsave", true) 904 .Case("xsavec", true) 905 .Case("xsaves", true) 906 .Case("xsaveopt", true) 907 .Default(false); 908 } 909 910 bool X86TargetInfo::hasFeature(StringRef Feature) const { 911 return llvm::StringSwitch<bool>(Feature) 912 .Case("adx", HasADX) 913 .Case("aes", HasAES) 914 .Case("amx-bf16", HasAMXBF16) 915 .Case("amx-int8", HasAMXINT8) 916 .Case("amx-tile", HasAMXTILE) 917 .Case("avx", SSELevel >= AVX) 918 .Case("avx2", SSELevel >= AVX2) 919 .Case("avx512f", SSELevel >= AVX512F) 920 .Case("avx512cd", HasAVX512CD) 921 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 922 .Case("avx512vnni", HasAVX512VNNI) 923 .Case("avx512bf16", HasAVX512BF16) 924 .Case("avx512er", HasAVX512ER) 925 .Case("avx512pf", HasAVX512PF) 926 .Case("avx512dq", HasAVX512DQ) 927 .Case("avx512bitalg", HasAVX512BITALG) 928 .Case("avx512bw", HasAVX512BW) 929 .Case("avx512vl", HasAVX512VL) 930 .Case("avx512vbmi", HasAVX512VBMI) 931 .Case("avx512vbmi2", HasAVX512VBMI2) 932 .Case("avx512ifma", HasAVX512IFMA) 933 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 934 .Case("bmi", HasBMI) 935 .Case("bmi2", HasBMI2) 936 .Case("cldemote", HasCLDEMOTE) 937 .Case("clflushopt", HasCLFLUSHOPT) 938 .Case("clwb", HasCLWB) 939 .Case("clzero", HasCLZERO) 940 .Case("cx8", HasCX8) 941 .Case("cx16", HasCX16) 942 .Case("enqcmd", HasENQCMD) 943 .Case("f16c", HasF16C) 944 .Case("fma", HasFMA) 945 .Case("fma4", XOPLevel >= FMA4) 946 .Case("fsgsbase", HasFSGSBASE) 947 .Case("fxsr", HasFXSR) 948 .Case("gfni", HasGFNI) 949 .Case("hreset", HasHRESET) 950 .Case("invpcid", HasINVPCID) 951 .Case("kl", HasKL) 952 .Case("widekl", HasWIDEKL) 953 .Case("lwp", HasLWP) 954 .Case("lzcnt", HasLZCNT) 955 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 956 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 957 .Case("mmx", MMX3DNowLevel >= MMX) 958 .Case("movbe", HasMOVBE) 959 .Case("movdiri", HasMOVDIRI) 960 .Case("movdir64b", HasMOVDIR64B) 961 .Case("mwaitx", HasMWAITX) 962 .Case("pclmul", HasPCLMUL) 963 .Case("pconfig", HasPCONFIG) 964 .Case("pku", HasPKU) 965 .Case("popcnt", HasPOPCNT) 966 .Case("prefetchwt1", HasPREFETCHWT1) 967 .Case("prfchw", HasPRFCHW) 968 .Case("ptwrite", HasPTWRITE) 969 .Case("rdpid", HasRDPID) 970 .Case("rdrnd", HasRDRND) 971 .Case("rdseed", HasRDSEED) 972 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 973 .Case("rtm", HasRTM) 974 .Case("sahf", HasLAHFSAHF) 975 .Case("serialize", HasSERIALIZE) 976 .Case("sgx", HasSGX) 977 .Case("sha", HasSHA) 978 .Case("shstk", HasSHSTK) 979 .Case("sse", SSELevel >= SSE1) 980 .Case("sse2", SSELevel >= SSE2) 981 .Case("sse3", SSELevel >= SSE3) 982 .Case("ssse3", SSELevel >= SSSE3) 983 .Case("sse4.1", SSELevel >= SSE41) 984 .Case("sse4.2", SSELevel >= SSE42) 985 .Case("sse4a", XOPLevel >= SSE4A) 986 .Case("tbm", HasTBM) 987 .Case("tsxldtrk", HasTSXLDTRK) 988 .Case("uintr", HasUINTR) 989 .Case("vaes", HasVAES) 990 .Case("vpclmulqdq", HasVPCLMULQDQ) 991 .Case("wbnoinvd", HasWBNOINVD) 992 .Case("waitpkg", HasWAITPKG) 993 .Case("x86", true) 994 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 995 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 996 .Case("xop", XOPLevel >= XOP) 997 .Case("xsave", HasXSAVE) 998 .Case("xsavec", HasXSAVEC) 999 .Case("xsaves", HasXSAVES) 1000 .Case("xsaveopt", HasXSAVEOPT) 1001 .Default(false); 1002 } 1003 1004 // We can't use a generic validation scheme for the features accepted here 1005 // versus subtarget features accepted in the target attribute because the 1006 // bitfield structure that's initialized in the runtime only supports the 1007 // below currently rather than the full range of subtarget features. (See 1008 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1009 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1010 return llvm::StringSwitch<bool>(FeatureStr) 1011 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, true) 1012 #include "llvm/Support/X86TargetParser.def" 1013 .Default(false); 1014 } 1015 1016 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1017 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1018 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, llvm::X86::FEATURE_##ENUM) 1019 #include "llvm/Support/X86TargetParser.def" 1020 ; 1021 // Note, this function should only be used after ensuring the value is 1022 // correct, so it asserts if the value is out of range. 1023 } 1024 1025 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1026 enum class FeatPriority { 1027 #define FEATURE(FEAT) FEAT, 1028 #include "clang/Basic/X86Target.def" 1029 }; 1030 switch (Feat) { 1031 #define FEATURE(FEAT) \ 1032 case llvm::X86::FEAT: \ 1033 return static_cast<unsigned>(FeatPriority::FEAT); 1034 #include "clang/Basic/X86Target.def" 1035 default: 1036 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1037 } 1038 } 1039 1040 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1041 // Valid CPUs have a 'key feature' that compares just better than its key 1042 // feature. 1043 using namespace llvm::X86; 1044 CPUKind Kind = parseArchX86(Name); 1045 if (Kind != CK_None) { 1046 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1047 return (getFeaturePriority(KeyFeature) << 1) + 1; 1048 } 1049 1050 // Now we know we have a feature, so get its priority and shift it a few so 1051 // that we have sufficient room for the CPUs (above). 1052 return getFeaturePriority(getFeature(Name)) << 1; 1053 } 1054 1055 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1056 return llvm::StringSwitch<bool>(Name) 1057 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1058 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1059 #include "clang/Basic/X86Target.def" 1060 .Default(false); 1061 } 1062 1063 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1064 return llvm::StringSwitch<StringRef>(Name) 1065 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1066 #include "clang/Basic/X86Target.def" 1067 .Default(Name); 1068 } 1069 1070 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1071 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1072 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1073 #include "clang/Basic/X86Target.def" 1074 .Default(0); 1075 } 1076 1077 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1078 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1079 StringRef WholeList = 1080 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1081 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1082 #include "clang/Basic/X86Target.def" 1083 .Default(""); 1084 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1085 } 1086 1087 // We can't use a generic validation scheme for the cpus accepted here 1088 // versus subtarget cpus accepted in the target attribute because the 1089 // variables intitialized by the runtime only support the below currently 1090 // rather than the full range of cpus. 1091 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1092 return llvm::StringSwitch<bool>(FeatureStr) 1093 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1094 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1095 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1096 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1097 #include "llvm/Support/X86TargetParser.def" 1098 .Default(false); 1099 } 1100 1101 static unsigned matchAsmCCConstraint(const char *&Name) { 1102 auto RV = llvm::StringSwitch<unsigned>(Name) 1103 .Case("@cca", 4) 1104 .Case("@ccae", 5) 1105 .Case("@ccb", 4) 1106 .Case("@ccbe", 5) 1107 .Case("@ccc", 4) 1108 .Case("@cce", 4) 1109 .Case("@ccz", 4) 1110 .Case("@ccg", 4) 1111 .Case("@ccge", 5) 1112 .Case("@ccl", 4) 1113 .Case("@ccle", 5) 1114 .Case("@ccna", 5) 1115 .Case("@ccnae", 6) 1116 .Case("@ccnb", 5) 1117 .Case("@ccnbe", 6) 1118 .Case("@ccnc", 5) 1119 .Case("@ccne", 5) 1120 .Case("@ccnz", 5) 1121 .Case("@ccng", 5) 1122 .Case("@ccnge", 6) 1123 .Case("@ccnl", 5) 1124 .Case("@ccnle", 6) 1125 .Case("@ccno", 5) 1126 .Case("@ccnp", 5) 1127 .Case("@ccns", 5) 1128 .Case("@cco", 4) 1129 .Case("@ccp", 4) 1130 .Case("@ccs", 4) 1131 .Default(0); 1132 return RV; 1133 } 1134 1135 bool X86TargetInfo::validateAsmConstraint( 1136 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1137 switch (*Name) { 1138 default: 1139 return false; 1140 // Constant constraints. 1141 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1142 // instructions. 1143 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1144 // x86_64 instructions. 1145 case 's': 1146 Info.setRequiresImmediate(); 1147 return true; 1148 case 'I': 1149 Info.setRequiresImmediate(0, 31); 1150 return true; 1151 case 'J': 1152 Info.setRequiresImmediate(0, 63); 1153 return true; 1154 case 'K': 1155 Info.setRequiresImmediate(-128, 127); 1156 return true; 1157 case 'L': 1158 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1159 return true; 1160 case 'M': 1161 Info.setRequiresImmediate(0, 3); 1162 return true; 1163 case 'N': 1164 Info.setRequiresImmediate(0, 255); 1165 return true; 1166 case 'O': 1167 Info.setRequiresImmediate(0, 127); 1168 return true; 1169 // Register constraints. 1170 case 'Y': // 'Y' is the first character for several 2-character constraints. 1171 // Shift the pointer to the second character of the constraint. 1172 Name++; 1173 switch (*Name) { 1174 default: 1175 return false; 1176 case 'z': // First SSE register. 1177 case '2': 1178 case 't': // Any SSE register, when SSE2 is enabled. 1179 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1180 case 'm': // Any MMX register, when inter-unit moves enabled. 1181 case 'k': // AVX512 arch mask registers: k1-k7. 1182 Info.setAllowsRegister(); 1183 return true; 1184 } 1185 case 'f': // Any x87 floating point stack register. 1186 // Constraint 'f' cannot be used for output operands. 1187 if (Info.ConstraintStr[0] == '=') 1188 return false; 1189 Info.setAllowsRegister(); 1190 return true; 1191 case 'a': // eax. 1192 case 'b': // ebx. 1193 case 'c': // ecx. 1194 case 'd': // edx. 1195 case 'S': // esi. 1196 case 'D': // edi. 1197 case 'A': // edx:eax. 1198 case 't': // Top of floating point stack. 1199 case 'u': // Second from top of floating point stack. 1200 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1201 case 'y': // Any MMX register. 1202 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1203 case 'x': // Any SSE register. 1204 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1205 // for intermideate k reg operations). 1206 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1207 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1208 case 'l': // "Index" registers: any general register that can be used as an 1209 // index in a base+index memory access. 1210 Info.setAllowsRegister(); 1211 return true; 1212 // Floating point constant constraints. 1213 case 'C': // SSE floating point constant. 1214 case 'G': // x87 floating point constant. 1215 return true; 1216 case '@': 1217 // CC condition changes. 1218 if (auto Len = matchAsmCCConstraint(Name)) { 1219 Name += Len - 1; 1220 Info.setAllowsRegister(); 1221 return true; 1222 } 1223 return false; 1224 } 1225 } 1226 1227 // Below is based on the following information: 1228 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1229 // | Processor Name | Cache Line Size (Bytes) | Source | 1230 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1231 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1232 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1233 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1234 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1235 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1236 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1237 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1238 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1239 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1240 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1241 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1242 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1243 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1244 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1245 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1246 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1247 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1248 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1249 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1250 using namespace llvm::X86; 1251 switch (CPU) { 1252 // i386 1253 case CK_i386: 1254 // i486 1255 case CK_i486: 1256 case CK_WinChipC6: 1257 case CK_WinChip2: 1258 case CK_C3: 1259 // Lakemont 1260 case CK_Lakemont: 1261 return 16; 1262 1263 // i586 1264 case CK_i586: 1265 case CK_Pentium: 1266 case CK_PentiumMMX: 1267 // i686 1268 case CK_PentiumPro: 1269 case CK_i686: 1270 case CK_Pentium2: 1271 case CK_Pentium3: 1272 case CK_PentiumM: 1273 case CK_C3_2: 1274 // K6 1275 case CK_K6: 1276 case CK_K6_2: 1277 case CK_K6_3: 1278 // Geode 1279 case CK_Geode: 1280 return 32; 1281 1282 // Netburst 1283 case CK_Pentium4: 1284 case CK_Prescott: 1285 case CK_Nocona: 1286 // Atom 1287 case CK_Bonnell: 1288 case CK_Silvermont: 1289 case CK_Goldmont: 1290 case CK_GoldmontPlus: 1291 case CK_Tremont: 1292 1293 case CK_Westmere: 1294 case CK_SandyBridge: 1295 case CK_IvyBridge: 1296 case CK_Haswell: 1297 case CK_Broadwell: 1298 case CK_SkylakeClient: 1299 case CK_SkylakeServer: 1300 case CK_Cascadelake: 1301 case CK_Nehalem: 1302 case CK_Cooperlake: 1303 case CK_Cannonlake: 1304 case CK_Tigerlake: 1305 case CK_SapphireRapids: 1306 case CK_IcelakeClient: 1307 case CK_IcelakeServer: 1308 case CK_KNL: 1309 case CK_KNM: 1310 // K7 1311 case CK_Athlon: 1312 case CK_AthlonXP: 1313 // K8 1314 case CK_K8: 1315 case CK_K8SSE3: 1316 case CK_AMDFAM10: 1317 // Bobcat 1318 case CK_BTVER1: 1319 case CK_BTVER2: 1320 // Bulldozer 1321 case CK_BDVER1: 1322 case CK_BDVER2: 1323 case CK_BDVER3: 1324 case CK_BDVER4: 1325 // Zen 1326 case CK_ZNVER1: 1327 case CK_ZNVER2: 1328 // Deprecated 1329 case CK_x86_64: 1330 case CK_x86_64_v2: 1331 case CK_x86_64_v3: 1332 case CK_x86_64_v4: 1333 case CK_Yonah: 1334 case CK_Penryn: 1335 case CK_Core2: 1336 return 64; 1337 1338 // The following currently have unknown cache line sizes (but they are probably all 64): 1339 // Core 1340 case CK_None: 1341 return None; 1342 } 1343 llvm_unreachable("Unknown CPU kind"); 1344 } 1345 1346 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1347 StringRef Constraint, 1348 unsigned Size) const { 1349 // Strip off constraint modifiers. 1350 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1351 Constraint = Constraint.substr(1); 1352 1353 return validateOperandSize(FeatureMap, Constraint, Size); 1354 } 1355 1356 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1357 StringRef Constraint, 1358 unsigned Size) const { 1359 return validateOperandSize(FeatureMap, Constraint, Size); 1360 } 1361 1362 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1363 StringRef Constraint, 1364 unsigned Size) const { 1365 switch (Constraint[0]) { 1366 default: 1367 break; 1368 case 'k': 1369 // Registers k0-k7 (AVX512) size limit is 64 bit. 1370 case 'y': 1371 return Size <= 64; 1372 case 'f': 1373 case 't': 1374 case 'u': 1375 return Size <= 128; 1376 case 'Y': 1377 // 'Y' is the first character for several 2-character constraints. 1378 switch (Constraint[1]) { 1379 default: 1380 return false; 1381 case 'm': 1382 // 'Ym' is synonymous with 'y'. 1383 case 'k': 1384 return Size <= 64; 1385 case 'z': 1386 // XMM0/YMM/ZMM0 1387 if (FeatureMap.lookup("avx512f")) 1388 // ZMM0 can be used if target supports AVX512F. 1389 return Size <= 512U; 1390 else if (FeatureMap.lookup("avx")) 1391 // YMM0 can be used if target supports AVX. 1392 return Size <= 256U; 1393 else if (FeatureMap.lookup("sse")) 1394 return Size <= 128U; 1395 return false; 1396 case 'i': 1397 case 't': 1398 case '2': 1399 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1400 if (SSELevel < SSE2) 1401 return false; 1402 break; 1403 } 1404 break; 1405 case 'v': 1406 case 'x': 1407 if (FeatureMap.lookup("avx512f")) 1408 // 512-bit zmm registers can be used if target supports AVX512F. 1409 return Size <= 512U; 1410 else if (FeatureMap.lookup("avx")) 1411 // 256-bit ymm registers can be used if target supports AVX. 1412 return Size <= 256U; 1413 return Size <= 128U; 1414 1415 } 1416 1417 return true; 1418 } 1419 1420 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1421 switch (*Constraint) { 1422 case '@': 1423 if (auto Len = matchAsmCCConstraint(Constraint)) { 1424 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1425 Constraint += Len - 1; 1426 return Converted; 1427 } 1428 return std::string(1, *Constraint); 1429 case 'a': 1430 return std::string("{ax}"); 1431 case 'b': 1432 return std::string("{bx}"); 1433 case 'c': 1434 return std::string("{cx}"); 1435 case 'd': 1436 return std::string("{dx}"); 1437 case 'S': 1438 return std::string("{si}"); 1439 case 'D': 1440 return std::string("{di}"); 1441 case 'p': // address 1442 return std::string("im"); 1443 case 't': // top of floating point stack. 1444 return std::string("{st}"); 1445 case 'u': // second from top of floating point stack. 1446 return std::string("{st(1)}"); // second from top of floating point stack. 1447 case 'Y': 1448 switch (Constraint[1]) { 1449 default: 1450 // Break from inner switch and fall through (copy single char), 1451 // continue parsing after copying the current constraint into 1452 // the return string. 1453 break; 1454 case 'k': 1455 case 'm': 1456 case 'i': 1457 case 't': 1458 case 'z': 1459 case '2': 1460 // "^" hints llvm that this is a 2 letter constraint. 1461 // "Constraint++" is used to promote the string iterator 1462 // to the next constraint. 1463 return std::string("^") + std::string(Constraint++, 2); 1464 } 1465 LLVM_FALLTHROUGH; 1466 default: 1467 return std::string(1, *Constraint); 1468 } 1469 } 1470 1471 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1472 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1473 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1474 } 1475 1476 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1477 llvm::X86::fillValidTuneCPUList(Values); 1478 } 1479 1480 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1481 return llvm::makeArrayRef(GCCRegNames); 1482 } 1483 1484 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1485 return llvm::makeArrayRef(AddlRegNames); 1486 } 1487 1488 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1489 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1490 Builtin::FirstTSBuiltin + 1); 1491 } 1492 1493 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1494 return llvm::makeArrayRef(BuiltinInfoX86, 1495 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1496 } 1497