[X86][BF16] Enable __bf16 for x86 targets.

X86 psABI has updated to support __bf16 type, the ABI of which is the
same as FP16. See https://discourse.llvm.org/t/patch-add-optional-bfloat16-support/63

[X86][BF16] Enable __bf16 for x86 targets.

X86 psABI has updated to support __bf16 type, the ABI of which is the
same as FP16. See https://discourse.llvm.org/t/patch-add-optional-bfloat16-support/63149

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D130964

(cherry picked from commit e4888a37d36780872d685c68ef8b26b2e14d6d39)

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[X86] Add RDPRU instruction

Add support for the RDPRU instruction on Zen2 processors.

User-facing features:

- Clang option -m[no-]rdpru to enable/disable the feature
- Support is implicit for znve

[X86] Add RDPRU instruction

Add support for the RDPRU instruction on Zen2 processors.

User-facing features:

- Clang option -m[no-]rdpru to enable/disable the feature
- Support is implicit for znver2/znver3 processors
- Preprocessor symbol __RDPRU__ to indicate support
- Header rdpruintrin.h to define intrinsics
- "rdpru" mnemonic supported for assembler code

Internal features:

- Clang builtin __builtin_ia32_rdpru
- IR intrinsic @llvm.x86.rdpru

Differential Revision: https://reviews.llvm.org/D128934

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[X86] Support `_Float16` on SSE2 and up

This is split from D113107 to address #56204 and https://discourse.llvm.org/t/how-to-build-compiler-rt-for-new-x86-half-float-abi/63366

Reviewed By: zahiraam

[X86] Support `_Float16` on SSE2 and up

This is split from D113107 to address #56204 and https://discourse.llvm.org/t/how-to-build-compiler-rt-for-new-x86-half-float-abi/63366

Reviewed By: zahiraam, rjmccall, bkramer, MaskRay

Differential Revision: https://reviews.llvm.org/D128571

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Revert "Reland "[X86] Support `_Float16` on SSE2 and up""

Broke compiler-rt on Darwin: https://green.lab.llvm.org/green/job/clang-stage1-RA/29920/

This reverts commit 527ef8ca981e88a35758c0e4143be6

Revert "Reland "[X86] Support `_Float16` on SSE2 and up""

Broke compiler-rt on Darwin: https://green.lab.llvm.org/green/job/clang-stage1-RA/29920/

This reverts commit 527ef8ca981e88a35758c0e4143be6853ea26dfc.

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Reland "[X86] Support `_Float16` on SSE2 and up"

Enable `COMPILER_RT_HAS_FLOAT16` to solve the lit fail.

This is split from D113107 to address #56204 and https://discourse.llvm.org/t/how-to-build-c

Reland "[X86] Support `_Float16` on SSE2 and up"

Enable `COMPILER_RT_HAS_FLOAT16` to solve the lit fail.

This is split from D113107 to address #56204 and https://discourse.llvm.org/t/how-to-build-compiler-rt-for-new-x86-half-float-abi/63366

Reviewed By: zahiraam, rjmccall, bkramer

Differential Revision: https://reviews.llvm.org/D128571

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Revert "[X86] Support `_Float16` on SSE2 and up"

Breaks buildbot
https://lab.llvm.org/buildbot/#/builders/37/builds/14334

This reverts commit f5d781d6273cc56dd8b44ee9e4cfb2ae5579bb04.

[X86] Support `_Float16` on SSE2 and up

This is split from D113107 to address #56204 and https://discourse.llvm.org/t/how-to-build-compiler-rt-for-new-x86-half-float-abi/63366

Reviewed By: zahiraam

[X86] Support `_Float16` on SSE2 and up

This is split from D113107 to address #56204 and https://discourse.llvm.org/t/how-to-build-compiler-rt-for-new-x86-half-float-abi/63366

Reviewed By: zahiraam, rjmccall, bkramer

Differential Revision: https://reviews.llvm.org/D128571

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[InlineAsm] Add support for address operands ("p").

This patch adds support for inline assembly address operands using the "p"
constraint on X86 and SystemZ.

This was in fact broken on X86 (see exa

[InlineAsm] Add support for address operands ("p").

This patch adds support for inline assembly address operands using the "p"
constraint on X86 and SystemZ.

This was in fact broken on X86 (see example at
https://reviews.llvm.org/D110267, Nov 23).

These operands should probably be treated the same as memory operands by
CodeGenPrepare, which have been commented with "TODO" there.

Review: Xiang Zhang and Ulrich Weigand

Differential Revision: https://reviews.llvm.org/D122220

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Have cpu-specific variants set 'tune-cpu' as an optimization hint

Due to various implementation constraints, despite the programmer
choosing a 'processor' cpu_dispatch/cpu_specific needs to use the

Have cpu-specific variants set 'tune-cpu' as an optimization hint

Due to various implementation constraints, despite the programmer
choosing a 'processor' cpu_dispatch/cpu_specific needs to use the
'feature' list of a processor to identify it. This results in the
identified processor in source-code not being propogated to the
optimizer, and thus, not able to be tuned for.

This patch changes to use the actual cpu as written for tune-cpu so that
opt can make decisions based on the cpu-as-spelled, which should better
match the behavior expected by the programmer.

Note that the 'valid' list of processors for x86 is in
llvm/include/llvm/Support/X86TargetParser.def. At the moment, this list
contains only Intel processors, but other vendors may wish to add their
own entries as 'alias'es (or with different feature lists!).

If this is not done, there is two potential performance issues with the
patch, but I believe them to be worth it in light of the improvements to
behavior and performance.

1- In the event that the user spelled "ProcessorB", but we only have the
features available to test for "ProcessorA" (where A is B minus
features),
AND there is an optimization opportunity for "B" that negatively affects
"A", the optimizer will likely choose to do so.

2- In the event that the user spelled VendorI's processor, and the
feature
list allows it to run on VendorA's processor of similar features, AND
there
is an optimization opportunity for VendorIs that negatively affects
"A"s,
the optimizer will likely choose to do so. This can be fixed by adding
an
alias to X86TargetParser.def.

Differential Revision: https://reviews.llvm.org/D121410

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Revert "[X86][clang] Emit diagnostic for float and double when we have features -x87 and -sse on 64-bits"

This reverts commit 4a2c827b178f89d4cdeb56153d9440ad4ba786a3.

Need to fix the problem when

Revert "[X86][clang] Emit diagnostic for float and double when we have features -x87 and -sse on 64-bits"

This reverts commit 4a2c827b178f89d4cdeb56153d9440ad4ba786a3.

Need to fix the problem when using `-mno-sse` together with "x86intrin.h"

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[X86][clang] Emit diagnostic for float and double when we have features -x87 and -sse on 64-bits

A follow up of D114162.

Reviewed By: asavonic

Differential Revision: https://reviews.llvm.org/D1147

[X86][clang] Emit diagnostic for float and double when we have features -x87 and -sse on 64-bits

A follow up of D114162.

Reviewed By: asavonic

Differential Revision: https://reviews.llvm.org/D114782

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[X86][clang] Enable floating-point type for -mno-x87 option on 32-bits

We should match GCC's behavior which allows floating-point type for -mno-x87 option on 32-bits. https://godbolt.org/z/KrbhfWc9o

[X86][clang] Enable floating-point type for -mno-x87 option on 32-bits

We should match GCC's behavior which allows floating-point type for -mno-x87 option on 32-bits. https://godbolt.org/z/KrbhfWc9o

The previous block issues have partially been fixed by D112143.

Reviewed By: asavonic, nickdesaulniers

Differential Revision: https://reviews.llvm.org/D114162

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Revert "The _Float16 type is supported on x86 systems with SSE2 enabled."

This reverts commit 6623c02d70c3732dbea59c6d79c69501baf9627b.
The change seems to be breaking build of compiler-rt on Debian.

The _Float16 type is supported on x86 systems with SSE2 enabled.
Operations are emulated by software emulation and “float” instructions.
This patch is allowing the support of _Float16 type without th

The _Float16 type is supported on x86 systems with SSE2 enabled.
Operations are emulated by software emulation and “float” instructions.
This patch is allowing the support of _Float16 type without the use of
-max512fp16 flag. The final goal being, perform _Float16 emulation for
all arithmetic expressions.

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[X86][clang] Disable long double type for -mno-x87 option

This patch attempts to fix a compiler crash that occurs when long
double type is used with -mno-x87 compiler option.

The option disables x8

[X86][clang] Disable long double type for -mno-x87 option

This patch attempts to fix a compiler crash that occurs when long
double type is used with -mno-x87 compiler option.

The option disables x87 target feature, which in turn disables x87
registers, so CG cannot select them for x86_fp80 LLVM IR type. Long
double is lowered as x86_fp80 for some targets, so it leads to a
crash.

The option seems to contradict the SystemV ABI, which requires long
double to be represented as a 80-bit floating point, and it also
requires to use x87 registers.

To avoid that, `long double` type is disabled when -mno-x87 option is
set. In addition to that, `float` and `double` also use x87 registers
for return values on 32-bit x86, so they are disabled as well.

Differential Revision: https://reviews.llvm.org/D98895

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[Basic] Use llvm::is_contained (NFC)

[X86] Add CRC32 feature.

d8faf03807ac implemented general-regs-only for X86 by disabling all features
with vector instructions. But the CRC32 instruction in SSE4.2 ISA, which uses
only GPRs, also be

[X86] Add CRC32 feature.

d8faf03807ac implemented general-regs-only for X86 by disabling all features
with vector instructions. But the CRC32 instruction in SSE4.2 ISA, which uses
only GPRs, also becomes unavailable. This patch adds a CRC32 feature for this
instruction and allows it to be used with general-regs-only.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D105462

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[NFC][clang] Move IR-independent parts of target MV support to X86TargetParser.cpp

...that is located under llvm/lib/Support/.

Reviewed By: erichkeane

Differential Revision: https://reviews.llvm.o

[NFC][clang] Move IR-independent parts of target MV support to X86TargetParser.cpp

...that is located under llvm/lib/Support/.

Reviewed By: erichkeane

Differential Revision: https://reviews.llvm.org/D108423

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[NFC][clang] Move remaining part of X86Target.def to llvm/Support/X86TargetParser.def

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D108422

[NFC][clang] Use X86 Features declaration from X86TargetParser

...instead of redeclaring them in clang's own X86Target.def. They were already
required to be in sync (IIUC), so no reason to maintain

[NFC][clang] Use X86 Features declaration from X86TargetParser

...instead of redeclaring them in clang's own X86Target.def. They were already
required to be in sync (IIUC), so no reason to maintain two identical lists.

Reviewed By: erichkeane, craig.topper

Differential Revision: https://reviews.llvm.org/D108151

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[X86] AVX512FP16 instructions enabling 1/6

1. Enable FP16 type support and basic declarations used by following patches.
2. Enable new instructions VMOVW and VMOVSH.

Ref.: https://software.intel.co

[X86] AVX512FP16 instructions enabling 1/6

1. Enable FP16 type support and basic declarations used by following patches.
2. Enable new instructions VMOVW and VMOVSH.

Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D105263

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[X86] Add -mgeneral-regs-only support.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D103943

Fix -Wswitch warning after 092c303955cd18be6c0b923b1c0a1b96e2c91893.

AMD k8 family does not support SSE4.x which are required by x86-64-v2+

So don't define __tune__k8__ for these micro architecture.

SSE, SSE2 and SSE3 appear in https://www.amd.com/system/files/TechD

AMD k8 family does not support SSE4.x which are required by x86-64-v2+

So don't define __tune__k8__ for these micro architecture.

SSE, SSE2 and SSE3 appear in https://www.amd.com/system/files/TechDocs/25112.PDF
but not SSE4.x.

Differential Revision: https://reviews.llvm.org/D104116

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[OpenCL] Introduce new method for validating OpenCL target

Language options are not available when a target is being created,
thus, a new method is introduced. Also, some refactoring is done,
such a

[OpenCL] Introduce new method for validating OpenCL target

Language options are not available when a target is being created,
thus, a new method is introduced. Also, some refactoring is done,
such as removing OpenCL feature macros setting from TargetInfo.

Reviewed By: Anastasia

Differential Revision: https://reviews.llvm.org/D101087

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