1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabled(Features, "sse2", true); 112 113 using namespace llvm::X86; 114 115 SmallVector<StringRef, 16> CPUFeatures; 116 getFeaturesForCPU(CPU, CPUFeatures); 117 for (auto &F : CPUFeatures) 118 setFeatureEnabled(Features, F, true); 119 120 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 121 return false; 122 123 // Can't do this earlier because we need to be able to explicitly enable 124 // or disable these features and the things that they depend upon. 125 126 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 127 auto I = Features.find("sse4.2"); 128 if (I != Features.end() && I->getValue() && 129 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 130 Features["popcnt"] = true; 131 132 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 133 // then enable MMX. 134 I = Features.find("sse"); 135 if (I != Features.end() && I->getValue() && 136 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 137 Features["mmx"] = true; 138 139 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 140 I = Features.find("avx"); 141 if (I != Features.end() && I->getValue() && 142 llvm::find(FeaturesVec, "-xsave") == FeaturesVec.end()) 143 Features["xsave"] = true; 144 145 return true; 146 } 147 148 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 149 StringRef Name, bool Enabled) const { 150 if (Name == "sse4") { 151 // We can get here via the __target__ attribute since that's not controlled 152 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 153 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 154 // disabled. 155 if (Enabled) 156 Name = "sse4.2"; 157 else 158 Name = "sse4.1"; 159 } 160 161 Features[Name] = Enabled; 162 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 163 } 164 165 /// handleTargetFeatures - Perform initialization based on the user 166 /// configured set of features. 167 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 168 DiagnosticsEngine &Diags) { 169 for (const auto &Feature : Features) { 170 if (Feature[0] != '+') 171 continue; 172 173 if (Feature == "+aes") { 174 HasAES = true; 175 } else if (Feature == "+vaes") { 176 HasVAES = true; 177 } else if (Feature == "+pclmul") { 178 HasPCLMUL = true; 179 } else if (Feature == "+vpclmulqdq") { 180 HasVPCLMULQDQ = true; 181 } else if (Feature == "+lzcnt") { 182 HasLZCNT = true; 183 } else if (Feature == "+rdrnd") { 184 HasRDRND = true; 185 } else if (Feature == "+fsgsbase") { 186 HasFSGSBASE = true; 187 } else if (Feature == "+bmi") { 188 HasBMI = true; 189 } else if (Feature == "+bmi2") { 190 HasBMI2 = true; 191 } else if (Feature == "+popcnt") { 192 HasPOPCNT = true; 193 } else if (Feature == "+rtm") { 194 HasRTM = true; 195 } else if (Feature == "+prfchw") { 196 HasPRFCHW = true; 197 } else if (Feature == "+rdseed") { 198 HasRDSEED = true; 199 } else if (Feature == "+adx") { 200 HasADX = true; 201 } else if (Feature == "+tbm") { 202 HasTBM = true; 203 } else if (Feature == "+lwp") { 204 HasLWP = true; 205 } else if (Feature == "+fma") { 206 HasFMA = true; 207 } else if (Feature == "+f16c") { 208 HasF16C = true; 209 } else if (Feature == "+gfni") { 210 HasGFNI = true; 211 } else if (Feature == "+avx512cd") { 212 HasAVX512CD = true; 213 } else if (Feature == "+avx512vpopcntdq") { 214 HasAVX512VPOPCNTDQ = true; 215 } else if (Feature == "+avx512vnni") { 216 HasAVX512VNNI = true; 217 } else if (Feature == "+avx512bf16") { 218 HasAVX512BF16 = true; 219 } else if (Feature == "+avx512er") { 220 HasAVX512ER = true; 221 } else if (Feature == "+avx512pf") { 222 HasAVX512PF = true; 223 } else if (Feature == "+avx512dq") { 224 HasAVX512DQ = true; 225 } else if (Feature == "+avx512bitalg") { 226 HasAVX512BITALG = true; 227 } else if (Feature == "+avx512bw") { 228 HasAVX512BW = true; 229 } else if (Feature == "+avx512vl") { 230 HasAVX512VL = true; 231 } else if (Feature == "+avx512vbmi") { 232 HasAVX512VBMI = true; 233 } else if (Feature == "+avx512vbmi2") { 234 HasAVX512VBMI2 = true; 235 } else if (Feature == "+avx512ifma") { 236 HasAVX512IFMA = true; 237 } else if (Feature == "+avx512vp2intersect") { 238 HasAVX512VP2INTERSECT = true; 239 } else if (Feature == "+sha") { 240 HasSHA = true; 241 } else if (Feature == "+shstk") { 242 HasSHSTK = true; 243 } else if (Feature == "+movbe") { 244 HasMOVBE = true; 245 } else if (Feature == "+sgx") { 246 HasSGX = true; 247 } else if (Feature == "+cx8") { 248 HasCX8 = true; 249 } else if (Feature == "+cx16") { 250 HasCX16 = true; 251 } else if (Feature == "+fxsr") { 252 HasFXSR = true; 253 } else if (Feature == "+xsave") { 254 HasXSAVE = true; 255 } else if (Feature == "+xsaveopt") { 256 HasXSAVEOPT = true; 257 } else if (Feature == "+xsavec") { 258 HasXSAVEC = true; 259 } else if (Feature == "+xsaves") { 260 HasXSAVES = true; 261 } else if (Feature == "+mwaitx") { 262 HasMWAITX = true; 263 } else if (Feature == "+pku") { 264 HasPKU = true; 265 } else if (Feature == "+clflushopt") { 266 HasCLFLUSHOPT = true; 267 } else if (Feature == "+clwb") { 268 HasCLWB = true; 269 } else if (Feature == "+wbnoinvd") { 270 HasWBNOINVD = true; 271 } else if (Feature == "+prefetchwt1") { 272 HasPREFETCHWT1 = true; 273 } else if (Feature == "+clzero") { 274 HasCLZERO = true; 275 } else if (Feature == "+cldemote") { 276 HasCLDEMOTE = true; 277 } else if (Feature == "+rdpid") { 278 HasRDPID = true; 279 } else if (Feature == "+kl") { 280 HasKL = true; 281 } else if (Feature == "+widekl") { 282 HasWIDEKL = true; 283 } else if (Feature == "+retpoline-external-thunk") { 284 HasRetpolineExternalThunk = true; 285 } else if (Feature == "+sahf") { 286 HasLAHFSAHF = true; 287 } else if (Feature == "+waitpkg") { 288 HasWAITPKG = true; 289 } else if (Feature == "+movdiri") { 290 HasMOVDIRI = true; 291 } else if (Feature == "+movdir64b") { 292 HasMOVDIR64B = true; 293 } else if (Feature == "+pconfig") { 294 HasPCONFIG = true; 295 } else if (Feature == "+ptwrite") { 296 HasPTWRITE = true; 297 } else if (Feature == "+invpcid") { 298 HasINVPCID = true; 299 } else if (Feature == "+enqcmd") { 300 HasENQCMD = true; 301 } else if (Feature == "+hreset") { 302 HasHRESET = true; 303 } else if (Feature == "+amx-bf16") { 304 HasAMXBF16 = true; 305 } else if (Feature == "+amx-int8") { 306 HasAMXINT8 = true; 307 } else if (Feature == "+amx-tile") { 308 HasAMXTILE = true; 309 } else if (Feature == "+serialize") { 310 HasSERIALIZE = true; 311 } else if (Feature == "+tsxldtrk") { 312 HasTSXLDTRK = true; 313 } 314 315 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 316 .Case("+avx512f", AVX512F) 317 .Case("+avx2", AVX2) 318 .Case("+avx", AVX) 319 .Case("+sse4.2", SSE42) 320 .Case("+sse4.1", SSE41) 321 .Case("+ssse3", SSSE3) 322 .Case("+sse3", SSE3) 323 .Case("+sse2", SSE2) 324 .Case("+sse", SSE1) 325 .Default(NoSSE); 326 SSELevel = std::max(SSELevel, Level); 327 328 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 329 .Case("+3dnowa", AMD3DNowAthlon) 330 .Case("+3dnow", AMD3DNow) 331 .Case("+mmx", MMX) 332 .Default(NoMMX3DNow); 333 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 334 335 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 336 .Case("+xop", XOP) 337 .Case("+fma4", FMA4) 338 .Case("+sse4a", SSE4A) 339 .Default(NoXOP); 340 XOPLevel = std::max(XOPLevel, XLevel); 341 } 342 343 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 344 // matches the selected sse level. 345 if ((FPMath == FP_SSE && SSELevel < SSE1) || 346 (FPMath == FP_387 && SSELevel >= SSE1)) { 347 Diags.Report(diag::err_target_unsupported_fpmath) 348 << (FPMath == FP_SSE ? "sse" : "387"); 349 return false; 350 } 351 352 SimdDefaultAlign = 353 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 354 return true; 355 } 356 357 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 358 /// definitions for this particular subtarget. 359 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 360 MacroBuilder &Builder) const { 361 // Inline assembly supports X86 flag outputs. 362 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 363 364 std::string CodeModel = getTargetOpts().CodeModel; 365 if (CodeModel == "default") 366 CodeModel = "small"; 367 Builder.defineMacro("__code_model_" + CodeModel + "__"); 368 369 // Target identification. 370 if (getTriple().getArch() == llvm::Triple::x86_64) { 371 Builder.defineMacro("__amd64__"); 372 Builder.defineMacro("__amd64"); 373 Builder.defineMacro("__x86_64"); 374 Builder.defineMacro("__x86_64__"); 375 if (getTriple().getArchName() == "x86_64h") { 376 Builder.defineMacro("__x86_64h"); 377 Builder.defineMacro("__x86_64h__"); 378 } 379 } else { 380 DefineStd(Builder, "i386", Opts); 381 } 382 383 Builder.defineMacro("__SEG_GS"); 384 Builder.defineMacro("__SEG_FS"); 385 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 386 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 387 388 // Subtarget options. 389 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 390 // truly should be based on -mtune options. 391 using namespace llvm::X86; 392 switch (CPU) { 393 case CK_None: 394 break; 395 case CK_i386: 396 // The rest are coming from the i386 define above. 397 Builder.defineMacro("__tune_i386__"); 398 break; 399 case CK_i486: 400 case CK_WinChipC6: 401 case CK_WinChip2: 402 case CK_C3: 403 defineCPUMacros(Builder, "i486"); 404 break; 405 case CK_PentiumMMX: 406 Builder.defineMacro("__pentium_mmx__"); 407 Builder.defineMacro("__tune_pentium_mmx__"); 408 LLVM_FALLTHROUGH; 409 case CK_i586: 410 case CK_Pentium: 411 defineCPUMacros(Builder, "i586"); 412 defineCPUMacros(Builder, "pentium"); 413 break; 414 case CK_Pentium3: 415 case CK_PentiumM: 416 Builder.defineMacro("__tune_pentium3__"); 417 LLVM_FALLTHROUGH; 418 case CK_Pentium2: 419 case CK_C3_2: 420 Builder.defineMacro("__tune_pentium2__"); 421 LLVM_FALLTHROUGH; 422 case CK_PentiumPro: 423 case CK_i686: 424 defineCPUMacros(Builder, "i686"); 425 defineCPUMacros(Builder, "pentiumpro"); 426 break; 427 case CK_Pentium4: 428 defineCPUMacros(Builder, "pentium4"); 429 break; 430 case CK_Yonah: 431 case CK_Prescott: 432 case CK_Nocona: 433 defineCPUMacros(Builder, "nocona"); 434 break; 435 case CK_Core2: 436 case CK_Penryn: 437 defineCPUMacros(Builder, "core2"); 438 break; 439 case CK_Bonnell: 440 defineCPUMacros(Builder, "atom"); 441 break; 442 case CK_Silvermont: 443 defineCPUMacros(Builder, "slm"); 444 break; 445 case CK_Goldmont: 446 defineCPUMacros(Builder, "goldmont"); 447 break; 448 case CK_GoldmontPlus: 449 defineCPUMacros(Builder, "goldmont_plus"); 450 break; 451 case CK_Tremont: 452 defineCPUMacros(Builder, "tremont"); 453 break; 454 case CK_Nehalem: 455 case CK_Westmere: 456 case CK_SandyBridge: 457 case CK_IvyBridge: 458 case CK_Haswell: 459 case CK_Broadwell: 460 case CK_SkylakeClient: 461 case CK_SkylakeServer: 462 case CK_Cascadelake: 463 case CK_Cooperlake: 464 case CK_Cannonlake: 465 case CK_IcelakeClient: 466 case CK_IcelakeServer: 467 case CK_Tigerlake: 468 case CK_SapphireRapids: 469 // FIXME: Historically, we defined this legacy name, it would be nice to 470 // remove it at some point. We've never exposed fine-grained names for 471 // recent primary x86 CPUs, and we should keep it that way. 472 defineCPUMacros(Builder, "corei7"); 473 break; 474 case CK_KNL: 475 defineCPUMacros(Builder, "knl"); 476 break; 477 case CK_KNM: 478 break; 479 case CK_Lakemont: 480 defineCPUMacros(Builder, "i586", /*Tuning*/false); 481 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 482 Builder.defineMacro("__tune_lakemont__"); 483 break; 484 case CK_K6_2: 485 Builder.defineMacro("__k6_2__"); 486 Builder.defineMacro("__tune_k6_2__"); 487 LLVM_FALLTHROUGH; 488 case CK_K6_3: 489 if (CPU != CK_K6_2) { // In case of fallthrough 490 // FIXME: GCC may be enabling these in cases where some other k6 491 // architecture is specified but -m3dnow is explicitly provided. The 492 // exact semantics need to be determined and emulated here. 493 Builder.defineMacro("__k6_3__"); 494 Builder.defineMacro("__tune_k6_3__"); 495 } 496 LLVM_FALLTHROUGH; 497 case CK_K6: 498 defineCPUMacros(Builder, "k6"); 499 break; 500 case CK_Athlon: 501 case CK_AthlonXP: 502 defineCPUMacros(Builder, "athlon"); 503 if (SSELevel != NoSSE) { 504 Builder.defineMacro("__athlon_sse__"); 505 Builder.defineMacro("__tune_athlon_sse__"); 506 } 507 break; 508 case CK_K8: 509 case CK_K8SSE3: 510 case CK_x86_64: 511 case CK_x86_64_v2: 512 case CK_x86_64_v3: 513 case CK_x86_64_v4: 514 defineCPUMacros(Builder, "k8"); 515 break; 516 case CK_AMDFAM10: 517 defineCPUMacros(Builder, "amdfam10"); 518 break; 519 case CK_BTVER1: 520 defineCPUMacros(Builder, "btver1"); 521 break; 522 case CK_BTVER2: 523 defineCPUMacros(Builder, "btver2"); 524 break; 525 case CK_BDVER1: 526 defineCPUMacros(Builder, "bdver1"); 527 break; 528 case CK_BDVER2: 529 defineCPUMacros(Builder, "bdver2"); 530 break; 531 case CK_BDVER3: 532 defineCPUMacros(Builder, "bdver3"); 533 break; 534 case CK_BDVER4: 535 defineCPUMacros(Builder, "bdver4"); 536 break; 537 case CK_ZNVER1: 538 defineCPUMacros(Builder, "znver1"); 539 break; 540 case CK_ZNVER2: 541 defineCPUMacros(Builder, "znver2"); 542 break; 543 case CK_Geode: 544 defineCPUMacros(Builder, "geode"); 545 break; 546 } 547 548 // Target properties. 549 Builder.defineMacro("__REGISTER_PREFIX__", ""); 550 551 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 552 // functions in glibc header files that use FP Stack inline asm which the 553 // backend can't deal with (PR879). 554 Builder.defineMacro("__NO_MATH_INLINES"); 555 556 if (HasAES) 557 Builder.defineMacro("__AES__"); 558 559 if (HasVAES) 560 Builder.defineMacro("__VAES__"); 561 562 if (HasPCLMUL) 563 Builder.defineMacro("__PCLMUL__"); 564 565 if (HasVPCLMULQDQ) 566 Builder.defineMacro("__VPCLMULQDQ__"); 567 568 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, 569 // the feature flag only applies to 64-bit mode. 570 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86) 571 Builder.defineMacro("__LAHF_SAHF__"); 572 573 if (HasLZCNT) 574 Builder.defineMacro("__LZCNT__"); 575 576 if (HasRDRND) 577 Builder.defineMacro("__RDRND__"); 578 579 if (HasFSGSBASE) 580 Builder.defineMacro("__FSGSBASE__"); 581 582 if (HasBMI) 583 Builder.defineMacro("__BMI__"); 584 585 if (HasBMI2) 586 Builder.defineMacro("__BMI2__"); 587 588 if (HasPOPCNT) 589 Builder.defineMacro("__POPCNT__"); 590 591 if (HasRTM) 592 Builder.defineMacro("__RTM__"); 593 594 if (HasPRFCHW) 595 Builder.defineMacro("__PRFCHW__"); 596 597 if (HasRDSEED) 598 Builder.defineMacro("__RDSEED__"); 599 600 if (HasADX) 601 Builder.defineMacro("__ADX__"); 602 603 if (HasTBM) 604 Builder.defineMacro("__TBM__"); 605 606 if (HasLWP) 607 Builder.defineMacro("__LWP__"); 608 609 if (HasMWAITX) 610 Builder.defineMacro("__MWAITX__"); 611 612 if (HasMOVBE) 613 Builder.defineMacro("__MOVBE__"); 614 615 switch (XOPLevel) { 616 case XOP: 617 Builder.defineMacro("__XOP__"); 618 LLVM_FALLTHROUGH; 619 case FMA4: 620 Builder.defineMacro("__FMA4__"); 621 LLVM_FALLTHROUGH; 622 case SSE4A: 623 Builder.defineMacro("__SSE4A__"); 624 LLVM_FALLTHROUGH; 625 case NoXOP: 626 break; 627 } 628 629 if (HasFMA) 630 Builder.defineMacro("__FMA__"); 631 632 if (HasF16C) 633 Builder.defineMacro("__F16C__"); 634 635 if (HasGFNI) 636 Builder.defineMacro("__GFNI__"); 637 638 if (HasAVX512CD) 639 Builder.defineMacro("__AVX512CD__"); 640 if (HasAVX512VPOPCNTDQ) 641 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 642 if (HasAVX512VNNI) 643 Builder.defineMacro("__AVX512VNNI__"); 644 if (HasAVX512BF16) 645 Builder.defineMacro("__AVX512BF16__"); 646 if (HasAVX512ER) 647 Builder.defineMacro("__AVX512ER__"); 648 if (HasAVX512PF) 649 Builder.defineMacro("__AVX512PF__"); 650 if (HasAVX512DQ) 651 Builder.defineMacro("__AVX512DQ__"); 652 if (HasAVX512BITALG) 653 Builder.defineMacro("__AVX512BITALG__"); 654 if (HasAVX512BW) 655 Builder.defineMacro("__AVX512BW__"); 656 if (HasAVX512VL) 657 Builder.defineMacro("__AVX512VL__"); 658 if (HasAVX512VBMI) 659 Builder.defineMacro("__AVX512VBMI__"); 660 if (HasAVX512VBMI2) 661 Builder.defineMacro("__AVX512VBMI2__"); 662 if (HasAVX512IFMA) 663 Builder.defineMacro("__AVX512IFMA__"); 664 if (HasAVX512VP2INTERSECT) 665 Builder.defineMacro("__AVX512VP2INTERSECT__"); 666 if (HasSHA) 667 Builder.defineMacro("__SHA__"); 668 669 if (HasFXSR) 670 Builder.defineMacro("__FXSR__"); 671 if (HasXSAVE) 672 Builder.defineMacro("__XSAVE__"); 673 if (HasXSAVEOPT) 674 Builder.defineMacro("__XSAVEOPT__"); 675 if (HasXSAVEC) 676 Builder.defineMacro("__XSAVEC__"); 677 if (HasXSAVES) 678 Builder.defineMacro("__XSAVES__"); 679 if (HasPKU) 680 Builder.defineMacro("__PKU__"); 681 if (HasCLFLUSHOPT) 682 Builder.defineMacro("__CLFLUSHOPT__"); 683 if (HasCLWB) 684 Builder.defineMacro("__CLWB__"); 685 if (HasWBNOINVD) 686 Builder.defineMacro("__WBNOINVD__"); 687 if (HasSHSTK) 688 Builder.defineMacro("__SHSTK__"); 689 if (HasSGX) 690 Builder.defineMacro("__SGX__"); 691 if (HasPREFETCHWT1) 692 Builder.defineMacro("__PREFETCHWT1__"); 693 if (HasCLZERO) 694 Builder.defineMacro("__CLZERO__"); 695 if (HasKL) 696 Builder.defineMacro("__KL__"); 697 if (HasWIDEKL) 698 Builder.defineMacro("__WIDEKL__"); 699 if (HasRDPID) 700 Builder.defineMacro("__RDPID__"); 701 if (HasCLDEMOTE) 702 Builder.defineMacro("__CLDEMOTE__"); 703 if (HasWAITPKG) 704 Builder.defineMacro("__WAITPKG__"); 705 if (HasMOVDIRI) 706 Builder.defineMacro("__MOVDIRI__"); 707 if (HasMOVDIR64B) 708 Builder.defineMacro("__MOVDIR64B__"); 709 if (HasPCONFIG) 710 Builder.defineMacro("__PCONFIG__"); 711 if (HasPTWRITE) 712 Builder.defineMacro("__PTWRITE__"); 713 if (HasINVPCID) 714 Builder.defineMacro("__INVPCID__"); 715 if (HasENQCMD) 716 Builder.defineMacro("__ENQCMD__"); 717 if (HasHRESET) 718 Builder.defineMacro("__HRESET__"); 719 if (HasAMXTILE) 720 Builder.defineMacro("__AMXTILE__"); 721 if (HasAMXINT8) 722 Builder.defineMacro("__AMXINT8__"); 723 if (HasAMXBF16) 724 Builder.defineMacro("__AMXBF16__"); 725 if (HasSERIALIZE) 726 Builder.defineMacro("__SERIALIZE__"); 727 if (HasTSXLDTRK) 728 Builder.defineMacro("__TSXLDTRK__"); 729 730 // Each case falls through to the previous one here. 731 switch (SSELevel) { 732 case AVX512F: 733 Builder.defineMacro("__AVX512F__"); 734 LLVM_FALLTHROUGH; 735 case AVX2: 736 Builder.defineMacro("__AVX2__"); 737 LLVM_FALLTHROUGH; 738 case AVX: 739 Builder.defineMacro("__AVX__"); 740 LLVM_FALLTHROUGH; 741 case SSE42: 742 Builder.defineMacro("__SSE4_2__"); 743 LLVM_FALLTHROUGH; 744 case SSE41: 745 Builder.defineMacro("__SSE4_1__"); 746 LLVM_FALLTHROUGH; 747 case SSSE3: 748 Builder.defineMacro("__SSSE3__"); 749 LLVM_FALLTHROUGH; 750 case SSE3: 751 Builder.defineMacro("__SSE3__"); 752 LLVM_FALLTHROUGH; 753 case SSE2: 754 Builder.defineMacro("__SSE2__"); 755 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 756 LLVM_FALLTHROUGH; 757 case SSE1: 758 Builder.defineMacro("__SSE__"); 759 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 760 LLVM_FALLTHROUGH; 761 case NoSSE: 762 break; 763 } 764 765 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 766 switch (SSELevel) { 767 case AVX512F: 768 case AVX2: 769 case AVX: 770 case SSE42: 771 case SSE41: 772 case SSSE3: 773 case SSE3: 774 case SSE2: 775 Builder.defineMacro("_M_IX86_FP", Twine(2)); 776 break; 777 case SSE1: 778 Builder.defineMacro("_M_IX86_FP", Twine(1)); 779 break; 780 default: 781 Builder.defineMacro("_M_IX86_FP", Twine(0)); 782 break; 783 } 784 } 785 786 // Each case falls through to the previous one here. 787 switch (MMX3DNowLevel) { 788 case AMD3DNowAthlon: 789 Builder.defineMacro("__3dNOW_A__"); 790 LLVM_FALLTHROUGH; 791 case AMD3DNow: 792 Builder.defineMacro("__3dNOW__"); 793 LLVM_FALLTHROUGH; 794 case MMX: 795 Builder.defineMacro("__MMX__"); 796 LLVM_FALLTHROUGH; 797 case NoMMX3DNow: 798 break; 799 } 800 801 if (CPU >= CK_i486 || CPU == CK_None) { 802 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 803 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 804 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 805 } 806 if (HasCX8) 807 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 808 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 809 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 810 811 if (HasFloat128) 812 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 813 } 814 815 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 816 return llvm::StringSwitch<bool>(Name) 817 .Case("3dnow", true) 818 .Case("3dnowa", true) 819 .Case("adx", true) 820 .Case("aes", true) 821 .Case("amx-bf16", true) 822 .Case("amx-int8", true) 823 .Case("amx-tile", true) 824 .Case("avx", true) 825 .Case("avx2", true) 826 .Case("avx512f", true) 827 .Case("avx512cd", true) 828 .Case("avx512vpopcntdq", true) 829 .Case("avx512vnni", true) 830 .Case("avx512bf16", true) 831 .Case("avx512er", true) 832 .Case("avx512pf", true) 833 .Case("avx512dq", true) 834 .Case("avx512bitalg", true) 835 .Case("avx512bw", true) 836 .Case("avx512vl", true) 837 .Case("avx512vbmi", true) 838 .Case("avx512vbmi2", true) 839 .Case("avx512ifma", true) 840 .Case("avx512vp2intersect", true) 841 .Case("bmi", true) 842 .Case("bmi2", true) 843 .Case("cldemote", true) 844 .Case("clflushopt", true) 845 .Case("clwb", true) 846 .Case("clzero", true) 847 .Case("cx16", true) 848 .Case("enqcmd", true) 849 .Case("f16c", true) 850 .Case("fma", true) 851 .Case("fma4", true) 852 .Case("fsgsbase", true) 853 .Case("fxsr", true) 854 .Case("gfni", true) 855 .Case("hreset", true) 856 .Case("invpcid", true) 857 .Case("kl", true) 858 .Case("widekl", true) 859 .Case("lwp", true) 860 .Case("lzcnt", true) 861 .Case("mmx", true) 862 .Case("movbe", true) 863 .Case("movdiri", true) 864 .Case("movdir64b", true) 865 .Case("mwaitx", true) 866 .Case("pclmul", true) 867 .Case("pconfig", true) 868 .Case("pku", true) 869 .Case("popcnt", true) 870 .Case("prefetchwt1", true) 871 .Case("prfchw", true) 872 .Case("ptwrite", true) 873 .Case("rdpid", true) 874 .Case("rdrnd", true) 875 .Case("rdseed", true) 876 .Case("rtm", true) 877 .Case("sahf", true) 878 .Case("serialize", true) 879 .Case("sgx", true) 880 .Case("sha", true) 881 .Case("shstk", true) 882 .Case("sse", true) 883 .Case("sse2", true) 884 .Case("sse3", true) 885 .Case("ssse3", true) 886 .Case("sse4", true) 887 .Case("sse4.1", true) 888 .Case("sse4.2", true) 889 .Case("sse4a", true) 890 .Case("tbm", true) 891 .Case("tsxldtrk", true) 892 .Case("vaes", true) 893 .Case("vpclmulqdq", true) 894 .Case("wbnoinvd", true) 895 .Case("waitpkg", true) 896 .Case("x87", true) 897 .Case("xop", true) 898 .Case("xsave", true) 899 .Case("xsavec", true) 900 .Case("xsaves", true) 901 .Case("xsaveopt", true) 902 .Default(false); 903 } 904 905 bool X86TargetInfo::hasFeature(StringRef Feature) const { 906 return llvm::StringSwitch<bool>(Feature) 907 .Case("adx", HasADX) 908 .Case("aes", HasAES) 909 .Case("amx-bf16", HasAMXBF16) 910 .Case("amx-int8", HasAMXINT8) 911 .Case("amx-tile", HasAMXTILE) 912 .Case("avx", SSELevel >= AVX) 913 .Case("avx2", SSELevel >= AVX2) 914 .Case("avx512f", SSELevel >= AVX512F) 915 .Case("avx512cd", HasAVX512CD) 916 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 917 .Case("avx512vnni", HasAVX512VNNI) 918 .Case("avx512bf16", HasAVX512BF16) 919 .Case("avx512er", HasAVX512ER) 920 .Case("avx512pf", HasAVX512PF) 921 .Case("avx512dq", HasAVX512DQ) 922 .Case("avx512bitalg", HasAVX512BITALG) 923 .Case("avx512bw", HasAVX512BW) 924 .Case("avx512vl", HasAVX512VL) 925 .Case("avx512vbmi", HasAVX512VBMI) 926 .Case("avx512vbmi2", HasAVX512VBMI2) 927 .Case("avx512ifma", HasAVX512IFMA) 928 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 929 .Case("bmi", HasBMI) 930 .Case("bmi2", HasBMI2) 931 .Case("cldemote", HasCLDEMOTE) 932 .Case("clflushopt", HasCLFLUSHOPT) 933 .Case("clwb", HasCLWB) 934 .Case("clzero", HasCLZERO) 935 .Case("cx8", HasCX8) 936 .Case("cx16", HasCX16) 937 .Case("enqcmd", HasENQCMD) 938 .Case("f16c", HasF16C) 939 .Case("fma", HasFMA) 940 .Case("fma4", XOPLevel >= FMA4) 941 .Case("fsgsbase", HasFSGSBASE) 942 .Case("fxsr", HasFXSR) 943 .Case("gfni", HasGFNI) 944 .Case("hreset", HasHRESET) 945 .Case("invpcid", HasINVPCID) 946 .Case("kl", HasKL) 947 .Case("widekl", HasWIDEKL) 948 .Case("lwp", HasLWP) 949 .Case("lzcnt", HasLZCNT) 950 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 951 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 952 .Case("mmx", MMX3DNowLevel >= MMX) 953 .Case("movbe", HasMOVBE) 954 .Case("movdiri", HasMOVDIRI) 955 .Case("movdir64b", HasMOVDIR64B) 956 .Case("mwaitx", HasMWAITX) 957 .Case("pclmul", HasPCLMUL) 958 .Case("pconfig", HasPCONFIG) 959 .Case("pku", HasPKU) 960 .Case("popcnt", HasPOPCNT) 961 .Case("prefetchwt1", HasPREFETCHWT1) 962 .Case("prfchw", HasPRFCHW) 963 .Case("ptwrite", HasPTWRITE) 964 .Case("rdpid", HasRDPID) 965 .Case("rdrnd", HasRDRND) 966 .Case("rdseed", HasRDSEED) 967 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 968 .Case("rtm", HasRTM) 969 .Case("sahf", HasLAHFSAHF) 970 .Case("serialize", HasSERIALIZE) 971 .Case("sgx", HasSGX) 972 .Case("sha", HasSHA) 973 .Case("shstk", HasSHSTK) 974 .Case("sse", SSELevel >= SSE1) 975 .Case("sse2", SSELevel >= SSE2) 976 .Case("sse3", SSELevel >= SSE3) 977 .Case("ssse3", SSELevel >= SSSE3) 978 .Case("sse4.1", SSELevel >= SSE41) 979 .Case("sse4.2", SSELevel >= SSE42) 980 .Case("sse4a", XOPLevel >= SSE4A) 981 .Case("tbm", HasTBM) 982 .Case("tsxldtrk", HasTSXLDTRK) 983 .Case("vaes", HasVAES) 984 .Case("vpclmulqdq", HasVPCLMULQDQ) 985 .Case("wbnoinvd", HasWBNOINVD) 986 .Case("waitpkg", HasWAITPKG) 987 .Case("x86", true) 988 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 989 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 990 .Case("xop", XOPLevel >= XOP) 991 .Case("xsave", HasXSAVE) 992 .Case("xsavec", HasXSAVEC) 993 .Case("xsaves", HasXSAVES) 994 .Case("xsaveopt", HasXSAVEOPT) 995 .Default(false); 996 } 997 998 // We can't use a generic validation scheme for the features accepted here 999 // versus subtarget features accepted in the target attribute because the 1000 // bitfield structure that's initialized in the runtime only supports the 1001 // below currently rather than the full range of subtarget features. (See 1002 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1003 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1004 return llvm::StringSwitch<bool>(FeatureStr) 1005 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, true) 1006 #include "llvm/Support/X86TargetParser.def" 1007 .Default(false); 1008 } 1009 1010 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1011 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1012 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, llvm::X86::FEATURE_##ENUM) 1013 #include "llvm/Support/X86TargetParser.def" 1014 ; 1015 // Note, this function should only be used after ensuring the value is 1016 // correct, so it asserts if the value is out of range. 1017 } 1018 1019 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1020 enum class FeatPriority { 1021 #define FEATURE(FEAT) FEAT, 1022 #include "clang/Basic/X86Target.def" 1023 }; 1024 switch (Feat) { 1025 #define FEATURE(FEAT) \ 1026 case llvm::X86::FEAT: \ 1027 return static_cast<unsigned>(FeatPriority::FEAT); 1028 #include "clang/Basic/X86Target.def" 1029 default: 1030 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1031 } 1032 } 1033 1034 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1035 // Valid CPUs have a 'key feature' that compares just better than its key 1036 // feature. 1037 using namespace llvm::X86; 1038 CPUKind Kind = parseArchX86(Name); 1039 if (Kind != CK_None) { 1040 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1041 return (getFeaturePriority(KeyFeature) << 1) + 1; 1042 } 1043 1044 // Now we know we have a feature, so get its priority and shift it a few so 1045 // that we have sufficient room for the CPUs (above). 1046 return getFeaturePriority(getFeature(Name)) << 1; 1047 } 1048 1049 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1050 return llvm::StringSwitch<bool>(Name) 1051 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1052 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1053 #include "clang/Basic/X86Target.def" 1054 .Default(false); 1055 } 1056 1057 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1058 return llvm::StringSwitch<StringRef>(Name) 1059 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1060 #include "clang/Basic/X86Target.def" 1061 .Default(Name); 1062 } 1063 1064 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1065 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1066 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1067 #include "clang/Basic/X86Target.def" 1068 .Default(0); 1069 } 1070 1071 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1072 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1073 StringRef WholeList = 1074 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1075 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1076 #include "clang/Basic/X86Target.def" 1077 .Default(""); 1078 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1079 } 1080 1081 // We can't use a generic validation scheme for the cpus accepted here 1082 // versus subtarget cpus accepted in the target attribute because the 1083 // variables intitialized by the runtime only support the below currently 1084 // rather than the full range of cpus. 1085 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1086 return llvm::StringSwitch<bool>(FeatureStr) 1087 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1088 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1089 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1090 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1091 #include "llvm/Support/X86TargetParser.def" 1092 .Default(false); 1093 } 1094 1095 static unsigned matchAsmCCConstraint(const char *&Name) { 1096 auto RV = llvm::StringSwitch<unsigned>(Name) 1097 .Case("@cca", 4) 1098 .Case("@ccae", 5) 1099 .Case("@ccb", 4) 1100 .Case("@ccbe", 5) 1101 .Case("@ccc", 4) 1102 .Case("@cce", 4) 1103 .Case("@ccz", 4) 1104 .Case("@ccg", 4) 1105 .Case("@ccge", 5) 1106 .Case("@ccl", 4) 1107 .Case("@ccle", 5) 1108 .Case("@ccna", 5) 1109 .Case("@ccnae", 6) 1110 .Case("@ccnb", 5) 1111 .Case("@ccnbe", 6) 1112 .Case("@ccnc", 5) 1113 .Case("@ccne", 5) 1114 .Case("@ccnz", 5) 1115 .Case("@ccng", 5) 1116 .Case("@ccnge", 6) 1117 .Case("@ccnl", 5) 1118 .Case("@ccnle", 6) 1119 .Case("@ccno", 5) 1120 .Case("@ccnp", 5) 1121 .Case("@ccns", 5) 1122 .Case("@cco", 4) 1123 .Case("@ccp", 4) 1124 .Case("@ccs", 4) 1125 .Default(0); 1126 return RV; 1127 } 1128 1129 bool X86TargetInfo::validateAsmConstraint( 1130 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1131 switch (*Name) { 1132 default: 1133 return false; 1134 // Constant constraints. 1135 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1136 // instructions. 1137 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1138 // x86_64 instructions. 1139 case 's': 1140 Info.setRequiresImmediate(); 1141 return true; 1142 case 'I': 1143 Info.setRequiresImmediate(0, 31); 1144 return true; 1145 case 'J': 1146 Info.setRequiresImmediate(0, 63); 1147 return true; 1148 case 'K': 1149 Info.setRequiresImmediate(-128, 127); 1150 return true; 1151 case 'L': 1152 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1153 return true; 1154 case 'M': 1155 Info.setRequiresImmediate(0, 3); 1156 return true; 1157 case 'N': 1158 Info.setRequiresImmediate(0, 255); 1159 return true; 1160 case 'O': 1161 Info.setRequiresImmediate(0, 127); 1162 return true; 1163 // Register constraints. 1164 case 'Y': // 'Y' is the first character for several 2-character constraints. 1165 // Shift the pointer to the second character of the constraint. 1166 Name++; 1167 switch (*Name) { 1168 default: 1169 return false; 1170 case 'z': // First SSE register. 1171 case '2': 1172 case 't': // Any SSE register, when SSE2 is enabled. 1173 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1174 case 'm': // Any MMX register, when inter-unit moves enabled. 1175 case 'k': // AVX512 arch mask registers: k1-k7. 1176 Info.setAllowsRegister(); 1177 return true; 1178 } 1179 case 'f': // Any x87 floating point stack register. 1180 // Constraint 'f' cannot be used for output operands. 1181 if (Info.ConstraintStr[0] == '=') 1182 return false; 1183 Info.setAllowsRegister(); 1184 return true; 1185 case 'a': // eax. 1186 case 'b': // ebx. 1187 case 'c': // ecx. 1188 case 'd': // edx. 1189 case 'S': // esi. 1190 case 'D': // edi. 1191 case 'A': // edx:eax. 1192 case 't': // Top of floating point stack. 1193 case 'u': // Second from top of floating point stack. 1194 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1195 case 'y': // Any MMX register. 1196 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1197 case 'x': // Any SSE register. 1198 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1199 // for intermideate k reg operations). 1200 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1201 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1202 case 'l': // "Index" registers: any general register that can be used as an 1203 // index in a base+index memory access. 1204 Info.setAllowsRegister(); 1205 return true; 1206 // Floating point constant constraints. 1207 case 'C': // SSE floating point constant. 1208 case 'G': // x87 floating point constant. 1209 return true; 1210 case '@': 1211 // CC condition changes. 1212 if (auto Len = matchAsmCCConstraint(Name)) { 1213 Name += Len - 1; 1214 Info.setAllowsRegister(); 1215 return true; 1216 } 1217 return false; 1218 } 1219 } 1220 1221 // Below is based on the following information: 1222 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1223 // | Processor Name | Cache Line Size (Bytes) | Source | 1224 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1225 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1226 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1227 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1228 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1229 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1230 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1231 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1232 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1233 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1234 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1235 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1236 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1237 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1238 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1239 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1240 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1241 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1242 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1243 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1244 using namespace llvm::X86; 1245 switch (CPU) { 1246 // i386 1247 case CK_i386: 1248 // i486 1249 case CK_i486: 1250 case CK_WinChipC6: 1251 case CK_WinChip2: 1252 case CK_C3: 1253 // Lakemont 1254 case CK_Lakemont: 1255 return 16; 1256 1257 // i586 1258 case CK_i586: 1259 case CK_Pentium: 1260 case CK_PentiumMMX: 1261 // i686 1262 case CK_PentiumPro: 1263 case CK_i686: 1264 case CK_Pentium2: 1265 case CK_Pentium3: 1266 case CK_PentiumM: 1267 case CK_C3_2: 1268 // K6 1269 case CK_K6: 1270 case CK_K6_2: 1271 case CK_K6_3: 1272 // Geode 1273 case CK_Geode: 1274 return 32; 1275 1276 // Netburst 1277 case CK_Pentium4: 1278 case CK_Prescott: 1279 case CK_Nocona: 1280 // Atom 1281 case CK_Bonnell: 1282 case CK_Silvermont: 1283 case CK_Goldmont: 1284 case CK_GoldmontPlus: 1285 case CK_Tremont: 1286 1287 case CK_Westmere: 1288 case CK_SandyBridge: 1289 case CK_IvyBridge: 1290 case CK_Haswell: 1291 case CK_Broadwell: 1292 case CK_SkylakeClient: 1293 case CK_SkylakeServer: 1294 case CK_Cascadelake: 1295 case CK_Nehalem: 1296 case CK_Cooperlake: 1297 case CK_Cannonlake: 1298 case CK_Tigerlake: 1299 case CK_SapphireRapids: 1300 case CK_IcelakeClient: 1301 case CK_IcelakeServer: 1302 case CK_KNL: 1303 case CK_KNM: 1304 // K7 1305 case CK_Athlon: 1306 case CK_AthlonXP: 1307 // K8 1308 case CK_K8: 1309 case CK_K8SSE3: 1310 case CK_AMDFAM10: 1311 // Bobcat 1312 case CK_BTVER1: 1313 case CK_BTVER2: 1314 // Bulldozer 1315 case CK_BDVER1: 1316 case CK_BDVER2: 1317 case CK_BDVER3: 1318 case CK_BDVER4: 1319 // Zen 1320 case CK_ZNVER1: 1321 case CK_ZNVER2: 1322 // Deprecated 1323 case CK_x86_64: 1324 case CK_x86_64_v2: 1325 case CK_x86_64_v3: 1326 case CK_x86_64_v4: 1327 case CK_Yonah: 1328 case CK_Penryn: 1329 case CK_Core2: 1330 return 64; 1331 1332 // The following currently have unknown cache line sizes (but they are probably all 64): 1333 // Core 1334 case CK_None: 1335 return None; 1336 } 1337 llvm_unreachable("Unknown CPU kind"); 1338 } 1339 1340 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1341 StringRef Constraint, 1342 unsigned Size) const { 1343 // Strip off constraint modifiers. 1344 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1345 Constraint = Constraint.substr(1); 1346 1347 return validateOperandSize(FeatureMap, Constraint, Size); 1348 } 1349 1350 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1351 StringRef Constraint, 1352 unsigned Size) const { 1353 return validateOperandSize(FeatureMap, Constraint, Size); 1354 } 1355 1356 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1357 StringRef Constraint, 1358 unsigned Size) const { 1359 switch (Constraint[0]) { 1360 default: 1361 break; 1362 case 'k': 1363 // Registers k0-k7 (AVX512) size limit is 64 bit. 1364 case 'y': 1365 return Size <= 64; 1366 case 'f': 1367 case 't': 1368 case 'u': 1369 return Size <= 128; 1370 case 'Y': 1371 // 'Y' is the first character for several 2-character constraints. 1372 switch (Constraint[1]) { 1373 default: 1374 return false; 1375 case 'm': 1376 // 'Ym' is synonymous with 'y'. 1377 case 'k': 1378 return Size <= 64; 1379 case 'z': 1380 // XMM0/YMM/ZMM0 1381 if (FeatureMap.lookup("avx512f")) 1382 // ZMM0 can be used if target supports AVX512F. 1383 return Size <= 512U; 1384 else if (FeatureMap.lookup("avx")) 1385 // YMM0 can be used if target supports AVX. 1386 return Size <= 256U; 1387 else if (FeatureMap.lookup("sse")) 1388 return Size <= 128U; 1389 return false; 1390 case 'i': 1391 case 't': 1392 case '2': 1393 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1394 if (SSELevel < SSE2) 1395 return false; 1396 break; 1397 } 1398 break; 1399 case 'v': 1400 case 'x': 1401 if (FeatureMap.lookup("avx512f")) 1402 // 512-bit zmm registers can be used if target supports AVX512F. 1403 return Size <= 512U; 1404 else if (FeatureMap.lookup("avx")) 1405 // 256-bit ymm registers can be used if target supports AVX. 1406 return Size <= 256U; 1407 return Size <= 128U; 1408 1409 } 1410 1411 return true; 1412 } 1413 1414 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1415 switch (*Constraint) { 1416 case '@': 1417 if (auto Len = matchAsmCCConstraint(Constraint)) { 1418 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1419 Constraint += Len - 1; 1420 return Converted; 1421 } 1422 return std::string(1, *Constraint); 1423 case 'a': 1424 return std::string("{ax}"); 1425 case 'b': 1426 return std::string("{bx}"); 1427 case 'c': 1428 return std::string("{cx}"); 1429 case 'd': 1430 return std::string("{dx}"); 1431 case 'S': 1432 return std::string("{si}"); 1433 case 'D': 1434 return std::string("{di}"); 1435 case 'p': // address 1436 return std::string("im"); 1437 case 't': // top of floating point stack. 1438 return std::string("{st}"); 1439 case 'u': // second from top of floating point stack. 1440 return std::string("{st(1)}"); // second from top of floating point stack. 1441 case 'Y': 1442 switch (Constraint[1]) { 1443 default: 1444 // Break from inner switch and fall through (copy single char), 1445 // continue parsing after copying the current constraint into 1446 // the return string. 1447 break; 1448 case 'k': 1449 case 'm': 1450 case 'i': 1451 case 't': 1452 case 'z': 1453 case '2': 1454 // "^" hints llvm that this is a 2 letter constraint. 1455 // "Constraint++" is used to promote the string iterator 1456 // to the next constraint. 1457 return std::string("^") + std::string(Constraint++, 2); 1458 } 1459 LLVM_FALLTHROUGH; 1460 default: 1461 return std::string(1, *Constraint); 1462 } 1463 } 1464 1465 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1466 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1467 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1468 } 1469 1470 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1471 llvm::X86::fillValidTuneCPUList(Values); 1472 } 1473 1474 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1475 return llvm::makeArrayRef(GCCRegNames); 1476 } 1477 1478 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1479 return llvm::makeArrayRef(AddlRegNames); 1480 } 1481 1482 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1483 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1484 Builtin::FirstTSBuiltin + 1); 1485 } 1486 1487 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1488 return llvm::makeArrayRef(BuiltinInfoX86, 1489 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1490 } 1491