1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements X86 TargetInfo objects. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86.h" 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Diagnostic.h" 17 #include "clang/Basic/TargetBuiltins.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 21 namespace clang { 22 namespace targets { 23 24 const Builtin::Info BuiltinInfoX86[] = { 25 #define BUILTIN(ID, TYPE, ATTRS) \ 26 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 27 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 29 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 30 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 31 #include "clang/Basic/BuiltinsX86.def" 32 33 #define BUILTIN(ID, TYPE, ATTRS) \ 34 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 35 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 37 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 38 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 39 #include "clang/Basic/BuiltinsX86_64.def" 40 }; 41 42 static const char *const GCCRegNames[] = { 43 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 44 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 45 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 46 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 47 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 48 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 49 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 50 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 51 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 52 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 53 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 54 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 55 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 56 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 57 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 58 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 59 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 60 "k2", "k3", "k4", "k5", "k6", "k7", 61 "cr0", "cr2", "cr3", "cr4", "cr8", 62 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 63 }; 64 65 const TargetInfo::AddlRegName AddlRegNames[] = { 66 {{"al", "ah", "eax", "rax"}, 0}, 67 {{"bl", "bh", "ebx", "rbx"}, 3}, 68 {{"cl", "ch", "ecx", "rcx"}, 2}, 69 {{"dl", "dh", "edx", "rdx"}, 1}, 70 {{"esi", "rsi"}, 4}, 71 {{"edi", "rdi"}, 5}, 72 {{"esp", "rsp"}, 7}, 73 {{"ebp", "rbp"}, 6}, 74 {{"r8d", "r8w", "r8b"}, 38}, 75 {{"r9d", "r9w", "r9b"}, 39}, 76 {{"r10d", "r10w", "r10b"}, 40}, 77 {{"r11d", "r11w", "r11b"}, 41}, 78 {{"r12d", "r12w", "r12b"}, 42}, 79 {{"r13d", "r13w", "r13b"}, 43}, 80 {{"r14d", "r14w", "r14b"}, 44}, 81 {{"r15d", "r15w", "r15b"}, 45}, 82 }; 83 84 } // namespace targets 85 } // namespace clang 86 87 using namespace clang; 88 using namespace clang::targets; 89 90 bool X86TargetInfo::setFPMath(StringRef Name) { 91 if (Name == "387") { 92 FPMath = FP_387; 93 return true; 94 } 95 if (Name == "sse") { 96 FPMath = FP_SSE; 97 return true; 98 } 99 return false; 100 } 101 102 bool X86TargetInfo::initFeatureMap( 103 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 104 const std::vector<std::string> &FeaturesVec) const { 105 // FIXME: This *really* should not be here. 106 // X86_64 always has SSE2. 107 if (getTriple().getArch() == llvm::Triple::x86_64) 108 setFeatureEnabledImpl(Features, "sse2", true); 109 110 const CPUKind Kind = getCPUKind(CPU); 111 112 // Enable X87 for all X86 processors but Lakemont. 113 if (Kind != CK_Lakemont) 114 setFeatureEnabledImpl(Features, "x87", true); 115 116 switch (Kind) { 117 case CK_Generic: 118 case CK_i386: 119 case CK_i486: 120 case CK_i586: 121 case CK_Pentium: 122 case CK_PentiumPro: 123 case CK_Lakemont: 124 break; 125 126 case CK_PentiumMMX: 127 case CK_Pentium2: 128 case CK_K6: 129 case CK_WinChipC6: 130 setFeatureEnabledImpl(Features, "mmx", true); 131 break; 132 133 case CK_Cannonlake: 134 setFeatureEnabledImpl(Features, "avx512ifma", true); 135 setFeatureEnabledImpl(Features, "avx512vbmi", true); 136 setFeatureEnabledImpl(Features, "sha", true); 137 LLVM_FALLTHROUGH; 138 case CK_SkylakeServer: 139 setFeatureEnabledImpl(Features, "avx512f", true); 140 setFeatureEnabledImpl(Features, "avx512cd", true); 141 setFeatureEnabledImpl(Features, "avx512dq", true); 142 setFeatureEnabledImpl(Features, "avx512bw", true); 143 setFeatureEnabledImpl(Features, "avx512vl", true); 144 setFeatureEnabledImpl(Features, "pku", true); 145 setFeatureEnabledImpl(Features, "clwb", true); 146 LLVM_FALLTHROUGH; 147 case CK_SkylakeClient: 148 setFeatureEnabledImpl(Features, "xsavec", true); 149 setFeatureEnabledImpl(Features, "xsaves", true); 150 setFeatureEnabledImpl(Features, "mpx", true); 151 setFeatureEnabledImpl(Features, "sgx", true); 152 setFeatureEnabledImpl(Features, "clflushopt", true); 153 setFeatureEnabledImpl(Features, "rtm", true); 154 LLVM_FALLTHROUGH; 155 case CK_Broadwell: 156 setFeatureEnabledImpl(Features, "rdseed", true); 157 setFeatureEnabledImpl(Features, "adx", true); 158 LLVM_FALLTHROUGH; 159 case CK_Haswell: 160 setFeatureEnabledImpl(Features, "avx2", true); 161 setFeatureEnabledImpl(Features, "lzcnt", true); 162 setFeatureEnabledImpl(Features, "bmi", true); 163 setFeatureEnabledImpl(Features, "bmi2", true); 164 setFeatureEnabledImpl(Features, "fma", true); 165 setFeatureEnabledImpl(Features, "movbe", true); 166 LLVM_FALLTHROUGH; 167 case CK_IvyBridge: 168 setFeatureEnabledImpl(Features, "rdrnd", true); 169 setFeatureEnabledImpl(Features, "f16c", true); 170 setFeatureEnabledImpl(Features, "fsgsbase", true); 171 LLVM_FALLTHROUGH; 172 case CK_SandyBridge: 173 setFeatureEnabledImpl(Features, "avx", true); 174 setFeatureEnabledImpl(Features, "xsave", true); 175 setFeatureEnabledImpl(Features, "xsaveopt", true); 176 LLVM_FALLTHROUGH; 177 case CK_Westmere: 178 setFeatureEnabledImpl(Features, "aes", true); 179 setFeatureEnabledImpl(Features, "pclmul", true); 180 LLVM_FALLTHROUGH; 181 case CK_Nehalem: 182 setFeatureEnabledImpl(Features, "sse4.2", true); 183 LLVM_FALLTHROUGH; 184 case CK_Penryn: 185 setFeatureEnabledImpl(Features, "sse4.1", true); 186 LLVM_FALLTHROUGH; 187 case CK_Core2: 188 setFeatureEnabledImpl(Features, "ssse3", true); 189 LLVM_FALLTHROUGH; 190 case CK_Yonah: 191 case CK_Prescott: 192 case CK_Nocona: 193 setFeatureEnabledImpl(Features, "sse3", true); 194 setFeatureEnabledImpl(Features, "cx16", true); 195 LLVM_FALLTHROUGH; 196 case CK_PentiumM: 197 case CK_Pentium4: 198 case CK_x86_64: 199 setFeatureEnabledImpl(Features, "sse2", true); 200 LLVM_FALLTHROUGH; 201 case CK_Pentium3: 202 case CK_C3_2: 203 setFeatureEnabledImpl(Features, "sse", true); 204 setFeatureEnabledImpl(Features, "fxsr", true); 205 break; 206 207 case CK_Goldmont: 208 setFeatureEnabledImpl(Features, "sha", true); 209 setFeatureEnabledImpl(Features, "rdrnd", true); 210 setFeatureEnabledImpl(Features, "rdseed", true); 211 setFeatureEnabledImpl(Features, "xsave", true); 212 setFeatureEnabledImpl(Features, "xsaveopt", true); 213 setFeatureEnabledImpl(Features, "xsavec", true); 214 setFeatureEnabledImpl(Features, "xsaves", true); 215 setFeatureEnabledImpl(Features, "clflushopt", true); 216 setFeatureEnabledImpl(Features, "mpx", true); 217 setFeatureEnabledImpl(Features, "fsgsbase", true); 218 LLVM_FALLTHROUGH; 219 case CK_Silvermont: 220 setFeatureEnabledImpl(Features, "aes", true); 221 setFeatureEnabledImpl(Features, "pclmul", true); 222 setFeatureEnabledImpl(Features, "sse4.2", true); 223 LLVM_FALLTHROUGH; 224 case CK_Bonnell: 225 setFeatureEnabledImpl(Features, "movbe", true); 226 setFeatureEnabledImpl(Features, "ssse3", true); 227 setFeatureEnabledImpl(Features, "fxsr", true); 228 setFeatureEnabledImpl(Features, "cx16", true); 229 break; 230 231 case CK_KNM: 232 // TODO: Add avx5124fmaps/avx5124vnniw. 233 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 234 LLVM_FALLTHROUGH; 235 case CK_KNL: 236 setFeatureEnabledImpl(Features, "avx512f", true); 237 setFeatureEnabledImpl(Features, "avx512cd", true); 238 setFeatureEnabledImpl(Features, "avx512er", true); 239 setFeatureEnabledImpl(Features, "avx512pf", true); 240 setFeatureEnabledImpl(Features, "prefetchwt1", true); 241 setFeatureEnabledImpl(Features, "fxsr", true); 242 setFeatureEnabledImpl(Features, "rdseed", true); 243 setFeatureEnabledImpl(Features, "adx", true); 244 setFeatureEnabledImpl(Features, "lzcnt", true); 245 setFeatureEnabledImpl(Features, "bmi", true); 246 setFeatureEnabledImpl(Features, "bmi2", true); 247 setFeatureEnabledImpl(Features, "rtm", true); 248 setFeatureEnabledImpl(Features, "fma", true); 249 setFeatureEnabledImpl(Features, "rdrnd", true); 250 setFeatureEnabledImpl(Features, "f16c", true); 251 setFeatureEnabledImpl(Features, "fsgsbase", true); 252 setFeatureEnabledImpl(Features, "aes", true); 253 setFeatureEnabledImpl(Features, "pclmul", true); 254 setFeatureEnabledImpl(Features, "cx16", true); 255 setFeatureEnabledImpl(Features, "xsaveopt", true); 256 setFeatureEnabledImpl(Features, "xsave", true); 257 setFeatureEnabledImpl(Features, "movbe", true); 258 break; 259 260 case CK_K6_2: 261 case CK_K6_3: 262 case CK_WinChip2: 263 case CK_C3: 264 setFeatureEnabledImpl(Features, "3dnow", true); 265 break; 266 267 case CK_AMDFAM10: 268 setFeatureEnabledImpl(Features, "sse4a", true); 269 setFeatureEnabledImpl(Features, "lzcnt", true); 270 setFeatureEnabledImpl(Features, "popcnt", true); 271 LLVM_FALLTHROUGH; 272 case CK_K8SSE3: 273 setFeatureEnabledImpl(Features, "sse3", true); 274 LLVM_FALLTHROUGH; 275 case CK_K8: 276 setFeatureEnabledImpl(Features, "sse2", true); 277 LLVM_FALLTHROUGH; 278 case CK_AthlonXP: 279 setFeatureEnabledImpl(Features, "sse", true); 280 setFeatureEnabledImpl(Features, "fxsr", true); 281 LLVM_FALLTHROUGH; 282 case CK_Athlon: 283 case CK_Geode: 284 setFeatureEnabledImpl(Features, "3dnowa", true); 285 break; 286 287 case CK_BTVER2: 288 setFeatureEnabledImpl(Features, "avx", true); 289 setFeatureEnabledImpl(Features, "aes", true); 290 setFeatureEnabledImpl(Features, "pclmul", true); 291 setFeatureEnabledImpl(Features, "bmi", true); 292 setFeatureEnabledImpl(Features, "f16c", true); 293 setFeatureEnabledImpl(Features, "xsaveopt", true); 294 setFeatureEnabledImpl(Features, "movbe", true); 295 LLVM_FALLTHROUGH; 296 case CK_BTVER1: 297 setFeatureEnabledImpl(Features, "ssse3", true); 298 setFeatureEnabledImpl(Features, "sse4a", true); 299 setFeatureEnabledImpl(Features, "lzcnt", true); 300 setFeatureEnabledImpl(Features, "popcnt", true); 301 setFeatureEnabledImpl(Features, "prfchw", true); 302 setFeatureEnabledImpl(Features, "cx16", true); 303 setFeatureEnabledImpl(Features, "fxsr", true); 304 break; 305 306 case CK_ZNVER1: 307 setFeatureEnabledImpl(Features, "adx", true); 308 setFeatureEnabledImpl(Features, "aes", true); 309 setFeatureEnabledImpl(Features, "avx2", true); 310 setFeatureEnabledImpl(Features, "bmi", true); 311 setFeatureEnabledImpl(Features, "bmi2", true); 312 setFeatureEnabledImpl(Features, "clflushopt", true); 313 setFeatureEnabledImpl(Features, "clzero", true); 314 setFeatureEnabledImpl(Features, "cx16", true); 315 setFeatureEnabledImpl(Features, "f16c", true); 316 setFeatureEnabledImpl(Features, "fma", true); 317 setFeatureEnabledImpl(Features, "fsgsbase", true); 318 setFeatureEnabledImpl(Features, "fxsr", true); 319 setFeatureEnabledImpl(Features, "lzcnt", true); 320 setFeatureEnabledImpl(Features, "mwaitx", true); 321 setFeatureEnabledImpl(Features, "movbe", true); 322 setFeatureEnabledImpl(Features, "pclmul", true); 323 setFeatureEnabledImpl(Features, "popcnt", true); 324 setFeatureEnabledImpl(Features, "prfchw", true); 325 setFeatureEnabledImpl(Features, "rdrnd", true); 326 setFeatureEnabledImpl(Features, "rdseed", true); 327 setFeatureEnabledImpl(Features, "sha", true); 328 setFeatureEnabledImpl(Features, "sse4a", true); 329 setFeatureEnabledImpl(Features, "xsave", true); 330 setFeatureEnabledImpl(Features, "xsavec", true); 331 setFeatureEnabledImpl(Features, "xsaveopt", true); 332 setFeatureEnabledImpl(Features, "xsaves", true); 333 break; 334 335 case CK_BDVER4: 336 setFeatureEnabledImpl(Features, "avx2", true); 337 setFeatureEnabledImpl(Features, "bmi2", true); 338 setFeatureEnabledImpl(Features, "mwaitx", true); 339 LLVM_FALLTHROUGH; 340 case CK_BDVER3: 341 setFeatureEnabledImpl(Features, "fsgsbase", true); 342 setFeatureEnabledImpl(Features, "xsaveopt", true); 343 LLVM_FALLTHROUGH; 344 case CK_BDVER2: 345 setFeatureEnabledImpl(Features, "bmi", true); 346 setFeatureEnabledImpl(Features, "fma", true); 347 setFeatureEnabledImpl(Features, "f16c", true); 348 setFeatureEnabledImpl(Features, "tbm", true); 349 LLVM_FALLTHROUGH; 350 case CK_BDVER1: 351 // xop implies avx, sse4a and fma4. 352 setFeatureEnabledImpl(Features, "xop", true); 353 setFeatureEnabledImpl(Features, "lwp", true); 354 setFeatureEnabledImpl(Features, "lzcnt", true); 355 setFeatureEnabledImpl(Features, "aes", true); 356 setFeatureEnabledImpl(Features, "pclmul", true); 357 setFeatureEnabledImpl(Features, "prfchw", true); 358 setFeatureEnabledImpl(Features, "cx16", true); 359 setFeatureEnabledImpl(Features, "fxsr", true); 360 setFeatureEnabledImpl(Features, "xsave", true); 361 break; 362 } 363 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 364 return false; 365 366 // Can't do this earlier because we need to be able to explicitly enable 367 // or disable these features and the things that they depend upon. 368 369 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 370 auto I = Features.find("sse4.2"); 371 if (I != Features.end() && I->getValue() && 372 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 373 FeaturesVec.end()) 374 Features["popcnt"] = true; 375 376 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 377 I = Features.find("3dnow"); 378 if (I != Features.end() && I->getValue() && 379 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 380 FeaturesVec.end()) 381 Features["prfchw"] = true; 382 383 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 384 // then enable MMX. 385 I = Features.find("sse"); 386 if (I != Features.end() && I->getValue() && 387 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 388 FeaturesVec.end()) 389 Features["mmx"] = true; 390 391 return true; 392 } 393 394 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 395 X86SSEEnum Level, bool Enabled) { 396 if (Enabled) { 397 switch (Level) { 398 case AVX512F: 399 Features["avx512f"] = true; 400 LLVM_FALLTHROUGH; 401 case AVX2: 402 Features["avx2"] = true; 403 LLVM_FALLTHROUGH; 404 case AVX: 405 Features["avx"] = true; 406 Features["xsave"] = true; 407 LLVM_FALLTHROUGH; 408 case SSE42: 409 Features["sse4.2"] = true; 410 LLVM_FALLTHROUGH; 411 case SSE41: 412 Features["sse4.1"] = true; 413 LLVM_FALLTHROUGH; 414 case SSSE3: 415 Features["ssse3"] = true; 416 LLVM_FALLTHROUGH; 417 case SSE3: 418 Features["sse3"] = true; 419 LLVM_FALLTHROUGH; 420 case SSE2: 421 Features["sse2"] = true; 422 LLVM_FALLTHROUGH; 423 case SSE1: 424 Features["sse"] = true; 425 LLVM_FALLTHROUGH; 426 case NoSSE: 427 break; 428 } 429 return; 430 } 431 432 switch (Level) { 433 case NoSSE: 434 case SSE1: 435 Features["sse"] = false; 436 LLVM_FALLTHROUGH; 437 case SSE2: 438 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 439 false; 440 LLVM_FALLTHROUGH; 441 case SSE3: 442 Features["sse3"] = false; 443 setXOPLevel(Features, NoXOP, false); 444 LLVM_FALLTHROUGH; 445 case SSSE3: 446 Features["ssse3"] = false; 447 LLVM_FALLTHROUGH; 448 case SSE41: 449 Features["sse4.1"] = false; 450 LLVM_FALLTHROUGH; 451 case SSE42: 452 Features["sse4.2"] = false; 453 LLVM_FALLTHROUGH; 454 case AVX: 455 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 456 Features["xsaveopt"] = false; 457 setXOPLevel(Features, FMA4, false); 458 LLVM_FALLTHROUGH; 459 case AVX2: 460 Features["avx2"] = false; 461 LLVM_FALLTHROUGH; 462 case AVX512F: 463 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 464 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 465 Features["avx512vl"] = Features["avx512vbmi"] = 466 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 467 break; 468 } 469 } 470 471 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 472 MMX3DNowEnum Level, bool Enabled) { 473 if (Enabled) { 474 switch (Level) { 475 case AMD3DNowAthlon: 476 Features["3dnowa"] = true; 477 LLVM_FALLTHROUGH; 478 case AMD3DNow: 479 Features["3dnow"] = true; 480 LLVM_FALLTHROUGH; 481 case MMX: 482 Features["mmx"] = true; 483 LLVM_FALLTHROUGH; 484 case NoMMX3DNow: 485 break; 486 } 487 return; 488 } 489 490 switch (Level) { 491 case NoMMX3DNow: 492 case MMX: 493 Features["mmx"] = false; 494 LLVM_FALLTHROUGH; 495 case AMD3DNow: 496 Features["3dnow"] = false; 497 LLVM_FALLTHROUGH; 498 case AMD3DNowAthlon: 499 Features["3dnowa"] = false; 500 break; 501 } 502 } 503 504 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 505 bool Enabled) { 506 if (Enabled) { 507 switch (Level) { 508 case XOP: 509 Features["xop"] = true; 510 LLVM_FALLTHROUGH; 511 case FMA4: 512 Features["fma4"] = true; 513 setSSELevel(Features, AVX, true); 514 LLVM_FALLTHROUGH; 515 case SSE4A: 516 Features["sse4a"] = true; 517 setSSELevel(Features, SSE3, true); 518 LLVM_FALLTHROUGH; 519 case NoXOP: 520 break; 521 } 522 return; 523 } 524 525 switch (Level) { 526 case NoXOP: 527 case SSE4A: 528 Features["sse4a"] = false; 529 LLVM_FALLTHROUGH; 530 case FMA4: 531 Features["fma4"] = false; 532 LLVM_FALLTHROUGH; 533 case XOP: 534 Features["xop"] = false; 535 break; 536 } 537 } 538 539 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 540 StringRef Name, bool Enabled) { 541 // This is a bit of a hack to deal with the sse4 target feature when used 542 // as part of the target attribute. We handle sse4 correctly everywhere 543 // else. See below for more information on how we handle the sse4 options. 544 if (Name != "sse4") 545 Features[Name] = Enabled; 546 547 if (Name == "mmx") { 548 setMMXLevel(Features, MMX, Enabled); 549 } else if (Name == "sse") { 550 setSSELevel(Features, SSE1, Enabled); 551 } else if (Name == "sse2") { 552 setSSELevel(Features, SSE2, Enabled); 553 } else if (Name == "sse3") { 554 setSSELevel(Features, SSE3, Enabled); 555 } else if (Name == "ssse3") { 556 setSSELevel(Features, SSSE3, Enabled); 557 } else if (Name == "sse4.2") { 558 setSSELevel(Features, SSE42, Enabled); 559 } else if (Name == "sse4.1") { 560 setSSELevel(Features, SSE41, Enabled); 561 } else if (Name == "3dnow") { 562 setMMXLevel(Features, AMD3DNow, Enabled); 563 } else if (Name == "3dnowa") { 564 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 565 } else if (Name == "aes") { 566 if (Enabled) 567 setSSELevel(Features, SSE2, Enabled); 568 } else if (Name == "pclmul") { 569 if (Enabled) 570 setSSELevel(Features, SSE2, Enabled); 571 } else if (Name == "avx") { 572 setSSELevel(Features, AVX, Enabled); 573 } else if (Name == "avx2") { 574 setSSELevel(Features, AVX2, Enabled); 575 } else if (Name == "avx512f") { 576 setSSELevel(Features, AVX512F, Enabled); 577 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 578 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 579 Name == "avx512vbmi" || Name == "avx512ifma" || 580 Name == "avx512vpopcntdq") { 581 if (Enabled) 582 setSSELevel(Features, AVX512F, Enabled); 583 // Enable BWI instruction if VBMI is being enabled. 584 if (Name == "avx512vbmi" && Enabled) 585 Features["avx512bw"] = true; 586 // Also disable VBMI if BWI is being disabled. 587 if (Name == "avx512bw" && !Enabled) 588 Features["avx512vbmi"] = false; 589 } else if (Name == "fma") { 590 if (Enabled) 591 setSSELevel(Features, AVX, Enabled); 592 } else if (Name == "fma4") { 593 setXOPLevel(Features, FMA4, Enabled); 594 } else if (Name == "xop") { 595 setXOPLevel(Features, XOP, Enabled); 596 } else if (Name == "sse4a") { 597 setXOPLevel(Features, SSE4A, Enabled); 598 } else if (Name == "f16c") { 599 if (Enabled) 600 setSSELevel(Features, AVX, Enabled); 601 } else if (Name == "sha") { 602 if (Enabled) 603 setSSELevel(Features, SSE2, Enabled); 604 } else if (Name == "sse4") { 605 // We can get here via the __target__ attribute since that's not controlled 606 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 607 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 608 // disabled. 609 if (Enabled) 610 setSSELevel(Features, SSE42, Enabled); 611 else 612 setSSELevel(Features, SSE41, Enabled); 613 } else if (Name == "xsave") { 614 if (!Enabled) 615 Features["xsaveopt"] = false; 616 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 617 if (Enabled) 618 Features["xsave"] = true; 619 } 620 } 621 622 /// handleTargetFeatures - Perform initialization based on the user 623 /// configured set of features. 624 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 625 DiagnosticsEngine &Diags) { 626 for (const auto &Feature : Features) { 627 if (Feature[0] != '+') 628 continue; 629 630 if (Feature == "+aes") { 631 HasAES = true; 632 } else if (Feature == "+pclmul") { 633 HasPCLMUL = true; 634 } else if (Feature == "+lzcnt") { 635 HasLZCNT = true; 636 } else if (Feature == "+rdrnd") { 637 HasRDRND = true; 638 } else if (Feature == "+fsgsbase") { 639 HasFSGSBASE = true; 640 } else if (Feature == "+bmi") { 641 HasBMI = true; 642 } else if (Feature == "+bmi2") { 643 HasBMI2 = true; 644 } else if (Feature == "+popcnt") { 645 HasPOPCNT = true; 646 } else if (Feature == "+rtm") { 647 HasRTM = true; 648 } else if (Feature == "+prfchw") { 649 HasPRFCHW = true; 650 } else if (Feature == "+rdseed") { 651 HasRDSEED = true; 652 } else if (Feature == "+adx") { 653 HasADX = true; 654 } else if (Feature == "+tbm") { 655 HasTBM = true; 656 } else if (Feature == "+lwp") { 657 HasLWP = true; 658 } else if (Feature == "+fma") { 659 HasFMA = true; 660 } else if (Feature == "+f16c") { 661 HasF16C = true; 662 } else if (Feature == "+avx512cd") { 663 HasAVX512CD = true; 664 } else if (Feature == "+avx512vpopcntdq") { 665 HasAVX512VPOPCNTDQ = true; 666 } else if (Feature == "+avx512er") { 667 HasAVX512ER = true; 668 } else if (Feature == "+avx512pf") { 669 HasAVX512PF = true; 670 } else if (Feature == "+avx512dq") { 671 HasAVX512DQ = true; 672 } else if (Feature == "+avx512bw") { 673 HasAVX512BW = true; 674 } else if (Feature == "+avx512vl") { 675 HasAVX512VL = true; 676 } else if (Feature == "+avx512vbmi") { 677 HasAVX512VBMI = true; 678 } else if (Feature == "+avx512ifma") { 679 HasAVX512IFMA = true; 680 } else if (Feature == "+sha") { 681 HasSHA = true; 682 } else if (Feature == "+mpx") { 683 HasMPX = true; 684 } else if (Feature == "+movbe") { 685 HasMOVBE = true; 686 } else if (Feature == "+sgx") { 687 HasSGX = true; 688 } else if (Feature == "+cx16") { 689 HasCX16 = true; 690 } else if (Feature == "+fxsr") { 691 HasFXSR = true; 692 } else if (Feature == "+xsave") { 693 HasXSAVE = true; 694 } else if (Feature == "+xsaveopt") { 695 HasXSAVEOPT = true; 696 } else if (Feature == "+xsavec") { 697 HasXSAVEC = true; 698 } else if (Feature == "+xsaves") { 699 HasXSAVES = true; 700 } else if (Feature == "+mwaitx") { 701 HasMWAITX = true; 702 } else if (Feature == "+pku") { 703 HasPKU = true; 704 } else if (Feature == "+clflushopt") { 705 HasCLFLUSHOPT = true; 706 } else if (Feature == "+clwb") { 707 HasCLWB = true; 708 } else if (Feature == "+prefetchwt1") { 709 HasPREFETCHWT1 = true; 710 } else if (Feature == "+clzero") { 711 HasCLZERO = true; 712 } 713 714 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 715 .Case("+avx512f", AVX512F) 716 .Case("+avx2", AVX2) 717 .Case("+avx", AVX) 718 .Case("+sse4.2", SSE42) 719 .Case("+sse4.1", SSE41) 720 .Case("+ssse3", SSSE3) 721 .Case("+sse3", SSE3) 722 .Case("+sse2", SSE2) 723 .Case("+sse", SSE1) 724 .Default(NoSSE); 725 SSELevel = std::max(SSELevel, Level); 726 727 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 728 .Case("+3dnowa", AMD3DNowAthlon) 729 .Case("+3dnow", AMD3DNow) 730 .Case("+mmx", MMX) 731 .Default(NoMMX3DNow); 732 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 733 734 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 735 .Case("+xop", XOP) 736 .Case("+fma4", FMA4) 737 .Case("+sse4a", SSE4A) 738 .Default(NoXOP); 739 XOPLevel = std::max(XOPLevel, XLevel); 740 } 741 742 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 743 // matches the selected sse level. 744 if ((FPMath == FP_SSE && SSELevel < SSE1) || 745 (FPMath == FP_387 && SSELevel >= SSE1)) { 746 Diags.Report(diag::err_target_unsupported_fpmath) 747 << (FPMath == FP_SSE ? "sse" : "387"); 748 return false; 749 } 750 751 SimdDefaultAlign = 752 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 753 return true; 754 } 755 756 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 757 /// definitions for this particular subtarget. 758 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 759 MacroBuilder &Builder) const { 760 // Target identification. 761 if (getTriple().getArch() == llvm::Triple::x86_64) { 762 Builder.defineMacro("__amd64__"); 763 Builder.defineMacro("__amd64"); 764 Builder.defineMacro("__x86_64"); 765 Builder.defineMacro("__x86_64__"); 766 if (getTriple().getArchName() == "x86_64h") { 767 Builder.defineMacro("__x86_64h"); 768 Builder.defineMacro("__x86_64h__"); 769 } 770 } else { 771 DefineStd(Builder, "i386", Opts); 772 } 773 774 // Subtarget options. 775 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 776 // truly should be based on -mtune options. 777 switch (CPU) { 778 case CK_Generic: 779 break; 780 case CK_i386: 781 // The rest are coming from the i386 define above. 782 Builder.defineMacro("__tune_i386__"); 783 break; 784 case CK_i486: 785 case CK_WinChipC6: 786 case CK_WinChip2: 787 case CK_C3: 788 defineCPUMacros(Builder, "i486"); 789 break; 790 case CK_PentiumMMX: 791 Builder.defineMacro("__pentium_mmx__"); 792 Builder.defineMacro("__tune_pentium_mmx__"); 793 LLVM_FALLTHROUGH; 794 case CK_i586: 795 case CK_Pentium: 796 defineCPUMacros(Builder, "i586"); 797 defineCPUMacros(Builder, "pentium"); 798 break; 799 case CK_Pentium3: 800 case CK_PentiumM: 801 Builder.defineMacro("__tune_pentium3__"); 802 LLVM_FALLTHROUGH; 803 case CK_Pentium2: 804 case CK_C3_2: 805 Builder.defineMacro("__tune_pentium2__"); 806 LLVM_FALLTHROUGH; 807 case CK_PentiumPro: 808 defineCPUMacros(Builder, "i686"); 809 defineCPUMacros(Builder, "pentiumpro"); 810 break; 811 case CK_Pentium4: 812 defineCPUMacros(Builder, "pentium4"); 813 break; 814 case CK_Yonah: 815 case CK_Prescott: 816 case CK_Nocona: 817 defineCPUMacros(Builder, "nocona"); 818 break; 819 case CK_Core2: 820 case CK_Penryn: 821 defineCPUMacros(Builder, "core2"); 822 break; 823 case CK_Bonnell: 824 defineCPUMacros(Builder, "atom"); 825 break; 826 case CK_Silvermont: 827 defineCPUMacros(Builder, "slm"); 828 break; 829 case CK_Goldmont: 830 defineCPUMacros(Builder, "goldmont"); 831 break; 832 case CK_Nehalem: 833 case CK_Westmere: 834 case CK_SandyBridge: 835 case CK_IvyBridge: 836 case CK_Haswell: 837 case CK_Broadwell: 838 case CK_SkylakeClient: 839 // FIXME: Historically, we defined this legacy name, it would be nice to 840 // remove it at some point. We've never exposed fine-grained names for 841 // recent primary x86 CPUs, and we should keep it that way. 842 defineCPUMacros(Builder, "corei7"); 843 break; 844 case CK_SkylakeServer: 845 defineCPUMacros(Builder, "skx"); 846 break; 847 case CK_Cannonlake: 848 break; 849 case CK_KNL: 850 defineCPUMacros(Builder, "knl"); 851 break; 852 case CK_KNM: 853 break; 854 case CK_Lakemont: 855 defineCPUMacros(Builder, "i586", /*Tuning*/false); 856 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 857 Builder.defineMacro("__tune_lakemont__"); 858 break; 859 case CK_K6_2: 860 Builder.defineMacro("__k6_2__"); 861 Builder.defineMacro("__tune_k6_2__"); 862 LLVM_FALLTHROUGH; 863 case CK_K6_3: 864 if (CPU != CK_K6_2) { // In case of fallthrough 865 // FIXME: GCC may be enabling these in cases where some other k6 866 // architecture is specified but -m3dnow is explicitly provided. The 867 // exact semantics need to be determined and emulated here. 868 Builder.defineMacro("__k6_3__"); 869 Builder.defineMacro("__tune_k6_3__"); 870 } 871 LLVM_FALLTHROUGH; 872 case CK_K6: 873 defineCPUMacros(Builder, "k6"); 874 break; 875 case CK_Athlon: 876 case CK_AthlonXP: 877 defineCPUMacros(Builder, "athlon"); 878 if (SSELevel != NoSSE) { 879 Builder.defineMacro("__athlon_sse__"); 880 Builder.defineMacro("__tune_athlon_sse__"); 881 } 882 break; 883 case CK_K8: 884 case CK_K8SSE3: 885 case CK_x86_64: 886 defineCPUMacros(Builder, "k8"); 887 break; 888 case CK_AMDFAM10: 889 defineCPUMacros(Builder, "amdfam10"); 890 break; 891 case CK_BTVER1: 892 defineCPUMacros(Builder, "btver1"); 893 break; 894 case CK_BTVER2: 895 defineCPUMacros(Builder, "btver2"); 896 break; 897 case CK_BDVER1: 898 defineCPUMacros(Builder, "bdver1"); 899 break; 900 case CK_BDVER2: 901 defineCPUMacros(Builder, "bdver2"); 902 break; 903 case CK_BDVER3: 904 defineCPUMacros(Builder, "bdver3"); 905 break; 906 case CK_BDVER4: 907 defineCPUMacros(Builder, "bdver4"); 908 break; 909 case CK_ZNVER1: 910 defineCPUMacros(Builder, "znver1"); 911 break; 912 case CK_Geode: 913 defineCPUMacros(Builder, "geode"); 914 break; 915 } 916 917 // Target properties. 918 Builder.defineMacro("__REGISTER_PREFIX__", ""); 919 920 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 921 // functions in glibc header files that use FP Stack inline asm which the 922 // backend can't deal with (PR879). 923 Builder.defineMacro("__NO_MATH_INLINES"); 924 925 if (HasAES) 926 Builder.defineMacro("__AES__"); 927 928 if (HasPCLMUL) 929 Builder.defineMacro("__PCLMUL__"); 930 931 if (HasLZCNT) 932 Builder.defineMacro("__LZCNT__"); 933 934 if (HasRDRND) 935 Builder.defineMacro("__RDRND__"); 936 937 if (HasFSGSBASE) 938 Builder.defineMacro("__FSGSBASE__"); 939 940 if (HasBMI) 941 Builder.defineMacro("__BMI__"); 942 943 if (HasBMI2) 944 Builder.defineMacro("__BMI2__"); 945 946 if (HasPOPCNT) 947 Builder.defineMacro("__POPCNT__"); 948 949 if (HasRTM) 950 Builder.defineMacro("__RTM__"); 951 952 if (HasPRFCHW) 953 Builder.defineMacro("__PRFCHW__"); 954 955 if (HasRDSEED) 956 Builder.defineMacro("__RDSEED__"); 957 958 if (HasADX) 959 Builder.defineMacro("__ADX__"); 960 961 if (HasTBM) 962 Builder.defineMacro("__TBM__"); 963 964 if (HasLWP) 965 Builder.defineMacro("__LWP__"); 966 967 if (HasMWAITX) 968 Builder.defineMacro("__MWAITX__"); 969 970 switch (XOPLevel) { 971 case XOP: 972 Builder.defineMacro("__XOP__"); 973 LLVM_FALLTHROUGH; 974 case FMA4: 975 Builder.defineMacro("__FMA4__"); 976 LLVM_FALLTHROUGH; 977 case SSE4A: 978 Builder.defineMacro("__SSE4A__"); 979 LLVM_FALLTHROUGH; 980 case NoXOP: 981 break; 982 } 983 984 if (HasFMA) 985 Builder.defineMacro("__FMA__"); 986 987 if (HasF16C) 988 Builder.defineMacro("__F16C__"); 989 990 if (HasAVX512CD) 991 Builder.defineMacro("__AVX512CD__"); 992 if (HasAVX512VPOPCNTDQ) 993 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 994 if (HasAVX512ER) 995 Builder.defineMacro("__AVX512ER__"); 996 if (HasAVX512PF) 997 Builder.defineMacro("__AVX512PF__"); 998 if (HasAVX512DQ) 999 Builder.defineMacro("__AVX512DQ__"); 1000 if (HasAVX512BW) 1001 Builder.defineMacro("__AVX512BW__"); 1002 if (HasAVX512VL) 1003 Builder.defineMacro("__AVX512VL__"); 1004 if (HasAVX512VBMI) 1005 Builder.defineMacro("__AVX512VBMI__"); 1006 if (HasAVX512IFMA) 1007 Builder.defineMacro("__AVX512IFMA__"); 1008 1009 if (HasSHA) 1010 Builder.defineMacro("__SHA__"); 1011 1012 if (HasFXSR) 1013 Builder.defineMacro("__FXSR__"); 1014 if (HasXSAVE) 1015 Builder.defineMacro("__XSAVE__"); 1016 if (HasXSAVEOPT) 1017 Builder.defineMacro("__XSAVEOPT__"); 1018 if (HasXSAVEC) 1019 Builder.defineMacro("__XSAVEC__"); 1020 if (HasXSAVES) 1021 Builder.defineMacro("__XSAVES__"); 1022 if (HasPKU) 1023 Builder.defineMacro("__PKU__"); 1024 if (HasCX16) 1025 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1026 if (HasCLFLUSHOPT) 1027 Builder.defineMacro("__CLFLUSHOPT__"); 1028 if (HasCLWB) 1029 Builder.defineMacro("__CLWB__"); 1030 if (HasMPX) 1031 Builder.defineMacro("__MPX__"); 1032 if (HasSGX) 1033 Builder.defineMacro("__SGX__"); 1034 if (HasPREFETCHWT1) 1035 Builder.defineMacro("__PREFETCHWT1__"); 1036 if (HasCLZERO) 1037 Builder.defineMacro("__CLZERO__"); 1038 1039 // Each case falls through to the previous one here. 1040 switch (SSELevel) { 1041 case AVX512F: 1042 Builder.defineMacro("__AVX512F__"); 1043 LLVM_FALLTHROUGH; 1044 case AVX2: 1045 Builder.defineMacro("__AVX2__"); 1046 LLVM_FALLTHROUGH; 1047 case AVX: 1048 Builder.defineMacro("__AVX__"); 1049 LLVM_FALLTHROUGH; 1050 case SSE42: 1051 Builder.defineMacro("__SSE4_2__"); 1052 LLVM_FALLTHROUGH; 1053 case SSE41: 1054 Builder.defineMacro("__SSE4_1__"); 1055 LLVM_FALLTHROUGH; 1056 case SSSE3: 1057 Builder.defineMacro("__SSSE3__"); 1058 LLVM_FALLTHROUGH; 1059 case SSE3: 1060 Builder.defineMacro("__SSE3__"); 1061 LLVM_FALLTHROUGH; 1062 case SSE2: 1063 Builder.defineMacro("__SSE2__"); 1064 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1065 LLVM_FALLTHROUGH; 1066 case SSE1: 1067 Builder.defineMacro("__SSE__"); 1068 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1069 LLVM_FALLTHROUGH; 1070 case NoSSE: 1071 break; 1072 } 1073 1074 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1075 switch (SSELevel) { 1076 case AVX512F: 1077 case AVX2: 1078 case AVX: 1079 case SSE42: 1080 case SSE41: 1081 case SSSE3: 1082 case SSE3: 1083 case SSE2: 1084 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1085 break; 1086 case SSE1: 1087 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1088 break; 1089 default: 1090 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1091 break; 1092 } 1093 } 1094 1095 // Each case falls through to the previous one here. 1096 switch (MMX3DNowLevel) { 1097 case AMD3DNowAthlon: 1098 Builder.defineMacro("__3dNOW_A__"); 1099 LLVM_FALLTHROUGH; 1100 case AMD3DNow: 1101 Builder.defineMacro("__3dNOW__"); 1102 LLVM_FALLTHROUGH; 1103 case MMX: 1104 Builder.defineMacro("__MMX__"); 1105 LLVM_FALLTHROUGH; 1106 case NoMMX3DNow: 1107 break; 1108 } 1109 1110 if (CPU >= CK_i486) { 1111 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1112 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1113 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1114 } 1115 if (CPU >= CK_i586) 1116 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1117 1118 if (HasFloat128) 1119 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1120 } 1121 1122 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1123 return llvm::StringSwitch<bool>(Name) 1124 .Case("3dnow", true) 1125 .Case("3dnowa", true) 1126 .Case("aes", true) 1127 .Case("avx", true) 1128 .Case("avx2", true) 1129 .Case("avx512f", true) 1130 .Case("avx512cd", true) 1131 .Case("avx512vpopcntdq", true) 1132 .Case("avx512er", true) 1133 .Case("avx512pf", true) 1134 .Case("avx512dq", true) 1135 .Case("avx512bw", true) 1136 .Case("avx512vl", true) 1137 .Case("avx512vbmi", true) 1138 .Case("avx512ifma", true) 1139 .Case("bmi", true) 1140 .Case("bmi2", true) 1141 .Case("clflushopt", true) 1142 .Case("clwb", true) 1143 .Case("clzero", true) 1144 .Case("cx16", true) 1145 .Case("f16c", true) 1146 .Case("fma", true) 1147 .Case("fma4", true) 1148 .Case("fsgsbase", true) 1149 .Case("fxsr", true) 1150 .Case("lwp", true) 1151 .Case("lzcnt", true) 1152 .Case("mm3dnow", true) 1153 .Case("mm3dnowa", true) 1154 .Case("mmx", true) 1155 .Case("movbe", true) 1156 .Case("mpx", true) 1157 .Case("pclmul", true) 1158 .Case("pku", true) 1159 .Case("popcnt", true) 1160 .Case("prefetchwt1", true) 1161 .Case("prfchw", true) 1162 .Case("rdrnd", true) 1163 .Case("rdseed", true) 1164 .Case("rtm", true) 1165 .Case("sgx", true) 1166 .Case("sha", true) 1167 .Case("sse", true) 1168 .Case("sse2", true) 1169 .Case("sse3", true) 1170 .Case("ssse3", true) 1171 .Case("sse4", true) 1172 .Case("sse4.1", true) 1173 .Case("sse4.2", true) 1174 .Case("sse4a", true) 1175 .Case("tbm", true) 1176 .Case("x87", true) 1177 .Case("xop", true) 1178 .Case("xsave", true) 1179 .Case("xsavec", true) 1180 .Case("xsaves", true) 1181 .Case("xsaveopt", true) 1182 .Default(false); 1183 } 1184 1185 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1186 return llvm::StringSwitch<bool>(Feature) 1187 .Case("aes", HasAES) 1188 .Case("avx", SSELevel >= AVX) 1189 .Case("avx2", SSELevel >= AVX2) 1190 .Case("avx512f", SSELevel >= AVX512F) 1191 .Case("avx512cd", HasAVX512CD) 1192 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1193 .Case("avx512er", HasAVX512ER) 1194 .Case("avx512pf", HasAVX512PF) 1195 .Case("avx512dq", HasAVX512DQ) 1196 .Case("avx512bw", HasAVX512BW) 1197 .Case("avx512vl", HasAVX512VL) 1198 .Case("avx512vbmi", HasAVX512VBMI) 1199 .Case("avx512ifma", HasAVX512IFMA) 1200 .Case("bmi", HasBMI) 1201 .Case("bmi2", HasBMI2) 1202 .Case("clflushopt", HasCLFLUSHOPT) 1203 .Case("clwb", HasCLWB) 1204 .Case("clzero", HasCLZERO) 1205 .Case("cx16", HasCX16) 1206 .Case("f16c", HasF16C) 1207 .Case("fma", HasFMA) 1208 .Case("fma4", XOPLevel >= FMA4) 1209 .Case("fsgsbase", HasFSGSBASE) 1210 .Case("fxsr", HasFXSR) 1211 .Case("lwp", HasLWP) 1212 .Case("lzcnt", HasLZCNT) 1213 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1214 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1215 .Case("mmx", MMX3DNowLevel >= MMX) 1216 .Case("movbe", HasMOVBE) 1217 .Case("mpx", HasMPX) 1218 .Case("pclmul", HasPCLMUL) 1219 .Case("pku", HasPKU) 1220 .Case("popcnt", HasPOPCNT) 1221 .Case("prefetchwt1", HasPREFETCHWT1) 1222 .Case("prfchw", HasPRFCHW) 1223 .Case("rdrnd", HasRDRND) 1224 .Case("rdseed", HasRDSEED) 1225 .Case("rtm", HasRTM) 1226 .Case("sgx", HasSGX) 1227 .Case("sha", HasSHA) 1228 .Case("sse", SSELevel >= SSE1) 1229 .Case("sse2", SSELevel >= SSE2) 1230 .Case("sse3", SSELevel >= SSE3) 1231 .Case("ssse3", SSELevel >= SSSE3) 1232 .Case("sse4.1", SSELevel >= SSE41) 1233 .Case("sse4.2", SSELevel >= SSE42) 1234 .Case("sse4a", XOPLevel >= SSE4A) 1235 .Case("tbm", HasTBM) 1236 .Case("x86", true) 1237 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1238 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1239 .Case("xop", XOPLevel >= XOP) 1240 .Case("xsave", HasXSAVE) 1241 .Case("xsavec", HasXSAVEC) 1242 .Case("xsaves", HasXSAVES) 1243 .Case("xsaveopt", HasXSAVEOPT) 1244 .Default(false); 1245 } 1246 1247 // We can't use a generic validation scheme for the features accepted here 1248 // versus subtarget features accepted in the target attribute because the 1249 // bitfield structure that's initialized in the runtime only supports the 1250 // below currently rather than the full range of subtarget features. (See 1251 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1252 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1253 return llvm::StringSwitch<bool>(FeatureStr) 1254 .Case("cmov", true) 1255 .Case("mmx", true) 1256 .Case("popcnt", true) 1257 .Case("sse", true) 1258 .Case("sse2", true) 1259 .Case("sse3", true) 1260 .Case("ssse3", true) 1261 .Case("sse4.1", true) 1262 .Case("sse4.2", true) 1263 .Case("avx", true) 1264 .Case("avx2", true) 1265 .Case("sse4a", true) 1266 .Case("fma4", true) 1267 .Case("xop", true) 1268 .Case("fma", true) 1269 .Case("avx512f", true) 1270 .Case("bmi", true) 1271 .Case("bmi2", true) 1272 .Case("aes", true) 1273 .Case("pclmul", true) 1274 .Case("avx512vl", true) 1275 .Case("avx512bw", true) 1276 .Case("avx512dq", true) 1277 .Case("avx512cd", true) 1278 .Case("avx512er", true) 1279 .Case("avx512pf", true) 1280 .Case("avx512vbmi", true) 1281 .Case("avx512ifma", true) 1282 .Case("avx5124vnniw", true) 1283 .Case("avx5124fmaps", true) 1284 .Case("avx512vpopcntdq", true) 1285 .Default(false); 1286 } 1287 1288 // We can't use a generic validation scheme for the cpus accepted here 1289 // versus subtarget cpus accepted in the target attribute because the 1290 // variables intitialized by the runtime only support the below currently 1291 // rather than the full range of cpus. 1292 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1293 return llvm::StringSwitch<bool>(FeatureStr) 1294 .Case("amd", true) 1295 .Case("amdfam10h", true) 1296 .Case("amdfam15h", true) 1297 .Case("amdfam17h", true) 1298 .Case("atom", true) 1299 .Case("barcelona", true) 1300 .Case("bdver1", true) 1301 .Case("bdver2", true) 1302 .Case("bdver3", true) 1303 .Case("bdver4", true) 1304 .Case("bonnell", true) 1305 .Case("broadwell", true) 1306 .Case("btver1", true) 1307 .Case("btver2", true) 1308 .Case("core2", true) 1309 .Case("corei7", true) 1310 .Case("haswell", true) 1311 .Case("intel", true) 1312 .Case("istanbul", true) 1313 .Case("ivybridge", true) 1314 .Case("knl", true) 1315 .Case("nehalem", true) 1316 .Case("sandybridge", true) 1317 .Case("shanghai", true) 1318 .Case("silvermont", true) 1319 .Case("skylake", true) 1320 .Case("skylake-avx512", true) 1321 .Case("slm", true) 1322 .Case("westmere", true) 1323 .Case("znver1", true) 1324 .Default(false); 1325 } 1326 1327 bool X86TargetInfo::validateAsmConstraint( 1328 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1329 switch (*Name) { 1330 default: 1331 return false; 1332 // Constant constraints. 1333 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1334 // instructions. 1335 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1336 // x86_64 instructions. 1337 case 's': 1338 Info.setRequiresImmediate(); 1339 return true; 1340 case 'I': 1341 Info.setRequiresImmediate(0, 31); 1342 return true; 1343 case 'J': 1344 Info.setRequiresImmediate(0, 63); 1345 return true; 1346 case 'K': 1347 Info.setRequiresImmediate(-128, 127); 1348 return true; 1349 case 'L': 1350 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1351 return true; 1352 case 'M': 1353 Info.setRequiresImmediate(0, 3); 1354 return true; 1355 case 'N': 1356 Info.setRequiresImmediate(0, 255); 1357 return true; 1358 case 'O': 1359 Info.setRequiresImmediate(0, 127); 1360 return true; 1361 // Register constraints. 1362 case 'Y': // 'Y' is the first character for several 2-character constraints. 1363 // Shift the pointer to the second character of the constraint. 1364 Name++; 1365 switch (*Name) { 1366 default: 1367 return false; 1368 case 'z': 1369 case '0': // First SSE register. 1370 case '2': 1371 case 't': // Any SSE register, when SSE2 is enabled. 1372 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1373 case 'm': // Any MMX register, when inter-unit moves enabled. 1374 case 'k': // AVX512 arch mask registers: k1-k7. 1375 Info.setAllowsRegister(); 1376 return true; 1377 } 1378 case 'f': // Any x87 floating point stack register. 1379 // Constraint 'f' cannot be used for output operands. 1380 if (Info.ConstraintStr[0] == '=') 1381 return false; 1382 Info.setAllowsRegister(); 1383 return true; 1384 case 'a': // eax. 1385 case 'b': // ebx. 1386 case 'c': // ecx. 1387 case 'd': // edx. 1388 case 'S': // esi. 1389 case 'D': // edi. 1390 case 'A': // edx:eax. 1391 case 't': // Top of floating point stack. 1392 case 'u': // Second from top of floating point stack. 1393 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1394 case 'y': // Any MMX register. 1395 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1396 case 'x': // Any SSE register. 1397 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 1398 // for intermideate k reg operations). 1399 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1400 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1401 case 'l': // "Index" registers: any general register that can be used as an 1402 // index in a base+index memory access. 1403 Info.setAllowsRegister(); 1404 return true; 1405 // Floating point constant constraints. 1406 case 'C': // SSE floating point constant. 1407 case 'G': // x87 floating point constant. 1408 return true; 1409 } 1410 } 1411 1412 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1413 unsigned Size) const { 1414 // Strip off constraint modifiers. 1415 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1416 Constraint = Constraint.substr(1); 1417 1418 return validateOperandSize(Constraint, Size); 1419 } 1420 1421 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1422 unsigned Size) const { 1423 return validateOperandSize(Constraint, Size); 1424 } 1425 1426 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1427 unsigned Size) const { 1428 switch (Constraint[0]) { 1429 default: 1430 break; 1431 case 'k': 1432 // Registers k0-k7 (AVX512) size limit is 64 bit. 1433 case 'y': 1434 return Size <= 64; 1435 case 'f': 1436 case 't': 1437 case 'u': 1438 return Size <= 128; 1439 case 'Y': 1440 // 'Y' is the first character for several 2-character constraints. 1441 switch (Constraint[1]) { 1442 default: 1443 return false; 1444 case 'm': 1445 // 'Ym' is synonymous with 'y'. 1446 case 'k': 1447 return Size <= 64; 1448 case 'z': 1449 case '0': 1450 // XMM0 1451 if (SSELevel >= SSE1) 1452 return Size <= 128U; 1453 return false; 1454 case 'i': 1455 case 't': 1456 case '2': 1457 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1458 if (SSELevel < SSE2) 1459 return false; 1460 break; 1461 } 1462 case 'v': 1463 case 'x': 1464 if (SSELevel >= AVX512F) 1465 // 512-bit zmm registers can be used if target supports AVX512F. 1466 return Size <= 512U; 1467 else if (SSELevel >= AVX) 1468 // 256-bit ymm registers can be used if target supports AVX. 1469 return Size <= 256U; 1470 return Size <= 128U; 1471 1472 } 1473 1474 return true; 1475 } 1476 1477 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1478 switch (*Constraint) { 1479 case 'a': 1480 return std::string("{ax}"); 1481 case 'b': 1482 return std::string("{bx}"); 1483 case 'c': 1484 return std::string("{cx}"); 1485 case 'd': 1486 return std::string("{dx}"); 1487 case 'S': 1488 return std::string("{si}"); 1489 case 'D': 1490 return std::string("{di}"); 1491 case 'p': // address 1492 return std::string("im"); 1493 case 't': // top of floating point stack. 1494 return std::string("{st}"); 1495 case 'u': // second from top of floating point stack. 1496 return std::string("{st(1)}"); // second from top of floating point stack. 1497 case 'Y': 1498 switch (Constraint[1]) { 1499 default: 1500 // Break from inner switch and fall through (copy single char), 1501 // continue parsing after copying the current constraint into 1502 // the return string. 1503 break; 1504 case 'k': 1505 case 'm': 1506 case 'i': 1507 case 't': 1508 case 'z': 1509 case '0': 1510 case '2': 1511 // "^" hints llvm that this is a 2 letter constraint. 1512 // "Constraint++" is used to promote the string iterator 1513 // to the next constraint. 1514 return std::string("^") + std::string(Constraint++, 2); 1515 } 1516 LLVM_FALLTHROUGH; 1517 default: 1518 return std::string(1, *Constraint); 1519 } 1520 } 1521 1522 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1523 // Perform any per-CPU checks necessary to determine if this CPU is 1524 // acceptable. 1525 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1526 // invalid without explaining *why*. 1527 switch (Kind) { 1528 case CK_Generic: 1529 // No processor selected! 1530 return false; 1531 1532 case CK_i386: 1533 case CK_i486: 1534 case CK_WinChipC6: 1535 case CK_WinChip2: 1536 case CK_C3: 1537 case CK_i586: 1538 case CK_Pentium: 1539 case CK_PentiumMMX: 1540 case CK_PentiumPro: 1541 case CK_Pentium2: 1542 case CK_Pentium3: 1543 case CK_PentiumM: 1544 case CK_Yonah: 1545 case CK_C3_2: 1546 case CK_Pentium4: 1547 case CK_Lakemont: 1548 case CK_Prescott: 1549 case CK_K6: 1550 case CK_K6_2: 1551 case CK_K6_3: 1552 case CK_Athlon: 1553 case CK_AthlonXP: 1554 case CK_Geode: 1555 // Only accept certain architectures when compiling in 32-bit mode. 1556 if (getTriple().getArch() != llvm::Triple::x86) 1557 return false; 1558 1559 LLVM_FALLTHROUGH; 1560 case CK_Nocona: 1561 case CK_Core2: 1562 case CK_Penryn: 1563 case CK_Bonnell: 1564 case CK_Silvermont: 1565 case CK_Goldmont: 1566 case CK_Nehalem: 1567 case CK_Westmere: 1568 case CK_SandyBridge: 1569 case CK_IvyBridge: 1570 case CK_Haswell: 1571 case CK_Broadwell: 1572 case CK_SkylakeClient: 1573 case CK_SkylakeServer: 1574 case CK_Cannonlake: 1575 case CK_KNL: 1576 case CK_KNM: 1577 case CK_K8: 1578 case CK_K8SSE3: 1579 case CK_AMDFAM10: 1580 case CK_BTVER1: 1581 case CK_BTVER2: 1582 case CK_BDVER1: 1583 case CK_BDVER2: 1584 case CK_BDVER3: 1585 case CK_BDVER4: 1586 case CK_ZNVER1: 1587 case CK_x86_64: 1588 return true; 1589 } 1590 llvm_unreachable("Unhandled CPU kind"); 1591 } 1592 1593 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1594 return llvm::StringSwitch<CPUKind>(CPU) 1595 .Case("i386", CK_i386) 1596 .Case("i486", CK_i486) 1597 .Case("winchip-c6", CK_WinChipC6) 1598 .Case("winchip2", CK_WinChip2) 1599 .Case("c3", CK_C3) 1600 .Case("i586", CK_i586) 1601 .Case("pentium", CK_Pentium) 1602 .Case("pentium-mmx", CK_PentiumMMX) 1603 .Cases("i686", "pentiumpro", CK_PentiumPro) 1604 .Case("pentium2", CK_Pentium2) 1605 .Cases("pentium3", "pentium3m", CK_Pentium3) 1606 .Case("pentium-m", CK_PentiumM) 1607 .Case("c3-2", CK_C3_2) 1608 .Case("yonah", CK_Yonah) 1609 .Cases("pentium4", "pentium4m", CK_Pentium4) 1610 .Case("prescott", CK_Prescott) 1611 .Case("nocona", CK_Nocona) 1612 .Case("core2", CK_Core2) 1613 .Case("penryn", CK_Penryn) 1614 .Cases("bonnell", "atom", CK_Bonnell) 1615 .Cases("silvermont", "slm", CK_Silvermont) 1616 .Case("goldmont", CK_Goldmont) 1617 .Cases("nehalem", "corei7", CK_Nehalem) 1618 .Case("westmere", CK_Westmere) 1619 .Cases("sandybridge", "corei7-avx", CK_SandyBridge) 1620 .Cases("ivybridge", "core-avx-i", CK_IvyBridge) 1621 .Cases("haswell", "core-avx2", CK_Haswell) 1622 .Case("broadwell", CK_Broadwell) 1623 .Case("skylake", CK_SkylakeClient) 1624 .Cases("skylake-avx512", "skx", CK_SkylakeServer) 1625 .Case("cannonlake", CK_Cannonlake) 1626 .Case("knl", CK_KNL) 1627 .Case("knm", CK_KNM) 1628 .Case("lakemont", CK_Lakemont) 1629 .Case("k6", CK_K6) 1630 .Case("k6-2", CK_K6_2) 1631 .Case("k6-3", CK_K6_3) 1632 .Cases("athlon", "athlon-tbird", CK_Athlon) 1633 .Cases("athlon-xp", "athlon-mp", "athlon-4", CK_AthlonXP) 1634 .Cases("k8", "athlon64", "athlon-fx", "opteron", CK_K8) 1635 .Cases("k8-sse3", "athlon64-sse3", "opteron-sse3", CK_K8SSE3) 1636 .Cases("amdfam10", "barcelona", CK_AMDFAM10) 1637 .Case("btver1", CK_BTVER1) 1638 .Case("btver2", CK_BTVER2) 1639 .Case("bdver1", CK_BDVER1) 1640 .Case("bdver2", CK_BDVER2) 1641 .Case("bdver3", CK_BDVER3) 1642 .Case("bdver4", CK_BDVER4) 1643 .Case("znver1", CK_ZNVER1) 1644 .Case("x86-64", CK_x86_64) 1645 .Case("geode", CK_Geode) 1646 .Default(CK_Generic); 1647 } 1648 1649 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1650 return llvm::makeArrayRef(GCCRegNames); 1651 } 1652 1653 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1654 return llvm::makeArrayRef(AddlRegNames); 1655 } 1656 1657 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1658 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1659 Builtin::FirstTSBuiltin + 1); 1660 } 1661 1662 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1663 return llvm::makeArrayRef(BuiltinInfoX86, 1664 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1665 } 1666