1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabled(Features, "sse2", true); 112 113 using namespace llvm::X86; 114 115 SmallVector<StringRef, 16> CPUFeatures; 116 getFeaturesForCPU(CPU, CPUFeatures); 117 for (auto &F : CPUFeatures) 118 setFeatureEnabled(Features, F, true); 119 120 std::vector<std::string> UpdatedFeaturesVec; 121 for (const auto &Feature : FeaturesVec) { 122 // Expand general-regs-only to -x86, -mmx and -sse 123 if (Feature == "+general-regs-only") { 124 UpdatedFeaturesVec.push_back("-x87"); 125 UpdatedFeaturesVec.push_back("-mmx"); 126 UpdatedFeaturesVec.push_back("-sse"); 127 continue; 128 } 129 130 UpdatedFeaturesVec.push_back(Feature); 131 } 132 133 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec)) 134 return false; 135 136 // Can't do this earlier because we need to be able to explicitly enable 137 // or disable these features and the things that they depend upon. 138 139 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 140 auto I = Features.find("sse4.2"); 141 if (I != Features.end() && I->getValue() && 142 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt")) 143 Features["popcnt"] = true; 144 145 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 146 // then enable MMX. 147 I = Features.find("sse"); 148 if (I != Features.end() && I->getValue() && 149 !llvm::is_contained(UpdatedFeaturesVec, "-mmx")) 150 Features["mmx"] = true; 151 152 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 153 I = Features.find("avx"); 154 if (I != Features.end() && I->getValue() && 155 !llvm::is_contained(UpdatedFeaturesVec, "-xsave")) 156 Features["xsave"] = true; 157 158 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled. 159 I = Features.find("sse4.2"); 160 if (I != Features.end() && I->getValue() && 161 !llvm::is_contained(UpdatedFeaturesVec, "-crc32")) 162 Features["crc32"] = true; 163 164 return true; 165 } 166 167 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 168 StringRef Name, bool Enabled) const { 169 if (Name == "sse4") { 170 // We can get here via the __target__ attribute since that's not controlled 171 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 172 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 173 // disabled. 174 if (Enabled) 175 Name = "sse4.2"; 176 else 177 Name = "sse4.1"; 178 } 179 180 Features[Name] = Enabled; 181 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 182 } 183 184 /// handleTargetFeatures - Perform initialization based on the user 185 /// configured set of features. 186 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 187 DiagnosticsEngine &Diags) { 188 for (const auto &Feature : Features) { 189 if (Feature[0] != '+') 190 continue; 191 192 if (Feature == "+aes") { 193 HasAES = true; 194 } else if (Feature == "+vaes") { 195 HasVAES = true; 196 } else if (Feature == "+pclmul") { 197 HasPCLMUL = true; 198 } else if (Feature == "+vpclmulqdq") { 199 HasVPCLMULQDQ = true; 200 } else if (Feature == "+lzcnt") { 201 HasLZCNT = true; 202 } else if (Feature == "+rdrnd") { 203 HasRDRND = true; 204 } else if (Feature == "+fsgsbase") { 205 HasFSGSBASE = true; 206 } else if (Feature == "+bmi") { 207 HasBMI = true; 208 } else if (Feature == "+bmi2") { 209 HasBMI2 = true; 210 } else if (Feature == "+popcnt") { 211 HasPOPCNT = true; 212 } else if (Feature == "+rtm") { 213 HasRTM = true; 214 } else if (Feature == "+prfchw") { 215 HasPRFCHW = true; 216 } else if (Feature == "+rdseed") { 217 HasRDSEED = true; 218 } else if (Feature == "+adx") { 219 HasADX = true; 220 } else if (Feature == "+tbm") { 221 HasTBM = true; 222 } else if (Feature == "+lwp") { 223 HasLWP = true; 224 } else if (Feature == "+fma") { 225 HasFMA = true; 226 } else if (Feature == "+f16c") { 227 HasF16C = true; 228 } else if (Feature == "+gfni") { 229 HasGFNI = true; 230 } else if (Feature == "+avx512cd") { 231 HasAVX512CD = true; 232 } else if (Feature == "+avx512vpopcntdq") { 233 HasAVX512VPOPCNTDQ = true; 234 } else if (Feature == "+avx512vnni") { 235 HasAVX512VNNI = true; 236 } else if (Feature == "+avx512bf16") { 237 HasAVX512BF16 = true; 238 } else if (Feature == "+avx512er") { 239 HasAVX512ER = true; 240 } else if (Feature == "+avx512fp16") { 241 HasAVX512FP16 = true; 242 HasFloat16 = true; 243 } else if (Feature == "+avx512pf") { 244 HasAVX512PF = true; 245 } else if (Feature == "+avx512dq") { 246 HasAVX512DQ = true; 247 } else if (Feature == "+avx512bitalg") { 248 HasAVX512BITALG = true; 249 } else if (Feature == "+avx512bw") { 250 HasAVX512BW = true; 251 } else if (Feature == "+avx512vl") { 252 HasAVX512VL = true; 253 } else if (Feature == "+avx512vbmi") { 254 HasAVX512VBMI = true; 255 } else if (Feature == "+avx512vbmi2") { 256 HasAVX512VBMI2 = true; 257 } else if (Feature == "+avx512ifma") { 258 HasAVX512IFMA = true; 259 } else if (Feature == "+avx512vp2intersect") { 260 HasAVX512VP2INTERSECT = true; 261 } else if (Feature == "+sha") { 262 HasSHA = true; 263 } else if (Feature == "+shstk") { 264 HasSHSTK = true; 265 } else if (Feature == "+movbe") { 266 HasMOVBE = true; 267 } else if (Feature == "+sgx") { 268 HasSGX = true; 269 } else if (Feature == "+cx8") { 270 HasCX8 = true; 271 } else if (Feature == "+cx16") { 272 HasCX16 = true; 273 } else if (Feature == "+fxsr") { 274 HasFXSR = true; 275 } else if (Feature == "+xsave") { 276 HasXSAVE = true; 277 } else if (Feature == "+xsaveopt") { 278 HasXSAVEOPT = true; 279 } else if (Feature == "+xsavec") { 280 HasXSAVEC = true; 281 } else if (Feature == "+xsaves") { 282 HasXSAVES = true; 283 } else if (Feature == "+mwaitx") { 284 HasMWAITX = true; 285 } else if (Feature == "+pku") { 286 HasPKU = true; 287 } else if (Feature == "+clflushopt") { 288 HasCLFLUSHOPT = true; 289 } else if (Feature == "+clwb") { 290 HasCLWB = true; 291 } else if (Feature == "+wbnoinvd") { 292 HasWBNOINVD = true; 293 } else if (Feature == "+prefetchwt1") { 294 HasPREFETCHWT1 = true; 295 } else if (Feature == "+clzero") { 296 HasCLZERO = true; 297 } else if (Feature == "+cldemote") { 298 HasCLDEMOTE = true; 299 } else if (Feature == "+rdpid") { 300 HasRDPID = true; 301 } else if (Feature == "+kl") { 302 HasKL = true; 303 } else if (Feature == "+widekl") { 304 HasWIDEKL = true; 305 } else if (Feature == "+retpoline-external-thunk") { 306 HasRetpolineExternalThunk = true; 307 } else if (Feature == "+sahf") { 308 HasLAHFSAHF = true; 309 } else if (Feature == "+waitpkg") { 310 HasWAITPKG = true; 311 } else if (Feature == "+movdiri") { 312 HasMOVDIRI = true; 313 } else if (Feature == "+movdir64b") { 314 HasMOVDIR64B = true; 315 } else if (Feature == "+pconfig") { 316 HasPCONFIG = true; 317 } else if (Feature == "+ptwrite") { 318 HasPTWRITE = true; 319 } else if (Feature == "+invpcid") { 320 HasINVPCID = true; 321 } else if (Feature == "+enqcmd") { 322 HasENQCMD = true; 323 } else if (Feature == "+hreset") { 324 HasHRESET = true; 325 } else if (Feature == "+amx-bf16") { 326 HasAMXBF16 = true; 327 } else if (Feature == "+amx-int8") { 328 HasAMXINT8 = true; 329 } else if (Feature == "+amx-tile") { 330 HasAMXTILE = true; 331 } else if (Feature == "+avxvnni") { 332 HasAVXVNNI = true; 333 } else if (Feature == "+serialize") { 334 HasSERIALIZE = true; 335 } else if (Feature == "+tsxldtrk") { 336 HasTSXLDTRK = true; 337 } else if (Feature == "+uintr") { 338 HasUINTR = true; 339 } else if (Feature == "+crc32") { 340 HasCRC32 = true; 341 } else if (Feature == "+x87") { 342 HasX87 = true; 343 } 344 345 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 346 .Case("+avx512f", AVX512F) 347 .Case("+avx2", AVX2) 348 .Case("+avx", AVX) 349 .Case("+sse4.2", SSE42) 350 .Case("+sse4.1", SSE41) 351 .Case("+ssse3", SSSE3) 352 .Case("+sse3", SSE3) 353 .Case("+sse2", SSE2) 354 .Case("+sse", SSE1) 355 .Default(NoSSE); 356 SSELevel = std::max(SSELevel, Level); 357 358 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 359 .Case("+3dnowa", AMD3DNowAthlon) 360 .Case("+3dnow", AMD3DNow) 361 .Case("+mmx", MMX) 362 .Default(NoMMX3DNow); 363 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 364 365 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 366 .Case("+xop", XOP) 367 .Case("+fma4", FMA4) 368 .Case("+sse4a", SSE4A) 369 .Default(NoXOP); 370 XOPLevel = std::max(XOPLevel, XLevel); 371 } 372 373 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 374 // matches the selected sse level. 375 if ((FPMath == FP_SSE && SSELevel < SSE1) || 376 (FPMath == FP_387 && SSELevel >= SSE1)) { 377 Diags.Report(diag::err_target_unsupported_fpmath) 378 << (FPMath == FP_SSE ? "sse" : "387"); 379 return false; 380 } 381 382 SimdDefaultAlign = 383 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 384 385 if (!HasX87) { 386 if (LongDoubleFormat == &llvm::APFloat::x87DoubleExtended()) 387 HasLongDouble = false; 388 if (getTriple().getArch() == llvm::Triple::x86) 389 HasFPReturn = false; 390 } 391 392 return true; 393 } 394 395 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 396 /// definitions for this particular subtarget. 397 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 398 MacroBuilder &Builder) const { 399 // Inline assembly supports X86 flag outputs. 400 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 401 402 std::string CodeModel = getTargetOpts().CodeModel; 403 if (CodeModel == "default") 404 CodeModel = "small"; 405 Builder.defineMacro("__code_model_" + CodeModel + "__"); 406 407 // Target identification. 408 if (getTriple().getArch() == llvm::Triple::x86_64) { 409 Builder.defineMacro("__amd64__"); 410 Builder.defineMacro("__amd64"); 411 Builder.defineMacro("__x86_64"); 412 Builder.defineMacro("__x86_64__"); 413 if (getTriple().getArchName() == "x86_64h") { 414 Builder.defineMacro("__x86_64h"); 415 Builder.defineMacro("__x86_64h__"); 416 } 417 } else { 418 DefineStd(Builder, "i386", Opts); 419 } 420 421 Builder.defineMacro("__SEG_GS"); 422 Builder.defineMacro("__SEG_FS"); 423 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 424 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 425 426 // Subtarget options. 427 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 428 // truly should be based on -mtune options. 429 using namespace llvm::X86; 430 switch (CPU) { 431 case CK_None: 432 break; 433 case CK_i386: 434 // The rest are coming from the i386 define above. 435 Builder.defineMacro("__tune_i386__"); 436 break; 437 case CK_i486: 438 case CK_WinChipC6: 439 case CK_WinChip2: 440 case CK_C3: 441 defineCPUMacros(Builder, "i486"); 442 break; 443 case CK_PentiumMMX: 444 Builder.defineMacro("__pentium_mmx__"); 445 Builder.defineMacro("__tune_pentium_mmx__"); 446 LLVM_FALLTHROUGH; 447 case CK_i586: 448 case CK_Pentium: 449 defineCPUMacros(Builder, "i586"); 450 defineCPUMacros(Builder, "pentium"); 451 break; 452 case CK_Pentium3: 453 case CK_PentiumM: 454 Builder.defineMacro("__tune_pentium3__"); 455 LLVM_FALLTHROUGH; 456 case CK_Pentium2: 457 case CK_C3_2: 458 Builder.defineMacro("__tune_pentium2__"); 459 LLVM_FALLTHROUGH; 460 case CK_PentiumPro: 461 case CK_i686: 462 defineCPUMacros(Builder, "i686"); 463 defineCPUMacros(Builder, "pentiumpro"); 464 break; 465 case CK_Pentium4: 466 defineCPUMacros(Builder, "pentium4"); 467 break; 468 case CK_Yonah: 469 case CK_Prescott: 470 case CK_Nocona: 471 defineCPUMacros(Builder, "nocona"); 472 break; 473 case CK_Core2: 474 case CK_Penryn: 475 defineCPUMacros(Builder, "core2"); 476 break; 477 case CK_Bonnell: 478 defineCPUMacros(Builder, "atom"); 479 break; 480 case CK_Silvermont: 481 defineCPUMacros(Builder, "slm"); 482 break; 483 case CK_Goldmont: 484 defineCPUMacros(Builder, "goldmont"); 485 break; 486 case CK_GoldmontPlus: 487 defineCPUMacros(Builder, "goldmont_plus"); 488 break; 489 case CK_Tremont: 490 defineCPUMacros(Builder, "tremont"); 491 break; 492 case CK_Nehalem: 493 case CK_Westmere: 494 case CK_SandyBridge: 495 case CK_IvyBridge: 496 case CK_Haswell: 497 case CK_Broadwell: 498 case CK_SkylakeClient: 499 case CK_SkylakeServer: 500 case CK_Cascadelake: 501 case CK_Cooperlake: 502 case CK_Cannonlake: 503 case CK_IcelakeClient: 504 case CK_Rocketlake: 505 case CK_IcelakeServer: 506 case CK_Tigerlake: 507 case CK_SapphireRapids: 508 case CK_Alderlake: 509 // FIXME: Historically, we defined this legacy name, it would be nice to 510 // remove it at some point. We've never exposed fine-grained names for 511 // recent primary x86 CPUs, and we should keep it that way. 512 defineCPUMacros(Builder, "corei7"); 513 break; 514 case CK_KNL: 515 defineCPUMacros(Builder, "knl"); 516 break; 517 case CK_KNM: 518 break; 519 case CK_Lakemont: 520 defineCPUMacros(Builder, "i586", /*Tuning*/false); 521 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 522 Builder.defineMacro("__tune_lakemont__"); 523 break; 524 case CK_K6_2: 525 Builder.defineMacro("__k6_2__"); 526 Builder.defineMacro("__tune_k6_2__"); 527 LLVM_FALLTHROUGH; 528 case CK_K6_3: 529 if (CPU != CK_K6_2) { // In case of fallthrough 530 // FIXME: GCC may be enabling these in cases where some other k6 531 // architecture is specified but -m3dnow is explicitly provided. The 532 // exact semantics need to be determined and emulated here. 533 Builder.defineMacro("__k6_3__"); 534 Builder.defineMacro("__tune_k6_3__"); 535 } 536 LLVM_FALLTHROUGH; 537 case CK_K6: 538 defineCPUMacros(Builder, "k6"); 539 break; 540 case CK_Athlon: 541 case CK_AthlonXP: 542 defineCPUMacros(Builder, "athlon"); 543 if (SSELevel != NoSSE) { 544 Builder.defineMacro("__athlon_sse__"); 545 Builder.defineMacro("__tune_athlon_sse__"); 546 } 547 break; 548 case CK_K8: 549 case CK_K8SSE3: 550 case CK_x86_64: 551 defineCPUMacros(Builder, "k8"); 552 break; 553 case CK_x86_64_v2: 554 case CK_x86_64_v3: 555 case CK_x86_64_v4: 556 break; 557 case CK_AMDFAM10: 558 defineCPUMacros(Builder, "amdfam10"); 559 break; 560 case CK_BTVER1: 561 defineCPUMacros(Builder, "btver1"); 562 break; 563 case CK_BTVER2: 564 defineCPUMacros(Builder, "btver2"); 565 break; 566 case CK_BDVER1: 567 defineCPUMacros(Builder, "bdver1"); 568 break; 569 case CK_BDVER2: 570 defineCPUMacros(Builder, "bdver2"); 571 break; 572 case CK_BDVER3: 573 defineCPUMacros(Builder, "bdver3"); 574 break; 575 case CK_BDVER4: 576 defineCPUMacros(Builder, "bdver4"); 577 break; 578 case CK_ZNVER1: 579 defineCPUMacros(Builder, "znver1"); 580 break; 581 case CK_ZNVER2: 582 defineCPUMacros(Builder, "znver2"); 583 break; 584 case CK_ZNVER3: 585 defineCPUMacros(Builder, "znver3"); 586 break; 587 case CK_Geode: 588 defineCPUMacros(Builder, "geode"); 589 break; 590 } 591 592 // Target properties. 593 Builder.defineMacro("__REGISTER_PREFIX__", ""); 594 595 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 596 // functions in glibc header files that use FP Stack inline asm which the 597 // backend can't deal with (PR879). 598 Builder.defineMacro("__NO_MATH_INLINES"); 599 600 if (HasAES) 601 Builder.defineMacro("__AES__"); 602 603 if (HasVAES) 604 Builder.defineMacro("__VAES__"); 605 606 if (HasPCLMUL) 607 Builder.defineMacro("__PCLMUL__"); 608 609 if (HasVPCLMULQDQ) 610 Builder.defineMacro("__VPCLMULQDQ__"); 611 612 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, 613 // the feature flag only applies to 64-bit mode. 614 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86) 615 Builder.defineMacro("__LAHF_SAHF__"); 616 617 if (HasLZCNT) 618 Builder.defineMacro("__LZCNT__"); 619 620 if (HasRDRND) 621 Builder.defineMacro("__RDRND__"); 622 623 if (HasFSGSBASE) 624 Builder.defineMacro("__FSGSBASE__"); 625 626 if (HasBMI) 627 Builder.defineMacro("__BMI__"); 628 629 if (HasBMI2) 630 Builder.defineMacro("__BMI2__"); 631 632 if (HasPOPCNT) 633 Builder.defineMacro("__POPCNT__"); 634 635 if (HasRTM) 636 Builder.defineMacro("__RTM__"); 637 638 if (HasPRFCHW) 639 Builder.defineMacro("__PRFCHW__"); 640 641 if (HasRDSEED) 642 Builder.defineMacro("__RDSEED__"); 643 644 if (HasADX) 645 Builder.defineMacro("__ADX__"); 646 647 if (HasTBM) 648 Builder.defineMacro("__TBM__"); 649 650 if (HasLWP) 651 Builder.defineMacro("__LWP__"); 652 653 if (HasMWAITX) 654 Builder.defineMacro("__MWAITX__"); 655 656 if (HasMOVBE) 657 Builder.defineMacro("__MOVBE__"); 658 659 switch (XOPLevel) { 660 case XOP: 661 Builder.defineMacro("__XOP__"); 662 LLVM_FALLTHROUGH; 663 case FMA4: 664 Builder.defineMacro("__FMA4__"); 665 LLVM_FALLTHROUGH; 666 case SSE4A: 667 Builder.defineMacro("__SSE4A__"); 668 LLVM_FALLTHROUGH; 669 case NoXOP: 670 break; 671 } 672 673 if (HasFMA) 674 Builder.defineMacro("__FMA__"); 675 676 if (HasF16C) 677 Builder.defineMacro("__F16C__"); 678 679 if (HasGFNI) 680 Builder.defineMacro("__GFNI__"); 681 682 if (HasAVX512CD) 683 Builder.defineMacro("__AVX512CD__"); 684 if (HasAVX512VPOPCNTDQ) 685 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 686 if (HasAVX512VNNI) 687 Builder.defineMacro("__AVX512VNNI__"); 688 if (HasAVX512BF16) 689 Builder.defineMacro("__AVX512BF16__"); 690 if (HasAVX512ER) 691 Builder.defineMacro("__AVX512ER__"); 692 if (HasAVX512FP16) 693 Builder.defineMacro("__AVX512FP16__"); 694 if (HasAVX512PF) 695 Builder.defineMacro("__AVX512PF__"); 696 if (HasAVX512DQ) 697 Builder.defineMacro("__AVX512DQ__"); 698 if (HasAVX512BITALG) 699 Builder.defineMacro("__AVX512BITALG__"); 700 if (HasAVX512BW) 701 Builder.defineMacro("__AVX512BW__"); 702 if (HasAVX512VL) 703 Builder.defineMacro("__AVX512VL__"); 704 if (HasAVX512VBMI) 705 Builder.defineMacro("__AVX512VBMI__"); 706 if (HasAVX512VBMI2) 707 Builder.defineMacro("__AVX512VBMI2__"); 708 if (HasAVX512IFMA) 709 Builder.defineMacro("__AVX512IFMA__"); 710 if (HasAVX512VP2INTERSECT) 711 Builder.defineMacro("__AVX512VP2INTERSECT__"); 712 if (HasSHA) 713 Builder.defineMacro("__SHA__"); 714 715 if (HasFXSR) 716 Builder.defineMacro("__FXSR__"); 717 if (HasXSAVE) 718 Builder.defineMacro("__XSAVE__"); 719 if (HasXSAVEOPT) 720 Builder.defineMacro("__XSAVEOPT__"); 721 if (HasXSAVEC) 722 Builder.defineMacro("__XSAVEC__"); 723 if (HasXSAVES) 724 Builder.defineMacro("__XSAVES__"); 725 if (HasPKU) 726 Builder.defineMacro("__PKU__"); 727 if (HasCLFLUSHOPT) 728 Builder.defineMacro("__CLFLUSHOPT__"); 729 if (HasCLWB) 730 Builder.defineMacro("__CLWB__"); 731 if (HasWBNOINVD) 732 Builder.defineMacro("__WBNOINVD__"); 733 if (HasSHSTK) 734 Builder.defineMacro("__SHSTK__"); 735 if (HasSGX) 736 Builder.defineMacro("__SGX__"); 737 if (HasPREFETCHWT1) 738 Builder.defineMacro("__PREFETCHWT1__"); 739 if (HasCLZERO) 740 Builder.defineMacro("__CLZERO__"); 741 if (HasKL) 742 Builder.defineMacro("__KL__"); 743 if (HasWIDEKL) 744 Builder.defineMacro("__WIDEKL__"); 745 if (HasRDPID) 746 Builder.defineMacro("__RDPID__"); 747 if (HasCLDEMOTE) 748 Builder.defineMacro("__CLDEMOTE__"); 749 if (HasWAITPKG) 750 Builder.defineMacro("__WAITPKG__"); 751 if (HasMOVDIRI) 752 Builder.defineMacro("__MOVDIRI__"); 753 if (HasMOVDIR64B) 754 Builder.defineMacro("__MOVDIR64B__"); 755 if (HasPCONFIG) 756 Builder.defineMacro("__PCONFIG__"); 757 if (HasPTWRITE) 758 Builder.defineMacro("__PTWRITE__"); 759 if (HasINVPCID) 760 Builder.defineMacro("__INVPCID__"); 761 if (HasENQCMD) 762 Builder.defineMacro("__ENQCMD__"); 763 if (HasHRESET) 764 Builder.defineMacro("__HRESET__"); 765 if (HasAMXTILE) 766 Builder.defineMacro("__AMXTILE__"); 767 if (HasAMXINT8) 768 Builder.defineMacro("__AMXINT8__"); 769 if (HasAMXBF16) 770 Builder.defineMacro("__AMXBF16__"); 771 if (HasAVXVNNI) 772 Builder.defineMacro("__AVXVNNI__"); 773 if (HasSERIALIZE) 774 Builder.defineMacro("__SERIALIZE__"); 775 if (HasTSXLDTRK) 776 Builder.defineMacro("__TSXLDTRK__"); 777 if (HasUINTR) 778 Builder.defineMacro("__UINTR__"); 779 if (HasCRC32) 780 Builder.defineMacro("__CRC32__"); 781 782 // Each case falls through to the previous one here. 783 switch (SSELevel) { 784 case AVX512F: 785 Builder.defineMacro("__AVX512F__"); 786 LLVM_FALLTHROUGH; 787 case AVX2: 788 Builder.defineMacro("__AVX2__"); 789 LLVM_FALLTHROUGH; 790 case AVX: 791 Builder.defineMacro("__AVX__"); 792 LLVM_FALLTHROUGH; 793 case SSE42: 794 Builder.defineMacro("__SSE4_2__"); 795 LLVM_FALLTHROUGH; 796 case SSE41: 797 Builder.defineMacro("__SSE4_1__"); 798 LLVM_FALLTHROUGH; 799 case SSSE3: 800 Builder.defineMacro("__SSSE3__"); 801 LLVM_FALLTHROUGH; 802 case SSE3: 803 Builder.defineMacro("__SSE3__"); 804 LLVM_FALLTHROUGH; 805 case SSE2: 806 Builder.defineMacro("__SSE2__"); 807 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 808 LLVM_FALLTHROUGH; 809 case SSE1: 810 Builder.defineMacro("__SSE__"); 811 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 812 LLVM_FALLTHROUGH; 813 case NoSSE: 814 break; 815 } 816 817 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 818 switch (SSELevel) { 819 case AVX512F: 820 case AVX2: 821 case AVX: 822 case SSE42: 823 case SSE41: 824 case SSSE3: 825 case SSE3: 826 case SSE2: 827 Builder.defineMacro("_M_IX86_FP", Twine(2)); 828 break; 829 case SSE1: 830 Builder.defineMacro("_M_IX86_FP", Twine(1)); 831 break; 832 default: 833 Builder.defineMacro("_M_IX86_FP", Twine(0)); 834 break; 835 } 836 } 837 838 // Each case falls through to the previous one here. 839 switch (MMX3DNowLevel) { 840 case AMD3DNowAthlon: 841 Builder.defineMacro("__3dNOW_A__"); 842 LLVM_FALLTHROUGH; 843 case AMD3DNow: 844 Builder.defineMacro("__3dNOW__"); 845 LLVM_FALLTHROUGH; 846 case MMX: 847 Builder.defineMacro("__MMX__"); 848 LLVM_FALLTHROUGH; 849 case NoMMX3DNow: 850 break; 851 } 852 853 if (CPU >= CK_i486 || CPU == CK_None) { 854 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 855 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 856 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 857 } 858 if (HasCX8) 859 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 860 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 861 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 862 863 if (HasFloat128) 864 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 865 } 866 867 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 868 return llvm::StringSwitch<bool>(Name) 869 .Case("3dnow", true) 870 .Case("3dnowa", true) 871 .Case("adx", true) 872 .Case("aes", true) 873 .Case("amx-bf16", true) 874 .Case("amx-int8", true) 875 .Case("amx-tile", true) 876 .Case("avx", true) 877 .Case("avx2", true) 878 .Case("avx512f", true) 879 .Case("avx512cd", true) 880 .Case("avx512vpopcntdq", true) 881 .Case("avx512vnni", true) 882 .Case("avx512bf16", true) 883 .Case("avx512er", true) 884 .Case("avx512fp16", true) 885 .Case("avx512pf", true) 886 .Case("avx512dq", true) 887 .Case("avx512bitalg", true) 888 .Case("avx512bw", true) 889 .Case("avx512vl", true) 890 .Case("avx512vbmi", true) 891 .Case("avx512vbmi2", true) 892 .Case("avx512ifma", true) 893 .Case("avx512vp2intersect", true) 894 .Case("avxvnni", true) 895 .Case("bmi", true) 896 .Case("bmi2", true) 897 .Case("cldemote", true) 898 .Case("clflushopt", true) 899 .Case("clwb", true) 900 .Case("clzero", true) 901 .Case("crc32", true) 902 .Case("cx16", true) 903 .Case("enqcmd", true) 904 .Case("f16c", true) 905 .Case("fma", true) 906 .Case("fma4", true) 907 .Case("fsgsbase", true) 908 .Case("fxsr", true) 909 .Case("general-regs-only", true) 910 .Case("gfni", true) 911 .Case("hreset", true) 912 .Case("invpcid", true) 913 .Case("kl", true) 914 .Case("widekl", true) 915 .Case("lwp", true) 916 .Case("lzcnt", true) 917 .Case("mmx", true) 918 .Case("movbe", true) 919 .Case("movdiri", true) 920 .Case("movdir64b", true) 921 .Case("mwaitx", true) 922 .Case("pclmul", true) 923 .Case("pconfig", true) 924 .Case("pku", true) 925 .Case("popcnt", true) 926 .Case("prefetchwt1", true) 927 .Case("prfchw", true) 928 .Case("ptwrite", true) 929 .Case("rdpid", true) 930 .Case("rdrnd", true) 931 .Case("rdseed", true) 932 .Case("rtm", true) 933 .Case("sahf", true) 934 .Case("serialize", true) 935 .Case("sgx", true) 936 .Case("sha", true) 937 .Case("shstk", true) 938 .Case("sse", true) 939 .Case("sse2", true) 940 .Case("sse3", true) 941 .Case("ssse3", true) 942 .Case("sse4", true) 943 .Case("sse4.1", true) 944 .Case("sse4.2", true) 945 .Case("sse4a", true) 946 .Case("tbm", true) 947 .Case("tsxldtrk", true) 948 .Case("uintr", true) 949 .Case("vaes", true) 950 .Case("vpclmulqdq", true) 951 .Case("wbnoinvd", true) 952 .Case("waitpkg", true) 953 .Case("x87", true) 954 .Case("xop", true) 955 .Case("xsave", true) 956 .Case("xsavec", true) 957 .Case("xsaves", true) 958 .Case("xsaveopt", true) 959 .Default(false); 960 } 961 962 bool X86TargetInfo::hasFeature(StringRef Feature) const { 963 return llvm::StringSwitch<bool>(Feature) 964 .Case("adx", HasADX) 965 .Case("aes", HasAES) 966 .Case("amx-bf16", HasAMXBF16) 967 .Case("amx-int8", HasAMXINT8) 968 .Case("amx-tile", HasAMXTILE) 969 .Case("avxvnni", HasAVXVNNI) 970 .Case("avx", SSELevel >= AVX) 971 .Case("avx2", SSELevel >= AVX2) 972 .Case("avx512f", SSELevel >= AVX512F) 973 .Case("avx512cd", HasAVX512CD) 974 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 975 .Case("avx512vnni", HasAVX512VNNI) 976 .Case("avx512bf16", HasAVX512BF16) 977 .Case("avx512er", HasAVX512ER) 978 .Case("avx512fp16", HasAVX512FP16) 979 .Case("avx512pf", HasAVX512PF) 980 .Case("avx512dq", HasAVX512DQ) 981 .Case("avx512bitalg", HasAVX512BITALG) 982 .Case("avx512bw", HasAVX512BW) 983 .Case("avx512vl", HasAVX512VL) 984 .Case("avx512vbmi", HasAVX512VBMI) 985 .Case("avx512vbmi2", HasAVX512VBMI2) 986 .Case("avx512ifma", HasAVX512IFMA) 987 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 988 .Case("bmi", HasBMI) 989 .Case("bmi2", HasBMI2) 990 .Case("cldemote", HasCLDEMOTE) 991 .Case("clflushopt", HasCLFLUSHOPT) 992 .Case("clwb", HasCLWB) 993 .Case("clzero", HasCLZERO) 994 .Case("crc32", HasCRC32) 995 .Case("cx8", HasCX8) 996 .Case("cx16", HasCX16) 997 .Case("enqcmd", HasENQCMD) 998 .Case("f16c", HasF16C) 999 .Case("fma", HasFMA) 1000 .Case("fma4", XOPLevel >= FMA4) 1001 .Case("fsgsbase", HasFSGSBASE) 1002 .Case("fxsr", HasFXSR) 1003 .Case("gfni", HasGFNI) 1004 .Case("hreset", HasHRESET) 1005 .Case("invpcid", HasINVPCID) 1006 .Case("kl", HasKL) 1007 .Case("widekl", HasWIDEKL) 1008 .Case("lwp", HasLWP) 1009 .Case("lzcnt", HasLZCNT) 1010 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1011 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1012 .Case("mmx", MMX3DNowLevel >= MMX) 1013 .Case("movbe", HasMOVBE) 1014 .Case("movdiri", HasMOVDIRI) 1015 .Case("movdir64b", HasMOVDIR64B) 1016 .Case("mwaitx", HasMWAITX) 1017 .Case("pclmul", HasPCLMUL) 1018 .Case("pconfig", HasPCONFIG) 1019 .Case("pku", HasPKU) 1020 .Case("popcnt", HasPOPCNT) 1021 .Case("prefetchwt1", HasPREFETCHWT1) 1022 .Case("prfchw", HasPRFCHW) 1023 .Case("ptwrite", HasPTWRITE) 1024 .Case("rdpid", HasRDPID) 1025 .Case("rdrnd", HasRDRND) 1026 .Case("rdseed", HasRDSEED) 1027 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1028 .Case("rtm", HasRTM) 1029 .Case("sahf", HasLAHFSAHF) 1030 .Case("serialize", HasSERIALIZE) 1031 .Case("sgx", HasSGX) 1032 .Case("sha", HasSHA) 1033 .Case("shstk", HasSHSTK) 1034 .Case("sse", SSELevel >= SSE1) 1035 .Case("sse2", SSELevel >= SSE2) 1036 .Case("sse3", SSELevel >= SSE3) 1037 .Case("ssse3", SSELevel >= SSSE3) 1038 .Case("sse4.1", SSELevel >= SSE41) 1039 .Case("sse4.2", SSELevel >= SSE42) 1040 .Case("sse4a", XOPLevel >= SSE4A) 1041 .Case("tbm", HasTBM) 1042 .Case("tsxldtrk", HasTSXLDTRK) 1043 .Case("uintr", HasUINTR) 1044 .Case("vaes", HasVAES) 1045 .Case("vpclmulqdq", HasVPCLMULQDQ) 1046 .Case("wbnoinvd", HasWBNOINVD) 1047 .Case("waitpkg", HasWAITPKG) 1048 .Case("x86", true) 1049 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1050 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1051 .Case("x87", HasX87) 1052 .Case("xop", XOPLevel >= XOP) 1053 .Case("xsave", HasXSAVE) 1054 .Case("xsavec", HasXSAVEC) 1055 .Case("xsaves", HasXSAVES) 1056 .Case("xsaveopt", HasXSAVEOPT) 1057 .Default(false); 1058 } 1059 1060 // We can't use a generic validation scheme for the features accepted here 1061 // versus subtarget features accepted in the target attribute because the 1062 // bitfield structure that's initialized in the runtime only supports the 1063 // below currently rather than the full range of subtarget features. (See 1064 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1065 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1066 return llvm::StringSwitch<bool>(FeatureStr) 1067 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true) 1068 #include "llvm/Support/X86TargetParser.def" 1069 .Default(false); 1070 } 1071 1072 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1073 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1074 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ 1075 .Case(STR, llvm::X86::FEATURE_##ENUM) 1076 1077 #include "llvm/Support/X86TargetParser.def" 1078 ; 1079 // Note, this function should only be used after ensuring the value is 1080 // correct, so it asserts if the value is out of range. 1081 } 1082 1083 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1084 // Valid CPUs have a 'key feature' that compares just better than its key 1085 // feature. 1086 using namespace llvm::X86; 1087 CPUKind Kind = parseArchX86(Name); 1088 if (Kind != CK_None) { 1089 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1090 return (getFeaturePriority(KeyFeature) << 1) + 1; 1091 } 1092 1093 // Now we know we have a feature, so get its priority and shift it a few so 1094 // that we have sufficient room for the CPUs (above). 1095 return getFeaturePriority(getFeature(Name)) << 1; 1096 } 1097 1098 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1099 return llvm::StringSwitch<bool>(Name) 1100 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1101 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1102 #include "llvm/Support/X86TargetParser.def" 1103 .Default(false); 1104 } 1105 1106 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1107 return llvm::StringSwitch<StringRef>(Name) 1108 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1109 #include "llvm/Support/X86TargetParser.def" 1110 .Default(Name); 1111 } 1112 1113 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1114 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1115 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1116 #include "llvm/Support/X86TargetParser.def" 1117 .Default(0); 1118 } 1119 1120 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1121 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1122 StringRef WholeList = 1123 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1124 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1125 #include "llvm/Support/X86TargetParser.def" 1126 .Default(""); 1127 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1128 } 1129 1130 // We can't use a generic validation scheme for the cpus accepted here 1131 // versus subtarget cpus accepted in the target attribute because the 1132 // variables intitialized by the runtime only support the below currently 1133 // rather than the full range of cpus. 1134 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1135 return llvm::StringSwitch<bool>(FeatureStr) 1136 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1137 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1138 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1139 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1140 #include "llvm/Support/X86TargetParser.def" 1141 .Default(false); 1142 } 1143 1144 static unsigned matchAsmCCConstraint(const char *&Name) { 1145 auto RV = llvm::StringSwitch<unsigned>(Name) 1146 .Case("@cca", 4) 1147 .Case("@ccae", 5) 1148 .Case("@ccb", 4) 1149 .Case("@ccbe", 5) 1150 .Case("@ccc", 4) 1151 .Case("@cce", 4) 1152 .Case("@ccz", 4) 1153 .Case("@ccg", 4) 1154 .Case("@ccge", 5) 1155 .Case("@ccl", 4) 1156 .Case("@ccle", 5) 1157 .Case("@ccna", 5) 1158 .Case("@ccnae", 6) 1159 .Case("@ccnb", 5) 1160 .Case("@ccnbe", 6) 1161 .Case("@ccnc", 5) 1162 .Case("@ccne", 5) 1163 .Case("@ccnz", 5) 1164 .Case("@ccng", 5) 1165 .Case("@ccnge", 6) 1166 .Case("@ccnl", 5) 1167 .Case("@ccnle", 6) 1168 .Case("@ccno", 5) 1169 .Case("@ccnp", 5) 1170 .Case("@ccns", 5) 1171 .Case("@cco", 4) 1172 .Case("@ccp", 4) 1173 .Case("@ccs", 4) 1174 .Default(0); 1175 return RV; 1176 } 1177 1178 bool X86TargetInfo::validateAsmConstraint( 1179 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1180 switch (*Name) { 1181 default: 1182 return false; 1183 // Constant constraints. 1184 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1185 // instructions. 1186 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1187 // x86_64 instructions. 1188 case 's': 1189 Info.setRequiresImmediate(); 1190 return true; 1191 case 'I': 1192 Info.setRequiresImmediate(0, 31); 1193 return true; 1194 case 'J': 1195 Info.setRequiresImmediate(0, 63); 1196 return true; 1197 case 'K': 1198 Info.setRequiresImmediate(-128, 127); 1199 return true; 1200 case 'L': 1201 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1202 return true; 1203 case 'M': 1204 Info.setRequiresImmediate(0, 3); 1205 return true; 1206 case 'N': 1207 Info.setRequiresImmediate(0, 255); 1208 return true; 1209 case 'O': 1210 Info.setRequiresImmediate(0, 127); 1211 return true; 1212 // Register constraints. 1213 case 'Y': // 'Y' is the first character for several 2-character constraints. 1214 // Shift the pointer to the second character of the constraint. 1215 Name++; 1216 switch (*Name) { 1217 default: 1218 return false; 1219 case 'z': // First SSE register. 1220 case '2': 1221 case 't': // Any SSE register, when SSE2 is enabled. 1222 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1223 case 'm': // Any MMX register, when inter-unit moves enabled. 1224 case 'k': // AVX512 arch mask registers: k1-k7. 1225 Info.setAllowsRegister(); 1226 return true; 1227 } 1228 case 'f': // Any x87 floating point stack register. 1229 // Constraint 'f' cannot be used for output operands. 1230 if (Info.ConstraintStr[0] == '=') 1231 return false; 1232 Info.setAllowsRegister(); 1233 return true; 1234 case 'a': // eax. 1235 case 'b': // ebx. 1236 case 'c': // ecx. 1237 case 'd': // edx. 1238 case 'S': // esi. 1239 case 'D': // edi. 1240 case 'A': // edx:eax. 1241 case 't': // Top of floating point stack. 1242 case 'u': // Second from top of floating point stack. 1243 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1244 case 'y': // Any MMX register. 1245 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1246 case 'x': // Any SSE register. 1247 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1248 // for intermideate k reg operations). 1249 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1250 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1251 case 'l': // "Index" registers: any general register that can be used as an 1252 // index in a base+index memory access. 1253 Info.setAllowsRegister(); 1254 return true; 1255 // Floating point constant constraints. 1256 case 'C': // SSE floating point constant. 1257 case 'G': // x87 floating point constant. 1258 return true; 1259 case '@': 1260 // CC condition changes. 1261 if (auto Len = matchAsmCCConstraint(Name)) { 1262 Name += Len - 1; 1263 Info.setAllowsRegister(); 1264 return true; 1265 } 1266 return false; 1267 } 1268 } 1269 1270 // Below is based on the following information: 1271 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1272 // | Processor Name | Cache Line Size (Bytes) | Source | 1273 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1274 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1275 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1276 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1277 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1278 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1279 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1280 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1281 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1282 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1283 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1284 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1285 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1286 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1287 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1288 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1289 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1290 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1291 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1292 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1293 using namespace llvm::X86; 1294 switch (CPU) { 1295 // i386 1296 case CK_i386: 1297 // i486 1298 case CK_i486: 1299 case CK_WinChipC6: 1300 case CK_WinChip2: 1301 case CK_C3: 1302 // Lakemont 1303 case CK_Lakemont: 1304 return 16; 1305 1306 // i586 1307 case CK_i586: 1308 case CK_Pentium: 1309 case CK_PentiumMMX: 1310 // i686 1311 case CK_PentiumPro: 1312 case CK_i686: 1313 case CK_Pentium2: 1314 case CK_Pentium3: 1315 case CK_PentiumM: 1316 case CK_C3_2: 1317 // K6 1318 case CK_K6: 1319 case CK_K6_2: 1320 case CK_K6_3: 1321 // Geode 1322 case CK_Geode: 1323 return 32; 1324 1325 // Netburst 1326 case CK_Pentium4: 1327 case CK_Prescott: 1328 case CK_Nocona: 1329 // Atom 1330 case CK_Bonnell: 1331 case CK_Silvermont: 1332 case CK_Goldmont: 1333 case CK_GoldmontPlus: 1334 case CK_Tremont: 1335 1336 case CK_Westmere: 1337 case CK_SandyBridge: 1338 case CK_IvyBridge: 1339 case CK_Haswell: 1340 case CK_Broadwell: 1341 case CK_SkylakeClient: 1342 case CK_SkylakeServer: 1343 case CK_Cascadelake: 1344 case CK_Nehalem: 1345 case CK_Cooperlake: 1346 case CK_Cannonlake: 1347 case CK_Tigerlake: 1348 case CK_SapphireRapids: 1349 case CK_IcelakeClient: 1350 case CK_Rocketlake: 1351 case CK_IcelakeServer: 1352 case CK_Alderlake: 1353 case CK_KNL: 1354 case CK_KNM: 1355 // K7 1356 case CK_Athlon: 1357 case CK_AthlonXP: 1358 // K8 1359 case CK_K8: 1360 case CK_K8SSE3: 1361 case CK_AMDFAM10: 1362 // Bobcat 1363 case CK_BTVER1: 1364 case CK_BTVER2: 1365 // Bulldozer 1366 case CK_BDVER1: 1367 case CK_BDVER2: 1368 case CK_BDVER3: 1369 case CK_BDVER4: 1370 // Zen 1371 case CK_ZNVER1: 1372 case CK_ZNVER2: 1373 case CK_ZNVER3: 1374 // Deprecated 1375 case CK_x86_64: 1376 case CK_x86_64_v2: 1377 case CK_x86_64_v3: 1378 case CK_x86_64_v4: 1379 case CK_Yonah: 1380 case CK_Penryn: 1381 case CK_Core2: 1382 return 64; 1383 1384 // The following currently have unknown cache line sizes (but they are probably all 64): 1385 // Core 1386 case CK_None: 1387 return None; 1388 } 1389 llvm_unreachable("Unknown CPU kind"); 1390 } 1391 1392 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1393 StringRef Constraint, 1394 unsigned Size) const { 1395 // Strip off constraint modifiers. 1396 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1397 Constraint = Constraint.substr(1); 1398 1399 return validateOperandSize(FeatureMap, Constraint, Size); 1400 } 1401 1402 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1403 StringRef Constraint, 1404 unsigned Size) const { 1405 return validateOperandSize(FeatureMap, Constraint, Size); 1406 } 1407 1408 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1409 StringRef Constraint, 1410 unsigned Size) const { 1411 switch (Constraint[0]) { 1412 default: 1413 break; 1414 case 'k': 1415 // Registers k0-k7 (AVX512) size limit is 64 bit. 1416 case 'y': 1417 return Size <= 64; 1418 case 'f': 1419 case 't': 1420 case 'u': 1421 return Size <= 128; 1422 case 'Y': 1423 // 'Y' is the first character for several 2-character constraints. 1424 switch (Constraint[1]) { 1425 default: 1426 return false; 1427 case 'm': 1428 // 'Ym' is synonymous with 'y'. 1429 case 'k': 1430 return Size <= 64; 1431 case 'z': 1432 // XMM0/YMM/ZMM0 1433 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1434 // ZMM0 can be used if target supports AVX512F. 1435 return Size <= 512U; 1436 else if (hasFeatureEnabled(FeatureMap, "avx")) 1437 // YMM0 can be used if target supports AVX. 1438 return Size <= 256U; 1439 else if (hasFeatureEnabled(FeatureMap, "sse")) 1440 return Size <= 128U; 1441 return false; 1442 case 'i': 1443 case 't': 1444 case '2': 1445 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1446 if (SSELevel < SSE2) 1447 return false; 1448 break; 1449 } 1450 break; 1451 case 'v': 1452 case 'x': 1453 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1454 // 512-bit zmm registers can be used if target supports AVX512F. 1455 return Size <= 512U; 1456 else if (hasFeatureEnabled(FeatureMap, "avx")) 1457 // 256-bit ymm registers can be used if target supports AVX. 1458 return Size <= 256U; 1459 return Size <= 128U; 1460 1461 } 1462 1463 return true; 1464 } 1465 1466 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1467 switch (*Constraint) { 1468 case '@': 1469 if (auto Len = matchAsmCCConstraint(Constraint)) { 1470 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1471 Constraint += Len - 1; 1472 return Converted; 1473 } 1474 return std::string(1, *Constraint); 1475 case 'a': 1476 return std::string("{ax}"); 1477 case 'b': 1478 return std::string("{bx}"); 1479 case 'c': 1480 return std::string("{cx}"); 1481 case 'd': 1482 return std::string("{dx}"); 1483 case 'S': 1484 return std::string("{si}"); 1485 case 'D': 1486 return std::string("{di}"); 1487 case 'p': // address 1488 return std::string("im"); 1489 case 't': // top of floating point stack. 1490 return std::string("{st}"); 1491 case 'u': // second from top of floating point stack. 1492 return std::string("{st(1)}"); // second from top of floating point stack. 1493 case 'Y': 1494 switch (Constraint[1]) { 1495 default: 1496 // Break from inner switch and fall through (copy single char), 1497 // continue parsing after copying the current constraint into 1498 // the return string. 1499 break; 1500 case 'k': 1501 case 'm': 1502 case 'i': 1503 case 't': 1504 case 'z': 1505 case '2': 1506 // "^" hints llvm that this is a 2 letter constraint. 1507 // "Constraint++" is used to promote the string iterator 1508 // to the next constraint. 1509 return std::string("^") + std::string(Constraint++, 2); 1510 } 1511 LLVM_FALLTHROUGH; 1512 default: 1513 return std::string(1, *Constraint); 1514 } 1515 } 1516 1517 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1518 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1519 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1520 } 1521 1522 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1523 llvm::X86::fillValidTuneCPUList(Values); 1524 } 1525 1526 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1527 return llvm::makeArrayRef(GCCRegNames); 1528 } 1529 1530 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1531 return llvm::makeArrayRef(AddlRegNames); 1532 } 1533 1534 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1535 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1536 Builtin::FirstTSBuiltin + 1); 1537 } 1538 1539 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1540 return llvm::makeArrayRef(BuiltinInfoX86, 1541 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1542 } 1543